From: Simon Glass Date: Sat, 12 Mar 2016 05:07:00 +0000 (-0700) Subject: x86: Move Intel Management Engine code to a common place X-Git-Tag: v2016.05-rc1~291 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8b900a417527d9ad94dc4aab2c9d6717bdc50b33;p=u-boot x86: Move Intel Management Engine code to a common place Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng --- diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 06de964cc8..1918ca30a8 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_HAVE_MRC) += car.o obj-y += cpu.o obj-y += lpc.o +obj-$(CONFIG_HAVE_MRC) += me_status.o ifndef CONFIG_TARGET_EFI obj-y += microcode.o endif +obj-$(CONFIG_HAVE_MRC) += report_platform.o diff --git a/arch/x86/cpu/intel_common/me_status.c b/arch/x86/cpu/intel_common/me_status.c new file mode 100644 index 0000000000..130d219bc9 --- /dev/null +++ b/arch/x86/cpu/intel_common/me_status.c @@ -0,0 +1,213 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me_status.c + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +/* HFS1[3:0] Current Working State Values */ +static const char *const me_cws_values[] = { + [ME_HFS_CWS_RESET] = "Reset", + [ME_HFS_CWS_INIT] = "Initializing", + [ME_HFS_CWS_REC] = "Recovery", + [ME_HFS_CWS_NORMAL] = "Normal", + [ME_HFS_CWS_WAIT] = "Platform Disable Wait", + [ME_HFS_CWS_TRANS] = "OP State Transition", + [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" +}; + +/* HFS1[8:6] Current Operation State Values */ +static const char *const me_opstate_values[] = { + [ME_HFS_STATE_PREBOOT] = "Preboot", + [ME_HFS_STATE_M0_UMA] = "M0 with UMA", + [ME_HFS_STATE_M3] = "M3 without UMA", + [ME_HFS_STATE_M0] = "M0 without UMA", + [ME_HFS_STATE_BRINGUP] = "Bring up", + [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" +}; + +/* HFS[19:16] Current Operation Mode Values */ +static const char *const me_opmode_values[] = { + [ME_HFS_MODE_NORMAL] = "Normal", + [ME_HFS_MODE_DEBUG] = "Debug", + [ME_HFS_MODE_DIS] = "Soft Temporary Disable", + [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", + [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" +}; + +/* HFS[15:12] Error Code Values */ +static const char *const me_error_values[] = { + [ME_HFS_ERROR_NONE] = "No Error", + [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", + [ME_HFS_ERROR_IMAGE] = "Image Failure", + [ME_HFS_ERROR_DEBUG] = "Debug Failure" +}; + +/* GMES[31:28] ME Progress Code */ +static const char *const me_progress_values[] = { + [ME_GMES_PHASE_ROM] = "ROM Phase", + [ME_GMES_PHASE_BUP] = "BUP Phase", + [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", + [ME_GMES_PHASE_POLICY] = "Policy Module", + [ME_GMES_PHASE_MODULE] = "Module Loading", + [ME_GMES_PHASE_UNKNOWN] = "Unknown", + [ME_GMES_PHASE_HOST] = "Host Communication" +}; + +/* GMES[27:24] Power Management Event */ +static const char *const me_pmevent_values[] = { + [0x00] = "Clean Moff->Mx wake", + [0x01] = "Moff->Mx wake after an error", + [0x02] = "Clean global reset", + [0x03] = "Global reset after an error", + [0x04] = "Clean Intel ME reset", + [0x05] = "Intel ME reset due to exception", + [0x06] = "Pseudo-global reset", + [0x07] = "S0/M0->Sx/M3", + [0x08] = "Sx/M3->S0/M0", + [0x09] = "Non-power cycle reset", + [0x0a] = "Power cycle reset through M3", + [0x0b] = "Power cycle reset through Moff", + [0x0c] = "Sx/Mx->Sx/Moff" +}; + +/* Progress Code 0 states */ +static const char *const me_progress_rom_values[] = { + [0x00] = "BEGIN", + [0x06] = "DISABLE" +}; + +/* Progress Code 1 states */ +static const char *const me_progress_bup_values[] = { + [0x00] = "Initialization starts", + [0x01] = "Disable the host wake event", + [0x04] = "Flow determination start process", + [0x08] = "Error reading/matching the VSCC table in the descriptor", + [0x0a] = "Check to see if straps say ME DISABLED", + [0x0b] = "Timeout waiting for PWROK", + [0x0d] = "Possibly handle BUP manufacturing override strap", + [0x11] = "Bringup in M3", + [0x12] = "Bringup in M0", + [0x13] = "Flow detection error", + [0x15] = "M3 clock switching error", + [0x18] = "M3 kernel load", + [0x1c] = "T34 missing - cannot program ICC", + [0x1f] = "Waiting for DID BIOS message", + [0x20] = "Waiting for DID BIOS message failure", + [0x21] = "DID reported an error", + [0x22] = "Enabling UMA", + [0x23] = "Enabling UMA error", + [0x24] = "Sending DID Ack to BIOS", + [0x25] = "Sending DID Ack to BIOS error", + [0x26] = "Switching clocks in M0", + [0x27] = "Switching clocks in M0 error", + [0x28] = "ME in temp disable", + [0x32] = "M0 kernel load", +}; + +/* Progress Code 3 states */ +static const char *const me_progress_policy_values[] = { + [0x00] = "Entery into Policy Module", + [0x03] = "Received S3 entry", + [0x04] = "Received S4 entry", + [0x05] = "Received S5 entry", + [0x06] = "Received UPD entry", + [0x07] = "Received PCR entry", + [0x08] = "Received NPCR entry", + [0x09] = "Received host wake", + [0x0a] = "Received AC<>DC switch", + [0x0b] = "Received DRAM Init Done", + [0x0c] = "VSCC Data not found for flash device", + [0x0d] = "VSCC Table is not valid", + [0x0e] = "Flash Partition Boundary is outside address space", + [0x0f] = "ME cannot access the chipset descriptor region", + [0x10] = "Required VSCC values for flash parts do not match", +}; + + +/** + * _intel_me_status() - Check Intel Management Engine status + * + * struct hfs: Firmware status + * struct gmes: Management engine status + */ +static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) +{ + /* Check Current States */ + debug("ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); + debug("ME: Bringup Loader Failure : %s\n", + hfs->ft_bup_ld_flr ? "YES" : "NO"); + debug("ME: Firmware Init Complete : %s\n", + hfs->fw_init_complete ? "YES" : "NO"); + debug("ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + debug("ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + debug("ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + debug("ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); + debug("ME: Current Operation State : %s\n", + me_opstate_values[hfs->operation_state]); + debug("ME: Current Operation Mode : %s\n", + me_opmode_values[hfs->operation_mode]); + debug("ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + debug("ME: Progress Phase : %s\n", + me_progress_values[gmes->progress_code]); + debug("ME: Power Management Event : %s\n", + me_pmevent_values[gmes->current_pmevent]); + + debug("ME: Progress Phase State : "); + switch (gmes->progress_code) { + case ME_GMES_PHASE_ROM: /* ROM Phase */ + debug("%s", me_progress_rom_values[gmes->current_state]); + break; + + case ME_GMES_PHASE_BUP: /* Bringup Phase */ + if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && + me_progress_bup_values[gmes->current_state]) + debug("%s", + me_progress_bup_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ + if (gmes->current_state < + ARRAY_SIZE(me_progress_policy_values) && + me_progress_policy_values[gmes->current_state]) + debug("%s", + me_progress_policy_values[gmes->current_state]); + else + debug("0x%02x", gmes->current_state); + break; + + case ME_GMES_PHASE_HOST: /* Host Communication Phase */ + if (!gmes->current_state) + debug("Host communication established"); + else + debug("0x%02x", gmes->current_state); + break; + + default: + debug("Unknown 0x%02x", gmes->current_state); + } + debug("\n"); +} + +void intel_me_status(struct udevice *me_dev) +{ + struct me_hfs hfs; + struct me_gmes gmes; + + pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); + pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES); + + _intel_me_status(&hfs, &gmes); +} diff --git a/arch/x86/cpu/intel_common/report_platform.c b/arch/x86/cpu/intel_common/report_platform.c new file mode 100644 index 0000000000..05e1cf9cdb --- /dev/null +++ b/arch/x86/cpu/intel_common/report_platform.c @@ -0,0 +1,90 @@ +/* + * From Coreboot src/northbridge/intel/sandybridge/report_platform.c + * + * Copyright (C) 2012 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +static void report_cpu_info(void) +{ + char cpu_string[CPU_MAX_NAME_LEN], *cpu_name; + const char *mode[] = {"NOT ", ""}; + struct cpuid_result cpuidr; + int vt, txt, aes; + u32 index; + + index = 0x80000000; + cpuidr = cpuid(index); + if (cpuidr.eax < 0x80000004) { + strcpy(cpu_string, "Platform info not available"); + cpu_name = cpu_string; + } else { + cpu_name = cpu_get_name(cpu_string); + } + + cpuidr = cpuid(1); + debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + debug("AES %ssupported, TXT %ssupported, VT %ssupported\n", + mode[aes], mode[txt], mode[vt]); +} + +/* The PCI id name match comes from Intel document 472178 */ +static struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(struct udevice *dev) +{ + const char *pch_type = "Unknown"; + int i; + u16 dev_id; + uint8_t rev_id; + + dm_pci_read_config16(dev, 2, &dev_id); + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + dm_pci_read_config8(dev, 8, &rev_id); + debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, + rev_id); +} + +void report_platform_info(struct udevice *dev) +{ + report_cpu_info(); + report_pch_info(dev); +} diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 78006f12b3..9cdb07bdf2 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -11,10 +11,8 @@ obj-y += cpu.o obj-y += early_me.o obj-y += gma.o obj-y += lpc.o -obj-y += me_status.o obj-y += model_206ax.o obj-y += northbridge.o -obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o endif diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index b1df77d571..cda96ab398 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -27,35 +27,6 @@ static const char *const me_ack_values[] = { [ME_HFS_ACK_CONTINUE] = "Continue to boot" }; -static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr, - int offset) -{ - u32 dword; - - dm_pci_read_config32(me_dev, offset, &dword); - memcpy(ptr, &dword, sizeof(dword)); -} - -static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr, - int offset) -{ - u32 dword = 0; - - memcpy(&dword, ptr, sizeof(dword)); - dm_pci_write_config32(me_dev, offset, dword); -} - -void intel_early_me_status(struct udevice *me_dev) -{ - struct me_hfs hfs; - struct me_gmes gmes; - - pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); - pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES); - - intel_me_status(&hfs, &gmes); -} - int intel_early_me_init(struct udevice *me_dev) { int count; @@ -159,7 +130,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]); /* Check status after acknowledgement */ - intel_early_me_status(me_dev); + intel_me_status(me_dev); switch (hfs.ack_data) { case ME_HFS_ACK_CONTINUE: diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c deleted file mode 100644 index 15cf69f40e..0000000000 --- a/arch/x86/cpu/ivybridge/me_status.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * From Coreboot src/southbridge/intel/bd82x6x/me_status.c - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -/* HFS1[3:0] Current Working State Values */ -static const char *const me_cws_values[] = { - [ME_HFS_CWS_RESET] = "Reset", - [ME_HFS_CWS_INIT] = "Initializing", - [ME_HFS_CWS_REC] = "Recovery", - [ME_HFS_CWS_NORMAL] = "Normal", - [ME_HFS_CWS_WAIT] = "Platform Disable Wait", - [ME_HFS_CWS_TRANS] = "OP State Transition", - [ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In" -}; - -/* HFS1[8:6] Current Operation State Values */ -static const char *const me_opstate_values[] = { - [ME_HFS_STATE_PREBOOT] = "Preboot", - [ME_HFS_STATE_M0_UMA] = "M0 with UMA", - [ME_HFS_STATE_M3] = "M3 without UMA", - [ME_HFS_STATE_M0] = "M0 without UMA", - [ME_HFS_STATE_BRINGUP] = "Bring up", - [ME_HFS_STATE_ERROR] = "M0 without UMA but with error" -}; - -/* HFS[19:16] Current Operation Mode Values */ -static const char *const me_opmode_values[] = { - [ME_HFS_MODE_NORMAL] = "Normal", - [ME_HFS_MODE_DEBUG] = "Debug", - [ME_HFS_MODE_DIS] = "Soft Temporary Disable", - [ME_HFS_MODE_OVER_JMPR] = "Security Override via Jumper", - [ME_HFS_MODE_OVER_MEI] = "Security Override via MEI Message" -}; - -/* HFS[15:12] Error Code Values */ -static const char *const me_error_values[] = { - [ME_HFS_ERROR_NONE] = "No Error", - [ME_HFS_ERROR_UNCAT] = "Uncategorized Failure", - [ME_HFS_ERROR_IMAGE] = "Image Failure", - [ME_HFS_ERROR_DEBUG] = "Debug Failure" -}; - -/* GMES[31:28] ME Progress Code */ -static const char *const me_progress_values[] = { - [ME_GMES_PHASE_ROM] = "ROM Phase", - [ME_GMES_PHASE_BUP] = "BUP Phase", - [ME_GMES_PHASE_UKERNEL] = "uKernel Phase", - [ME_GMES_PHASE_POLICY] = "Policy Module", - [ME_GMES_PHASE_MODULE] = "Module Loading", - [ME_GMES_PHASE_UNKNOWN] = "Unknown", - [ME_GMES_PHASE_HOST] = "Host Communication" -}; - -/* GMES[27:24] Power Management Event */ -static const char *const me_pmevent_values[] = { - [0x00] = "Clean Moff->Mx wake", - [0x01] = "Moff->Mx wake after an error", - [0x02] = "Clean global reset", - [0x03] = "Global reset after an error", - [0x04] = "Clean Intel ME reset", - [0x05] = "Intel ME reset due to exception", - [0x06] = "Pseudo-global reset", - [0x07] = "S0/M0->Sx/M3", - [0x08] = "Sx/M3->S0/M0", - [0x09] = "Non-power cycle reset", - [0x0a] = "Power cycle reset through M3", - [0x0b] = "Power cycle reset through Moff", - [0x0c] = "Sx/Mx->Sx/Moff" -}; - -/* Progress Code 0 states */ -static const char *const me_progress_rom_values[] = { - [0x00] = "BEGIN", - [0x06] = "DISABLE" -}; - -/* Progress Code 1 states */ -static const char *const me_progress_bup_values[] = { - [0x00] = "Initialization starts", - [0x01] = "Disable the host wake event", - [0x04] = "Flow determination start process", - [0x08] = "Error reading/matching the VSCC table in the descriptor", - [0x0a] = "Check to see if straps say ME DISABLED", - [0x0b] = "Timeout waiting for PWROK", - [0x0d] = "Possibly handle BUP manufacturing override strap", - [0x11] = "Bringup in M3", - [0x12] = "Bringup in M0", - [0x13] = "Flow detection error", - [0x15] = "M3 clock switching error", - [0x18] = "M3 kernel load", - [0x1c] = "T34 missing - cannot program ICC", - [0x1f] = "Waiting for DID BIOS message", - [0x20] = "Waiting for DID BIOS message failure", - [0x21] = "DID reported an error", - [0x22] = "Enabling UMA", - [0x23] = "Enabling UMA error", - [0x24] = "Sending DID Ack to BIOS", - [0x25] = "Sending DID Ack to BIOS error", - [0x26] = "Switching clocks in M0", - [0x27] = "Switching clocks in M0 error", - [0x28] = "ME in temp disable", - [0x32] = "M0 kernel load", -}; - -/* Progress Code 3 states */ -static const char *const me_progress_policy_values[] = { - [0x00] = "Entery into Policy Module", - [0x03] = "Received S3 entry", - [0x04] = "Received S4 entry", - [0x05] = "Received S5 entry", - [0x06] = "Received UPD entry", - [0x07] = "Received PCR entry", - [0x08] = "Received NPCR entry", - [0x09] = "Received host wake", - [0x0a] = "Received AC<>DC switch", - [0x0b] = "Received DRAM Init Done", - [0x0c] = "VSCC Data not found for flash device", - [0x0d] = "VSCC Table is not valid", - [0x0e] = "Flash Partition Boundary is outside address space", - [0x0f] = "ME cannot access the chipset descriptor region", - [0x10] = "Required VSCC values for flash parts do not match", -}; - -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) -{ - /* Check Current States */ - debug("ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); - debug("ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); - debug("ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - debug("ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - debug("ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - debug("ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - debug("ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); - debug("ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); - debug("ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - debug("ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - debug("ME: Progress Phase : %s\n", - me_progress_values[gmes->progress_code]); - debug("ME: Power Management Event : %s\n", - me_pmevent_values[gmes->current_pmevent]); - - debug("ME: Progress Phase State : "); - switch (gmes->progress_code) { - case ME_GMES_PHASE_ROM: /* ROM Phase */ - debug("%s", me_progress_rom_values[gmes->current_state]); - break; - - case ME_GMES_PHASE_BUP: /* Bringup Phase */ - if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && - me_progress_bup_values[gmes->current_state]) - debug("%s", - me_progress_bup_values[gmes->current_state]); - else - debug("0x%02x", gmes->current_state); - break; - - case ME_GMES_PHASE_POLICY: /* Policy Module Phase */ - if (gmes->current_state < - ARRAY_SIZE(me_progress_policy_values) && - me_progress_policy_values[gmes->current_state]) - debug("%s", - me_progress_policy_values[gmes->current_state]); - else - debug("0x%02x", gmes->current_state); - break; - - case ME_GMES_PHASE_HOST: /* Host Communication Phase */ - if (!gmes->current_state) - debug("Host communication established"); - else - debug("0x%02x", gmes->current_state); - break; - - default: - debug("Unknown 0x%02x", gmes->current_state); - } - debug("\n"); -} diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c deleted file mode 100644 index c78322aef9..0000000000 --- a/arch/x86/cpu/ivybridge/report_platform.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * From Coreboot src/northbridge/intel/sandybridge/report_platform.c - * - * Copyright (C) 2012 Google Inc. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include -#include -#include -#include - -static void report_cpu_info(void) -{ - char cpu_string[CPU_MAX_NAME_LEN], *cpu_name; - const char *mode[] = {"NOT ", ""}; - struct cpuid_result cpuidr; - int vt, txt, aes; - u32 index; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - cpu_name = cpu_string; - } else { - cpu_name = cpu_get_name(cpu_string); - } - - cpuidr = cpuid(1); - debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - debug("AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - -/* The PCI id name match comes from Intel document 472178 */ -static struct { - u16 dev_id; - const char *dev_name; -} pch_table[] = { - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, -}; - -static void report_pch_info(struct udevice *dev) -{ - const char *pch_type = "Unknown"; - int i; - u16 dev_id; - uint8_t rev_id; - - dm_pci_read_config16(dev, 2, &dev_id); - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].dev_id == dev_id) { - pch_type = pch_table[i].dev_name; - break; - } - } - dm_pci_read_config8(dev, 8, &rev_id); - debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, - rev_id); -} - -void report_platform_info(struct udevice *dev) -{ - report_cpu_info(); - report_pch_info(dev); -} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index f7dd61f045..e0296a24b3 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -384,7 +385,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev, if (BASE_REV_SNB == done) intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS); else - intel_early_me_status(me_dev); + intel_me_status(me_dev); post_system_agent_init(pei_data); report_memory_config(); diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h index eb1b73f92e..bc1bc8e778 100644 --- a/arch/x86/include/asm/arch-ivybridge/me.h +++ b/arch/x86/include/asm/arch-ivybridge/me.h @@ -9,225 +9,7 @@ #ifndef _ASM_INTEL_ME_H #define _ASM_INTEL_ME_H -#include -#include - -#define ME_RETRY 100000 /* 1 second */ -#define ME_DELAY 10 /* 10 us */ - -/* - * Management Engine PCI registers - */ - -#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ -#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ - -#define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 - -struct me_hfs { - u32 working_state:4; - u32 mfg_mode:1; - u32 fpt_bad:1; - u32 operation_state:3; - u32 fw_init_complete:1; - u32 ft_bup_ld_flr:1; - u32 update_in_progress:1; - u32 error_code:4; - u32 operation_mode:4; - u32 reserved:4; - u32 boot_options_present:1; - u32 ack_data:3; - u32 bios_msg_ack:4; -} __packed; - -#define PCI_ME_UMA 0x44 - -struct me_uma { - u32 size:6; - u32 reserved_1:10; - u32 valid:1; - u32 reserved_0:14; - u32 set_to_one:1; -} __packed; - -#define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 - -struct me_did { - u32 uma_base:16; - u32 reserved:8; - u32 status:4; - u32 init_done:4; -} __packed; - -#define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 - -struct me_gmes { - u32 bist_in_prog:1; - u32 icc_prog_sts:2; - u32 invoke_mebx:1; - u32 cpu_replaced_sts:1; - u32 mbp_rdy:1; - u32 mfs_failure:1; - u32 warm_rst_req_for_df:1; - u32 cpu_replaced_valid:1; - u32 reserved_1:2; - u32 fw_upd_ipu:1; - u32 reserved_2:4; - u32 current_state:8; - u32 current_pmevent:4; - u32 progress_code:4; -} __packed; - -#define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 -#define PCI_ME_HER(x) (0xc0+(4*(x))) - -struct me_heres { - u32 extend_reg_algorithm:4; - u32 reserved:26; - u32 extend_feature_present:1; - u32 extend_reg_valid:1; -} __packed; - -/* - * Management Engine MEI registers - */ - -#define MEI_H_CB_WW 0x00 -#define MEI_H_CSR 0x04 -#define MEI_ME_CB_RW 0x08 -#define MEI_ME_CSR_HA 0x0c - -struct mei_csr { - u32 interrupt_enable:1; - u32 interrupt_status:1; - u32 interrupt_generate:1; - u32 ready:1; - u32 reset:1; - u32 reserved:3; - u32 buffer_read_ptr:8; - u32 buffer_write_ptr:8; - u32 buffer_depth:8; -} __packed; - -#define MEI_ADDRESS_CORE 0x01 -#define MEI_ADDRESS_AMT 0x02 -#define MEI_ADDRESS_RESERVED 0x03 -#define MEI_ADDRESS_WDT 0x04 -#define MEI_ADDRESS_MKHI 0x07 -#define MEI_ADDRESS_ICC 0x08 -#define MEI_ADDRESS_THERMAL 0x09 - -#define MEI_HOST_ADDRESS 0 - -struct mei_header { - u32 client_address:8; - u32 host_address:8; - u32 length:9; - u32 reserved:6; - u32 is_complete:1; -} __packed; - -#define MKHI_GROUP_ID_CBM 0x00 -#define MKHI_GROUP_ID_FWCAPS 0x03 -#define MKHI_GROUP_ID_MDES 0x08 -#define MKHI_GROUP_ID_GEN 0xff - -#define MKHI_GLOBAL_RESET 0x0b - -#define MKHI_FWCAPS_GET_RULE 0x02 - -#define MKHI_MDES_ENABLE 0x09 - -#define MKHI_GET_FW_VERSION 0x02 -#define MKHI_END_OF_POST 0x0c -#define MKHI_FEATURE_OVERRIDE 0x14 - -struct mkhi_header { - u32 group_id:8; - u32 command:7; - u32 is_response:1; - u32 reserved:8; - u32 result:8; -} __packed; - -struct me_fw_version { - u16 code_minor; - u16 code_major; - u16 code_build_number; - u16 code_hot_fix; - u16 recovery_minor; - u16 recovery_major; - u16 recovery_build_number; - u16 recovery_hot_fix; -} __packed; - - -#define HECI_EOP_STATUS_SUCCESS 0x0 -#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 - -#define CBM_RR_GLOBAL_RESET 0x01 - -#define GLOBAL_RESET_BIOS_MRC 0x01 -#define GLOBAL_RESET_BIOS_POST 0x02 -#define GLOBAL_RESET_MEBX 0x03 - -struct me_global_reset { - u8 request_origin; - u8 reset_type; -} __packed; - -enum me_bios_path { - ME_NORMAL_BIOS_PATH, - ME_S3WAKE_BIOS_PATH, - ME_ERROR_BIOS_PATH, - ME_RECOVERY_BIOS_PATH, - ME_DISABLE_BIOS_PATH, - ME_FIRMWARE_UPDATE_BIOS_PATH, -}; +#include struct __packed mbp_fw_version_name { u32 major_version:16; @@ -244,46 +26,6 @@ struct __packed mbp_icc_profile { u32 register_lock_mask[3]; }; -struct __packed mefwcaps_sku { - u32 full_net:1; - u32 std_net:1; - u32 manageability:1; - u32 small_business:1; - u32 l3manageability:1; - u32 intel_at:1; - u32 intel_cls:1; - u32 reserved:3; - u32 intel_mpc:1; - u32 icc_over_clocking:1; - u32 pavp:1; - u32 reserved_1:4; - u32 ipv6:1; - u32 kvm:1; - u32 och:1; - u32 vlan:1; - u32 tls:1; - u32 reserved_4:1; - u32 wlan:1; - u32 reserved_5:8; -}; - -struct __packed tdt_state_flag { - u16 lock_state:1; - u16 authenticate_module:1; - u16 s3authentication:1; - u16 flash_wear_out:1; - u16 flash_variable_security:1; - u16 wwan3gpresent:1; - u16 wwan3goob:1; - u16 reserved:9; -}; - -struct __packed tdt_state_info { - u8 state; - u8 last_theft_trigger; - struct tdt_state_flag flags; -}; - struct __packed platform_type_rule_data { u32 platform_target_usage_type:4; u32 platform_target_market_type:2; @@ -299,16 +41,6 @@ struct __packed mbp_fw_caps { u8 available; }; -struct __packed mbp_rom_bist_data { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; -}; - -struct __packed mbp_platform_key { - u32 key[8]; -}; - struct __packed mbp_plat_type { struct platform_type_rule_data rule_data; u8 available; @@ -325,67 +57,4 @@ struct __packed me_bios_payload { u32 mfsintegrity; }; -struct __packed mbp_header { - u32 mbp_size:8; - u32 num_entries:8; - u32 rsvd:16; -}; - -struct __packed mbp_item_header { - u32 app_id:8; - u32 item_id:8; - u32 length:8; - u32 rsvd:8; -}; - -struct __packed me_fwcaps { - u32 id; - u8 length; - struct mefwcaps_sku caps_sku; - u8 reserved[3]; -}; - -/** - * intel_me_status() - Check Intel Management Engine status - * - * struct hfs: Firmware status - * struct gmes: Management engine status - */ -void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); - -/** - * intel_early_me_status() - Check early Management Engine Status - * - * @me_dev: Management engine PCI device - */ -void intel_early_me_status(struct udevice *me_dev); - -/** - * intel_early_me_init() - Early Intel Management Engine init - * - * @me_dev: Management engine PCI device - * @return 0 if OK, -ve on error - */ -int intel_early_me_init(struct udevice *me_dev); - -/** - * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine - * - * @me_dev: Management engine PCI device - * @return UMA size if OK, -EINVAL on error - */ -int intel_early_me_uma_size(struct udevice *me_dev); - -/** - * intel_early_me_init_done() - Complete Intel Management Engine init - * - * @dev: Northbridge device - * @me_dev: Management engine PCI device - * @status: Status result (ME_INIT_...) - * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT - * if ME did not respond - */ -int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, - uint status); - #endif diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h index 59b05cc72e..c395d53371 100644 --- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h +++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h @@ -113,8 +113,6 @@ */ int bridge_silicon_revision(struct udevice *dev); -void report_platform_info(struct udevice *dev); - void sandybridge_early_init(int chipset_type); #endif diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h new file mode 100644 index 0000000000..2e2251cc1c --- /dev/null +++ b/arch/x86/include/asm/me_common.h @@ -0,0 +1,373 @@ +/* + * From Coreboot src/southbridge/intel/bd82x6x/me.h + * + * Coreboot copies lots of code around. Here we are trying to keep the common + * code in a separate file to reduce code duplication and hopefully make it + * easier to add new platform. + * + * Copyright (C) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ME_COMMON_H +#define __ASM_ME_COMMON_H + +#include +#include +#include + +#define MCHBAR_PEI_VERSION 0x5034 + +#define ME_RETRY 100000 /* 1 second */ +#define ME_DELAY 10 /* 10 us */ + +/* + * Management Engine PCI registers + */ + +#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ +#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ + +#define PCI_ME_HFS 0x40 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 + +struct me_hfs { + u32 working_state:4; + u32 mfg_mode:1; + u32 fpt_bad:1; + u32 operation_state:3; + u32 fw_init_complete:1; + u32 ft_bup_ld_flr:1; + u32 update_in_progress:1; + u32 error_code:4; + u32 operation_mode:4; + u32 reserved:4; + u32 boot_options_present:1; + u32 ack_data:3; + u32 bios_msg_ack:4; +} __packed; + +#define PCI_ME_UMA 0x44 + +struct me_uma { + u32 size:6; + u32 reserved_1:10; + u32 valid:1; + u32 reserved_0:14; + u32 set_to_one:1; +} __packed; + +#define PCI_ME_H_GS 0x4c +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 + +struct me_did { + u32 uma_base:16; + u32 reserved:7; + u32 rapid_start:1; /* Broadwell only */ + u32 status:4; + u32 init_done:4; +} __packed; + +#define PCI_ME_GMES 0x48 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 + +struct me_gmes { + u32 bist_in_prog:1; + u32 icc_prog_sts:2; + u32 invoke_mebx:1; + u32 cpu_replaced_sts:1; + u32 mbp_rdy:1; + u32 mfs_failure:1; + u32 warm_rst_req_for_df:1; + u32 cpu_replaced_valid:1; + u32 reserved_1:2; + u32 fw_upd_ipu:1; + u32 reserved_2:4; + u32 current_state:8; + u32 current_pmevent:4; + u32 progress_code:4; +} __packed; + +#define PCI_ME_HERES 0xbc +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_HER(x) (0xc0+(4*(x))) + +struct me_heres { + u32 extend_reg_algorithm:4; + u32 reserved:26; + u32 extend_feature_present:1; + u32 extend_reg_valid:1; +} __packed; + +/* + * Management Engine MEI registers + */ + +#define MEI_H_CB_WW 0x00 +#define MEI_H_CSR 0x04 +#define MEI_ME_CB_RW 0x08 +#define MEI_ME_CSR_HA 0x0c + +struct mei_csr { + u32 interrupt_enable:1; + u32 interrupt_status:1; + u32 interrupt_generate:1; + u32 ready:1; + u32 reset:1; + u32 reserved:3; + u32 buffer_read_ptr:8; + u32 buffer_write_ptr:8; + u32 buffer_depth:8; +} __packed; + +#define MEI_ADDRESS_CORE 0x01 +#define MEI_ADDRESS_AMT 0x02 +#define MEI_ADDRESS_RESERVED 0x03 +#define MEI_ADDRESS_WDT 0x04 +#define MEI_ADDRESS_MKHI 0x07 +#define MEI_ADDRESS_ICC 0x08 +#define MEI_ADDRESS_THERMAL 0x09 + +#define MEI_HOST_ADDRESS 0 + +struct mei_header { + u32 client_address:8; + u32 host_address:8; + u32 length:9; + u32 reserved:6; + u32 is_complete:1; +} __packed; + +#define MKHI_GROUP_ID_CBM 0x00 +#define MKHI_GROUP_ID_FWCAPS 0x03 +#define MKHI_GROUP_ID_MDES 0x08 +#define MKHI_GROUP_ID_GEN 0xff + +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_END_OF_POST 0x0c +#define MKHI_FEATURE_OVERRIDE 0x14 + +/* Ivybridge only: */ +#define MKHI_GLOBAL_RESET 0x0b +#define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_MDES_ENABLE 0x09 + +/* Broadwell only: */ +#define MKHI_GLOBAL_RESET 0x0b +#define MKHI_FWCAPS_GET_RULE 0x02 +#define MKHI_GROUP_ID_HMRFPO 0x05 +#define MKHI_HMRFPO_LOCK 0x02 +#define MKHI_HMRFPO_LOCK_NOACK 0x05 +#define MKHI_MDES_ENABLE 0x09 +#define MKHI_END_OF_POST_NOACK 0x1a + +struct mkhi_header { + u32 group_id:8; + u32 command:7; + u32 is_response:1; + u32 reserved:8; + u32 result:8; +} __packed; + +struct me_fw_version { + u16 code_minor; + u16 code_major; + u16 code_build_number; + u16 code_hot_fix; + u16 recovery_minor; + u16 recovery_major; + u16 recovery_build_number; + u16 recovery_hot_fix; +} __packed; + + +#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 + +#define CBM_RR_GLOBAL_RESET 0x01 + +#define GLOBAL_RESET_BIOS_MRC 0x01 +#define GLOBAL_RESET_BIOS_POST 0x02 +#define GLOBAL_RESET_MEBX 0x03 + +struct me_global_reset { + u8 request_origin; + u8 reset_type; +} __packed; + +enum me_bios_path { + ME_NORMAL_BIOS_PATH, + ME_S3WAKE_BIOS_PATH, + ME_ERROR_BIOS_PATH, + ME_RECOVERY_BIOS_PATH, + ME_DISABLE_BIOS_PATH, + ME_FIRMWARE_UPDATE_BIOS_PATH, +}; + +struct __packed mefwcaps_sku { + u32 full_net:1; + u32 std_net:1; + u32 manageability:1; + u32 small_business:1; + u32 l3manageability:1; + u32 intel_at:1; + u32 intel_cls:1; + u32 reserved:3; + u32 intel_mpc:1; + u32 icc_over_clocking:1; + u32 pavp:1; + u32 reserved_1:4; + u32 ipv6:1; + u32 kvm:1; + u32 och:1; + u32 vlan:1; + u32 tls:1; + u32 reserved_4:1; + u32 wlan:1; + u32 reserved_5:8; +}; + +struct __packed tdt_state_flag { + u16 lock_state:1; + u16 authenticate_module:1; + u16 s3authentication:1; + u16 flash_wear_out:1; + u16 flash_variable_security:1; + u16 wwan3gpresent:1; /* ivybridge only */ + u16 wwan3goob:1; /* ivybridge only */ + u16 reserved:9; +}; + +struct __packed tdt_state_info { + u8 state; + u8 last_theft_trigger; + struct tdt_state_flag flags; +}; + +struct __packed mbp_rom_bist_data { + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; +}; + +struct __packed mbp_platform_key { + u32 key[8]; +}; + +struct __packed mbp_header { + u32 mbp_size:8; + u32 num_entries:8; + u32 rsvd:16; +}; + +struct __packed mbp_item_header { + u32 app_id:8; + u32 item_id:8; + u32 length:8; + u32 rsvd:8; +}; + +struct __packed me_fwcaps { + u32 id; + u8 length; + struct mefwcaps_sku caps_sku; + u8 reserved[3]; +}; + +/** + * intel_me_status() - Check Intel Management Engine status + * + * @me_dev: Management engine PCI device + */ +void intel_me_status(struct udevice *me_dev); + +/** + * intel_early_me_init() - Early Intel Management Engine init + * + * @me_dev: Management engine PCI device + * @return 0 if OK, -ve on error + */ +int intel_early_me_init(struct udevice *me_dev); + +/** + * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine + * + * @me_dev: Management engine PCI device + * @return UMA size if OK, -EINVAL on error + */ +int intel_early_me_uma_size(struct udevice *me_dev); + +/** + * intel_early_me_init_done() - Complete Intel Management Engine init + * + * @dev: Northbridge device + * @me_dev: Management engine PCI device + * @status: Status result (ME_INIT_...) + * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT + * if ME did not respond + */ +int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, + uint status); + +int intel_me_hsio_version(struct udevice *dev, uint16_t *version, + uint16_t *checksum); + +static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr, + int offset) +{ + u32 dword; + + dm_pci_read_config32(me_dev, offset, &dword); + memcpy(ptr, &dword, sizeof(dword)); +} + +static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr, + int offset) +{ + u32 dword = 0; + + memcpy(&dword, ptr, sizeof(dword)); + dm_pci_write_config32(me_dev, offset, dword); +} +#endif diff --git a/arch/x86/include/asm/report_platform.h b/arch/x86/include/asm/report_platform.h new file mode 100644 index 0000000000..4607dd334e --- /dev/null +++ b/arch/x86/include/asm/report_platform.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ARCH_REPORT_PLATFORM_H +#define __ARCH_REPORT_PLATFORM_H + +/** + * report_platform_info() - Report platform information + * + * This reports information about the CPU and chipset. + * + * @dev: Northbridge device + */ +void report_platform_info(struct udevice *dev); + +#endif