From: Andreas Fritiofson Date: Thu, 3 Jul 2014 17:33:45 +0000 (+0200) Subject: tcl: Add default hooks for STM32F3x X-Git-Tag: v0.9.0-rc1~80 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8d80a25410bb76670c7fcf780b624212bd769e47;p=openocd tcl: Add default hooks for STM32F3x Keep clocks running in low power modes. Stop watchdogs from interfering with the debug session. Set up PLL and increase clock at reset init. Change-Id: I984d2018f7d47a1042f1e12894563154fa7b566c Signed-off-by: Andreas Fritiofson Reviewed-on: http://openocd.zylin.com/2196 Tested-by: jenkins Reviewed-by: Uwe Bonnes Reviewed-by: Paul Fertser --- diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index 472cbc9b..7ddf7d04 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -4,6 +4,7 @@ # stm32 devices support both JTAG and SWD transports. # source [find target/swj-dp.tcl] +source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -87,3 +88,33 @@ if {![using_hla]} { # perform a soft reset cortex_m reset_config sysresetreq } + +proc stm32f3x_default_reset_start {} { + # Reset clock is HSI (8 MHz) + adapter_khz 1000 +} + +proc stm32f3x_default_examine_end {} { + # Enable debug during low power modes (uses more power) + mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + + # Stop watchdog counters during halt + mww 0xe0042008 0x00001800 ;# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP +} + +proc stm32f3x_default_reset_init {} { + # Configure PLL to boost clock to HSI x 8 (64 MHz) + mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] + mwh 0x40021002 0x0100 ;# RCC_CR[31:16] = PLLON + mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] + sleep 10 ;# Wait for PLL to lock + mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1] + + # Boost JTAG frequency + adapter_khz 8000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }