From: Dinh Nguyen Date: Thu, 15 Oct 2015 15:13:36 +0000 (-0500) Subject: arm: socfpga: enable data/inst prefetch and shared override in the L2 X-Git-Tag: v2015.10~21^2~1 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8d8e13e129f20ef82a271094eb713d513e83adf4;p=u-boot arm: socfpga: enable data/inst prefetch and shared override in the L2 Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen --- diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index de7650eae7..d588f94350 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -17,6 +17,8 @@ #define L2X0_CTRL_EN 1 #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) +#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) +#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) struct pl310_regs { u32 pl310_cache_id; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 0940cc5a4f..bbd31ef7b5 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -52,6 +52,18 @@ void enable_caches(void) #endif } +void v7_outer_cache_enable(void) +{ + /* disable the L2 cache */ + writel(0, &pl310->pl310_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); +} + /* * DesignWare Ethernet initialization */