From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Date: Thu, 2 Mar 2017 09:10:51 +0000 (+0530)
Subject: arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3
X-Git-Tag: v2018.01-rc1~59^2~30
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8e5a4e6f0ec7d475fc32b7f8083c9aefb9723fad;p=u-boot

arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3

This patch adds support for reading silicon revision using zynqmp nvmem
driver.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 10a53bb9f0..dce5da4e06 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -1022,6 +1022,8 @@
 			iommus = <&smmu 0x860>;
 			power-domains = <&pd_usb0>;
 			ranges;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 
 			dwc3_0: dwc3@fe200000 {
 				compatible = "snps,dwc3";
@@ -1045,6 +1047,8 @@
 			iommus = <&smmu 0x861>;
 			power-domains = <&pd_usb1>;
 			ranges;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 
 			dwc3_1: dwc3@fe300000 {
 				compatible = "snps,dwc3";