From: Marek Vasut <marex@denx.de>
Date: Mon, 4 Apr 2016 15:28:16 +0000 (+0200)
Subject: ddr: altera: Fix scc_mgr_set() argument order
X-Git-Tag: v2016.05-rc2~4^2~9
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1;p=u-boot

ddr: altera: Fix scc_mgr_set() argument order

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index bf74b4e651..3859e66a00 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -279,7 +279,7 @@ static void scc_mgr_initialize(void)
 	for (i = 0; i < 16; i++) {
 		debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 			   __func__, __LINE__, i);
-		scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
+		scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
 	}
 }