From: Kumar Gala <galak@kernel.crashing.org>
Date: Fri, 7 Dec 2007 18:17:34 +0000 (-0600)
Subject: Handle MPC85xx PCIe reset errata (PCI-Ex 38)
X-Git-Tag: v1.3.2-rc1~109^2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d;p=u-boot

Handle MPC85xx PCIe reset errata (PCI-Ex 38)

On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 1e778844a5..68e45e17b3 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -112,6 +112,29 @@ fsl_pci_init(struct pci_controller *hose)
 		pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 		enabled = ltssm >= PCI_LTSSM_L0;
 
+#ifdef CONFIG_FSL_PCIE_RESET
+		if (ltssm == 1) {
+			int i;
+			debug("....PCIe link error. "
+			      "LTSSM=0x%02x.", ltssm);
+			pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
+			temp32 = pci->pdb_stat;
+			udelay(100);
+			debug("  Asserting PCIe reset @%x = %x\n",
+			      &pci->pdb_stat, pci->pdb_stat);
+			pci->pdb_stat &= ~0x08000000; /* clear reset */
+			asm("sync;isync");
+			for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
+				pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+							&ltssm);
+				udelay(1000);
+				debug("....PCIe link error. "
+				      "LTSSM=0x%02x.\n", ltssm);
+			}
+			enabled = ltssm >= PCI_LTSSM_L0;
+		}
+#endif
+
 		if (!enabled) {
 			debug("....PCIE link error.  Skipping scan."
 			      "LTSSM=0x%02x\n", ltssm);
diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h
index bd732b6688..6715064c94 100644
--- a/include/asm-ppc/immap_fsl_pci.h
+++ b/include/asm-ppc/immap_fsl_pci.h
@@ -144,7 +144,9 @@ typedef struct ccsr_pci {
 	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
 	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
 	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
-	char	res23[456];	/*     (- #x1000 #xe38) 456 */
+	char	res23[200];
+	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
+	char	res24[252];
 } ccsr_fsl_pci_t;
 
 #endif /*__IMMAP_fsl_pci__*/
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index b8cd50b629..545a76cc62 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -40,6 +40,7 @@
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 95affa556a..3f382e59a6 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -42,6 +42,7 @@
 #undef CONFIG_RIO
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 3822c1b825..59f490e856 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -37,6 +37,7 @@
 #define CONFIG_PCI1		1	/* PCI controller */
 #define CONFIG_PCIE1		1	/* PCIE controller */
 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE