From: Tom Rini Date: Sun, 20 May 2018 13:44:05 +0000 (-0400) Subject: Merge branch 'master' of git://git.denx.de/u-boot-socfpga X-Git-Tag: v2018.07-rc1~131 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=904e546970184d9f5b7e1bde7065b745e67a1bef;hp=855ff8e6dd58b01930d8b8b726e65310d546a0c9;p=u-boot Merge branch 'master' of git://git.denx.de/u-boot-socfpga --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 923fa49735..3e05f79f63 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -730,14 +730,27 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" + select ARCH_EARLY_INIT_R + select ARCH_MISC_INIT select CPU_V7A - select SUPPORT_SPL - select OF_CONTROL - select SPL_OF_CONTROL select DM + select DM_SERIAL select ENABLE_ARM_SOC_BOOT0_HOOK - select ARCH_EARLY_INIT_R - select ARCH_MISC_INIT + select OF_CONTROL + select SPL_LIBCOMMON_SUPPORT + select SPL_LIBDISK_SUPPORT + select SPL_LIBGENERIC_SUPPORT + select SPL_MMC_SUPPORT if DM_MMC + select SPL_NAND_SUPPORT if SPL_NAND_DENALI + select SPL_OF_CONTROL + select SPL_SERIAL_SUPPORT + select SPL_DM_SERIAL + select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT + select SPL_SPI_SUPPORT if DM_SPI + select SPL_WATCHDOG_SUPPORT + select SUPPORT_SPL + select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + select SYS_NS16550 select SYS_THUMB_BUILD imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3a240590f..a0349a8975 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -183,20 +183,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ - socfpga_arria10_socdk_sdmmc.dtb \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_dbm_soc1.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_de1_soc.dtb \ socfpga_cyclone5_de10_nano.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ - socfpga_stratix10_socdk.dtb \ - socfpga_cyclone5_vining_fpga.dtb + socfpga_cyclone5_vining_fpga.dtb \ + socfpga_stratix10_socdk.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index e64127fcb2..314449478d 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -737,6 +737,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + clock-frequency = <100000000>; }; uart1: serial1@ffc03000 { @@ -746,6 +747,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + clock-frequency = <100000000>; }; rst: rstmgr@ffd05000 { diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index abfd0bc4f8..b51febda9c 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -1,5 +1,5 @@ /* - * Copyright Altera Corporation (C) 2014-2017. All rights reserved. + * Copyright Altera Corporation (C) 2014. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms and conditions of the GNU General Public License, @@ -14,7 +14,6 @@ * this program. If not, see . */ -#include "skeleton.dtsi" #include #include @@ -22,29 +21,10 @@ #address-cells = <1>; #size-cells = <1>; - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - spi0 = &spi0; - spi1 = &spi1; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "altr,socfpga-a10-smp"; cpu@0 { compatible = "arm,cortex-a9"; @@ -102,321 +82,335 @@ }; }; - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - reg-names = "soc_clock_manager_OCP_SLV"; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb_intosc_ls_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; - f2s_free_clk: f2s_free_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; - main_pll: main_pll { + clocks { #address-cells = <1>; #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>; - reg = <0x40>; - main_mpu_base_clk: main_mpu_base_clk { + cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x140 0 11>; + compatible = "fixed-clock"; }; - main_noc_base_clk: main_noc_base_clk { + cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - div-reg = <0x144 0 11>; + compatible = "fixed-clock"; }; - main_emaca_clk: main_emaca_clk { + f2s_free_clk: f2s_free_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x68>; + compatible = "fixed-clock"; }; - main_emacb_clk: main_emacb_clk { + osc1: osc1 { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x6C>; + compatible = "fixed-clock"; }; - main_emac_ptp_clk: main_emac_ptp_clk { + main_pll: main_pll@40 { + #address-cells = <1>; + #size-cells = <0>; #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x70>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>; + reg = <0x40>; + + main_mpu_base_clk: main_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x140 0 11>; + }; + + main_noc_base_clk: main_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x144 0 11>; + }; + + main_emaca_clk: main_emaca_clk@68 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x68>; + }; + + main_emacb_clk: main_emacb_clk@6c { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x6C>; + }; + + main_emac_ptp_clk: main_emac_ptp_clk@70 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x70>; + }; + + main_gpio_db_clk: main_gpio_db_clk@74 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x74>; + }; + + main_sdmmc_clk: main_sdmmc_clk@78 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk" +; + clocks = <&main_pll>; + reg = <0x78>; + }; + + main_s2f_usr0_clk: main_s2f_usr0_clk@7c { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x7C>; + }; + + main_s2f_usr1_clk: main_s2f_usr1_clk@80 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x80>; + }; + + main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x84>; + }; + + main_periph_ref_clk: main_periph_ref_clk@9c { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x9C>; + }; }; - main_gpio_db_clk: main_gpio_db_clk { + periph_pll: periph_pll@c0 { + #address-cells = <1>; + #size-cells = <0>; #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x74>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>, <&main_periph_ref_clk>; + reg = <0xC0>; + + peri_mpu_base_clk: peri_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x140 16 11>; + }; + + peri_noc_base_clk: peri_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x144 16 11>; + }; + + peri_emaca_clk: peri_emaca_clk@e8 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xE8>; + }; + + peri_emacb_clk: peri_emacb_clk@ec { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xEC>; + }; + + peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF0>; + }; + + peri_gpio_db_clk: peri_gpio_db_clk@f4 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF4>; + }; + + peri_sdmmc_clk: peri_sdmmc_clk@f8 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF8>; + }; + + peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xFC>; + }; + + peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x100>; + }; + + peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x104>; + }; }; - main_sdmmc_clk: main_sdmmc_clk { + mpu_free_clk: mpu_free_clk@60 { #clock-cells = <0>; compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x78>; + clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x60>; }; - main_s2f_usr0_clk: main_s2f_usr0_clk { + noc_free_clk: noc_free_clk@64 { #clock-cells = <0>; compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x7C>; + clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x64>; }; - main_s2f_usr1_clk: main_s2f_usr1_clk { + s2f_user1_free_clk: s2f_user1_free_clk@104 { #clock-cells = <0>; compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x80>; + clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x104>; }; - main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { + sdmmc_free_clk: sdmmc_free_clk@f8 { #clock-cells = <0>; compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x84>; + clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + fixed-divider = <4>; + reg = <0xF8>; }; - main_periph_ref_clk: main_periph_ref_clk { + l4_sys_free_clk: l4_sys_free_clk { #clock-cells = <0>; compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_pll>; - reg = <0x9C>; + clocks = <&noc_free_clk>; + fixed-divider = <4>; }; - }; - - periph_pll: periph_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-a10-pll-clock"; - clocks = <&osc1>, <&cb_intosc_ls_clk>, - <&f2s_free_clk>, <&main_periph_ref_clk>; - reg = <0xC0>; - peri_mpu_base_clk: peri_mpu_base_clk { + l4_main_clk: l4_main_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x140 16 11>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 0 2>; + clk-gate = <0x48 1>; }; - peri_noc_base_clk: peri_noc_base_clk { + l4_mp_clk: l4_mp_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - div-reg = <0x144 16 11>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 8 2>; + clk-gate = <0x48 2>; }; - peri_emaca_clk: peri_emaca_clk { + l4_sp_clk: l4_sp_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xE8>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 16 2>; + clk-gate = <0x48 3>; }; - peri_emacb_clk: peri_emacb_clk { + mpu_periph_clk: mpu_periph_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xEC>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&mpu_free_clk>; + fixed-divider = <4>; + clk-gate = <0x48 0>; }; - peri_emac_ptp_clk: peri_emac_ptp_clk { + sdmmc_clk: sdmmc_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&sdmmc_free_clk>; + clk-gate = <0xC8 5>; + clk-phase = <0 135>; }; - peri_gpio_db_clk: peri_gpio_db_clk { + qspi_clk: qspi_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF4>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 11>; }; - peri_sdmmc_clk: peri_sdmmc_clk { + nand_clk: nand_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xF8>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 10>; }; - peri_s2f_usr0_clk: peri_s2f_usr0_clk { + spi_m_clk: spi_m_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0xFC>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 9>; }; - peri_s2f_usr1_clk: peri_s2f_usr1_clk { + usb_clk: usb_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x100>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 8>; }; - peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { + s2f_usr1_clk: s2f_usr1_clk { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&periph_pll>; - reg = <0x104>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&peri_s2f_usr1_clk>; + clk-gate = <0xC8 6>; }; }; + }; - mpu_free_clk: mpu_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x60>; - }; - - noc_free_clk: noc_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x64>; - }; - - s2f_user1_free_clk: s2f_user1_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - reg = <0x104>; - }; - - sdmmc_free_clk: sdmmc_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, - <&osc1>, <&cb_intosc_hs_div2_clk>, - <&f2s_free_clk>; - fixed-divider = <4>; - reg = <0xF8>; - }; - - l4_sys_free_clk: l4_sys_free_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk"; - clocks = <&noc_free_clk>; - fixed-divider = <4>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 0 2>; - clk-gate = <0x48 1>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 8 2>; - clk-gate = <0x48 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&noc_free_clk>; - div-reg = <0xA8 16 2>; - clk-gate = <0x48 3>; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&mpu_free_clk>; - fixed-divider = <4>; - clk-gate = <0x48 0>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&sdmmc_free_clk>; - clk-gate = <0xC8 5>; - clk-phase = <0 135>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 11>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 10>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_main_clk>; - clk-gate = <0xC8 9>; - }; - - usb_clk: usb_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&l4_mp_clk>; - clk-gate = <0xC8 8>; - }; - - s2f_usr1_clk: s2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-a10-gate-clk"; - clocks = <&peri_s2f_usr1_clk>; - clk-gate = <0xC8 6>; - }; - }; + socfpga_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <0 0 0 0 16 0 0>; }; gmac0: ethernet@ff800000 { @@ -435,6 +429,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC0_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -454,6 +449,7 @@ clock-names = "stmmaceth"; resets = <&rst EMAC1_RESET>; reset-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -471,6 +467,7 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; + snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -483,6 +480,7 @@ porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "porta"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -502,6 +500,7 @@ portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "portb"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -521,6 +520,7 @@ portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "portc"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <27>; @@ -590,37 +590,24 @@ status = "disabled"; }; - sdr: sdr@0xffcfb100 { - compatible = "syscon"; - reg = <0xffcfb100 0x80>; - }; - - spi0: spi@ffda4000 { + spi1: spi@ffda5000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; #size-cells = <0>; - reg = <0xffda4000 0x100>; - interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; num-chipselect = <4>; bus-num = <0>; + /*32bit_access;*/ tx-dma-channel = <&pdma 16>; rx-dma-channel = <&pdma 17>; clocks = <&spi_m_clk>; status = "disabled"; }; - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x100>; - interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; - num-chipselect = <4>; - bus-num = <0>; - tx-dma-channel = <&pdma 20>; - rx-dma-channel = <&pdma 21>; - clocks = <&spi_m_clk>; - status = "disabled"; + sdr: sdr@ffc25000 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xffcfb100 0x80>; }; L2: l2-cache@fffff000 { @@ -629,6 +616,9 @@ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,shared-override; }; mmc: dwmmc0@ff808000 { @@ -638,18 +628,30 @@ reg = <0xff808000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; fifo-depth = <0x400>; - bus-width = <4>; clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x72000>, + <0xffb80000 0x10000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 99 4>; + dma-mask = <0xffffffff>; + clocks = <&nand_clk>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; }; - eccmgr: eccmgr@ffd06000 { + eccmgr: eccmgr { compatible = "altr,socfpga-a10-ecc-manager"; altr,sysmgr-syscon = <&sysmgr>; #address-cells = <1>; @@ -681,16 +683,6 @@ <33 IRQ_TYPE_LEVEL_HIGH>; }; - sdmmca-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; - emac0-rx-ecc@ff8c0800 { compatible = "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0800 0x400>; @@ -724,19 +716,17 @@ }; }; - qspi: qspi@ff809000 { + qspi: spi@ff809000 { + compatible = "cdns,qspi-nor", "cadence,qspi"; #address-cells = <1>; #size-cells = <0>; - compatible = "cadence,qspi"; reg = <0xff809000 0x100>, - <0xffa00000 0x100000>; + <0xffa00000 0x100000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&l4_main_clk>; - ext-decoder = <0>; /* external decoder */ - num-chipselect = <4>; cdns,fifo-depth = <128>; cdns,fifo-width = <4>; - bus-num = <2>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; status = "disabled"; }; @@ -818,7 +808,7 @@ status = "disabled"; }; - usbphy0: usbphy@0 { + usbphy0: usbphy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; status = "okay"; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi new file mode 100644 index 0000000000..d7616dd1c5 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2015 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + serial0 = &uart1; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + a10leds { + compatible = "gpio-leds"; + + a10sr_led0 { + label = "a10sr-led0"; + gpios = <&a10sr_gpio 0 1>; + }; + + a10sr_led1 { + label = "a10sr-led1"; + gpios = <&a10sr_gpio 1 1>; + }; + + a10sr_led2 { + label = "a10sr-led2"; + gpios = <&a10sr_gpio 2 1>; + }; + + a10sr_led3 { + label = "a10sr-led3"; + gpios = <&a10sr_gpio 3 1>; + }; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + /* + * These skews assume the user's FPGA design is adding 600ps of delay + * for TX_CLK on Arria 10. + * + * All skews are offset since hardware skew values for the ksz9031 + * range from a negative skew to a positive skew. + * See the micrel-ksz90x1.txt Documentation file for details. + */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + max-frame-size = <3800>; + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + resource-manager@0 { + compatible = "altr,a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + /* low-level active IRQ at GPIO1_5 */ + interrupt-parent = <&portb>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + a10sr_gpio: gpio-controller { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + a10sr_rst: reset-controller { + compatible = "altr,a10sr-reset"; + #reset-cells = <1>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + /* + * adjust the falling times to decrease the i2c frequency to 50Khz + * because the LCD module does not work at the standard 100Khz + */ + clock-frequency = <100000>; + i2c-sda-falling-time-ns = <6000>; + i2c-scl-falling-time-ns = <6000>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + + ltc@5c { + compatible = "ltc2977"; + reg = <0x5c>; + }; +}; + +&uart1 { + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog1 { + status = "okay"; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index b573d0e658..9c6070ded9 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -1,32 +1,22 @@ /* - * Copyright (C) 2015-2017 Altera Corporation. All rights reserved. + * Copyright (C) 2014-2015 Altera Corporation * * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ /dts-v1/; -#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" - -/ { - chosen { - bootargs = "console=ttyS0,115200"; - }; -}; - -&uart1 { - u-boot,dm-pre-reloc; - status = "okay"; -}; +#include "socfpga_arria10_socdk.dtsi" &mmc { u-boot,dm-pre-reloc; @@ -36,3 +26,15 @@ broken-cd; bus-width = <4>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi index b6939b011a..39009654d9 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi @@ -14,467 +14,337 @@ #include "socfpga_arria10.dtsi" / { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + #address-cells = <1>; + #size-cells = <1>; + model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ chosen { - /* Bootloader setting: uboot.rbf_filename */ - cff-file = "ghrd_10as066n2.periph.rbf"; - early-release-fpga-config; + cff-file = "socfpga.rbf"; /* Bootloader setting: uboot.rbf_filename */ }; - soc { + /* Clock sources */ + clocks { u-boot,dm-pre-reloc; - clkmgr@ffd04000 { + #address-cells = <1>; + #size-cells = <1>; + + /* Clock source: altera_arria10_hps_eosc1 */ + altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + /* Clock source: altera_arria10_hps_cb_intosc_ls */ + altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + /* Clock source: altera_arria10_hps_f2h_free */ + altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + }; + + /* + * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_clk_mgr: clock_manager@0xffd04000 { + u-boot,dm-pre-reloc; + compatible = "altr,socfpga-a10-clk-init"; + reg = <0xffd04000 0x00000200>; + reg-names = "soc_clock_manager_OCP_SLV"; + + /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */ + mainpll { u-boot,dm-pre-reloc; - clocks { - u-boot,dm-pre-reloc; - osc1 { - u-boot,dm-pre-reloc; - clock-frequency = <25000000>; - clock-output-names = "altera_arria10_hps_eosc1-clk"; - }; + vco0-psrc = <0>; /* Field: vco0.psrc */ + vco1-denom = <1>; /* Field: vco1.denom */ + vco1-numer = <191>; /* Field: vco1.numer */ + mpuclk-cnt = <0>; /* Field: mpuclk.cnt */ + mpuclk-src = <0>; /* Field: mpuclk.src */ + nocclk-cnt = <0>; /* Field: nocclk.cnt */ + nocclk-src = <0>; /* Field: nocclk.src */ + cntr2clk-cnt = <900>; /* Field: cntr2clk.cnt */ + cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ + cntr4clk-cnt = <900>; /* Field: cntr4clk.cnt */ + cntr5clk-cnt = <900>; /* Field: cntr5clk.cnt */ + cntr6clk-cnt = <900>; /* Field: cntr6clk.cnt */ + cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ + cntr7clk-src = <0>; /* Field: cntr7clk.src */ + cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ + cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ + cntr9clk-src = <0>; /* Field: cntr9clk.src */ + cntr15clk-cnt = <900>; /* Field: cntr15clk.cnt */ + nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */ + nocdiv-l4mpclk = <0>; /* Field: nocdiv.l4mpclk */ + nocdiv-l4spclk = <2>; /* Field: nocdiv.l4spclk */ + nocdiv-csatclk = <0>; /* Field: nocdiv.csatclk */ + nocdiv-cstraceclk = <1>; /* Field: nocdiv.cstraceclk */ + nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */ + }; - cb_intosc_ls_clk { - u-boot,dm-pre-reloc; - clock-frequency = <60000000>; - clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; - }; + /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */ + perpll { + u-boot,dm-pre-reloc; + vco0-psrc = <0>; /* Field: vco0.psrc */ + vco1-denom = <1>; /* Field: vco1.denom */ + vco1-numer = <159>; /* Field: vco1.numer */ + cntr2clk-cnt = <7>; /* Field: cntr2clk.cnt */ + cntr2clk-src = <1>; /* Field: cntr2clk.src */ + cntr3clk-cnt = <900>; /* Field: cntr3clk.cnt */ + cntr3clk-src = <1>; /* Field: cntr3clk.src */ + cntr4clk-cnt = <19>; /* Field: cntr4clk.cnt */ + cntr4clk-src = <1>; /* Field: cntr4clk.src */ + cntr5clk-cnt = <499>; /* Field: cntr5clk.cnt */ + cntr5clk-src = <1>; /* Field: cntr5clk.src */ + cntr6clk-cnt = <9>; /* Field: cntr6clk.cnt */ + cntr6clk-src = <1>; /* Field: cntr6clk.src */ + cntr7clk-cnt = <900>; /* Field: cntr7clk.cnt */ + cntr8clk-cnt = <900>; /* Field: cntr8clk.cnt */ + cntr8clk-src = <0>; /* Field: cntr8clk.src */ + cntr9clk-cnt = <900>; /* Field: cntr9clk.cnt */ + emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */ + emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */ + emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */ + gpiodiv-gpiodbclk = <32000>; /* Field: gpiodiv.gpiodbclk */ + }; - f2s_free_clk { - u-boot,dm-pre-reloc; - clock-frequency = <200000000>; - clock-output-names = "altera_arria10_hps_f2h_free-clk"; - }; + /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */ + alteragrp { + u-boot,dm-pre-reloc; + nocclk = <0x0384000b>; /* Register: nocclk */ + mpuclk = <0x03840001>; /* Register: mpuclk */ + }; + }; - main_pll { - u-boot,dm-pre-reloc; - /* - * Address Block: soc_clock_manager_OCP_SLV. - * i_clk_mgr_mainpllgrp - */ - altr,of_reg_value = < - 0 /* Field: vco0.psrc */ - 1 /* Field: vco1.denom */ - 191 /* Field: vco1.numer */ - 0 /* Field: mpuclk */ - 0 /* Field: mpuclk.cnt */ - 0 /* Field: mpuclk.src */ - 0 /* Field: nocclk */ - 0 /* Field: nocclk.cnt */ - 0 /* Field: nocclk.src */ - 900 /* Field: cntr2clk.cnt */ - 900 /* Field: cntr3clk.cnt */ - 900 /* Field: cntr4clk.cnt */ - 900 /* Field: cntr5clk.cnt */ - 900 /* Field: cntr6clk.cnt */ - 900 /* Field: cntr7clk.cnt */ - 0 /* Field: cntr7clk.src */ - 900 /* Field: cntr8clk.cnt */ - 900 /* Field: cntr9clk.cnt */ - 0 /* Field: cntr9clk.src */ - 900 /* Field: cntr15clk.cnt */ - 0 /* Field: nocdiv.l4mainclk */ - 0 /* Field: nocdiv.l4mpclk */ - 2 /* Field: nocdiv.l4spclk */ - 0 /* Field: nocdiv.csatclk */ - 1 /* Field: nocdiv.cstraceclk */ - 1 /* Field: nocdiv.cspdbgclk */ - >; - }; + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Version: 1.0 + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; - periph_pll { - u-boot,dm-pre-reloc; - /* - * Address Block: soc_clock_manager_OCP_SLV. - * i_clk_mgr_perpllgrp - */ - altr,of_reg_value = < - 0 /* Field: vco0.psrc */ - 1 /* Field: vco1.denom */ - 159 /* Field: vco1.numer */ - 7 /* Field: cntr2clk.cnt */ - 1 /* Field: cntr2clk.src */ - 900 /* Field: cntr3clk.cnt */ - 1 /* Field: cntr3clk.src */ - 19 /* Field: cntr4clk.cnt */ - 1 /* Field: cntr4clk.src */ - 499 /* Field: cntr5clk.cnt */ - 1 /* Field: cntr5clk.src */ - 9 /* Field: cntr6clk.cnt */ - 1 /* Field: cntr6clk.src */ - 900 /* Field: cntr7clk.cnt */ - 900 /* Field: cntr8clk.cnt */ - 0 /* Field: cntr8clk.src */ - 900 /* Field: cntr9clk.cnt */ - 0 /* Field: emacctl.emac0sel */ - 0 /* Field: emacctl.emac1sel */ - 0 /* Field: emacctl.emac2sel */ - 32000 /* Field: gpiodiv.gpiodbclk */ - >; - }; + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */ + shared { + u-boot,dm-pre-reloc; + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + <0x00000000 0x00000008>, /* Register: pinmux_shared_io_q1_1 */ + <0x00000004 0x00000008>, /* Register: pinmux_shared_io_q1_2 */ + <0x00000008 0x00000008>, /* Register: pinmux_shared_io_q1_3 */ + <0x0000000c 0x00000008>, /* Register: pinmux_shared_io_q1_4 */ + <0x00000010 0x00000008>, /* Register: pinmux_shared_io_q1_5 */ + <0x00000014 0x00000008>, /* Register: pinmux_shared_io_q1_6 */ + <0x00000018 0x00000008>, /* Register: pinmux_shared_io_q1_7 */ + <0x0000001c 0x00000008>, /* Register: pinmux_shared_io_q1_8 */ + <0x00000020 0x00000008>, /* Register: pinmux_shared_io_q1_9 */ + <0x00000024 0x00000008>, /* Register: pinmux_shared_io_q1_10 */ + <0x00000028 0x00000008>, /* Register: pinmux_shared_io_q1_11 */ + <0x0000002c 0x00000008>, /* Register: pinmux_shared_io_q1_12 */ + <0x00000030 0x00000004>, /* Register: pinmux_shared_io_q2_1 */ + <0x00000034 0x00000004>, /* Register: pinmux_shared_io_q2_2 */ + <0x00000038 0x00000004>, /* Register: pinmux_shared_io_q2_3 */ + <0x0000003c 0x00000004>, /* Register: pinmux_shared_io_q2_4 */ + <0x00000040 0x00000004>, /* Register: pinmux_shared_io_q2_5 */ + <0x00000044 0x00000004>, /* Register: pinmux_shared_io_q2_6 */ + <0x00000048 0x00000004>, /* Register: pinmux_shared_io_q2_7 */ + <0x0000004c 0x00000004>, /* Register: pinmux_shared_io_q2_8 */ + <0x00000050 0x00000004>, /* Register: pinmux_shared_io_q2_9 */ + <0x00000054 0x00000004>, /* Register: pinmux_shared_io_q2_10 */ + <0x00000058 0x00000004>, /* Register: pinmux_shared_io_q2_11 */ + <0x0000005c 0x00000004>, /* Register: pinmux_shared_io_q2_12 */ + <0x00000060 0x00000003>, /* Register: pinmux_shared_io_q3_1 */ + <0x00000064 0x00000003>, /* Register: pinmux_shared_io_q3_2 */ + <0x00000068 0x00000003>, /* Register: pinmux_shared_io_q3_3 */ + <0x0000006c 0x00000003>, /* Register: pinmux_shared_io_q3_4 */ + <0x00000070 0x00000003>, /* Register: pinmux_shared_io_q3_5 */ + <0x00000074 0x0000000f>, /* Register: pinmux_shared_io_q3_6 */ + <0x00000078 0x0000000a>, /* Register: pinmux_shared_io_q3_7 */ + <0x0000007c 0x0000000a>, /* Register: pinmux_shared_io_q3_8 */ + <0x00000080 0x0000000a>, /* Register: pinmux_shared_io_q3_9 */ + <0x00000084 0x0000000a>, /* Register: pinmux_shared_io_q3_10 */ + <0x00000088 0x00000001>, /* Register: pinmux_shared_io_q3_11 */ + <0x0000008c 0x00000001>, /* Register: pinmux_shared_io_q3_12 */ + <0x00000090 0x00000000>, /* Register: pinmux_shared_io_q4_1 */ + <0x00000094 0x00000000>, /* Register: pinmux_shared_io_q4_2 */ + <0x00000098 0x0000000f>, /* Register: pinmux_shared_io_q4_3 */ + <0x0000009c 0x0000000c>, /* Register: pinmux_shared_io_q4_4 */ + <0x000000a0 0x0000000f>, /* Register: pinmux_shared_io_q4_5 */ + <0x000000a4 0x0000000f>, /* Register: pinmux_shared_io_q4_6 */ + <0x000000a8 0x0000000a>, /* Register: pinmux_shared_io_q4_7 */ + <0x000000ac 0x0000000a>, /* Register: pinmux_shared_io_q4_8 */ + <0x000000b0 0x0000000c>, /* Register: pinmux_shared_io_q4_9 */ + <0x000000b4 0x0000000c>, /* Register: pinmux_shared_io_q4_10 */ + <0x000000b8 0x0000000c>, /* Register: pinmux_shared_io_q4_11 */ + <0x000000bc 0x0000000c>; /* Register: pinmux_shared_io_q4_12 */ + }; + + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ + dedicated { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + <0x0000000c 0x00000008>, /* Register: pinmux_dedicated_io_4 */ + <0x00000010 0x00000008>, /* Register: pinmux_dedicated_io_5 */ + <0x00000014 0x00000008>, /* Register: pinmux_dedicated_io_6 */ + <0x00000018 0x00000008>, /* Register: pinmux_dedicated_io_7 */ + <0x0000001c 0x00000008>, /* Register: pinmux_dedicated_io_8 */ + <0x00000020 0x00000008>, /* Register: pinmux_dedicated_io_9 */ + <0x00000024 0x0000000a>, /* Register: pinmux_dedicated_io_10 */ + <0x00000028 0x0000000a>, /* Register: pinmux_dedicated_io_11 */ + <0x0000002c 0x00000008>, /* Register: pinmux_dedicated_io_12 */ + <0x00000030 0x00000008>, /* Register: pinmux_dedicated_io_13 */ + <0x00000034 0x00000008>, /* Register: pinmux_dedicated_io_14 */ + <0x00000038 0x00000008>, /* Register: pinmux_dedicated_io_15 */ + <0x0000003c 0x0000000d>, /* Register: pinmux_dedicated_io_16 */ + <0x00000040 0x0000000d>; /* Register: pinmux_dedicated_io_17 */ + }; - altera { - u-boot,dm-pre-reloc; - /* - * Address Block: soc_clock_manager_OCP_SLV. - * i_clk_mgr_alteragrp - */ - altr,of_reg_value = < - 0x0384000b /* Register: nocclk */ - 0x03840001 /* Register: mpuclk */ - >; - }; - }; + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */ + dedicated_cfg { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + <0x00000100 0x00000101>, /* Register: configuration_dedicated_io_bank */ + <0x00000104 0x000b080a>, /* Register: configuration_dedicated_io_1 */ + <0x00000108 0x000b080a>, /* Register: configuration_dedicated_io_2 */ + <0x0000010c 0x000b080a>, /* Register: configuration_dedicated_io_3 */ + <0x00000110 0x000a282a>, /* Register: configuration_dedicated_io_4 */ + <0x00000114 0x000a282a>, /* Register: configuration_dedicated_io_5 */ + <0x00000118 0x0008282a>, /* Register: configuration_dedicated_io_6 */ + <0x0000011c 0x000a282a>, /* Register: configuration_dedicated_io_7 */ + <0x00000120 0x000a282a>, /* Register: configuration_dedicated_io_8 */ + <0x00000124 0x000a282a>, /* Register: configuration_dedicated_io_9 */ + <0x00000128 0x00090000>, /* Register: configuration_dedicated_io_10 */ + <0x0000012c 0x00090000>, /* Register: configuration_dedicated_io_11 */ + <0x00000130 0x000b282a>, /* Register: configuration_dedicated_io_12 */ + <0x00000134 0x000b282a>, /* Register: configuration_dedicated_io_13 */ + <0x00000138 0x000b282a>, /* Register: configuration_dedicated_io_14 */ + <0x0000013c 0x000b282a>, /* Register: configuration_dedicated_io_15 */ + <0x00000140 0x0008282a>, /* Register: configuration_dedicated_io_16 */ + <0x00000144 0x000a282a>; /* Register: configuration_dedicated_io_17 */ }; - /* - * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver - * Binding: pinmux - */ - i_io48_pin_mux: pinmux@0xffd07000 { + /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */ + fpga { u-boot,dm-pre-reloc; - #address-cells = <1>; - #size-cells = <1>; - compatible = "pinctrl-single"; - reg = <0xffd07000 0x00000800>; - reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + <0x00000000 0x00000000>, /* Register: pinmux_emac0_usefpga */ + <0x00000004 0x00000000>, /* Register: pinmux_emac1_usefpga */ + <0x00000008 0x00000000>, /* Register: pinmux_emac2_usefpga */ + <0x0000000c 0x00000000>, /* Register: pinmux_i2c0_usefpga */ + <0x00000010 0x00000000>, /* Register: pinmux_i2c1_usefpga */ + <0x00000014 0x00000000>, /* Register: pinmux_i2c_emac0_usefpga */ + <0x00000018 0x00000000>, /* Register: pinmux_i2c_emac1_usefpga */ + <0x0000001c 0x00000000>, /* Register: pinmux_i2c_emac2_usefpga */ + <0x00000020 0x00000000>, /* Register: pinmux_nand_usefpga */ + <0x00000024 0x00000000>, /* Register: pinmux_qspi_usefpga */ + <0x00000028 0x00000000>, /* Register: pinmux_sdmmc_usefpga */ + <0x0000002c 0x00000000>, /* Register: pinmux_spim0_usefpga */ + <0x00000030 0x00000000>, /* Register: pinmux_spim1_usefpga */ + <0x00000034 0x00000000>, /* Register: pinmux_spis0_usefpga */ + <0x00000038 0x00000000>, /* Register: pinmux_spis1_usefpga */ + <0x0000003c 0x00000000>, /* Register: pinmux_uart0_usefpga */ + <0x00000040 0x00000000>; /* Register: pinmux_uart1_usefpga */ + }; + }; + + /* + * Driver: altera_arria10_soc_noc_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_noc: noc@0xffd10000 { + u-boot,dm-pre-reloc; + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + firewall { + u-boot,dm-pre-reloc; /* - * Address Block: soc_3v_io48_pin_mux_OCP_SLV. - * i_io48_pin_mux_shared_3v_io_grp + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit */ - shared { - u-boot,dm-pre-reloc; - reg = <0xffd07000 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - pinctrl-single,pins = - /* Reg: pinmux_shared_io_q1_1 */ - <0x00000000 0x00000008>, - /* Reg: pinmux_shared_io_q1_2 */ - <0x00000004 0x00000008>, - /* Reg: pinmux_shared_io_q1_3 */ - <0x00000008 0x00000008>, - /* Reg: pinmux_shared_io_q1_4 */ - <0x0000000c 0x00000008>, - /* Reg: pinmux_shared_io_q1_5 */ - <0x00000010 0x00000008>, - /* Reg: pinmux_shared_io_q1_6 */ - <0x00000014 0x00000008>, - /* Reg: pinmux_shared_io_q1_7 */ - <0x00000018 0x00000008>, - /* Reg: pinmux_shared_io_q1_8 */ - <0x0000001c 0x00000008>, - /* Reg: pinmux_shared_io_q1_9 */ - <0x00000020 0x00000008>, - /* Reg: pinmux_shared_io_q1_10 */ - <0x00000024 0x00000008>, - /* Reg: pinmux_shared_io_q1_11 */ - <0x00000028 0x00000008>, - /* Reg: pinmux_shared_io_q1_12 */ - <0x0000002c 0x00000008>, - /* Reg: pinmux_shared_io_q2_1 */ - <0x00000030 0x00000004>, - /* Reg: pinmux_shared_io_q2_2 */ - <0x00000034 0x00000004>, - /* Reg: pinmux_shared_io_q2_3 */ - <0x00000038 0x00000004>, - /* Reg: pinmux_shared_io_q2_4 */ - <0x0000003c 0x00000004>, - /* Reg: pinmux_shared_io_q2_5 */ - <0x00000040 0x00000004>, - /* Reg: pinmux_shared_io_q2_6 */ - <0x00000044 0x00000004>, - /* Reg: pinmux_shared_io_q2_7 */ - <0x00000048 0x00000004>, - /* Reg: pinmux_shared_io_q2_8 */ - <0x0000004c 0x00000004>, - /* Reg: pinmux_shared_io_q2_9 */ - <0x00000050 0x00000004>, - /* Reg: pinmux_shared_io_q2_10 */ - <0x00000054 0x00000004>, - /* Reg: pinmux_shared_io_q2_11 */ - <0x00000058 0x00000004>, - /* Reg: pinmux_shared_io_q2_12 */ - <0x0000005c 0x00000004>, - /* Reg: pinmux_shared_io_q3_1 */ - <0x00000060 0x00000003>, - /* Reg: pinmux_shared_io_q3_2 */ - <0x00000064 0x00000003>, - /* Reg: pinmux_shared_io_q3_3 */ - <0x00000068 0x00000003>, - /* Reg: pinmux_shared_io_q3_4 */ - <0x0000006c 0x00000003>, - /* Reg: pinmux_shared_io_q3_5 */ - <0x00000070 0x00000003>, - /* Reg: pinmux_shared_io_q3_6 */ - <0x00000074 0x0000000f>, - /* Reg: pinmux_shared_io_q3_7 */ - <0x00000078 0x0000000a>, - /* Reg: pinmux_shared_io_q3_8 */ - <0x0000007c 0x0000000a>, - /* Reg: pinmux_shared_io_q3_9 */ - <0x00000080 0x0000000a>, - /* Reg: pinmux_shared_io_q3_10 */ - <0x00000084 0x0000000a>, - /* Reg: pinmux_shared_io_q3_11 */ - <0x00000088 0x00000001>, - /* Reg: pinmux_shared_io_q3_12 */ - <0x0000008c 0x00000001>, - /* Reg: pinmux_shared_io_q4_1 */ - <0x00000090 0x00000000>, - /* Reg: pinmux_shared_io_q4_2 */ - <0x00000094 0x00000000>, - /* Reg: pinmux_shared_io_q4_3 */ - <0x00000098 0x0000000f>, - /* Reg: pinmux_shared_io_q4_4 */ - <0x0000009c 0x0000000c>, - /* Reg: pinmux_shared_io_q4_5 */ - <0x000000a0 0x0000000f>, - /* Reg: pinmux_shared_io_q4_6 */ - <0x000000a4 0x0000000f>, - /* Reg: pinmux_shared_io_q4_7 */ - <0x000000a8 0x0000000a>, - /* Reg: pinmux_shared_io_q4_8 */ - <0x000000ac 0x0000000a>, - /* Reg: pinmux_shared_io_q4_9 */ - <0x000000b0 0x0000000c>, - /* Reg: pinmux_shared_io_q4_10 */ - <0x000000b4 0x0000000c>, - /* Reg: pinmux_shared_io_q4_11 */ - <0x000000b8 0x0000000c>, - /* Reg: pinmux_shared_io_q4_12 */ - <0x000000bc 0x0000000c>; - }; - + mpu0 = <0x00000000 0x0000ffff>; /* - * Address Block: soc_3v_io48_pin_mux_OCP_SLV. - * i_io48_pin_mux_dedicated_io_grp + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit */ - dedicated { - u-boot,dm-pre-reloc; - reg = <0xffd07200 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000f>; - pinctrl-single,pins = - /* Reg: pinmux_dedicated_io_4 */ - <0x0000000c 0x00000008>, - /* Reg: pinmux_dedicated_io_5 */ - <0x00000010 0x00000008>, - /* Reg: pinmux_dedicated_io_6 */ - <0x00000014 0x00000008>, - /* Regi: pinmux_dedicated_io_7 */ - <0x00000018 0x00000008>, - /* Reg: pinmux_dedicated_io_8 */ - <0x0000001c 0x00000008>, - /* Reg: pinmux_dedicated_io_9 */ - <0x00000020 0x00000008>, - /* Reg: pinmux_dedicated_io_10 */ - <0x00000024 0x0000000a>, - /* Reg: pinmux_dedicated_io_11 */ - <0x00000028 0x0000000a>, - /* Reg: pinmux_dedicated_io_12 */ - <0x0000002c 0x00000008>, - /* Reg: pinmux_dedicated_io_13 */ - <0x00000030 0x00000008>, - /* Reg: pinmux_dedicated_io_14 */ - <0x00000034 0x00000008>, - /* Reg: pinmux_dedicated_io_15 */ - <0x00000038 0x00000008>, - /* Reg: pinmux_dedicated_io_16 */ - <0x0000003c 0x0000000d>, - /* Reg: pinmux_dedicated_io_17 */ - <0x00000040 0x0000000d>; - }; - + l3-0 = <0x00000000 0x0000ffff>; /* - * Address Block: soc_3v_io48_pin_mux_OCP_SLV. - * i_io48_pin_mux_dedicated_io_grp + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit */ - dedicated_cfg { - u-boot,dm-pre-reloc; - reg = <0xffd07200 0x00000200>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x003f3f3f>; - pinctrl-single,pins = - /* Reg: cfg_dedicated_io_bank */ - <0x00000100 0x00000101>, - /* Reg: cfg_dedicated_io_1 */ - <0x00000104 0x000b080a>, - /* Reg: cfg_dedicated_io_2 */ - <0x00000108 0x000b080a>, - /* Reg: cfg_dedicated_io_3 */ - <0x0000010c 0x000b080a>, - /* Reg: cfg_dedicated_io_4 */ - <0x00000110 0x000a282a>, - /* Reg: cfg_dedicated_io_5 */ - <0x00000114 0x000a282a>, - /* Reg: cfg_dedicated_io_6 */ - <0x00000118 0x0008282a>, - /* Reg: cfg_dedicated_io_7 */ - <0x0000011c 0x000a282a>, - /* Reg: cfg_dedicated_io_8 */ - <0x00000120 0x000a282a>, - /* Reg: cfg_dedicated_io_9 */ - <0x00000124 0x000a282a>, - /* Reg: cfg_dedicated_io_10 */ - <0x00000128 0x00090000>, - /* Reg: cfg_dedicated_io_11 */ - <0x0000012c 0x00090000>, - /* Reg: cfg_dedicated_io_12 */ - <0x00000130 0x000b282a>, - /* Reg: cfg_dedicated_io_13 */ - <0x00000134 0x000b282a>, - /* Reg: cfg_dedicated_io_14 */ - <0x00000138 0x000b282a>, - /* Reg: cfg_dedicated_io_15 */ - <0x0000013c 0x000b282a>, - /* Reg: cfg_dedicated_io_16 */ - <0x00000140 0x0008282a>, - /* Reg: cfg_dedicated_io_17 */ - <0x00000144 0x000a282a>; - }; - + fpga2sdram0-0 = <0x00000000 0x0000ffff>; /* - * Address Block: soc_3v_io48_pin_mux_OCP_SLV. - * i_io48_pin_mux_fpga_interface_grp + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit */ - fpga { - u-boot,dm-pre-reloc; - reg = <0xffd07400 0x00000100>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x00000001>; - pinctrl-single,pins = - /* Reg: pinmux_emac0_usefpga */ - <0x00000000 0x00000000>, - /* Reg: pinmux_emac1_usefpga */ - <0x00000004 0x00000000>, - /* Reg: pinmux_emac2_usefpga */ - <0x00000008 0x00000000>, - /* Reg: pinmux_i2c0_usefpga */ - <0x0000000c 0x00000000>, - /* Reg: pinmux_i2c1_usefpga */ - <0x00000010 0x00000000>, - /* Reg: pinmux_i2c_emac0_usefpga */ - <0x00000014 0x00000000>, - /* Reg: pinmux_i2c_emac1_usefpga */ - <0x00000018 0x00000000>, - /* Reg: pinmux_i2c_emac2_usefpga */ - <0x0000001c 0x00000000>, - /* Reg: pinmux_nand_usefpga */ - <0x00000020 0x00000000>, - /* Reg: pinmux_qspi_usefpga */ - <0x00000024 0x00000000>, - /* Reg: pinmux_sdmmc_usefpga */ - <0x00000028 0x00000000>, - /* Reg: pinmux_spim0_usefpga */ - <0x0000002c 0x00000000>, - /* Reg: pinmux_spim1_usefpga */ - <0x00000030 0x00000000>, - /* Reg: pinmux_spis0_usefpga */ - <0x00000034 0x00000000>, - /* Reg: pinmux_spis1_usefpga */ - <0x00000038 0x00000000>, - /* Reg: pinmux_uart0_usefpga */ - <0x0000003c 0x00000000>, - /* Reg: pinmux_uart1_usefpga */ - <0x00000040 0x00000000>; - }; - }; - - i_noc: noc@0xffd10000 { - u-boot,dm-pre-reloc; - compatible = "altr,socfpga-a10-noc"; - reg = <0xffd10000 0x00008000>; - reg-names = "mpu_m0"; - - firewall { - u-boot,dm-pre-reloc; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * mpuregion0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * mpuregion0addr.limit - */ - altr,mpu0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. - * hpsregion0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. - * hpsregion0addr.limit - */ - altr,l3-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * fpga2sdram0region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * fpga2sdram0region0addr.limit - */ - altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * fpga2sdram1region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * fpga2sdram1region0addr.limit - */ - altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>; - /* - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * fpga2sdram2region0addr.base - * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. - * I_NOC.mpu_m0. - * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. - * fpga2sdram2region0addr.limit - */ - altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>; - }; + fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit + */ + fpga2sdram2-0 = <0x00000000 0x0000ffff>; }; + }; - hps_fpgabridge0: fpgabridge@0 { - compatible = "altr,socfpga-hps2fpga-bridge"; - altr,init-val = <1>; - }; + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + init-val = <1>; + }; - hps_fpgabridge1: fpgabridge@1 { - compatible = "altr,socfpga-lwhps2fpga-bridge"; - altr,init-val = <1>; - }; + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + init-val = <1>; + }; - hps_fpgabridge2: fpgabridge@2 { - compatible = "altr,socfpga-fpga2hps-bridge"; - altr,init-val = <1>; - }; + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + init-val = <1>; + }; - hps_fpgabridge3: fpgabridge@3 { - compatible = "altr,socfpga-fpga2sdram0-bridge"; - altr,init-val = <1>; - }; + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + init-val = <1>; + }; - hps_fpgabridge4: fpgabridge@4 { - compatible = "altr,socfpga-fpga2sdram1-bridge"; - altr,init-val = <0>; - }; + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + init-val = <0>; + }; - hps_fpgabridge5: fpgabridge@5 { - compatible = "altr,socfpga-fpga2sdram2-bridge"; - altr,init-val = <1>; - }; + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + init-val = <1>; }; }; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index db8eb7ce7a..ccd3f32301 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -80,6 +80,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges = <0 0 0 0xffffffff>; + u-boot,dm-pre-reloc; clkmgr@ffd1000 { compatible = "altr,clk-mgr"; @@ -92,7 +93,7 @@ interrupts = <0 90 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth"; status = "disabled"; }; @@ -103,7 +104,7 @@ interrupts = <0 91 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth"; status = "disabled"; }; @@ -114,7 +115,7 @@ interrupts = <0 92 4>; interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth"; status = "disabled"; }; @@ -136,6 +137,7 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 110 4>; + bank-name = "porta"; }; }; @@ -156,6 +158,7 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 111 4>; + bank-name = "portb"; }; }; @@ -166,6 +169,7 @@ reg = <0xffc02800 0x100>; interrupts = <0 103 4>; resets = <&rst I2C0_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -176,6 +180,7 @@ reg = <0xffc02900 0x100>; interrupts = <0 104 4>; resets = <&rst I2C1_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -186,6 +191,7 @@ reg = <0xffc02a00 0x100>; interrupts = <0 105 4>; resets = <&rst I2C2_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -196,6 +202,7 @@ reg = <0xffc02b00 0x100>; interrupts = <0 106 4>; resets = <&rst I2C3_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -206,6 +213,7 @@ reg = <0xffc02c00 0x100>; interrupts = <0 107 4>; resets = <&rst I2C4_RESET>; + reset-names = "i2c"; status = "disabled"; }; @@ -216,8 +224,8 @@ reg = <0xff808000 0x1000>; interrupts = <0 96 4>; fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; + u-boot,dm-pre-reloc; status = "disabled"; }; @@ -231,6 +239,7 @@ compatible = "altr,rst-mgr"; reg = <0xffd11000 0x1000>; altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; }; spi0: spi@ffda4000 { @@ -304,6 +313,8 @@ reg-shift = <2>; reg-io-width = <4>; resets = <&rst UART0_RESET>; + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; status = "disabled"; }; @@ -350,6 +361,7 @@ reg = <0xffd00200 0x100>; interrupts = <0 117 4>; resets = <&rst WATCHDOG0_RESET>; + u-boot,dm-pre-reloc; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index d5f43a23e7..c6ab0ae992 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -78,8 +78,11 @@ &mmc { status = "okay"; cap-sd-highspeed; + cap-mmc-highspeed; broken-cd; bus-width = <4>; + drvsel = <3>; + smplsel = <0>; }; &uart0 { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index afc38d5da9..b8fc81b20c 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,35 +1,5 @@ if ARCH_SOCFPGA -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - default y if DM_MMC - -config SPL_NAND_SUPPORT - default y if SPL_NAND_DENALI - -config SPL_SERIAL_SUPPORT - default y - -config SPL_SPI_FLASH_SUPPORT - default y if SPL_SPI_SUPPORT - -config SPL_SPI_SUPPORT - default y if DM_SPI - -config SPL_WATCHDOG_SUPPORT - default y - -config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE - default y - config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 @@ -40,6 +10,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool select SPL_BOARD_INIT if SPL + select ALTERA_SDRAM config TARGET_SOCFPGA_CYCLONE5 bool diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 89b4fdf0f7..61f5778de5 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -28,6 +28,13 @@ obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o endif +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += clock_manager_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_pll_config_s10.o +endif ifdef CONFIG_SPL_BUILD obj-y += spl.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index c23ac4ead3..189e12a668 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,7 +7,10 @@ #include #include +#include #include +#include +#include #include #include @@ -25,6 +28,21 @@ int board_init(void) /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); +#endif + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + return 0; } diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index bc2c0f8854..59ede59b59 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -20,7 +20,7 @@ void cm_wait_for_lock(u32 mask) do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else inter_val = readl(&clock_manager_base->stat) & mask; #endif /* Wait for stable lock */ @@ -51,7 +51,7 @@ int set_cpu_clk_info(void) #if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else gd->bd->bi_ddr_freq = 0; #endif diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 4ee6a82b5f..defa2f6261 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -9,6 +9,9 @@ #include #include +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + static u32 eosc1_hz; static u32 cb_intosc_hz; static u32 f2s_free_hz; @@ -64,89 +67,150 @@ struct perpll_cfg { u32 cntr8clk_cnt; u32 cntr8clk_src; u32 cntr9clk_cnt; + u32 cntr9clk_src; u32 emacctl_emac0sel; u32 emacctl_emac1sel; u32 emacctl_emac2sel; u32 gpiodiv_gpiodbclk; }; -struct alteragrp_cfg { - u32 nocclk; - u32 mpuclk; +struct strtou32 { + const char *str; + const u32 val; }; -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; +static const struct strtou32 mainpll_cfg_tab[] = { + { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) }, + { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) }, + { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) }, + { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) }, + { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) }, + { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) }, + { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) }, + { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) }, + { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) }, + { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) }, + { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) }, + { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) }, + { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) }, + { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) }, + { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) }, + { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) }, + { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) }, + { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) }, + { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) }, + { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) }, + { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) }, + { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) }, + { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) }, + { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) }, +}; + +static const struct strtou32 perpll_cfg_tab[] = { + { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) }, + { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) }, + { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) }, + { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) }, + { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) }, + { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) }, + { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) }, + { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) }, + { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) }, + { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) }, + { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) }, + { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) }, + { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) }, + { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) }, + { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) }, + { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) }, + { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) }, + { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) }, + { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) }, + { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) }, + { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) }, +}; + +static const struct strtou32 alteragrp_cfg_tab[] = { + { "nocclk", offsetof(struct mainpll_cfg, nocclk) }, + { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) }, +}; + +struct strtopu32 { + const char *str; + u32 *p; +}; + +const struct strtopu32 dt_to_val[] = { + { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz}, + { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz}, + { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz}, +}; -static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg) +static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, + int cfg_tab_len, void *cfg) { - if (fdtdec_get_int_array(blob, node, "altr,of_reg_value", - (u32 *)cfg, cfg_len)) { - /* could not find required property */ - return -EINVAL; + int i; + u32 val; + + for (i = 0; i < cfg_tab_len; i++) { + if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) { + /* could not find required property */ + return -EINVAL; + } + *(u32 *)(cfg + cfg_tab[i].val) = val; } return 0; } -static int of_get_input_clks(const void *blob, int node, u32 *val) +static void of_get_input_clks(const void *blob) { - *val = fdtdec_get_uint(blob, node, "clock-frequency", 0); - if (!*val) - return -EINVAL; + int node, i; - return 0; + for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { + node = fdt_path_offset(blob, dt_to_val[i].str); + + if (node < 0) + continue; + + fdtdec_get_int_array(blob, node, "clock-frequency", + dt_to_val[i].p, 1); + } } static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, - struct perpll_cfg *per_cfg, - struct alteragrp_cfg *altrgrp_cfg) + struct perpll_cfg *per_cfg) { int node, child, len; const char *node_name; - node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK); + of_get_input_clks(blob); + + node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); + if (node < 0) return -EINVAL; child = fdt_first_subnode(blob, node); - if (child < 0) - return -EINVAL; - child = fdt_first_subnode(blob, child); if (child < 0) return -EINVAL; node_name = fdt_get_name(blob, child, &len); while (node_name) { - if (!strcmp(node_name, "osc1")) { - if (of_get_input_clks(blob, child, &eosc1_hz)) + if (!strcmp(node_name, "mainpll")) { + if (of_to_struct(blob, child, mainpll_cfg_tab, + ARRAY_SIZE(mainpll_cfg_tab), main_cfg)) return -EINVAL; - } else if (!strcmp(node_name, "cb_intosc_ls_clk")) { - if (of_get_input_clks(blob, child, &cb_intosc_hz)) + } else if (!strcmp(node_name, "perpll")) { + if (of_to_struct(blob, child, perpll_cfg_tab, + ARRAY_SIZE(perpll_cfg_tab), per_cfg)) return -EINVAL; - } else if (!strcmp(node_name, "f2s_free_clk")) { - if (of_get_input_clks(blob, child, &f2s_free_hz)) + } else if (!strcmp(node_name, "alteragrp")) { + if (of_to_struct(blob, child, alteragrp_cfg_tab, + ARRAY_SIZE(alteragrp_cfg_tab), main_cfg)) return -EINVAL; - } else if (!strcmp(node_name, "main_pll")) { - if (of_to_struct(blob, child, - sizeof(*main_cfg)/sizeof(u32), - main_cfg)) - return -EINVAL; - } else if (!strcmp(node_name, "periph_pll")) { - if (of_to_struct(blob, child, - sizeof(*per_cfg)/sizeof(u32), - per_cfg)) - return -EINVAL; - } else if (!strcmp(node_name, "altera")) { - if (of_to_struct(blob, child, - sizeof(*altrgrp_cfg)/sizeof(u32), - altrgrp_cfg)) - return -EINVAL; - - main_cfg->mpuclk = altrgrp_cfg->mpuclk; - main_cfg->nocclk = altrgrp_cfg->nocclk; } child = fdt_next_subnode(blob, child); @@ -878,15 +942,13 @@ int cm_basic_init(const void *blob) { struct mainpll_cfg main_cfg; struct perpll_cfg per_cfg; - struct alteragrp_cfg altrgrp_cfg; int rval; /* initialize to zero for use case of optional node */ memset(&main_cfg, 0, sizeof(main_cfg)); memset(&per_cfg, 0, sizeof(per_cfg)); - memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg)); - rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg); + rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg); if (rval) return rval; diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c new file mode 100644 index 0000000000..3ba2a00c02 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void cm_write_bypass_mainpll(u32 val) +{ + writel(val, &clock_manager_base->main_pll.bypass); + cm_wait_for_fsm(); +} + +static void cm_write_bypass_perpll(u32 val) +{ + writel(val, &clock_manager_base->per_pll.bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void cm_write_ctrl(u32 val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + */ +void cm_basic_init(const struct cm_config * const cfg) +{ + u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; + + if (cfg == 0) + return; + + /* Put all plls in bypass */ + cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL); + cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL); + + /* setup main PLL dividers where calculate the vcocalib value */ + mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & + CLKMGR_FDBCK_MDIV_MASK; + refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - + CLKMGR_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << + CLKMGR_VCOCALIB_MSCNT_OFFSET); + + writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & + ~CLKMGR_PLLGLOB_RST_MASK), + &clock_manager_base->main_pll.pllglob); + writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck); + writel(vcocalib, &clock_manager_base->main_pll.vcocalib); + writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0); + writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); + writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv); + + /* setup peripheral PLL dividers */ + /* calculate the vcocalib value */ + mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & + CLKMGR_FDBCK_MDIV_MASK; + refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; + hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - + CLKMGR_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << + CLKMGR_VCOCALIB_MSCNT_OFFSET); + + writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & + ~CLKMGR_PLLGLOB_RST_MASK), + &clock_manager_base->per_pll.pllglob); + writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck); + writel(vcocalib, &clock_manager_base->per_pll.vcocalib); + writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0); + writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); + writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl); + writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv); + + /* Take both PLL out of reset and power up */ + setbits_le32(&clock_manager_base->main_pll.pllglob, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + setbits_le32(&clock_manager_base->per_pll.pllglob, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + +#define LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | \ + CLKMGR_STAT_PERPLL_LOCKED) + + cm_wait_for_lock(LOCKED_MASK); + + /* + * Dividers for C2 to C9 only init after PLLs are lock. As dividers + * only take effect upon value change, we shall set a maximum value as + * default value. + */ + writel(0xff, &clock_manager_base->main_pll.mpuclk); + writel(0xff, &clock_manager_base->main_pll.nocclk); + writel(0xff, &clock_manager_base->main_pll.cntr2clk); + writel(0xff, &clock_manager_base->main_pll.cntr3clk); + writel(0xff, &clock_manager_base->main_pll.cntr4clk); + writel(0xff, &clock_manager_base->main_pll.cntr5clk); + writel(0xff, &clock_manager_base->main_pll.cntr6clk); + writel(0xff, &clock_manager_base->main_pll.cntr7clk); + writel(0xff, &clock_manager_base->main_pll.cntr8clk); + writel(0xff, &clock_manager_base->main_pll.cntr9clk); + writel(0xff, &clock_manager_base->per_pll.cntr2clk); + writel(0xff, &clock_manager_base->per_pll.cntr3clk); + writel(0xff, &clock_manager_base->per_pll.cntr4clk); + writel(0xff, &clock_manager_base->per_pll.cntr5clk); + writel(0xff, &clock_manager_base->per_pll.cntr6clk); + writel(0xff, &clock_manager_base->per_pll.cntr7clk); + writel(0xff, &clock_manager_base->per_pll.cntr8clk); + writel(0xff, &clock_manager_base->per_pll.cntr9clk); + + writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); + writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk); + writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk); + writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk); + writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk); + writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk); + writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk); + writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk); + writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk); + writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk); + writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk); + writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk); + writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk); + writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk); + writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk); + writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk); + writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk); + writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk); + + /* Take all PLLs out of bypass */ + cm_write_bypass_mainpll(0); + cm_write_bypass_perpll(0); + + /* clear safe mode / out of boot mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) + & ~(CLKMGR_CTRL_SAFEMODE)); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll.en); + writel(~0, &clock_manager_base->per_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->intrclr); +} + +static unsigned long cm_get_main_vco_clk_hz(void) +{ + unsigned long fref, refdiv, mdiv, reg, vco; + + reg = readl(&clock_manager_base->main_pll.pllglob); + + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK; + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + + reg = readl(&clock_manager_base->main_pll.fdbck); + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; + + vco = fref / refdiv; + vco = vco * (CLKMGR_MDIV_CONST + mdiv); + return vco; +} + +static unsigned long cm_get_per_vco_clk_hz(void) +{ + unsigned long fref, refdiv, mdiv, reg, vco; + + reg = readl(&clock_manager_base->per_pll.pllglob); + + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK; + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & + CLKMGR_PLLGLOB_REFCLKDIV_MASK; + + reg = readl(&clock_manager_base->per_pll.fdbck); + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK; + + vco = fref / refdiv; + vco = vco * (CLKMGR_MDIV_CONST + mdiv); + return vco; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); + + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_main_vco_clk_hz(); + clock /= (readl(&clock_manager_base->main_pll.pllc0) & + CLKMGR_PLLC0_DIV_MASK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_per_vco_clk_hz(); + clock /= (readl(&clock_manager_base->per_pll.pllc0) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & + CLKMGR_CLKCNT_MSK); + return clock; +} + +unsigned int cm_get_l3_main_clk_hz(void) +{ + u32 clock = readl(&clock_manager_base->main_pll.nocclk); + + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_main_vco_clk_hz(); + clock /= (readl(&clock_manager_base->main_pll.pllc1) & + CLKMGR_PLLC0_DIV_MASK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_per_vco_clk_hz(); + clock /= (readl(&clock_manager_base->per_pll.pllc1) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) & + CLKMGR_CLKCNT_MSK); + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + u32 clock = readl(&clock_manager_base->per_pll.cntr6clk); + + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = cm_get_l3_main_clk_hz(); + clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = cm_get_l3_main_clk_hz(); + clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + return clock / 4; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + u32 clock = cm_get_l3_main_clk_hz(); + + clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK)); + return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + return readl(&sysmgr_regs->boot_scratch_cold0); +} + +unsigned int cm_get_spi_controller_clk_hz(void) +{ + u32 clock = cm_get_l3_main_clk_hz(); + + clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >> + CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK)); + return clock; +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_l3_main_clk_hz() / 4; +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000)); + printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000); + printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000)); + printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000)); + printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000); + printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000); +} diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index 2c6e412f61..1f549d7e70 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -6,9 +6,11 @@ #ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ #define _SOCFPGA_S10_BASE_HARDWARE_H_ +#define SOCFPGA_CCU_ADDRESS 0xf7000000 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 @@ -17,12 +19,21 @@ #define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 #define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 #define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400 +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500 #define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 #define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 #define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000 +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100 +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 +#define SOCFPGA_FIREWALL_TCU 0xffd21400 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 3ace040d15..dd80e3a767 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -16,6 +16,8 @@ void cm_print_clock_quick_summary(void); #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include #endif #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index a3289ee2da..cb2306e5bc 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -107,7 +107,7 @@ unsigned int cm_get_spi_controller_clk_hz(void); #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144 -#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ +#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK) /* value */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file mode 100644 index 0000000000..24b20de011 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#ifndef _CLOCK_MANAGER_S10_ +#define _CLOCK_MANAGER_S10_ + +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void); + +#define CLKMGR_EOSC1_HZ 25000000 +#define CLKMGR_INTOSC_HZ 460000000 +#define CLKMGR_FPGA_CLK_HZ 50000000 + +/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void); + +struct cm_config { + /* main group */ + u32 main_pll_mpuclk; + u32 main_pll_nocclk; + u32 main_pll_cntr2clk; + u32 main_pll_cntr3clk; + u32 main_pll_cntr4clk; + u32 main_pll_cntr5clk; + u32 main_pll_cntr6clk; + u32 main_pll_cntr7clk; + u32 main_pll_cntr8clk; + u32 main_pll_cntr9clk; + u32 main_pll_nocdiv; + u32 main_pll_pllglob; + u32 main_pll_fdbck; + u32 main_pll_pllc0; + u32 main_pll_pllc1; + u32 spare; + + /* peripheral group */ + u32 per_pll_cntr2clk; + u32 per_pll_cntr3clk; + u32 per_pll_cntr4clk; + u32 per_pll_cntr5clk; + u32 per_pll_cntr6clk; + u32 per_pll_cntr7clk; + u32 per_pll_cntr8clk; + u32 per_pll_cntr9clk; + u32 per_pll_emacctl; + u32 per_pll_gpiodiv; + u32 per_pll_pllglob; + u32 per_pll_fdbck; + u32 per_pll_pllc0; + u32 per_pll_pllc1; + + /* incoming clock */ + u32 hps_osc_clk_hz; + u32 fpga_clk_hz; +}; + +void cm_basic_init(const struct cm_config * const cfg); + +struct socfpga_clock_manager_main_pll { + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 mpuclk; + u32 nocclk; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 nocdiv; + u32 pllglob; + u32 fdbck; + u32 mem; + u32 memstat; + u32 pllc0; + u32 pllc1; + u32 vcocalib; + u32 _pad_0x90_0xA0[5]; +}; + +struct socfpga_clock_manager_per_pll { + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 emacctl; + u32 gpiodiv; + u32 pllglob; + u32 fdbck; + u32 mem; + u32 memstat; + u32 pllc0; + u32 pllc1; + u32 vcocalib; + u32 _pad_0x100_0x124[10]; +}; + +struct socfpga_clock_manager { + u32 ctrl; + u32 stat; + u32 testioctrl; + u32 intrgen; + u32 intrmsk; + u32 intrclr; + u32 intrsts; + u32 intrstk; + u32 intrraw; + u32 _pad_0x24_0x2c[3]; + struct socfpga_clock_manager_main_pll main_pll; + struct socfpga_clock_manager_per_pll per_pll; +}; + +#define CLKMGR_CTRL_SAFEMODE BIT(0) +#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 +#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 +#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(9) + +#define CLKMGR_PLLGLOB_PD_MASK 0x00000001 +#define CLKMGR_PLLGLOB_RST_MASK 0x00000002 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3 +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 + +#define CLKMGR_CLKSRC_MASK 0x7 +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK 0x7ff + +#define CLKMGR_FDBCK_MDIV_MASK 0xff +#define CLKMGR_FDBCK_MDIV_OFFSET 24 + +#define CLKMGR_PLLC0_DIV_MASK 0xff +#define CLKMGR_PLLC1_DIV_MASK 0xff +#define CLKMGR_PLLC0_EN_OFFSET 27 +#define CLKMGR_PLLC1_EN_OFFSET 24 + +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 + +#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3 +#define CLKMGR_NOCDIV_DIV1 0 +#define CLKMGR_NOCDIV_DIV2 1 +#define CLKMGR_NOCDIV_DIV4 2 +#define CLKMGR_NOCDIV_DIV8 3 +#define CLKMGR_CSPDBGCLK_DIV1 0 +#define CLKMGR_CSPDBGCLK_DIV4 1 + +#define CLKMGR_MSCNT_CONST 200 +#define CLKMGR_MDIV_CONST 6 +#define CLKMGR_HSCNT_CONST 9 + +#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9 +#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff + +#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26 +#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27 +#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28 + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 + +#endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h new file mode 100644 index 0000000000..ba0f1fd1b2 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#ifndef _HANDOFF_S10_H_ +#define _HANDOFF_S10_H_ + +/* + * Offset for HW handoff from Quartus tools + */ +#define S10_HANDOFF_BASE 0xFFE3F000 +#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10) +#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0) +#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330) +#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0) +#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580) +#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610) +#define S10_HANDOFF_MAGIC_MUX 0x504D5558 +#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354 +#define S10_HANDOFF_MAGIC_FPGA 0x46504741 +#define S10_HANDOFF_MAGIC_DELAY 0x444C4159 +#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define S10_HANDOFF_MAGIC_MISC 0x4D495343 +#define S10_HANDOFF_OFFSET_LENGTH 0x4 +#define S10_HANDOFF_OFFSET_DATA 0x10 + +#define S10_HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) +#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) + +#define S10_HANDOFF_SIZE 4096 + +#endif /* _HANDOFF_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 7cfed7d001..d9e0b33c60 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -10,12 +10,10 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, + const u8 phymode)); -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 -#else #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 -#endif /* * Define a reset identifier, from which a permodrst bank ID @@ -44,6 +42,8 @@ void socfpga_per_reset_all(void); #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include #endif #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h new file mode 100644 index 0000000000..6182d5fa3f --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#ifndef _RESET_MANAGER_S10_ +#define _RESET_MANAGER_S10_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +void socfpga_bridges_reset(int enable); + +void socfpga_per_reset(u32 reset, int set); +void socfpga_per_reset_all(void); + +struct socfpga_reset_manager { + u32 status; + u32 mpu_rst_stat; + u32 misc_stat; + u32 padding1; + u32 hdsk_en; + u32 hdsk_req; + u32 hdsk_ack; + u32 hdsk_stall; + u32 mpumodrst; + u32 per0modrst; + u32 per1modrst; + u32 brgmodrst; + u32 padding2; + u32 cold_mod_reset; + u32 padding3; + u32 dbg_mod_reset; + u32 tap_mod_reset; + u32 padding4; + u32 padding5; + u32 brg_warm_mask; + u32 padding6[3]; + u32 tst_stat; + u32 padding7; + u32 hdsk_timeout; + u32 mpul2flushtimeout; + u32 dbghdsktimeout; +}; + +#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 + +/* + * Define a reset identifier, from which a permodrst bank ID + * and reset ID can be extracted using the subsequent macros + * RSTMGR_RESET() and RSTMGR_BANK(). + */ +#define RSTMGR_BANK_OFFSET 8 +#define RSTMGR_BANK_MASK 0x7 +#define RSTMGR_RESET_OFFSET 0 +#define RSTMGR_RESET_MASK 0x1f +#define RSTMGR_DEFINE(_bank, _offset) \ + ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) + +/* Extract reset ID from the reset identifier. */ +#define RSTMGR_RESET(_reset) \ + (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) + +/* Extract bank ID from the reset identifier. */ +#define RSTMGR_BANK(_reset) \ + (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) + +/* + * SocFPGA Stratix10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) +#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) +#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) +#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) +#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) +#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) +#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) +#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) +#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) +#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) +#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) +#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) +#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) +#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) +#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) +#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) +#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) +#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) +#define RSTMGR_SDR RSTMGR_DEFINE(3, 6) + +void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state); + +/* Create a human-readable reference to SoCFPGA reset. */ +#define SOCFPGA_RESET(_name) RSTMGR_##_name + +#endif /* _RESET_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/scu.h b/arch/arm/mach-socfpga/include/mach/scu.h index 27224b1a87..b684a55019 100644 --- a/arch/arm/mach-socfpga/include/mach/scu.h +++ b/arch/arm/mach-socfpga/include/mach/scu.h @@ -14,8 +14,8 @@ struct scu_registers { u32 _pad_0x10_0x3c[12]; /* 0x10 */ u32 fsar; /* 0x40 */ u32 fear; - u32 _pad_0x48_0x50[2]; - u32 acr; /* 0x54 */ + u32 _pad_0x48_0x4c[2]; + u32 acr; /* 0x50 */ u32 sacr; }; diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index a58872c3d9..79cb9e6064 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -7,435 +7,11 @@ #ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size(void); -int sdram_mmr_init_full(unsigned int sdr_phy_reg); -int sdram_calibration_full(void); - -const struct socfpga_sdram_config *socfpga_get_sdram_config(void); - -void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); -void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); -const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); -const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void); -const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void); - -#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) - -struct socfpga_sdr_ctrl { - u32 ctrl_cfg; - u32 dram_timing1; - u32 dram_timing2; - u32 dram_timing3; - u32 dram_timing4; /* 0x10 */ - u32 lowpwr_timing; - u32 dram_odt; - u32 extratime1; - u32 __padding0[3]; - u32 dram_addrw; /* 0x2c */ - u32 dram_if_width; /* 0x30 */ - u32 dram_dev_width; - u32 dram_sts; - u32 dram_intr; - u32 sbe_count; /* 0x40 */ - u32 dbe_count; - u32 err_addr; - u32 drop_count; - u32 drop_addr; /* 0x50 */ - u32 lowpwr_eq; - u32 lowpwr_ack; - u32 static_cfg; - u32 ctrl_width; /* 0x60 */ - u32 cport_width; - u32 cport_wmap; - u32 cport_rmap; - u32 rfifo_cmap; /* 0x70 */ - u32 wfifo_cmap; - u32 cport_rdwr; - u32 port_cfg; - u32 fpgaport_rst; /* 0x80 */ - u32 __padding1; - u32 fifo_cfg; - u32 protport_default; - u32 prot_rule_addr; /* 0x90 */ - u32 prot_rule_id; - u32 prot_rule_data; - u32 prot_rule_rdwr; - u32 __padding2[3]; - u32 mp_priority; /* 0xac */ - u32 mp_weight0; /* 0xb0 */ - u32 mp_weight1; - u32 mp_weight2; - u32 mp_weight3; - u32 mp_pacing0; /* 0xc0 */ - u32 mp_pacing1; - u32 mp_pacing2; - u32 mp_pacing3; - u32 mp_threshold0; /* 0xd0 */ - u32 mp_threshold1; - u32 mp_threshold2; - u32 __padding3[29]; - u32 phy_ctrl0; /* 0x150 */ - u32 phy_ctrl1; - u32 phy_ctrl2; -}; - -/* SDRAM configuration structure for the SPL. */ -struct socfpga_sdram_config { - u32 ctrl_cfg; - u32 dram_timing1; - u32 dram_timing2; - u32 dram_timing3; - u32 dram_timing4; - u32 lowpwr_timing; - u32 dram_odt; - u32 extratime1; - u32 dram_addrw; - u32 dram_if_width; - u32 dram_dev_width; - u32 dram_intr; - u32 lowpwr_eq; - u32 static_cfg; - u32 ctrl_width; - u32 cport_width; - u32 cport_wmap; - u32 cport_rmap; - u32 rfifo_cmap; - u32 wfifo_cmap; - u32 cport_rdwr; - u32 port_cfg; - u32 fpgaport_rst; - u32 fifo_cfg; - u32 mp_priority; - u32 mp_weight0; - u32 mp_weight1; - u32 mp_weight2; - u32 mp_weight3; - u32 mp_pacing0; - u32 mp_pacing1; - u32 mp_pacing2; - u32 mp_pacing3; - u32 mp_threshold0; - u32 mp_threshold1; - u32 mp_threshold2; - u32 phy_ctrl0; -}; - -struct socfpga_sdram_rw_mgr_config { - u8 activate_0_and_1; - u8 activate_0_and_1_wait1; - u8 activate_0_and_1_wait2; - u8 activate_1; - u8 clear_dqs_enable; - u8 guaranteed_read; - u8 guaranteed_read_cont; - u8 guaranteed_write; - u8 guaranteed_write_wait0; - u8 guaranteed_write_wait1; - u8 guaranteed_write_wait2; - u8 guaranteed_write_wait3; - u8 idle; - u8 idle_loop1; - u8 idle_loop2; - u8 init_reset_0_cke_0; - u8 init_reset_1_cke_0; - u8 lfsr_wr_rd_bank_0; - u8 lfsr_wr_rd_bank_0_data; - u8 lfsr_wr_rd_bank_0_dqs; - u8 lfsr_wr_rd_bank_0_nop; - u8 lfsr_wr_rd_bank_0_wait; - u8 lfsr_wr_rd_bank_0_wl_1; - u8 lfsr_wr_rd_dm_bank_0; - u8 lfsr_wr_rd_dm_bank_0_data; - u8 lfsr_wr_rd_dm_bank_0_dqs; - u8 lfsr_wr_rd_dm_bank_0_nop; - u8 lfsr_wr_rd_dm_bank_0_wait; - u8 lfsr_wr_rd_dm_bank_0_wl_1; - u8 mrs0_dll_reset; - u8 mrs0_dll_reset_mirr; - u8 mrs0_user; - u8 mrs0_user_mirr; - u8 mrs1; - u8 mrs1_mirr; - u8 mrs2; - u8 mrs2_mirr; - u8 mrs3; - u8 mrs3_mirr; - u8 precharge_all; - u8 read_b2b; - u8 read_b2b_wait1; - u8 read_b2b_wait2; - u8 refresh_all; - u8 rreturn; - u8 sgle_read; - u8 zqcl; - - u8 true_mem_data_mask_width; - u8 mem_address_mirroring; - u8 mem_data_mask_width; - u8 mem_data_width; - u8 mem_dq_per_read_dqs; - u8 mem_dq_per_write_dqs; - u8 mem_if_read_dqs_width; - u8 mem_if_write_dqs_width; - u8 mem_number_of_cs_per_dimm; - u8 mem_number_of_ranks; - u8 mem_virtual_groups_per_read_dqs; - u8 mem_virtual_groups_per_write_dqs; -}; - -struct socfpga_sdram_io_config { - u16 delay_per_opa_tap; - u8 delay_per_dchain_tap; - u8 delay_per_dqs_en_dchain_tap; - u8 dll_chain_length; - u8 dqdqs_out_phase_max; - u8 dqs_en_delay_max; - u8 dqs_en_delay_offset; - u8 dqs_en_phase_max; - u8 dqs_in_delay_max; - u8 dqs_in_reserve; - u8 dqs_out_reserve; - u8 io_in_delay_max; - u8 io_out1_delay_max; - u8 io_out2_delay_max; - u8 shift_dqs_en_when_shift_dqs; -}; - -struct socfpga_sdram_misc_config { - u32 reg_file_init_seq_signature; - u8 afi_rate_ratio; - u8 calib_lfifo_offset; - u8 calib_vfifo_offset; - u8 enable_super_quick_calibration; - u8 max_latency_count_width; - u8 read_valid_fifo_size; - u8 tinit_cntr0_val; - u8 tinit_cntr1_val; - u8 tinit_cntr2_val; - u8 treset_cntr0_val; - u8 treset_cntr1_val; - u8 treset_cntr2_val; -}; - -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 -/* Register template: sdr::ctrlgrp::dramtiming1 */ -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming2 */ -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff -/* Register template: sdr::ctrlgrp::dramtiming3 */ -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming4 */ -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::lowpwrtiming */ -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff -/* Register template: sdr::ctrlgrp::dramaddrw */ -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f -/* Register template: sdr::ctrlgrp::dramifwidth */ -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::dramdevwidth */ -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramintr */ -#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 -#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 -/* Register template: sdr::ctrlgrp::staticcfg */ -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 -#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 -#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::ctrlwidth */ -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::cportwidth */ -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::cportwmap */ -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::cportrmap */ -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::rfifocmap */ -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::wfifocmap */ -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::cportrdwr */ -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::portcfg */ -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::fifocfg */ -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::mppriority */ -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ -0x0000ffff -/* Register template: sdr::ctrlgrp::remappriority */ -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ - (((x) << 10) & 0x00000c00) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ - (((x) << 6) & 0x000000c0) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ - (((x) << 8) & 0x00000100) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ - (((x) << 9) & 0x00000200) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ - (((x) << 4) & 0x00000030) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ - (((x) << 2) & 0x0000000c) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ - (((x) << 0) & 0x00000003) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::dramodt */ -#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 -#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 -#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 -#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f -/* Field instance: sdr::ctrlgrp::dramsts */ -#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 -#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 -/* Register template: sdr::ctrlgrp::extratime1 */ -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 - -/* SDRAM width macro for configuration with ECC */ -#define SDRAM_WIDTH_32BIT_WITH_ECC 40 -#define SDRAM_WIDTH_16BIT_WITH_ECC 24 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include +#endif #endif #endif /* _SDRAM_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h index 8ae8d1bc96..25b82fb285 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h @@ -7,6 +7,7 @@ #define _SOCFPGA_SDRAM_ARRIA10_H_ #ifndef __ASSEMBLY__ +int ddr_calibration_sequence(void); struct socfpga_ecc_hmc { u32 ip_rev_id; @@ -203,6 +204,7 @@ struct socfpga_io48_mmr { u32 niosreserve1; u32 niosreserve2; }; + #endif /*__ASSEMBLY__*/ #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000 diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h new file mode 100644 index 0000000000..b16d77668f --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h @@ -0,0 +1,442 @@ +/* + * Copyright Altera Corporation (C) 2014-2015 + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SOCFPGA_SDRAM_GEN5_H_ +#define _SOCFPGA_SDRAM_GEN5_H_ + +#ifndef __ASSEMBLY__ + +unsigned long sdram_calculate_size(void); +int sdram_mmr_init_full(unsigned int sdr_phy_reg); +int sdram_calibration_full(void); + +const struct socfpga_sdram_config *socfpga_get_sdram_config(void); + +void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); +void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); +const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); +const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void); +const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void); + +#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) + +struct socfpga_sdr_ctrl { + u32 ctrl_cfg; + u32 dram_timing1; + u32 dram_timing2; + u32 dram_timing3; + u32 dram_timing4; /* 0x10 */ + u32 lowpwr_timing; + u32 dram_odt; + u32 extratime1; + u32 __padding0[3]; + u32 dram_addrw; /* 0x2c */ + u32 dram_if_width; /* 0x30 */ + u32 dram_dev_width; + u32 dram_sts; + u32 dram_intr; + u32 sbe_count; /* 0x40 */ + u32 dbe_count; + u32 err_addr; + u32 drop_count; + u32 drop_addr; /* 0x50 */ + u32 lowpwr_eq; + u32 lowpwr_ack; + u32 static_cfg; + u32 ctrl_width; /* 0x60 */ + u32 cport_width; + u32 cport_wmap; + u32 cport_rmap; + u32 rfifo_cmap; /* 0x70 */ + u32 wfifo_cmap; + u32 cport_rdwr; + u32 port_cfg; + u32 fpgaport_rst; /* 0x80 */ + u32 __padding1; + u32 fifo_cfg; + u32 protport_default; + u32 prot_rule_addr; /* 0x90 */ + u32 prot_rule_id; + u32 prot_rule_data; + u32 prot_rule_rdwr; + u32 __padding2[3]; + u32 mp_priority; /* 0xac */ + u32 mp_weight0; /* 0xb0 */ + u32 mp_weight1; + u32 mp_weight2; + u32 mp_weight3; + u32 mp_pacing0; /* 0xc0 */ + u32 mp_pacing1; + u32 mp_pacing2; + u32 mp_pacing3; + u32 mp_threshold0; /* 0xd0 */ + u32 mp_threshold1; + u32 mp_threshold2; + u32 __padding3[29]; + u32 phy_ctrl0; /* 0x150 */ + u32 phy_ctrl1; + u32 phy_ctrl2; +}; + +/* SDRAM configuration structure for the SPL. */ +struct socfpga_sdram_config { + u32 ctrl_cfg; + u32 dram_timing1; + u32 dram_timing2; + u32 dram_timing3; + u32 dram_timing4; + u32 lowpwr_timing; + u32 dram_odt; + u32 extratime1; + u32 dram_addrw; + u32 dram_if_width; + u32 dram_dev_width; + u32 dram_intr; + u32 lowpwr_eq; + u32 static_cfg; + u32 ctrl_width; + u32 cport_width; + u32 cport_wmap; + u32 cport_rmap; + u32 rfifo_cmap; + u32 wfifo_cmap; + u32 cport_rdwr; + u32 port_cfg; + u32 fpgaport_rst; + u32 fifo_cfg; + u32 mp_priority; + u32 mp_weight0; + u32 mp_weight1; + u32 mp_weight2; + u32 mp_weight3; + u32 mp_pacing0; + u32 mp_pacing1; + u32 mp_pacing2; + u32 mp_pacing3; + u32 mp_threshold0; + u32 mp_threshold1; + u32 mp_threshold2; + u32 phy_ctrl0; +}; + +struct socfpga_sdram_rw_mgr_config { + u8 activate_0_and_1; + u8 activate_0_and_1_wait1; + u8 activate_0_and_1_wait2; + u8 activate_1; + u8 clear_dqs_enable; + u8 guaranteed_read; + u8 guaranteed_read_cont; + u8 guaranteed_write; + u8 guaranteed_write_wait0; + u8 guaranteed_write_wait1; + u8 guaranteed_write_wait2; + u8 guaranteed_write_wait3; + u8 idle; + u8 idle_loop1; + u8 idle_loop2; + u8 init_reset_0_cke_0; + u8 init_reset_1_cke_0; + u8 lfsr_wr_rd_bank_0; + u8 lfsr_wr_rd_bank_0_data; + u8 lfsr_wr_rd_bank_0_dqs; + u8 lfsr_wr_rd_bank_0_nop; + u8 lfsr_wr_rd_bank_0_wait; + u8 lfsr_wr_rd_bank_0_wl_1; + u8 lfsr_wr_rd_dm_bank_0; + u8 lfsr_wr_rd_dm_bank_0_data; + u8 lfsr_wr_rd_dm_bank_0_dqs; + u8 lfsr_wr_rd_dm_bank_0_nop; + u8 lfsr_wr_rd_dm_bank_0_wait; + u8 lfsr_wr_rd_dm_bank_0_wl_1; + u8 mrs0_dll_reset; + u8 mrs0_dll_reset_mirr; + u8 mrs0_user; + u8 mrs0_user_mirr; + u8 mrs1; + u8 mrs1_mirr; + u8 mrs2; + u8 mrs2_mirr; + u8 mrs3; + u8 mrs3_mirr; + u8 precharge_all; + u8 read_b2b; + u8 read_b2b_wait1; + u8 read_b2b_wait2; + u8 refresh_all; + u8 rreturn; + u8 sgle_read; + u8 zqcl; + + u8 true_mem_data_mask_width; + u8 mem_address_mirroring; + u8 mem_data_mask_width; + u8 mem_data_width; + u8 mem_dq_per_read_dqs; + u8 mem_dq_per_write_dqs; + u8 mem_if_read_dqs_width; + u8 mem_if_write_dqs_width; + u8 mem_number_of_cs_per_dimm; + u8 mem_number_of_ranks; + u8 mem_virtual_groups_per_read_dqs; + u8 mem_virtual_groups_per_write_dqs; +}; + +struct socfpga_sdram_io_config { + u16 delay_per_opa_tap; + u8 delay_per_dchain_tap; + u8 delay_per_dqs_en_dchain_tap; + u8 dll_chain_length; + u8 dqdqs_out_phase_max; + u8 dqs_en_delay_max; + u8 dqs_en_delay_offset; + u8 dqs_en_phase_max; + u8 dqs_in_delay_max; + u8 dqs_in_reserve; + u8 dqs_out_reserve; + u8 io_in_delay_max; + u8 io_out1_delay_max; + u8 io_out2_delay_max; + u8 shift_dqs_en_when_shift_dqs; +}; + +struct socfpga_sdram_misc_config { + u32 reg_file_init_seq_signature; + u8 afi_rate_ratio; + u8 calib_lfifo_offset; + u8 calib_vfifo_offset; + u8 enable_super_quick_calibration; + u8 max_latency_count_width; + u8 read_valid_fifo_size; + u8 tinit_cntr0_val; + u8 tinit_cntr1_val; + u8 tinit_cntr2_val; + u8 treset_cntr0_val; + u8 treset_cntr1_val; + u8 treset_cntr2_val; +}; + +#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 +#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 +#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 +#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 +#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 +#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 +#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 +#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 +#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 +#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 +#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 +#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 +#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 +#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 +#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 +#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 +#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 +#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 +/* Register template: sdr::ctrlgrp::dramtiming1 */ +#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 +#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 +#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 +#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 +#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 +#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 +#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 +#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 +#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 +#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 +#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramtiming2 */ +#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 +#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 +#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 +#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 +#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 +#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 +#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 +#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 +#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff +/* Register template: sdr::ctrlgrp::dramtiming3 */ +#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 +#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 +#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 +#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 +#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 +#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 +#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 +#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 +#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramtiming4 */ +#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 +#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 +#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 +#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 +#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 +#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::lowpwrtiming */ +#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 +#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 +#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 +#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff +/* Register template: sdr::ctrlgrp::dramaddrw */ +#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 +#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 +#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 +#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 +#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 +#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 +#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 +#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f +/* Register template: sdr::ctrlgrp::dramifwidth */ +#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 +#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff +/* Register template: sdr::ctrlgrp::dramdevwidth */ +#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 +#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f +/* Register template: sdr::ctrlgrp::dramintr */ +#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 +#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 +#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 +#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 +/* Register template: sdr::ctrlgrp::staticcfg */ +#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 +#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 +#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 +#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 +#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 +#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 +/* Register template: sdr::ctrlgrp::ctrlwidth */ +#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 +#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 +/* Register template: sdr::ctrlgrp::cportwidth */ +#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 +#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff +/* Register template: sdr::ctrlgrp::cportwmap */ +#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 +#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff +/* Register template: sdr::ctrlgrp::cportrmap */ +#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 +#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff +/* Register template: sdr::ctrlgrp::rfifocmap */ +#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 +#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff +/* Register template: sdr::ctrlgrp::wfifocmap */ +#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 +#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff +/* Register template: sdr::ctrlgrp::cportrdwr */ +#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 +#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff +/* Register template: sdr::ctrlgrp::portcfg */ +#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 +#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 +#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 +#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::fifocfg */ +#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 +#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 +#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 +#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff +/* Register template: sdr::ctrlgrp::mppriority */ +#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 +#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 +#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff +/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ +#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 +#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff +/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ +0xffffffff +/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ +0xffffffff +/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 +#define \ +SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ +0x0000ffff +/* Register template: sdr::ctrlgrp::remappriority */ +#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 +#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff +/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \ + (((x) << 12) & 0xfffff000) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \ + (((x) << 10) & 0x00000c00) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \ + (((x) << 6) & 0x000000c0) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \ + (((x) << 8) & 0x00000100) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \ + (((x) << 9) & 0x00000200) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \ + (((x) << 4) & 0x00000030) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \ + (((x) << 2) & 0x0000000c) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \ + (((x) << 0) & 0x00000003) +/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \ + (((x) << 12) & 0xfffff000) +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \ + (((x) << 0) & 0x00000fff) +/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ +#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \ + (((x) << 0) & 0x00000fff) +/* Register template: sdr::ctrlgrp::dramodt */ +#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 +#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 +#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 +#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f +/* Field instance: sdr::ctrlgrp::dramsts */ +#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 +#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 +/* Register template: sdr::ctrlgrp::extratime1 */ +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 +#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 + +/* SDRAM width macro for configuration with ECC */ +#define SDRAM_WIDTH_32BIT_WITH_ECC 40 +#define SDRAM_WIDTH_16BIT_WITH_ECC 24 + +#endif +#endif /* _SOCFPGA_SDRAM_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index fbe2a8be28..7e76df74b7 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -6,6 +6,9 @@ #ifndef _SYSTEM_MANAGER_H_ #define _SYSTEM_MANAGER_H_ +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include +#else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) #define SYSMGR_ECC_OCRAM_EN BIT(0) @@ -88,5 +91,5 @@ #define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7) - +#endif #endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h new file mode 100644 index 0000000000..813dff2153 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#ifndef _SYSTEM_MANAGER_S10_ +#define _SYSTEM_MANAGER_S10_ + +void sysmgr_pinmux_init(void); +void populate_sysmgr_fpgaintf_module(void); +void populate_sysmgr_pinmux(void); +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 wddbg; + u32 _pad_0xc; + u32 mpu_status; /* 0x10 */ + u32 mpu_ace; + u32 _pad_0x18_0x1c[2]; + u32 dma; /* 0x20 */ + u32 dma_periph; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x30 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usb0_l3master; + u32 usb1_l3master; + /* EMAC Group */ + u32 emac_gbl; /* 0x40 */ + u32 emac0; + u32 emac1; + u32 emac2; + u32 emac0_ace; /* 0x50 */ + u32 emac1_ace; + u32 emac2_ace; + u32 nand_axuser; + u32 _pad_0x60_0x64[2]; /* 0x60 */ + /* FPGA interface Group */ + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; /* 0x70 */ + u32 dma_l3master; + u32 etr_l3master; + u32 _pad_0x7c; + u32 sec_ctrl_slt; /* 0x80 */ + u32 osc_trim; + u32 _pad_0x88_0x8c[2]; + /* ECC Group */ + u32 ecc_intmask_value; /* 0x90 */ + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; /* 0xa0 */ + u32 _pad_0xa4_0xac[3]; + u32 noc_addr_remap; /* 0xb0 */ + u32 hmc_clk; + u32 io_pa_ctrl; + u32 _pad_0xbc; + /* NOC Group */ + u32 noc_timeout; /* 0xc0 */ + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; /* 0xd0 */ + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 fpga_config; + u32 iocsrclk_gate; /* 0xe0 */ + u32 gpo; + u32 gpi; + u32 _pad_0xec; + u32 mpu; /* 0xf0 */ + u32 sdm_hps_spare; + u32 hps_sdm_spare; + u32 _pad_0xfc_0x1fc[65]; + /* Boot scratch register group */ + u32 boot_scratch_cold0; /* 0x200 */ + u32 boot_scratch_cold1; + u32 boot_scratch_cold2; + u32 boot_scratch_cold3; + u32 boot_scratch_cold4; /* 0x210 */ + u32 boot_scratch_cold5; + u32 boot_scratch_cold6; + u32 boot_scratch_cold7; + u32 boot_scratch_cold8; /* 0x220 */ + u32 boot_scratch_cold9; + u32 _pad_0x228_0xffc[886]; + /* Pin select and pin control group */ + u32 pinsel0[40]; /* 0x1000 */ + u32 _pad_0x10a0_0x10fc[24]; + u32 pinsel40[8]; + u32 _pad_0x1120_0x112c[4]; + u32 ioctrl0[28]; + u32 _pad_0x11a0_0x11fc[24]; + u32 ioctrl28[20]; + u32 _pad_0x1250_0x12fc[44]; + /* Use FPGA mux */ + u32 rgmii0usefpga; /* 0x1300 */ + u32 rgmii1usefpga; + u32 rgmii2usefpga; + u32 i2c0usefpga; + u32 i2c1usefpga; + u32 i2c_emac0_usefpga; + u32 i2c_emac1_usefpga; + u32 i2c_emac2_usefpga; + u32 nandusefpga; + u32 _pad_0x1324; + u32 spim0usefpga; + u32 spim1usefpga; + u32 spis0usefpga; + u32 spis1usefpga; + u32 uart0usefpga; + u32 uart1usefpga; + u32 mdio0usefpga; + u32 mdio1usefpga; + u32 mdio2usefpga; + u32 _pad_0x134c; + u32 jtagusefpga; + u32 sdmmcusefpga; + u32 hps_osc_clk; + u32 _pad_0x135c_0x13fc[41]; + u32 iodelay0[40]; + u32 _pad_0x14a0_0x14fc[24]; + u32 iodelay40[8]; + +}; + +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 + +#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(8) +#define SYSMGR_FPGAINTF_SPIM0 BIT(16) +#define SYSMGR_FPGAINTF_SPIM1 BIT(24) +#define SYSMGR_FPGAINTF_EMAC0 (0x11 << 0) +#define SYSMGR_FPGAINTF_EMAC1 (0x11 << 8) +#define SYSMGR_FPGAINTF_EMAC2 (0x11 << 16) + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 + +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + +#define SYSMGR_NOC_H2F_MSK 0x00000001 +#define SYSMGR_NOC_LWH2F_MSK 0x00000010 +#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 + +#define SYSMGR_DMA_IRQ_NS 0xFF000000 +#define SYSMGR_DMA_MGR_NS 0x00010000 + +#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF + +#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F + +#endif /* _SYSTEM_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 5c27f1984e..fca86507f1 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -22,8 +22,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -52,6 +54,7 @@ void enable_caches(void) #endif } +#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -72,6 +75,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) @@ -135,3 +139,68 @@ int arch_cpu_init(void) return 0; } + +#ifdef CONFIG_ETH_DESIGNWARE +static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + +int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, + const u8 phymode)) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[2]; /* Max. two GMACs */ + int ret, count; + int i, node; + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + resetfn(args.args[0], phy_modereg); + } + + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index f909568312..47a9d50ef1 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -41,8 +41,7 @@ static struct socfpga_system_manager *sysmgr_regs = * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE -void dwmac_deassert_reset(const unsigned int of_reset_id, - const u32 phymode) +static void arria10_dwmac_reset(const u8 of_reset_id, const u8 phymode) { u32 reset; @@ -64,6 +63,20 @@ void dwmac_deassert_reset(const unsigned int of_reset_id, /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); } + +static int socfpga_eth_reset(void) +{ + /* Put all GMACs into RESET state. */ + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); + socfpga_per_reset(SOCFPGA_RESET(EMAC2), 1); + return socfpga_eth_reset_common(arria10_dwmac_reset); +}; +#else +static int socfpga_eth_reset(void) +{ + return 0; +}; #endif #if defined(CONFIG_SPL_BUILD) @@ -91,11 +104,6 @@ int arch_early_init_r(void) /* assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); - /* configuring the clock based on handoff */ - /* TODO: Add call to cm_basic_init() */ - - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); return 0; } #else @@ -251,6 +259,6 @@ int print_cpuinfo(void) #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { - return 0; + return socfpga_eth_reset(); } #endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index b9db3aef09..434373404e 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -38,8 +38,7 @@ static struct scu_registers *scu_regs = * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE -void dwmac_deassert_reset(const unsigned int of_reset_id, - const u32 phymode) +static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode) { u32 physhift, reset; @@ -63,71 +62,13 @@ void dwmac_deassert_reset(const unsigned int of_reset_id, socfpga_per_reset(reset, 0); } -static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - static int socfpga_eth_reset(void) { - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - /* Put both GMACs into RESET state. */ + /* Put all GMACs into RESET state. */ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - dwmac_deassert_reset(args.args[0], phy_modereg); - } - - return 0; -} + return socfpga_eth_reset_common(gen5_dwmac_reset); +}; #else static int socfpga_eth_reset(void) { @@ -264,12 +205,8 @@ int arch_early_init_r(void) setbits_le32(&scu_regs->sacr, 0xfff); /* Configure the L2 controller to make SDRAM start at 0 */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET - writel(0x2, &nic301_regs->remap); -#else writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ writel(0x1, &pl310->pl310_addr_filter_start); -#endif /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 1389c82169..e0a01ed07a 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -8,8 +8,16 @@ #include #include +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +#endif /* * Write the reset manager register to cause reset @@ -17,8 +25,13 @@ static const struct socfpga_reset_manager *reset_manager_base = void reset_cpu(ulong addr) { /* request a warm reset */ +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); +#else writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); +#endif /* * infinite loop here as watchdog will trigger and reset * the processor diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 99e2b8e6e6..b4434f2ded 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -316,13 +316,6 @@ void socfpga_per_reset_all(void) setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp); } -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -int socfpga_bridges_reset(void) -{ - /* For SoCFPGA-VT, this is NOP. */ - return 0; -} -#else int socfpga_bridges_reset(void) { int ret; @@ -379,4 +372,3 @@ int socfpga_bridges_reset(void) return 0; } -#endif diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index b261a94486..25baef79bc 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -69,14 +69,6 @@ void reset_deassert_peripherals_handoff(void) writel(0, &reset_manager_base->per_mod_reset); } -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -void socfpga_bridges_reset(int enable) -{ - /* For SoCFPGA-VT, this is NOP. */ - return; -} -#else - #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 @@ -110,4 +102,3 @@ void socfpga_bridges_reset(int enable) } return; } -#endif diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c new file mode 100644 index 0000000000..5cc8336740 --- /dev/null +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; +static const struct socfpga_system_manager *system_manager_base = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +/* Assert or de-assert SoCFPGA reset manager reset. */ +void socfpga_per_reset(u32 reset, int set) +{ + const void *reg; + + if (RSTMGR_BANK(reset) == 0) + reg = &reset_manager_base->mpumodrst; + else if (RSTMGR_BANK(reset) == 1) + reg = &reset_manager_base->per0modrst; + else if (RSTMGR_BANK(reset) == 2) + reg = &reset_manager_base->per1modrst; + else if (RSTMGR_BANK(reset) == 3) + reg = &reset_manager_base->brgmodrst; + else /* Invalid reset register, do nothing */ + return; + + if (set) + setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + else + clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); +} + +/* + * Assert reset on every peripheral but L4WD0. + * Watchdog must be kept intact to prevent glitches + * and/or hangs. + */ +void socfpga_per_reset_all(void) +{ + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); + + /* disable all except OCP and l4wd0. OCP disable later */ + writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), + &reset_manager_base->per0modrst); + writel(~l4wd0, &reset_manager_base->per0modrst); + writel(0xffffffff, &reset_manager_base->per1modrst); +} + +void socfpga_bridges_reset(int enable) +{ + if (enable) { + /* clear idle request to all bridges */ + setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); + + /* Release bridges from reset state per handoff value */ + clrbits_le32(&reset_manager_base->brgmodrst, ~0); + + /* Poll until all idleack to 0 */ + while (readl(&system_manager_base->noc_idleack)) + ; + } else { + /* set idle request to all bridges */ + writel(~0, &system_manager_base->noc_idlereq_set); + + /* Enable the NOC timeout */ + writel(1, &system_manager_base->noc_timeout); + + /* Poll until all idleack to 1 */ + while ((readl(&system_manager_base->noc_idleack) ^ + (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) + ; + + /* Poll until all idlestatus to 1 */ + while ((readl(&system_manager_base->noc_idlestatus) ^ + (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) + ; + + /* Put all bridges (except NOR DDR scheduler) into reset */ + setbits_le32(&reset_manager_base->brgmodrst, + ~RSTMGR_BRGMODRST_DDRSCH_MASK); + + /* Disable NOC timeout */ + writel(0, &system_manager_base->noc_timeout); + } +} + +/* of_reset_id: emac reset id + * state: 0 - disable reset, !0 - enable reset + */ +void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state) +{ + u32 reset_emac; + u32 reset_emacocp; + + /* hardcode this now */ + switch (of_reset_id) { + case EMAC0_RESET: + reset_emac = SOCFPGA_RESET(EMAC0); + reset_emacocp = SOCFPGA_RESET(EMAC0_OCP); + break; + case EMAC1_RESET: + reset_emac = SOCFPGA_RESET(EMAC1); + reset_emacocp = SOCFPGA_RESET(EMAC1_OCP); + break; + case EMAC2_RESET: + reset_emac = SOCFPGA_RESET(EMAC2); + reset_emacocp = SOCFPGA_RESET(EMAC2_OCP); + break; + default: + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + hang(); + break; + } + + /* Reset ECC OCP first */ + socfpga_per_reset(reset_emacocp, state); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset_emac, state); +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per1modrst); + /* Enable OCP first */ + writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); + writel(0, &reset_manager_base->per0modrst); +} diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 4b86eadd81..0c9d7388e6 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -78,9 +79,7 @@ static void socfpga_nic301_slave_ns(void) void board_init_f(ulong dummy) { -#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET const struct cm_config *cm_default_cfg = cm_get_default_config(); -#endif unsigned long sdram_size; unsigned long reg; @@ -107,7 +106,6 @@ void board_init_f(ulong dummy) writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ writel(0x1, &pl310->pl310_addr_filter_start); -#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); @@ -142,8 +140,6 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); -#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ - /* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); socfpga_bridges_reset(0); @@ -196,6 +192,11 @@ void spl_board_init(void) /* enable console uart printing */ preloader_console_init(); + + WATCHDOG_RESET(); + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); } void board_init_f(ulong dummy) diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c new file mode 100644 index 0000000000..122828c9ce --- /dev/null +++ b/arch/arm/mach-socfpga/system_manager_s10.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * Configure all the pin muxes + */ +void sysmgr_pinmux_init(void) +{ + populate_sysmgr_pinmux(); + populate_sysmgr_fpgaintf_module(); +} + +/* + * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. + * The value is not wrote to SYSMGR.FPGAINTF.MODULE but + * CONFIG_SYSMGR_ISWGRP_HANDOFF. + */ +void populate_sysmgr_fpgaintf_module(void) +{ + u32 handoff_val = 0; + + /* Enable the signal for those HPS peripherals that use FPGA. */ + if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_NAND; + if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SDMMC; + if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM0; + if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_SPIM1; + writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); + + handoff_val = 0; + if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC0; + if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC1; + if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) + handoff_val |= SYSMGR_FPGAINTF_EMAC2; + writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); +} + +/* + * Configure all the pin muxes + */ +void populate_sysmgr_pinmux(void) +{ + const u32 *sys_mgr_table_u32; + unsigned int len, i; + + /* setup the pin sel */ + sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]); + } + + /* setup the pin ctrl */ + sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]); + } + + /* setup the fpga use */ + sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + + (u8 *)&sysmgr_regs->rgmii0usefpga); + } + + /* setup the IO delay */ + sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); + for (i = 0; i < len; i = i + 2) { + writel(sys_mgr_table_u32[i + 1], + sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]); + } +} diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c new file mode 100644 index 0000000000..0b497ec30c --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#include +#include +#include +#include + +static void sysmgr_pinmux_handoff_read(void *handoff_address, + const u32 **table, + unsigned int *table_len) +{ + unsigned int handoff_entry = (swab32(readl(handoff_address + + S10_HANDOFF_OFFSET_LENGTH)) - + S10_HANDOFF_OFFSET_DATA) / + sizeof(unsigned int); + unsigned int handoff_chunk[handoff_entry], temp, i; + + if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) { + /* using handoff from Quartus tools if exists */ + for (i = 0; i < handoff_entry; i++) { + temp = readl(handoff_address + + S10_HANDOFF_OFFSET_DATA + (i * 4)); + handoff_chunk[i] = swab32(temp); + } + *table = handoff_chunk; + *table_len = ARRAY_SIZE(handoff_chunk); + } +} + +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table, + table_len); +} + +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table, + table_len); +} + +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table, + table_len); +} + +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) +{ + sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table, + table_len); +} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c new file mode 100644 index 0000000000..7cafc7dcfc --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#include +#include +#include +#include +#include + +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +const struct cm_config * const cm_get_default_config(void) +{ + struct cm_config *cm_handoff_cfg = (struct cm_config *) + (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); + u32 *conversion = (u32 *)cm_handoff_cfg; + u32 i; + u32 handoff_clk = readl(S10_HANDOFF_CLOCK); + + if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) { + writel(swab32(handoff_clk), S10_HANDOFF_CLOCK); + for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) + conversion[i] = swab32(conversion[i]); + return cm_handoff_cfg; + } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { + return cm_handoff_cfg; + } + + return NULL; +} + +const unsigned int cm_get_osc_clk_hz(void) +{ +#ifdef CONFIG_SPL_BUILD + u32 clock = readl(S10_HANDOFF_CLOCK_OSC); + + writel(clock, &sysmgr_regs->boot_scratch_cold1); +#endif + return readl(&sysmgr_regs->boot_scratch_cold1); +} + +const unsigned int cm_get_intosc_clk_hz(void) +{ + return CLKMGR_INTOSC_HZ; +} + +const unsigned int cm_get_fpga_clk_hz(void) +{ +#ifdef CONFIG_SPL_BUILD + u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); + + writel(clock, &sysmgr_regs->boot_scratch_cold2); +#endif + return readl(&sysmgr_regs->boot_scratch_cold2); +} diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 021ec1d857..2b28a97f6e 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,5 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" - depends on TARGET_SOCFPGA_GEN5 + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index d42fd4451d..f05314a373 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,5 +7,6 @@ # Copyright (C) 2014 Altera Corporation ifdef CONFIG_ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o endif diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c deleted file mode 100644 index 821060459c..0000000000 --- a/drivers/ddr/altera/sdram.c +++ /dev/null @@ -1,536 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright Altera Corporation (C) 2014-2015 - */ -#include -#include -#include -#include -#include -#include -#include -#include - -struct sdram_prot_rule { - u32 sdram_start; /* SDRAM start address */ - u32 sdram_end; /* SDRAM end address */ - u32 rule; /* SDRAM protection rule number: 0-19 */ - int valid; /* Rule valid or not? 1 - valid, 0 not*/ - - u32 security; - u32 portmask; - u32 result; - u32 lo_prot_id; - u32 hi_prot_id; -}; - -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = - (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; - -/** - * get_errata_rows() - Up the number of DRAM rows to cover entire address space - * @cfg: SDRAM controller configuration data - * - * SDRAM Failure happens when accessing non-existent memory. Artificially - * increase the number of rows so that the memory controller thinks it has - * 4GB of RAM. This function returns such amount of rows. - */ -static int get_errata_rows(const struct socfpga_sdram_config *cfg) -{ - /* Define constant for 4G memory - used for SDRAM errata workaround */ -#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) - const unsigned long long memsize = MEMSIZE_4G; - const unsigned int cs = - ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; - const unsigned int rows = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - const unsigned int banks = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; - const unsigned int cols = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; - const unsigned int width = 8; - - unsigned long long newrows; - int bits, inewrowslog2; - - debug("workaround rows - memsize %lld\n", memsize); - debug("workaround rows - cs %d\n", cs); - debug("workaround rows - width %d\n", width); - debug("workaround rows - rows %d\n", rows); - debug("workaround rows - banks %d\n", banks); - debug("workaround rows - cols %d\n", cols); - - newrows = lldiv(memsize, cs * (width / 8)); - debug("rows workaround - term1 %lld\n", newrows); - - newrows = lldiv(newrows, (1 << banks) * (1 << cols)); - debug("rows workaround - term2 %lld\n", newrows); - - /* - * Compute the hamming weight - same as number of bits set. - * Need to see if result is ordinal power of 2 before - * attempting log2 of result. - */ - bits = generic_hweight32(newrows); - - debug("rows workaround - bits %d\n", bits); - - if (bits != 1) { - printf("SDRAM workaround failed, bits set %d\n", bits); - return rows; - } - - if (newrows > UINT_MAX) { - printf("SDRAM workaround rangecheck failed, %lld\n", newrows); - return rows; - } - - inewrowslog2 = __ilog2(newrows); - - debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); - - if (inewrowslog2 == -1) { - printf("SDRAM workaround failed, newrows %lld\n", newrows); - return rows; - } - - return inewrowslog2; -} - -/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ -static void sdram_set_rule(struct sdram_prot_rule *prule) -{ - u32 lo_addr_bits; - u32 hi_addr_bits; - int ruleno = prule->rule; - - /* Select the rule */ - writel(ruleno, &sdr_ctrl->prot_rule_rdwr); - - /* Obtain the address bits */ - lo_addr_bits = prule->sdram_start >> 20ULL; - hi_addr_bits = (prule->sdram_end - 1) >> 20ULL; - - debug("sdram set rule start %x, %d\n", lo_addr_bits, - prule->sdram_start); - debug("sdram set rule end %x, %d\n", hi_addr_bits, - prule->sdram_end); - - /* Set rule addresses */ - writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); - - /* Set rule protection ids */ - writel(prule->lo_prot_id | (prule->hi_prot_id << 12), - &sdr_ctrl->prot_rule_id); - - /* Set the rule data */ - writel(prule->security | (prule->valid << 2) | - (prule->portmask << 3) | (prule->result << 13), - &sdr_ctrl->prot_rule_data); - - /* write the rule */ - writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); - - /* Set rule number to 0 by default */ - writel(0, &sdr_ctrl->prot_rule_rdwr); -} - -static void sdram_get_rule(struct sdram_prot_rule *prule) -{ - u32 addr; - u32 id; - u32 data; - int ruleno = prule->rule; - - /* Read the rule */ - writel(ruleno, &sdr_ctrl->prot_rule_rdwr); - writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); - - /* Get the addresses */ - addr = readl(&sdr_ctrl->prot_rule_addr); - prule->sdram_start = (addr & 0xFFF) << 20; - prule->sdram_end = ((addr >> 12) & 0xFFF) << 20; - - /* Get the configured protection IDs */ - id = readl(&sdr_ctrl->prot_rule_id); - prule->lo_prot_id = id & 0xFFF; - prule->hi_prot_id = (id >> 12) & 0xFFF; - - /* Get protection data */ - data = readl(&sdr_ctrl->prot_rule_data); - - prule->security = data & 0x3; - prule->valid = (data >> 2) & 0x1; - prule->portmask = (data >> 3) & 0x3FF; - prule->result = (data >> 13) & 0x1; -} - -static void -sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) -{ - struct sdram_prot_rule rule; - int rules; - - /* Start with accepting all SDRAM transaction */ - writel(0x0, &sdr_ctrl->protport_default); - - /* Clear all protection rules for warm boot case */ - memset(&rule, 0, sizeof(rule)); - - for (rules = 0; rules < 20; rules++) { - rule.rule = rules; - sdram_set_rule(&rule); - } - - /* new rule: accept SDRAM */ - rule.sdram_start = sdram_start; - rule.sdram_end = sdram_end; - rule.lo_prot_id = 0x0; - rule.hi_prot_id = 0xFFF; - rule.portmask = 0x3FF; - rule.security = 0x3; - rule.result = 0; - rule.valid = 1; - rule.rule = 0; - - /* set new rule */ - sdram_set_rule(&rule); - - /* default rule: reject everything */ - writel(0x3ff, &sdr_ctrl->protport_default); -} - -static void sdram_dump_protection_config(void) -{ - struct sdram_prot_rule rule; - int rules; - - debug("SDRAM Prot rule, default %x\n", - readl(&sdr_ctrl->protport_default)); - - for (rules = 0; rules < 20; rules++) { - rule.rule = rules; - sdram_get_rule(&rule); - debug("Rule %d, rules ...\n", rules); - debug(" sdram start %x\n", rule.sdram_start); - debug(" sdram end %x\n", rule.sdram_end); - debug(" low prot id %d, hi prot id %d\n", - rule.lo_prot_id, - rule.hi_prot_id); - debug(" portmask %x\n", rule.portmask); - debug(" security %d\n", rule.security); - debug(" result %d\n", rule.result); - debug(" valid %d\n", rule.valid); - } -} - -/** - * sdram_write_verify() - write to register and verify the write. - * @addr: Register address - * @val: Value to be written and verified - * - * This function writes to a register, reads back the value and compares - * the result with the written value to check if the data match. - */ -static unsigned sdram_write_verify(const u32 *addr, const u32 val) -{ - u32 rval; - - debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); - writel(val, addr); - - debug(" Read and verify..."); - rval = readl(addr); - if (rval != val) { - debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", - addr, val, rval); - return -EINVAL; - } - - debug("correct!\n"); - return 0; -} - -/** - * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register - * @cfg: SDRAM controller configuration data - * - * Return the value of DRAM CTRLCFG register. - */ -static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) -{ - const u32 csbits = - ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; - u32 addrorder = - (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> - SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; - - u32 ctrl_cfg = cfg->ctrl_cfg; - - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Set the addrorder field of the SDRAM control register - * based on the CSBITs setting. - */ - if (csbits == 1) { - if (addrorder != 0) - debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); - addrorder = 0; - } else if (csbits == 2) { - if (addrorder != 2) - debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); - addrorder = 2; - } - - ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; - ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; - - return ctrl_cfg; -} - -/** - * sdr_get_addr_rw() - Get the value of DRAM ADDRW register - * @cfg: SDRAM controller configuration data - * - * Return the value of DRAM ADDRW register. - */ -static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) -{ - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to - * log2(number of chip select bits). Since there's only - * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, - * which is the same as "chip selects" - 1. - */ - const int rows = get_errata_rows(cfg); - u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK; - - return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); -} - -/** - * sdr_load_regs() - Load SDRAM controller registers - * @cfg: SDRAM controller configuration data - * - * This function loads the register values into the SDRAM controller block. - */ -static void sdr_load_regs(const struct socfpga_sdram_config *cfg) -{ - const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); - const u32 dram_addrw = sdr_get_addr_rw(cfg); - - debug("\nConfiguring CTRLCFG\n"); - writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); - - debug("Configuring DRAMTIMING1\n"); - writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); - - debug("Configuring DRAMTIMING2\n"); - writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); - - debug("Configuring DRAMTIMING3\n"); - writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); - - debug("Configuring DRAMTIMING4\n"); - writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); - - debug("Configuring LOWPWRTIMING\n"); - writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); - - debug("Configuring DRAMADDRW\n"); - writel(dram_addrw, &sdr_ctrl->dram_addrw); - - debug("Configuring DRAMIFWIDTH\n"); - writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width); - - debug("Configuring DRAMDEVWIDTH\n"); - writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width); - - debug("Configuring LOWPWREQ\n"); - writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq); - - debug("Configuring DRAMINTR\n"); - writel(cfg->dram_intr, &sdr_ctrl->dram_intr); - - debug("Configuring STATICCFG\n"); - writel(cfg->static_cfg, &sdr_ctrl->static_cfg); - - debug("Configuring CTRLWIDTH\n"); - writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); - - debug("Configuring PORTCFG\n"); - writel(cfg->port_cfg, &sdr_ctrl->port_cfg); - - debug("Configuring FIFOCFG\n"); - writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); - - debug("Configuring MPPRIORITY\n"); - writel(cfg->mp_priority, &sdr_ctrl->mp_priority); - - debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); - writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); - writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); - writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); - writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); - - debug("Configuring MPPACING_MPPACING_0\n"); - writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); - writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); - writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); - writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); - - debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); - writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); - writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); - writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); - - debug("Configuring PHYCTRL_PHYCTRL_0\n"); - writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); - - debug("Configuring CPORTWIDTH\n"); - writel(cfg->cport_width, &sdr_ctrl->cport_width); - - debug("Configuring CPORTWMAP\n"); - writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap); - - debug("Configuring CPORTRMAP\n"); - writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap); - - debug("Configuring RFIFOCMAP\n"); - writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap); - - debug("Configuring WFIFOCMAP\n"); - writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap); - - debug("Configuring CPORTRDWR\n"); - writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr); - - debug("Configuring DRAMODT\n"); - writel(cfg->dram_odt, &sdr_ctrl->dram_odt); - - debug("Configuring EXTRATIME1\n"); - writel(cfg->extratime1, &sdr_ctrl->extratime1); -} - -/** - * sdram_mmr_init_full() - Function to initialize SDRAM MMR - * @sdr_phy_reg: Value of the PHY control register 0 - * - * Initialize the SDRAM MMR. - */ -int sdram_mmr_init_full(unsigned int sdr_phy_reg) -{ - const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); - const unsigned int rows = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - int ret; - - writel(rows, &sysmgr_regs->iswgrp_handoff[4]); - - sdr_load_regs(cfg); - - /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); - - /* only enable if the FPGA is programmed */ - if (fpgamgr_test_fpga_ready()) { - ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, - cfg->fpgaport_rst); - if (ret) - return ret; - } - - /* Restore the SDR PHY Register if valid */ - if (sdr_phy_reg != 0xffffffff) - writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); - - /* Final step - apply configuration changes */ - debug("Configuring STATICCFG\n"); - clrsetbits_le32(&sdr_ctrl->static_cfg, - SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, - 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); - - sdram_set_protection_config(0, sdram_calculate_size() - 1); - - sdram_dump_protection_config(); - - return 0; -} - -/** - * sdram_calculate_size() - Calculate SDRAM size - * - * Calculate SDRAM device size based on SDRAM controller parameters. - * Size is specified in bytes. - */ -unsigned long sdram_calculate_size(void) -{ - unsigned long temp; - unsigned long row, bank, col, cs, width; - const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); - const unsigned int csbits = - ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; - const unsigned int rowbits = - (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; - - temp = readl(&sdr_ctrl->dram_addrw); - col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; - - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Use ROWBITS from Quartus/QSys to calculate SDRAM size - * since the FB specifies we modify ROWBITs to work around SDRAM - * controller issue. - */ - row = readl(&sysmgr_regs->iswgrp_handoff[4]); - if (row == 0) - row = rowbits; - /* - * If the stored handoff value for rows is greater than - * the field width in the sdr.dramaddrw register then - * something is very wrong. Revert to using the the #define - * value handed off by the SOCEDS tool chain instead of - * using a broken value. - */ - if (row > 31) - row = rowbits; - - bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> - SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; - - /* - * SDRAM Failure When Accessing Non-Existent Memory - * Use CSBITs from Quartus/QSys to calculate SDRAM size - * since the FB specifies we modify CSBITs to work around SDRAM - * controller issue. - */ - cs = csbits; - - width = readl(&sdr_ctrl->dram_if_width); - - /* ECC would not be calculated as its not addressible */ - if (width == SDRAM_WIDTH_32BIT_WITH_ECC) - width = 32; - if (width == SDRAM_WIDTH_16BIT_WITH_ECC) - width = 16; - - /* calculate the SDRAM size base on this info */ - temp = 1 << (row + bank + col); - temp = temp * cs * (width / 8); - - debug("%s returns %ld\n", __func__, temp); - - return temp; -} diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c new file mode 100644 index 0000000000..d953c376b8 --- /dev/null +++ b/drivers/ddr/altera/sdram_arria10.c @@ -0,0 +1,741 @@ +/* + * Copyright (C) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void sdram_mmr_init(void); +static u64 sdram_size_calc(void); + +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) + +#define ARRIA_DDR_CONFIG(A, B, C, R) \ + (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) +#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) +#define DDR_REG_SEQ2CORE 0xFFD0507C +#define DDR_REG_CORE2SEQ 0xFFD05078 +#define DDR_READ_LATENCY_DELAY 40 +#define DDR_SIZE_2GB_HEX 0x80000000 +#define DDR_MAX_TRIES 0x00100000 + +#define IO48_MMR_DRAMSTS 0xFFCFA0EC +#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 +#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 +#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 + +#define SEQ2CORE_MASK 0xF +#define CORE2SEQ_INT_REQ 0xF +#define SEQ2CORE_INT_RESP_BIT 3 + +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = + (void *)SOCFPGA_SDR_ADDRESS; +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram + *socfpga_noc_fw_ddr_mpu_fpga2sdram_base = + (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; + +/* The following are the supported configurations */ +static u32 ddr_config[] = { + /* Chip - Row - Bank - Column Style */ + /* All Types */ + ARRIA_DDR_CONFIG(0, 3, 10, 12), + ARRIA_DDR_CONFIG(0, 3, 10, 13), + ARRIA_DDR_CONFIG(0, 3, 10, 14), + ARRIA_DDR_CONFIG(0, 3, 10, 15), + ARRIA_DDR_CONFIG(0, 3, 10, 16), + ARRIA_DDR_CONFIG(0, 3, 10, 17), + /* LPDDR x16 */ + ARRIA_DDR_CONFIG(0, 3, 11, 14), + ARRIA_DDR_CONFIG(0, 3, 11, 15), + ARRIA_DDR_CONFIG(0, 3, 11, 16), + ARRIA_DDR_CONFIG(0, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(0, 4, 10, 14), + ARRIA_DDR_CONFIG(0, 4, 10, 15), + ARRIA_DDR_CONFIG(0, 4, 10, 16), + ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ + /* Chip - Bank - Row - Column Style */ + ARRIA_DDR_CONFIG(1, 3, 10, 12), + ARRIA_DDR_CONFIG(1, 3, 10, 13), + ARRIA_DDR_CONFIG(1, 3, 10, 14), + ARRIA_DDR_CONFIG(1, 3, 10, 15), + ARRIA_DDR_CONFIG(1, 3, 10, 16), + ARRIA_DDR_CONFIG(1, 3, 10, 17), + ARRIA_DDR_CONFIG(1, 3, 11, 14), + ARRIA_DDR_CONFIG(1, 3, 11, 15), + ARRIA_DDR_CONFIG(1, 3, 11, 16), + ARRIA_DDR_CONFIG(1, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(1, 4, 10, 14), + ARRIA_DDR_CONFIG(1, 4, 10, 15), + ARRIA_DDR_CONFIG(1, 4, 10, 16), + ARRIA_DDR_CONFIG(1, 4, 10, 17), +}; + +static int match_ddr_conf(u32 ddr_conf) +{ + int i; + + for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +/* Check whether SDRAM is successfully Calibrated */ +static int is_sdram_cal_success(void) +{ + return readl(&socfpga_ecc_hmc_base->ddrcalstat); +} + +static unsigned char ddr_get_bit(u32 ereg, unsigned char bit) +{ + u32 reg = readl(ereg); + + return (reg & BIT(bit)) ? 1 : 0; +} + +static unsigned char ddr_wait_bit(u32 ereg, u32 bit, + u32 expected, u32 timeout_usec) +{ + u32 tmr; + + for (tmr = 0; tmr < timeout_usec; tmr += 100) { + udelay(100); + WATCHDOG_RESET(); + if (ddr_get_bit(ereg, bit) == expected) + return 0; + } + + return 1; +} + +static int emif_clear(void) +{ + u32 i = DDR_MAX_TRIES; + u8 ret = 0; + + writel(0, DDR_REG_CORE2SEQ); + + do { + ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, + SEQ2CORE_MASK, 1, 50, 0); + } while (ret && (--i > 0)); + + return !i; +} + +static int emif_reset(void) +{ + u32 c2s, s2c; + + c2s = readl(DDR_REG_CORE2SEQ); + s2c = readl(DDR_REG_SEQ2CORE); + + debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0), + readl(IO48_MMR_NIOS2_RESERVE1), + readl(IO48_MMR_NIOS2_RESERVE2), + readl(IO48_MMR_DRAMSTS)); + + if ((s2c & SEQ2CORE_MASK) && emif_clear()) { + debug("failed emif_clear()\n"); + return -EPERM; + } + + writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); + + if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { + debug("emif_reset failed to see interrupt acknowledge\n"); + return -EPERM; + } else { + debug("emif_reset interrupt acknowledged\n"); + } + + if (emif_clear()) { + debug("emif_clear() failed\n"); + return -EPERM; + } + debug("emif_reset interrupt cleared\n"); + + debug("nr0=%08x nr1=%08x nr2=%08x\n", + readl(IO48_MMR_NIOS2_RESERVE0), + readl(IO48_MMR_NIOS2_RESERVE1), + readl(IO48_MMR_NIOS2_RESERVE2)); + + return 0; +} + +static int ddr_setup(void) +{ + int i, j, ddr_setup_complete = 0; + + /* Try 3 times to do a calibration */ + for (i = 0; (i < 3) && !ddr_setup_complete; i++) { + WATCHDOG_RESET(); + + /* A delay to wait for calibration bit to set */ + for (j = 0; (j < 10) && !ddr_setup_complete; j++) { + mdelay(500); + ddr_setup_complete = is_sdram_cal_success(); + } + + if (!ddr_setup_complete) + if (emif_reset()) + puts("Error: Failed to reset EMIF\n"); + } + + /* After 3 times trying calibration */ + if (!ddr_setup_complete) { + puts("Error: Could Not Calibrate SDRAM\n"); + return -EPERM; + } + + return 0; +} + +/* Function to startup the SDRAM*/ +static int sdram_startup(void) +{ + /* Release NOC ddr scheduler from reset */ + socfpga_reset_deassert_noc_ddr_scheduler(); + + /* Bringup the DDR (calibration and configuration) */ + return ddr_setup(); +} + +static u64 sdram_size_calc(void) +{ + u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); + + u64 size = BIT(((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) + + (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK)); + + size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & + ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK)); + + debug("SDRAM size=%llu", size); + + return size; +} + +/* Function to initialize SDRAM MMR and NOC DDR scheduler*/ +static void sdram_mmr_init(void) +{ + u32 update_value, io48_value; + u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0); + u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1); + u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw); + u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0); + u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1); + u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2); + u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3); + u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4); + u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9); + u32 ddrioctl; + + /* + * Configure the DDR IO size [0xFFCFB008] + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (0x20 for 32bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) { + update_value = readl(&socfpga_io48_mmr_base->niosreserve0); + writel(((update_value & 0xFF) >> 5), + &socfpga_ecc_hmc_base->ddrioctrl); + } + + ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl); + + /* Set the DDR Configuration [0xFFD12400] */ + io48_value = ARRIA_DDR_CONFIG( + ((ctrlcfg1 & + IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >> + IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT), + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) + + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT), + (dramaddrw & + IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK), + ((dramaddrw & + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >> + IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT)); + + update_value = match_ddr_conf(io48_value); + if (update_value) + writel(update_value, + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf); + + /* + * Configure DDR timing [0xFFD1240C] + * RDTOMISS = tRTP + tRP + tRCD - BL/2 + * WRTOMISS = WL + tWR + tRP + tRCD and + * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... + * First part of equation is in memory clock units so divide by 2 + * for HMC clock units. 1066MHz is close to 1ns so use 15 directly. + * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD + */ + u32 ctrlcfg0_cfg_ctrl_burst_len = + (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >> + IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT; + + u32 caltim0_cfg_act_to_rdwr = caltim0 & + IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK; + + u32 caltim0_cfg_act_to_act = + (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >> + IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT; + + u32 caltim0_cfg_act_to_act_db = + (caltim0 & + IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >> + IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT; + + u32 caltim1_cfg_rd_to_wr = + (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >> + IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT; + + u32 caltim1_cfg_rd_to_rd_dc = + (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >> + IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT; + + u32 caltim1_cfg_rd_to_wr_dc = + (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >> + IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT; + + u32 caltim2_cfg_rd_to_pch = + (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >> + IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT; + + u32 caltim3_cfg_wr_to_rd = + (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >> + IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT; + + u32 caltim3_cfg_wr_to_rd_dc = + (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >> + IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT; + + u32 caltim4_cfg_pch_to_valid = + (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >> + IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT; + + u32 caltim9_cfg_4_act_to_act = caltim9 & + IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK; + + update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + + caltim0_cfg_act_to_rdwr - + (ctrlcfg0_cfg_ctrl_burst_len >> 2)); + + io48_value = ((((socfpga_io48_mmr_base->dramtiming0 & + ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 + + (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - + /* Up to here was in memory cycles so divide by 2 */ + caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr + + caltim4_cfg_pch_to_valid); + + writel(((caltim0_cfg_act_to_act << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) | + (update_value << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) | + (io48_value << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) | + ((ctrlcfg0_cfg_ctrl_burst_len >> 2) << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) | + (caltim1_cfg_rd_to_wr << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) | + (caltim3_cfg_wr_to_rd << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) | + (((ddrioctl == 1) ? 1 : 0) << + ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)), + &socfpga_noc_ddr_scheduler_base-> + ddr_t_main_scheduler_ddrtiming); + + /* Configure DDR mode [0xFFD12410] [precharge = 0] */ + writel(((ddrioctl ? 0 : 1) << + ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB), + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); + + /* Configure the read latency [0xFFD12414] */ + writel(((socfpga_io48_mmr_base->dramtiming0 & + ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) + + DDR_READ_LATENCY_DELAY, + &socfpga_noc_ddr_scheduler_base-> + ddr_t_main_scheduler_readlatency); + + /* + * Configuring timing values concerning activate commands + * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR] + */ + writel(((caltim0_cfg_act_to_act_db << + ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) | + (caltim9_cfg_4_act_to_act << + ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) | + (ARRIA10_SDR_ACTIVATE_FAWBANK << + ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)), + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate); + + /* + * Configuring timing values concerning device to device data bus + * ownership change [0xFFD1243C] + */ + writel(((caltim1_cfg_rd_to_rd_dc << + ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) | + (caltim1_cfg_rd_to_wr_dc << + ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) | + (caltim3_cfg_wr_to_rd_dc << + ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)), + &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev); + + /* Enable or disable the SDRAM ECC */ + if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) { + setbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); + } else { + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl, + (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2, + (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK | + ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK)); + } +} + +struct firewall_entry { + const char *prop_name; + const u32 cfg_addr; + const u32 en_addr; + const u32 en_bit; +}; +#define FW_MPU_FPGA_ADDRESS \ + ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\ + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS) + +#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \ + (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \ + offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR)) + +#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \ + (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \ + offsetof(struct socfpga_noc_fw_ddr_l3, ADDR)) + +const struct firewall_entry firewall_table[] = { + { + "mpu0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK + }, + { + "mpu1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK + }, + { + "mpu2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK + }, + { + "mpu3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK + }, + { + "l3-0", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK + }, + { + "l3-1", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK + }, + { + "l3-2", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK + }, + { + "l3-3", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK + }, + { + "l3-4", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK + }, + { + "l3-5", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK + }, + { + "l3-6", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK + }, + { + "l3-7", + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr), + SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK + }, + { + "fpga2sdram0-0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK + }, + { + "fpga2sdram0-1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK + }, + { + "fpga2sdram0-2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK + }, + { + "fpga2sdram0-3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram0region3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK + }, + { + "fpga2sdram1-0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK + }, + { + "fpga2sdram1-1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK + }, + { + "fpga2sdram1-2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK + }, + { + "fpga2sdram1-3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram1region3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK + }, + { + "fpga2sdram2-0", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region0addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK + }, + { + "fpga2sdram2-1", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region1addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK + }, + { + "fpga2sdram2-2", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region2addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK + }, + { + "fpga2sdram2-3", + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET + (fpga2sdram2region3addr), + SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable), + ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK + }, + +}; + +static int of_sdram_firewall_setup(const void *blob) +{ + int child, i, node, ret; + u32 start_end[2]; + char name[32]; + + node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC); + if (node < 0) + return -ENXIO; + + child = fdt_first_subnode(blob, node); + if (child < 0) + return -ENXIO; + + /* set to default state */ + writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); + writel(0, &socfpga_noc_fw_ddr_l3_base->enable); + + + for (i = 0; i < ARRAY_SIZE(firewall_table); i++) { + sprintf(name, "%s", firewall_table[i].prop_name); + ret = fdtdec_get_int_array(blob, child, name, + start_end, 2); + if (ret) { + sprintf(name, "altr,%s", firewall_table[i].prop_name); + ret = fdtdec_get_int_array(blob, child, name, + start_end, 2); + if (ret) + continue; + } + + writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) | + (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB), + firewall_table[i].cfg_addr); + setbits_le32(firewall_table[i].en_addr, + firewall_table[i].en_bit); + } + + return 0; +} + +int ddr_calibration_sequence(void) +{ + WATCHDOG_RESET(); + + /* Check to see if SDRAM cal was success */ + if (sdram_startup()) { + puts("DDRCAL: Failed\n"); + return -EPERM; + } + + puts("DDRCAL: Success\n"); + + WATCHDOG_RESET(); + + /* initialize the MMR register */ + sdram_mmr_init(); + + /* assigning the SDRAM size */ + u64 size = sdram_size_calc(); + + /* + * If size is less than zero, this is invalid/weird value from + * calculation, use default Config size. + * Up to 2GB is supported, 2GB would be used if more than that. + */ + if (size <= 0) + gd->ram_size = PHYS_SDRAM_1_SIZE; + else if (DDR_SIZE_2GB_HEX <= size) + gd->ram_size = DDR_SIZE_2GB_HEX; + else + gd->ram_size = (u32)size; + + /* setup the dram info within bd */ + dram_init_banksize(); + + if (of_sdram_firewall_setup(gd->fdt_blob)) + puts("FW: Error Configuring Firewall\n"); + + return 0; +} + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + debug("%s: bank: %d\n", __func__, bank); + for (i = bd->bi_dram[bank].start >> 20; + i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i++) { +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + set_section_dcache(i, DCACHE_WRITETHROUGH); +#else + set_section_dcache(i, DCACHE_WRITEBACK); +#endif + } + + /* same as above but just that we would want cacheable for ocram too */ + i = CONFIG_SYS_INIT_RAM_ADDR >> 20; +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + set_section_dcache(i, DCACHE_WRITETHROUGH); +#else + set_section_dcache(i, DCACHE_WRITEBACK); +#endif +} diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c new file mode 100644 index 0000000000..821060459c --- /dev/null +++ b/drivers/ddr/altera/sdram_gen5.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright Altera Corporation (C) 2014-2015 + */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct sdram_prot_rule { + u32 sdram_start; /* SDRAM start address */ + u32 sdram_end; /* SDRAM end address */ + u32 rule; /* SDRAM protection rule number: 0-19 */ + int valid; /* Rule valid or not? 1 - valid, 0 not*/ + + u32 security; + u32 portmask; + u32 result; + u32 lo_prot_id; + u32 hi_prot_id; +}; + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_sdr_ctrl *sdr_ctrl = + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +/** + * get_errata_rows() - Up the number of DRAM rows to cover entire address space + * @cfg: SDRAM controller configuration data + * + * SDRAM Failure happens when accessing non-existent memory. Artificially + * increase the number of rows so that the memory controller thinks it has + * 4GB of RAM. This function returns such amount of rows. + */ +static int get_errata_rows(const struct socfpga_sdram_config *cfg) +{ + /* Define constant for 4G memory - used for SDRAM errata workaround */ +#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL) + const unsigned long long memsize = MEMSIZE_4G; + const unsigned int cs = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + const unsigned int banks = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; + const unsigned int cols = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; + const unsigned int width = 8; + + unsigned long long newrows; + int bits, inewrowslog2; + + debug("workaround rows - memsize %lld\n", memsize); + debug("workaround rows - cs %d\n", cs); + debug("workaround rows - width %d\n", width); + debug("workaround rows - rows %d\n", rows); + debug("workaround rows - banks %d\n", banks); + debug("workaround rows - cols %d\n", cols); + + newrows = lldiv(memsize, cs * (width / 8)); + debug("rows workaround - term1 %lld\n", newrows); + + newrows = lldiv(newrows, (1 << banks) * (1 << cols)); + debug("rows workaround - term2 %lld\n", newrows); + + /* + * Compute the hamming weight - same as number of bits set. + * Need to see if result is ordinal power of 2 before + * attempting log2 of result. + */ + bits = generic_hweight32(newrows); + + debug("rows workaround - bits %d\n", bits); + + if (bits != 1) { + printf("SDRAM workaround failed, bits set %d\n", bits); + return rows; + } + + if (newrows > UINT_MAX) { + printf("SDRAM workaround rangecheck failed, %lld\n", newrows); + return rows; + } + + inewrowslog2 = __ilog2(newrows); + + debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); + + if (inewrowslog2 == -1) { + printf("SDRAM workaround failed, newrows %lld\n", newrows); + return rows; + } + + return inewrowslog2; +} + +/* SDRAM protection rules vary from 0-19, a total of 20 rules. */ +static void sdram_set_rule(struct sdram_prot_rule *prule) +{ + u32 lo_addr_bits; + u32 hi_addr_bits; + int ruleno = prule->rule; + + /* Select the rule */ + writel(ruleno, &sdr_ctrl->prot_rule_rdwr); + + /* Obtain the address bits */ + lo_addr_bits = prule->sdram_start >> 20ULL; + hi_addr_bits = (prule->sdram_end - 1) >> 20ULL; + + debug("sdram set rule start %x, %d\n", lo_addr_bits, + prule->sdram_start); + debug("sdram set rule end %x, %d\n", hi_addr_bits, + prule->sdram_end); + + /* Set rule addresses */ + writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr); + + /* Set rule protection ids */ + writel(prule->lo_prot_id | (prule->hi_prot_id << 12), + &sdr_ctrl->prot_rule_id); + + /* Set the rule data */ + writel(prule->security | (prule->valid << 2) | + (prule->portmask << 3) | (prule->result << 13), + &sdr_ctrl->prot_rule_data); + + /* write the rule */ + writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr); + + /* Set rule number to 0 by default */ + writel(0, &sdr_ctrl->prot_rule_rdwr); +} + +static void sdram_get_rule(struct sdram_prot_rule *prule) +{ + u32 addr; + u32 id; + u32 data; + int ruleno = prule->rule; + + /* Read the rule */ + writel(ruleno, &sdr_ctrl->prot_rule_rdwr); + writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr); + + /* Get the addresses */ + addr = readl(&sdr_ctrl->prot_rule_addr); + prule->sdram_start = (addr & 0xFFF) << 20; + prule->sdram_end = ((addr >> 12) & 0xFFF) << 20; + + /* Get the configured protection IDs */ + id = readl(&sdr_ctrl->prot_rule_id); + prule->lo_prot_id = id & 0xFFF; + prule->hi_prot_id = (id >> 12) & 0xFFF; + + /* Get protection data */ + data = readl(&sdr_ctrl->prot_rule_data); + + prule->security = data & 0x3; + prule->valid = (data >> 2) & 0x1; + prule->portmask = (data >> 3) & 0x3FF; + prule->result = (data >> 13) & 0x1; +} + +static void +sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end) +{ + struct sdram_prot_rule rule; + int rules; + + /* Start with accepting all SDRAM transaction */ + writel(0x0, &sdr_ctrl->protport_default); + + /* Clear all protection rules for warm boot case */ + memset(&rule, 0, sizeof(rule)); + + for (rules = 0; rules < 20; rules++) { + rule.rule = rules; + sdram_set_rule(&rule); + } + + /* new rule: accept SDRAM */ + rule.sdram_start = sdram_start; + rule.sdram_end = sdram_end; + rule.lo_prot_id = 0x0; + rule.hi_prot_id = 0xFFF; + rule.portmask = 0x3FF; + rule.security = 0x3; + rule.result = 0; + rule.valid = 1; + rule.rule = 0; + + /* set new rule */ + sdram_set_rule(&rule); + + /* default rule: reject everything */ + writel(0x3ff, &sdr_ctrl->protport_default); +} + +static void sdram_dump_protection_config(void) +{ + struct sdram_prot_rule rule; + int rules; + + debug("SDRAM Prot rule, default %x\n", + readl(&sdr_ctrl->protport_default)); + + for (rules = 0; rules < 20; rules++) { + rule.rule = rules; + sdram_get_rule(&rule); + debug("Rule %d, rules ...\n", rules); + debug(" sdram start %x\n", rule.sdram_start); + debug(" sdram end %x\n", rule.sdram_end); + debug(" low prot id %d, hi prot id %d\n", + rule.lo_prot_id, + rule.hi_prot_id); + debug(" portmask %x\n", rule.portmask); + debug(" security %d\n", rule.security); + debug(" result %d\n", rule.result); + debug(" valid %d\n", rule.valid); + } +} + +/** + * sdram_write_verify() - write to register and verify the write. + * @addr: Register address + * @val: Value to be written and verified + * + * This function writes to a register, reads back the value and compares + * the result with the written value to check if the data match. + */ +static unsigned sdram_write_verify(const u32 *addr, const u32 val) +{ + u32 rval; + + debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); + writel(val, addr); + + debug(" Read and verify..."); + rval = readl(addr); + if (rval != val) { + debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", + addr, val, rval); + return -EINVAL; + } + + debug("correct!\n"); + return 0; +} + +/** + * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register + * @cfg: SDRAM controller configuration data + * + * Return the value of DRAM CTRLCFG register. + */ +static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) +{ + const u32 csbits = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + u32 addrorder = + (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> + SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; + + u32 ctrl_cfg = cfg->ctrl_cfg; + + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Set the addrorder field of the SDRAM control register + * based on the CSBITs setting. + */ + if (csbits == 1) { + if (addrorder != 0) + debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); + addrorder = 0; + } else if (csbits == 2) { + if (addrorder != 2) + debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); + addrorder = 2; + } + + ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK; + ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB; + + return ctrl_cfg; +} + +/** + * sdr_get_addr_rw() - Get the value of DRAM ADDRW register + * @cfg: SDRAM controller configuration data + * + * Return the value of DRAM ADDRW register. + */ +static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) +{ + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to + * log2(number of chip select bits). Since there's only + * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1, + * which is the same as "chip selects" - 1. + */ + const int rows = get_errata_rows(cfg); + u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK; + + return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB); +} + +/** + * sdr_load_regs() - Load SDRAM controller registers + * @cfg: SDRAM controller configuration data + * + * This function loads the register values into the SDRAM controller block. + */ +static void sdr_load_regs(const struct socfpga_sdram_config *cfg) +{ + const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg); + const u32 dram_addrw = sdr_get_addr_rw(cfg); + + debug("\nConfiguring CTRLCFG\n"); + writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg); + + debug("Configuring DRAMTIMING1\n"); + writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1); + + debug("Configuring DRAMTIMING2\n"); + writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2); + + debug("Configuring DRAMTIMING3\n"); + writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3); + + debug("Configuring DRAMTIMING4\n"); + writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); + + debug("Configuring LOWPWRTIMING\n"); + writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing); + + debug("Configuring DRAMADDRW\n"); + writel(dram_addrw, &sdr_ctrl->dram_addrw); + + debug("Configuring DRAMIFWIDTH\n"); + writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width); + + debug("Configuring DRAMDEVWIDTH\n"); + writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width); + + debug("Configuring LOWPWREQ\n"); + writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq); + + debug("Configuring DRAMINTR\n"); + writel(cfg->dram_intr, &sdr_ctrl->dram_intr); + + debug("Configuring STATICCFG\n"); + writel(cfg->static_cfg, &sdr_ctrl->static_cfg); + + debug("Configuring CTRLWIDTH\n"); + writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width); + + debug("Configuring PORTCFG\n"); + writel(cfg->port_cfg, &sdr_ctrl->port_cfg); + + debug("Configuring FIFOCFG\n"); + writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg); + + debug("Configuring MPPRIORITY\n"); + writel(cfg->mp_priority, &sdr_ctrl->mp_priority); + + debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); + writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0); + writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1); + writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2); + writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3); + + debug("Configuring MPPACING_MPPACING_0\n"); + writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0); + writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1); + writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2); + writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3); + + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); + writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0); + writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1); + writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2); + + debug("Configuring PHYCTRL_PHYCTRL_0\n"); + writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0); + + debug("Configuring CPORTWIDTH\n"); + writel(cfg->cport_width, &sdr_ctrl->cport_width); + + debug("Configuring CPORTWMAP\n"); + writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap); + + debug("Configuring CPORTRMAP\n"); + writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap); + + debug("Configuring RFIFOCMAP\n"); + writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap); + + debug("Configuring WFIFOCMAP\n"); + writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap); + + debug("Configuring CPORTRDWR\n"); + writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr); + + debug("Configuring DRAMODT\n"); + writel(cfg->dram_odt, &sdr_ctrl->dram_odt); + + debug("Configuring EXTRATIME1\n"); + writel(cfg->extratime1, &sdr_ctrl->extratime1); +} + +/** + * sdram_mmr_init_full() - Function to initialize SDRAM MMR + * @sdr_phy_reg: Value of the PHY control register 0 + * + * Initialize the SDRAM MMR. + */ +int sdram_mmr_init_full(unsigned int sdr_phy_reg) +{ + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); + const unsigned int rows = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + int ret; + + writel(rows, &sysmgr_regs->iswgrp_handoff[4]); + + sdr_load_regs(cfg); + + /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */ + writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); + + /* only enable if the FPGA is programmed */ + if (fpgamgr_test_fpga_ready()) { + ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst, + cfg->fpgaport_rst); + if (ret) + return ret; + } + + /* Restore the SDR PHY Register if valid */ + if (sdr_phy_reg != 0xffffffff) + writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0); + + /* Final step - apply configuration changes */ + debug("Configuring STATICCFG\n"); + clrsetbits_le32(&sdr_ctrl->static_cfg, + SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK, + 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB); + + sdram_set_protection_config(0, sdram_calculate_size() - 1); + + sdram_dump_protection_config(); + + return 0; +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +unsigned long sdram_calculate_size(void) +{ + unsigned long temp; + unsigned long row, bank, col, cs, width; + const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config(); + const unsigned int csbits = + ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1; + const unsigned int rowbits = + (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB; + + temp = readl(&sdr_ctrl->dram_addrw); + col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB; + + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Use ROWBITS from Quartus/QSys to calculate SDRAM size + * since the FB specifies we modify ROWBITs to work around SDRAM + * controller issue. + */ + row = readl(&sysmgr_regs->iswgrp_handoff[4]); + if (row == 0) + row = rowbits; + /* + * If the stored handoff value for rows is greater than + * the field width in the sdr.dramaddrw register then + * something is very wrong. Revert to using the the #define + * value handed off by the SOCEDS tool chain instead of + * using a broken value. + */ + if (row > 31) + row = rowbits; + + bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> + SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB; + + /* + * SDRAM Failure When Accessing Non-Existent Memory + * Use CSBITs from Quartus/QSys to calculate SDRAM size + * since the FB specifies we modify CSBITs to work around SDRAM + * controller issue. + */ + cs = csbits; + + width = readl(&sdr_ctrl->dram_if_width); + + /* ECC would not be calculated as its not addressible */ + if (width == SDRAM_WIDTH_32BIT_WITH_ECC) + width = 32; + if (width == SDRAM_WIDTH_16BIT_WITH_ECC) + width = 16; + + /* calculate the SDRAM size base on this info */ + temp = 1 << (row + bank + col); + temp = temp * cs * (width / 8); + + debug("%s returns %ld\n", __func__, temp); + + return temp; +} diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4de2aa7929..acac4a7108 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -5,9 +5,6 @@ #ifndef __CONFIG_SOCFPGA_COMMON_H__ #define __CONFIG_SOCFPGA_COMMON_H__ -/* Virtual target or real hardware */ -#undef CONFIG_SOCFPGA_VIRTUAL_TARGET - /* * High level configuration */ @@ -35,10 +32,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ #endif -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 @@ -78,7 +73,7 @@ /* * Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#ifdef CONFIG_CMD_NET #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #endif @@ -97,11 +92,7 @@ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else #define CONFIG_SYS_TIMER_RATE 25000000 -#endif /* * L4 Watchdog @@ -182,16 +173,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * Serial Driver */ #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_NS16550_CLK 1000000 -#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550_CLK 100000000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS -#define CONFIG_SYS_NS16550_CLK 50000000 -#endif /* * USB @@ -245,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * SPL * - * SRAM Memory layout: + * SRAM Memory layout for gen 5: * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_yyyy ...... Malloc area * 0xFFFF_zzzz ...... Global Data * 0xFFFF_FF00 ...... End of SRAM + * + * SRAM Memory layout for Arria 10: + * 0xFFE0_0000 ...... Start of SRAM (bottom) + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc area (grows up to top) + * 0xFFE3_FFFF ...... End of SRAM (top) */ #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +/* SPL memory allocation configuration, this is for FAT implementation */ +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SYS_INIT_RAM_ADDR) +#endif +#endif + /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) @@ -282,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Stack setup */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START +#endif /* Extra Environment */ #ifndef CONFIG_SPL_BUILD diff --git a/include/fdtdec.h b/include/fdtdec.h index 5456a17d1a..c15b2a04a7 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -160,6 +160,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */ COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */ + COMPAT_ALTERA_SOCFPGA_CLK_INIT, /* SOCFPGA Arria 10 clk init */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 69bf12623e..f4e8dbf699 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -72,6 +72,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"), COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"), + COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init") }; const char *fdtdec_get_compatible(enum fdt_compat_id id) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 71df6dbebd..07dad617cf 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1848,7 +1848,6 @@ CONFIG_SMSTP6_ENA CONFIG_SMSTP7_ENA CONFIG_SMSTP8_ENA CONFIG_SMSTP9_ENA -CONFIG_SOCFPGA_VIRTUAL_TARGET CONFIG_SOCRATES CONFIG_SOC_AU1000 CONFIG_SOC_AU1100