From: Robert Jarzmik Date: Mon, 24 Jun 2013 02:52:51 +0000 (+0200) Subject: target: xscale make reset init work properly X-Git-Tag: v0.8.0-rc1~381 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=9188a9bc680702a10ed5ccd4a748829816fe172d;p=openocd target: xscale make reset init work properly On XScale architecture, to write debug control register DCSR and activate JTAG debug (ie. to choose Halt Mode), the enabling can only be done while the board is held in reset state (ie. PXAxx #RST line held low). The current implementation writes to the register before asserting the SRST line. Swap the order to activate the SRST line before writing to DCSR. Change-Id: I914b9d53d39bdeb5fe4ee5e11068cafafe0da4d2 Signed-off-by: Robert Jarzmik Reviewed-on: http://openocd.zylin.com/1458 Tested-by: jenkins Reviewed-by: Marek Vasut Reviewed-by: Spencer Oliver --- diff --git a/src/target/xscale.c b/src/target/xscale.c index 92c4ede8..ed2afa46 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -1447,6 +1447,13 @@ static int xscale_assert_reset(struct target *target) LOG_DEBUG("target->state: %s", target_state_name(target)); + /* assert reset */ + jtag_add_reset(0, 1); + + /* sleep 1ms, to be sure we fulfill any requirements */ + jtag_add_sleep(1000); + jtag_execute_queue(); + /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ @@ -1463,13 +1470,6 @@ static int xscale_assert_reset(struct target *target) xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE); jtag_execute_queue(); - /* assert reset */ - jtag_add_reset(0, 1); - - /* sleep 1ms, to be sure we fulfill any requirements */ - jtag_add_sleep(1000); - jtag_execute_queue(); - target->state = TARGET_RESET; if (target->reset_halt) {