From: Anton Vorontsov <avorontsov@ru.mvista.com>
Date: Mon, 24 Mar 2008 17:46:24 +0000 (+0300)
Subject: uec: add support for gbit mii status readings
X-Git-Tag: v1.3.3-rc1~158
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=91cdaa3a9d7562b869d96774e9c9ddf142c0848d;p=u-boot

uec: add support for gbit mii status readings

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index a42701c59b..8c4a558d82 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -318,16 +318,26 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 		return err;
 
 	if (mii_info->autoneg) {
-		status = phy_read (mii_info, PHY_ANLPAR);
+		status = phy_read(mii_info, MII_1000BASETSTATUS);
 
-		if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
-			mii_info->duplex = DUPLEX_FULL;
-		else
-			mii_info->duplex = DUPLEX_HALF;
-		if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
-			mii_info->speed = SPEED_100;
-		else
-			mii_info->speed = SPEED_10;
+		if (status & (LPA_1000FULL | LPA_1000HALF)) {
+			mii_info->speed = SPEED_1000;
+			if (status & LPA_1000FULL)
+				mii_info->duplex = DUPLEX_FULL;
+			else
+				mii_info->duplex = DUPLEX_HALF;
+		} else {
+			status = phy_read(mii_info, PHY_ANLPAR);
+
+			if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+				mii_info->duplex = DUPLEX_FULL;
+			else
+				mii_info->duplex = DUPLEX_HALF;
+			if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+				mii_info->speed = SPEED_100;
+			else
+				mii_info->speed = SPEED_10;
+		}
 		mii_info->pause = 0;
 	}
 	/* On non-aneg, we assume what we put in BMCR is the speed,
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index e59a940e0d..6f769fb50b 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -29,6 +29,11 @@
 #define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
 #define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
 
+/* 1000BT status */
+#define MII_1000BASETSTATUS	0x0a
+#define LPA_1000FULL		0x0400
+#define LPA_1000HALF		0x0200
+
 /* Cicada Extended Control Register 1 */
 #define MII_CIS8201_EXT_CON1	    0x17
 #define MII_CIS8201_EXTCON1_INIT    0x0000