From: Bruce Adler <bruce.adler@ccpu.com>
Date: Fri, 10 Aug 2007 21:54:47 +0000 (-0700)
Subject: add image size and descriptors for Spartan 3E FPGA chips
X-Git-Tag: v1.3.0-rc1~19^2~20^2~3
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=923efd286411ed052d9e074f59f8986d6081061c;p=u-boot

add image size and descriptors for Spartan 3E FPGA chips

Spartan 3E image sizes taken from Table 1-4 in Xilinx UG332 (v1.1)

Signed-off by: Bruce Adler <bruce.adler@ccpu.com>
---

diff --git a/include/spartan3.h b/include/spartan3.h
index b14db039c4..65a3f5a4db 100644
--- a/include/spartan3.h
+++ b/include/spartan3.h
@@ -73,6 +73,13 @@ typedef struct {
 #define XILINX_XC3S4000_SIZE 	11316864/8
 #define XILINX_XC3S5000_SIZE 	13271936/8
 
+/* Spartan-3E (v3.4) */
+#define	XILINX_XC3S100E_SIZE	581344/8
+#define	XILINX_XC3S250E_SIZE	1353728/8
+#define	XILINX_XC3S500E_SIZE	2270208/8
+#define	XILINX_XC3S1200E_SIZE	3841184/8
+#define	XILINX_XC3S1600E_SIZE	5969696/8
+
 /* Descriptor Macros
  *********************************************************************/
 /* Spartan-II devices */
@@ -100,4 +107,21 @@ typedef struct {
 #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
 { Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
 
+
+/* Spartan-3E devices */
+#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
+
 #endif /* _SPARTAN3_H_ */