From: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Date: Tue, 27 Oct 2009 03:56:55 +0000 (+0530)
Subject: 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.
X-Git-Tag: v2009.11-rc1~7^2~10
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=924024c396761c267b948f38d78e9905f2036501;p=u-boot

85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.

The data being modified was in NOR flash which caused the crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 37c4b0a3ba..5cb4a13e08 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -206,7 +206,7 @@ phys_size_t fixed_sdram (void)
 {
 	sys_info_t sysinfo;
 	char buf[32];
-	fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
 	size_t ddr_size;
 	struct cpu_type *cpu;
 
@@ -215,13 +215,13 @@ phys_size_t fixed_sdram (void)
 				strmhz(buf, sysinfo.freqDDRBus));
 
 	if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
-		ddr_cfg_regs = &ddr_cfg_regs_400;
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
 	else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
-		ddr_cfg_regs = &ddr_cfg_regs_533;
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
 	else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
-		ddr_cfg_regs = &ddr_cfg_regs_667;
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
 	else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
-		ddr_cfg_regs = &ddr_cfg_regs_800;
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
 	else
 		panic("Unsupported DDR data rate %s MT/s data rate\n",
 					strmhz(buf, sysinfo.freqDDRBus));
@@ -230,14 +230,14 @@ phys_size_t fixed_sdram (void)
 	/* P1020 and it's derivatives support max 32bit DDR width */
 	if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
 		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
-		ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
-		ddr_cfg_regs->cs[0].bnds = 0x0000001F;
+		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
 		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
 	}
 	else
 		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
-	fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
 
 	return ddr_size;
 }