From: Andy Fleming <afleming@freescale.com>
Date: Sat, 24 Feb 2007 07:16:45 +0000 (-0600)
Subject: Tweak DDR ECC error counter
X-Git-Tag: v1.3.0-rc1~90^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=9343dbf85bc03033f2102d8e8543567c2c1ad2d2;p=u-boot

Tweak DDR ECC error counter

Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 6da5367a70..4b3c4eb706 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -786,14 +786,17 @@ spd_sdram(void)
 	 * Is this an ECC DDR chip?
 	 * But don't mess with it if the DDR controller will init mem.
 	 */
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+#ifdef CONFIG_DDR_ECC
 	if (spd.config == 0x02) {
+#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 		ddr->err_disable = 0x0000000d;
+#endif
 		ddr->err_sbe = 0x00ff0000;
 	}
+
 	debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
 	debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
-#endif
+#endif /* CONFIG_DDR_ECC */
 
 	asm("sync;isync;msync");
 	udelay(500);