From: James Yang Date: Tue, 12 Jan 2010 21:50:18 +0000 (-0600) Subject: ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT X-Git-Tag: v2010.03-rc1~105^2~7 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=93cedc71647b4b72ac9b48e11997eb2f91645001;p=u-boot ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RAT The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang Signed-off-by: Kumar Gala --- diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2103e2edf1..8dab8d1cf2 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -80,8 +80,8 @@ void get_sys_info (sys_info_t * sysInfo) freqCC_PLL[2] = sysclk; freqCC_PLL[3] = sysclk; - sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; - sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f); freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;