From: Liu Ying Date: Sat, 6 Oct 2012 04:16:04 +0000 (+0000) Subject: ipu common: reset ipuv3 correctly X-Git-Tag: v2013.01-rc2~139^2~10 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=945d069fb5c8932e74aeba178c60a9dc6e9cba93;p=u-boot ipu common: reset ipuv3 correctly This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond. Signed-off-by: Liu Ying --- diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 0f2d113a6f..ad4af5283a 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -94,6 +94,7 @@ struct ipu_ch_param { temp1; \ }) +#define IPU_SW_RST_TOUT_USEC (10000) void clk_enable(struct clk *clk) { @@ -398,11 +399,20 @@ void ipu_reset(void) { u32 *reg; u32 value; + int timeout = IPU_SW_RST_TOUT_USEC; reg = (u32 *)SRC_BASE_ADDR; value = __raw_readl(reg); value = value | SW_IPU_RST; __raw_writel(value, reg); + + while (__raw_readl(reg) & SW_IPU_RST) { + udelay(1); + if (!(timeout--)) { + printf("ipu software reset timeout\n"); + break; + } + }; } /*