From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Sun, 3 Aug 2014 02:32:45 +0000 (+0300)
Subject: sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions
X-Git-Tag: v2014.10-rc2~53^2~9
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=94cd3019881523b7776138f93f9e6b9849adc4d4;p=u-boot

sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions

The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---

diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 9042e9a294..4a72480425 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -36,18 +36,34 @@
 #define CPU_CFG_CHIP_REV_B 0x3
 
 /*
- * Wait up to 1s for mask to be clear in given reg.
+ * Wait up to 1s for value to be set in given part of reg.
  */
-static void await_completion(u32 *reg, u32 mask)
+static void await_completion(u32 *reg, u32 mask, u32 val)
 {
 	unsigned long tmo = timer_get_us() + 1000000;
 
-	while (readl(reg) & mask) {
+	while ((readl(reg) & mask) != val) {
 		if (timer_get_us() > tmo)
 			panic("Timeout initialising DRAM\n");
 	}
 }
 
+/*
+ * Wait up to 1s for mask to be clear in given reg.
+ */
+static inline void await_bits_clear(u32 *reg, u32 mask)
+{
+	await_completion(reg, mask, 0);
+}
+
+/*
+ * Wait up to 1s for mask to be set in given reg.
+ */
+static inline void await_bits_set(u32 *reg, u32 mask)
+{
+	await_completion(reg, mask, mask);
+}
+
 /*
  * This performs the external DRAM reset by driving the RESET pin low and
  * then high again. According to the DDR3 spec, the RESET pin needs to be
@@ -329,7 +345,7 @@ static int dramc_scan_readpipe(void)
 	setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
 	/* check whether data training process has completed */
-	await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+	await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
 
 	/* check data training result */
 	reg_val = readl(&dram->csr);
@@ -426,7 +442,7 @@ static void mctl_ddr3_initialize(void)
 {
 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
 	setbits_le32(&dram->ccr, DRAM_CCR_INIT);
-	await_completion(&dram->ccr, DRAM_CCR_INIT);
+	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
 }
 
 unsigned long dramc_init(struct dram_para *para)
@@ -495,7 +511,7 @@ unsigned long dramc_init(struct dram_para *para)
 
 	udelay(1);
 
-	await_completion(&dram->ccr, DRAM_CCR_INIT);
+	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
 
 	mctl_enable_dllx(para->tpr3);