From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
Date: Tue, 5 Dec 2006 08:42:30 +0000 (+0800)
Subject: u-boot: Fix e500 v2 core reset bug
X-Git-Tag: v1.3.0-rc1~90^2~15
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=96629cbabdb727d4a5e62542deefc01d498db6dc;p=u-boot

u-boot: Fix e500 v2 core reset bug

The following patch fixes the e500 v2 core reset bug.
For e500 v2 core, a new reset control register is added to reset the
processor.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 0507c47e6e..2fe4f2abba 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -140,16 +140,25 @@ int checkcpu (void)
 
 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
+	uint pvr;
+	uint ver;
+	pvr = get_pvr();
+	ver = PVR_VER(pvr);
+	if (ver & 1){
+	/* e500 v2 core has reset control register */
+		volatile unsigned int * rstcr;
+		rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
+		*rstcr = 0x2;           /* HRESET_REQ */
+	}else{
 	/*
 	 * Initiate hard reset in debug control register DBCR0
 	 * Make sure MSR[DE] = 1
 	 */
-	unsigned long val;
-
-	val = mfspr(DBCR0);
-	val |= 0x70000000;
-	mtspr(DBCR0,val);
-
+		unsigned long val;
+		val = mfspr(DBCR0);
+		val |= 0x70000000;
+		mtspr(DBCR0,val);
+	}
 	return 1;
 }