From: Linus Walleij <linus.walleij@linaro.org>
Date: Sun, 2 Oct 2011 11:52:52 +0000 (+0000)
Subject: serial: pl01x: drain PL01x FIFO before baudrate change
X-Git-Tag: v2011.12-rc1~499
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=96baa4c37695b4dac2bde981f59c38e7af19f2eb;p=u-boot

serial: pl01x: drain PL01x FIFO before baudrate change

Not draining the FIFO and waiting for the UART to be non-busy
before changing baudrate results in crap characters on the
console, so let's wait for the FIFO to drain and the last
character to be clocked out before we do that.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---

diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 7a064ffb24..ed581ae22b 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -194,7 +194,17 @@ int serial_tstc (void)
 
 void serial_setbrg (void)
 {
+	struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
+
 	baudrate = gd->baudrate;
+	/*
+	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
+	 * crap in console
+	 */
+	while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
+		WATCHDOG_RESET();
+	while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
+		WATCHDOG_RESET();
 	serial_init();
 }