From: richardbarry Date: Wed, 4 Sep 2013 14:22:45 +0000 (+0000) Subject: Add XMC4200 and XMC4400 build configurations to the XMC4000 Dave project. X-Git-Tag: V7.5.3~43 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=97dfcfa974c107126e929e181e74e57f588a87ec;p=freertos Add XMC4200 and XMC4400 build configurations to the XMC4000 Dave project. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2023 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.cproject b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.cproject index d5830de98..8309b16ff 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.cproject +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/.cproject @@ -3,8 +3,8 @@ - - + + @@ -18,89 +18,259 @@ - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + - + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4200.jlink b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4200.jlink new file mode 100644 index 000000000..5d3ee40a6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4200.jlink @@ -0,0 +1,31 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4400.jlink b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4400.jlink new file mode 100644 index 000000000..5d3ee40a6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4400.jlink @@ -0,0 +1,31 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4500.jlink b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4500.jlink index 5d3ee40a6..4902fa027 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4500.jlink +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/ARM_toolset_settings_XMC4500.jlink @@ -15,8 +15,8 @@ SkipProgOnCRCMatch = 1 VerifyDownload = 1 AllowCaching = 1 EnableFlashDL = 2 -Override = 0 -Device="UNSPECIFIED" +Override = 1 +Device="XMC4500-1024" [GENERAL] WorkRAMSize = 0x00 WorkRAMAddr = 0x00 diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h index 68fcedee2..8a4839bbf 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/FreeRTOSConfig.h @@ -169,7 +169,7 @@ standard names. */ #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 ) /* To toggle the single LED */ #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) -#elif defined( PART_XMC4400 ) +#elif UC_ID == 4400 /* Hardware includes. */ #include "XMC4400.h" #include "System_XMC4200.h" @@ -178,7 +178,7 @@ standard names. */ #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 ) /* To toggle the single LED */ #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 ) -#elif defined( PART_XMC4200 ) +#elif UC_ID == 4206 /* Hardware includes. */ #include "XMC4200.h" #include "System_XMC4200.h" diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/GPIO.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/GPIO.h deleted file mode 100644 index f2eebd036..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/GPIO.h +++ /dev/null @@ -1,3299 +0,0 @@ -#ifndef __GPIO_H__ -#define __GPIO_H__ - -/* Generated automatically for XMC4500_QFP144 on: Mon Jan 14 10:10:13 2013*/ - -#include - -#define INPUT 0x00U -#define INPUT_PD 0x08U -#define INPUT_PU 0x10U -#define INPUT_PPS 0x18U -#define INPUT_INV 0x20U -#define INPUT_INV_PD 0x28U -#define INPUT_INV_PU 0x30U -#define INPUT_INV_PPS 0x38U -#define OUTPUT_PP_GP 0x80U -#define OUTPUT_PP_AF1 0x88U -#define OUTPUT_PP_AF2 0x90U -#define OUTPUT_PP_AF3 0x98U -#define OUTPUT_PP_AF4 0xA0U -#define OUTPUT_OD_GP 0xC0U -#define OUTPUT_OD_AF1 0xC8U -#define OUTPUT_OD_AF2 0xD0U -#define OUTPUT_OD_AF3 0xD8U -#define OUTPUT_OD_AF4 0XE0U - -#define WEAK 0x7UL -#define MEDIUM 0x4UL -#define STRONG 0x2UL -#define VERYSTRONG 0x0UL - -#define SOFTWARE 0x0UL -#define HW0 0x1UL -#define HW1 0x2UL - -__STATIC_INLINE void P0_0_set_mode(uint8_t mode){ - PORT0->IOCR0 &= ~0x000000f8UL; - PORT0->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P0_0_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x00000007UL; - PORT0->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P0_0_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00000003UL; - PORT0->HWSEL |= config << 0; -} - -__STATIC_INLINE void P0_0_set(void){ - PORT0->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P0_0_reset(void){ - PORT0->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P0_0_toggle(void){ - PORT0->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P0_0_read(void){ - return(PORT0->IN & 0x00000001UL); -} - -__STATIC_INLINE void P0_1_set_mode(uint8_t mode){ - PORT0->IOCR0 &= ~0x0000f800UL; - PORT0->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P0_1_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x00000070UL; - PORT0->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P0_1_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x0000000cUL; - PORT0->HWSEL |= config << 2; -} - -__STATIC_INLINE void P0_1_set(void){ - PORT0->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P0_1_reset(void){ - PORT0->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P0_1_toggle(void){ - PORT0->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P0_1_read(void){ - return(PORT0->IN & 0x00000002UL); -} - -__STATIC_INLINE void P0_2_set_mode(uint8_t mode){ - PORT0->IOCR0 &= ~0x00f80000UL; - PORT0->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P0_2_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x00000700UL; - PORT0->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P0_2_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00000030UL; - PORT0->HWSEL |= config << 4; -} - -__STATIC_INLINE void P0_2_set(void){ - PORT0->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P0_2_reset(void){ - PORT0->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P0_2_toggle(void){ - PORT0->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P0_2_read(void){ - return(PORT0->IN & 0x00000004UL); -} - -__STATIC_INLINE void P0_3_set_mode(uint8_t mode){ - PORT0->IOCR0 &= ~0xf8000000UL; - PORT0->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P0_3_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x00007000UL; - PORT0->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P0_3_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x000000c0UL; - PORT0->HWSEL |= config << 6; -} - -__STATIC_INLINE void P0_3_set(void){ - PORT0->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P0_3_reset(void){ - PORT0->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P0_3_toggle(void){ - PORT0->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P0_3_read(void){ - return(PORT0->IN & 0x00000008UL); -} - -__STATIC_INLINE void P0_4_set_mode(uint8_t mode){ - PORT0->IOCR4 &= ~0x000000f8UL; - PORT0->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P0_4_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x00070000UL; - PORT0->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P0_4_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00000300UL; - PORT0->HWSEL |= config << 8; -} - -__STATIC_INLINE void P0_4_set(void){ - PORT0->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P0_4_reset(void){ - PORT0->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P0_4_toggle(void){ - PORT0->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P0_4_read(void){ - return(PORT0->IN & 0x00000010UL); -} - -__STATIC_INLINE void P0_5_set_mode(uint8_t mode){ - PORT0->IOCR4 &= ~0x0000f800UL; - PORT0->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P0_5_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x00700000UL; - PORT0->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P0_5_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00000c00UL; - PORT0->HWSEL |= config << 10; -} - -__STATIC_INLINE void P0_5_set(void){ - PORT0->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P0_5_reset(void){ - PORT0->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P0_5_toggle(void){ - PORT0->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P0_5_read(void){ - return(PORT0->IN & 0x00000020UL); -} - -__STATIC_INLINE void P0_6_set_mode(uint8_t mode){ - PORT0->IOCR4 &= ~0x00f80000UL; - PORT0->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P0_6_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x07000000UL; - PORT0->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P0_6_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00003000UL; - PORT0->HWSEL |= config << 12; -} - -__STATIC_INLINE void P0_6_set(void){ - PORT0->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P0_6_reset(void){ - PORT0->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P0_6_toggle(void){ - PORT0->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P0_6_read(void){ - return(PORT0->IN & 0x00000040UL); -} - -__STATIC_INLINE void P0_7_set_mode(uint8_t mode){ - PORT0->IOCR4 &= ~0xf8000000UL; - PORT0->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P0_7_set_driver_strength(uint8_t strength){ - PORT0->PDR0 &= ~0x70000000UL; - PORT0->PDR0 |= strength << 28; -} - -__STATIC_INLINE void P0_7_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x0000c000UL; - PORT0->HWSEL |= config << 14; -} - -__STATIC_INLINE void P0_7_set(void){ - PORT0->OMR = 0x00000080UL; -} - -__STATIC_INLINE void P0_7_reset(void){ - PORT0->OMR = 0x00800000UL; -} - -__STATIC_INLINE void P0_7_toggle(void){ - PORT0->OMR = 0x00800080UL; -} - -__STATIC_INLINE uint32_t P0_7_read(void){ - return(PORT0->IN & 0x00000080UL); -} - -__STATIC_INLINE void P0_8_set_mode(uint8_t mode){ - PORT0->IOCR8 &= ~0x000000f8UL; - PORT0->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P0_8_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x00000007UL; - PORT0->PDR1 |= strength << 0; -} - -__STATIC_INLINE void P0_8_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00030000UL; - PORT0->HWSEL |= config << 16; -} - -__STATIC_INLINE void P0_8_set(void){ - PORT0->OMR = 0x00000100UL; -} - -__STATIC_INLINE void P0_8_reset(void){ - PORT0->OMR = 0x01000000UL; -} - -__STATIC_INLINE void P0_8_toggle(void){ - PORT0->OMR = 0x01000100UL; -} - -__STATIC_INLINE uint32_t P0_8_read(void){ - return(PORT0->IN & 0x00000100UL); -} - -__STATIC_INLINE void P0_9_set_mode(uint8_t mode){ - PORT0->IOCR8 &= ~0x0000f800UL; - PORT0->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P0_9_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x00000070UL; - PORT0->PDR1 |= strength << 4; -} - -__STATIC_INLINE void P0_9_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x000c0000UL; - PORT0->HWSEL |= config << 18; -} - -__STATIC_INLINE void P0_9_set(void){ - PORT0->OMR = 0x00000200UL; -} - -__STATIC_INLINE void P0_9_reset(void){ - PORT0->OMR = 0x02000000UL; -} - -__STATIC_INLINE void P0_9_toggle(void){ - PORT0->OMR = 0x02000200UL; -} - -__STATIC_INLINE uint32_t P0_9_read(void){ - return(PORT0->IN & 0x00000200UL); -} - -__STATIC_INLINE void P0_10_set_mode(uint8_t mode){ - PORT0->IOCR8 &= ~0x00f80000UL; - PORT0->IOCR8 |= mode << 16; -} - -__STATIC_INLINE void P0_10_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x00000700UL; - PORT0->PDR1 |= strength << 8; -} - -__STATIC_INLINE void P0_10_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00300000UL; - PORT0->HWSEL |= config << 20; -} - -__STATIC_INLINE void P0_10_set(void){ - PORT0->OMR = 0x00000400UL; -} - -__STATIC_INLINE void P0_10_reset(void){ - PORT0->OMR = 0x04000000UL; -} - -__STATIC_INLINE void P0_10_toggle(void){ - PORT0->OMR = 0x04000400UL; -} - -__STATIC_INLINE uint32_t P0_10_read(void){ - return(PORT0->IN & 0x00000400UL); -} - -__STATIC_INLINE void P0_11_set_mode(uint8_t mode){ - PORT0->IOCR8 &= ~0xf8000000UL; - PORT0->IOCR8 |= mode << 24; -} - -__STATIC_INLINE void P0_11_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x00007000UL; - PORT0->PDR1 |= strength << 12; -} - -__STATIC_INLINE void P0_11_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x00c00000UL; - PORT0->HWSEL |= config << 22; -} - -__STATIC_INLINE void P0_11_set(void){ - PORT0->OMR = 0x00000800UL; -} - -__STATIC_INLINE void P0_11_reset(void){ - PORT0->OMR = 0x08000000UL; -} - -__STATIC_INLINE void P0_11_toggle(void){ - PORT0->OMR = 0x08000800UL; -} - -__STATIC_INLINE uint32_t P0_11_read(void){ - return(PORT0->IN & 0x00000800UL); -} - -__STATIC_INLINE void P0_12_set_mode(uint8_t mode){ - PORT0->IOCR12 &= ~0x000000f8UL; - PORT0->IOCR12 |= mode << 0; -} - -__STATIC_INLINE void P0_12_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x00070000UL; - PORT0->PDR1 |= strength << 16; -} - -__STATIC_INLINE void P0_12_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x03000000UL; - PORT0->HWSEL |= config << 24; -} - -__STATIC_INLINE void P0_12_set(void){ - PORT0->OMR = 0x00001000UL; -} - -__STATIC_INLINE void P0_12_reset(void){ - PORT0->OMR = 0x10000000UL; -} - -__STATIC_INLINE void P0_12_toggle(void){ - PORT0->OMR = 0x10001000UL; -} - -__STATIC_INLINE uint32_t P0_12_read(void){ - return(PORT0->IN & 0x00001000UL); -} - -__STATIC_INLINE void P0_13_set_mode(uint8_t mode){ - PORT0->IOCR12 &= ~0x0000f800UL; - PORT0->IOCR12 |= mode << 8; -} - -__STATIC_INLINE void P0_13_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x00700000UL; - PORT0->PDR1 |= strength << 20; -} - -__STATIC_INLINE void P0_13_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x0c000000UL; - PORT0->HWSEL |= config << 26; -} - -__STATIC_INLINE void P0_13_set(void){ - PORT0->OMR = 0x00002000UL; -} - -__STATIC_INLINE void P0_13_reset(void){ - PORT0->OMR = 0x20000000UL; -} - -__STATIC_INLINE void P0_13_toggle(void){ - PORT0->OMR = 0x20002000UL; -} - -__STATIC_INLINE uint32_t P0_13_read(void){ - return(PORT0->IN & 0x00002000UL); -} - -__STATIC_INLINE void P0_14_set_mode(uint8_t mode){ - PORT0->IOCR12 &= ~0x00f80000UL; - PORT0->IOCR12 |= mode << 16; -} - -__STATIC_INLINE void P0_14_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x07000000UL; - PORT0->PDR1 |= strength << 24; -} - -__STATIC_INLINE void P0_14_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0x30000000UL; - PORT0->HWSEL |= config << 28; -} - -__STATIC_INLINE void P0_14_set(void){ - PORT0->OMR = 0x00004000UL; -} - -__STATIC_INLINE void P0_14_reset(void){ - PORT0->OMR = 0x40000000UL; -} - -__STATIC_INLINE void P0_14_toggle(void){ - PORT0->OMR = 0x40004000UL; -} - -__STATIC_INLINE uint32_t P0_14_read(void){ - return(PORT0->IN & 0x00004000UL); -} - -__STATIC_INLINE void P0_15_set_mode(uint8_t mode){ - PORT0->IOCR12 &= ~0xf8000000UL; - PORT0->IOCR12 |= mode << 24; -} - -__STATIC_INLINE void P0_15_set_driver_strength(uint8_t strength){ - PORT0->PDR1 &= ~0x70000000UL; - PORT0->PDR1 |= strength << 28; -} - -__STATIC_INLINE void P0_15_set_hwsel(uint32_t config){ - PORT0->HWSEL &= ~0xc0000000UL; - PORT0->HWSEL |= config << 30; -} - -__STATIC_INLINE void P0_15_set(void){ - PORT0->OMR = 0x00008000UL; -} - -__STATIC_INLINE void P0_15_reset(void){ - PORT0->OMR = 0x80000000UL; -} - -__STATIC_INLINE void P0_15_toggle(void){ - PORT0->OMR = 0x80008000UL; -} - -__STATIC_INLINE uint32_t P0_15_read(void){ - return(PORT0->IN & 0x00008000UL); -} - -__STATIC_INLINE void P1_0_set_mode(uint8_t mode){ - PORT1->IOCR0 &= ~0x000000f8UL; - PORT1->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P1_0_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x00000007UL; - PORT1->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P1_0_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00000003UL; - PORT1->HWSEL |= config << 0; -} - -__STATIC_INLINE void P1_0_set(void){ - PORT1->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P1_0_reset(void){ - PORT1->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P1_0_toggle(void){ - PORT1->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P1_0_read(void){ - return(PORT1->IN & 0x00000001UL); -} - -__STATIC_INLINE void P1_1_set_mode(uint8_t mode){ - PORT1->IOCR0 &= ~0x0000f800UL; - PORT1->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P1_1_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x00000070UL; - PORT1->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P1_1_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x0000000cUL; - PORT1->HWSEL |= config << 2; -} - -__STATIC_INLINE void P1_1_set(void){ - PORT1->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P1_1_reset(void){ - PORT1->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P1_1_toggle(void){ - PORT1->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P1_1_read(void){ - return(PORT1->IN & 0x00000002UL); -} - -__STATIC_INLINE void P1_2_set_mode(uint8_t mode){ - PORT1->IOCR0 &= ~0x00f80000UL; - PORT1->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P1_2_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x00000700UL; - PORT1->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P1_2_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00000030UL; - PORT1->HWSEL |= config << 4; -} - -__STATIC_INLINE void P1_2_set(void){ - PORT1->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P1_2_reset(void){ - PORT1->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P1_2_toggle(void){ - PORT1->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P1_2_read(void){ - return(PORT1->IN & 0x00000004UL); -} - -__STATIC_INLINE void P1_3_set_mode(uint8_t mode){ - PORT1->IOCR0 &= ~0xf8000000UL; - PORT1->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P1_3_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x00007000UL; - PORT1->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P1_3_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x000000c0UL; - PORT1->HWSEL |= config << 6; -} - -__STATIC_INLINE void P1_3_set(void){ - PORT1->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P1_3_reset(void){ - PORT1->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P1_3_toggle(void){ - PORT1->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P1_3_read(void){ - return(PORT1->IN & 0x00000008UL); -} - -__STATIC_INLINE void P1_4_set_mode(uint8_t mode){ - PORT1->IOCR4 &= ~0x000000f8UL; - PORT1->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P1_4_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x00070000UL; - PORT1->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P1_4_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00000300UL; - PORT1->HWSEL |= config << 8; -} - -__STATIC_INLINE void P1_4_set(void){ - PORT1->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P1_4_reset(void){ - PORT1->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P1_4_toggle(void){ - PORT1->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P1_4_read(void){ - return(PORT1->IN & 0x00000010UL); -} - -__STATIC_INLINE void P1_5_set_mode(uint8_t mode){ - PORT1->IOCR4 &= ~0x0000f800UL; - PORT1->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P1_5_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x00700000UL; - PORT1->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P1_5_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00000c00UL; - PORT1->HWSEL |= config << 10; -} - -__STATIC_INLINE void P1_5_set(void){ - PORT1->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P1_5_reset(void){ - PORT1->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P1_5_toggle(void){ - PORT1->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P1_5_read(void){ - return(PORT1->IN & 0x00000020UL); -} - -__STATIC_INLINE void P1_6_set_mode(uint8_t mode){ - PORT1->IOCR4 &= ~0x00f80000UL; - PORT1->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P1_6_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x07000000UL; - PORT1->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P1_6_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00003000UL; - PORT1->HWSEL |= config << 12; -} - -__STATIC_INLINE void P1_6_set(void){ - PORT1->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P1_6_reset(void){ - PORT1->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P1_6_toggle(void){ - PORT1->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P1_6_read(void){ - return(PORT1->IN & 0x00000040UL); -} - -__STATIC_INLINE void P1_7_set_mode(uint8_t mode){ - PORT1->IOCR4 &= ~0xf8000000UL; - PORT1->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P1_7_set_driver_strength(uint8_t strength){ - PORT1->PDR0 &= ~0x70000000UL; - PORT1->PDR0 |= strength << 28; -} - -__STATIC_INLINE void P1_7_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x0000c000UL; - PORT1->HWSEL |= config << 14; -} - -__STATIC_INLINE void P1_7_set(void){ - PORT1->OMR = 0x00000080UL; -} - -__STATIC_INLINE void P1_7_reset(void){ - PORT1->OMR = 0x00800000UL; -} - -__STATIC_INLINE void P1_7_toggle(void){ - PORT1->OMR = 0x00800080UL; -} - -__STATIC_INLINE uint32_t P1_7_read(void){ - return(PORT1->IN & 0x00000080UL); -} - -__STATIC_INLINE void P1_8_set_mode(uint8_t mode){ - PORT1->IOCR8 &= ~0x000000f8UL; - PORT1->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P1_8_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x00000007UL; - PORT1->PDR1 |= strength << 0; -} - -__STATIC_INLINE void P1_8_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00030000UL; - PORT1->HWSEL |= config << 16; -} - -__STATIC_INLINE void P1_8_set(void){ - PORT1->OMR = 0x00000100UL; -} - -__STATIC_INLINE void P1_8_reset(void){ - PORT1->OMR = 0x01000000UL; -} - -__STATIC_INLINE void P1_8_toggle(void){ - PORT1->OMR = 0x01000100UL; -} - -__STATIC_INLINE uint32_t P1_8_read(void){ - return(PORT1->IN & 0x00000100UL); -} - -__STATIC_INLINE void P1_9_set_mode(uint8_t mode){ - PORT1->IOCR8 &= ~0x0000f800UL; - PORT1->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P1_9_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x00000070UL; - PORT1->PDR1 |= strength << 4; -} - -__STATIC_INLINE void P1_9_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x000c0000UL; - PORT1->HWSEL |= config << 18; -} - -__STATIC_INLINE void P1_9_set(void){ - PORT1->OMR = 0x00000200UL; -} - -__STATIC_INLINE void P1_9_reset(void){ - PORT1->OMR = 0x02000000UL; -} - -__STATIC_INLINE void P1_9_toggle(void){ - PORT1->OMR = 0x02000200UL; -} - -__STATIC_INLINE uint32_t P1_9_read(void){ - return(PORT1->IN & 0x00000200UL); -} - -__STATIC_INLINE void P1_10_set_mode(uint8_t mode){ - PORT1->IOCR8 &= ~0x00f80000UL; - PORT1->IOCR8 |= mode << 16; -} - -__STATIC_INLINE void P1_10_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x00000700UL; - PORT1->PDR1 |= strength << 8; -} - -__STATIC_INLINE void P1_10_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00300000UL; - PORT1->HWSEL |= config << 20; -} - -__STATIC_INLINE void P1_10_set(void){ - PORT1->OMR = 0x00000400UL; -} - -__STATIC_INLINE void P1_10_reset(void){ - PORT1->OMR = 0x04000000UL; -} - -__STATIC_INLINE void P1_10_toggle(void){ - PORT1->OMR = 0x04000400UL; -} - -__STATIC_INLINE uint32_t P1_10_read(void){ - return(PORT1->IN & 0x00000400UL); -} - -__STATIC_INLINE void P1_11_set_mode(uint8_t mode){ - PORT1->IOCR8 &= ~0xf8000000UL; - PORT1->IOCR8 |= mode << 24; -} - -__STATIC_INLINE void P1_11_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x00007000UL; - PORT1->PDR1 |= strength << 12; -} - -__STATIC_INLINE void P1_11_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x00c00000UL; - PORT1->HWSEL |= config << 22; -} - -__STATIC_INLINE void P1_11_set(void){ - PORT1->OMR = 0x00000800UL; -} - -__STATIC_INLINE void P1_11_reset(void){ - PORT1->OMR = 0x08000000UL; -} - -__STATIC_INLINE void P1_11_toggle(void){ - PORT1->OMR = 0x08000800UL; -} - -__STATIC_INLINE uint32_t P1_11_read(void){ - return(PORT1->IN & 0x00000800UL); -} - -__STATIC_INLINE void P1_12_set_mode(uint8_t mode){ - PORT1->IOCR12 &= ~0x000000f8UL; - PORT1->IOCR12 |= mode << 0; -} - -__STATIC_INLINE void P1_12_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x00070000UL; - PORT1->PDR1 |= strength << 16; -} - -__STATIC_INLINE void P1_12_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x03000000UL; - PORT1->HWSEL |= config << 24; -} - -__STATIC_INLINE void P1_12_set(void){ - PORT1->OMR = 0x00001000UL; -} - -__STATIC_INLINE void P1_12_reset(void){ - PORT1->OMR = 0x10000000UL; -} - -__STATIC_INLINE void P1_12_toggle(void){ - PORT1->OMR = 0x10001000UL; -} - -__STATIC_INLINE uint32_t P1_12_read(void){ - return(PORT1->IN & 0x00001000UL); -} - -__STATIC_INLINE void P1_13_set_mode(uint8_t mode){ - PORT1->IOCR12 &= ~0x0000f800UL; - PORT1->IOCR12 |= mode << 8; -} - -__STATIC_INLINE void P1_13_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x00700000UL; - PORT1->PDR1 |= strength << 20; -} - -__STATIC_INLINE void P1_13_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x0c000000UL; - PORT1->HWSEL |= config << 26; -} - -__STATIC_INLINE void P1_13_set(void){ - PORT1->OMR = 0x00002000UL; -} - -__STATIC_INLINE void P1_13_reset(void){ - PORT1->OMR = 0x20000000UL; -} - -__STATIC_INLINE void P1_13_toggle(void){ - PORT1->OMR = 0x20002000UL; -} - -__STATIC_INLINE uint32_t P1_13_read(void){ - return(PORT1->IN & 0x00002000UL); -} - -__STATIC_INLINE void P1_14_set_mode(uint8_t mode){ - PORT1->IOCR12 &= ~0x00f80000UL; - PORT1->IOCR12 |= mode << 16; -} - -__STATIC_INLINE void P1_14_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x07000000UL; - PORT1->PDR1 |= strength << 24; -} - -__STATIC_INLINE void P1_14_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0x30000000UL; - PORT1->HWSEL |= config << 28; -} - -__STATIC_INLINE void P1_14_set(void){ - PORT1->OMR = 0x00004000UL; -} - -__STATIC_INLINE void P1_14_reset(void){ - PORT1->OMR = 0x40000000UL; -} - -__STATIC_INLINE void P1_14_toggle(void){ - PORT1->OMR = 0x40004000UL; -} - -__STATIC_INLINE uint32_t P1_14_read(void){ - return(PORT1->IN & 0x00004000UL); -} - -__STATIC_INLINE void P1_15_set_mode(uint8_t mode){ - PORT1->IOCR12 &= ~0xf8000000UL; - PORT1->IOCR12 |= mode << 24; -} - -__STATIC_INLINE void P1_15_set_driver_strength(uint8_t strength){ - PORT1->PDR1 &= ~0x70000000UL; - PORT1->PDR1 |= strength << 28; -} - -__STATIC_INLINE void P1_15_set_hwsel(uint32_t config){ - PORT1->HWSEL &= ~0xc0000000UL; - PORT1->HWSEL |= config << 30; -} - -__STATIC_INLINE void P1_15_set(void){ - PORT1->OMR = 0x00008000UL; -} - -__STATIC_INLINE void P1_15_reset(void){ - PORT1->OMR = 0x80000000UL; -} - -__STATIC_INLINE void P1_15_toggle(void){ - PORT1->OMR = 0x80008000UL; -} - -__STATIC_INLINE uint32_t P1_15_read(void){ - return(PORT1->IN & 0x00008000UL); -} - -__STATIC_INLINE void P2_0_set_mode(uint8_t mode){ - PORT2->IOCR0 &= ~0x000000f8UL; - PORT2->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P2_0_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x00000007UL; - PORT2->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P2_0_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00000003UL; - PORT2->HWSEL |= config << 0; -} - -__STATIC_INLINE void P2_0_set(void){ - PORT2->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P2_0_reset(void){ - PORT2->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P2_0_toggle(void){ - PORT2->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P2_0_read(void){ - return(PORT2->IN & 0x00000001UL); -} - -__STATIC_INLINE void P2_1_set_mode(uint8_t mode){ - PORT2->IOCR0 &= ~0x0000f800UL; - PORT2->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P2_1_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x00000070UL; - PORT2->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P2_1_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x0000000cUL; - PORT2->HWSEL |= config << 2; -} - -__STATIC_INLINE void P2_1_set(void){ - PORT2->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P2_1_reset(void){ - PORT2->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P2_1_toggle(void){ - PORT2->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P2_1_read(void){ - return(PORT2->IN & 0x00000002UL); -} - -__STATIC_INLINE void P2_2_set_mode(uint8_t mode){ - PORT2->IOCR0 &= ~0x00f80000UL; - PORT2->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P2_2_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x00000700UL; - PORT2->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P2_2_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00000030UL; - PORT2->HWSEL |= config << 4; -} - -__STATIC_INLINE void P2_2_set(void){ - PORT2->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P2_2_reset(void){ - PORT2->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P2_2_toggle(void){ - PORT2->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P2_2_read(void){ - return(PORT2->IN & 0x00000004UL); -} - -__STATIC_INLINE void P2_3_set_mode(uint8_t mode){ - PORT2->IOCR0 &= ~0xf8000000UL; - PORT2->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P2_3_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x00007000UL; - PORT2->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P2_3_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x000000c0UL; - PORT2->HWSEL |= config << 6; -} - -__STATIC_INLINE void P2_3_set(void){ - PORT2->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P2_3_reset(void){ - PORT2->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P2_3_toggle(void){ - PORT2->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P2_3_read(void){ - return(PORT2->IN & 0x00000008UL); -} - -__STATIC_INLINE void P2_4_set_mode(uint8_t mode){ - PORT2->IOCR4 &= ~0x000000f8UL; - PORT2->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P2_4_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x00070000UL; - PORT2->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P2_4_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00000300UL; - PORT2->HWSEL |= config << 8; -} - -__STATIC_INLINE void P2_4_set(void){ - PORT2->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P2_4_reset(void){ - PORT2->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P2_4_toggle(void){ - PORT2->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P2_4_read(void){ - return(PORT2->IN & 0x00000010UL); -} - -__STATIC_INLINE void P2_5_set_mode(uint8_t mode){ - PORT2->IOCR4 &= ~0x0000f800UL; - PORT2->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P2_5_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x00700000UL; - PORT2->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P2_5_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00000c00UL; - PORT2->HWSEL |= config << 10; -} - -__STATIC_INLINE void P2_5_set(void){ - PORT2->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P2_5_reset(void){ - PORT2->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P2_5_toggle(void){ - PORT2->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P2_5_read(void){ - return(PORT2->IN & 0x00000020UL); -} - -__STATIC_INLINE void P2_6_set_mode(uint8_t mode){ - PORT2->IOCR4 &= ~0x00f80000UL; - PORT2->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P2_6_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x07000000UL; - PORT2->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P2_6_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00003000UL; - PORT2->HWSEL |= config << 12; -} - -__STATIC_INLINE void P2_6_set(void){ - PORT2->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P2_6_reset(void){ - PORT2->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P2_6_toggle(void){ - PORT2->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P2_6_read(void){ - return(PORT2->IN & 0x00000040UL); -} - -__STATIC_INLINE void P2_7_set_mode(uint8_t mode){ - PORT2->IOCR4 &= ~0xf8000000UL; - PORT2->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P2_7_set_driver_strength(uint8_t strength){ - PORT2->PDR0 &= ~0x70000000UL; - PORT2->PDR0 |= strength << 28; -} - -__STATIC_INLINE void P2_7_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x0000c000UL; - PORT2->HWSEL |= config << 14; -} - -__STATIC_INLINE void P2_7_set(void){ - PORT2->OMR = 0x00000080UL; -} - -__STATIC_INLINE void P2_7_reset(void){ - PORT2->OMR = 0x00800000UL; -} - -__STATIC_INLINE void P2_7_toggle(void){ - PORT2->OMR = 0x00800080UL; -} - -__STATIC_INLINE uint32_t P2_7_read(void){ - return(PORT2->IN & 0x00000080UL); -} - -__STATIC_INLINE void P2_8_set_mode(uint8_t mode){ - PORT2->IOCR8 &= ~0x000000f8UL; - PORT2->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P2_8_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x00000007UL; - PORT2->PDR1 |= strength << 0; -} - -__STATIC_INLINE void P2_8_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00030000UL; - PORT2->HWSEL |= config << 16; -} - -__STATIC_INLINE void P2_8_set(void){ - PORT2->OMR = 0x00000100UL; -} - -__STATIC_INLINE void P2_8_reset(void){ - PORT2->OMR = 0x01000000UL; -} - -__STATIC_INLINE void P2_8_toggle(void){ - PORT2->OMR = 0x01000100UL; -} - -__STATIC_INLINE uint32_t P2_8_read(void){ - return(PORT2->IN & 0x00000100UL); -} - -__STATIC_INLINE void P2_9_set_mode(uint8_t mode){ - PORT2->IOCR8 &= ~0x0000f800UL; - PORT2->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P2_9_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x00000070UL; - PORT2->PDR1 |= strength << 4; -} - -__STATIC_INLINE void P2_9_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x000c0000UL; - PORT2->HWSEL |= config << 18; -} - -__STATIC_INLINE void P2_9_set(void){ - PORT2->OMR = 0x00000200UL; -} - -__STATIC_INLINE void P2_9_reset(void){ - PORT2->OMR = 0x02000000UL; -} - -__STATIC_INLINE void P2_9_toggle(void){ - PORT2->OMR = 0x02000200UL; -} - -__STATIC_INLINE uint32_t P2_9_read(void){ - return(PORT2->IN & 0x00000200UL); -} - -__STATIC_INLINE void P2_10_set_mode(uint8_t mode){ - PORT2->IOCR8 &= ~0x00f80000UL; - PORT2->IOCR8 |= mode << 16; -} - -__STATIC_INLINE void P2_10_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x00000700UL; - PORT2->PDR1 |= strength << 8; -} - -__STATIC_INLINE void P2_10_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00300000UL; - PORT2->HWSEL |= config << 20; -} - -__STATIC_INLINE void P2_10_set(void){ - PORT2->OMR = 0x00000400UL; -} - -__STATIC_INLINE void P2_10_reset(void){ - PORT2->OMR = 0x04000000UL; -} - -__STATIC_INLINE void P2_10_toggle(void){ - PORT2->OMR = 0x04000400UL; -} - -__STATIC_INLINE uint32_t P2_10_read(void){ - return(PORT2->IN & 0x00000400UL); -} - -__STATIC_INLINE void P2_11_set_mode(uint8_t mode){ - PORT2->IOCR8 &= ~0xf8000000UL; - PORT2->IOCR8 |= mode << 24; -} - -__STATIC_INLINE void P2_11_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x00007000UL; - PORT2->PDR1 |= strength << 12; -} - -__STATIC_INLINE void P2_11_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x00c00000UL; - PORT2->HWSEL |= config << 22; -} - -__STATIC_INLINE void P2_11_set(void){ - PORT2->OMR = 0x00000800UL; -} - -__STATIC_INLINE void P2_11_reset(void){ - PORT2->OMR = 0x08000000UL; -} - -__STATIC_INLINE void P2_11_toggle(void){ - PORT2->OMR = 0x08000800UL; -} - -__STATIC_INLINE uint32_t P2_11_read(void){ - return(PORT2->IN & 0x00000800UL); -} - -__STATIC_INLINE void P2_12_set_mode(uint8_t mode){ - PORT2->IOCR12 &= ~0x000000f8UL; - PORT2->IOCR12 |= mode << 0; -} - -__STATIC_INLINE void P2_12_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x00070000UL; - PORT2->PDR1 |= strength << 16; -} - -__STATIC_INLINE void P2_12_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x03000000UL; - PORT2->HWSEL |= config << 24; -} - -__STATIC_INLINE void P2_12_set(void){ - PORT2->OMR = 0x00001000UL; -} - -__STATIC_INLINE void P2_12_reset(void){ - PORT2->OMR = 0x10000000UL; -} - -__STATIC_INLINE void P2_12_toggle(void){ - PORT2->OMR = 0x10001000UL; -} - -__STATIC_INLINE uint32_t P2_12_read(void){ - return(PORT2->IN & 0x00001000UL); -} - -__STATIC_INLINE void P2_13_set_mode(uint8_t mode){ - PORT2->IOCR12 &= ~0x0000f800UL; - PORT2->IOCR12 |= mode << 8; -} - -__STATIC_INLINE void P2_13_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x00700000UL; - PORT2->PDR1 |= strength << 20; -} - -__STATIC_INLINE void P2_13_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x0c000000UL; - PORT2->HWSEL |= config << 26; -} - -__STATIC_INLINE void P2_13_set(void){ - PORT2->OMR = 0x00002000UL; -} - -__STATIC_INLINE void P2_13_reset(void){ - PORT2->OMR = 0x20000000UL; -} - -__STATIC_INLINE void P2_13_toggle(void){ - PORT2->OMR = 0x20002000UL; -} - -__STATIC_INLINE uint32_t P2_13_read(void){ - return(PORT2->IN & 0x00002000UL); -} - -__STATIC_INLINE void P2_14_set_mode(uint8_t mode){ - PORT2->IOCR12 &= ~0x00f80000UL; - PORT2->IOCR12 |= mode << 16; -} - -__STATIC_INLINE void P2_14_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x07000000UL; - PORT2->PDR1 |= strength << 24; -} - -__STATIC_INLINE void P2_14_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0x30000000UL; - PORT2->HWSEL |= config << 28; -} - -__STATIC_INLINE void P2_14_set(void){ - PORT2->OMR = 0x00004000UL; -} - -__STATIC_INLINE void P2_14_reset(void){ - PORT2->OMR = 0x40000000UL; -} - -__STATIC_INLINE void P2_14_toggle(void){ - PORT2->OMR = 0x40004000UL; -} - -__STATIC_INLINE uint32_t P2_14_read(void){ - return(PORT2->IN & 0x00004000UL); -} - -__STATIC_INLINE void P2_15_set_mode(uint8_t mode){ - PORT2->IOCR12 &= ~0xf8000000UL; - PORT2->IOCR12 |= mode << 24; -} - -__STATIC_INLINE void P2_15_set_driver_strength(uint8_t strength){ - PORT2->PDR1 &= ~0x70000000UL; - PORT2->PDR1 |= strength << 28; -} - -__STATIC_INLINE void P2_15_set_hwsel(uint32_t config){ - PORT2->HWSEL &= ~0xc0000000UL; - PORT2->HWSEL |= config << 30; -} - -__STATIC_INLINE void P2_15_set(void){ - PORT2->OMR = 0x00008000UL; -} - -__STATIC_INLINE void P2_15_reset(void){ - PORT2->OMR = 0x80000000UL; -} - -__STATIC_INLINE void P2_15_toggle(void){ - PORT2->OMR = 0x80008000UL; -} - -__STATIC_INLINE uint32_t P2_15_read(void){ - return(PORT2->IN & 0x00008000UL); -} - -__STATIC_INLINE void P3_0_set_mode(uint8_t mode){ - PORT3->IOCR0 &= ~0x000000f8UL; - PORT3->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P3_0_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x00000007UL; - PORT3->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P3_0_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00000003UL; - PORT3->HWSEL |= config << 0; -} - -__STATIC_INLINE void P3_0_set(void){ - PORT3->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P3_0_reset(void){ - PORT3->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P3_0_toggle(void){ - PORT3->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P3_0_read(void){ - return(PORT3->IN & 0x00000001UL); -} - -__STATIC_INLINE void P3_1_set_mode(uint8_t mode){ - PORT3->IOCR0 &= ~0x0000f800UL; - PORT3->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P3_1_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x00000070UL; - PORT3->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P3_1_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x0000000cUL; - PORT3->HWSEL |= config << 2; -} - -__STATIC_INLINE void P3_1_set(void){ - PORT3->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P3_1_reset(void){ - PORT3->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P3_1_toggle(void){ - PORT3->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P3_1_read(void){ - return(PORT3->IN & 0x00000002UL); -} - -__STATIC_INLINE void P3_2_set_mode(uint8_t mode){ - PORT3->IOCR0 &= ~0x00f80000UL; - PORT3->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P3_2_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x00000700UL; - PORT3->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P3_2_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00000030UL; - PORT3->HWSEL |= config << 4; -} - -__STATIC_INLINE void P3_2_set(void){ - PORT3->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P3_2_reset(void){ - PORT3->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P3_2_toggle(void){ - PORT3->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P3_2_read(void){ - return(PORT3->IN & 0x00000004UL); -} - -__STATIC_INLINE void P3_3_set_mode(uint8_t mode){ - PORT3->IOCR0 &= ~0xf8000000UL; - PORT3->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P3_3_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x00007000UL; - PORT3->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P3_3_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x000000c0UL; - PORT3->HWSEL |= config << 6; -} - -__STATIC_INLINE void P3_3_set(void){ - PORT3->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P3_3_reset(void){ - PORT3->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P3_3_toggle(void){ - PORT3->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P3_3_read(void){ - return(PORT3->IN & 0x00000008UL); -} - -__STATIC_INLINE void P3_4_set_mode(uint8_t mode){ - PORT3->IOCR4 &= ~0x000000f8UL; - PORT3->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P3_4_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x00070000UL; - PORT3->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P3_4_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00000300UL; - PORT3->HWSEL |= config << 8; -} - -__STATIC_INLINE void P3_4_set(void){ - PORT3->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P3_4_reset(void){ - PORT3->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P3_4_toggle(void){ - PORT3->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P3_4_read(void){ - return(PORT3->IN & 0x00000010UL); -} - -__STATIC_INLINE void P3_5_set_mode(uint8_t mode){ - PORT3->IOCR4 &= ~0x0000f800UL; - PORT3->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P3_5_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x00700000UL; - PORT3->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P3_5_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00000c00UL; - PORT3->HWSEL |= config << 10; -} - -__STATIC_INLINE void P3_5_set(void){ - PORT3->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P3_5_reset(void){ - PORT3->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P3_5_toggle(void){ - PORT3->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P3_5_read(void){ - return(PORT3->IN & 0x00000020UL); -} - -__STATIC_INLINE void P3_6_set_mode(uint8_t mode){ - PORT3->IOCR4 &= ~0x00f80000UL; - PORT3->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P3_6_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x07000000UL; - PORT3->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P3_6_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00003000UL; - PORT3->HWSEL |= config << 12; -} - -__STATIC_INLINE void P3_6_set(void){ - PORT3->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P3_6_reset(void){ - PORT3->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P3_6_toggle(void){ - PORT3->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P3_6_read(void){ - return(PORT3->IN & 0x00000040UL); -} - -__STATIC_INLINE void P3_7_set_mode(uint8_t mode){ - PORT3->IOCR4 &= ~0xf8000000UL; - PORT3->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P3_7_set_driver_strength(uint8_t strength){ - PORT3->PDR0 &= ~0x70000000UL; - PORT3->PDR0 |= strength << 28; -} - -__STATIC_INLINE void P3_7_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x0000c000UL; - PORT3->HWSEL |= config << 14; -} - -__STATIC_INLINE void P3_7_set(void){ - PORT3->OMR = 0x00000080UL; -} - -__STATIC_INLINE void P3_7_reset(void){ - PORT3->OMR = 0x00800000UL; -} - -__STATIC_INLINE void P3_7_toggle(void){ - PORT3->OMR = 0x00800080UL; -} - -__STATIC_INLINE uint32_t P3_7_read(void){ - return(PORT3->IN & 0x00000080UL); -} - -__STATIC_INLINE void P3_8_set_mode(uint8_t mode){ - PORT3->IOCR8 &= ~0x000000f8UL; - PORT3->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P3_8_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x00000007UL; - PORT3->PDR1 |= strength << 0; -} - -__STATIC_INLINE void P3_8_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00030000UL; - PORT3->HWSEL |= config << 16; -} - -__STATIC_INLINE void P3_8_set(void){ - PORT3->OMR = 0x00000100UL; -} - -__STATIC_INLINE void P3_8_reset(void){ - PORT3->OMR = 0x01000000UL; -} - -__STATIC_INLINE void P3_8_toggle(void){ - PORT3->OMR = 0x01000100UL; -} - -__STATIC_INLINE uint32_t P3_8_read(void){ - return(PORT3->IN & 0x00000100UL); -} - -__STATIC_INLINE void P3_9_set_mode(uint8_t mode){ - PORT3->IOCR8 &= ~0x0000f800UL; - PORT3->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P3_9_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x00000070UL; - PORT3->PDR1 |= strength << 4; -} - -__STATIC_INLINE void P3_9_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x000c0000UL; - PORT3->HWSEL |= config << 18; -} - -__STATIC_INLINE void P3_9_set(void){ - PORT3->OMR = 0x00000200UL; -} - -__STATIC_INLINE void P3_9_reset(void){ - PORT3->OMR = 0x02000000UL; -} - -__STATIC_INLINE void P3_9_toggle(void){ - PORT3->OMR = 0x02000200UL; -} - -__STATIC_INLINE uint32_t P3_9_read(void){ - return(PORT3->IN & 0x00000200UL); -} - -__STATIC_INLINE void P3_10_set_mode(uint8_t mode){ - PORT3->IOCR8 &= ~0x00f80000UL; - PORT3->IOCR8 |= mode << 16; -} - -__STATIC_INLINE void P3_10_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x00000700UL; - PORT3->PDR1 |= strength << 8; -} - -__STATIC_INLINE void P3_10_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00300000UL; - PORT3->HWSEL |= config << 20; -} - -__STATIC_INLINE void P3_10_set(void){ - PORT3->OMR = 0x00000400UL; -} - -__STATIC_INLINE void P3_10_reset(void){ - PORT3->OMR = 0x04000000UL; -} - -__STATIC_INLINE void P3_10_toggle(void){ - PORT3->OMR = 0x04000400UL; -} - -__STATIC_INLINE uint32_t P3_10_read(void){ - return(PORT3->IN & 0x00000400UL); -} - -__STATIC_INLINE void P3_11_set_mode(uint8_t mode){ - PORT3->IOCR8 &= ~0xf8000000UL; - PORT3->IOCR8 |= mode << 24; -} - -__STATIC_INLINE void P3_11_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x00007000UL; - PORT3->PDR1 |= strength << 12; -} - -__STATIC_INLINE void P3_11_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x00c00000UL; - PORT3->HWSEL |= config << 22; -} - -__STATIC_INLINE void P3_11_set(void){ - PORT3->OMR = 0x00000800UL; -} - -__STATIC_INLINE void P3_11_reset(void){ - PORT3->OMR = 0x08000000UL; -} - -__STATIC_INLINE void P3_11_toggle(void){ - PORT3->OMR = 0x08000800UL; -} - -__STATIC_INLINE uint32_t P3_11_read(void){ - return(PORT3->IN & 0x00000800UL); -} - -__STATIC_INLINE void P3_12_set_mode(uint8_t mode){ - PORT3->IOCR12 &= ~0x000000f8UL; - PORT3->IOCR12 |= mode << 0; -} - -__STATIC_INLINE void P3_12_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x00070000UL; - PORT3->PDR1 |= strength << 16; -} - -__STATIC_INLINE void P3_12_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x03000000UL; - PORT3->HWSEL |= config << 24; -} - -__STATIC_INLINE void P3_12_set(void){ - PORT3->OMR = 0x00001000UL; -} - -__STATIC_INLINE void P3_12_reset(void){ - PORT3->OMR = 0x10000000UL; -} - -__STATIC_INLINE void P3_12_toggle(void){ - PORT3->OMR = 0x10001000UL; -} - -__STATIC_INLINE uint32_t P3_12_read(void){ - return(PORT3->IN & 0x00001000UL); -} - -__STATIC_INLINE void P3_13_set_mode(uint8_t mode){ - PORT3->IOCR12 &= ~0x0000f800UL; - PORT3->IOCR12 |= mode << 8; -} - -__STATIC_INLINE void P3_13_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x00700000UL; - PORT3->PDR1 |= strength << 20; -} - -__STATIC_INLINE void P3_13_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x0c000000UL; - PORT3->HWSEL |= config << 26; -} - -__STATIC_INLINE void P3_13_set(void){ - PORT3->OMR = 0x00002000UL; -} - -__STATIC_INLINE void P3_13_reset(void){ - PORT3->OMR = 0x20000000UL; -} - -__STATIC_INLINE void P3_13_toggle(void){ - PORT3->OMR = 0x20002000UL; -} - -__STATIC_INLINE uint32_t P3_13_read(void){ - return(PORT3->IN & 0x00002000UL); -} - -__STATIC_INLINE void P3_14_set_mode(uint8_t mode){ - PORT3->IOCR12 &= ~0x00f80000UL; - PORT3->IOCR12 |= mode << 16; -} - -__STATIC_INLINE void P3_14_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x07000000UL; - PORT3->PDR1 |= strength << 24; -} - -__STATIC_INLINE void P3_14_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0x30000000UL; - PORT3->HWSEL |= config << 28; -} - -__STATIC_INLINE void P3_14_set(void){ - PORT3->OMR = 0x00004000UL; -} - -__STATIC_INLINE void P3_14_reset(void){ - PORT3->OMR = 0x40000000UL; -} - -__STATIC_INLINE void P3_14_toggle(void){ - PORT3->OMR = 0x40004000UL; -} - -__STATIC_INLINE uint32_t P3_14_read(void){ - return(PORT3->IN & 0x00004000UL); -} - -__STATIC_INLINE void P3_15_set_mode(uint8_t mode){ - PORT3->IOCR12 &= ~0xf8000000UL; - PORT3->IOCR12 |= mode << 24; -} - -__STATIC_INLINE void P3_15_set_driver_strength(uint8_t strength){ - PORT3->PDR1 &= ~0x70000000UL; - PORT3->PDR1 |= strength << 28; -} - -__STATIC_INLINE void P3_15_set_hwsel(uint32_t config){ - PORT3->HWSEL &= ~0xc0000000UL; - PORT3->HWSEL |= config << 30; -} - -__STATIC_INLINE void P3_15_set(void){ - PORT3->OMR = 0x00008000UL; -} - -__STATIC_INLINE void P3_15_reset(void){ - PORT3->OMR = 0x80000000UL; -} - -__STATIC_INLINE void P3_15_toggle(void){ - PORT3->OMR = 0x80008000UL; -} - -__STATIC_INLINE uint32_t P3_15_read(void){ - return(PORT3->IN & 0x00008000UL); -} - -__STATIC_INLINE void P4_0_set_mode(uint8_t mode){ - PORT4->IOCR0 &= ~0x000000f8UL; - PORT4->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P4_0_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x00000007UL; - PORT4->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P4_0_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x00000003UL; - PORT4->HWSEL |= config << 0; -} - -__STATIC_INLINE void P4_0_set(void){ - PORT4->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P4_0_reset(void){ - PORT4->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P4_0_toggle(void){ - PORT4->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P4_0_read(void){ - return(PORT4->IN & 0x00000001UL); -} - -__STATIC_INLINE void P4_1_set_mode(uint8_t mode){ - PORT4->IOCR0 &= ~0x0000f800UL; - PORT4->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P4_1_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x00000070UL; - PORT4->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P4_1_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x0000000cUL; - PORT4->HWSEL |= config << 2; -} - -__STATIC_INLINE void P4_1_set(void){ - PORT4->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P4_1_reset(void){ - PORT4->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P4_1_toggle(void){ - PORT4->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P4_1_read(void){ - return(PORT4->IN & 0x00000002UL); -} - -__STATIC_INLINE void P4_2_set_mode(uint8_t mode){ - PORT4->IOCR0 &= ~0x00f80000UL; - PORT4->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P4_2_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x00000700UL; - PORT4->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P4_2_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x00000030UL; - PORT4->HWSEL |= config << 4; -} - -__STATIC_INLINE void P4_2_set(void){ - PORT4->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P4_2_reset(void){ - PORT4->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P4_2_toggle(void){ - PORT4->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P4_2_read(void){ - return(PORT4->IN & 0x00000004UL); -} - -__STATIC_INLINE void P4_3_set_mode(uint8_t mode){ - PORT4->IOCR0 &= ~0xf8000000UL; - PORT4->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P4_3_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x00007000UL; - PORT4->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P4_3_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x000000c0UL; - PORT4->HWSEL |= config << 6; -} - -__STATIC_INLINE void P4_3_set(void){ - PORT4->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P4_3_reset(void){ - PORT4->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P4_3_toggle(void){ - PORT4->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P4_3_read(void){ - return(PORT4->IN & 0x00000008UL); -} - -__STATIC_INLINE void P4_4_set_mode(uint8_t mode){ - PORT4->IOCR4 &= ~0x000000f8UL; - PORT4->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P4_4_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x00070000UL; - PORT4->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P4_4_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x00000300UL; - PORT4->HWSEL |= config << 8; -} - -__STATIC_INLINE void P4_4_set(void){ - PORT4->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P4_4_reset(void){ - PORT4->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P4_4_toggle(void){ - PORT4->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P4_4_read(void){ - return(PORT4->IN & 0x00000010UL); -} - -__STATIC_INLINE void P4_5_set_mode(uint8_t mode){ - PORT4->IOCR4 &= ~0x0000f800UL; - PORT4->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P4_5_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x00700000UL; - PORT4->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P4_5_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x00000c00UL; - PORT4->HWSEL |= config << 10; -} - -__STATIC_INLINE void P4_5_set(void){ - PORT4->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P4_5_reset(void){ - PORT4->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P4_5_toggle(void){ - PORT4->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P4_5_read(void){ - return(PORT4->IN & 0x00000020UL); -} - -__STATIC_INLINE void P4_6_set_mode(uint8_t mode){ - PORT4->IOCR4 &= ~0x00f80000UL; - PORT4->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P4_6_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x07000000UL; - PORT4->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P4_6_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x00003000UL; - PORT4->HWSEL |= config << 12; -} - -__STATIC_INLINE void P4_6_set(void){ - PORT4->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P4_6_reset(void){ - PORT4->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P4_6_toggle(void){ - PORT4->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P4_6_read(void){ - return(PORT4->IN & 0x00000040UL); -} - -__STATIC_INLINE void P4_7_set_mode(uint8_t mode){ - PORT4->IOCR4 &= ~0xf8000000UL; - PORT4->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P4_7_set_driver_strength(uint8_t strength){ - PORT4->PDR0 &= ~0x70000000UL; - PORT4->PDR0 |= strength << 28; -} - -__STATIC_INLINE void P4_7_set_hwsel(uint32_t config){ - PORT4->HWSEL &= ~0x0000c000UL; - PORT4->HWSEL |= config << 14; -} - -__STATIC_INLINE void P4_7_set(void){ - PORT4->OMR = 0x00000080UL; -} - -__STATIC_INLINE void P4_7_reset(void){ - PORT4->OMR = 0x00800000UL; -} - -__STATIC_INLINE void P4_7_toggle(void){ - PORT4->OMR = 0x00800080UL; -} - -__STATIC_INLINE uint32_t P4_7_read(void){ - return(PORT4->IN & 0x00000080UL); -} - -__STATIC_INLINE void P5_0_set_mode(uint8_t mode){ - PORT5->IOCR0 &= ~0x000000f8UL; - PORT5->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P5_0_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x00000007UL; - PORT5->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P5_0_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00000003UL; - PORT5->HWSEL |= config << 0; -} - -__STATIC_INLINE void P5_0_set(void){ - PORT5->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P5_0_reset(void){ - PORT5->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P5_0_toggle(void){ - PORT5->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P5_0_read(void){ - return(PORT5->IN & 0x00000001UL); -} - -__STATIC_INLINE void P5_1_set_mode(uint8_t mode){ - PORT5->IOCR0 &= ~0x0000f800UL; - PORT5->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P5_1_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x00000070UL; - PORT5->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P5_1_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x0000000cUL; - PORT5->HWSEL |= config << 2; -} - -__STATIC_INLINE void P5_1_set(void){ - PORT5->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P5_1_reset(void){ - PORT5->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P5_1_toggle(void){ - PORT5->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P5_1_read(void){ - return(PORT5->IN & 0x00000002UL); -} - -__STATIC_INLINE void P5_2_set_mode(uint8_t mode){ - PORT5->IOCR0 &= ~0x00f80000UL; - PORT5->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P5_2_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x00000700UL; - PORT5->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P5_2_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00000030UL; - PORT5->HWSEL |= config << 4; -} - -__STATIC_INLINE void P5_2_set(void){ - PORT5->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P5_2_reset(void){ - PORT5->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P5_2_toggle(void){ - PORT5->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P5_2_read(void){ - return(PORT5->IN & 0x00000004UL); -} - -__STATIC_INLINE void P5_3_set_mode(uint8_t mode){ - PORT5->IOCR0 &= ~0xf8000000UL; - PORT5->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P5_3_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x00007000UL; - PORT5->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P5_3_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x000000c0UL; - PORT5->HWSEL |= config << 6; -} - -__STATIC_INLINE void P5_3_set(void){ - PORT5->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P5_3_reset(void){ - PORT5->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P5_3_toggle(void){ - PORT5->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P5_3_read(void){ - return(PORT5->IN & 0x00000008UL); -} - -__STATIC_INLINE void P5_4_set_mode(uint8_t mode){ - PORT5->IOCR4 &= ~0x000000f8UL; - PORT5->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P5_4_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x00070000UL; - PORT5->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P5_4_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00000300UL; - PORT5->HWSEL |= config << 8; -} - -__STATIC_INLINE void P5_4_set(void){ - PORT5->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P5_4_reset(void){ - PORT5->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P5_4_toggle(void){ - PORT5->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P5_4_read(void){ - return(PORT5->IN & 0x00000010UL); -} - -__STATIC_INLINE void P5_5_set_mode(uint8_t mode){ - PORT5->IOCR4 &= ~0x0000f800UL; - PORT5->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P5_5_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x00700000UL; - PORT5->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P5_5_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00000c00UL; - PORT5->HWSEL |= config << 10; -} - -__STATIC_INLINE void P5_5_set(void){ - PORT5->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P5_5_reset(void){ - PORT5->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P5_5_toggle(void){ - PORT5->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P5_5_read(void){ - return(PORT5->IN & 0x00000020UL); -} - -__STATIC_INLINE void P5_6_set_mode(uint8_t mode){ - PORT5->IOCR4 &= ~0x00f80000UL; - PORT5->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P5_6_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x07000000UL; - PORT5->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P5_6_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00003000UL; - PORT5->HWSEL |= config << 12; -} - -__STATIC_INLINE void P5_6_set(void){ - PORT5->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P5_6_reset(void){ - PORT5->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P5_6_toggle(void){ - PORT5->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P5_6_read(void){ - return(PORT5->IN & 0x00000040UL); -} - -__STATIC_INLINE void P5_7_set_mode(uint8_t mode){ - PORT5->IOCR4 &= ~0xf8000000UL; - PORT5->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P5_7_set_driver_strength(uint8_t strength){ - PORT5->PDR0 &= ~0x70000000UL; - PORT5->PDR0 |= strength << 28; -} - -__STATIC_INLINE void P5_7_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x0000c000UL; - PORT5->HWSEL |= config << 14; -} - -__STATIC_INLINE void P5_7_set(void){ - PORT5->OMR = 0x00000080UL; -} - -__STATIC_INLINE void P5_7_reset(void){ - PORT5->OMR = 0x00800000UL; -} - -__STATIC_INLINE void P5_7_toggle(void){ - PORT5->OMR = 0x00800080UL; -} - -__STATIC_INLINE uint32_t P5_7_read(void){ - return(PORT5->IN & 0x00000080UL); -} - -__STATIC_INLINE void P5_8_set_mode(uint8_t mode){ - PORT5->IOCR8 &= ~0x000000f8UL; - PORT5->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P5_8_set_driver_strength(uint8_t strength){ - PORT5->PDR1 &= ~0x00000007UL; - PORT5->PDR1 |= strength << 0; -} - -__STATIC_INLINE void P5_8_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00030000UL; - PORT5->HWSEL |= config << 16; -} - -__STATIC_INLINE void P5_8_set(void){ - PORT5->OMR = 0x00000100UL; -} - -__STATIC_INLINE void P5_8_reset(void){ - PORT5->OMR = 0x01000000UL; -} - -__STATIC_INLINE void P5_8_toggle(void){ - PORT5->OMR = 0x01000100UL; -} - -__STATIC_INLINE uint32_t P5_8_read(void){ - return(PORT5->IN & 0x00000100UL); -} - -__STATIC_INLINE void P5_9_set_mode(uint8_t mode){ - PORT5->IOCR8 &= ~0x0000f800UL; - PORT5->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P5_9_set_driver_strength(uint8_t strength){ - PORT5->PDR1 &= ~0x00000070UL; - PORT5->PDR1 |= strength << 4; -} - -__STATIC_INLINE void P5_9_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x000c0000UL; - PORT5->HWSEL |= config << 18; -} - -__STATIC_INLINE void P5_9_set(void){ - PORT5->OMR = 0x00000200UL; -} - -__STATIC_INLINE void P5_9_reset(void){ - PORT5->OMR = 0x02000000UL; -} - -__STATIC_INLINE void P5_9_toggle(void){ - PORT5->OMR = 0x02000200UL; -} - -__STATIC_INLINE uint32_t P5_9_read(void){ - return(PORT5->IN & 0x00000200UL); -} - -__STATIC_INLINE void P5_10_set_mode(uint8_t mode){ - PORT5->IOCR8 &= ~0x00f80000UL; - PORT5->IOCR8 |= mode << 16; -} - -__STATIC_INLINE void P5_10_set_driver_strength(uint8_t strength){ - PORT5->PDR1 &= ~0x00000700UL; - PORT5->PDR1 |= strength << 8; -} - -__STATIC_INLINE void P5_10_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00300000UL; - PORT5->HWSEL |= config << 20; -} - -__STATIC_INLINE void P5_10_set(void){ - PORT5->OMR = 0x00000400UL; -} - -__STATIC_INLINE void P5_10_reset(void){ - PORT5->OMR = 0x04000000UL; -} - -__STATIC_INLINE void P5_10_toggle(void){ - PORT5->OMR = 0x04000400UL; -} - -__STATIC_INLINE uint32_t P5_10_read(void){ - return(PORT5->IN & 0x00000400UL); -} - -__STATIC_INLINE void P5_11_set_mode(uint8_t mode){ - PORT5->IOCR8 &= ~0xf8000000UL; - PORT5->IOCR8 |= mode << 24; -} - -__STATIC_INLINE void P5_11_set_driver_strength(uint8_t strength){ - PORT5->PDR1 &= ~0x00007000UL; - PORT5->PDR1 |= strength << 12; -} - -__STATIC_INLINE void P5_11_set_hwsel(uint32_t config){ - PORT5->HWSEL &= ~0x00c00000UL; - PORT5->HWSEL |= config << 22; -} - -__STATIC_INLINE void P5_11_set(void){ - PORT5->OMR = 0x00000800UL; -} - -__STATIC_INLINE void P5_11_reset(void){ - PORT5->OMR = 0x08000000UL; -} - -__STATIC_INLINE void P5_11_toggle(void){ - PORT5->OMR = 0x08000800UL; -} - -__STATIC_INLINE uint32_t P5_11_read(void){ - return(PORT5->IN & 0x00000800UL); -} - -__STATIC_INLINE void P6_0_set_mode(uint8_t mode){ - PORT6->IOCR0 &= ~0x000000f8UL; - PORT6->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P6_0_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x00000007UL; - PORT6->PDR0 |= strength << 0; -} - -__STATIC_INLINE void P6_0_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x00000003UL; - PORT6->HWSEL |= config << 0; -} - -__STATIC_INLINE void P6_0_set(void){ - PORT6->OMR = 0x00000001UL; -} - -__STATIC_INLINE void P6_0_reset(void){ - PORT6->OMR = 0x00010000UL; -} - -__STATIC_INLINE void P6_0_toggle(void){ - PORT6->OMR = 0x00010001UL; -} - -__STATIC_INLINE uint32_t P6_0_read(void){ - return(PORT6->IN & 0x00000001UL); -} - -__STATIC_INLINE void P6_1_set_mode(uint8_t mode){ - PORT6->IOCR0 &= ~0x0000f800UL; - PORT6->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P6_1_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x00000070UL; - PORT6->PDR0 |= strength << 4; -} - -__STATIC_INLINE void P6_1_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x0000000cUL; - PORT6->HWSEL |= config << 2; -} - -__STATIC_INLINE void P6_1_set(void){ - PORT6->OMR = 0x00000002UL; -} - -__STATIC_INLINE void P6_1_reset(void){ - PORT6->OMR = 0x00020000UL; -} - -__STATIC_INLINE void P6_1_toggle(void){ - PORT6->OMR = 0x00020002UL; -} - -__STATIC_INLINE uint32_t P6_1_read(void){ - return(PORT6->IN & 0x00000002UL); -} - -__STATIC_INLINE void P6_2_set_mode(uint8_t mode){ - PORT6->IOCR0 &= ~0x00f80000UL; - PORT6->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P6_2_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x00000700UL; - PORT6->PDR0 |= strength << 8; -} - -__STATIC_INLINE void P6_2_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x00000030UL; - PORT6->HWSEL |= config << 4; -} - -__STATIC_INLINE void P6_2_set(void){ - PORT6->OMR = 0x00000004UL; -} - -__STATIC_INLINE void P6_2_reset(void){ - PORT6->OMR = 0x00040000UL; -} - -__STATIC_INLINE void P6_2_toggle(void){ - PORT6->OMR = 0x00040004UL; -} - -__STATIC_INLINE uint32_t P6_2_read(void){ - return(PORT6->IN & 0x00000004UL); -} - -__STATIC_INLINE void P6_3_set_mode(uint8_t mode){ - PORT6->IOCR0 &= ~0xf8000000UL; - PORT6->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P6_3_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x00007000UL; - PORT6->PDR0 |= strength << 12; -} - -__STATIC_INLINE void P6_3_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x000000c0UL; - PORT6->HWSEL |= config << 6; -} - -__STATIC_INLINE void P6_3_set(void){ - PORT6->OMR = 0x00000008UL; -} - -__STATIC_INLINE void P6_3_reset(void){ - PORT6->OMR = 0x00080000UL; -} - -__STATIC_INLINE void P6_3_toggle(void){ - PORT6->OMR = 0x00080008UL; -} - -__STATIC_INLINE uint32_t P6_3_read(void){ - return(PORT6->IN & 0x00000008UL); -} - -__STATIC_INLINE void P6_4_set_mode(uint8_t mode){ - PORT6->IOCR4 &= ~0x000000f8UL; - PORT6->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P6_4_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x00070000UL; - PORT6->PDR0 |= strength << 16; -} - -__STATIC_INLINE void P6_4_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x00000300UL; - PORT6->HWSEL |= config << 8; -} - -__STATIC_INLINE void P6_4_set(void){ - PORT6->OMR = 0x00000010UL; -} - -__STATIC_INLINE void P6_4_reset(void){ - PORT6->OMR = 0x00100000UL; -} - -__STATIC_INLINE void P6_4_toggle(void){ - PORT6->OMR = 0x00100010UL; -} - -__STATIC_INLINE uint32_t P6_4_read(void){ - return(PORT6->IN & 0x00000010UL); -} - -__STATIC_INLINE void P6_5_set_mode(uint8_t mode){ - PORT6->IOCR4 &= ~0x0000f800UL; - PORT6->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P6_5_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x00700000UL; - PORT6->PDR0 |= strength << 20; -} - -__STATIC_INLINE void P6_5_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x00000c00UL; - PORT6->HWSEL |= config << 10; -} - -__STATIC_INLINE void P6_5_set(void){ - PORT6->OMR = 0x00000020UL; -} - -__STATIC_INLINE void P6_5_reset(void){ - PORT6->OMR = 0x00200000UL; -} - -__STATIC_INLINE void P6_5_toggle(void){ - PORT6->OMR = 0x00200020UL; -} - -__STATIC_INLINE uint32_t P6_5_read(void){ - return(PORT6->IN & 0x00000020UL); -} - -__STATIC_INLINE void P6_6_set_mode(uint8_t mode){ - PORT6->IOCR4 &= ~0x00f80000UL; - PORT6->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P6_6_set_driver_strength(uint8_t strength){ - PORT6->PDR0 &= ~0x07000000UL; - PORT6->PDR0 |= strength << 24; -} - -__STATIC_INLINE void P6_6_set_hwsel(uint32_t config){ - PORT6->HWSEL &= ~0x00003000UL; - PORT6->HWSEL |= config << 12; -} - -__STATIC_INLINE void P6_6_set(void){ - PORT6->OMR = 0x00000040UL; -} - -__STATIC_INLINE void P6_6_reset(void){ - PORT6->OMR = 0x00400000UL; -} - -__STATIC_INLINE void P6_6_toggle(void){ - PORT6->OMR = 0x00400040UL; -} - -__STATIC_INLINE uint32_t P6_6_read(void){ - return(PORT6->IN & 0x00000040UL); -} - -__STATIC_INLINE void P14_0_set_mode(uint8_t mode){ - PORT14->IOCR0 &= ~0x000000f8UL; - PORT14->IOCR0 |= mode << 0; -} - -__STATIC_INLINE void P14_0_enable_digital(void){ - PORT14->PDISC &= ~0x00000001UL; -} - -__STATIC_INLINE void P14_0_disable_digital(void){ - PORT14->PDISC |= 0x00000001UL; -} - -__STATIC_INLINE uint32_t P14_0_read(void){ - return(PORT14->IN & 0x00000001UL); -} - -__STATIC_INLINE void P14_1_set_mode(uint8_t mode){ - PORT14->IOCR0 &= ~0x0000f800UL; - PORT14->IOCR0 |= mode << 8; -} - -__STATIC_INLINE void P14_1_enable_digital(void){ - PORT14->PDISC &= ~0x00000002UL; -} - -__STATIC_INLINE void P14_1_disable_digital(void){ - PORT14->PDISC |= 0x00000002UL; -} - -__STATIC_INLINE uint32_t P14_1_read(void){ - return(PORT14->IN & 0x00000002UL); -} - -__STATIC_INLINE void P14_2_set_mode(uint8_t mode){ - PORT14->IOCR0 &= ~0x00f80000UL; - PORT14->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P14_2_enable_digital(void){ - PORT14->PDISC &= ~0x00000004UL; -} - -__STATIC_INLINE void P14_2_disable_digital(void){ - PORT14->PDISC |= 0x00000004UL; -} - -__STATIC_INLINE uint32_t P14_2_read(void){ - return(PORT14->IN & 0x00000004UL); -} - -__STATIC_INLINE void P14_3_set_mode(uint8_t mode){ - PORT14->IOCR0 &= ~0xf8000000UL; - PORT14->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P14_3_enable_digital(void){ - PORT14->PDISC &= ~0x00000008UL; -} - -__STATIC_INLINE void P14_3_disable_digital(void){ - PORT14->PDISC |= 0x00000008UL; -} - -__STATIC_INLINE uint32_t P14_3_read(void){ - return(PORT14->IN & 0x00000008UL); -} - -__STATIC_INLINE void P14_4_set_mode(uint8_t mode){ - PORT14->IOCR4 &= ~0x000000f8UL; - PORT14->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P14_4_enable_digital(void){ - PORT14->PDISC &= ~0x00000010UL; -} - -__STATIC_INLINE void P14_4_disable_digital(void){ - PORT14->PDISC |= 0x00000010UL; -} - -__STATIC_INLINE uint32_t P14_4_read(void){ - return(PORT14->IN & 0x00000010UL); -} - -__STATIC_INLINE void P14_5_set_mode(uint8_t mode){ - PORT14->IOCR4 &= ~0x0000f800UL; - PORT14->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P14_5_enable_digital(void){ - PORT14->PDISC &= ~0x00000020UL; -} - -__STATIC_INLINE void P14_5_disable_digital(void){ - PORT14->PDISC |= 0x00000020UL; -} - -__STATIC_INLINE uint32_t P14_5_read(void){ - return(PORT14->IN & 0x00000020UL); -} - -__STATIC_INLINE void P14_6_set_mode(uint8_t mode){ - PORT14->IOCR4 &= ~0x00f80000UL; - PORT14->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P14_6_enable_digital(void){ - PORT14->PDISC &= ~0x00000040UL; -} - -__STATIC_INLINE void P14_6_disable_digital(void){ - PORT14->PDISC |= 0x00000040UL; -} - -__STATIC_INLINE uint32_t P14_6_read(void){ - return(PORT14->IN & 0x00000040UL); -} - -__STATIC_INLINE void P14_7_set_mode(uint8_t mode){ - PORT14->IOCR4 &= ~0xf8000000UL; - PORT14->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P14_7_enable_digital(void){ - PORT14->PDISC &= ~0x00000080UL; -} - -__STATIC_INLINE void P14_7_disable_digital(void){ - PORT14->PDISC |= 0x00000080UL; -} - -__STATIC_INLINE uint32_t P14_7_read(void){ - return(PORT14->IN & 0x00000080UL); -} - -__STATIC_INLINE void P14_8_set_mode(uint8_t mode){ - PORT14->IOCR8 &= ~0x000000f8UL; - PORT14->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P14_8_enable_digital(void){ - PORT14->PDISC &= ~0x00000100UL; -} - -__STATIC_INLINE void P14_8_disable_digital(void){ - PORT14->PDISC |= 0x00000100UL; -} - -__STATIC_INLINE uint32_t P14_8_read(void){ - return(PORT14->IN & 0x00000100UL); -} - -__STATIC_INLINE void P14_9_set_mode(uint8_t mode){ - PORT14->IOCR8 &= ~0x0000f800UL; - PORT14->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P14_9_enable_digital(void){ - PORT14->PDISC &= ~0x00000200UL; -} - -__STATIC_INLINE void P14_9_disable_digital(void){ - PORT14->PDISC |= 0x00000200UL; -} - -__STATIC_INLINE uint32_t P14_9_read(void){ - return(PORT14->IN & 0x00000200UL); -} - -__STATIC_INLINE void P14_12_set_mode(uint8_t mode){ - PORT14->IOCR12 &= ~0x000000f8UL; - PORT14->IOCR12 |= mode << 0; -} - -__STATIC_INLINE void P14_12_enable_digital(void){ - PORT14->PDISC &= ~0x00001000UL; -} - -__STATIC_INLINE void P14_12_disable_digital(void){ - PORT14->PDISC |= 0x00001000UL; -} - -__STATIC_INLINE uint32_t P14_12_read(void){ - return(PORT14->IN & 0x00001000UL); -} - -__STATIC_INLINE void P14_13_set_mode(uint8_t mode){ - PORT14->IOCR12 &= ~0x0000f800UL; - PORT14->IOCR12 |= mode << 8; -} - -__STATIC_INLINE void P14_13_enable_digital(void){ - PORT14->PDISC &= ~0x00002000UL; -} - -__STATIC_INLINE void P14_13_disable_digital(void){ - PORT14->PDISC |= 0x00002000UL; -} - -__STATIC_INLINE uint32_t P14_13_read(void){ - return(PORT14->IN & 0x00002000UL); -} - -__STATIC_INLINE void P14_14_set_mode(uint8_t mode){ - PORT14->IOCR12 &= ~0x00f80000UL; - PORT14->IOCR12 |= mode << 16; -} - -__STATIC_INLINE void P14_14_enable_digital(void){ - PORT14->PDISC &= ~0x00004000UL; -} - -__STATIC_INLINE void P14_14_disable_digital(void){ - PORT14->PDISC |= 0x00004000UL; -} - -__STATIC_INLINE uint32_t P14_14_read(void){ - return(PORT14->IN & 0x00004000UL); -} - -__STATIC_INLINE void P14_15_set_mode(uint8_t mode){ - PORT14->IOCR12 &= ~0xf8000000UL; - PORT14->IOCR12 |= mode << 24; -} - -__STATIC_INLINE void P14_15_enable_digital(void){ - PORT14->PDISC &= ~0x00008000UL; -} - -__STATIC_INLINE void P14_15_disable_digital(void){ - PORT14->PDISC |= 0x00008000UL; -} - -__STATIC_INLINE uint32_t P14_15_read(void){ - return(PORT14->IN & 0x00008000UL); -} - -__STATIC_INLINE void P15_2_set_mode(uint8_t mode){ - PORT15->IOCR0 &= ~0x00f80000UL; - PORT15->IOCR0 |= mode << 16; -} - -__STATIC_INLINE void P15_2_enable_digital(void){ - PORT15->PDISC &= ~0x00000004UL; -} - -__STATIC_INLINE void P15_2_disable_digital(void){ - PORT15->PDISC |= 0x00000004UL; -} - -__STATIC_INLINE uint32_t P15_2_read(void){ - return(PORT15->IN & 0x00000004UL); -} - -__STATIC_INLINE void P15_3_set_mode(uint8_t mode){ - PORT15->IOCR0 &= ~0xf8000000UL; - PORT15->IOCR0 |= mode << 24; -} - -__STATIC_INLINE void P15_3_enable_digital(void){ - PORT15->PDISC &= ~0x00000008UL; -} - -__STATIC_INLINE void P15_3_disable_digital(void){ - PORT15->PDISC |= 0x00000008UL; -} - -__STATIC_INLINE uint32_t P15_3_read(void){ - return(PORT15->IN & 0x00000008UL); -} - -__STATIC_INLINE void P15_4_set_mode(uint8_t mode){ - PORT15->IOCR4 &= ~0x000000f8UL; - PORT15->IOCR4 |= mode << 0; -} - -__STATIC_INLINE void P15_4_enable_digital(void){ - PORT15->PDISC &= ~0x00000010UL; -} - -__STATIC_INLINE void P15_4_disable_digital(void){ - PORT15->PDISC |= 0x00000010UL; -} - -__STATIC_INLINE uint32_t P15_4_read(void){ - return(PORT15->IN & 0x00000010UL); -} - -__STATIC_INLINE void P15_5_set_mode(uint8_t mode){ - PORT15->IOCR4 &= ~0x0000f800UL; - PORT15->IOCR4 |= mode << 8; -} - -__STATIC_INLINE void P15_5_enable_digital(void){ - PORT15->PDISC &= ~0x00000020UL; -} - -__STATIC_INLINE void P15_5_disable_digital(void){ - PORT15->PDISC |= 0x00000020UL; -} - -__STATIC_INLINE uint32_t P15_5_read(void){ - return(PORT15->IN & 0x00000020UL); -} - -__STATIC_INLINE void P15_6_set_mode(uint8_t mode){ - PORT15->IOCR4 &= ~0x00f80000UL; - PORT15->IOCR4 |= mode << 16; -} - -__STATIC_INLINE void P15_6_enable_digital(void){ - PORT15->PDISC &= ~0x00000040UL; -} - -__STATIC_INLINE void P15_6_disable_digital(void){ - PORT15->PDISC |= 0x00000040UL; -} - -__STATIC_INLINE uint32_t P15_6_read(void){ - return(PORT15->IN & 0x00000040UL); -} - -__STATIC_INLINE void P15_7_set_mode(uint8_t mode){ - PORT15->IOCR4 &= ~0xf8000000UL; - PORT15->IOCR4 |= mode << 24; -} - -__STATIC_INLINE void P15_7_enable_digital(void){ - PORT15->PDISC &= ~0x00000080UL; -} - -__STATIC_INLINE void P15_7_disable_digital(void){ - PORT15->PDISC |= 0x00000080UL; -} - -__STATIC_INLINE uint32_t P15_7_read(void){ - return(PORT15->IN & 0x00000080UL); -} - -__STATIC_INLINE void P15_8_set_mode(uint8_t mode){ - PORT15->IOCR8 &= ~0x000000f8UL; - PORT15->IOCR8 |= mode << 0; -} - -__STATIC_INLINE void P15_8_enable_digital(void){ - PORT15->PDISC &= ~0x00000100UL; -} - -__STATIC_INLINE void P15_8_disable_digital(void){ - PORT15->PDISC |= 0x00000100UL; -} - -__STATIC_INLINE uint32_t P15_8_read(void){ - return(PORT15->IN & 0x00000100UL); -} - -__STATIC_INLINE void P15_9_set_mode(uint8_t mode){ - PORT15->IOCR8 &= ~0x0000f800UL; - PORT15->IOCR8 |= mode << 8; -} - -__STATIC_INLINE void P15_9_enable_digital(void){ - PORT15->PDISC &= ~0x00000200UL; -} - -__STATIC_INLINE void P15_9_disable_digital(void){ - PORT15->PDISC |= 0x00000200UL; -} - -__STATIC_INLINE uint32_t P15_9_read(void){ - return(PORT15->IN & 0x00000200UL); -} - -__STATIC_INLINE void P15_12_set_mode(uint8_t mode){ - PORT15->IOCR12 &= ~0x000000f8UL; - PORT15->IOCR12 |= mode << 0; -} - -__STATIC_INLINE void P15_12_enable_digital(void){ - PORT15->PDISC &= ~0x00001000UL; -} - -__STATIC_INLINE void P15_12_disable_digital(void){ - PORT15->PDISC |= 0x00001000UL; -} - -__STATIC_INLINE uint32_t P15_12_read(void){ - return(PORT15->IN & 0x00001000UL); -} - -__STATIC_INLINE void P15_13_set_mode(uint8_t mode){ - PORT15->IOCR12 &= ~0x0000f800UL; - PORT15->IOCR12 |= mode << 8; -} - -__STATIC_INLINE void P15_13_enable_digital(void){ - PORT15->PDISC &= ~0x00002000UL; -} - -__STATIC_INLINE void P15_13_disable_digital(void){ - PORT15->PDISC |= 0x00002000UL; -} - -__STATIC_INLINE uint32_t P15_13_read(void){ - return(PORT15->IN & 0x00002000UL); -} - -__STATIC_INLINE void P15_14_set_mode(uint8_t mode){ - PORT15->IOCR12 &= ~0x00f80000UL; - PORT15->IOCR12 |= mode << 16; -} - -__STATIC_INLINE void P15_14_enable_digital(void){ - PORT15->PDISC &= ~0x00004000UL; -} - -__STATIC_INLINE void P15_14_disable_digital(void){ - PORT15->PDISC |= 0x00004000UL; -} - -__STATIC_INLINE uint32_t P15_14_read(void){ - return(PORT15->IN & 0x00004000UL); -} - -__STATIC_INLINE void P15_15_set_mode(uint8_t mode){ - PORT15->IOCR12 &= ~0xf8000000UL; - PORT15->IOCR12 |= mode << 24; -} - -__STATIC_INLINE void P15_15_enable_digital(void){ - PORT15->PDISC &= ~0x00008000UL; -} - -__STATIC_INLINE void P15_15_disable_digital(void){ - PORT15->PDISC |= 0x00008000UL; -} - -__STATIC_INLINE uint32_t P15_15_read(void){ - return(PORT15->IN & 0x00008000UL); -} - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4200.ld b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4200.ld new file mode 100644 index 000000000..7dfbd64f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4200.ld @@ -0,0 +1,174 @@ +/* Generated Linker Script file */ +/* + * Template Version 1.2 dated 19 Nov 2012 + */ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(__Xmc4200_reset_cortex_m) +GROUP(-lxmclibcstubs) + +MEMORY +{ + FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x40000 + FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x40000 + PSRAM_1(!RX) : ORIGIN = 0x1FFFE000, LENGTH = 0x2000 + DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x6000 + SRAM_combined(!RX) : ORIGIN = 0x1FFFE000, LENGTH = 0x8000 +} + +stack_size = 2048; + +SECTIONS +{ + /* TEXT section */ + + .text : AT(ORIGIN(FLASH_1_uncached)) + { + sText = .; + *(.Xmc4200.reset); + *(.Xmc4200.postreset); + *(.XmcStartup); + *(.text .text.* .gnu.linkonce.t.*); + + /* ARM <->THUMB interworking */ + *(.glue*) + *(.v4*) + *(.vfp11_veneer) + + /* C++ Support */ + KEEP(*(.init)) + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + KEEP(*(.fini)) + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + /* Exception handling support */ + __extab_start = .; + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + __extab_end = ABSOLUTE(.); + } > FLASH_1_cached + + /* Exception handling, exidx needs a dedicated section */ + .ARM.exidx ABSOLUTE(__extab_end): AT(__extab_end | 0x04000000) + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + . = ALIGN(4); + __exidx_end = ABSOLUTE(.); + } > FLASH_1_cached + + /* CONST data section */ + .rodata ABSOLUTE(__exidx_end): AT(__exidx_end | 0x04000000) + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r*) + } > FLASH_1_cached + + . = ALIGN(16); + + /* End of RO-DATA and start of LOAD region for DATA */ + eROData = . | 0x04000000; + + /* DSRAM layout (Lowest to highest)*/ + /* Fully Descending Stack <-> BSS <-> DATA <-> HEAP */ + /* Dummy section for stack */ + Stack (NOLOAD) : + { + . = . + stack_size; + __Xmc4200_stack = .; + } > SRAM_combined + + /* BSS section */ + .bss : + { + __Xmc4200_sBSS = .; + * (.bss); + * (.bss*); + * (COMMON); + *(.gnu.linkonce.b*) + __Xmc4200_eBSS = ALIGN(4); + } > SRAM_combined + /* Yes, the size must be kept outside */ + __Xmc4200_BSS_Size = __Xmc4200_eBSS - __Xmc4200_sBSS; + + /* Standard DATA and user defined DATA/BSS/CONST sections */ + .data ABSOLUTE(ALIGN(16)): AT(eROData) + { + __Xmc4200_sData = .; + * (.data); + * (.data*); + *(*.data); + *(.gnu.linkonce.d*) + __Xmc4200_eData = ALIGN(4); + } > SRAM_combined + /* Yes, the size must be kept outside */ + __Xmc4200_Data_Size = __Xmc4200_eData - __Xmc4200_sData; + + /* Heap - Bank1*/ + __Xmc4200_heap_start = ALIGN(8); + __Xmc4200_heap_end = ORIGIN(SRAM_combined) + LENGTH (SRAM_combined); + Heap_Bank1_Start = __Xmc4200_heap_start; + Heap_Bank1_Size = __Xmc4200_heap_end - __Xmc4200_heap_start; + Heap_Bank1_End = ABSOLUTE(__Xmc4200_heap_end); + + /DISCARD/ : + { + *(.comment) + } + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_pubtypes 0 : { *(.debug_pubtypes) } + + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Build attributes */ + .build_attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4400.ld b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4400.ld new file mode 100644 index 000000000..fdf890765 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/LinkerScripts/RTOSDemo_XMC4400.ld @@ -0,0 +1,175 @@ +/* Generated Linker Script file */ +/* + * Template Version 1.2 dated 19 Nov 2012 + */ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(__Xmc4400_reset_cortex_m) +GROUP(-lxmclibcstubs) + +MEMORY +{ + FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x80000 + FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x80000 + PSRAM_1(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x4000 + DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x8000 + DSRAM_2_comm(!RX) : ORIGIN = 0x20008000, LENGTH = 0x8000 + SRAM_combined(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x14000 +} + +stack_size = 2048; + +SECTIONS +{ + /* TEXT section */ + + .text : AT(ORIGIN(FLASH_1_uncached)) + { + sText = .; + *(.Xmc4400.reset); + *(.Xmc4400.postreset); + *(.XmcStartup); + *(.text .text.* .gnu.linkonce.t.*); + + /* ARM <->THUMB interworking */ + *(.glue*) + *(.v4*) + *(.vfp11_veneer) + + /* C++ Support */ + KEEP(*(.init)) + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + KEEP(*(.fini)) + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + /* Exception handling support */ + __extab_start = .; + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + __extab_end = ABSOLUTE(.); + } > FLASH_1_cached + + /* Exception handling, exidx needs a dedicated section */ + .ARM.exidx ABSOLUTE(__extab_end): AT(__extab_end | 0x04000000) + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + . = ALIGN(4); + __exidx_end = ABSOLUTE(.); + } > FLASH_1_cached + + /* CONST data section */ + .rodata ABSOLUTE(__exidx_end): AT(__exidx_end | 0x04000000) + { + *(.rodata .rodata.*) + *(.gnu.linkonce.r*) + } > FLASH_1_cached + + . = ALIGN(16); + + /* End of RO-DATA and start of LOAD region for DATA */ + eROData = . | 0x04000000; + + /* DSRAM layout (Lowest to highest)*/ + /* Fully Descending Stack <-> BSS <-> DATA <-> HEAP */ + /* Dummy section for stack */ + Stack (NOLOAD) : + { + . = . + stack_size; + __Xmc4400_stack = .; + } > SRAM_combined + + /* BSS section */ + .bss : + { + __Xmc4400_sBSS = .; + * (.bss); + * (.bss*); + * (COMMON); + *(.gnu.linkonce.b*) + __Xmc4400_eBSS = ALIGN(4); + } > SRAM_combined + /* Yes, the size must be kept outside */ + __Xmc4400_BSS_Size = __Xmc4400_eBSS - __Xmc4400_sBSS; + + /* Standard DATA and user defined DATA/BSS/CONST sections */ + .data ABSOLUTE(ALIGN(16)): AT(eROData) + { + __Xmc4400_sData = .; + * (.data); + * (.data*); + *(*.data); + *(.gnu.linkonce.d*) + __Xmc4400_eData = ALIGN(4); + } > SRAM_combined + /* Yes, the size must be kept outside */ + __Xmc4400_Data_Size = __Xmc4400_eData - __Xmc4400_sData; + + /* Heap - Bank1*/ + __Xmc4400_heap_start = ALIGN(8); + __Xmc4400_heap_end = ORIGIN(SRAM_combined) + LENGTH (SRAM_combined); + Heap_Bank1_Start = __Xmc4400_heap_start; + Heap_Bank1_Size = __Xmc4400_heap_end - __Xmc4400_heap_start; + Heap_Bank1_End = ABSOLUTE(__Xmc4400_heap_end); + + /DISCARD/ : + { + *(.comment) + } + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_pubtypes 0 : { *(.debug_pubtypes) } + + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Build attributes */ + .build_attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4200.c new file mode 100644 index 000000000..d2385b4b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4200.c @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file system_XMC4200.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4000 Device Series + * @version V3.0.1 Alpha + * @date 26. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 80000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 5 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 5 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4400.c new file mode 100644 index 000000000..70162d923 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/System_XMC4400.c @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file system_XMC4400.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4200.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4200.s new file mode 100644 index 000000000..951dd5707 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4200.s @@ -0,0 +1,559 @@ +/*****************************************************************************/ +/* Startup_XMC4200.s: Startup file for XMC4200 device series */ +/*****************************************************************************/ + +/* ********************* Version History *********************************** */ +/* *************************************************************************** +V0.1 , Sep, 13, 2012 ES : initial version +V0.2 , Oct, 12, 2012 PKB: C++ support +V0.3 , Jan, 26, 2013 PKB: Workaround for prefetch bug +**************************************************************************** */ +/** +* @file Startup_XMC4200.s +* XMC4000 Device Series +* @version V0.3 +* @date Jan 2013 +* +Copyright (C) 2013 Infineon Technologies AG. All rights reserved. +* +* +* @par +* Infineon Technologies AG (Infineon) is supplying this software for use with +* Infineon's microcontrollers. This file can be freely distributed +* within development tools that are supporting such microcontrollers. +* +* @par +* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +* +******************************************************************************/ +#include + +/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ +/* + * STEP_AB and below have the prefetch bug. A veneer defined below will first + * be executed which in turn branches to the final exception handler. + * + * In addition to defining the veneers, the vector table must for these buggy + * devices contain the veneers. + */ + +/* A macro to setup a vector table entry based on STEP ID */ +.macro Entry Handler + #if (UC_STEP > STEP_AA) + .long \Handler + #else + .long \Handler\()_Veneer + #endif +.endm + +/* A macro to ease definition of the various handlers based on STEP ID */ +#if (UC_STEP == STEP_AA) + /* First define the final exception handler */ + .macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func + .type \Handler_Func, %function + \Handler_Func: + B . + .size \Handler_Func, . - \Handler_Func + + /* And then define a veneer that will branch to the final excp handler */ + .weak \Handler_Func\()_Veneer + .type \Handler_Func\()_Veneer, %function + \Handler_Func\()_Veneer: + LDR R0, =\Handler_Func + PUSH {LR} + BLX R0 + POP {PC} + .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer + .endm +#else + /* No prefetch bug, hence define only the final exception handler */ + .macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func + .type \Handler_Func, %function + \Handler_Func: + B . + .size \Handler_Func, . - \Handler_Func + .endm +#endif +/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ + +/* ================== START OF VECTOR TABLE DEFINITION ====================== */ +/* Vector Table - This gets programed into VTOR register by onchip BootROM */ + .syntax unified + + .section ".Xmc4200.reset" + .globl __Xmc4200_interrupt_vector_cortex_m + .type __Xmc4200_interrupt_vector_cortex_m, %object + +__Xmc4200_interrupt_vector_cortex_m: + .long __Xmc4200_stack /* Top of Stack */ + .long __Xmc4200_reset_cortex_m /* Reset Handler */ + + Entry NMI_Handler /* NMI Handler */ + Entry HardFault_Handler /* Hard Fault Handler */ + Entry MemManage_Handler /* MPU Fault Handler */ + Entry BusFault_Handler /* Bus Fault Handler */ + Entry UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + Entry DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */ + Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ + Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ + Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ + Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ + Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ + Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ + Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ + Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ + Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ + .long 0 /* Not Available */ + Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ + Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ + Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ + Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ + Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ + Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ + Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ + Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ + Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ + Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ + Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */ + Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ + Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ + Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ + Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ + Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ + Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ + Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ + Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ + Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ + Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ + Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ + Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */ + Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */ + Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */ + Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */ + Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ + Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ + Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ + Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ + Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ + Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ + Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ + Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ + Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ + Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ + Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ + Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ + Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ + Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ + Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ + Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ + Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ + Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ + Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ + Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ + .long 0 /* Not Available */ + Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ + Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ + .long 0 /* Not Available */ + Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + + .size __Xmc4200_interrupt_vector_cortex_m, . - __Xmc4200_interrupt_vector_cortex_m +/* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +/* ================== START OF VECTOR ROUTINES ============================= */ + .thumb +/* ======================================================================== */ +/* Reset Handler */ + + .thumb_func + .globl __Xmc4200_reset_cortex_m + .type __Xmc4200_reset_cortex_m, %function +__Xmc4200_reset_cortex_m: + .fnstart + + /* C routines are likely to be called. Setup the stack now */ + /* This is already setup by BootROM,hence this step is optional */ + LDR SP,=__Xmc4200_stack + + /* Clock tree, External memory setup etc may be done here */ + LDR R0, =SystemInit + BLX R0 + +/* + SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is + weakly defined here though for a potential override. +*/ + LDR R0, =SystemInit_DAVE3 + BLX R0 + + B __Xmc4200_Program_Loader + + .pool + .cantunwind + .fnend + .size __Xmc4200_reset_cortex_m,.-__Xmc4200_reset_cortex_m +/* ======================================================================== */ +/* __Xmc4200_reset must yield control to __Xmc4200_Program_Loader before control + to C land is given */ + .section .Xmc4200.postreset,"x",%progbits + __Xmc4200_Program_Loader: + .fnstart + /* Memories are accessible now*/ + + /* DATA COPY */ + /* R0 = Start address, R1 = Destination address, R2 = Size */ + LDR R0, =eROData + LDR R1, =__Xmc4200_sData + LDR R2, =__Xmc4200_Data_Size + + /* Is there anything to be copied? */ + CMP R2,#0 + BEQ SKIPCOPY + + /* For bytecount less than 4, at least 1 word must be copied */ + CMP R2,#4 + BCS STARTCOPY + + /* Byte count < 4 ; so bump it up */ + MOV R2,#4 + +STARTCOPY: + /* + R2 contains byte count. Change it to word count. It is ensured in the + linker script that the length is always word aligned. + */ + LSR R2,R2,#2 /* Divide by 4 to obtain word count */ + + /* The proverbial loop from the schooldays */ +COPYLOOP: + LDR R3,[R0] + STR R3,[R1] + SUBS R2,#1 + BEQ SKIPCOPY + ADD R0,#4 + ADD R1,#4 + B COPYLOOP + +SKIPCOPY: + /* BSS CLEAR */ + LDR R0, =__Xmc4200_sBSS /* Start of BSS */ + LDR R1, =__Xmc4200_BSS_Size /* BSS size in bytes */ + + /* Find out if there are items assigned to BSS */ + CMP R1,#0 + BEQ SKIPCLEAR + + /* At least 1 word must be copied */ + CMP R1,#4 + BCS STARTCLEAR + + /* Byte count < 4 ; so bump it up to a word*/ + MOV R1,#4 + +STARTCLEAR: + LSR R1,R1,#2 /* BSS size in words */ + + MOV R2,#0 +CLEARLOOP: + STR R2,[R0] + SUBS R1,#1 + BEQ SKIPCLEAR + ADD R0,#4 + B CLEARLOOP + +SKIPCLEAR: + /* Remap vector table */ + /* This is already setup by BootROM,hence this step is optional */ + LDR R0, =__Xmc4200_interrupt_vector_cortex_m + LDR R1, =SCB_VTOR + STR R0,[R1] + + /* Update System Clock */ + LDR R0,=SystemCoreClockUpdate + BLX R0 + + /* C++ : Call the global constructor */ + LDR R0,=__libc_init_array + BLX R0 + + /* Reset stack pointer before zipping off to user application, Optional */ + LDR SP,=__Xmc4200_stack + MOV R0,#0 + MOV R1,#0 + LDR PC, =main + .pool + .cantunwind + .fnend + .size __Xmc4200_Program_Loader,.-__Xmc4200_Program_Loader +/* ======================================================================== */ +/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* Default exception Handlers - Users may override this default functionality by + defining handlers of the same name in their C code */ + .thumb + .text + + Insert_ExceptionHandler NMI_Handler +/* ======================================================================== */ + Insert_ExceptionHandler HardFault_Handler +/* ======================================================================== */ + Insert_ExceptionHandler MemManage_Handler +/* ======================================================================== */ + Insert_ExceptionHandler BusFault_Handler +/* ======================================================================== */ + Insert_ExceptionHandler UsageFault_Handler +/* ======================================================================== */ + Insert_ExceptionHandler SVC_Handler +/* ======================================================================== */ + Insert_ExceptionHandler DebugMon_Handler +/* ======================================================================== */ + Insert_ExceptionHandler PendSV_Handler +/* ======================================================================== */ + Insert_ExceptionHandler SysTick_Handler + +/* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +/* IRQ Handlers */ + Insert_ExceptionHandler SCU_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler PMU0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DAC0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DAC0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler POSIF0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler POSIF0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_6_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_7_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler LEDTS0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler FCE0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler GPDMA0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USB0_0_IRQHandler +/* ======================================================================== */ +/* ======================================================================== */ + +/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +/* ========= Decision function queried by CMSIS startup for PLL setup ======== */ +/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock + tree setup. + + This decision routine defined here will always return TRUE. + + When overridden by a definition defined in DAVE code engine, this routine + returns FALSE indicating that the code engine has performed the clock setup +*/ + .weak AllowPLLInitByStartup + .type AllowPLLInitByStartup, %function +AllowPLLInitByStartup: + MOV R0,#1 + BX LR + .size AllowPLLInitByStartup, . - AllowPLLInitByStartup + +/* ====== Definition of the default weak SystemInit_DAVE3 function ========= +If DAVE3 requires an extended SystemInit it will create its own version of +SystemInit_DAVE3 which overrides this weak definition. Example includes +setting up of external memory interfaces. +*/ + .section ".XmcStartup" + .weak SystemInit_DAVE3 + .type SystemInit_DAVE3, %function +SystemInit_DAVE3: + NOP + BX LR + .size SystemInit_DAVE3, . - SystemInit_DAVE3 +/* ======================================================================== */ +/* ======================================================================== */ + +/* ======================== Data references =============================== */ +.equ SCB_VTOR, 0xE000ED08 +.equ PREF_PCON, 0x58004000 +.equ SCU_GCU_PEEN, 0x5000413C +.equ SCU_GCU_PEFLAG, 0x50004150 +.equ FLASH_FCON, 0x58002014 + + .end diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4400.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4400.s new file mode 100644 index 000000000..b6457ab5a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/Startup/startup_XMC4400.s @@ -0,0 +1,621 @@ +/*****************************************************************************/ +/* Startup_XMC4400.s: Startup file for XMC4400 device series */ +/*****************************************************************************/ + +/* ********************* Version History *********************************** */ +/* *************************************************************************** +V0.1 , Aug, 13, 2012 ES: initial version +V0.2 , Oct, 12, 2012 PKB: C++ support +V0.3 , Jan, 25, 2013 PKB: Prefetch bug workaround for STEP_AA +**************************************************************************** */ +/** +* @file Startup_XMC4400.s +* XMC4000 Device Series +* @version V0.3 +* @date Jan 2013 +* +Copyright (C) 2013 Infineon Technologies AG. All rights reserved. +* +* +* @par +* Infineon Technologies AG (Infineon) is supplying this software for use with +* Infineon's microcontrollers. This file can be freely distributed +* within development tools that are supporting such microcontrollers. +* +* @par +* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +* +******************************************************************************/ +#include + +/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ +/* + * STEP_AB and below have the prefetch bug. A veneer defined below will first + * be executed which in turn branches to the final exception handler. + * + * In addition to defining the veneers, the vector table must for these buggy + * devices contain the veneers. + */ + +/* A macro to setup a vector table entry based on STEP ID */ +.macro Entry Handler + #if (UC_STEP > STEP_AA) + .long \Handler + #else + .long \Handler\()_Veneer + #endif +.endm + +/* A macro to ease definition of the various handlers based on STEP ID */ +#if (UC_STEP == STEP_AA) + /* First define the final exception handler */ + .macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func + .type \Handler_Func, %function + \Handler_Func: + B . + .size \Handler_Func, . - \Handler_Func + + /* And then define a veneer that will branch to the final excp handler */ + .weak \Handler_Func\()_Veneer + .type \Handler_Func\()_Veneer, %function + \Handler_Func\()_Veneer: + LDR R0, =\Handler_Func + PUSH {LR} + BLX R0 + POP {PC} + .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer + .endm +#else + /* No prefetch bug, hence define only the final exception handler */ + .macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func + .type \Handler_Func, %function + \Handler_Func: + B . + .size \Handler_Func, . - \Handler_Func + .endm +#endif +/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ +/* ================== START OF VECTOR TABLE DEFINITION ====================== */ +/* Vector Table - This gets programed into VTOR register by onchip BootROM */ + .syntax unified + + .section ".Xmc4400.reset" + .globl __Xmc4400_interrupt_vector_cortex_m + .type __Xmc4400_interrupt_vector_cortex_m, %object + +__Xmc4400_interrupt_vector_cortex_m: + .long __Xmc4400_stack /* Top of Stack */ + .long __Xmc4400_reset_cortex_m /* Reset Handler */ + + Entry NMI_Handler /* NMI Handler */ + Entry HardFault_Handler /* Hard Fault Handler */ + Entry MemManage_Handler /* MPU Fault Handler */ + Entry BusFault_Handler /* Bus Fault Handler */ + Entry UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + Entry DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals */ + Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ + Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ + Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ + Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ + Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ + Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ + Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ + Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ + Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ + .long 0 /* Not Available */ + Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ + Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ + Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ + Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ + Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ + Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ + Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ + Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ + Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ + Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ + Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */ + Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */ + Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */ + Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */ + Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */ + Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */ + Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */ + Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */ + Entry DSD0_0_IRQHandler /* Handler name for SR DSD_SRM_0 */ + Entry DSD0_1_IRQHandler /* Handler name for SR DSD_SRM_1 */ + Entry DSD0_2_IRQHandler /* Handler name for SR DSD_SRM_2 */ + Entry DSD0_3_IRQHandler /* Handler name for SR DSD_SRM_3 */ + Entry DSD0_4_IRQHandler /* Handler name for SR DSD_SRA_0 */ + Entry DSD0_5_IRQHandler /* Handler name for SR DSD_SRA_1 */ + Entry DSD0_6_IRQHandler /* Handler name for SR DSD_SRA_2 */ + Entry DSD0_7_IRQHandler /* Handler name for SR DSD_SRA_3 */ + Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ + Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */ + Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ + Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ + Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ + Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ + Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ + Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ + Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ + Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ + Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */ + Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */ + Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */ + Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */ + Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */ + Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */ + Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */ + Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */ + Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ + Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ + Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ + Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ + Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */ + Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */ + Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */ + Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */ + Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ + Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ + Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */ + Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */ + Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */ + Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */ + Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */ + Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */ + Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ + Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ + Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ + Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ + Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ + Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ + Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ + Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ + Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ + Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ + Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ + Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ + Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ + Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ + Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ + Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ + Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ + Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ + Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ + Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ + .long 0 /* Not Available */ + Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ + Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ + .long 0 /* Not Available */ + Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ + Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + + .size __Xmc4400_interrupt_vector_cortex_m, . - __Xmc4400_interrupt_vector_cortex_m +/* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +/* ================== START OF VECTOR ROUTINES ============================= */ + .thumb +/* ======================================================================== */ +/* Reset Handler */ + + .thumb_func + .globl __Xmc4400_reset_cortex_m + .type __Xmc4400_reset_cortex_m, %function +__Xmc4400_reset_cortex_m: + .fnstart + + /* C routines are likely to be called. Setup the stack now */ + /* This is already setup by BootROM,hence this step is optional */ + LDR SP,=__Xmc4400_stack + + /* Clock tree, External memory setup etc may be done here */ + LDR R0, =SystemInit + BLX R0 + +/* + SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is + weakly defined here though for a potential override. +*/ + LDR R0, =SystemInit_DAVE3 + BLX R0 + + B __Xmc4400_Program_Loader + + .pool + .cantunwind + .fnend + .size __Xmc4400_reset_cortex_m,.-__Xmc4400_reset_cortex_m +/* ======================================================================== */ +/* __Xmc4400_reset must yield control to __Xmc4400_Program_Loader before control + to C land is given */ + .section .Xmc4400.postreset,"x",%progbits + __Xmc4400_Program_Loader: + .fnstart + /* Memories are accessible now*/ + + /* DATA COPY */ + /* R0 = Start address, R1 = Destination address, R2 = Size */ + LDR R0, =eROData + LDR R1, =__Xmc4400_sData + LDR R2, =__Xmc4400_Data_Size + + /* Is there anything to be copied? */ + CMP R2,#0 + BEQ SKIPCOPY + + /* For bytecount less than 4, at least 1 word must be copied */ + CMP R2,#4 + BCS STARTCOPY + + /* Byte count < 4 ; so bump it up */ + MOV R2,#4 + +STARTCOPY: + /* + R2 contains byte count. Change it to word count. It is ensured in the + linker script that the length is always word aligned. + */ + LSR R2,R2,#2 /* Divide by 4 to obtain word count */ + + /* The proverbial loop from the schooldays */ +COPYLOOP: + LDR R3,[R0] + STR R3,[R1] + SUBS R2,#1 + BEQ SKIPCOPY + ADD R0,#4 + ADD R1,#4 + B COPYLOOP + +SKIPCOPY: + /* BSS CLEAR */ + LDR R0, =__Xmc4400_sBSS /* Start of BSS */ + LDR R1, =__Xmc4400_BSS_Size /* BSS size in bytes */ + + /* Find out if there are items assigned to BSS */ + CMP R1,#0 + BEQ SKIPCLEAR + + /* At least 1 word must be copied */ + CMP R1,#4 + BCS STARTCLEAR + + /* Byte count < 4 ; so bump it up to a word*/ + MOV R1,#4 + +STARTCLEAR: + LSR R1,R1,#2 /* BSS size in words */ + + MOV R2,#0 +CLEARLOOP: + STR R2,[R0] + SUBS R1,#1 + BEQ SKIPCLEAR + ADD R0,#4 + B CLEARLOOP + +SKIPCLEAR: + /* Remap vector table */ + /* This is already setup by BootROM,hence this step is optional */ + LDR R0, =__Xmc4400_interrupt_vector_cortex_m + LDR R1, =SCB_VTOR + STR R0,[R1] + + /* Update System Clock */ + LDR R0,=SystemCoreClockUpdate + BLX R0 + + /* C++ : Call the global constructor */ + LDR R0,=__libc_init_array + BLX R0 + + /* Reset stack pointer before zipping off to user application, Optional */ + LDR SP,=__Xmc4400_stack + MOV R0,#0 + MOV R1,#0 + LDR PC, =main + .pool + .cantunwind + .fnend + .size __Xmc4400_Program_Loader,.-__Xmc4400_Program_Loader +/* ======================================================================== */ +/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* Default exception Handlers - Users may override this default functionality by + defining handlers of the same name in their C code */ + .thumb + .text + + Insert_ExceptionHandler NMI_Handler +/* ======================================================================== */ + Insert_ExceptionHandler HardFault_Handler +/* ======================================================================== */ + Insert_ExceptionHandler MemManage_Handler +/* ======================================================================== */ + Insert_ExceptionHandler BusFault_Handler +/* ======================================================================== */ + Insert_ExceptionHandler UsageFault_Handler +/* ======================================================================== */ + Insert_ExceptionHandler SVC_Handler +/* ======================================================================== */ + Insert_ExceptionHandler DebugMon_Handler +/* ======================================================================== */ + Insert_ExceptionHandler PendSV_Handler +/* ======================================================================== */ + Insert_ExceptionHandler SysTick_Handler +/* ======================================================================== */ + +/* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +/* IRQ Handlers */ + Insert_ExceptionHandler SCU_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ERU1_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler PMU0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_C0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G1_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G2_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G2_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G2_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G2_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G3_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G3_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G3_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler VADC0_G3_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_6_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DSD0_7_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DAC0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler DAC0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU40_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU41_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU42_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU42_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU42_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU42_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU43_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU43_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU43_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU43_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU80_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU81_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU81_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU81_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CCU81_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler POSIF0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler POSIF0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler POSIF1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler POSIF1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler HRPWM_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_6_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler CAN0_7_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC0_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_1_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_2_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_3_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_4_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USIC1_5_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler LEDTS0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler FCE0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler GPDMA0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler USB0_0_IRQHandler +/* ======================================================================== */ + Insert_ExceptionHandler ETH0_0_IRQHandler +/* ======================================================================== */ +/* ======================================================================== */ + +/* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +/* ========= Decision function queried by CMSIS startup for PLL setup ======== */ +/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock + tree setup. + + This decision routine defined here will always return TRUE. + + When overridden by a definition defined in DAVE code engine, this routine + returns FALSE indicating that the code engine has performed the clock setup +*/ + .weak AllowPLLInitByStartup + .type AllowPLLInitByStartup, %function +AllowPLLInitByStartup: + MOV R0,#1 + BX LR + .size AllowPLLInitByStartup, . - AllowPLLInitByStartup + +/* ====== Definition of the default weak SystemInit_DAVE3 function ========= +If DAVE3 requires an extended SystemInit it will create its own version of +SystemInit_DAVE3 which overrides this weak definition. Example includes +setting up of external memory interfaces. +*/ + .section ".XmcStartup" + .weak SystemInit_DAVE3 + .type SystemInit_DAVE3, %function +SystemInit_DAVE3: + NOP + BX LR + .size SystemInit_DAVE3, . - SystemInit_DAVE3 +/* ======================================================================== */ +/* ======================================================================== */ + +/* ======================== Data references =============================== */ +.equ SCB_VTOR, 0xE000ED08 +.equ PREF_PCON, 0x58004000 +.equ SCU_GCU_PEEN, 0x5000413C +.equ SCU_GCU_PEFLAG, 0x50004150 +.equ FLASH_FCON, 0x58002014 + + .end diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/System_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/System_XMC4500.h new file mode 100644 index 000000000..73eb6d590 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/System_XMC4500.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file system_XMC4500.h + * @brief Header file for the XMC4500-Series systeminit + * + * @version V1.6 + * @date 23. October 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4500_H +#define __SYSTEM_XMC4500_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 + + + +/* + * mandatory clock parameters ************************************************** + */ +/* source for clock generation + * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) + * mandatory for old system_xmc4500.c files - please do not remove!!! + **************************************************************************************/ + +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +#define CLOCK_OSC_HP 24000000 +#define CLOCK_BACK_UP 24000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define SYSTEM_FREQUENCY 120000000 + +/* OSC_HP setup parameters */ +#define OSC_HP_MODE 0 +#define OSCHPWDGDIV 2 + +/* MAIN PLL setup parameters */ + + +#define PLL_K1DIV 1 +#define PLL_K2DIV 3 +#define PLL_PDIV 1 +#define PLL_NDIV 79 + + + +#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz +#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz +#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz + + + +#define USBPLL_PDIV 1 +#define USBPLL_NDIV 15 + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/XMC4200.h new file mode 100644 index 000000000..3984b45cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/XMC4200.h @@ -0,0 +1,13138 @@ + +/****************************************************************************************************//** + * @file XMC4200.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * XMC4200 from Infineon. + * + * @version V1.1.0 (Reference Manual v1.1) + * @date 10. January 2013 + * + * @note Generated with SVDConv V2.78b + * from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1), + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC4200 + * @{ + */ + +#ifndef XMC4200_H +#define XMC4200_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC4200 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< 0 SCU_0 */ + ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */ + ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */ + ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */ + ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */ + ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */ + ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */ + ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */ + ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */ + PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */ + VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */ + VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */ + VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */ + VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */ + VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */ + VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */ + VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */ + VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */ + VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */ + VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */ + VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */ + VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */ + DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */ + DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */ + CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */ + CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */ + CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */ + CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */ + CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */ + CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */ + CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */ + CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */ + CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */ + CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */ + CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */ + CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */ + POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */ + POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */ + HRPWM_0_IRQn = 72, /*!< 72 HRPWM_0 */ + HRPWM_1_IRQn = 73, /*!< 73 HRPWM_1 */ + HRPWM_2_IRQn = 74, /*!< 74 HRPWM_0 */ + HRPWM_3_IRQn = 75, /*!< 75 HRPWM_1 */ + CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */ + CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */ + CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */ + CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */ + CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */ + CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */ + CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */ + CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */ + USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */ + USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */ + USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */ + USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */ + USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */ + USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */ + USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */ + USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */ + USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */ + USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */ + USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */ + USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */ + LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */ + FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */ + GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */ + USB0_0_IRQn = 107, /*!< 107 USB0_0 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4200.h" /*!< XMC4200 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4400.h" /*!< XMC4400 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4500.h" /*!< XMC4500 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/system_XMC4400.h new file mode 100644 index 000000000..953e1b099 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/System/system_XMC4400.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_XMC4400.h + * @brief Header file for the XMC4400-Series systeminit + * + * @version V1.0 + * @date 17. August 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4400_H +#define __SYSTEM_XMC4400_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c index 44ba2da83..0e24f3c59 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c @@ -648,6 +648,13 @@ static void prvRegTest2Task( void *pvParameters ) " ldr r1, [r0] \n" " adds r1, r1, #1 \n" " str r1, [r0] \n" + " \n" + " /* Yield to increase test coverage. */ \n" + " movs r0, #0x01 \n" + " ldr r1, =0xe000ed04 \n" /*NVIC_INT_CTRL */ + " lsl r0, #28 \n" /* Shift to PendSV bit */ + " str r0, [r1] \n" + " dsb \n" " pop { r0-r1 } \n" " \n" " /* Start again. */ \n"