From: Fabio Estevam Date: Tue, 29 Apr 2014 13:15:46 +0000 (-0300) Subject: iomux-v3: Add support for mx6sl LVE bit X-Git-Tag: v2014.07-rc2~9^2~3^2~9 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=98d2cffd23503225108e0ceb36dbe6b1bbd93ed6;p=u-boot iomux-v3: Add support for mx6sl LVE bit On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam Tested-by: Otavio Salvador --- diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802830..6e46ea8dcd 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; +#if defined CONFIG_MX6SL + /* Check whether LVE bit needs to be set */ + if (pad_ctrl & PAD_CTL_LVE) { + pad_ctrl &= ~PAD_CTL_LVE; + pad_ctrl |= PAD_CTL_LVE_BIT; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dec11a1330..cca920b28e 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#if defined CONFIG_MX6SL +#define PAD_CTL_LVE (1 << 1) +#define PAD_CTL_LVE_BIT (1 << 22) +#endif + #elif defined(CONFIG_VF610) #define PAD_MUX_MODE_SHIFT 20