From: Dave Liu <daveliu@freescale.com>
Date: Tue, 8 Dec 2009 03:56:48 +0000 (+0800)
Subject: fsl-ddr: Add extra cycle to turnaround times
X-Git-Tag: v2010.06-rc1~77^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=99bac479dd183529f4e259a0de8d31644219d487;p=u-boot

fsl-ddr: Add extra cycle to turnaround times

Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 03f9c4380d..4a282bc52d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	taxpd_mclk = 8;
 	tmrd_mclk = 4;
+	/* set the turnaround time */
+	trwt_mclk = 1;
 #else /* CONFIG_FSL_DDR2 */
 	/*
 	 * (tXARD and tXARDS). Empirical?