From: richardbarry Date: Sat, 20 Jun 2009 16:45:08 +0000 (+0000) Subject: New driver files for Connectivity Line. X-Git-Tag: V5.3.1~12 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=99cbd72775a2033a820cb397e6a99b76e4713e1e;p=freertos New driver files for Connectivity Line. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@773 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h new file mode 100644 index 000000000..e8b2dd7bf --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/misc.h @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the + * miscellaneous firmware library functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h new file mode 100644 index 000000000..ef33aa3c0 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_crc.h @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h new file mode 100644 index 000000000..59caa2799 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dac.h @@ -0,0 +1,261 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; + uint32_t DAC_WaveGeneration; + uint32_t DAC_LFSRUnmask_TriangleAmplitude; + uint32_t DAC_OutputBuffer; +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) +#define DAC_Trigger_Software ((uint32_t)0x0000003C) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_noise_wave_generation_mask_triangle_wave_generation_max_amplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h new file mode 100644 index 000000000..7af3b6668 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFE000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h new file mode 100644 index 000000000..5daf2b648 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_flash.h @@ -0,0 +1,305 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32F10Xxx Medium-density devices: FLASH memory density + ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */ + +/* Values to be used with STM32F10Xxx High-density devices: FLASH memory density + ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG); +void FLASH_ClearFlag(uint16_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h new file mode 100644 index 000000000..c1ea5874a --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_fsmc.h @@ -0,0 +1,598 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the FSMC + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; + uint32_t FSMC_AddressHoldTime; + uint32_t FSMC_DataSetupTime; + uint32_t FSMC_BusTurnAroundDuration; + uint32_t FSMC_CLKDivision; + uint32_t FSMC_DataLatency; + uint32_t FSMC_AccessMode; +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; + uint32_t FSMC_DataAddressMux; + uint32_t FSMC_MemoryType; + uint32_t FSMC_MemoryDataWidth; + uint32_t FSMC_BurstAccessMode; + uint32_t FSMC_WaitSignalPolarity; + uint32_t FSMC_WrapMode; + uint32_t FSMC_WaitSignalActive; + uint32_t FSMC_WriteOperation; + uint32_t FSMC_WaitSignal; + uint32_t FSMC_ExtendedMode; + uint32_t FSMC_WriteBurst; + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;/* Timing Parameters for write and read access if the ExtendedMode is not used*/ + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;/* Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; + uint32_t FSMC_WaitSetupTime; + uint32_t FSMC_HoldSetupTime; + uint32_t FSMC_HiZSetupTime; +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; + uint32_t FSMC_Waitfeature; + uint32_t FSMC_MemoryDataWidth; + uint32_t FSMC_ECC; + uint32_t FSMC_ECCPageSize; + uint32_t FSMC_TCLRSetupTime; + uint32_t FSMC_TARSetupTime; + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;/* FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; + uint32_t FSMC_TCLRSetupTime; + uint32_t FSMC_TARSetupTime; + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;/* FSMC Common Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /* FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_Banks_definitions + * @{ + */ + +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) +/** + * @} + */ + +/** @defgroup NOR_SRAM_Banks + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_and_PCCARD_Banks + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Data_Width + * @{ + */ +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h new file mode 100644 index 000000000..4353fc185 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32f10x_sdio.h @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.0.0 + * @date 04/06/2009 + * @brief This file contains all the functions prototypes for the SDIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint8_t SDIO_ClockDiv; + uint32_t SDIO_ClockEdge; + uint32_t SDIO_ClockBypass; + uint32_t SDIO_ClockPowerSave; + uint32_t SDIO_BusWide; + uint32_t SDIO_HardwareFlowControl; +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; + uint32_t SDIO_CmdIndex; + uint32_t SDIO_Response; + uint32_t SDIO_Wait; + uint32_t SDIO_CPSM; +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; + uint32_t SDIO_DataLength; + uint32_t SDIO_DataBlockSize; + uint32_t SDIO_TransferDir; + uint32_t SDIO_TransferMode; + uint32_t SDIO_DPSM; +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save_ + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control_ + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_soucres + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index_ + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /* SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /* SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /* SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h new file mode 100644 index 000000000..11f15b005 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth.h @@ -0,0 +1,1118 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth.h +* Author : MCD Application Team +* Version : V0.0.1 +* Date : 12/17/2008 +* Desciption : This file contains all the functions prototypes for the +* ETHERNET firmware library. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32FXXX_ETH_H +#define __STM32FXXX_ETH_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32fxxx_eth_map.h" + +/* Exported types ------------------------------------------------------------*/ +/* ETHERNET MAC Init structure definition */ +typedef struct { + /* MAC ----------------------------------*/ + u32 ETH_AutoNegotiation; /* Selects or not the AutoNegotiation with the external PHY */ + u32 ETH_Watchdog; /* Enable/disable Watchdog timer */ + u32 ETH_Jabber; /* Enable/disable Jabber timer */ + u32 ETH_JumboFrame; /* Enable/disable Jumbo frame */ + u32 ETH_InterFrameGap; /* Selects minimum IFG between frames during transmission */ + u32 ETH_CarrierSense; /* Enable/disable Carrier Sense */ + u32 ETH_Speed; /* Indicates the Ethernet speed: 10/100 Mbps */ + u32 ETH_ReceiveOwn; /* Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ + u32 ETH_LoopbackMode; /* Enable/disable internal MAC MII Loopback mode */ + u32 ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + u32 ETH_ChecksumOffload; /* Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ + u32 ETH_RetryTransmission; /* Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ + u32 ETH_AutomaticPadCRCStrip; /* Enable/disable Automatic MAC Pad/CRC Stripping */ + u32 ETH_BackOffLimit; /* Selects the BackOff limit value */ + u32 ETH_DeferralCheck; /* Enable/disable deferral check function (Half-Duplex mode) */ + u32 ETH_ReceiveAll; /* Enable/disable all frames reception by the MAC (No fitering)*/ + u32 ETH_SourceAddrFilter; /* Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ + u32 ETH_PassControlFrames; /* Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ + u32 ETH_BroadcastFramesReception; /* Enable/disable reception of Broadcast Frames */ + u32 ETH_DestinationAddrFilter; /* Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ + u32 ETH_PromiscuousMode; /* Enable/disable Promiscuous Mode */ + u32 ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + u32 ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + u32 ETH_HashTableHigh; /* This field contains the higher 32 bits of Hash table. */ + u32 ETH_HashTableLow; /* This field contains the lower 32 bits of Hash table. */ + u32 ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the transmit control frame */ + u32 ETH_ZeroQuantaPause; /* Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ + u32 ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ + u32 ETH_UnicastPauseFrameDetect; /* Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ + u32 ETH_ReceiveFlowControl; /* Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ + u32 ETH_TransmitFlowControl; /* Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ + u32 ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ + u32 ETH_VLANTagIdentifier; /* VLAN tag identifier for receive frames */ + + /* DMA --------------------------*/ + u32 ETH_DropTCPIPChecksumErrorFrame; /* Enable/disable Dropping of TCP/IP Checksum Error Frames */ + u32 ETH_ReceiveStoreForward; /* Enable/disable Receive store and forward */ + u32 ETH_FlushReceivedFrame; /* Enable/disable flushing of received frames */ + u32 ETH_TransmitStoreForward; /* Enable/disable Transmit store and forward */ + u32 ETH_TransmitThresholdControl; /* Selects the Transmit Threshold Control */ + u32 ETH_ForwardErrorFrames; /* Enable/disable forward to DMA of all frames except runt error frames */ + u32 ETH_ForwardUndersizedGoodFrames; /* Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ + u32 ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO */ + u32 ETH_SecondFrameOperate; /* Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ + u32 ETH_AddressAlignedBeats; /* Enable/disable Address Aligned Beats */ + u32 ETH_FixedBurst; /* Enable/disable the AHB Master interface fixed burst transfers */ + u32 ETH_RxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ + u32 ETH_TxDMABurstLength; /* Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ + u32 ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + u32 ETH_DMAArbitration; /* Selects DMA Tx/Rx arbitration */ +}ETH_InitTypeDef; + +/*----------------------------------------------------------------------------*/ +/* DMA descriptors types */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET DMA Desciptors data structure definition */ +typedef struct { + volatile u32 Status; /* Status */ + volatile u32 ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + volatile u32 Buffer1Addr; /* Buffer1 address pointer */ + volatile u32 Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/* ETHERNET Frames defines */ +/*----------------------------------------------------------------------------*/ +/* ENET Buffers setting */ +#define ETH_MAX_PACKET_SIZE 1520 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/*--------------------------------------------------------*/ +/* Ethernet DMA descriptors registers bits definition */ +/*--------------------------------------------------------*/ +/* DMA Tx Desciptor ---------------------------------------------------------*/ +/*----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ----------------------------------------------------------------------------------------------*/ + +/* Bit definition of TDES0 register: DMA Tx descriptor status register */ +#define ETH_DMATxDesc_OWN (0x80000000UL) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((u32)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((u32)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((u32)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((u32)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((u32)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((u32)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((u32)0x00C00000) /* Checksum Insertion Control: 4 cases */ + #define ETH_DMATxDesc_CIC_ByPass ((u32)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ + #define ETH_DMATxDesc_CIC_IPV4Header ((u32)0x00400000) /* IPV4 header Checksum Insertion */ + #define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((u32)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ + #define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((u32)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((u32)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((u32)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((u32)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((u32)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((u32)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((u32)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((u32)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((u32)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((u32)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((u32)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((u32)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((u32)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((u32)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((u32)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((u32)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((u32)0x00000001) /* Deferred Bit */ + +/* Bit definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((u32)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((u32)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Bit definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Bit definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* DMA Rx descriptor ---------------------------------------------------------*/ +/*--------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------*/ + +/* Bit definition of RDES0 register: DMA Rx descriptor status register */ +#define ETH_DMARxDesc_OWN ((u32)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((u32)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((u32)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((u32)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((u32)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((u32)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((u32)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((u32)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((u32)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((u32)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((u32)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((u32)0x00000080) /* IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_RxLongFrame ((u32)0x00000080) /* (Giant Frame)Rx - frame is longer than 1518/1522 */ +#define ETH_DMARxDesc_LC ((u32)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((u32)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((u32)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((u32)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((u32)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((u32)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((u32)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((u32)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((u32)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((u32)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((u32)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((u32)0x00001FFF) /* Receive Buffer1 Size */ + +/* Bit definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((u32)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Bit definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((u32)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/*----------------------------------------------------------------------------*/ +/* Desciption of common PHY registers */ +/*----------------------------------------------------------------------------*/ +/* PHY Read/write Timeouts */ +#define PHY_READ_TO ((u32)0x0004FFFF) +#define PHY_WRITE_TO ((u32)0x0004FFFF) + +/* PHY Reset Delay */ +#define PHY_ResetDelay ((u32)0x000FFFFF) + +/* PHY Config Delay */ +#define PHY_ConfigDelay ((u32)0x00FFFFFF) + +/* PHY Register address */ +#define PHY_BCR 0 /* Tranceiver Basic Control Register */ +#define PHY_BSR 1 /* Tranceiver Basic Status Register */ + +/* PHY basic Control register */ +#define PHY_Reset ((u16)0x8000) /* PHY Reset */ +#define PHY_Loopback ((u16)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((u16)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((u16)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((u16)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((u16)0x0400) /* Isolate PHY from MII */ + +/* PHY basic status register */ +#define PHY_AutoNego_Complete ((u16)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((u16)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((u16)0x0002) /* Jabber condition detected */ + +/* The PHY status register value change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/* For LAN8700 */ +//#define PHY_SR 31 /* Tranceiver Status Register */ +/* For DP83848 */ +#define PHY_SR 16 /* Tranceiver Status Register */ + +/* PHY status register */ +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/* For LAN8700 */ +//#define PHY_Speed_Status ((u16)0x0004) /* Configured information of Speed: 10Mbps */ +//#define PHY_Duplex_Status ((u16)0x0010) /* Configured information of Duplex: Full-duplex */ +/* For DP83848 */ +#define PHY_Speed_Status ((u16)0x0002) /* Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((u16)0x0004) /* Configured information of Duplex: Full-duplex */ + +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) + +/*----------------------------------------------------------------------------*/ +/* MAC defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET AutoNegotiation --------------------------------------------------*/ +#define ETH_AutoNegotiation_Enable ((u32)0x00000001) +#define ETH_AutoNegotiation_Disable ((u32)0x00000000) + +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/* ETHERNET watchdog ---------------------------------------------------------*/ +#define ETH_Watchdog_Enable ((u32)0x00000000) +#define ETH_Watchdog_Disable ((u32)0x00800000) + +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/* ETHERNET Jabber -----------------------------------------------------------*/ +#define ETH_Jabber_Enable ((u32)0x00000000) +#define ETH_Jabber_Disable ((u32)0x00400000) + +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/* ETHERNET Jumbo Frame ------------------------------------------------------*/ +#define ETH_JumboFrame_Enable ((u32)0x00100000) +#define ETH_JumboFrame_Disable ((u32)0x00000000) + +#define IS_ETH_JUMBO_FRAME(CMD) (((CMD) == ETH_JumboFrame_Enable) || \ + ((CMD) == ETH_JumboFrame_Disable)) + +/* ETHERNET Inter Frame Gap --------------------------------------------------*/ +#define ETH_InterFrameGap_96Bit ((u32)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((u32)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((u32)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((u32)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((u32)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((u32)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((u32)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((u32)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/* ETHERNET Carrier Sense ----------------------------------------------------*/ +#define ETH_CarrierSense_Enable ((u32)0x00000000) +#define ETH_CarrierSense_Disable ((u32)0x00010000) + +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/* ETHERNET Speed ------------------------------------------------------------*/ +#define ETH_Speed_10M ((u32)0x00000000) +#define ETH_Speed_100M ((u32)0x00004000) + +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/* ETHERNET Receive Own ------------------------------------------------------*/ +#define ETH_ReceiveOwn_Enable ((u32)0x00000000) +#define ETH_ReceiveOwn_Disable ((u32)0x00002000) + +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/* ETHERNET Loop back Mode ---------------------------------------------------*/ +#define ETH_LoopbackMode_Enable ((u32)0x00001000) +#define ETH_LoopbackMode_Disable ((u32)0x00000000) + +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/* ETHERNET Duplex mode ------------------------------------------------------*/ +#define ETH_Mode_FullDuplex ((u32)0x00000800) +#define ETH_Mode_HalfDuplex ((u32)0x00000000) + +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/* ETHERNET Checksum Offload -------------------------------------------------*/ +#define ETH_ChecksumOffload_Enable ((u32)0x00000400) +#define ETH_ChecksumOffload_Disable ((u32)0x00000000) + +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/* ETHERNET Retry Transmission -----------------------------------------------*/ +#define ETH_RetryTransmission_Enable ((u32)0x00000000) +#define ETH_RetryTransmission_Disable ((u32)0x00000200) + +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/* ETHERNET Automatic Pad/CRC Strip ------------------------------------------*/ +#define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000) + +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/* ETHERNET Back-Off limit ---------------------------------------------------*/ +#define ETH_BackOffLimit_10 ((u32)0x00000000) +#define ETH_BackOffLimit_8 ((u32)0x00000020) +#define ETH_BackOffLimit_4 ((u32)0x00000040) +#define ETH_BackOffLimit_1 ((u32)0x00000060) + +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/* ETHERNET Deferral Check ---------------------------------------------------*/ +#define ETH_DeferralCheck_Enable ((u32)0x00000010) +#define ETH_DeferralCheck_Disable ((u32)0x00000000) + +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/* ETHERNET Receive All ------------------------------------------------------*/ +#define ETH_ReceiveAll_Enable ((u32)0x80000000) +#define ETH_ReceiveAll_Disable ((u32)0x00000000) + +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/* ETHERNET Source Addr Filter ------------------------------------------------*/ +#define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300) +#define ETH_SourceAddrFilter_Disable ((u32)0x00000000) + +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/* ETHERNET Pass Control Frames ----------------------------------------------*/ +#define ETH_PassControlFrames_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/* ETHERNET Broadcast Frames Reception ---------------------------------------*/ +#define ETH_BroadcastFramesReception_Enable ((u32)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((u32)0x00000020) + +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/* ETHERNET Destination Addr Filter ------------------------------------------*/ +#define ETH_DestinationAddrFilter_Normal ((u32)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008) + +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/* ETHERNET Promiscuous Mode -------------------------------------------------*/ +#define ETH_PromiscuousMode_Enable ((u32)0x00000001) +#define ETH_PromiscuousMode_Disable ((u32)0x00000000) + +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/* ETHERNET multicast frames filter --------------------------------------------*/ +#define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000) +#define ETH_MulticastFramesFilter_None ((u32)0x00000010) + +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + +/* ETHERNET unicast frames filter --------------------------------------------*/ +#define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000) + +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/* ETHERNET Pause Time ------------------------------------------------*/ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/* ETHERNET Zero Quanta Pause ------------------------------------------------*/ +#define ETH_ZeroQuantaPause_Enable ((u32)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((u32)0x00000080) + +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) + +/* ETHERNET Pause Low Threshold ----------------------------------------------*/ +#define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */ + +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/* ETHERNET Unicast Pause Frame Detect ---------------------------------------*/ +#define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000) + +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/* ETHERNET Receive Flow Control ---------------------------------------------*/ +#define ETH_ReceiveFlowControl_Enable ((u32)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((u32)0x00000000) + +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/* ETHERNET Transmit Flow Control --------------------------------------------*/ +#define ETH_TransmitFlowControl_Enable ((u32)0x00000002) +#define ETH_TransmitFlowControl_Disable ((u32)0x00000000) + +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/* ETHERNET VLAN Tag Comparison ----------------------------------------------*/ +#define ETH_VLANTagComparison_12Bit ((u32)0x00010000) +#define ETH_VLANTagComparison_16Bit ((u32)0x00000000) + +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) + +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/* ETHERNET MAC Flags ---------------------------------------------------*/ +#define ETH_MAC_FLAG_TST ((u32)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((u32)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((u32)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((u32)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((u32)0x00000008) /* PMT flag (on MAC) */ + +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) + +/* ETHERNET MAC Interrupts ---------------------------------------------------*/ +#define ETH_MAC_IT_TST ((u32)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((u32)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((u32)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((u32)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((u32)0x00000008) /* PMT interrupt (on MAC) */ + +#define IS_ETH_MAC_IT(IT) ((((IT) & (u32)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) + +/* ETHERNET MAC addresses ----------------------------------------------------*/ +#define ETH_MAC_Address0 ((u32)0x00000000) +#define ETH_MAC_Address1 ((u32)0x00000008) +#define ETH_MAC_Address2 ((u32)0x00000010) +#define ETH_MAC_Address3 ((u32)0x00000018) + +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) + +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) + +/* ETHERNET MAC addresses filter: SA/DA filed of received frames ------------*/ +#define ETH_MAC_AddressFilter_SA ((u32)0x00000000) +#define ETH_MAC_AddressFilter_DA ((u32)0x00000008) + +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) + +/* ETHERNET MAC addresses filter: Mask bytes ---------------------------------*/ +#define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet DMA Desciptors defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET DMA Tx descriptor flags --------------------------------------------------------*/ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/* ETHERNET DMA Tx descriptor segment ----------------------------------------*/ +#define ETH_DMATxDesc_LastSegment ((u32)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((u32)0x20000000) /* First Segment */ + +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/* ETHERNET DMA Tx descriptor Checksum Insertion Control --------------------*/ +#define ETH_DMATxDesc_ChecksumByPass ((u32)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((u32)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((u32)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((u32)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) + +/* ETHERNET DMA Tx Desciptor buffer size */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/* ETHERNET DMA Rx descriptor flags --------------------------------------------------------*/ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_RxLongFrame) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/* ETHERNET DMA Rx descriptor buffers ---------------------------------------*/ +#define ETH_DMARxDesc_Buffer1 ((u32)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((u32)0x00000001) /* DMA Rx Desc Buffer2 */ + +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet DMA defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET Drop TCP/IP Checksum Error Frame ---------------------------------*/ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000) + +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) + +/* ETHERNET Receive Store Forward --------------------------------------------*/ +#define ETH_ReceiveStoreForward_Enable ((u32)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((u32)0x00000000) + +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) + +/* ETHERNET Flush Received Frame ---------------------------------------------*/ +#define ETH_FlushReceivedFrame_Enable ((u32)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((u32)0x01000000) + +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) + +/* ETHERNET Transmit Store Forward -------------------------------------------*/ +#define ETH_TransmitStoreForward_Enable ((u32)0x00200000) +#define ETH_TransmitStoreForward_Disable ((u32)0x00000000) + +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) + +/* ETHERNET Transmit Threshold Control ---------------------------------------*/ +#define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) + +/* ETHERNET Forward Error Frames ---------------------------------------------*/ +#define ETH_ForwardErrorFrames_Enable ((u32)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((u32)0x00000000) + +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) + +/* ETHERNET Forward Undersized Good Frames -----------------------------------*/ +#define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000) + +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/* ETHERNET Receive Threshold Control ----------------------------------------*/ +#define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) + +/* ETHERNET Second Frame Operate ---------------------------------------------*/ +#define ETH_SecondFrameOperate_Enable ((u32)0x00000004) +#define ETH_SecondFrameOperate_Disable ((u32)0x00000000) + +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/* ETHERNET Address Aligned Beats --------------------------------------------*/ +#define ETH_AddressAlignedBeats_Enable ((u32)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((u32)0x00000000) + +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/* ETHERNET Fixed Burst ------------------------------------------------------*/ +#define ETH_FixedBurst_Enable ((u32)0x00010000) +#define ETH_FixedBurst_Disable ((u32)0x00000000) + +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/* ETHERNET Rx DMA Burst Length ----------------------------------------------*/ +#define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + +#define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/* ETHERNET Tx DMA Burst Length ----------------------------------------------*/ +#define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + +#define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) + +/* ETHERNET DMA Desciptor SkipLength */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/* ETHERNET DMA Arbitration --------------------------------------------------*/ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002) + +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) + +/* ETHERNET DMA Flags ---------------------------------------------------*/ +#define ETH_DMA_FLAG_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */ + +#define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((u32)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((u32)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((u32)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((u32)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((u32)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((u32)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((u32)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((u32)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((u32)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((u32)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((u32)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((u32)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((u32)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((u32)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((u32)0x00000001) /* Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (u32)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) + +/* ETHERNET DMA Interrupts ---------------------------------------------------*/ +#define ETH_DMA_IT_TST ((u32)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((u32)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((u32)0x08000000) /* MMC interrupt (on DMA) */ + +#define ETH_DMA_IT_NIS ((u32)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((u32)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((u32)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((u32)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((u32)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((u32)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((u32)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((u32)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((u32)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((u32)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((u32)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((u32)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((u32)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((u32)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((u32)0x00000001) /* Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (u32)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/* ETHERNET DMA transmit process state --------------------------------------------------------*/ +#define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */ + +/* ETHERNET DMA receive process state --------------------------------------------------------*/ +#define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* ETHERNET DMA overflow --------------------------------------------------------*/ +#define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) /* Overflow bit for missed frame counter */ + +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet PMT defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET PMT Flags --------------------------------------------------------*/ +#define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((u32)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((u32)0x00000020) /* Magic Packet Received */ + +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet MMC defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET MMC Tx Interrupts */ +#define ETH_MMC_IT_TGF ((u32)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((u32)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((u32)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* ETHERNET MMC Rx Interrupts */ +#define ETH_MMC_IT_RGUF ((u32)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((u32)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((u32)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + +#define IS_ETH_MMC_IT(IT) (((((IT) & (u32)0xFFDF3FFF) == 0x00) || (((IT) & (u32)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) + +/* ETHERNET MMC Registers */ +#define ETH_MMCCR ((u32)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((u32)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((u32)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((u32)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((u32)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((u32)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((u32)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((u32)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((u32)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((u32)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((u32)0x000001C4) /* MMC RGUFCR register */ + +/* ETHERNET MMC registers */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/*----------------------------------------------------------------------------*/ +/* Ethernet PTP defines */ +/*----------------------------------------------------------------------------*/ +/* ETHERNET PTP time update method -------------------------------------------*/ +#define ETH_PTP_FineUpdate ((u32)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((u32)0x00000000) /* Coarse Update method */ + +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/* ETHERNET PTP Flags --------------------------------------------------------*/ +#define ETH_PTP_FLAG_TSARU ((u32)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((u32)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) /* Time Stamp Initialize */ + +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI)) + +/* ETHERNET PTP subsecond increment */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/* ETHERNET PTP time sign ----------------------------------------------------*/ +#define ETH_PTP_PositiveTime ((u32)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((u32)0x80000000) /* Negative time value */ + +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/* ETHERNET PTP time stamp low update */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/* ETHERNET PTP registers */ +#define ETH_PTPTSCR ((u32)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((u32)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((u32)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((u32)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((u32)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((u32)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((u32)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((u32)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((u32)0x00000720) /* PTP TTLR register */ + +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR)) + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void ETH_DeInit(void); +u32 ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +u32 ETH_HandleTxPkt(u32 addr, u16 FrameLength); +u32 ETH_HandleRxPkt(u32 addr); + + +u32 ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +/*--------------------------------- PHY ------------------------------------*/ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); +u32 ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +u32 ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); +/*--------------------------------- MAC ------------------------------------*/ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(u32 ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(u32 ETH_MAC_IT); +void ETH_MACITConfig(u32 ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(u32 MacAddr, u8 *Addr); +void ETH_GetMACAddress(u32 MacAddr, u8 *Addr); +void ETH_MACAddressPerfectFilterCmd(u32 MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(u32 MacAddr, u32 Filter); +void ETH_MACAddressMaskBytesFilterConfig(u32 MacAddr, u32 MaskByte); +/*----------------------- DMA Tx/Rx descriptors ----------------------------*/ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, u32 TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, u32 TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, u32 ETH_DMATxDescFlag); +u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, u32 BufferSize1, u32 BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, u32 RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, u32 RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, u32 ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, u32 DMARxDesc_Buffer); +/*--------------------------------- DMA ------------------------------------*/ +FlagStatus ETH_GetDMAFlagStatus(u32 ETH_DMA_FLAG); +void ETH_DMAClearFlag(u32 ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(u32 ETH_DMA_IT); +void ETH_DMAClearITPendingBit(u32 ETH_DMA_IT); +u32 ETH_GetTransmitProcessState(void); +u32 ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(u32 ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(u32 ETH_DMA_Overflow); +u32 ETH_GetRxOverflowMissedFrameCounter(void); +u32 ETH_GetBufferUnavailableMissedFrameCounter(void); +u32 ETH_GetCurrentTxDescStartAddress(void); +u32 ETH_GetCurrentRxDescStartAddress(void); +u32 ETH_GetCurrentTxBufferAddress(void); +u32 ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); +/*--------------------------------- PMT ------------------------------------*/ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(u32 *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(u32 ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); +/*--------------------------------- MMC ------------------------------------*/ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(u32 ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(u32 ETH_MMC_IT); +u32 ETH_GetMMCRegister(u32 ETH_MMCReg); +/*--------------------------------- PTP ------------------------------------*/ +u32 ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, u32 *PTPTxTab); +u32 ETH_HandlePTPRxPkt(u8 *ppkt, u32 *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, u32 TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, u32 RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(u32 UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(u32 ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(u32 SubSecondValue); +void ETH_SetPTPTimeStampUpdate(u32 Sign, u32 SecondValue, u32 SubSecondValue); +void ETH_SetPTPTimeStampAddend(u32 Value); +void ETH_SetPTPTargetTime(u32 HighValue, u32 LowValue); +u32 ETH_GetPTPRegister(u32 ETH_PTPReg); + +#endif /* __STM32FXXX_ETH_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h new file mode 100644 index 000000000..93f7fb3ac --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_conf.h @@ -0,0 +1,58 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32f_eth_conf.h +* Author : MCD Application Team +* Version : VX.Y.Z +* Date : mm/dd/2008 +* Description : ETHERNET firmware library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F_ETH_CONF_H +#define __STM32F_ETH_CONF_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_type.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to compile the ETHERNET firmware library in DEBUG mode, + this will expanse the "assert_param" macro in the firmware library code (see + "Exported macro" section below) */ +/*#define ETH_DEBUG 1*/ + +/* Comment the line below to disable the specific peripheral inclusion */ +/************************************* ETHERNET *******************************/ +#define _ETH_MAC +//#define _ETH_PTP +//#define _ETH_MMC +#define _ETH_DMA + +/* Exported macro ------------------------------------------------------------*/ +#ifdef ETH_DEBUG +/******************************************************************************* +* Macro Name : eth_assert_param +* Description : The eth_assert_param macro is used for ethernet function's parameters +* check. +* It is used only if the ethernet library is compiled in DEBUG mode. +* Input : - expr: If expr is false, it calls assert_failed function +* which reports the name of the source file and the source +* line number of the call that failed. +* If expr is true, it returns no value. +* Return : None +*******************************************************************************/ + #define eth_assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(u8* file, u32 line); +#else + #define eth_assert_param(expr) ((void)0) +#endif /* ETH_DEBUG */ + +#endif /* __STM32F_ETH_CONF_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h new file mode 100644 index 000000000..a501d70c9 --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_lib.h @@ -0,0 +1,39 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth_lib.h +* Author : MCD Application Team +* Version : V2.0.2 +* Date : 07/11/2008 +* Description : This file includes the peripherals header files in the +* user application. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32FXXX_ETH_LIB_H +#define __STM32FXXX_ETH_LIB_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32fxxx_eth_map.h" + +#ifdef _ETH_MAC +//RP_Modif + #include "ipport.h" + #include "netbuf.h" + #include "stm32fxxx_eth.h" +#endif /*_ETH_MAC */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +void eth_debug(void); + +#endif /* __STM32FXXX_ETH_LIB_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h new file mode 100644 index 000000000..cae9ce07b --- /dev/null +++ b/Demo/Common/drivers/ST/STM32F10xFWLib/inc/stm32fxxx_eth_map.h @@ -0,0 +1,593 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32fxxx_eth_map.h +* Author : MCD Application Team +* Version : VX.Y.Z +* Date : mm/dd/2008 +* Description : This file contains all ETHERNET peripheral register's +* definitions and memory mapping. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32FXXX_ETH_MAP_H +#define __STM32FXXX_ETH_MAP_H + +#ifndef EXT + #define EXT extern +#endif /* EXT */ + +/* Includes ------------------------------------------------------------------*/ + +#include "stm32fxxx_eth_conf.h" +#include "stm32f10x_type.h" + +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Ethernet Peripheral registers structures */ +/******************************************************************************/ + +typedef struct +{ + vu32 MACCR; + vu32 MACFFR; + vu32 MACHTHR; + vu32 MACHTLR; + vu32 MACMIIAR; + vu32 MACMIIDR; + vu32 MACFCR; + vu32 MACVLANTR; + vu32 RESERVED0[2]; + vu32 MACRWUFFR; + vu32 MACPMTCSR; + vu32 RESERVED1[2]; + vu32 MACSR; + vu32 MACIMR; + vu32 MACA0HR; + vu32 MACA0LR; + vu32 MACA1HR; + vu32 MACA1LR; + vu32 MACA2HR; + vu32 MACA2LR; + vu32 MACA3HR; + vu32 MACA3LR; +} ETH_MAC_TypeDef; + +typedef struct +{ + vu32 MMCCR; + vu32 MMCRIR; + vu32 MMCTIR; + vu32 MMCRIMR; + vu32 MMCTIMR; + vu32 RESERVED0[14]; + vu32 MMCTGFSCCR; + vu32 MMCTGFMSCCR; + vu32 RESERVED1[5]; + vu32 MMCTGFCR; + vu32 RESERVED2[10]; + vu32 MMCRFCECR; + vu32 MMCRFAER; + vu32 RESERVED3[10]; + vu32 MMCRGUFCR; +} ETH_MMC_TypeDef; + +typedef struct +{ + vu32 PTPTSCR; + vu32 PTPSSIR; + vu32 PTPTSHR; + vu32 PTPTSLR; + vu32 PTPTSHUR; + vu32 PTPTSLUR; + vu32 PTPTSAR; + vu32 PTPTTHR; + vu32 PTPTTLR; +} ETH_PTP_TypeDef; + +typedef struct +{ + vu32 DMABMR; + vu32 DMATPDR; + vu32 DMARPDR; + vu32 DMARDLAR; + vu32 DMATDLAR; + vu32 DMASR; + vu32 DMAOMR; + vu32 DMAIER; + vu32 DMAMFBOCR; + vu32 RESERVED0[9]; + vu32 DMACHTDR; + vu32 DMACHRDR; + vu32 DMACHTBAR; + vu32 DMACHRBAR; +} ETH_DMA_TypeDef; + +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +//#define IPNAME_REGNAME_BITNAME /* BIT MASK */ + +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((u32)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((u32)0x00400000) /* Jabber disable */ +#define ETH_MACCR_JFE ((u32)0x00100000) /* Jumbo frame enable */ +#define ETH_MACCR_IFG ((u32)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((u32)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((u32)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((u32)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((u32)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((u32)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((u32)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((u32)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((u32)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((u32)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((u32)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((u32)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((u32)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((u32)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((u32)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((u32)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((u32)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((u32)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((u32)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((u32)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((u32)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((u32)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((u32)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((u32)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((u32)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((u32)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((u32)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((u32)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((u32)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((u32)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((u32)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((u32)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((u32)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((u32)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((u32)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((u32)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((u32)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((u32)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((u32)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((u32)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((u32)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((u32)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((u32)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((u32)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((u32)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((u32)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((u32)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((u32)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((u32)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((u32)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((u32)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((u32)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((u32)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((u32)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((u32)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((u32)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((u32)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((u32)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((u32)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((u32)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((u32)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((u32)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((u32)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((u32)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((u32)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((u32)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((u32)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((u32)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((u32)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((u32)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((u32)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((u32)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((u32)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((u32)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((u32)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((u32)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((u32)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((u32)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((u32)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((u32)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((u32)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((u32)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((u32)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((u32)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((u32)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((u32)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((u32)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((u32)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((u32)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((u32)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((u32)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((u32)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((u32)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((u32)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((u32)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((u32)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((u32)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((u32)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((u32)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((u32)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((u32)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((u32)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((u32)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((u32)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((u32)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((u32)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((u32)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((u32)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((u32)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((u32)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((u32)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((u32)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((u32)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((u32)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((u32)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((u32)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((u32)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((u32)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((u32)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((u32)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((u32)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((u32)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((u32)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((u32)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((u32)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((u32)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((u32)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((u32)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((u32)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((u32)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((u32)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((u32)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((u32)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((u32)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((u32)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((u32)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((u32)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((u32)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((u32)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((u32)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((u32)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((u32)0x007E0000) /* RxDMA PBL */ + /* Values to be confirmed: maybe they are inversed */ + #define ETH_DMABMR_RDP_1Beat ((u32)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((u32)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((u32)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((u32)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((u32)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((u32)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((u32)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((u32)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((u32)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((u32)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((u32)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((u32)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((u32)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((u32)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((u32)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((u32)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((u32)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((u32)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((u32)0x00003F00) /* Programmable burst length */ + /* Values to be confirmed: maybe they are inversed */ + #define ETH_DMABMR_PBL_1Beat ((u32)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((u32)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((u32)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((u32)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((u32)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((u32)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((u32)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((u32)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((u32)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((u32)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((u32)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((u32)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((u32)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((u32)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((u32)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((u32)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((u32)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((u32)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((u32)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((u32)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((u32)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((u32)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((u32)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((u32)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((u32)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((u32)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((u32)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((u32)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((u32)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((u32)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((u32)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((u32)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((u32)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((u32)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((u32)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((u32)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((u32)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((u32)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((u32)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((u32)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((u32)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((u32)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((u32)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((u32)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((u32)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((u32)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((u32)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((u32)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((u32)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((u32)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((u32)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((u32)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((u32)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((u32)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((u32)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((u32)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((u32)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((u32)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((u32)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((u32)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((u32)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((u32)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((u32)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((u32)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((u32)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((u32)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((u32)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((u32)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((u32)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((u32)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((u32)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((u32)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((u32)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((u32)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((u32)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((u32)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((u32)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((u32)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((u32)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((u32)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((u32)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((u32)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((u32)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((u32)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((u32)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((u32)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((u32)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((u32)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((u32)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((u32)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((u32)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((u32)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((u32)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((u32)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((u32)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((u32)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((u32)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((u32)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((u32)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((u32)0xFFFFFFFF) /* Host receive buffer address pointer */ + +/******************************************************************************/ +/* Macros */ +/******************************************************************************/ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* ETHERNET registers base address */ +#define ETH_BASE ((u32)0x40028000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/*------------------------ Non Debug Mode ------------------------------------*/ +#ifndef ETH_DEBUG +#ifdef _ETH_MAC + #define ETH_MAC ((ETH_MAC_TypeDef *) ETH_MAC_BASE) +#endif /*_ETH_MAC */ + +#ifdef _ETH_MMC + #define ETH_MMC ((ETH_MMC_TypeDef *) ETH_MMC_BASE) +#endif /*_ETH_MMC */ + +#ifdef _ETH_PTP + #define ETH_PTP ((ETH_PTP_TypeDef *) ETH_PTP_BASE) +#endif /*_ETH_PTP */ + +#ifdef _ETH_DMA + #define ETH_DMA ((ETH_DMA_TypeDef *) ETH_DMA_BASE) +#endif /*_ETH_DMA */ + +/*------------------------ Debug Mode ----------------------------------------*/ +#else /* ETH_DEBUG */ +#ifdef _ETH_MAC + EXT ETH_MAC_TypeDef *ETH_MAC; +#endif /*_ETH_MAC */ + +#ifdef _ETH_MMC + EXT ETH_MMC_TypeDef *ETH_MMC; +#endif /*_ETH_MMC */ + +#ifdef _ETH_PTP + EXT ETH_PTP_TypeDef *ETH_PTP; +#endif /*_ETH_PTP */ + +#ifdef _ETH_DMA + EXT ETH_DMA_TypeDef *ETH_DMA; +#endif /*_ETH_DMA */ + +#endif /* ETH_DEBUG */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM32FXXX_ETH_MAP_H */ + +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/