From: richardbarry Date: Tue, 16 Apr 2013 15:50:17 +0000 (+0000) Subject: Add memory barrier instructions to Tasking CM4F port. X-Git-Tag: V7.4.1~13 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=9b6be16e4336a0b4782b910a5f51d69a843e44c8;p=freertos Add memory barrier instructions to Tasking CM4F port. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1862 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c index 07995e3ea..f94d06f6e 100644 --- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c +++ b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c @@ -56,19 +56,19 @@ *************************************************************************** - http://www.FreeRTOS.org - Documentation, books, training, latest versions, + http://www.FreeRTOS.org - Documentation, books, training, latest versions, license and Real Time Engineers Ltd. contact details. http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, including FreeRTOS+Trace - an indispensable productivity tool, and our new fully thread aware and reentrant UDP/IP stack. - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems, who sell the code with commercial support, + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems, who sell the code with commercial support, indemnification and middleware, under the OpenRTOS brand. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and mission critical applications that require provable dependability. */ @@ -83,12 +83,10 @@ /* Constants required to manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 ) #define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned long * ) 0xe000ed04 ) #define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 ) #define portNVIC_SYSTICK_CLK 0x00000004 #define portNVIC_SYSTICK_INT 0x00000002 #define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) @@ -204,10 +202,15 @@ void vPortEndScheduler( void ) } /*-----------------------------------------------------------*/ -void vPortYieldFromISR( void ) +void vPortYield( void ) { /* Set a PendSV to request a context switch. */ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is completely + within the specified behaviour for the architecture. */ + __DSB(); + __ISB(); } /*-----------------------------------------------------------*/ @@ -215,6 +218,8 @@ void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); ulCriticalNesting++; + __DSB(); + __ISB(); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h index b2631954a..59d16b4cc 100644 --- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h +++ b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h @@ -56,19 +56,19 @@ *************************************************************************** - http://www.FreeRTOS.org - Documentation, books, training, latest versions, + http://www.FreeRTOS.org - Documentation, books, training, latest versions, license and Real Time Engineers Ltd. contact details. http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, including FreeRTOS+Trace - an indispensable productivity tool, and our new fully thread aware and reentrant UDP/IP stack. - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems, who sell the code with commercial support, + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems, who sell the code with commercial support, indemnification and middleware, under the OpenRTOS brand. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and mission critical applications that require provable dependability. */ @@ -81,7 +81,7 @@ extern "C" { #endif /*----------------------------------------------------------- - * Port specific definitions. + * Port specific definitions. * * The settings in this file configure FreeRTOS correctly for the * given hardware and compiler. @@ -106,40 +106,41 @@ extern "C" { typedef unsigned portLONG portTickType; #define portMAX_DELAY ( portTickType ) 0xffffffff #endif -/*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ /* Architecture specifics. */ #define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) +#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) #define portBYTE_ALIGNMENT 8 -/*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ /* Scheduler utilities. */ -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() +extern void vPortYield( void ); +#define portNVIC_INT_CTRL ( ( volatile unsigned long * ) 0xe000ed04 ) +#define portNVIC_PENDSVSET 0x10000000 +#define portYIELD() vPortYield() -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET /*-----------------------------------------------------------*/ /* Critical section management. */ -/* +/* * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other * registers. r0 is clobbered. - */ + */ #define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ) - + /* * Set basepri back to 0 without effective other registers. - * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see + * r0 is clobbered. FAQ: Setting BASEPRI to 0 is not a bug. Please see * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */ #define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 ) -/* FAQ: Setting BASEPRI to 0 is not a bug. Please see +/* FAQ: Setting BASEPRI to 0 is not a bug. Please see http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing. */ #define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x @@ -153,7 +154,7 @@ extern void vPortExitCritical( void ); #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() -/* There are an uneven number of items on the initial stack, so +/* There are an uneven number of items on the initial stack, so portALIGNMENT_ASSERT_pxCurrentTCB() will trigger false positive asserts. */ #define portALIGNMENT_ASSERT_pxCurrentTCB ( void )