From: Marek Vasut <marex@denx.de>
Date: Sun, 14 Sep 2014 23:27:57 +0000 (+0200)
Subject: arm: socfpga: cache: Define cacheline size
X-Git-Tag: v2014.10-rc3~2^2~13
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=9ca2116ce49449602eb9e2f8a0cafe811bcc3086;p=u-boot

arm: socfpga: cache: Define cacheline size

The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
---

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 54343b83a4..76979b10b8 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -26,6 +26,8 @@
 #define CONFIG_SOCFPGA
 #define CONFIG_CLOCKS
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040