From: richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Tue, 21 Jul 2009 19:35:59 +0000 (+0000)
Subject: Correct interrupt priority assignment.
X-Git-Tag: V5.4.1~3
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=9d063f686ddb3582d0cc5a9a6c9abcff0bb537cf;p=freertos

Correct interrupt priority assignment.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@822 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h
index 1458e9e73..2ce1eaab7 100644
--- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/FreeRTOSConfig.h
@@ -132,7 +132,9 @@ to exclude the API function. */
 /* Priority 5, or 160 as only the top three bits are implemented. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( 5 << (8 - configPRIO_BITS) )
 
-
+/* Priorities passed to NVIC_SetPriority() do not require shifting as the
+function does the shifting itself. */
+#define configEMAC_INTERRUPT_PRIORITY		5
 
 
 
diff --git a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c
index 6f56b92cd..71ad5ce3d 100644
--- a/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c
+++ b/Demo/CORTEX_LPC1768_GCC_RedSuite/src/webserver/uIP_Task.c
@@ -142,7 +142,7 @@ extern void ( vEMAC_ISR_Wrapper )( void );
 
 		/* Set the interrupt priority to the max permissible to cause some
 		interrupt nesting. */
-		NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+		NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );
 
 		/* Enable the interrupt. */
 		NVIC_EnableIRQ( ENET_IRQn );
diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h
index 1458e9e73..f63270552 100644
--- a/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LPC1768_GCC_Rowley/FreeRTOSConfig.h
@@ -132,6 +132,9 @@ to exclude the API function. */
 /* Priority 5, or 160 as only the top three bits are implemented. */
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( 5 << (8 - configPRIO_BITS) )
 
+/* Priorities passed to NVIC_SetPriority() do not require shifting as the
+function does the shifting itself. */
+#define configEMAC_INTERRUPT_PRIORITY		5
 
 
 
diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
index ea9e43e35..deab7e8f8 100644
--- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
+++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c
@@ -142,7 +142,7 @@ extern void ( vEMAC_ISR_Wrapper )( void );
 
 		/* Set the interrupt priority to the max permissible to cause some
 		interrupt nesting. */
-		NVIC_SetPriority( ENET_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+		NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );
 
 		/* Enable the interrupt. */
 		NVIC_EnableIRQ( ENET_IRQn );