From: richardbarry Date: Wed, 4 Sep 2013 15:44:48 +0000 (+0000) Subject: Reworked XMC4500 IAR project to use latest system files and include build configurati... X-Git-Tag: V7.5.3~42 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=9da7b10163a8e7ae4acb4a77420916b71239a3bb;p=freertos Reworked XMC4500 IAR project to use latest system files and include build configurations for the XMC4200 and XMC4400 parts. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2024 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c index 0e24f3c59..4e425431f 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/main_full.c @@ -113,16 +113,12 @@ /* Standard demo application includes. */ #include "flop.h" -#include "integer.h" -#include "PollQ.h" #include "semtest.h" #include "dynamic.h" -#include "BlockQ.h" #include "blocktim.h" #include "countsem.h" #include "GenQTest.h" #include "recmutex.h" -#include "death.h" /* Priorities for the demo application tasks. */ #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h index 92373f513..51df1616b 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h @@ -87,12 +87,12 @@ #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 +#define configUSE_TICK_HOOK 1 #define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 @@ -105,6 +105,7 @@ #define configUSE_APPLICATION_TASK_TAG 0 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_QUEUE_SETS 1 /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 @@ -150,16 +151,50 @@ to all Cortex-M ports, and do not rely on any particular library functions. */ /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ #define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - + /* Normal assert() semantics without relying on the provision of an assert.h header file. */ -#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } - +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS standard names. */ #define vPortSVCHandler SVC_Handler #define xPortPendSVHandler PendSV_Handler #define xPortSysTickHandler SysTick_Handler +/* Demo application specific settings. */ +#ifdef __ICCARM__ + #if defined( PART_XMC4500 ) + /* Hardware includes. */ + #include "XMC4500.h" + #include "System_XMC4500.h" + + /* Configure pin P3.9 for the LED. */ + #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 ) + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) + #elif defined( PART_XMC4400 ) + /* Hardware includes. */ + #include "XMC4400.h" + #include "System_XMC4200.h" + + /* Configure pin P5.2 for the LED. */ + #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 ) + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 ) + #elif defined( PART_XMC4200 ) + /* Hardware includes. */ + #include "XMC4200.h" + #include "System_XMC4200.h" + + /* Configure pin P2.1 for the LED. */ + #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 ) + #else + #error Part number not specified in project options + #endif +#endif + #endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd index d423de175..10b837d23 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd @@ -3,7 +3,7 @@ 2 - Debug + XMC4500 ARM @@ -12,7 +12,7 @@ C-SPY 2 - 23 + 25 1 1 + + @@ -245,6 +253,153 @@ + + CMSISDAP_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID 2 @@ -314,233 +469,437 @@ - JLINK_ID + IJET_ID 2 - 14 + 2 1 1 + - LMIFTDI_ID + JLINK_ID 2 - 2 + 15 1 1 + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + MACRAIGOR_ID @@ -635,7 +994,7 @@ PEMICRO_ID 2 - 0 + 1 1 1 + + @@ -752,63 +1119,6 @@ - - RDIJTAGJET_ID - 0 - - 1 - 1 - 1 - - - - - - - - - - - - - - STLINK_ID 2 @@ -876,7 +1186,7 @@ XDS100_ID 2 - 1 + 2 1 1 - - - - + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin 0 @@ -968,28 +1290,28 @@ 0 - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin 1 - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 - Release + XMC4200 ARM - 0 + 1 C-SPY 2 - 23 + 25 1 - 0 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + + + IJET_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 15 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + MACRAIGOR_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + PEMICRO_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + RDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + STLINK_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + XDS100_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + XMC4400 + + ARM + + 1 + + C-SPY + 2 + + 25 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IARROM_ID + 2 + + 1 + 1 + 1 + + + + + + + IJET_ID + 2 + + 2 + 1 + 1 + - - - - ARMSIM_ID - 2 - - 1 - 1 - 0 - - - - ANGEL_ID - 2 - - 0 - 1 - 0 - - - - GDBSERVER_ID - 2 - - 0 - 1 - 0 - - - - IARROM_ID - 2 - - 1 - 1 - 0 @@ -1292,9 +3266,9 @@ JLINK_ID 2 - 14 + 15 1 - 0 + 1 + @@ -1490,7 +3468,7 @@ 2 1 - 0 + 1 @@ -1676,7 +3662,7 @@ 2 1 - 0 + 1 - - RDIJTAGJET_ID - 0 - - 1 - 1 - 0 - - - - - - - - - - - - - - STLINK_ID 2 2 1 - 0 + 1 + + $TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin + 0 + $TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin 0 @@ -1943,12 +3884,12 @@ 0 - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin 1 - $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin - 1 + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp index 934a2b4b8..402737146 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewp @@ -3,7 +3,7 @@ 2 - Debug + XMC4500 ARM @@ -12,20 +12,20 @@ General 3 - 21 + 22 1 1 + + + + + ICCARM + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + XMC4200 + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM 2 - 28 + 29 1 1 + AARM 2 - 8 + 9 1 1 + @@ -613,7 +1561,7 @@ ILINK 0 - 15 + 16 1 1 + @@ -923,34 +1875,34 @@ - Release + XMC4400 ARM - 0 + 1 General 3 - 21 + 22 1 - 0 + 1 + ICCARM 2 - 28 + 29 1 - 0 + 1 + AARM 2 - 8 + 9 1 - 0 + 1 + @@ -1480,7 +2448,7 @@ 1 1 - 0 + 1 @@ -1817,7 +2789,7 @@ 0 1 - 0 + 1 Common_Demo_Source - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\..\Common\Minimal\blocktim.c - - $PROJ_DIR$\..\Common\Minimal\countsem.c - - - $PROJ_DIR$\..\Common\Minimal\death.c - $PROJ_DIR$\..\Common\Minimal\dynamic.c @@ -1859,17 +2822,14 @@ $PROJ_DIR$\..\Common\Minimal\GenQTest.c - $PROJ_DIR$\..\Common\Minimal\integer.c + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c - $PROJ_DIR$\..\Common\Minimal\PollQ.c + $PROJ_DIR$\..\Common\Minimal\QueueSet.c $PROJ_DIR$\..\Common\Minimal\recmutex.c - - $PROJ_DIR$\..\Common\Minimal\semtest.c - $PROJ_DIR$\..\Common\Minimal\sp_flop.c @@ -1877,7 +2837,7 @@ FreeRTOS_Source - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c $PROJ_DIR$\..\..\Source\list.c @@ -1901,12 +2861,51 @@ System - $PROJ_DIR$\system\low_level_init.c + $PROJ_DIR$\system\startup_XMC4200.s + + XMC4500 + XMC4400 + + + + $PROJ_DIR$\system\startup_XMC4400.s + + XMC4500 + XMC4200 + + + + $PROJ_DIR$\system\startup_XMC4500.s + + XMC4200 + XMC4400 + - $PROJ_DIR$\system\CMSIS\DeviceSupport\Infineon\XMC45xx\System_XMC4500.c + $PROJ_DIR$\system\System_XMC4200.c + + XMC4500 + XMC4400 + + + + $PROJ_DIR$\system\System_XMC4400.c + + XMC4500 + XMC4200 + + + + $PROJ_DIR$\system\system_XMC4500.c + + XMC4200 + XMC4400 + + + $PROJ_DIR$\FreeRTOSConfig.h + $PROJ_DIR$\main.c @@ -1919,9 +2918,6 @@ $PROJ_DIR$\RegTest.s - - $PROJ_DIR$\system\CMSIS\DeviceSupport\Infineon\XMC45xx\startup\iar\vector_table_M_forXMC4500.s - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c deleted file mode 100644 index cf2aeaed9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -__asm vRegTest1Task( void ) -{ - PRESERVE8 - IMPORT ulRegTest1LoopCounter - - /* Fill the core registers with known values. */ - mov r0, #100 - mov r1, #101 - mov r2, #102 - mov r3, #103 - mov r4, #104 - mov r5, #105 - mov r6, #106 - mov r7, #107 - mov r8, #108 - mov r9, #109 - mov r10, #110 - mov r11, #111 - mov r12, #112 - - /* Fill the VFP registers with known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg1_loop - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d1 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d2 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d3 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d4 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d5 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d6 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d7 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d8 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d9 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d10 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d11 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d12 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d13 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d14 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d15 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg1_loopf_pass - -reg1_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg1_error_loopf - -reg1_loopf_pass - - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - cmp r8, #108 - bne reg1_error_loop - cmp r9, #109 - bne reg1_error_loop - cmp r10, #110 - bne reg1_error_loop - cmp r11, #111 - bne reg1_error_loop - cmp r12, #112 - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg1_loop - -reg1_error_loop - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop -} -/*-----------------------------------------------------------*/ - -__asm vRegTest2Task( void ) -{ - PRESERVE8 - IMPORT ulRegTest2LoopCounter - - /* Set all the core registers to known values. */ - mov r0, #-1 - mov r1, #1 - mov r2, #2 - mov r3, #3 - mov r4, #4 - mov r5, #5 - mov r6, #6 - mov r7, #7 - mov r8, #8 - mov r9, #9 - mov r10, #10 - mov r11, #11 - mov r12, #12 - - /* Set all the VFP to known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg2_loop - - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d1 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d2 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d3 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d4 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d5 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d6 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d7 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d8 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d9 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d10 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d11 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d12 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d13 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d14 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d15 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg2_loopf_pass - -reg2_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg2_error_loopf - -reg2_loopf_pass - - cmp r0, #-1 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - cmp r8, #8 - bne reg2_error_loop - cmp r9, #9 - bne reg2_error_loop - cmp r10, #10 - bne reg2_error_loop - cmp r11, #11 - bne reg2_error_loop - cmp r12, #12 - bne reg2_error_loop - - /* Increment the loop counter to indicate this test is still functioning - correctly. */ - push { r0-r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg2_loop - -reg2_error_loop - /* If this line is hit then there was an error in a core register value. - This loop ensures the loop counter variable stops incrementing. */ - b reg2_error_loop - nop -} -/*-----------------------------------------------------------*/ - -__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue ) -{ - PRESERVE8 - - /* Clobber the auto saved registers. */ - vmov d0, r0, r0 - vmov d1, r0, r0 - vmov d2, r0, r0 - vmov d3, r0, r0 - vmov d4, r0, r0 - vmov d5, r0, r0 - vmov d6, r0, r0 - vmov d7, r0, r0 - bx lr -} -/*-----------------------------------------------------------*/ - -__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue ) -{ - PRESERVE8 - - vmov r1, s0 - cmp r0, r1 - bne return_error - vmov r1, s1 - cmp r0, r1 - bne return_error - vmov r1, s2 - cmp r0, r1 - bne return_error - vmov r1, s3 - cmp r0, r1 - bne return_error - vmov r1, s4 - cmp r0, r1 - bne return_error - vmov r1, s5 - cmp r0, r1 - bne return_error - vmov r1, s6 - cmp r0, r1 - bne return_error - vmov r1, s7 - cmp r0, r1 - bne return_error - vmov r1, s8 - cmp r0, r1 - bne return_error - vmov r1, s9 - cmp r0, r1 - bne return_error - vmov r1, s10 - cmp r0, r1 - bne return_error - vmov r1, s11 - cmp r0, r1 - bne return_error - vmov r1, s12 - cmp r0, r1 - bne return_error - vmov r1, s13 - cmp r0, r1 - bne return_error - vmov r1, s14 - cmp r0, r1 - bne return_error - vmov r1, s15 - cmp r0, r1 - bne return_error - -return_pass - mov r0, #1 - bx lr - -return_error - mov r0, #0 - bx lr -} - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s index bd89de3f7..45105d369 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s @@ -75,7 +75,7 @@ PUBLIC vRegTest2Task PUBLIC vRegTestClearFlopRegistersToParameterValue PUBLIC ulRegTestCheckFlopRegistersContainParameterValue - + /*-----------------------------------------------------------*/ vRegTest1Task @@ -117,7 +117,7 @@ reg1_loop: /* Check all the VFP registers still contain the values set above. First save registers that are clobbered by the test. */ push { r0-r1 } - + vmov r0, r1, d0 cmp r0, #100 bne reg1_error_loopf @@ -198,10 +198,10 @@ reg1_loop: bne reg1_error_loopf cmp r1, #107 bne reg1_error_loopf - + /* Restore the registers that were clobbered by the test. */ pop {r0-r1} - + /* VFP register test passed. Jump to the core register test. */ b reg1_loopf_pass @@ -238,7 +238,7 @@ reg1_loopf_pass bne reg1_error_loop cmp r12, #112 bne reg1_error_loop - + /* Everything passed, increment the loop counter. */ push { r0-r1 } ldr r0, =ulRegTest1LoopCounter @@ -246,7 +246,7 @@ reg1_loopf_pass adds r1, r1, #1 str r1, [r0] pop { r0-r1 } - + /* Start again. */ b reg1_loop @@ -294,11 +294,11 @@ vRegTest2Task vmov d15, r6, r7 reg2_loop: - + /* Check all the VFP registers still contain the values set above. First save registers that are clobbered by the test. */ push { r0-r1 } - + vmov r0, r1, d0 cmp r0, #-1 bne reg2_error_loopf @@ -379,10 +379,10 @@ reg2_loop: bne reg2_error_loopf cmp r1, #7 bne reg2_error_loopf - + /* Restore the registers that were clobbered by the test. */ pop {r0-r1} - + /* VFP register test passed. Jump to the core register test. */ b reg2_loopf_pass @@ -419,7 +419,7 @@ reg2_loopf_pass bne reg2_error_loop cmp r12, #12 bne reg2_error_loop - + /* Increment the loop counter to indicate this test is still functioning correctly. */ push { r0-r1 } @@ -427,8 +427,16 @@ reg2_loopf_pass ldr r1, [r0] adds r1, r1, #1 str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + pop { r0-r1 } - + /* Start again. */ b reg2_loop @@ -504,7 +512,7 @@ ulRegTestCheckFlopRegistersContainParameterValue vmov r1, s15 cmp r0, r1 bne return_error - + return_pass mov r0, #1 bx lr @@ -514,4 +522,4 @@ return_error bx lr END - + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c index b9ad4ebb4..9dfc362fd 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c @@ -92,9 +92,9 @@ #include "FreeRTOS.h" #include "task.h" -/* Hardware includes. */ -#include "XMC4500.h" -#include "System_XMC4500.h" +/* Standard demo includes. */ +#include "QueueSet.h" +#include "QueueOverwrite.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, or 0 to run the more comprehensive test and demo application. */ @@ -139,13 +139,7 @@ int main( void ) static void prvSetupHardware( void ) { -extern void SystemCoreClockUpdate( void ); - - /* Ensure SystemCoreClock variable is set. */ - SystemCoreClockUpdate(); - - /* Configure pin P3.9 for the LED. */ - PORT3->IOCR8 = 0x00008000; + configCONFIGURE_LED(); /* Ensure all priority bits are assigned as preemption priority bits. */ NVIC_SetPriorityGrouping( 0 ); @@ -203,6 +197,17 @@ void vApplicationTickHook( void ) added here, but the tick hook is called from an interrupt context, so code must not attempt to block, and only the interrupt safe FreeRTOS API functions can be used (those that end in FromISR()). */ + + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* Write to a queue that is in use as part of the queue set demo to + demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + + /* Test the ISR safe queue overwrite functions. */ + vQueueOverwritePeriodicISRDemo(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ } /*-----------------------------------------------------------*/ @@ -214,12 +219,12 @@ long lHigherPriorityTaskWoken = pdFALSE; /* Clear the interrupt if necessary. */ Dummy_ClearITPendingBit(); - + /* This interrupt does nothing more than demonstrate how to synchronise a task with an interrupt. A semaphore is used for this purpose. Note lHigherPriorityTaskWoken is initialised to zero. */ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - + /* If there was a task that was blocked on the semaphore, and giving the semaphore caused the task to unblock, and the unblocked task has a priority higher than the current Running state task (the task that this interrupt diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c index cbc2ba905..83d8398d8 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c @@ -107,10 +107,6 @@ #include "task.h" #include "semphr.h" -/* Hardware includes. */ -#include "XMC4500.h" -#include "System_XMC4500.h" - /* Priorities at which the tasks are created. */ #define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) @@ -129,9 +125,6 @@ functionality. */ #define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) #define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) -/* To toggle the single LED */ -#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) - /*-----------------------------------------------------------*/ /* @@ -146,11 +139,6 @@ static void prvQueueSendTask( void *pvParameters ); */ void main_blinky( void ); -/* - * The hardware only has a single LED. Simply toggle it. - */ -extern void vMainToggleLED( void ); - /*-----------------------------------------------------------*/ /* The queue used by both tasks. */ @@ -235,7 +223,7 @@ unsigned long ulReceivedValue; is it the expected value? If it is, toggle the LED. */ if( ulReceivedValue == 100UL ) { - mainTOGGLE_LED(); + configTOGGLE_LED(); ulReceivedValue = 0U; } } diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c index ded660a6e..29c5be7bd 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c @@ -75,8 +75,8 @@ ****************************************************************************** * * main_full() creates all the demo application tasks and a software timer, then - * starts the scheduler. The web documentation provides more details of the - * standard demo application tasks, which provide no particular functionality, + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, * but do provide a good example of how to use the FreeRTOS API. * * In addition to the standard demo tasks, the following tasks and tests are @@ -113,20 +113,14 @@ /* Standard demo application includes. */ #include "flop.h" -#include "integer.h" -#include "PollQ.h" #include "semtest.h" #include "dynamic.h" -#include "BlockQ.h" #include "blocktim.h" #include "countsem.h" #include "GenQTest.h" #include "recmutex.h" -#include "death.h" - -/* Hardware includes. */ -#include "XMC4500.h" -#include "System_XMC4500.h" +#include "QueueSet.h" +#include "QueueOverwrite.h" /* Priorities for the demo application tasks. */ #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) @@ -135,9 +129,6 @@ #define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) #define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -/* To toggle the single LED */ -#define mainTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) - /* A block time of zero simply means "don't block". */ #define mainDONT_BLOCK ( 0UL ) @@ -183,17 +174,14 @@ xTimerHandle xCheckTimer = NULL; /* Start all the other standard demo/test tasks. The have not particular functionality, but do demonstrate how to use the FreeRTOS API and test the kernel port. */ - vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vStartQueueSetTasks(); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); vStartGenericQueueTasks( tskIDLE_PRIORITY ); vStartRecursiveMutexTasks(); - vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); vStartMathTasks( mainFLOP_TASK_PRIORITY ); - + /* Create the register check tasks, as described at the top of this file */ xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); @@ -206,27 +194,22 @@ xTimerHandle xCheckTimer = NULL; pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ ( void * ) 0, /* The ID is not used, so can be set to anything. */ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - + ); + if( xCheckTimer != NULL ) { xTimerStart( xCheckTimer, mainDONT_BLOCK ); } - /* The set of tasks created by the following function call have to be - created last as they keep account of the number of tasks they expect to see - running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - /* Start the scheduler. */ vTaskStartScheduler(); - + /* If all is well, the scheduler will now be running, and the following line will never be reached. If the following line does execute, then there was insufficient FreeRTOS heap memory available for the idle and/or timer tasks to be created. See the memory management section on the FreeRTOS web site for more details. */ - for( ;; ); + for( ;; ); } /*-----------------------------------------------------------*/ @@ -244,21 +227,11 @@ unsigned long ulErrorFound = pdFALSE; ulErrorFound = pdTRUE; } - if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) { ulErrorFound = pdTRUE; } - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) { ulErrorFound = pdTRUE; @@ -274,21 +247,16 @@ unsigned long ulErrorFound = pdFALSE; ulErrorFound = pdTRUE; } - if( xIsCreateTaskStillRunning() != pdTRUE ) + if( xAreQueueSetTasksStillRunning() != pdTRUE ) { ulErrorFound = pdTRUE; } - if( xArePollingQueuesStillRunning() != pdTRUE ) + if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) { ulErrorFound = pdTRUE; } - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - /* Check that the register test 1 task is still running. */ if( ulLastRegTest1Value == ulRegTest1LoopCounter ) { @@ -306,8 +274,8 @@ unsigned long ulErrorFound = pdFALSE; /* Toggle the check LED to give an indication of the system status. If the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then everything is ok. A faster toggle indicates an error. */ - mainTOGGLE_LED(); - + configTOGGLE_LED(); + /* Have any errors been latch in ulErrorFound? If so, shorten the period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. This will result in an increase in the rate at which mainCHECK_LED @@ -317,7 +285,7 @@ unsigned long ulErrorFound = pdFALSE; if( lChangedTimerPeriodAlready == pdFALSE ) { lChangedTimerPeriodAlready = pdTRUE; - + /* This call to xTimerChangePeriod() uses a zero block time. Functions called from inside of a timer callback function must *never* attempt to block. */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat deleted file mode 100644 index 58a800489..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.cspy.bat +++ /dev/null @@ -1,24 +0,0 @@ -@REM This batch file has been generated by the IAR Embedded Workbench -@REM C-SPY Debugger, as an aid to preparing a command line for running -@REM the cspybat command line utility using the appropriate settings. -@REM -@REM Note that this file is generated every time a new debug session -@REM is initialized, so you may want to move or rename the file before -@REM making changes. -@REM -@REM You can launch cspybat by typing the name of this batch file followed -@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). -@REM -@REM Read about available command line parameters in the C-SPY Debugging -@REM Guide. Hints about additional command line parameters that may be -@REM useful in specific cases: -@REM --download_only Downloads a code image without starting a debug -@REM session afterwards. -@REM --silent Omits the sign-on message. -@REM --timeout Limits the maximum allowed execution time. -@REM - - -"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --macro "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\Infineon\Trace_XMC4500.dmac" --backend -B "--endian=little" "--cpu=Cortex-M4F" "--fpu=VFPv4" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc4500.ddf" "--semihosting" "--device=xmc4500" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" "--jlink_script_file=C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\Infineon\XMC4500.jlinkscript" "--drv_swo_clock_setup=72000000,0,2000000" - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt deleted file mode 100644 index 33f4649c2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dbgdt +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni deleted file mode 100644 index 297b67265..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.dni +++ /dev/null @@ -1,17 +0,0 @@ -[Stack] -FillEnabled=0 -OverflowWarningsEnabled=1 -WarningThreshold=90 -SpWarningsEnabled=1 -WarnLogOnly=1 -UseTrigger=1 -TriggerName=main -LimitSize=0 -ByteLimit=50 -[Disassemble mode] -mode=0 -[Breakpoints2] -Count=0 -[Aliases] -Count=0 -SuppressDialog=0 diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt deleted file mode 100644 index 81d875313..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/settings/RTOSDemo.wsdt +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - RTOSDemo/Debug - - - - - - - - - 124272727 - - 20121632481 - - - - - - TabID-11195-18312 - Workspace - Workspace - - - RTOSDemo - - - - 0TabID-6727-18343BuildBuild0 - - - - - - TextEditor$WS_DIR$\main.c00000630000100000010000001 - - - - - - - iaridepm.enu1-2-2740198-2-2200200119048203666119048755601-2-21981682-2-216842001002381203666119048203666 - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c deleted file mode 100644 index c4f5fe876..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/System_XMC4500.c +++ /dev/null @@ -1,412 +0,0 @@ -/****************************************************************************** - * @file system_XMC4500.c - * @brief Device specific initialization for the XMC4500-Series according to CMSIS - * @version V2.2 - * @date 20. January 2012 - * - * @note - * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. - * This file can be freely distributed within development tools that are supporting such microcontrollers. - - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * - ******************************************************************************/ - -#include "System_XMC4500.h" -#include - -/*---------------------------------------------------------------------------- - Define clocks is located in System_XMC4500.h - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock = CLOCK_OSC_HP; - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 - - - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> USB Clock -// <3=> Divided value of PLL Clock -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 // recommended to keep disabled -#define SCU_CLOCKOUT_SOURCE 0x00000000 -#define SCU_CLOCKOUT_PIN 0x00000000 - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static void USBClockSetup(void); -#endif - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -/* Setup the WDT */ -#if (WDT_SETUP == 1) -WDT->CTR &= ~WDTENB_nVal; -#endif - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Disable branch prediction - PCON.PBS = 1 */ -PREF->PCON |= (PREF_PCON_PBS_Msk); - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the clockout */ -/* README README README README README README README README README README */ -/* - * Please use the CLOCKOUT feature with diligence. Use this only if you know - * what you are doing. - * - * You must be aware that the settings below can potentially be in conflict - * with DAVE code generation engine preferences. - * - * Even worse, the setting below configures the ports as output ports while in - * reality, the board on which this chip is mounted may have a source driving - * the ports. - * - * So use this feature only when you are absolutely sure that the port must - * indeed be configured as an output AND you are NOT linking this startup code - * with code that was generated by DAVE code engine. - */ -#if (SCU_CLOCKOUT_SETUP == 1) -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - } -else PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ -#endif - -/* Setup the System clock */ -#if (SCU_CLOCK_SETUP == 1) -SystemClockSetup(); -#endif - -/* Setup the USB PL */ -#if (SCU_USB_CLOCK_SETUP == 1) -USBClockSetup(); -#endif - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClock = SYSTEM_FREQUENCY;/*!< System Clock Frequency (Core Clock)*/ - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | - SCU_PLL_PLLCON0_PLLPWD_Msk); - -/* Enable OSC_HP */ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /* Enable the OSC_HP*/ - SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); - /* Setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); - /* Select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* Restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - do - { - ; /* here a timeout need to be added */ - }while(!( (SCU_PLL->PLLSTAT) & - (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk | - SCU_PLL_PLLSTAT_PLLSP_Msk) - ) - ); - - } - -/* Setup Main PLL */ - /* Select FOFI as system clock */ - if(SCU_CLK->SYSCLKCR != 0X000000) - SCU_CLK->SYSCLKCR = 0x00000000; /*Select FOFI*/ - - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | - (PLL_K2DIV_STEP_1<<16) | (PLL_PDIV<<24)); - - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - - /* wait for PLL Lock */ - while (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)); - - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /********************************************************* - here the ramp up of the system clock starts - *********************************************************/ - /* Delay for next K2 step ~50µs */ - /********************************/ - /* Set reload register */ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1; - - /* Load the SysTick Counter Value */ - SysTick->VAL = 0; - - /* Enable SysTick IRQ and SysTick Timer */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; - - /* wait for ~50µs */ - while (SysTick->VAL >= 100); - - /* Stop SysTick Timer */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | - (PLL_K2DIV_STEP_2<<16) | (PLL_PDIV<<24)); - - /* Delay for next K2 step ~50µs */ - /********************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - - /* Load the SysTick Counter Value */ - SysTick->VAL = 0; - - /* Enable SysTick IRQ and SysTick Timer */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; - - /* Wait for ~50µs */ - while (SysTick->VAL >= 100); - - /* Stop SysTick Timer */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | - (PLL_K2DIV_STEP_3<<16) | (PLL_PDIV<<24)); - - /* Delay for next K2 step ~50µs */ - /********************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - - /* Load the SysTick Counter Value */ - SysTick->VAL = 0; - - /* Enable SysTick IRQ and SysTick Timer */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; - - /* Wait for ~50µs */ - while (SysTick->VAL >= 100); - - /* Stop SysTick Timer */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((PLL_K1DIV) | (PLL_NDIV<<8) | (PLL_K2DIV<<16) | - (PLL_PDIV<<24)); - - /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | - SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; - - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if(SCU_USB_CLOCK_SETUP == 1) -static void USBClockSetup(void) -{ -/* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | - SCU_PLL_USBPLLCON_PLLPWD_Msk); - -/* check and if not already running enable OSC_HP */ - if(!((SCU_PLL->PLLSTAT) & - (SCU_PLL_PLLSTAT_PLLHV_Msk | - SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))) - { - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - - SCU_OSC->OSCHPCTRL = (OSC_HP_MODE<<4); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - do - { - ; /* here a timeout need to be added */ - }while(!((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | - SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk))); - - } - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((USBPLL_NDIV<<8) | (USBPLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - } -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h deleted file mode 100644 index 20791a82f..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/CMSIS/DeviceSupport/Infineon/XMC45xx/XMC4500.h +++ /dev/null @@ -1,20654 +0,0 @@ -/****************************************************************************/ -/** -* @file XMC4500.h -* XMC4000 Device Series -* @version V1.14 -* @date 23 Feb 2012 -* -Copyright (C) 2011-2012 Infineon Technologies AG. All rights reserved. -* -* -* @par -* Infineon Technologies AG (Infineon) is supplying this software for use with Infineon's -* microcontrollers. This file can be freely distributed -* within development tools that are supporting such microcontrollers. -* -* @par -* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -* -******************************************************************************/ - -/** @mainpage CMSIS device specific (XMC4500) peripheral access layer. -* -* @par -* This file provides the XMC4500 Device specific peripheral access layer for -* all peripherals. This file contains all the data structures and the address -* mapping of the device specific peripherals. -* @par -* The file also provides interrupt numbers (IRQHandler) for all core and device -* specific exceptions and interrupts. -* -*/ - -#ifndef __XMC4500_H__ -#define __XMC4500_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - - -/******************************************** -** Start of section using anonymous unions ** -*********************************************/ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ - #elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - -/* -* ========================================================================== -* --------------------- __NVIC_PRIO_BITS ----------------------------------- -* ========================================================================== -*/ -#ifndef __NVIC_PRIO_BITS -#define __NVIC_PRIO_BITS (6) -#endif - -/* -* ========================================================================== -* ----------------------------- M4 Stuff ----------------------------------- -* ========================================================================== -*/ -#define __CM4_REV 0x0001 /**< Core revision r0p1 */ -#define __MPU_PRESENT 1 /**< MPU present or not */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /**< FPU present or not */ - -/* -* ========================================================================== -* ---------- Interrupt Number Definition ----------------------------------- -* ========================================================================== -*/ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers **********************************/ -NMI_IRQn = -14, /*!< 2 Non Maskable Interrupt */ -MemManage_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ -BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ -UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ -SVC_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ -DebugMon_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ -PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ -SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ - -/****** XMC45xx Specific Interrupt Numbers ***************************************/ -SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */ -ERU0_0_IRQn = 1, /*!< SCU SR1 Interrupt */ -ERU0_1_IRQn = 2, /*!< SCU SR2 Interrupt */ -ERU0_2_IRQn = 3, /*!< SCU SR3 Interrupt */ -ERU0_3_IRQn = 4, /*!< SCU SR4 Interrupt */ -ERU1_0_IRQn = 5, /*!< SCU SR5 Interrupt */ -ERU1_1_IRQn = 6, /*!< SCU SR6 Interrupt */ -ERU1_2_IRQn = 7, /*!< SCU SR7 Interrupt */ -ERU1_3_IRQn = 8, /*!< SCU SR8 Interrupt */ -PMU0_0_IRQn = 12, /*!< PMU SR0 Interrupt */ -VADC0_C0_0_IRQn = 14, /*!< VADC SR0 Interrupt */ -VADC0_C0_1_IRQn = 15, /*!< VADC SR1 Interrupt */ -VADC0_C0_2_IRQn = 16, /*!< VADC SR2 Interrupt */ -VADC0_C0_3_IRQn = 17, /*!< VADC SR3 Interrupt */ -VADC0_G0_0_IRQn = 18, /*!< VADC SR4 Interrupt */ -VADC0_G0_1_IRQn = 19, /*!< VADC SR5 Interrupt */ -VADC0_G0_2_IRQn = 20, /*!< VADC SR6 Interrupt */ -VADC0_G0_3_IRQn = 21, /*!< VADC SR7 Interrupt */ -VADC0_G1_0_IRQn = 22, /*!< VADC SR8 Interrupt */ -VADC0_G1_1_IRQn = 23, /*!< VADC SR9 Interrupt */ -VADC0_G1_2_IRQn = 24, /*!< VADC SR10 Interrupt */ -VADC0_G1_3_IRQn = 25, /*!< VADC SR11 Interrupt */ -VADC0_G2_0_IRQn = 26, /*!< VADC SR12 Interrupt */ -VADC0_G2_1_IRQn = 27, /*!< VADC SR13 Interrupt */ -VADC0_G2_2_IRQn = 28, /*!< VADC SR14 Interrupt */ -VADC0_G2_3_IRQn = 29, /*!< VADC SR15 Interrupt */ -VADC0_G3_0_IRQn = 30, /*!< VADC SR16 Interrupt */ -VADC0_G3_1_IRQn = 31, /*!< VADC SR17 Interrupt */ -VADC0_G3_2_IRQn = 32, /*!< VADC SR18 Interrupt */ -VADC0_G3_3_IRQn = 33, /*!< VADC SR19 Interrupt */ -DSD0_M_0_IRQn = 34, /*!< DSD SR0 Interrupt */ -DSD0_M_1_IRQn = 35, /*!< DSD SR1 Interrupt */ -DSD0_M_2_IRQn = 36, /*!< DSD SR2 Interrupt */ -DSD0_M_3_IRQn = 37, /*!< DSD SR3 Interrupt */ -DSD0_A_4_IRQn = 38, /*!< DSD SR4 Interrupt */ -DSD0_A_5_IRQn = 39, /*!< DSD SR5 Interrupt */ -DSD0_A_6_IRQn = 40, /*!< DSD SR6 Interrupt */ -DSD0_A_7_IRQn = 41, /*!< DSD SR7 Interrupt */ -DAC0_0_IRQn = 42, /*!< DAC SR0 Interrupt */ -DAC1_1_IRQn = 43, /*!< DAC SR1 Interrupt */ -CCU40_0_IRQn = 44, /*!< CCU40 SR0 Interrupt */ -CCU40_1_IRQn = 45, /*!< CCU40 SR1 Interrupt */ -CCU40_2_IRQn = 46, /*!< CCU40 SR2 Interrupt */ -CCU40_3_IRQn = 47, /*!< CCU40 SR3 Interrupt */ -CCU41_0_IRQn = 48, /*!< CCU41 SR0 Interrupt */ -CCU41_1_IRQn = 49, /*!< CCU41 SR1 Interrupt */ -CCU41_2_IRQn = 50, /*!< CCU41 SR2 Interrupt */ -CCU41_3_IRQn = 51, /*!< CCU41 SR3 Interrupt */ -CCU42_0_IRQn = 52, /*!< CCU42 SR0 Interrupt */ -CCU42_1_IRQn = 53, /*!< CCU42 SR1 Interrupt */ -CCU42_2_IRQn = 54, /*!< CCU42 SR2 Interrupt */ -CCU42_3_IRQn = 55, /*!< CCU42 SR3 Interrupt */ -CCU43_0_IRQn = 56, /*!< CCU43 SR0 Interrupt */ -CCU43_1_IRQn = 57, /*!< CCU43 SR1 Interrupt */ -CCU43_2_IRQn = 58, /*!< CCU43 SR2 Interrupt */ -CCU43_3_IRQn = 59, /*!< CCU43 SR3 Interrupt */ -CCU80_0_IRQn = 60, /*!< CCU80 SR0 Interrupt */ -CCU80_1_IRQn = 61, /*!< CCU80 SR1 Interrupt */ -CCU80_2_IRQn = 62, /*!< CCU80 SR2 Interrupt */ -CCU80_3_IRQn = 63, /*!< CCU80 SR3 Interrupt */ -CCU81_0_IRQn = 64, /*!< CCU81 SR0 Interrupt */ -CCU81_1_IRQn = 65, /*!< CCU81 SR1 Interrupt */ -CCU81_2_IRQn = 66, /*!< CCU81 SR2 Interrupt */ -CCU81_3_IRQn = 67, /*!< CCU81 SR3 Interrupt */ -POSIF0_0_IRQn = 68, /*!< POSIF0 SR0 Interrupt */ -POSIF0_1_IRQn = 69, /*!< POSIF0 SR1 Interrupt */ -POSIF1_0_IRQn = 70, /*!< POSIF1 SR0 Interrupt */ -POSIF1_1_IRQn = 71, /*!< POSIF1 SR1 Interrupt */ -CAN0_0_IRQn = 76, /*!< MCAN SR0 Interrupt */ -CAN0_1_IRQn = 77, /*!< MCAN SR1 Interrupt */ -CAN0_2_IRQn = 78, /*!< MCAN SR2 Interrupt */ -CAN0_3_IRQn = 79, /*!< MCAN SR3 Interrupt */ -CAN0_4_IRQn = 80, /*!< MCAN SR4 Interrupt */ -CAN0_5_IRQn = 81, /*!< MCAN SR5 Interrupt */ -CAN0_6_IRQn = 82, /*!< MCAN SR6 Interrupt */ -CAN0_7_IRQn = 83, /*!< MCAN SR7 Interrupt */ -USIC0_0_IRQn = 84, /*!< USIC0 SR0 Interrupt */ -USIC0_1_IRQn = 85, /*!< USIC0 SR1 Interrupt */ -USIC0_2_IRQn = 86, /*!< USIC0 SR2 Interrupt */ -USIC0_3_IRQn = 87, /*!< USIC0 SR3 Interrupt */ -USIC0_4_IRQn = 88, /*!< USIC0 SR4 Interrupt */ -USIC0_5_IRQn = 89, /*!< USIC0 SR5 Interrupt */ -USIC1_0_IRQn = 90, /*!< USIC1 SR0 Interrupt */ -USIC1_1_IRQn = 91, /*!< USIC1 SR1 Interrupt */ -USIC1_2_IRQn = 92, /*!< USIC1 SR2 Interrupt */ -USIC1_3_IRQn = 93, /*!< USIC1 SR3 Interrupt */ -USIC1_4_IRQn = 94, /*!< USIC1 SR4 Interrupt */ -USIC1_5_IRQn = 95, /*!< USIC1 SR5 Interrupt */ -USIC2_0_IRQn = 96, /*!< USIC2 SR0 Interrupt */ -USIC2_1_IRQn = 97, /*!< USIC2 SR1 Interrupt */ -USIC2_2_IRQn = 98, /*!< USIC2 SR2 Interrupt */ -USIC2_3_IRQn = 99, /*!< USIC2 SR3 Interrupt */ -USIC2_4_IRQn = 100, /*!< USIC2 SR4 Interrupt */ -USIC2_5_IRQn = 101, /*!< USIC2 SR5 Interrupt */ -LEDTS0_0_IRQn = 102, /*!< LEDTSU SR0 Interrupt */ -FCE0_0_IRQn = 104, /*!< FCE SR0 Interrupt */ -GPDMA0_0_IRQn = 105, /*!< GPDMA SR0 Interrupt */ -SDMMC0_0_IRQn = 106, /*!< MMCI SR0 Interrupt */ -USB0_0_IRQn = 107, /*!< USB SR0 Interrupt */ -ETH0_0_IRQn = 108, /*!< ETH SR0 Interrupt */ -GPDMA1_0_IRQn = 110 /*!< GPDMA1 SR0 Interrupt */ -}IRQn_Type; - - -/* -* ========================================================================== -* ----------- Processor and Core Peripheral Section ------------------------ -* ========================================================================== -*/ - -/** Macro to write new value to the bits in register */ -#define WR_REG(reg, mask, pos, val) { \ - reg &= ~(mask);\ - reg |= (val << pos) & mask;\ - } - -/** Macro to read the bits in register */ -#define RD_REG(reg, mask, pos) (((reg)&mask) >> pos) -/** Macro to set the particular bit in register */ -#define SET_BIT(reg, pos) (reg) |= (1U< /* Cortex-M4 processor and core peripherals */ -#include "system_XMC4500.h" - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -/***************************************************************************/ -/* CAN */ -/***************************************************************************/ - - /* - *CAN GLOBAL registers - */ -typedef struct { -__IO uint32_t CLC; /*! - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 - - - -/* - * mandatory clock parameters ************************************************** - */ -/* source for clock generation - * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) - * - **************************************************************************************/ - -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -#define CLOCK_OSC_HP 24000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define SYSTEM_FREQUENCY 120000000 - -/* OSC_HP setup parameters */ -#define OSC_HP_MODE 0 -#define OSCHPWDGDIV 2 - -/* MAIN PLL setup parameters */ - - -#define PLL_K1DIV 1 -#define PLL_K2DIV 3 -#define PLL_PDIV 1 -#define PLL_NDIV 79 - - - -#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz -#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz -#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz - - - -#define USBPLL_PDIV 1 -#define USBPLL_NDIV 15 - - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c new file mode 100644 index 000000000..d2385b4b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file system_XMC4200.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4000 Device Series + * @version V3.0.1 Alpha + * @date 26. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 80000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 5 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 5 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c new file mode 100644 index 000000000..70162d923 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file system_XMC4400.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h new file mode 100644 index 000000000..3984b45cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h @@ -0,0 +1,13138 @@ + +/****************************************************************************************************//** + * @file XMC4200.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * XMC4200 from Infineon. + * + * @version V1.1.0 (Reference Manual v1.1) + * @date 10. January 2013 + * + * @note Generated with SVDConv V2.78b + * from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1), + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC4200 + * @{ + */ + +#ifndef XMC4200_H +#define XMC4200_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC4200 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< 0 SCU_0 */ + ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */ + ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */ + ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */ + ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */ + ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */ + ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */ + ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */ + ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */ + PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */ + VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */ + VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */ + VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */ + VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */ + VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */ + VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */ + VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */ + VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */ + VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */ + VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */ + VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */ + VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */ + DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */ + DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */ + CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */ + CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */ + CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */ + CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */ + CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */ + CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */ + CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */ + CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */ + CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */ + CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */ + CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */ + CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */ + POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */ + POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */ + HRPWM_0_IRQn = 72, /*!< 72 HRPWM_0 */ + HRPWM_1_IRQn = 73, /*!< 73 HRPWM_1 */ + HRPWM_2_IRQn = 74, /*!< 74 HRPWM_0 */ + HRPWM_3_IRQn = 75, /*!< 75 HRPWM_1 */ + CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */ + CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */ + CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */ + CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */ + CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */ + CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */ + CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */ + CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */ + USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */ + USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */ + USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */ + USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */ + USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */ + USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */ + USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */ + USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */ + USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */ + USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */ + USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */ + USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */ + LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */ + FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */ + GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */ + USB0_0_IRQn = 107, /*!< 107 USB0_0 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4200.h" /*!< XMC4200 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4400.h" /*!< XMC4400 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4500.h" /*!< XMC4500 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h new file mode 100644 index 000000000..953e1b099 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_XMC4400.h + * @brief Header file for the XMC4400-Series systeminit + * + * @version V1.0 + * @date 17. August 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4400_H +#define __SYSTEM_XMC4400_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c new file mode 100644 index 000000000..74ecf74d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c @@ -0,0 +1,705 @@ +/**************************************************************************//** + * @file system_XMC4500.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "system_XMC4500.h" +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000003 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + + /* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h new file mode 100644 index 000000000..73eb6d590 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file system_XMC4500.h + * @brief Header file for the XMC4500-Series systeminit + * + * @version V1.6 + * @date 23. October 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4500_H +#define __SYSTEM_XMC4500_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 + + + +/* + * mandatory clock parameters ************************************************** + */ +/* source for clock generation + * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) + * mandatory for old system_xmc4500.c files - please do not remove!!! + **************************************************************************************/ + +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +#define CLOCK_OSC_HP 24000000 +#define CLOCK_BACK_UP 24000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define SYSTEM_FREQUENCY 120000000 + +/* OSC_HP setup parameters */ +#define OSC_HP_MODE 0 +#define OSCHPWDGDIV 2 + +/* MAIN PLL setup parameters */ + + +#define PLL_K1DIV 1 +#define PLL_K2DIV 3 +#define PLL_PDIV 1 +#define PLL_NDIV 79 + + + +#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz +#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz +#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz + + + +#define USBPLL_PDIV 1 +#define USBPLL_NDIV 15 + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt index adb4267af..c03a8bbea 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt @@ -734,7 +734,7 @@ Demo_Source - 0 + 1 0 0 0 @@ -744,9 +744,9 @@ 1 0 0 - 0 + 4 0 - 64 + 113 140 0 .\main.c @@ -778,8 +778,8 @@ 0 0 0 - 0 - 0 + 367 + 418 0 .\RegTest.c RegTest.c @@ -926,7 +926,7 @@ Common_Demo_Source - 0 + 1 0 0 0 diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c index cf2aeaed9..2c42e38f1 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c @@ -418,6 +418,14 @@ reg2_loopf_pass ldr r1, [r0] adds r1, r1, #1 str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + pop { r0-r1 } /* Start again. */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c index 8d415a924..768a44d96 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c @@ -135,8 +135,8 @@ int main( void ) static void prvSetupHardware( void ) { -extern void SystemCoreClockUpdate( void ); - + configCONFIGURE_LED(); + /* Ensure all priority bits are assigned as preemption priority bits. */ NVIC_SetPriorityGrouping( 0 ); } diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c index b93e72df2..a9cda91ad 100644 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c @@ -113,16 +113,12 @@ /* Standard demo application includes. */ #include "flop.h" -#include "integer.h" -#include "PollQ.h" #include "semtest.h" #include "dynamic.h" -#include "BlockQ.h" #include "blocktim.h" #include "countsem.h" #include "GenQTest.h" #include "recmutex.h" -#include "death.h" /* Priorities for the demo application tasks. */ #define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )