From: rtel Date: Mon, 4 Aug 2014 07:53:20 +0000 (+0000) Subject: Common demo tasks: X-Git-Tag: V8.1.0~6 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a0a9466899eecea835bb76ea867bff7d87e38d98;p=freertos Common demo tasks: - Add additional tests to GenQTest.c to test the updated priority inheritance mechanism. - Slightly increase some delays in recmutex.c to prevent it reporting false errors in high load test cases. SAMA5D3 Xplained IAR demo: - Remove space being allocated for stacks that are not used. - Remove explicit enabling of interrupts in ISR handers as this is now done from the central ISR callback before the individual handers are invoked. - Reduce both the allocated heap size and the stack allocated to each task. - Enable I cache. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2286 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf index cae1fd6ce..f1dc6f99b 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf @@ -6,8 +6,8 @@ define symbol __ICFEDIT_region_RAM_start__ = 0x300000; define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_vectors__ = 0x100; -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_sysstack__ = 0x600; +define symbol __ICFEDIT_size_cstack__ = 0x400; +/*define symbol __ICFEDIT_size_sysstack__ = 0x600; Not used. */ define symbol __ICFEDIT_size_irqstack__ = 0x600; define symbol __ICFEDIT_size_heap__ = 0x0; /*-Exports-*/ @@ -15,7 +15,7 @@ export symbol __ICFEDIT_region_RAM_start__; export symbol __ICFEDIT_region_RAM_end__; export symbol __ICFEDIT_size_vectors__; export symbol __ICFEDIT_size_cstack__; -export symbol __ICFEDIT_size_sysstack__; +/*export symbol __ICFEDIT_size_sysstack__; Not used. */ export symbol __ICFEDIT_size_irqstack__; export symbol __ICFEDIT_size_heap__; /**** End of ICF editor section. ###ICF###*/ @@ -25,14 +25,14 @@ define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +/* define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; not used. */ define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -initialize by copy with packing=none { readwrite }; +initialize by copy with packing=none { readwrite }; do not initialize { readonly section .noinit }; place in VEC_region { section .vectors }; place in RAM_region { readonly }; place in RAM_region { section .cstartup }; -place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; +place in RAM_region { readwrite, block IRQ_STACK, /* block SYS_STACK not used, */ block CSTACK, block HEAP }; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c index 64660bfe4..c6a2fa6b9 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c @@ -108,6 +108,7 @@ extern WEAK void LowLevelInit( void ) /* Wait for the PCKRDY1 bit to be set in the PMC_SR register*/ while ((REG_PMC_SR & PMC_SR_PCKRDY1) == 0); #endif + /* select FIQ */ AIC->AIC_SSR = 0; AIC->AIC_SVR = (unsigned int) defaultFiqHandler; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/usb/common/core/USBDescriptors.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/usb/common/core/USBDescriptors.c index 110d3e04a..80cd4e0c0 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/usb/common/core/USBDescriptors.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/usb/common/core/USBDescriptors.c @@ -186,8 +186,8 @@ uint8_t *pc1, *pc2; usTemp = ( ( *pc2 ) << 8 ) | *pc1; return usTemp; -#warning The original code below crashes when build for A5 as endpoint can be misaligned. - //_RB_return endpoint->wMaxPacketSize; +#warning The above code replaces the line below to ensure aborts are not received due to unaligned accesses. Alternatively use the --no_unaligned_access compiler option. + //return endpoint->wMaxPacketSize; } /** diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c index 3cb73a4c6..f80639014 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/CDCCommandConsole.c @@ -124,7 +124,7 @@ extern void USBD_IrqHandler( void ); /* * The function that creates the CLI task. */ -void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); +void vUSBCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); /* * Send xDataLength bytes from pcData to the CDC port. @@ -178,7 +178,7 @@ static EventGroupHandle_t xCDCEventBits; /*-----------------------------------------------------------*/ -void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ) +void vUSBCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ) { /* Event group used to indicate that bytes are available in the Rx buffer or that bytes have finished sending. */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h index afa4c9380..0aada96ee 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h @@ -86,8 +86,8 @@ #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 1 #define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 160 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 45 * 1024 ) ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 150 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 42 * 1024 ) ) #define configMAX_TASK_NAME_LEN ( 10 ) #define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 @@ -156,7 +156,7 @@ used. */ and one on TCP/IP). This is done to prevent an output buffer being defined by each implementation - which would waste RAM. In this case, there is only one command interpreter running. */ - #define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 + #define configCOMMAND_INT_MAX_OUTPUT_SIZE 3000 /* Normal assert() semantics without relying on the provision of an assert.h header file. */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c index e90c521f7..9e1417ad5 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c @@ -88,8 +88,6 @@ static void System_Handler( void ); static void System_Handler( void ) { - __enable_interrupt(); - /* See the comments above the function prototype in this file. */ FreeRTOS_Tick_Handler(); } diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c index 8a11f5f5a..2e497aa88 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/IntQueueTimer.c @@ -71,15 +71,16 @@ * interrupts. As the interrupt is shared the nesting achieved is not as deep * as normal when this test is executed, but still worth while. * - * TC2 channel 0 provides a much higher frequency timer that tests the nesting of - * interrupts that execute above the maximum syscall interrupt priority. + * TC2 channel 0 provides a much higher frequency timer that tests the nesting + * of interrupts that don't use the FreeRTOS API. For convenience, the high + * frequency timer also keeps a count of the number of time it executes, and the + * count is used as the time base for the run time stats (which can be viewed + * through the CLI). * * All the timers can nest with the tick interrupt - creating a maximum * interrupt nesting depth of 3 (normally 4, if the first two timers used * separate interrupts). * - * For convenience, the high frequency timer is also used to provide the time - * base for the run time stats. */ /* Scheduler includes. */ @@ -96,7 +97,6 @@ ensure they don't remain synchronised. The frequency of the highest priority interrupt is 20 times faster so really hammers the interrupt entry and exit code. */ -#define tmrTIMERS_USED 3 #define tmrTIMER_0_FREQUENCY ( 2000UL ) #define tmrTIMER_1_FREQUENCY ( 2003UL ) #define tmrTIMER_2_FREQUENCY ( 20000UL ) @@ -115,7 +115,8 @@ of the lower frequency timers must still be above the tick interrupt priority. * #define tmrHIGHER_PRIORITY 5 /*-----------------------------------------------------------*/ -/* Handlers for the three timer channels. */ +/* Handlers for the two timer peripherals - two channels are used in the TC0 +timer. */ static void prvTC0_Handler( void ); static void prvTC1_Handler( void ); @@ -169,9 +170,6 @@ const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL; static void prvTC0_Handler( void ) { -#warning Why can interrupts only be enabled inside the C function? - __enable_interrupt(); - /* Read will clear the status bit. */ if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 ) { @@ -189,8 +187,6 @@ static void prvTC1_Handler( void ) { volatile uint32_t ulDummy; - __enable_interrupt(); - /* Dummy read to clear status bit. */ ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c index 1eff84509..b99b2ef5c 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/Full_Demo/main_full.c @@ -84,13 +84,12 @@ * In addition to the standard demo tasks, the following tasks and tests are * defined and/or created within this file: * - * FreeRTOS+CLI command console. The command console is access through the - * UART to USB connector on the _RB_. For - * reasons of robustness testing the UART driver is deliberately written to be - * inefficient and should not be used as a template for a production driver. - * Type "help" to see a list of registered commands. The FreeRTOS+CLI license - * is different to the FreeRTOS license, see http://www.FreeRTOS.org/cli for - * license and usage details. The default baud rate is 115200. + * "FreeRTOS+CLI command console" - The command console is access using the USB + * CDC driver provided by Atmel. It is accessed through the USB connector + * marked J6 SAMA5D3 Xplained board. Type "help" to see a list of registered + * commands. The FreeRTOS+CLI license is different to the FreeRTOS license, see + * http://www.FreeRTOS.org/cli for license and usage details. The default baud + * rate is 115200. * * "Reg test" tasks - These fill both the core and floating point registers with * known values, then check that each register maintains its expected value for @@ -143,12 +142,12 @@ #define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) #define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) #define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL ) #define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) #define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) #define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) -/* The priority used by the UART command console task. */ +/* The initial priority used by the UART command console task. */ #define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) /* The LED used by the check timer. */ @@ -209,7 +208,7 @@ extern void vRegisterSampleCLICommands( void ); /* * The task that manages the FreeRTOS+CLI input and output. */ -extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); +extern void vUSBCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); /* * A high priority task that does nothing other than execute at a pseudo random @@ -227,7 +226,7 @@ stops incrementing, then an error has been found. */ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; /*-----------------------------------------------------------*/ -#warning Check demo and source folders for _RB_ + void main_full( void ) { /* Start all the other standard demo/test tasks. They have not particular @@ -248,7 +247,7 @@ void main_full( void ) /* Start the tasks that implements the command console on the UART, as described above. */ - vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); + vUSBCommandConsoleStart( mainCDC_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); /* Register the standard CLI commands. */ vRegisterSampleCLICommands(); diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd index 604ac47a9..f1ac72d9c 100644 --- a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd @@ -49,7 +49,7 @@