From: Paul Fertser <fercerpav@gmail.com>
Date: Sat, 10 Jan 2015 10:19:26 +0000 (+0300)
Subject: cfg: add srst_nogate to the supported targets, remove from board configs
X-Git-Tag: v0.9.0-rc1~186
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a1bbf4b75bc68aeed3c72e37b302bb36757401c2;p=openocd

cfg: add srst_nogate to the supported targets, remove from board configs

It depends on the particular target whether it can work with SRST
asserted or not, so this belongs to the target config rather than the
board config.

Also, this allows for simple

openocd -f myboard.cfg -c "reset_config connect_assert_srst"

command to be used whenever a user feels a need to connect to an
unresponsive target.

Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2459
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---

diff --git a/tcl/board/st_nucleo_f0.cfg b/tcl/board/st_nucleo_f0.cfg
index 0cd75b60..e9fda19a 100644
--- a/tcl/board/st_nucleo_f0.cfg
+++ b/tcl/board/st_nucleo_f0.cfg
@@ -1,4 +1,4 @@
-# This is for all ST NUCLEO with any STM32F0. Know Boards at the moment:
+# This is for all ST NUCLEO with any STM32F0. Known boards at the moment:
 # STM32F030R8
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
 # NUCLEO-F072RB
@@ -12,5 +12,4 @@ transport select hla_swd
 
 source [find target/stm32f0x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_f103rb.cfg b/tcl/board/st_nucleo_f103rb.cfg
index d5024cc6..71a92f70 100644
--- a/tcl/board/st_nucleo_f103rb.cfg
+++ b/tcl/board/st_nucleo_f103rb.cfg
@@ -7,5 +7,4 @@ transport select hla_swd
 
 source [find target/stm32f1x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_f334r8.cfg b/tcl/board/st_nucleo_f334r8.cfg
index e0dfb689..9dffdcbb 100644
--- a/tcl/board/st_nucleo_f334r8.cfg
+++ b/tcl/board/st_nucleo_f334r8.cfg
@@ -7,5 +7,4 @@ transport select hla_swd
 
 source [find target/stm32f3x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_f4.cfg b/tcl/board/st_nucleo_f4.cfg
index 84b4b53f..b5a78c1c 100644
--- a/tcl/board/st_nucleo_f4.cfg
+++ b/tcl/board/st_nucleo_f4.cfg
@@ -1,4 +1,4 @@
-# This is for all ST NUCLEO with any STM32F. Know Boards at the moment:
+# This is for all ST NUCLEO with any STM32F4. Known boards at the moment:
 # STM32F401RET6
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000
 # STM32F411RET6
@@ -10,5 +10,4 @@ transport select hla_swd
 
 source [find target/stm32f4x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm320518_eval_stlink.cfg b/tcl/board/stm320518_eval_stlink.cfg
index 0e2ac598..ce074cbf 100644
--- a/tcl/board/stm320518_eval_stlink.cfg
+++ b/tcl/board/stm320518_eval_stlink.cfg
@@ -16,5 +16,4 @@ set CHIPNAME STM32F051R8T6
 
 source [find target/stm32f0x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm3220g_eval_stlink.cfg b/tcl/board/stm3220g_eval_stlink.cfg
index 55856cf0..43a4df98 100644
--- a/tcl/board/stm3220g_eval_stlink.cfg
+++ b/tcl/board/stm3220g_eval_stlink.cfg
@@ -16,5 +16,4 @@ set CHIPNAME STM32F207IGH6
 
 source [find target/stm32f2x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm3241g_eval_stlink.cfg b/tcl/board/stm3241g_eval_stlink.cfg
index 72b2d32c..9c7ad5d9 100644
--- a/tcl/board/stm3241g_eval_stlink.cfg
+++ b/tcl/board/stm3241g_eval_stlink.cfg
@@ -16,5 +16,4 @@ set CHIPNAME STM32F417IGH6
 
 source [find target/stm32f4x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32429i_eval_stlink.cfg b/tcl/board/stm32429i_eval_stlink.cfg
index 117409aa..2b51cea6 100644
--- a/tcl/board/stm32429i_eval_stlink.cfg
+++ b/tcl/board/stm32429i_eval_stlink.cfg
@@ -16,5 +16,4 @@ set CHIPNAME STM32F429NIH6
 
 source [find target/stm32f4x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32439i_eval_stlink.cfg b/tcl/board/stm32439i_eval_stlink.cfg
index efc47f7d..5995fb1d 100644
--- a/tcl/board/stm32439i_eval_stlink.cfg
+++ b/tcl/board/stm32439i_eval_stlink.cfg
@@ -16,5 +16,4 @@ set CHIPNAME STM32F439NIH6
 
 source [find target/stm32f4x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32f0discovery.cfg b/tcl/board/stm32f0discovery.cfg
index 66086cdd..bae9a69b 100644
--- a/tcl/board/stm32f0discovery.cfg
+++ b/tcl/board/stm32f0discovery.cfg
@@ -8,5 +8,4 @@ transport select hla_swd
 set WORKAREASIZE 0x2000
 source [find target/stm32f0x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32f3discovery.cfg b/tcl/board/stm32f3discovery.cfg
index 24a9261f..5a17b4c9 100644
--- a/tcl/board/stm32f3discovery.cfg
+++ b/tcl/board/stm32f3discovery.cfg
@@ -7,5 +7,4 @@ transport select hla_swd
 
 source [find target/stm32f3x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32f429discovery.cfg b/tcl/board/stm32f429discovery.cfg
index 220298ec..eddaa9f6 100644
--- a/tcl/board/stm32f429discovery.cfg
+++ b/tcl/board/stm32f429discovery.cfg
@@ -9,5 +9,4 @@ transport select hla_swd
 
 source [find target/stm32f4x.cfg]
 
-# use hardware reset, connect under reset supported
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32f4discovery.cfg b/tcl/board/stm32f4discovery.cfg
index 990ee328..f5b52920 100644
--- a/tcl/board/stm32f4discovery.cfg
+++ b/tcl/board/stm32f4discovery.cfg
@@ -7,5 +7,4 @@ transport select hla_swd
 
 source [find target/stm32f4x.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32l0discovery.cfg b/tcl/board/stm32l0discovery.cfg
index 57b8a600..a0350622 100644
--- a/tcl/board/stm32l0discovery.cfg
+++ b/tcl/board/stm32l0discovery.cfg
@@ -8,5 +8,4 @@ transport select hla_swd
 set WORKAREASIZE 0x2000
 source [find target/stm32l0.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32ldiscovery.cfg b/tcl/board/stm32ldiscovery.cfg
index b31a663a..8678d290 100644
--- a/tcl/board/stm32ldiscovery.cfg
+++ b/tcl/board/stm32ldiscovery.cfg
@@ -8,5 +8,4 @@ transport select hla_swd
 set WORKAREASIZE 0x4000
 source [find target/stm32l1.cfg]
 
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
+reset_config srst_only
diff --git a/tcl/board/stm32vldiscovery.cfg b/tcl/board/stm32vldiscovery.cfg
index 19b42aef..970b5101 100644
--- a/tcl/board/stm32vldiscovery.cfg
+++ b/tcl/board/stm32vldiscovery.cfg
@@ -8,3 +8,4 @@ transport select hla_swd
 set WORKAREASIZE 0x2000
 source [find target/stm32f1x.cfg]
 
+reset_config srst_only
diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg
index a139dcdb..b0f69940 100644
--- a/tcl/target/k40.cfg
+++ b/tcl/target/k40.cfg
@@ -31,8 +31,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 
 target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
-$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
-$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
+reset_config srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg
index a368e0b2..0e7adc4a 100644
--- a/tcl/target/k60.cfg
+++ b/tcl/target/k60.cfg
@@ -31,8 +31,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 
 target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
 
-$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
-$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
+reset_config srst_nogate
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
diff --git a/tcl/target/kl25.cfg b/tcl/target/kl25.cfg
index 7b14ecc8..b75e0a56 100644
--- a/tcl/target/kl25.cfg
+++ b/tcl/target/kl25.cfg
@@ -55,6 +55,8 @@ flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
 # specifies up to 1MHz for VLPR mode.
 adapter_khz 1000
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg
index 30ea7171..ff6d7f14 100644
--- a/tcl/target/stm32f0x.cfg
+++ b/tcl/target/stm32f0x.cfg
@@ -46,6 +46,8 @@ adapter_khz 1000
 
 adapter_nsrst_delay 100
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 46d70b1e..6a62992d 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -86,6 +86,8 @@ if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
+reset_config srst_nogate
+
 if {![using_hla]} {
     # if srst is not fitted use SYSRESETREQ to
     # perform a soft reset
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 62e35a4c..0ac73a51 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -70,6 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 4ad4bd57..9547d843 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -70,6 +70,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index faa6a7e5..fd5cab6a 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -82,6 +82,8 @@ if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index 45b3c364..fd8f951b 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -46,6 +46,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index ccbec09d..8591830c 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -75,6 +75,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index 864917f4..1a191354 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -63,6 +63,8 @@ set _FLASHNAME $_CHIPNAME.flash
 # 64k (0x10000) of flash
 flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    cortex_m reset_config sysresetreq
 }