From: Peng Fan <Peng.Fan@freescale.com>
Date: Mon, 20 Jul 2015 11:28:28 +0000 (+0800)
Subject: imx: mx6ul select SYS_L2CACHE_OFF
X-Git-Tag: v2015.10-rc1~2^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a2c74aaf51171fbdfab725c4dd05b58b1ce45070;p=u-boot

imx: mx6ul select SYS_L2CACHE_OFF

i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 68b46c10d4..dce7ffc022 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -25,6 +25,10 @@ config MX6SL
 config MX6SX
 	bool
 
+config MX6UL
+	select SYS_L2CACHE_OFF
+	bool
+
 choice
 	prompt "MX6 board select"
 	optional