From: rtel Date: Thu, 7 Apr 2016 10:57:36 +0000 (+0000) Subject: Rename CORTEX_M4F_CEC1302_Keil to CORTEX_M4F_CEC1302_Keil_GCC as it now contains... X-Git-Tag: V9.0.0~23 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a466e505e0411df37b0d1a5533df645661cf6650;p=freertos Rename CORTEX_M4F_CEC1302_Keil to CORTEX_M4F_CEC1302_Keil_GCC as it now contains both GCC and Keil projects. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2440 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/cmsis_armcc.h deleted file mode 100644 index f2bb66a09..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/cmsis_gcc.h deleted file mode 100644 index a144be795..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/cmsis_gcc.h +++ /dev/null @@ -1,1366 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ - (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ - (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */ - - -#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ - (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ - (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ - (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cm4.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cm4.h deleted file mode 100644 index 01cb73bf3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmFunc.h deleted file mode 100644 index ca319a55c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmInstr.h deleted file mode 100644 index a0a506458..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmSimd.h deleted file mode 100644 index 4d76bf901..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/CMSIS/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/FreeRTOSConfig.h deleted file mode 100644 index 625a39c20..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/FreeRTOSConfig.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - - -/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky demo low power -example, or 1 to run the more comprehensive test and demo application. See -the comments at the top of main.c for more information. */ -#define configCREATE_LOW_POWER_DEMO 1 - -/* Some configuration is dependent on the demo being built. */ -#if( configCREATE_LOW_POWER_DEMO == 1 ) - - /* The low power demo uses a slow low power clock, so the SysTick clock, - which is used by default by Cortex-M ports, is not used to generate the - tick interrupt. */ - #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1 - - /* The slow clock used to generate the tick interrupt in the low power demo - runs at 32768Hz. Ensure the clock is a multiple of the tick rate. */ - #define configTICK_RATE_HZ ( 128 ) - - /* The low power demo uses the tickless idle feature. */ - #define configUSE_TICKLESS_IDLE 1 - -#else - - /* Some of the standard demo test tasks assume a tick rate of 1KHz, even - though that is faster than would normally be warranted by a real - application. */ - #define configTICK_RATE_HZ ( 1000 ) - - /* The full demo always has tasks to run so the tick will never be turned - off. The blinky demo will use the default tickless idle implementation to - turn the tick off. */ - #define configUSE_TICKLESS_IDLE 0 - -#endif - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configUSE_QUEUE_SETS 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ 48000000 -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 28 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 0 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configSUPPORT_STATIC_ALLOCATION 1 - -/* Run time stats gathering definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() -#define portGET_RUN_TIME_COUNTER_VALUE() - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 2 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTimerPendFunctionCall 1 - -/* Cortex-M specific definitions. */ -#ifdef __NVIC_PRIO_BITS - /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ - #define configPRIO_BITS __NVIC_PRIO_BITS -#else - #define configPRIO_BITS 3 /* 7 priority levels */ -#endif - -/* The lowest interrupt priority that can be used in a call to a "set priority" -function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7 - -/* The highest interrupt priority that can be used by any interrupt service -routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL -INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER -PRIORITY THAN THIS! (higher priorities are lower numeric values. */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 - -/* Interrupt priorities used by the kernel port layer itself. These are generic -to all Cortex-M ports, and do not rely on any particular library functions. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! -See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names. */ -#define xPortPendSVHandler PendSV_Handler -#define vPortSVCHandler SVC_Handler -#define xPortSysTickHandler SysTick_Handler - -/* Normal assert() semantics without relying on the provision of an assert.h -header file. */ -#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); } - -/* LED not used at present, so just increment a variable to keep a count of the -number of times the LED would otherwise have been toggled. */ -#define configTOGGLE_LED() ulLED++ - - -#ifdef __cplusplus -} -#endif -#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/JLinkLog.txt b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/JLinkLog.txt deleted file mode 100644 index d6b5ccdce..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/JLinkLog.txt +++ /dev/null @@ -1,492 +0,0 @@ - -T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total) -T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total) -T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total) -T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total) -T220C 000:298 JLINK_OpenEx(...) -Firmware: J-Link V9 compiled Oct 9 2015 20:34:47 -Hardware: V9.10 -S/N: 59101789 -Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total) -T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total) -T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total) -T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total) -T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) -T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total) -T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) -T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total) -T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total) -T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total) -T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) - -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0) -ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total) -T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total) -T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total) -T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total) -T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total) -T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total) -T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total) -T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total) -T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total) -T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total) -T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total) -T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total) -T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total) -T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total) -T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total) -T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total) -T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total) -T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total) -T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total) -T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total) -T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total) -T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total) -T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total) -T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) - -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) - -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total) -T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total) -T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total) -T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total) -T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total) -T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total) -T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total) -T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total) -T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total) -T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total) -T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total) -T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total) -T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total) -T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total) -T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total) -T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total) -T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total) -T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total) -T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total) -T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total) -T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total) -T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total) -T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total) -T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total) -T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total) -T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total) -T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total) -T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total) -T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total) -T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total) -T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) -T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total) -T1854 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JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total) -T1854 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total) -T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total) -T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total) -T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total) -T220C 027:508 (0005ms, 2544ms total) -T220C 027:508 Closed (0005ms, 2544ms total) diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/JLinkSettings.ini deleted file mode 100644 index 706cf39a9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/JLinkSettings.ini +++ /dev/null @@ -1,35 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 1 -Device="Unspecified" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RTOSDemo.uvguix.barryri b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RTOSDemo.uvguix.barryri deleted file mode 100644 index 111b4c0a1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RTOSDemo.uvguix.barryri +++ /dev/null @@ -1,2601 +0,0 @@ - - - - -5.1 - -
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- - - - 0 - 1920 - 1200 - - - - - - 1 - 0 - - 100 - 0 - - ..\main.c - 0 - 66 - 141 - 1 - - 0 - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RTOSDemo.uvoptx deleted file mode 100644 index e4186479a..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RTOSDemo.uvoptx +++ /dev/null @@ -1,610 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c;*.S - - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - RTOSDemo_GCC - 0x3 - ARM-GNU - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 120 - 65 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 7 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - - - - - - - - - - init_app.ini - BIN\UL2CM3.DLL - - - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - (105=-1,-1,-1,-1,0) - - - 0 - UL2CM3 - -UV1115SAE -O2983 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0100000 -FL018000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) - - - - - 0 - 0 - 0 - 0 -
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### uVision Project, (C) Keil Software
- - - - RTOSDemo_GCC - 0x3 - ARM-GNU - 5060061::V5.06 update 1 (build 61)::ARMCC - - - ARMCM4_FP - ARM - ARM.CMSIS.4.5.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) - 0 - $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h - - - - - - - - - - $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - RTOSDemo - 1 - 0 - 0 - 1 - 0 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - "Cortex-M4" - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - - - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 2 - 1 - - -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections -O0 -g - - - ..;..\..\..\Source\include;..\..\..\Source\portable\GCC\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full - - - - 0 - 1 - - - - - - - - - 1 - 0 - 1 - 0 - 1 - - - - - - -Xlinker --gc-sections - .\sections.ld - - - - - - System - - - system.c - 1 - .\system.c - - - startup_ARMCM4.S - 2 - .\startup_ARMCM4.S - - - - - main_and_config - - - main.c - 1 - ..\main.c - - - FreeRTOSConfig.h - 5 - ..\FreeRTOSConfig.h - - - - - FreeRTOS_Source - - - event_groups.c - 1 - ..\..\..\Source\event_groups.c - - - list.c - 1 - ..\..\..\Source\list.c - - - queue.c - 1 - ..\..\..\Source\queue.c - - - tasks.c - 1 - ..\..\..\Source\tasks.c - - - timers.c - 1 - ..\..\..\Source\timers.c - - - heap_4.c - 1 - ..\..\..\Source\portable\MemMang\heap_4.c - - - port.c - 1 - ..\..\..\Source\portable\GCC\ARM_CM4F\port.c - - - - - main_low_power - - - main_low_power.c - 1 - ..\main_low_power\main_low_power.c - - - low_power_tick_config.c - 1 - ..\main_low_power\low_power_tick_config.c - - - - - main_full - - - main_full.c - 1 - ..\main_full\main_full.c - - - RegTest.c - 1 - .\RegTest.c - - - flop.c - 1 - ..\..\Common\Minimal\flop.c - - - EventGroupsDemo.c - 1 - ..\..\Common\Minimal\EventGroupsDemo.c - - - TaskNotify.c - 1 - ..\..\Common\Minimal\TaskNotify.c - - - blocktim.c - 1 - ..\..\Common\Minimal\blocktim.c - - - dynamic.c - 1 - ..\..\Common\Minimal\dynamic.c - - - GenQTest.c - 1 - ..\..\Common\Minimal\GenQTest.c - - - TimerDemo.c - 1 - ..\..\Common\Minimal\TimerDemo.c - - - IntQueue.c - 1 - ..\..\Common\Minimal\IntQueue.c - - - IntQueueTimer.c - 1 - ..\main_full\IntQueueTimer.c - - - countsem.c - 1 - ..\..\Common\Minimal\countsem.c - - - semtest.c - 1 - ..\..\Common\Minimal\semtest.c - - - death.c - 1 - ..\..\Common\Minimal\death.c - - - - - peripheral_library - - - btimer_api.c - 1 - ..\peripheral_library\basic_timer\btimer_api.c - - - btimer_perphl.c - 1 - ..\peripheral_library\basic_timer\btimer_perphl.c - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RegTest.c deleted file mode 100644 index dd82dd892..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/RegTest.c +++ /dev/null @@ -1,457 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * "Reg test" tasks - These fill the registers with known values, then check - * that each register maintains its expected value for the lifetime of the - * task. Each task uses a different set of values. The reg test tasks execute - * with a very low priority, so get preempted very frequently. A register - * containing an unexpected value is indicative of an error in the context - * switching mechanism. - */ - -void vRegTest1Implementation( void ) __attribute__ ((naked)); -void vRegTest2Implementation( void ) __attribute__ ((naked)); - -void vRegTest1Implementation( void ) -{ - __asm volatile - ( - ".extern ulRegTest1LoopCounter \n" - "/* Fill the core registers with known values. */ \n" - "mov r0, #100 \n" - "mov r1, #101 \n" - "mov r2, #102 \n" - "mov r3, #103 \n" - "mov r4, #104 \n" - "mov r5, #105 \n" - "mov r6, #106 \n" - "mov r7, #107 \n" - "mov r8, #108 \n" - "mov r9, #109 \n" - "mov r10, #110 \n" - "mov r11, #111 \n" - "mov r12, #112 \n" - - "/* Fill the VFP registers with known values. */ \n" - "vmov d0, r0, r1 \n" - "vmov d1, r2, r3 \n" - "vmov d2, r4, r5 \n" - "vmov d3, r6, r7 \n" - "vmov d4, r8, r9 \n" - "vmov d5, r10, r11 \n" - "vmov d6, r0, r1 \n" - "vmov d7, r2, r3 \n" - "vmov d8, r4, r5 \n" - "vmov d9, r6, r7 \n" - "vmov d10, r8, r9 \n" - "vmov d11, r10, r11 \n" - "vmov d12, r0, r1 \n" - "vmov d13, r2, r3 \n" - "vmov d14, r4, r5 \n" - "vmov d15, r6, r7 \n" - - "reg1_loop: \n" - "/* Check all the VFP registers still contain the values set above. \n" - "First save registers that are clobbered by the test. */ \n" - "push { r0-r1 } \n" - - "vmov r0, r1, d0 \n" - "cmp r0, #100 \n" - "bne reg1_error_loopf \n" - "cmp r1, #101 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d1 \n" - "cmp r0, #102 \n" - "bne reg1_error_loopf \n" - "cmp r1, #103 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d2 \n" - "cmp r0, #104 \n" - "bne reg1_error_loopf \n" - "cmp r1, #105 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d3 \n" - "cmp r0, #106 \n" - "bne reg1_error_loopf \n" - "cmp r1, #107 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d4 \n" - "cmp r0, #108 \n" - "bne reg1_error_loopf \n" - "cmp r1, #109 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d5 \n" - "cmp r0, #110 \n" - "bne reg1_error_loopf \n" - "cmp r1, #111 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d6 \n" - "cmp r0, #100 \n" - "bne reg1_error_loopf \n" - "cmp r1, #101 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d7 \n" - "cmp r0, #102 \n" - "bne reg1_error_loopf \n" - "cmp r1, #103 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d8 \n" - "cmp r0, #104 \n" - "bne reg1_error_loopf \n" - "cmp r1, #105 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d9 \n" - "cmp r0, #106 \n" - "bne reg1_error_loopf \n" - "cmp r1, #107 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d10 \n" - "cmp r0, #108 \n" - "bne reg1_error_loopf \n" - "cmp r1, #109 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d11 \n" - "cmp r0, #110 \n" - "bne reg1_error_loopf \n" - "cmp r1, #111 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d12 \n" - "cmp r0, #100 \n" - "bne reg1_error_loopf \n" - "cmp r1, #101 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d13 \n" - "cmp r0, #102 \n" - "bne reg1_error_loopf \n" - "cmp r1, #103 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d14 \n" - "cmp r0, #104 \n" - "bne reg1_error_loopf \n" - "cmp r1, #105 \n" - "bne reg1_error_loopf \n" - "vmov r0, r1, d15 \n" - "cmp r0, #106 \n" - "bne reg1_error_loopf \n" - "cmp r1, #107 \n" - "bne reg1_error_loopf \n" - - "/* Restore the registers that were clobbered by the test. */ \n" - "pop {r0-r1} \n" - - "/* VFP register test passed. Jump to the core register test. */ \n" - "b reg1_loopf_pass \n" - - "reg1_error_loopf: \n" - "/* If this line is hit then a VFP register value was found to be incorrect. */ \n" - "b reg1_error_loopf \n" - - "reg1_loopf_pass: \n" - - "cmp r0, #100 \n" - "bne reg1_error_loop \n" - "cmp r1, #101 \n" - "bne reg1_error_loop \n" - "cmp r2, #102 \n" - "bne reg1_error_loop \n" - "cmp r3, #103 \n" - "bne reg1_error_loop \n" - "cmp r4, #104 \n" - "bne reg1_error_loop \n" - "cmp r5, #105 \n" - "bne reg1_error_loop \n" - "cmp r6, #106 \n" - "bne reg1_error_loop \n" - "cmp r7, #107 \n" - "bne reg1_error_loop \n" - "cmp r8, #108 \n" - "bne reg1_error_loop \n" - "cmp r9, #109 \n" - "bne reg1_error_loop \n" - "cmp r10, #110 \n" - "bne reg1_error_loop \n" - "cmp r11, #111 \n" - "bne reg1_error_loop \n" - "cmp r12, #112 \n" - "bne reg1_error_loop \n" - - "/* Everything passed, increment the loop counter. */ \n" - "push { r0-r1 } \n" - "ldr r0, =ulRegTest1LoopCounter \n" - "ldr r1, [r0] \n" - "adds r1, r1, #1 \n" - "str r1, [r0] \n" - "pop { r0-r1 } \n" - - "/* Start again. */ \n" - "b reg1_loop \n" - - "reg1_error_loop: \n" - "/* If this line is hit then there was an error in a core register value. \n" - "The loop ensures the loop counter stops incrementing. */ \n" - "b reg1_error_loop \n" - "nop " - ); /* __asm volatile. */ -} -/*-----------------------------------------------------------*/ - -void vRegTest2Implementation( void ) -{ - __asm volatile - ( - ".extern ulRegTest2LoopCounter \n" - "/* Set all the core registers to known values. */ \n" - "mov r0, #-1 \n" - "mov r1, #1 \n" - "mov r2, #2 \n" - "mov r3, #3 \n" - "mov r4, #4 \n" - "mov r5, #5 \n" - "mov r6, #6 \n" - "mov r7, #7 \n" - "mov r8, #8 \n" - "mov r9, #9 \n" - "mov r10, #10 \n" - "mov r11, #11 \n" - "mov r12, #12 \n" - - "/* Set all the VFP to known values. */ \n" - "vmov d0, r0, r1 \n" - "vmov d1, r2, r3 \n" - "vmov d2, r4, r5 \n" - "vmov d3, r6, r7 \n" - "vmov d4, r8, r9 \n" - "vmov d5, r10, r11 \n" - "vmov d6, r0, r1 \n" - "vmov d7, r2, r3 \n" - "vmov d8, r4, r5 \n" - "vmov d9, r6, r7 \n" - "vmov d10, r8, r9 \n" - "vmov d11, r10, r11 \n" - "vmov d12, r0, r1 \n" - "vmov d13, r2, r3 \n" - "vmov d14, r4, r5 \n" - "vmov d15, r6, r7 \n" - - "reg2_loop: \n" - - "/* Check all the VFP registers still contain the values set above. \n" - "First save registers that are clobbered by the test. */ \n" - "push { r0-r1 } \n" - - "vmov r0, r1, d0 \n" - "cmp r0, #-1 \n" - "bne reg2_error_loopf \n" - "cmp r1, #1 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d1 \n" - "cmp r0, #2 \n" - "bne reg2_error_loopf \n" - "cmp r1, #3 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d2 \n" - "cmp r0, #4 \n" - "bne reg2_error_loopf \n" - "cmp r1, #5 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d3 \n" - "cmp r0, #6 \n" - "bne reg2_error_loopf \n" - "cmp r1, #7 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d4 \n" - "cmp r0, #8 \n" - "bne reg2_error_loopf \n" - "cmp r1, #9 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d5 \n" - "cmp r0, #10 \n" - "bne reg2_error_loopf \n" - "cmp r1, #11 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d6 \n" - "cmp r0, #-1 \n" - "bne reg2_error_loopf \n" - "cmp r1, #1 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d7 \n" - "cmp r0, #2 \n" - "bne reg2_error_loopf \n" - "cmp r1, #3 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d8 \n" - "cmp r0, #4 \n" - "bne reg2_error_loopf \n" - "cmp r1, #5 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d9 \n" - "cmp r0, #6 \n" - "bne reg2_error_loopf \n" - "cmp r1, #7 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d10 \n" - "cmp r0, #8 \n" - "bne reg2_error_loopf \n" - "cmp r1, #9 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d11 \n" - "cmp r0, #10 \n" - "bne reg2_error_loopf \n" - "cmp r1, #11 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d12 \n" - "cmp r0, #-1 \n" - "bne reg2_error_loopf \n" - "cmp r1, #1 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d13 \n" - "cmp r0, #2 \n" - "bne reg2_error_loopf \n" - "cmp r1, #3 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d14 \n" - "cmp r0, #4 \n" - "bne reg2_error_loopf \n" - "cmp r1, #5 \n" - "bne reg2_error_loopf \n" - "vmov r0, r1, d15 \n" - "cmp r0, #6 \n" - "bne reg2_error_loopf \n" - "cmp r1, #7 \n" - "bne reg2_error_loopf \n" - - "/* Restore the registers that were clobbered by the test. */ \n" - "pop {r0-r1} \n" - - "/* VFP register test passed. Jump to the core register test. */ \n" - "b reg2_loopf_pass \n" - - "reg2_error_loopf: \n" - "/* If this line is hit then a VFP register value was found to be \n" - "incorrect. */ \n" - "b reg2_error_loopf \n" - - "reg2_loopf_pass: \n" - - "cmp r0, #-1 \n" - "bne reg2_error_loop \n" - "cmp r1, #1 \n" - "bne reg2_error_loop \n" - "cmp r2, #2 \n" - "bne reg2_error_loop \n" - "cmp r3, #3 \n" - "bne reg2_error_loop \n" - "cmp r4, #4 \n" - "bne reg2_error_loop \n" - "cmp r5, #5 \n" - "bne reg2_error_loop \n" - "cmp r6, #6 \n" - "bne reg2_error_loop \n" - "cmp r7, #7 \n" - "bne reg2_error_loop \n" - "cmp r8, #8 \n" - "bne reg2_error_loop \n" - "cmp r9, #9 \n" - "bne reg2_error_loop \n" - "cmp r10, #10 \n" - "bne reg2_error_loop \n" - "cmp r11, #11 \n" - "bne reg2_error_loop \n" - "cmp r12, #12 \n" - "bne reg2_error_loop \n" - - "/* Increment the loop counter to indicate this test is still functioning \n" - "correctly. */ \n" - "push { r0-r1 } \n" - "ldr r0, =ulRegTest2LoopCounter \n" - "ldr r1, [r0] \n" - "adds r1, r1, #1 \n" - "str r1, [r0] \n" - - "/* Yield to increase test coverage. */ \n" - "movs r0, #0x01 \n" - "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n" - "lsl r0, r0, #28 /* Shift to PendSV bit */ \n" - "str r0, [r1] \n" - "dsb \n" - - "pop { r0-r1 } \n" - - "/* Start again. */ \n" - "b reg2_loop \n" - - "reg2_error_loop: \n" - "/* If this line is hit then there was an error in a core register value. \n" - "This loop ensures the loop counter variable stops incrementing. */ \n" - "b reg2_error_loop \n" - ); /* __asm volatile */ -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/init_app.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/init_app.ini deleted file mode 100644 index a98d32f13..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/init_app.ini +++ /dev/null @@ -1,8 +0,0 @@ -//Initialization file for the application code -RESET -T -T -T -//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine -eval PC = Reset_Handler; -T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/mem.ld b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/mem.ld deleted file mode 100644 index f9b07a691..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/mem.ld +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Memory Spaces Definitions. - * - * Need modifying for a specific board. - * FLASH.ORIGIN: starting address of flash - * FLASH.LENGTH: length of flash - * RAM.ORIGIN: starting address of RAM bank 0 - * RAM.LENGTH: length of RAM bank 0 - * - * The values below can be addressed in further linker scripts - * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'. - */ - -MEMORY -{ - ROM (rx) : ORIGIN = 0x100000, LENGTH = 0x18000 - RAM (rw) : ORIGIN = 0x118000, LENGTH = 0x8000 -} - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/sections.ld b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/sections.ld deleted file mode 100644 index 95e1da65d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/sections.ld +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Default linker script for GCC MEC1322 - * Based upon linker scripts from GNU ARM Eclipse plug-in - */ - -INCLUDE mem.ld - -/* - * The '__stack' definition is required by crt0, do not remove it. - */ -/* Place top of stack immediate before ROM Log - *__stack = ORIGIN(RAM) + LENGTH(RAM); - */ -__stack = ORIGIN(RAM) + LENGTH(RAM); - -_estack = __stack; - -/* - * Default stack sizes. - * These are used by the startup in order to allocate stacks - * for the different modes. - */ - -__Main_Stack_Size = 2048 ; - -PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ; - -__Main_Stack_Limit = __stack - __Main_Stack_Size ; - -/*"PROVIDE" allows to easily override these values from an object file or the command line. */ -PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ; - -/* - * There will be a link error if there is not this amount of - * RAM free at the end. - */ -_Minimum_Stack_Size = 256 ; - -/* - * Default heap definitions. - * The heap start immediately after the last statically allocated - * .sbss/.noinit section, and extends up to the main stack limit. - */ -PROVIDE ( _Heap_Begin = _end_noinit ) ; -PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ; - -/* - * The entry point is informative, for debuggers and simulators, - * since the Cortex-M vector points to it anyway. - */ -ENTRY(_start) - -/* Sections Definitions */ - -SECTIONS -{ - /* - * For Cortex-M devices, the beginning of the startup code is stored in - * the .isr_vector section, which goes to ROM - */ - - .isr_vector : - { - . = ALIGN(4); - _isr_vector = .; - KEEP(*(.isr_vector)) - . = ALIGN(4); - } >ROM - - - .text : - { - . = ALIGN(4); - - /* - * This section is here for convenience, to store the - * startup code at the beginning of the flash area, hoping that - * this will increase the readability of the listing. - */ - KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */ - - . = ALIGN(4); - - /* - * These are the old initialisation sections, intended to contain - * naked code, with the prologue/epilogue added by crti.o/crtn.o - * when linking with startup files. The standalone startup code - * currently does not run these, better use the init arrays below. - */ - KEEP(*(.init)) - KEEP(*(.fini)) - - . = ALIGN(4); - - /* - * The preinit code, i.e. an array of pointers to initialisation - * functions to be performed before constructors. - */ - PROVIDE_HIDDEN (__preinit_array_start = .); - - /* - * Used to run the SystemInit() before anything else. - */ - KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*)) - - /* - * Used for other platform inits. - */ - KEEP(*(.preinit_array_platform .preinit_array_platform.*)) - - /* - * The application inits. If you need to enforce some order in - * execution, create new sections, as before. - */ - KEEP(*(.preinit_array .preinit_array.*)) - - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - - /* - * The init code, i.e. an array of pointers to static constructors. - */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - - /* - * The fini code, i.e. an array of pointers to static destructors. - */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - - . = ALIGN(4); - - *(.text*) /* all remaining code */ - - *(vtable) /* C++ virtual tables */ - - } >ROM - - .rodata : - { - *(.rodata*) /* read-only data (constants) */ - } >ROM - - .glue : - { - KEEP(*(.eh_frame*)) - - /* - * Stub sections generated by the linker, to glue together - * ARM and Thumb code. .glue_7 is used for ARM code calling - * Thumb code, and .glue_7t is used for Thumb code calling - * ARM code. Apparently always generated by the linker, for some - * architectures, so better leave them here. - */ - *(.glue_7) - *(.glue_7t) - } >ROM - - /* ARM magic sections */ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ROM - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ROM - __exidx_end = .; - - . = ALIGN(4); - _etext = .; - __etext = .; - - /* - * This address is used by the startup code to - * initialise the .data section. - */ - _sidata = _etext; - - /* MEMORY_ARRAY */ - /* - .ROarraySection : - { - *(.ROarraySection .ROarraySection.*) - } >MEMORY_ARRAY - */ - /* - * The initialised data section. - * The program executes knowing that the data is in the RAM - * but the loader puts the initial values in the ROM (inidata). - * It is one task of the startup to copy the initial values from - * ROM to RAM. - */ - .data : AT ( _sidata ) - { - . = ALIGN(4); - - /* This is used by the startup code to initialise the .data section */ - _sdata = . ; /* STM specific definition */ - __data_start__ = . ; - *(.data_begin .data_begin.*) - - *(.data .data.*) - - *(.data_end .data_end.*) - . = ALIGN(4); - - /* This is used by the startup code to initialise the .data section */ - _edata = . ; /* STM specific definition */ - __data_end__ = . ; - - } >RAM - - - /* - * The uninitialised data section. NOLOAD is used to avoid - * the "section `.bss' type changed to PROGBITS" warning - */ - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; /* standard newlib definition */ - _sbss = .; /* STM specific definition */ - *(.bss_begin .bss_begin.*) - - *(.bss .bss.*) - *(COMMON) - - *(.bss_end .bss_end.*) - . = ALIGN(4); - __bss_end__ = .; /* standard newlib definition */ - _ebss = . ; /* STM specific definition */ - } >RAM - - .noinit (NOLOAD) : - { - . = ALIGN(4); - _noinit = .; - - *(.noinit .noinit.*) - - . = ALIGN(4) ; - _end_noinit = .; - } > RAM - - /* Mandatory to be word aligned, _sbrk assumes this */ - PROVIDE ( end = _end_noinit ); /* was _ebss */ - PROVIDE ( _end = _end_noinit ); - PROVIDE ( __end = _end_noinit ); - PROVIDE ( __end__ = _end_noinit ); - PROVIDE ( ROM_DATA_START = __data_start__ ); - - /* - * Used for validation only, do not allocate anything here! - * - * This is just to check that there is enough RAM left for the Main - * stack. It should generate an error if it's full. - */ - ._check_stack : - { - . = ALIGN(4); - - . = . + _Minimum_Stack_Size ; - - . = ALIGN(4); - } >RAM - - ._check_rom_log : - { - . = ALIGN(4); - -/* . = . + __ROM_Log_Size ; */ - - . = ALIGN(4); - } >RAM - -/* - .bss_CCMRAM : ALIGN(4) - { - *(.bss.CCMRAM .bss.CCMRAM.*) - } > CCMRAM -*/ - /* - * The ROM Bank1. - * The C or assembly source must explicitly place the code - * or data there using the "section" attribute. - */ - - - /* remaining code */ - /* read-only data (constants) */ -/* - .b1text : - { - *(.b1text) - *(.b1rodata) - *(.b1rodata.*) - } >ROMB1 -*/ - /* - * The EXTMEM. - * The C or assembly source must explicitly place the code or data there - * using the "section" attribute. - */ - - /* EXTMEM Bank0 */ -/* - .eb0text : - { - *(.eb0text) - *(.eb0rodata) - *(.eb0rodata.*) - } >EXTMEMB0 -*/ - /* EXTMEM Bank1 */ -/* - .eb1text : - { - *(.eb1text) - *(.eb1rodata) - *(.eb1rodata.*) - } >EXTMEMB1 -*/ - /* EXTMEM Bank2 */ -/* - .eb2text : - { - *(.eb2text) - *(.eb2rodata) - *(.eb2rodata.*) - } >EXTMEMB2 -*/ - /* EXTMEM Bank0 */ -/* - .eb3text : - { - *(.eb3text) - *(.eb3rodata) - *(.eb3rodata.*) - } >EXTMEMB3 -*/ - - /* After that there are only debugging sections. */ - - /* This can remove the debugging information from the standard libraries */ - /* - DISCARD : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - */ - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* - * DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. - */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/startup_ARMCM4.S b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/startup_ARMCM4.S deleted file mode 100644 index 5178bec41..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/startup_ARMCM4.S +++ /dev/null @@ -1,383 +0,0 @@ -/* File: startup_ARMCM4.S - * Purpose: startup file for Cortex-M4 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V2.0 - * Date: 16 August 2013 - * -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - .syntax unified - .arch armv7e-m - - .section .stack - .align 3 - - .equ ulMainStackSize, 200 * 4 - .equ Stack_Size, 0x004 - .globl __StackTop - .globl __StackLimit - .extern ulMainStack -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector,"a",%progbits - .global __Vectors - .type __Vectors, %object - .size __Vectors, .-__Vectors -__Vectors: - .long ulMainStack + ulMainStackSize /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts */ - .long NVIC_Handler_I2C0 - .long NVIC_Handler_I2C1 - .long NVIC_Handler_I2C2 - .long NVIC_Handler_I2C3 - .long NVIC_Handler_DMA0 - .long NVIC_Handler_DMA1 - .long NVIC_Handler_DMA2 - .long NVIC_Handler_DMA3 - .long NVIC_Handler_DMA4 - .long NVIC_Handler_DMA5 - .long NVIC_Handler_DMA6 - .long NVIC_Handler_DMA7 - .long NVIC_Handler_LPCBERR - .long NVIC_Handler_UART0 - .long NVIC_Handler_IMAP0 - .long NVIC_Handler_EC0_IBF - .long NVIC_Handler_EC0_OBF - .long NVIC_Handler_EC1_IBF - .long NVIC_Handler_EC1_OBF - .long NVIC_Handler_PM1_CTL - .long NVIC_Handler_PM1_EN - .long NVIC_Handler_PM1_STS - .long NVIC_Handler_MIF8042_OBF - .long NVIC_Handler_MIF8042_IBF - .long NVIC_Handler_MAILBOX - .long NVIC_Handler_PECI - .long NVIC_Handler_TACH0 - .long NVIC_Handler_TACH1 - .long NVIC_Handler_ADC_SNGL - .long NVIC_Handler_ADC_RPT - .long NVIC_Handler_V2P_INT0 - .long NVIC_Handler_V2P_INT1 - .long NVIC_Handler_PS2_CH0 - .long NVIC_Handler_PS2_CH1 - .long NVIC_Handler_PS2_CH2 - .long NVIC_Handler_PS2_CH3 - .long NVIC_Handler_SPI0_TX - .long NVIC_Handler_SPI0_RX - .long NVIC_Handler_HIB_TMR - .long NVIC_Handler_KEY_INT - .long NVIC_Handler_KEY_WAKE - .long NVIC_Handler_RPM_STALL - .long NVIC_Handler_RPM_SPIN - .long NVIC_Handler_VBAT - .long NVIC_Handler_LED0 - .long NVIC_Handler_LED1 - .long NVIC_Handler_LED2 - .long NVIC_Handler_MBC_ERR - .long NVIC_Handler_MBC_BUSY - .long NVIC_Handler_TMR0 - .long NVIC_Handler_TMR1 - .long NVIC_Handler_TMR2 - .long NVIC_Handler_TMR3 - .long NVIC_Handler_TMR4 - .long NVIC_Handler_TMR5 - .long NVIC_Handler_SPI1_TX - .long NVIC_Handler_SPI1_RX - .long NVIC_Handler_GIRQ08 - .long NVIC_Handler_GIRQ09 - .long NVIC_Handler_GIRQ10 - .long NVIC_Handler_GIRQ11 - ;.long NVIC_Handler_GIRQ12 - .long interrupt_irq12 - ;.long NVIC_Handler_GIRQ13 - .long NVIC_Handler_GIRQ13 - .long NVIC_Handler_GIRQ14 - .long NVIC_Handler_GIRQ15 - .long NVIC_Handler_GIRQ16 - .long NVIC_Handler_GIRQ17 - .long NVIC_Handler_GIRQ18 - .long NVIC_Handler_GIRQ19 - .long NVIC_Handler_GIRQ20 - .long NVIC_Handler_GIRQ21 - .long NVIC_Handler_GIRQ22 - .long NVIC_Handler_GIRQ23 - .long NVIC_Handler_073 - .long NVIC_Handler_074 - .long NVIC_Handler_075 - .long NVIC_Handler_076 - .long NVIC_Handler_077 - .long NVIC_Handler_078 - .long NVIC_Handler_079 - .long NVIC_Handler_080 - .long NVIC_Handler_DMA8 - .long NVIC_Handler_DMA9 - .long NVIC_Handler_DMA10 - .long NVIC_Handler_DMA11 - .long NVIC_Handler_LED3 - .long NVIC_Handler_PKE_ERR - .long NVIC_Handler_PKE_END - .long NVIC_Handler_TRNG - .long NVIC_Handler_AES - .long NVIC_Handler_HASH - - - .text - .thumb - .thumb_func - .align 2 - .globl _start - .extern main - .globl Reset_Handler - .type Reset_Handler, %function -_start: -Reset_Handler: -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr sp, =ulMainStack + ulMainStackSize - sub sp, sp, #4 - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. - */ - - /* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 - -#ifndef __NO_SYSTEM_INIT -/* bl SystemInit */ -#endif - - bl main - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - def_irq_handler HardFault_Handler - def_irq_handler MemManage_Handler - def_irq_handler BusFault_Handler - def_irq_handler UsageFault_Handler -/* def_irq_handler SVC_Handler */ - def_irq_handler DebugMon_Handler -/* def_irq_handler PendSV_Handler */ -/* def_irq_handler SysTick_Handler */ - def_irq_handler DEF_IRQHandler - - def_irq_handler NVIC_Handler_I2C0 - def_irq_handler NVIC_Handler_I2C1 - def_irq_handler NVIC_Handler_I2C2 - def_irq_handler NVIC_Handler_I2C3 - def_irq_handler NVIC_Handler_DMA0 - def_irq_handler NVIC_Handler_DMA1 - def_irq_handler NVIC_Handler_DMA2 - def_irq_handler NVIC_Handler_DMA3 - def_irq_handler NVIC_Handler_DMA4 - def_irq_handler NVIC_Handler_DMA5 - def_irq_handler NVIC_Handler_DMA6 - def_irq_handler NVIC_Handler_DMA7 - def_irq_handler NVIC_Handler_LPCBERR - def_irq_handler NVIC_Handler_UART0 - def_irq_handler NVIC_Handler_IMAP0 - def_irq_handler NVIC_Handler_EC0_IBF - def_irq_handler NVIC_Handler_EC0_OBF - def_irq_handler NVIC_Handler_EC1_IBF - def_irq_handler NVIC_Handler_EC1_OBF - def_irq_handler NVIC_Handler_PM1_CTL - def_irq_handler NVIC_Handler_PM1_EN - def_irq_handler NVIC_Handler_PM1_STS - def_irq_handler NVIC_Handler_MIF8042_OBF - def_irq_handler NVIC_Handler_MIF8042_IBF - def_irq_handler NVIC_Handler_MAILBOX - def_irq_handler NVIC_Handler_PECI - def_irq_handler NVIC_Handler_TACH0 - def_irq_handler NVIC_Handler_TACH1 - def_irq_handler NVIC_Handler_ADC_SNGL - def_irq_handler NVIC_Handler_ADC_RPT - def_irq_handler NVIC_Handler_V2P_INT0 - def_irq_handler NVIC_Handler_V2P_INT1 - def_irq_handler NVIC_Handler_PS2_CH0 - def_irq_handler NVIC_Handler_PS2_CH1 - def_irq_handler NVIC_Handler_PS2_CH2 - def_irq_handler NVIC_Handler_PS2_CH3 - def_irq_handler NVIC_Handler_SPI0_TX - def_irq_handler NVIC_Handler_SPI0_RX - def_irq_handler NVIC_Handler_HIB_TMR - def_irq_handler NVIC_Handler_KEY_INT - def_irq_handler NVIC_Handler_KEY_WAKE - def_irq_handler NVIC_Handler_RPM_STALL - def_irq_handler NVIC_Handler_RPM_SPIN - def_irq_handler NVIC_Handler_VBAT - def_irq_handler NVIC_Handler_LED0 - def_irq_handler NVIC_Handler_LED1 - def_irq_handler NVIC_Handler_LED2 - def_irq_handler NVIC_Handler_MBC_ERR - def_irq_handler NVIC_Handler_MBC_BUSY - def_irq_handler NVIC_Handler_TMR0 - def_irq_handler NVIC_Handler_TMR1 - def_irq_handler NVIC_Handler_TMR2 - def_irq_handler NVIC_Handler_TMR3 - def_irq_handler NVIC_Handler_TMR4 - def_irq_handler NVIC_Handler_TMR5 - def_irq_handler NVIC_Handler_SPI1_TX - def_irq_handler NVIC_Handler_SPI1_RX - def_irq_handler NVIC_Handler_GIRQ08 - def_irq_handler NVIC_Handler_GIRQ09 - def_irq_handler NVIC_Handler_GIRQ10 - def_irq_handler NVIC_Handler_GIRQ11 - ;def_irq_handler NVIC_Handler_GIRQ12 - def_irq_handler interrupt_irq12 - ;def_irq_handler NVIC_Handler_GIRQ13 - def_irq_handler interrupt_irq13 - def_irq_handler NVIC_Handler_GIRQ14 - def_irq_handler NVIC_Handler_GIRQ15 - def_irq_handler NVIC_Handler_GIRQ16 - def_irq_handler NVIC_Handler_GIRQ17 - def_irq_handler NVIC_Handler_GIRQ18 - def_irq_handler NVIC_Handler_GIRQ19 - def_irq_handler NVIC_Handler_GIRQ20 - def_irq_handler NVIC_Handler_GIRQ21 - def_irq_handler NVIC_Handler_GIRQ22 - def_irq_handler NVIC_Handler_GIRQ23 - def_irq_handler NVIC_Handler_073 - def_irq_handler NVIC_Handler_074 - def_irq_handler NVIC_Handler_075 - def_irq_handler NVIC_Handler_076 - def_irq_handler NVIC_Handler_077 - def_irq_handler NVIC_Handler_078 - def_irq_handler NVIC_Handler_079 - def_irq_handler NVIC_Handler_080 - def_irq_handler NVIC_Handler_DMA8 - def_irq_handler NVIC_Handler_DMA9 - def_irq_handler NVIC_Handler_DMA10 - def_irq_handler NVIC_Handler_DMA11 - def_irq_handler NVIC_Handler_LED3 - def_irq_handler NVIC_Handler_PKE_ERR - def_irq_handler NVIC_Handler_PKE_END - def_irq_handler NVIC_Handler_TRNG - def_irq_handler NVIC_Handler_AES - def_irq_handler NVIC_Handler_HASH - - .end diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/system.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/system.c deleted file mode 100644 index 9ecd3201d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/GCC_Specific/system.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -*/ - -/** @defgroup pwm pwm_c_wrapper - * @{ - */ -/** @file pwm_c_wrapper.cpp - \brief the pwm component C wrapper - This program is designed to allow the other C programs to be able to use this component - - There are entry points for all C wrapper API implementation - -Platform: This is ARC-based component - -Toolset: Metaware IDE(8.5.1) -Reference: smsc_reusable_fw_requirement.doc */ - -/******************************************************************************* - * SMSC version control information (Perforce): - * - * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $ - * REVISION: $Revision: #1 $ - * DATETIME: $DateTime: 2015/12/23 15:37:58 $ - * AUTHOR: $Author: akrishnan $ - * - * Revision history (latest first): - * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) - * #2 2011/03/25 martin_y support FPGA build 058 apps - * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200 - *********************************************************************************** - */ -/* Imported Header File */ -//#include "common.h" -//#include "build.h" -#include - -#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 -#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) -#define CPU_CLOCK_DIVIDER 1 - -/* The start up code is configured to use the following array as the stack used -by main(), which will then also get used by FreeRTOS interrupt handlers after -the scheduler has been started. */ -#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S. -volatile uint32_t ulMainStack[ 200 ]; - -/******************************************************************************/ -/** system_set_ec_clock -* Set CPU speed -* @param void -* @return void -*******************************************************************************/ - -void system_set_ec_clock(void) -{ - - /* Set ARC CPU Clock Divider to determine the CPU speed */ - /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */ - MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER; - -} /* End system_set_ec_clock() */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/JLinkLog.txt b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/JLinkLog.txt deleted file mode 100644 index d6b5ccdce..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/JLinkLog.txt +++ /dev/null @@ -1,492 +0,0 @@ - -T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total) -T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total) -T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total) -T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total) -T220C 000:298 JLINK_OpenEx(...) -Firmware: J-Link V9 compiled Oct 9 2015 20:34:47 -Hardware: V9.10 -S/N: 59101789 -Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total) -T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total) -T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total) -T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total) -T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) -T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) -T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total) -T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) -T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total) -T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total) -T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total) -T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) - -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0) -ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total) -T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total) -T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total) -T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total) -T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total) -T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total) -T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total) -T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total) -T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total) -T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total) -T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total) -T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total) -T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total) -T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total) -T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total) -T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total) -T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total) -T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total) -T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total) -T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total) -T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total) -T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total) -T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total) -T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) - -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) - -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total) -T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total) -T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total) -T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total) -T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total) -T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total) -T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total) -T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total) -T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total) -T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total) -T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total) -T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total) -T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total) -T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total) -T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total) -T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total) -T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total) -T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total) -T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total) -T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total) -T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total) -T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total) -T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total) -T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total) -T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total) -T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total) -T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total) -T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total) -T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total) -T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total) -T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total) -T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total) -T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) -T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) -T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total) -T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total) -T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total) -T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total) -T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total) -T220C 027:508 (0005ms, 2544ms total) -T220C 027:508 Closed (0005ms, 2544ms total) diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/JLinkSettings.ini deleted file mode 100644 index 706cf39a9..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/JLinkSettings.ini +++ /dev/null @@ -1,35 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 1 -Device="Unspecified" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.sct b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.sct deleted file mode 100644 index fe37a40a3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.sct +++ /dev/null @@ -1,28 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - - -LR_IROM1 0x00100000 0x00020000 { ; load region size_region - ER_IROM1 0x00000000 0x00000000 { ; load address = execution address - } - RW_IRAM1 0x00100000 0x00020000 { ; RW data - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+RW +ZI) - } -} - - -;LR_IROM1 0x00100000 0x00018000 { ; load region size_region -; ER_IROM1 0x00100000 0x00018000 { ; load address = execution address -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x00118000 0x00008000 { ; RW data -; .ANY (+RW +ZI) -; } -;} - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.uvoptx deleted file mode 100644 index f4f0cce03..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.uvoptx +++ /dev/null @@ -1,622 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - RTOSDemo - 0x4 - ARM-ADS - - 48000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 7 - - 0 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - - - - - - - - - - init_app.ini - BIN\UL2CM3.DLL - - - - 0 - DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - DLGUARM - (105=-1,-1,-1,-1,0) - - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - -T0 - - - 0 - UL2CM3 - -UV1115SAE -O2983 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0100000 -FL018000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) - - - - - - 0 - 1 - ulLED,0x0A - - - - - 1 - 2 - 0xe000e284 - 4 - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - - - 0 - - - - - System - 0 - 0 - 0 - 0 - - 1 - 1 - 2 - 0 - 0 - 0 - .\startup_CEC1302.s - startup_CEC1302.s - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - .\system.c - system.c - 0 - 0 - - - - - main_and_config - 0 - 0 - 0 - 0 - - 2 - 3 - 1 - 0 - 0 - 0 - ..\main.c - main.c - 0 - 0 - - - 2 - 4 - 5 - 0 - 0 - 0 - ..\FreeRTOSConfig.h - FreeRTOSConfig.h - 0 - 0 - - - - - FreeRTOS_Source - 0 - 0 - 0 - 0 - - 3 - 5 - 1 - 0 - 0 - 0 - ..\..\..\Source\event_groups.c - event_groups.c - 0 - 0 - - - 3 - 6 - 1 - 0 - 0 - 0 - ..\..\..\Source\list.c - list.c - 0 - 0 - - - 3 - 7 - 1 - 0 - 0 - 0 - ..\..\..\Source\queue.c - queue.c - 0 - 0 - - - 3 - 8 - 1 - 0 - 0 - 0 - ..\..\..\Source\tasks.c - tasks.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 - ..\..\..\Source\timers.c - timers.c - 0 - 0 - - - 3 - 10 - 1 - 0 - 0 - 0 - ..\..\..\Source\portable\MemMang\heap_4.c - heap_4.c - 0 - 0 - - - 3 - 11 - 1 - 1 - 0 - 0 - ..\..\..\Source\portable\RVDS\ARM_CM4F\port.c - port.c - 0 - 0 - - - - - main_low_power - 0 - 0 - 0 - 0 - - 4 - 12 - 1 - 0 - 0 - 0 - ..\main_low_power\main_low_power.c - main_low_power.c - 0 - 0 - - - 4 - 13 - 1 - 0 - 0 - 0 - ..\main_low_power\low_power_tick_config.c - low_power_tick_config.c - 0 - 0 - - - - - main_full - 0 - 0 - 0 - 0 - - 5 - 14 - 1 - 1 - 0 - 0 - ..\main_full\main_full.c - main_full.c - 0 - 0 - - - 5 - 15 - 1 - 0 - 0 - 0 - .\RegTest.c - RegTest.c - 0 - 0 - - - 5 - 16 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\flop.c - flop.c - 0 - 0 - - - 5 - 17 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\EventGroupsDemo.c - EventGroupsDemo.c - 0 - 0 - - - 5 - 18 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\TaskNotify.c - TaskNotify.c - 0 - 0 - - - 5 - 19 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\blocktim.c - blocktim.c - 0 - 0 - - - 5 - 20 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\dynamic.c - dynamic.c - 0 - 0 - - - 5 - 21 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\GenQTest.c - GenQTest.c - 0 - 0 - - - 5 - 22 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\TimerDemo.c - TimerDemo.c - 0 - 0 - - - 5 - 23 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\IntQueue.c - IntQueue.c - 0 - 0 - - - 5 - 24 - 1 - 0 - 0 - 0 - ..\main_full\IntQueueTimer.c - IntQueueTimer.c - 0 - 0 - - - 5 - 25 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\countsem.c - countsem.c - 0 - 0 - - - 5 - 26 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\semtest.c - semtest.c - 0 - 0 - - - 5 - 27 - 1 - 0 - 0 - 0 - ..\..\Common\Minimal\death.c - death.c - 0 - 0 - - - - - peripheral_library - 0 - 0 - 0 - 0 - - 6 - 28 - 1 - 0 - 0 - 0 - ..\peripheral_library\basic_timer\btimer_api.c - btimer_api.c - 0 - 0 - - - 6 - 29 - 1 - 0 - 0 - 0 - ..\peripheral_library\basic_timer\btimer_perphl.c - btimer_perphl.c - 0 - 0 - - - 6 - 30 - 1 - 0 - 0 - 0 - ..\peripheral_library\pcr\pcr_perphl.c - pcr_perphl.c - 0 - 0 - - - 6 - 31 - 1 - 0 - 0 - 0 - ..\peripheral_library\pcr\pcr_api.c - pcr_api.c - 0 - 0 - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.uvprojx deleted file mode 100644 index c0cb1e1eb..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RTOSDemo.uvprojx +++ /dev/null @@ -1,628 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - RTOSDemo - 0x4 - ARM-ADS - 5060061::V5.06 update 1 (build 61)::ARMCC - - - ARMCM4_FP - ARM - ARM.CMSIS.4.5.0 - http://www.keil.com/pack/ - IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) - 0 - $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h - - - - - - - - - - $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\Objects\ - RTOSDemo - 1 - 0 - 1 - 1 - 1 - .\Listings\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 8 - 1 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x0 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x100000 - 0x18000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x118000 - 0x8000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - ..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x20000000 - - RTOSDemo.sct - - - - - - - - - - - System - - - startup_CEC1302.s - 2 - .\startup_CEC1302.s - - - system.c - 1 - .\system.c - - - - - main_and_config - - - main.c - 1 - ..\main.c - - - FreeRTOSConfig.h - 5 - ..\FreeRTOSConfig.h - - - - - FreeRTOS_Source - - - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 0 - 0 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - - event_groups.c - 1 - ..\..\..\Source\event_groups.c - - - list.c - 1 - ..\..\..\Source\list.c - - - queue.c - 1 - ..\..\..\Source\queue.c - - - tasks.c - 1 - ..\..\..\Source\tasks.c - - - timers.c - 1 - ..\..\..\Source\timers.c - - - heap_4.c - 1 - ..\..\..\Source\portable\MemMang\heap_4.c - - - port.c - 1 - ..\..\..\Source\portable\RVDS\ARM_CM4F\port.c - - - - - main_low_power - - - main_low_power.c - 1 - ..\main_low_power\main_low_power.c - - - low_power_tick_config.c - 1 - ..\main_low_power\low_power_tick_config.c - - - - - main_full - - - main_full.c - 1 - ..\main_full\main_full.c - - - RegTest.c - 1 - .\RegTest.c - - - flop.c - 1 - ..\..\Common\Minimal\flop.c - - - EventGroupsDemo.c - 1 - ..\..\Common\Minimal\EventGroupsDemo.c - - - TaskNotify.c - 1 - ..\..\Common\Minimal\TaskNotify.c - - - blocktim.c - 1 - ..\..\Common\Minimal\blocktim.c - - - dynamic.c - 1 - ..\..\Common\Minimal\dynamic.c - - - GenQTest.c - 1 - ..\..\Common\Minimal\GenQTest.c - - - TimerDemo.c - 1 - ..\..\Common\Minimal\TimerDemo.c - - - IntQueue.c - 1 - ..\..\Common\Minimal\IntQueue.c - - - IntQueueTimer.c - 1 - ..\main_full\IntQueueTimer.c - - - countsem.c - 1 - ..\..\Common\Minimal\countsem.c - - - semtest.c - 1 - ..\..\Common\Minimal\semtest.c - - - death.c - 1 - ..\..\Common\Minimal\death.c - - - - - peripheral_library - - - btimer_api.c - 1 - ..\peripheral_library\basic_timer\btimer_api.c - - - btimer_perphl.c - 1 - ..\peripheral_library\basic_timer\btimer_perphl.c - - - pcr_perphl.c - 1 - ..\peripheral_library\pcr\pcr_perphl.c - - - pcr_api.c - 1 - ..\peripheral_library\pcr\pcr_api.c - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RegTest.c deleted file mode 100644 index e0bd936d1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/RegTest.c +++ /dev/null @@ -1,454 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * "Reg test" tasks - These fill the registers with known values, then check - * that each register maintains its expected value for the lifetime of the - * task. Each task uses a different set of values. The reg test tasks execute - * with a very low priority, so get preempted very frequently. A register - * containing an unexpected value is indicative of an error in the context - * switching mechanism. - */ - - -__asm void vRegTest1Implementation( void ) -{ - PRESERVE8 - IMPORT ulRegTest1LoopCounter - - /* Fill the core registers with known values. */ - mov r0, #100 - mov r1, #101 - mov r2, #102 - mov r3, #103 - mov r4, #104 - mov r5, #105 - mov r6, #106 - mov r7, #107 - mov r8, #108 - mov r9, #109 - mov r10, #110 - mov r11, #111 - mov r12, #112 - - /* Fill the VFP registers with known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg1_loop - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d1 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d2 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d3 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d4 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d5 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d6 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d7 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d8 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d9 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d10 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d11 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d12 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d13 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d14 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d15 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg1_loopf_pass - -reg1_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg1_error_loopf - -reg1_loopf_pass - - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - cmp r8, #108 - bne reg1_error_loop - cmp r9, #109 - bne reg1_error_loop - cmp r10, #110 - bne reg1_error_loop - cmp r11, #111 - bne reg1_error_loop - cmp r12, #112 - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg1_loop - -reg1_error_loop - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop -} -/*-----------------------------------------------------------*/ - -__asm void vRegTest2Implementation( void ) -{ - PRESERVE8 - IMPORT ulRegTest2LoopCounter - - /* Set all the core registers to known values. */ - mov r0, #-1 - mov r1, #1 - mov r2, #2 - mov r3, #3 - mov r4, #4 - mov r5, #5 - mov r6, #6 - mov r7, #7 - mov r8, #8 - mov r9, #9 - mov r10, #10 - mov r11, #11 - mov r12, #12 - - /* Set all the VFP to known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg2_loop - - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d1 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d2 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d3 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d4 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d5 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d6 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d7 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d8 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d9 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d10 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d11 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d12 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d13 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d14 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d15 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg2_loopf_pass - -reg2_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg2_error_loopf - -reg2_loopf_pass - - cmp r0, #-1 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - cmp r8, #8 - bne reg2_error_loop - cmp r9, #9 - bne reg2_error_loop - cmp r10, #10 - bne reg2_error_loop - cmp r11, #11 - bne reg2_error_loop - cmp r12, #12 - bne reg2_error_loop - - /* Increment the loop counter to indicate this test is still functioning - correctly. */ - push { r0-r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - - /* Yield to increase test coverage. */ - movs r0, #0x01 - ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ - lsl r0, r0, #28 /* Shift to PendSV bit */ - str r0, [r1] - dsb - - pop { r0-r1 } - - /* Start again. */ - b reg2_loop - -reg2_error_loop - /* If this line is hit then there was an error in a core register value. - This loop ensures the loop counter variable stops incrementing. */ - b reg2_error_loop -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/init_app.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/init_app.ini deleted file mode 100644 index 6a0e39168..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/init_app.ini +++ /dev/null @@ -1,7 +0,0 @@ -//Initialization file for the application code -RESET -T -T -T -eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine -T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/startup_CEC1302.s b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/startup_CEC1302.s deleted file mode 100644 index 17984f30e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/startup_CEC1302.s +++ /dev/null @@ -1,496 +0,0 @@ -;/* -;****************************************************************************** -;* © 2013 Microchip Technology Inc. and its subsidiaries. -;* You may use this software and any derivatives exclusively with -;* Microchip products. -;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -;* OF THESE TERMS. -;****************************************************************************** -; */ -;/** @file startup_MEC1322.s -; *MEC1322 API Test: startup and vector table -; */ -;/** @defgroup startup_MEC1322 -; * @{ -; */ - - IMPORT __main - IMPORT |Image$$RW_IRAM1$$Base| - IMPORT |Image$$RW_IRAM1$$Limit| - IMPORT |Image$$RW_IRAM1$$Length| - IMPORT |Image$$RW_IRAM1$$ZI$$Base| - IMPORT |Image$$RW_IRAM1$$ZI$$Limit| - IMPORT |Image$$ER_IROM1$$Base| - IMPORT |Image$$ER_IROM1$$Limit| - IMPORT main - IMPORT system_set_ec_clock - - EXPORT Reset_Handler - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000800 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __stack_bottom -__stack_bottom -Stack_Mem SPACE Stack_Size -__initial_sp - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __tx_vectors -__tx_vectors -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; MEC1322 External Interrupts - DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0 - DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1 - DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2 - DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3 - DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0 - DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1 - DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2 - DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3 - DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4 - DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5 - DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6 - DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7 - DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error - DCD NVIC_Handler_UART0 ; 74h: 13, UART0 - DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0 - DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF - DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF - DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF - DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF - DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL - DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN - DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS - DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF - DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF - DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox - DCD NVIC_Handler_PECI ; A4h: 25, PECI - DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0 - DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1 - DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL - DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT - DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0 - DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1 - DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0 - DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1 - DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2 - DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3 - DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX - DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX - DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR - DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT - DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE - DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL - DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN - DCD NVIC_Handler_VBAT ; ECh: 43, VBAT - DCD NVIC_Handler_LED0 ; F0h: 44, LED0 - DCD NVIC_Handler_LED1 ; F4h: 45, LED1 - DCD NVIC_Handler_LED2 ; F8h: 46, LED2 - DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR - DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY - DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0 - DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1 - DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2 - DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3 - DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4 - DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5 - DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX - DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX - DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08 - DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09 - DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10 - DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11 - DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12 - DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13 - DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14 - DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15 - DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16 - DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17 - DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18 - DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19 - DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20 - DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21 - DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22 - DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23 - DCD NVIC_Handler_073 ; 164h: 73, unknown - DCD NVIC_Handler_074 ; 168h: 74, unknown - DCD NVIC_Handler_075 ; 16Ch: 75, unknown - DCD NVIC_Handler_076 ; 170h: 76, unknown - DCD NVIC_Handler_077 ; 174h: 77, unknown - DCD NVIC_Handler_078 ; 178h: 78, unknown - DCD NVIC_Handler_079 ; 17Ch: 79, unknown - DCD NVIC_Handler_080 ; 180h: 80, unknown - DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8 - DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9 - DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10 - DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11 - DCD NVIC_Handler_LED3 ; 194h: 85, LED3 - DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error - DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End - DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen - DCD NVIC_Handler_AES ; 1A4h: 89, AES - DCD NVIC_Handler_HASH ; 1A8h: 90, HASH - - - AREA ROMTABLE, CODE, READONLY - THUMB -; ---------- ROM API ---------- -; Jump table to ROM API C functions -; -; -; ---------- ROM API End ------ -; Reset Handler - - AREA |.text|, CODE, READONLY - THUMB - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - - CPSID i - - ; support code is loaded from ROM loader - LDR SP, =__initial_sp - ; configure CPU speed - LDR R0, =system_set_ec_clock - BLX R0 - - LDR SP, =__initial_sp - - ; support FPU - IF {CPU} = "Cortex-M4.fp" - LDR R0, =0xE000ED88 ; Enable CP10,CP11 - LDR R1,[R0] - ORR R1,R1,#(0xF << 20) - STR R1,[R0] - ENDIF - - ; Enter Keil startup code which calls our main - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - MOV R7,#1 - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - MOV R7,#2 - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - MOV R7,#3 - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - MOV R7,#4 - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - MOV R7,#5 - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - MOV R7,#6 - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - MOV R7,#7 - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - MOV R7,#8 - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - MOV R7,#9 - B . - ENDP - -Default_Handler PROC - - ; External MEC1322 NVIC Interrupt Inputs - EXPORT NVIC_Handler_I2C0 [WEAK] - EXPORT NVIC_Handler_I2C1 [WEAK] - EXPORT NVIC_Handler_I2C2 [WEAK] - EXPORT NVIC_Handler_I2C3 [WEAK] - EXPORT NVIC_Handler_DMA0 [WEAK] - EXPORT NVIC_Handler_DMA1 [WEAK] - EXPORT NVIC_Handler_DMA2 [WEAK] - EXPORT NVIC_Handler_DMA3 [WEAK] - EXPORT NVIC_Handler_DMA4 [WEAK] - EXPORT NVIC_Handler_DMA5 [WEAK] - EXPORT NVIC_Handler_DMA6 [WEAK] - EXPORT NVIC_Handler_DMA7 [WEAK] - EXPORT NVIC_Handler_LPCBERR [WEAK] - EXPORT NVIC_Handler_UART0 [WEAK] - EXPORT NVIC_Handler_IMAP0 [WEAK] - EXPORT NVIC_Handler_EC0_IBF [WEAK] - EXPORT NVIC_Handler_EC0_OBF [WEAK] - EXPORT NVIC_Handler_EC1_IBF [WEAK] - EXPORT NVIC_Handler_EC1_OBF [WEAK] - EXPORT NVIC_Handler_PM1_CTL [WEAK] - EXPORT NVIC_Handler_PM1_EN [WEAK] - EXPORT NVIC_Handler_PM1_STS [WEAK] - EXPORT NVIC_Handler_MIF8042_OBF [WEAK] - EXPORT NVIC_Handler_MIF8042_IBF [WEAK] - EXPORT NVIC_Handler_MAILBOX [WEAK] - EXPORT NVIC_Handler_PECI [WEAK] - EXPORT NVIC_Handler_TACH0 [WEAK] - EXPORT NVIC_Handler_TACH1 [WEAK] - EXPORT NVIC_Handler_ADC_SNGL [WEAK] - EXPORT NVIC_Handler_ADC_RPT [WEAK] - EXPORT NVIC_Handler_V2P_INT0 [WEAK] - EXPORT NVIC_Handler_V2P_INT1 [WEAK] - EXPORT NVIC_Handler_PS2_CH0 [WEAK] - EXPORT NVIC_Handler_PS2_CH1 [WEAK] - EXPORT NVIC_Handler_PS2_CH2 [WEAK] - EXPORT NVIC_Handler_PS2_CH3 [WEAK] - EXPORT NVIC_Handler_SPI0_TX [WEAK] - EXPORT NVIC_Handler_SPI0_RX [WEAK] - EXPORT NVIC_Handler_HIB_TMR [WEAK] - EXPORT NVIC_Handler_KEY_INT [WEAK] - EXPORT NVIC_Handler_KEY_WAKE [WEAK] - EXPORT NVIC_Handler_RPM_STALL [WEAK] - EXPORT NVIC_Handler_RPM_SPIN [WEAK] - EXPORT NVIC_Handler_VBAT [WEAK] - EXPORT NVIC_Handler_LED0 [WEAK] - EXPORT NVIC_Handler_LED1 [WEAK] - EXPORT NVIC_Handler_LED2 [WEAK] - EXPORT NVIC_Handler_MBC_ERR [WEAK] - EXPORT NVIC_Handler_MBC_BUSY [WEAK] - EXPORT NVIC_Handler_TMR0 [WEAK] - EXPORT NVIC_Handler_TMR1 [WEAK] - EXPORT NVIC_Handler_TMR2 [WEAK] - EXPORT NVIC_Handler_TMR3 [WEAK] - EXPORT NVIC_Handler_TMR4 [WEAK] - EXPORT NVIC_Handler_TMR5 [WEAK] - EXPORT NVIC_Handler_SPI1_TX [WEAK] - EXPORT NVIC_Handler_SPI1_RX [WEAK] - EXPORT NVIC_Handler_GIRQ08 [WEAK] - EXPORT NVIC_Handler_GIRQ09 [WEAK] - EXPORT NVIC_Handler_GIRQ10 [WEAK] - EXPORT NVIC_Handler_GIRQ11 [WEAK] - EXPORT NVIC_Handler_GIRQ12 [WEAK] - EXPORT NVIC_Handler_GIRQ13 [WEAK] - EXPORT NVIC_Handler_GIRQ14 [WEAK] - EXPORT NVIC_Handler_GIRQ15 [WEAK] - EXPORT NVIC_Handler_GIRQ16 [WEAK] - EXPORT NVIC_Handler_GIRQ17 [WEAK] - EXPORT NVIC_Handler_GIRQ18 [WEAK] - EXPORT NVIC_Handler_GIRQ19 [WEAK] - EXPORT NVIC_Handler_GIRQ20 [WEAK] - EXPORT NVIC_Handler_GIRQ21 [WEAK] - EXPORT NVIC_Handler_GIRQ22 [WEAK] - EXPORT NVIC_Handler_GIRQ23 [WEAK] - EXPORT NVIC_Handler_073 [WEAK] - EXPORT NVIC_Handler_074 [WEAK] - EXPORT NVIC_Handler_075 [WEAK] - EXPORT NVIC_Handler_076 [WEAK] - EXPORT NVIC_Handler_077 [WEAK] - EXPORT NVIC_Handler_078 [WEAK] - EXPORT NVIC_Handler_079 [WEAK] - EXPORT NVIC_Handler_080 [WEAK] - EXPORT NVIC_Handler_DMA8 [WEAK] - EXPORT NVIC_Handler_DMA9 [WEAK] - EXPORT NVIC_Handler_DMA10 [WEAK] - EXPORT NVIC_Handler_DMA11 [WEAK] - EXPORT NVIC_Handler_LED3 [WEAK] - EXPORT NVIC_Handler_PKE_ERR [WEAK] - EXPORT NVIC_Handler_PKE_END [WEAK] - EXPORT NVIC_Handler_TRNG [WEAK] - EXPORT NVIC_Handler_AES [WEAK] - EXPORT NVIC_Handler_HASH [WEAK] - -NVIC_Handler_I2C0 -NVIC_Handler_I2C1 -NVIC_Handler_I2C2 -NVIC_Handler_I2C3 -NVIC_Handler_DMA0 -NVIC_Handler_DMA1 -NVIC_Handler_DMA2 -NVIC_Handler_DMA3 -NVIC_Handler_DMA4 -NVIC_Handler_DMA5 -NVIC_Handler_DMA6 -NVIC_Handler_DMA7 -NVIC_Handler_LPCBERR -NVIC_Handler_UART0 -NVIC_Handler_IMAP0 -NVIC_Handler_EC0_IBF -NVIC_Handler_EC0_OBF -NVIC_Handler_EC1_IBF -NVIC_Handler_EC1_OBF -NVIC_Handler_PM1_CTL -NVIC_Handler_PM1_EN -NVIC_Handler_PM1_STS -NVIC_Handler_MIF8042_OBF -NVIC_Handler_MIF8042_IBF -NVIC_Handler_MAILBOX -NVIC_Handler_PECI -NVIC_Handler_TACH0 -NVIC_Handler_TACH1 -NVIC_Handler_ADC_SNGL -NVIC_Handler_ADC_RPT -NVIC_Handler_V2P_INT0 -NVIC_Handler_V2P_INT1 -NVIC_Handler_PS2_CH0 -NVIC_Handler_PS2_CH1 -NVIC_Handler_PS2_CH2 -NVIC_Handler_PS2_CH3 -NVIC_Handler_SPI0_TX -NVIC_Handler_SPI0_RX -NVIC_Handler_HIB_TMR -NVIC_Handler_KEY_INT -NVIC_Handler_KEY_WAKE -NVIC_Handler_RPM_STALL -NVIC_Handler_RPM_SPIN -NVIC_Handler_VBAT -NVIC_Handler_LED0 -NVIC_Handler_LED1 -NVIC_Handler_LED2 -NVIC_Handler_MBC_ERR -NVIC_Handler_MBC_BUSY -NVIC_Handler_TMR0 -NVIC_Handler_TMR1 -NVIC_Handler_TMR2 -NVIC_Handler_TMR3 -NVIC_Handler_TMR4 -NVIC_Handler_TMR5 -NVIC_Handler_SPI1_TX -NVIC_Handler_SPI1_RX -NVIC_Handler_GIRQ08 -NVIC_Handler_GIRQ09 -NVIC_Handler_GIRQ10 -NVIC_Handler_GIRQ11 -NVIC_Handler_GIRQ12 -NVIC_Handler_GIRQ13 -NVIC_Handler_GIRQ14 -NVIC_Handler_GIRQ15 -NVIC_Handler_GIRQ16 -NVIC_Handler_GIRQ17 -NVIC_Handler_GIRQ18 -NVIC_Handler_GIRQ19 -NVIC_Handler_GIRQ20 -NVIC_Handler_GIRQ21 -NVIC_Handler_GIRQ22 -NVIC_Handler_GIRQ23 -NVIC_Handler_073 -NVIC_Handler_074 -NVIC_Handler_075 -NVIC_Handler_076 -NVIC_Handler_077 -NVIC_Handler_078 -NVIC_Handler_079 -NVIC_Handler_080 -NVIC_Handler_DMA8 -NVIC_Handler_DMA9 -NVIC_Handler_DMA10 -NVIC_Handler_DMA11 -NVIC_Handler_LED3 -NVIC_Handler_PKE_ERR -NVIC_Handler_PKE_END -NVIC_Handler_TRNG -NVIC_Handler_AES -NVIC_Handler_HASH - B . - - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - EXPORT __stack_bottom - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;/** @} -; */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/system.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/system.c deleted file mode 100644 index a41b64f3b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/Keil_Specific/system.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -*/ - -/** @defgroup pwm pwm_c_wrapper - * @{ - */ -/** @file pwm_c_wrapper.cpp - \brief the pwm component C wrapper - This program is designed to allow the other C programs to be able to use this component - - There are entry points for all C wrapper API implementation - -Platform: This is ARC-based component - -Toolset: Metaware IDE(8.5.1) -Reference: smsc_reusable_fw_requirement.doc */ - -/******************************************************************************* - * SMSC version control information (Perforce): - * - * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $ - * REVISION: $Revision: #1 $ - * DATETIME: $DateTime: 2015/12/23 15:37:58 $ - * AUTHOR: $Author: akrishnan $ - * - * Revision history (latest first): - * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) - * #2 2011/03/25 martin_y support FPGA build 058 apps - * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200 - *********************************************************************************** - */ -/* Imported Header File */ -//#include "common.h" -//#include "build.h" -#include - -#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 -#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) -#define CPU_CLOCK_DIVIDER 1 - -/******************************************************************************/ -/** system_set_ec_clock -* Set CPU speed -* @param void -* @return void -*******************************************************************************/ - -void system_set_ec_clock(void) -{ - - /* Set ARC CPU Clock Divider to determine the CPU speed */ - /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */ - MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER; - -} /* End system_set_ec_clock() */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main.c deleted file mode 100644 index 37ada5990..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * This project provides two demo applications. A simple blinky style project - * that demonstrates low power tickless functionality, and a more comprehensive - * test and demo application. The configCREATE_LOW_POWER_DEMO setting, which is - * defined in FreeRTOSConfig.h, is used to select between the two. The simply - * blinky low power demo is implemented and described in main_low_power.c. The - * more comprehensive test and demo application is implemented and described in - * main_full.c. - * - * This file implements the code that is not demo specific, including the - * hardware setup and standard FreeRTOS hook functions. - * - * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON - * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO - * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! - * - */ - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Hardware register addresses. */ -#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 ) -#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 ) - -/*-----------------------------------------------------------*/ - -/* - * Configure the hardware as necessary to run this demo. - */ -static void prvSetupHardware( void ); - -/* - * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1. - * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0. - */ -#if( configCREATE_LOW_POWER_DEMO == 1 ) - - extern void main_low_power( void ); - -#else - - extern void main_full( void ); - - /* Some of the tests and examples executed as part of the full demo make use - of the tick hook to call API functions from an interrupt context. */ - extern void vFullDemoTickHook( void ); - -#endif /* #if configCREATE_LOW_POWER_DEMO == 1 */ - -/* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ -void vApplicationMallocFailedHook( void ); -void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); -void vApplicationTickHook( void ); - -/*-----------------------------------------------------------*/ - -/* The variable that is incremented to represent each LED toggle. On the -clicker hardware the LED state is set to the value of the least significant bit -of this variable. On other hardware, where an LED is not used, the LED just -keeps a count of the number of times the LED would otherwise have been toggled. -See the comments in main_low_power.c and main_full.c for information on the -expected LED toggle rate). */ -volatile uint32_t ulLED = 0; - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The configCREATE_LOW_POWER_DEMO setting is described at the top - of this file. */ - #if( configCREATE_LOW_POWER_DEMO == 1 ) - { - main_low_power(); - } - #else - { - main_full(); - } - #endif - - /* Should not get here. */ - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ -extern void system_set_ec_clock( void ); -extern unsigned long __Vectors[]; - - /* Disable M4 write buffer: fix MEC1322 hardware bug. */ - mainNVIC_AUX_ACTLR |= 0x07; - - system_set_ec_clock(); - - /* Assuming downloading code via the debugger - so ensure the hardware - is using the vector table downloaded with the application. */ - mainVTOR = ( uint32_t ) __Vectors; -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - /* The full demo includes tests that run from the tick hook. */ - #if( configCREATE_LOW_POWER_DEMO == 0 ) - { - /* Some of the tests and demo tasks executed by the full demo include - interaction from an interrupt - for which the tick interrupt is used - via the tick hook function. */ - vFullDemoTickHook(); - } - #endif -} -/*-----------------------------------------------------------*/ - -/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an -implementation of vApplicationGetIdleTaskMemory() to provide the memory that is -used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) -{ -/* If the buffers to be provided to the Idle task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xIdleTaskTCB; -static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} -/*-----------------------------------------------------------*/ - -/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the -application must provide an implementation of vApplicationGetTimerTaskMemory() -to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) -{ -/* If the buffers to be provided to the Timer task are declared inside this -function then they must be declared static - otherwise they will be allocated on -the stack and so not exists after this function exits. */ -static StaticTask_t xTimerTaskTCB; -static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/IntQueueTimer.c deleted file mode 100644 index bdc8e3d69..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/IntQueueTimer.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * This file initialises three timers as follows: - * - * Basic timer channels 0 and 1 provide the interrupts that are used with the - * IntQ standard demo tasks, which test interrupt nesting and using queues from - * interrupts. The interrupts use slightly different frequencies so will - * occasionally nest. - * - * Basic timer channel 2 provides a much higher frequency timer that tests the - * nesting of interrupts that don't use the FreeRTOS API. - * - * All the timers can nest with the tick interrupt - creating a maximum - * interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the - * tick interrupt does not increment the nesting count variable). - * - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "IntQueueTimer.h" -#include "IntQueue.h" - -/* Library includes. */ -#include "common_lib.h" -#include "peripheral_library/interrupt/interrupt.h" -#include "peripheral_library/basic_timer/btimer.h" - -/* The frequencies at which the first two timers expire are slightly offset to -ensure they don't remain synchronised. The frequency of the highest priority -interrupt is 20 times faster so really hammers the interrupt entry and exit -code. */ -#define tmrTIMER_0_FREQUENCY ( 2000UL ) -#define tmrTIMER_1_FREQUENCY ( 2003UL ) -#define tmrTIMER_2_FREQUENCY ( 20000UL ) - -/* The basic timer channels used for generating the three interrupts. */ -#define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */ -#define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */ -#define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */ - -/* The high frequency interrupt is given a priority above the maximum at which -interrupt safe FreeRTOS calls can be made. The priority of the lower frequency -timers must still be above the tick interrupt priority. */ -#define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 ) -#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 ) -#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) - -/* Hardware register locations. */ -#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 ) -#define tmrMMCR_EC_INTERRUPT_CONTROL ( * ( volatile uint8_t * ) 0x4000FC18 ) - -#define tmrRECORD_NESTING_DEPTH() \ - ulNestingDepth++; \ - if( ulNestingDepth > ulMaxRecordedNestingDepth ) \ - { \ - ulMaxRecordedNestingDepth = ulNestingDepth; \ - } - -/* Used to count the nesting depth, and record the maximum nesting depth. */ -volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0; - -/*-----------------------------------------------------------*/ - -void vInitialiseTimerForIntQueueTest( void ) -{ -const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY; -const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY; -const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY; - - tmrGIRQ23_ENABLE_SET = 0x03; - tmrMMCR_EC_INTERRUPT_CONTROL = 1; - - /* Initialise the three timers as described at the top of this file, and - enable their interrupts in the NVIC. */ - btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count ); - btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 ); - enable_timer0_irq(); - NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431 - NVIC_ClearPendingIRQ( TIMER0_IRQn ); - NVIC_EnableIRQ( TIMER0_IRQn ); - btimer_start( tmrTIMER_CHANNEL_0 ); - - btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count ); - btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 ); - enable_timer1_irq(); - NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432 - NVIC_ClearPendingIRQ( TIMER1_IRQn ); - NVIC_EnableIRQ( TIMER1_IRQn ); - btimer_start( tmrTIMER_CHANNEL_1 ); - - btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count ); - btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 ); - enable_timer2_irq(); - NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY ); - NVIC_ClearPendingIRQ( TIMER2_IRQn ); - NVIC_EnableIRQ( TIMER2_IRQn ); - btimer_start( tmrTIMER_CHANNEL_2 ); -} -/*-----------------------------------------------------------*/ - -/* The TMR0 interrupt is used for different purposes by the low power and full -demos respectively. */ -#if( configCREATE_LOW_POWER_DEMO == 0 ) - - void NVIC_Handler_TMR0( void ) - { - tmrRECORD_NESTING_DEPTH(); - - /* Call the IntQ test function for this channel. */ - portYIELD_FROM_ISR( xFirstTimerHandler() ); - - ulNestingDepth--; - } - -#endif /* configCREATE_LOW_POWER_DEMO */ -/*-----------------------------------------------------------*/ - -void NVIC_Handler_TMR1( void ) -{ - tmrRECORD_NESTING_DEPTH(); - - /* Just testing the xPortIsInsideInterrupt() functionality. */ - configASSERT( xPortIsInsideInterrupt() == pdTRUE ); - - /* Call the IntQ test function for this channel. */ - portYIELD_FROM_ISR( xSecondTimerHandler() ); - - ulNestingDepth--; -} -/*-----------------------------------------------------------*/ - -void NVIC_Handler_TMR2( void ) -{ - tmrRECORD_NESTING_DEPTH(); - ulNestingDepth--; -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/IntQueueTimer.h deleted file mode 100644 index 5c133ff23..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/IntQueueTimer.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef INT_QUEUE_TIMER_H -#define INT_QUEUE_TIMER_H - -void vInitialiseTimerForIntQueueTest( void ); -BaseType_t xTimer0Handler( void ); -BaseType_t xTimer1Handler( void ); - -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/main_full.c deleted file mode 100644 index a2deb7adc..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_full/main_full.c +++ /dev/null @@ -1,422 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project that demonstrates the tickless low power features of FreeRTOS, and a - * more comprehensive test and demo application. The configCREATE_LOW_POWER_DEMO - * setting in FreeRTOSConifg.h is used to select between the two. See the notes - * on using conifgCREATE_LOW_POWER_DEMO in main.c. This file implements the - * comprehensive test and demo version. - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - * - ****************************************************************************** - * - * main_full() creates all the demo application tasks and software timers, then - * starts the scheduler. The web documentation provides more details of the - * standard demo application tasks, which provide no particular functionality, - * but do provide a good example of how to use the FreeRTOS API. - * - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Reg test" tasks - These fill both the core and floating point registers with - * known values, then check that each register maintains its expected value for - * the lifetime of the task. Each task uses a different set of values. The reg - * test tasks execute with a very low priority, so get preempted very - * frequently. A register containing an unexpected value is indicative of an - * error in the context switching mechanism. - * - * "Check" task - The check task period is initially set to three seconds. The - * task checks that all the standard demo tasks, and the register check tasks, - * are not only still executing, but are executing without reporting any errors. - * If the check task discovers that a task has either stalled, or reported an - * error, then it changes its own execution period from the initial three - * seconds, to just 200ms. The check task also toggles an LED each time it is - * called. This provides a visual indication of the system status: If the LED - * toggles every three seconds, then no issues have been discovered. If the LED - * toggles every 200ms, then an issue has been discovered with at least one - * task. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "semphr.h" - -/* Standard demo application includes. */ -#include "flop.h" -#include "semtest.h" -#include "dynamic.h" -#include "blocktim.h" -#include "countsem.h" -#include "GenQTest.h" -#include "death.h" -#include "TimerDemo.h" -#include "IntQueue.h" -#include "EventGroupsDemo.h" -#include "TaskNotify.h" - -/* Priorities for the demo application tasks. */ -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) - -/* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) - -/* The period of the check task, in ms, provided no errors have been reported by -any of the standard demo tasks. ms are converted to the equivalent in ticks -using the pdMS_TO_TICKS() macro constant. */ -#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) - -/* The period of the check task, in ms, if an error has been reported in one of -the standard demo tasks. ms are converted to the equivalent in ticks using the -pdMS_TO_TICKS() macro. */ -#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) - -/* Parameters that are passed into the register check tasks solely for the -purpose of ensuring parameters are passed into tasks correctly. */ -#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) -#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) - -/* The base period used by the timer test tasks. */ -#define mainTIMER_TEST_PERIOD ( 50 ) - -/*-----------------------------------------------------------*/ - -/* - * Called by main() to run the full demo (as opposed to the blinky demo) when - * configCREATE_LOW_POWER_DEMO is set to 0. - */ -void main_full( void ); - -/* - * The check task, as described at the top of this file. - */ -static void prvCheckTask( void *pvParameters ); - -/* - * Some of the tests and demo tasks executed by the full demo include - * interaction from an interrupt - for which the tick interrupt is used via the - * tick hook function. - */ -void vFullDemoTickHook( void ); - -/* - * Register check tasks, and the tasks used to write over and check the contents - * of the FPU registers, as described at the top of this file. The nature of - * these files necessitates that they are written in an assembly file, but the - * entry points are kept in the C file for the convenience of checking the task - * parameter. - */ -static void prvRegTestTaskEntry1( void *pvParameters ); -extern void vRegTest1Implementation( void ); -static void prvRegTestTaskEntry2( void *pvParameters ); -extern void vRegTest2Implementation( void ); - -/*-----------------------------------------------------------*/ - -/* The following two variables are used to communicate the status of the -register check tasks to the check task. If the variables keep incrementing, -then the register check tasks have not discovered any errors. If a variable -stops incrementing, then an error has been found. */ -volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; - -/* The variable that is incremented to represent each LED toggle. On the -clicker hardware the LED state is set to the value of the least significant bit -of this variable. On other hardware, where an LED is not used, the LED just -keeps a count of the number of times the LED would otherwise have been toggled. -See the comments at the top of this file for information on the expected LED -toggle rate. */ -extern volatile uint32_t ulLED; - -/*-----------------------------------------------------------*/ - -void main_full( void ) -{ - /* Start all the other standard demo/test tasks. They have no particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - vStartEventGroupTasks(); - vStartTaskNotifyTask(); - vStartInterruptQueueTasks(); - - /* Create the register check tasks, as described at the top of this file */ - xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* The set of tasks created by the following function call have to be - created last as they keep account of the number of tasks they expect to see - running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the Idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details on the FreeRTOS heap - http://www.freertos.org/a00111.html. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvCheckTask( void *pvParameters ) -{ -TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; -TickType_t xLastExecutionTime; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration. - If an error is detected then the delay period is decreased from - mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the - effect of increasing the rate at which the onboard LED toggles, and in so - doing gives visual feedback of the system status. */ - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - if( xAreIntQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 0UL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 1UL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 2UL; - } - - if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 4UL; - } - - if( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 5UL; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 7UL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 8UL; - } - - if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS ) - { - ulErrorFound = 1UL << 9UL; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = 1UL << 10UL; - } - - if( xAreEventGroupTasksStillRunning() != pdPASS ) - { - ulErrorFound = 1UL << 12UL; - } - - if( xAreTaskNotificationTasksStillRunning() != pdPASS ) - { - ulErrorFound = 1UL << 14UL; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = 1UL << 15UL; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = 1UL << 16UL; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - if( ulErrorFound != pdFALSE ) - { - /* An error has been detected in one of the tasks - flash the LED - at a higher frequency to give visible feedback that something has - gone wrong (it might just be that the loop back connector required - by the comtest tasks has not been fitted). */ - xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; - } - - configASSERT( ulErrorFound == pdFALSE ); - - /* Just testing the xPortIsInsideInterrupt() functionality. */ - configASSERT( xPortIsInsideInterrupt() == pdFALSE ); - } -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTaskEntry1( void *pvParameters ) -{ - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest1Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTaskEntry2( void *pvParameters ) -{ - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) - { - /* Start the part of the test that is written in assembler. */ - vRegTest2Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check task will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ - -void vFullDemoTickHook( void ) -{ - /* Some of the tests and demo tasks executed by the full demo include - interaction from an interrupt - for which the tick interrupt is used via - the tick hook function. */ - - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); - - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - - /* Call the code that 'gives' a task notification from an ISR. */ - xNotifyTaskFromISR(); -} diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c deleted file mode 100644 index dbc969d72..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/low_power_tick_config.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* Standard includes. */ -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Library includes. */ -#include "common_lib.h" - -/* This file contains functions that will override the default implementations -in the RTOS port layer. Therefore only build this file if the low power demo -is being built. */ -#if( configCREATE_LOW_POWER_DEMO == 1 ) - -/* ID of the hibernation timer used to generate the tick. */ -#define mainTICK_HTIMER_ID 0 - -/* Written to the hibernation timer control register to configure the timer for -its higher resolution. */ -#define mainHTIMER_HIGH_RESOLUTION 0 - -/* The frequency of the hibernation timer when it is running at its higher -resolution and low resolution respectively. */ -#define mainHIGHER_RESOLUTION_TIMER_HZ ( 32787UL ) /* (1000000us / 30.5us) as each LSB is 30.5us. */ -#define mainLOW_RESOLUTION_TIMER_HZ ( 8UL ) /* ( 1000ms / 125ms ) as each LSB is 0.125s. */ - -/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate -interrupts at a low frequency. The purpose being to bring the CPU out of its -sleep mode by an interrupt other than the tick interrupt, and therefore -allowing an additional paths through the code to be tested. */ -#define lpINCLUDE_TEST_TIMER 0 - -/* Some registers are accessed directly as the library is not compatible with -all the compilers used. */ -#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 ) -#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 ) -#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 ) -#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 ) -#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL ) - -/* - * The low power demo does not use the SysTick, so override the - * vPortSetupTickInterrupt() function with an implementation that configures - * the low power clock. NOTE: This function name must not be changed as it - * is called from the RTOS portable layer. - */ -void vPortSetupTimerInterrupt( void ); - -/* - * To fully test the low power tick processing it is necessary to sometimes - * bring the MCU out of its sleep state by a method other than the tick - * interrupt. Interrupts generated from a basic timer are used for this - * purpose. - */ -#if( lpINCLUDE_TEST_TIMER == 1 ) - static void prvSetupBasicTimer( void ); -#endif - -/*-----------------------------------------------------------*/ - -/* The reload value to use in the timer to generate the tick interrupt - -assumes the timer is running at its higher resolution. */ -static const uint32_t ulHighResolutionReloadValue = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ ); - -/* Calculate how many clock increments make up a single tick period. */ -static const uint32_t ulReloadValueForOneHighResolutionTick = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ ); -//static const uint32_t usReloadValueForOneLowResolutionTick = ( mainLOW_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ ); - -/* Calculate the maximum number of ticks that can be suppressed when using the -high resolution clock and low resolution clock respectively. */ -static uint32_t ulMaximumPossibleSuppressedHighResolutionTicks = 0; -//static const uint16_t usMaximumPossibleSuppressedLowResolutionTicks = USHRT_MAX / usReloadValueForOneLowResolutionTick; - -/* As the clock is only 2KHz, it is likely a value of 1 will be too much, so -use zero - but leave the value here to assist porting to different clock -speeds. */ -static const uint32_t ulStoppedTimerCompensation = 0UL; - -/* Flag set from the tick interrupt to allow the sleep processing to know if -sleep mode was exited because of an timer interrupt or a different interrupt. */ -static volatile uint32_t ulTickFlag = pdFALSE; - -/*-----------------------------------------------------------*/ - -void NVIC_Handler_HIB_TMR( void ) -{ - lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue; - - /* Increment the RTOS tick. */ - if( xTaskIncrementTick() != pdFALSE ) - { - /* A context switch is required. Context switching is performed in - the PendSV interrupt. Pend the PendSV interrupt. */ - portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; - } - - /* The CPU woke because of a tick. */ - ulTickFlag = pdTRUE; -} -/*-----------------------------------------------------------*/ - -#if( lpINCLUDE_TEST_TIMER == 1 ) - - #define GIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 ) - - static void prvSetupBasicTimer( void ) - { - const uint8_t ucTimerChannel = 0; - const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10; - - GIRQ23_ENABLE_SET = 0x03; - *(unsigned int*)0x4000FC18 = 1; - - /* To fully test the low power tick processing it is necessary to sometimes - bring the MCU out of its sleep state by a method other than the tick - interrupt. Interrupts generated from a basic timer are used for this - purpose. */ - btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count ); - btimer_interrupt_status_get_clr( ucTimerChannel ); - enable_timer0_irq(); - NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel ); - NVIC_ClearPendingIRQ( TIMER0_IRQn ); - NVIC_EnableIRQ( TIMER0_IRQn ); - btimer_start( ucTimerChannel ); - } - -#endif /* lpINCLUDE_TEST_TIMER */ -/*-----------------------------------------------------------*/ - -void vPortSetupTimerInterrupt( void ) -{ - ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick; - - /* Set up the hibernation timer to start at the value required by the - tick interrupt. Equivalent to the following libarary call. The library - is not used as it is not compatible with all the compilers used: - htimer_enable( mainTICK_HTIMER_ID, ulHighResolutionReloadValue, mainHTIMER_HIGH_RESOLUTION ); */ - lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue; - lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION; - - /* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */ - lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT; - - /* The hibernation timer is not an auto-reload timer, so gets reset - from within the ISR itself. For that reason it's interrupt is set - to the highest possible priority to ensure clock slippage is minimised. */ - NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); - NVIC_ClearPendingIRQ( HTIMER_IRQn ); - NVIC_EnableIRQ( HTIMER_IRQn ); - - /* A basic timer is also started, purely for test purposes. Its only - purpose is to bring the CPU out of its sleep mode by an interrupt other - than the tick interrupt in order to get more code test coverage. */ - #if( lpINCLUDE_TEST_TIMER == 1 ) - { - prvSetupBasicTimer(); - } - #endif -} -/*-----------------------------------------------------------*/ - -/* Override the default definition of vPortSuppressTicksAndSleep() that is -weakly defined in the FreeRTOS Cortex-M port layer with a version that manages -the hibernation timer, as the tick is generated from the low power hibernation -timer and not the SysTick as would normally be the case on a Cortex-M. */ -void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) -{ -uint32_t ulCompleteTickPeriods, ulReloadValue, ulCompletedTimerDecrements, ulCountAfterSleep, ulCountBeforeSleep; -eSleepModeStatus eSleepAction; -TickType_t xModifiableIdleTime; - - /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* Make sure the hibernation timer reload value does not overflow the - counter. */ - if( xExpectedIdleTime > ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks ) - { - xExpectedIdleTime = ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks; - } - - /* Stop the timer momentarily. The time the timer is stopped for is - accounted for as best it can be, but using the tickless mode will - inevitably result in some tiny drift of the time maintained by the kernel - with respect to calendar time. Take the count value first as clearing - the preload value also seems to clear the count. */ - ulCountBeforeSleep = ( uint32_t ) lpHTIMER_COUNT_REGISTER; - lpHTIMER_PRELOAD_REGISTER = 0; - - /* Calculate the reload value required to wait xExpectedIdleTime tick - periods. -1 is used as the current time slice will already be part way - through, the part value coming from the current timer count value. */ - ulReloadValue = ulCountBeforeSleep + ( ulReloadValueForOneHighResolutionTick * ( xExpectedIdleTime - 1UL ) ); - - if( ulReloadValue > ulStoppedTimerCompensation ) - { - /* Compensate for the fact that the timer is going to be stopped - momentarily. */ - ulReloadValue -= ulStoppedTimerCompensation; - } - - /* Enter a critical section but don't use the taskENTER_CRITICAL() method as - that will mask interrupts that should exit sleep mode. */ - __asm volatile( "cpsid i" ); - __asm volatile( "dsb" ); - __asm volatile( "isb" ); - - /* The tick flag is set to false before sleeping. If it is true when sleep - mode is exited then sleep mode was probably exited because the tick was - suppressed for the entire xExpectedIdleTime period. */ - ulTickFlag = pdFALSE; - - /* If a context switch is pending then abandon the low power entry as - the context switch might have been pended by an external interrupt that - requires processing. */ - eSleepAction = eTaskConfirmSleepModeStatus(); - if( eSleepAction == eAbortSleep ) - { - /* Resetart the timer from whatever remains in the counter register, - but 0 is not a valid value. */ - ulReloadValue = ulCountBeforeSleep - ulStoppedTimerCompensation; - - if( ulReloadValue == 0 ) - { - ulReloadValue = ulReloadValueForOneHighResolutionTick; - ulCompleteTickPeriods = 1UL; - } - else - { - ulCompleteTickPeriods = 0UL; - } - - lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue; - - /* Re-enable interrupts - see comments above the cpsid instruction() - above. */ - __asm volatile( "cpsie i" ); - __asm volatile( "dsb" ); - __asm volatile( "isb" ); - } - else - { - /* Write the calculated reload value, which will also start the - timer. */ - lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue; - - /* Allow the application to define some pre-sleep processing. */ - xModifiableIdleTime = xExpectedIdleTime; - configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); - - /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() - means the application defined code has already executed the sleep - instructions. */ - if( xModifiableIdleTime > 0 ) - { - __asm volatile( "dsb" ); - __asm volatile( "wfi" ); - __asm volatile( "isb" ); - } - - /* Allow the application to define some post sleep processing. */ - configPOST_SLEEP_PROCESSING( xModifiableIdleTime ); - - /* Stop the hibernation timer. Again, the time the tiemr is stopped - for is accounted for as best it can be, but using the tickless mode - will inevitably result in some tiny drift of the time maintained by the - kernel with respect to calendar time. Take the count value first as - setting the preload to zero also seems to clear the count. */ - ulCountAfterSleep = lpHTIMER_COUNT_REGISTER; - lpHTIMER_PRELOAD_REGISTER = 0; - - /* Re-enable interrupts - see comments above the cpsid instruction() - above. */ - __asm volatile( "cpsie i" ); - __asm volatile( "dsb" ); - __asm volatile( "isb" ); - - if( ulTickFlag != pdFALSE ) - { - /* The tick interrupt has already executed, although because this - function is called with the scheduler suspended the actual tick - processing will not occur until after this function has exited. - The timer has already been reloaded to count in ticks, and can just - continue counting down from its current value. */ - ulReloadValue = ulCountAfterSleep; - - /* Sanity check that the timer's reload value has indeed been - reset. */ - configASSERT( ( uint32_t ) lpHTIMER_PRELOAD_REGISTER == ulReloadValueForOneHighResolutionTick ); - - /* The tick interrupt handler will already have pended the tick - processing in the kernel. As the pending tick will be processed as - soon as this function exits, the tick value maintained by the tick - is stepped forward by one less than the time spent sleeping. The - actual stepping of the tick appears later in this function. */ - ulCompleteTickPeriods = xExpectedIdleTime - 1UL; - } - else - { - /* Something other than the tick interrupt ended the sleep. How - many complete tick periods passed while the processor was - sleeping? */ - ulCompletedTimerDecrements = ulReloadValue - ulCountAfterSleep; - - /* Undo the adjustment that was made to the reload value to account - for the fact that a time slice was part way through when this - function was called before working out how many complete tick - periods this represents. (could have used [ulExpectedIdleTime * - ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on - the previous line, but this way avoids the multiplication). */ - ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep ); - ulCompleteTickPeriods = ulCompletedTimerDecrements / ulReloadValueForOneHighResolutionTick; - - /* The reload value is set to whatever fraction of a single tick - period remains. */ - ulReloadValue = ( ( ulCompleteTickPeriods + 1UL ) * ulReloadValueForOneHighResolutionTick ) - ulCompletedTimerDecrements; - } - - /* Cannot use a reload value of 0 - it will not start the timer. */ - if( ulReloadValue == 0 ) - { - /* There is no fraction remaining. */ - ulReloadValue = ulReloadValueForOneHighResolutionTick; - ulCompleteTickPeriods++; - } - - /* Restart the timer so it runs down from the reload value. The reload - value will get set to the value required to generate exactly one tick - period the next time the tick interrupt executes. */ - lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue; - } - - /* Wind the tick forward by the number of tick periods that the CPU - remained in a low power state. */ - vTaskStepTick( ulCompleteTickPeriods ); -} -/*-----------------------------------------------------------*/ - -void NVIC_Handler_TMR0( void ) -{ - /* This timer is used for test purposes. Its only function is to - generate interrupts while the MCU is sleeping, so the MCU is sometimes - brought out of sleep by a means other than the tick interrupt. */ -} -/*-----------------------------------------------------------*/ - - -#endif /* configCREATE_LOW_POWER_DEMO */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/main_low_power.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/main_low_power.c deleted file mode 100644 index 26659dedf..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/main_low_power/main_low_power.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky demo - * that demonstrates tickless low power operation, and a more comprehensive - * test and demo application. The configCREATE_LOW_POWER_DEMO setting in - * FreeRTOSConfig.h is used to select between the two. See the notes on using - * configCREATE_LOW_POWER_DEMO in main.c. This file implements the low power - * version. - * - * NOTE 2: This file only contains the source code that is specific to the - * low power demo. Generic functions, such FreeRTOS hook functions, and - * functions required to configure the hardware are defined in main.c. - ****************************************************************************** - * - * main_low_power() creates one queue, and two tasks. It then starts the - * scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. It sends the value 100 to the queue every second. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() blocks on the queue, blipping (quickly - * turn on then off again) the LED each time it received the value 100 from the - * queue send task. The queue send task writes to the queue every second, so - * the LED will blip once a second. - * - * The RTOS tick is turned off when the queue send task and queue receive task - * are both in the Blocked state. - * - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 ) - -/* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) - -/*-----------------------------------------------------------*/ - -/* - * Called by main when configCREATE_LOW_POWER_DEMO is set to 1 in - * main.c. - */ -void main_low_power( void ); - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used by both tasks. */ -static QueueHandle_t xQueue = NULL; - -/* The variable that is incremented to represent each LED toggle. On the -clicker hardware the LED state is set to the value of the least significant bit -of this variable. On other hardware, where an LED is not used, the LED just -keeps a count of the number of times the LED would otherwise have been toggled. -See the comments at the top of this file for information on the expected LED -toggle rate. */ -extern volatile uint32_t ulLED; - -/*-----------------------------------------------------------*/ - -void main_low_power( void ) -{ - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the Idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details on the FreeRTOS heap - http://www.freertos.org/a00111.html. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const uint32_t ulValueToSend = 100UL; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -uint32_t ulReceivedValue; -const uint32_t ulExpectedValue = 100UL; -const TickType_t xShortDelay = pdMS_TO_TICKS( 10 ); - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == ulExpectedValue ) - { - /* Blip the LED briefly to show the demo is running, but without - leaving the LED on too long as energy is being conserved. */ - configTOGGLE_LED(); - vTaskDelay( xShortDelay ); - configTOGGLE_LED(); - - ulReceivedValue = 0U; - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/ARM_REG.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/ARM_REG.h deleted file mode 100644 index 035a10875..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/ARM_REG.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - ********************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. - ********************************************************************************** - * ARM_REG.h - * This is the header to define Cortex-M3 system control & status registers - ********************************************************************************** - * SMSC version control information (Perforce): - * - * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $ - * REVISION: $Revision: #1 $ - * DATETIME: $DateTime: 2015/12/23 15:37:58 $ - * AUTHOR: $Author: akrishnan $ - * - * Revision history (latest first): - * #xx - *********************************************************************************** - */ - -/******************************************************************************/ -/** @defgroup ARM_REG ARM_REG - * @{ - */ - -/** @file ARM_REG.h -* \brief ARM Cortex-M3 registers header file -* \author KBCEC Team -* -* This file contains ARM Cortex-M3 system control & status registers. -******************************************************************************/ -#ifndef ARM_REG_H_ -#define ARM_REG_H_ - -#define REG8(x) (*((volatile unsigned char *)(x))) -#define REG16(x) (*((volatile unsigned short *)(x))) -#define REG32(x) (*((volatile unsigned long *)(x))) - -/* NVIC Registers */ -#define NVIC_INT_TYPE REG32(0xE000E004) -#define NVIC_AUX_ACTLR REG32(0xE000E008) - #define WR_BUF_DISABLE (1 << 1) -#define NVIC_ST_CTRL REG32(0xE000E010) - #define ST_ENABLE (1 << 0) - #define ST_TICKINT (1 << 1) - #define ST_CLKSOURCE (1 << 2) - #define ST_COUNTFLAG (1 << 3) -#define NVIC_ST_RELOAD REG32(0xE000E014) -#define NVIC_ST_CURRENT REG32(0xE000E018) -#define NVIC_ST_CALIB REG32(0xE000E01C) -#define NVIC_ENABLE0 REG32(0xE000E100) -#define NVIC_ENABLE1 REG32(0xE000E104) -#define NVIC_ENABLE2 REG32(0xE000E108) -#define NVIC_ENABLE3 REG32(0xE000E10C) -#define NVIC_ENABLE4 REG32(0xE000E110) -#define NVIC_ENABLE5 REG32(0xE000E114) -#define NVIC_ENABLE6 REG32(0xE000E118) -#define NVIC_ENABLE7 REG32(0xE000E11C) -#define NVIC_DISABLE0 REG32(0xE000E180) -#define NVIC_DISABLE1 REG32(0xE000E184) -#define NVIC_DISABLE2 REG32(0xE000E188) -#define NVIC_DISABLE3 REG32(0xE000E18C) -#define NVIC_DISABLE4 REG32(0xE000E190) -#define NVIC_DISABLE5 REG32(0xE000E194) -#define NVIC_DISABLE6 REG32(0xE000E198) -#define NVIC_DISABLE7 REG32(0xE000E19C) -#define NVIC_PEND0 REG32(0xE000E200) -#define NVIC_PEND1 REG32(0xE000E204) -#define NVIC_PEND2 REG32(0xE000E208) -#define NVIC_PEND3 REG32(0xE000E20C) -#define NVIC_PEND4 REG32(0xE000E210) -#define NVIC_PEND5 REG32(0xE000E214) -#define NVIC_PEND6 REG32(0xE000E218) -#define NVIC_PEND7 REG32(0xE000E21C) -#define NVIC_UNPEND0 REG32(0xE000E280) -#define NVIC_UNPEND1 REG32(0xE000E284) -#define NVIC_UNPEND2 REG32(0xE000E288) -#define NVIC_UNPEND3 REG32(0xE000E28C) -#define NVIC_UNPEND4 REG32(0xE000E290) -#define NVIC_UNPEND5 REG32(0xE000E294) -#define NVIC_UNPEND6 REG32(0xE000E298) -#define NVIC_UNPEND7 REG32(0xE000E29C) -#define NVIC_ACTIVE0 REG32(0xE000E300) -#define NVIC_ACTIVE1 REG32(0xE000E304) -#define NVIC_ACTIVE2 REG32(0xE000E308) -#define NVIC_ACTIVE3 REG32(0xE000E30C) -#define NVIC_ACTIVE4 REG32(0xE000E310) -#define NVIC_ACTIVE5 REG32(0xE000E314) -#define NVIC_ACTIVE6 REG32(0xE000E318) -#define NVIC_ACTIVE7 REG32(0xE000E31C) -#define NVIC_PRI0 REG32(0xE000E400) -#define NVIC_PRI1 REG32(0xE000E404) -#define NVIC_PRI2 REG32(0xE000E408) -#define NVIC_PRI3 REG32(0xE000E40C) -#define NVIC_PRI4 REG32(0xE000E410) -#define NVIC_PRI5 REG32(0xE000E414) -#define NVIC_PRI6 REG32(0xE000E418) -#define NVIC_PRI7 REG32(0xE000E41C) -#define NVIC_PRI8 REG32(0xE000E420) -#define NVIC_PRI9 REG32(0xE000E424) -#define NVIC_PRI10 REG32(0xE000E428) -#define NVIC_PRI11 REG32(0xE000E42C) -#define NVIC_PRI12 REG32(0xE000E430) -#define NVIC_PRI13 REG32(0xE000E434) -#define NVIC_PRI14 REG32(0xE000E438) -#define NVIC_PRI15 REG32(0xE000E43C) -#define NVIC_PRI16 REG32(0xE000E440) -#define NVIC_PRI17 REG32(0xE000E444) -#define NVIC_PRI18 REG32(0xE000E448) -#define NVIC_PRI19 REG32(0xE000E44C) -#define NVIC_PRI20 REG32(0xE000E450) -#define NVIC_PRI21 REG32(0xE000E454) -#define NVIC_PRI22 REG32(0xE000E458) -#define NVIC_PRI23 REG32(0xE000E45C) -#define NVIC_PRI24 REG32(0xE000E460) -#define NVIC_PRI25 REG32(0xE000E464) -#define NVIC_PRI26 REG32(0xE000E468) -#define NVIC_PRI27 REG32(0xE000E46C) -#define NVIC_PRI28 REG32(0xE000E470) -#define NVIC_PRI29 REG32(0xE000E474) -#define NVIC_PRI30 REG32(0xE000E478) -#define NVIC_PRI31 REG32(0xE000E47C) -#define NVIC_PRI32 REG32(0xE000E480) -#define NVIC_PRI33 REG32(0xE000E484) -#define NVIC_PRI34 REG32(0xE000E488) -#define NVIC_PRI35 REG32(0xE000E48C) -#define NVIC_PRI36 REG32(0xE000E490) -#define NVIC_PRI37 REG32(0xE000E494) -#define NVIC_PRI38 REG32(0xE000E498) -#define NVIC_PRI39 REG32(0xE000E49C) -#define NVIC_PRI40 REG32(0xE000E4A0) -#define NVIC_PRI41 REG32(0xE000E4A4) -#define NVIC_PRI42 REG32(0xE000E4A8) -#define NVIC_PRI43 REG32(0xE000E4AC) -#define NVIC_PRI44 REG32(0xE000E4B0) -#define NVIC_PRI45 REG32(0xE000E4B4) -#define NVIC_PRI46 REG32(0xE000E4B8) -#define NVIC_PRI47 REG32(0xE000E4BC) -#define NVIC_PRI48 REG32(0xE000E4C0) -#define NVIC_PRI49 REG32(0xE000E4C4) -#define NVIC_PRI50 REG32(0xE000E4C8) -#define NVIC_PRI51 REG32(0xE000E4CC) -#define NVIC_PRI52 REG32(0xE000E4D0) -#define NVIC_PRI53 REG32(0xE000E4D4) -#define NVIC_PRI54 REG32(0xE000E4D8) -#define NVIC_PRI55 REG32(0xE000E4DC) -#define NVIC_PRI56 REG32(0xE000E4E0) -#define NVIC_PRI57 REG32(0xE000E4E4) -#define NVIC_PRI58 REG32(0xE000E4E8) -#define NVIC_PRI59 REG32(0xE000E4EC) -#define NVIC_CPUID REG32(0xE000ED00) -#define NVIC_INT_CTRL REG32(0xE000ED04) -#define NVIC_VECT_TABLE REG32(0xE000ED08) -#define NVIC_AP_INT_RST REG32(0xE000ED0C) -#define NVIC_SYS_CTRL REG32(0xE000ED10) -#define NVIC_CFG_CTRL REG32(0xE000ED14) -#define NVIC_SYS_H_PRI1 REG32(0xE000ED18) -#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C) -#define NVIC_SYS_H_PRI3 REG32(0xE000ED20) -#define NVIC_SYS_H_CTRL REG32(0xE000ED24) -#define NVIC_FAULT_STA REG32(0xE000ED28) -#define NVIC_HARD_F_STA REG32(0xE000ED2C) -#define NVIC_DBG_F_STA REG32(0xE000ED30) -#define NVIC_MM_F_ADR REG32(0xE000ED34) -#define NVIC_BUS_F_ADR REG32(0xE000ED38) -#define NVIC_SW_TRIG REG32(0xE000EF00) - -/* MPU Registers */ -#define MPU_TYPE REG32(0xE000ED90) -#define MPU_CTRL REG32(0xE000ED94) -#define MPU_RG_NUM REG32(0xE000ED98) -#define MPU_RG_ADDR REG32(0xE000ED9C) -#define MPU_RG_AT_SZ REG32(0xE000EDA0) - - -#endif /* #ifndef ARM_REG_H_ */ - -/** @} - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/CEC1302_crypto_api.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/CEC1302_crypto_api.h deleted file mode 100644 index d62569240..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/CEC1302_crypto_api.h +++ /dev/null @@ -1,691 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -*****************************************************************************/ - - - -#ifndef INCLUDE_CEC1302_CRYPTO_API_H_ -#define INCLUDE_CEC1302_CRYPTO_API_H_ - -#include -#include -#ifdef __cplusplus -extern "C" { -#endif - -/* Misc. */ - -/* RNG */ -/** - * \rng_power - * - * \param [in] pwr_on Power On? - * \return none - * - * \details Gate clocks on/off to NDRNG block - */ -extern void -rng_power(bool pwr_on); - - -/** - * \rng_reset - * - * \return Reset NDRNG block - * - * \details - */ -extern void -rng_reset(void); - - -/** - * \rng_mode - * - * \param [in] mode tmode_pseudo 0(asynchronous/true random mode), - * Non-zero(pseudo-random mode) - * \return None - * - * \details Set NDRNG random number generation mode - */ -extern void -rng_mode(uint8_t mode); - - -/** - * \rng_is_on - * - * \return is NDRNG Block powered on? True if yes, false otherwise - * - * \details Check if NDRNG block is powered on. - */ -extern bool -rng_is_on(void); - - -/** - * \rng_start - * - * \return None - * - * \details Start NDRNG engine - */ -extern void -rng_start(void); - -/** - * \rng_stop - * - * \return Void - * - * \details Stop NDRNG engine - */ -extern void -rng_stop(void); - - -/** - * \rng_get_fifo_level - * - * \return actual number of 32-bit words in the NDRNG FIFO. - * - * \details return the number of 32-bit words of random data - * currently in the FIFO. - */ -extern uint32_t -rng_get_fifo_level(void); - - -/** - * \rng_get_bytes - * - * \param [in] pbuff Output Buffer - * \param [in] nbytes Number of bytes to be read - * \return Number of bytes retrieved - * - * \details read bytes from the NDRNG FIFO - */ -extern uint32_t -rng_get_bytes(uint8_t* pbuff, uint32_t nbytes); - - -/** - * \rng_get_words - * - * \param [in] pwords Pointer to output buffer - * \param [in] nwords Number of words to read - * \return actual number of words read - * - * \details Details - */ -extern uint32_t -rng_get_words(uint32_t* pwords, uint32_t nwords); - - -/* AES */ -/** - * \aes_hash_power - * - * \param [in] pwr_on Gate/Ungate clocks to block - * \return None - * - * \details Enable/Disable AES and HASH H/W Block - */ -extern void -aes_hash_power(uint8_t pwr_on); - -/** - * \aes_hash_reset - * - * \return None - * - * \details Stop AES and HASH - */ -extern void -aes_hash_reset(void); - -/** - * \aes_busy - * - * \return Is AES Block Running? True if yes, false Otherwise. - * - * \details Is AES Block Running? - */ -extern bool -aes_busy(void); - - -/** - * \aes_status - * - * \return Status of AES Block - * - * \details Returns the Status of AES Block - */ -extern uint32_t -aes_status(void); - -/** - * \aes_done_status - * - * \param [in] hw_status Pointer to where the status value will be updated - * \return True if done, false otherwise - * - * \details Returns the done status of AES block - */ -extern bool -aes_done_status(uint32_t* hw_status); - -/** - * \aes_stop - * - * \return Return aes_busy() Status - * - * \details Stop AES Operations - */ -extern bool -aes_stop(void); - -/** - * \aes_start - * - * \param [in] ien Enable interrupts? - * \return None - * - * \details Start AES block with or without interrupts - */ -extern void -aes_start(bool ien); - -/** - * \aes_iclr - * - * \return Status of the AES Block - * - * \details Clears AES Hash Interrupts - */ -extern uint32_t -aes_iclr(void); - - -/** - * \brief Brief - * - * \param [in] pkey Aligned buffer with AES Key - * \param [in] piv Aligned buffer with AES initialization - * \param [in] key_len AES_KEYLEN_128, AES_KEYLEN_192, AES_KEYLEN_256 - * \param [in] msbf Most Significant Byte order first? - * \return AES_ERR_BAD_POINTER, AES_ERR_BAD_KEY_LEN, AES_OK - * - * \details Load AES Accelerator with key and optional Initialization vector - */ -extern uint8_t -aes_set_key(const uint32_t* pkey, - const uint32_t* piv, - uint8_t key_len, bool msbf); - -/** - * \aes_crypt - * - * \param [in] data_in Aligned input data Buffer - * \param [in] data_out Aligned output data buffer - * \param [in] num_128bit_blocks Size of input in 16-byte blocks - * \param [in] mode AES Encryption/Decryption Mode - * \return AES_OK, AES_ERR_BAD_POINTER, - * - * \details Program specified AES Operation using currently programmed key - */ -extern uint8_t -aes_crypt(const uint32_t* data_in, - uint32_t* data_out, - uint32_t num_128bit_blocks, uint8_t mode); - - -/* SHA */ -#define SHA1_BLEN (20u) -#define SHA1_WLEN (5u) -#define SHA2_BLEN (32u) -#define SHA2_WLEN (8u) -#define SHA12_BLOCK_BLEN (64u) -#define SHA12_BLOCK_WLEN (16u) -#define SHA3_BLEN (48u) -#define SHA3_WLEN (12u) -#define SHA5_BLEN (64u) -#define SHA5_WLEN (16u) - -/* return values */ -#define SHA_RET_OK (0) /* OK */ -#define SHA_RET_START (1) /* OK, SHA Engine started */ -#define SHA_RET_ERROR (0x80) /* b[7]==1 indicates an error */ -#define SHA_RET_ERR_BUSY (0x80) -#define SHA_RET_ERR_BAD_ADDR (0x81) -#define SHA_RET_ERR_TIMEOUT (0x82) -#define SHA_RET_ERR_MAX_LEN (0x83) -#define SHA_RET_ERR_UNSUPPORTED (0x84) - -#define SHA_MODE_MD5 (0) // Not supported by HW -#define SHA_MODE_1 (1) -#define SHA_MODE_224 (2) // Not supported by HW -#define SHA_MODE_256 (3) -#define SHA_MODE_384 (4) // Not supported by HW -#define SHA_MODE_512 (5) // Not supported by HW - -#define HASH_START_IEN (1u) -#define HASH_START_NOIEN (0u) - -typedef union { - uint32_t w[SHA2_WLEN]; - uint8_t b[SHA2_BLEN]; -} SHA12_DIGEST_U; - - -/* - * !!! SHA-1 & SHA-256 - * HW Engine requires alignment >= 4-byte boundary !!! - */ -typedef struct sha12_context_s SHA12_CONTEXT_T; -struct sha12_context_s { - SHA12_DIGEST_U hash; - union { - uint32_t w[(SHA12_BLOCK_WLEN) * 2]; - uint8_t b[(SHA12_BLOCK_BLEN) * 2]; - } block; - uint8_t mode; - uint8_t block_len; - uint8_t rsvd[2]; - uint32_t total_msg_len; -}; - - -/** - * \hash_busy - * - * \return is busy? True if yes, Flase other wise - * - * \details returns the busy status of Hash Block - */ -extern bool hash_busy(void); - -/** - * \hash_start - * - * \param [in] ien enable/disable interrupts - * \return None - * - * \details start hash block - */ -extern void -hash_start(bool ien); - -/** - * \hash_done_status - * - * \param [in] hw_status Hash Status Register Value - * \return true if done, false otherwise - * - * \details reflects the done status of HASH black and updates - * status regsiter value into the input variable - */ -extern bool -hash_done_status(uint32_t* hw_status); - -/** - * \sha12_init - * - * \param [in] psha12_ctx Data Structure for Input data and Output Digest - * \param [in] mode SHA_MODE_1 or SHA_MODE_256 - * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_UNSPPORTED ,SHA_RET_OK - * - * \details Initializes the Data structure provided - */ -extern uint8_t -sha12_init(SHA12_CONTEXT_T* psha12_ctx, uint8_t mode); - -/** - * \sha12_update - * - * \param [in] psha12_ctx Data Structure for Input data and Output Digest - * \param [in] pdata Input Data to Hash Block - * \param [in] num_bytes Byte length of input data - * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY, SHA_RET_ERR_MAX_LEN, SHA_RET_OK - * - * \details Run hash block on data and if data greater than block size, put remaining bytes back into the data structure - */ -extern uint8_t -sha12_update(SHA12_CONTEXT_T* psha12_ctx, - const uint32_t* pdata, uint32_t num_bytes); - -/** - * \sha12_finalize - * - * \param [in] psha12_ctx Data Structure for Input data and Output Digest - * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START - * - * \details Apply FIPS padding to SHA256 and perform final hash calculation. - */ -extern uint8_t -sha12_finalize(SHA12_CONTEXT_T* psha12_ctx); - -/** - * \sha256_pad_fill - * - * \param [in] pblock64 Aligned Memory buffer of atleast 64 bytes - * \param [in] msg_byte_len Length of Message in bytes - * \return None - * - * \details Zero and fill a 64-byte SHA256 pad block with FIP padding values - */ -extern void -sha256_pad_fill(uint32_t* pblock64, uint32_t msg_byte_len); - - -/** - * \sha256_raw - * - * \param [in] pdata Input Message - * \param [in] pdigest Pointer to biffer where digest will be written - * \param [in] num64byte_blocks size of input data in blocks - * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START - * - * \details Calculate SHA256 on data - */ -extern uint8_t -sha256_raw(uint32_t* pdata, uint32_t* pdigest, uint32_t num64byte_blocks); - -/** - * \sha256_raw_init - * - * \param [in] psha256_digest Pointer to buffer where digest will be written - * \return None - * - * \details Initialize the SHA256 Digest data block - */ -extern void -sha256_raw_init(uint32_t* psha256_digest); - -/** - * \sha256_raw_update - * - * \param [in] pdata Message on which HASH block is to be called - * \param [in] pdigest Pointer to where the digest will be stored - * \param [in] num64byte_blocks size of input data in blocks - * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START - * - * \details run Hash block on data - */ -extern uint8_t -sha256_raw_update(uint32_t* pdata, - uint32_t* pdigest, uint32_t num64byte_blocks); - -/** - * \hash_iclr - * - * \return Hash Block status - * - * \details Clear Hash Interrupt - */ -extern uint32_t -hash_iclr(void); - - -/** - * \sha_init - * - * \param [in] mode SHA_MODE_1, SHA_MODE_256, SHA_MODE_512 - * \param [in] pdigest Address where digest will be stored - * \return * 0 = Success - * 1 = Hash Engine busy - * 2 = Unsupported SHA operation - * 3 = Bad digest pointer, NULL or mis-aligned. - * \details Initialize Hash engine for SHA operation. - * Programs supported SHA operation's initial value, digest address, - * and operation - */ -extern uint8_t -sha_init(uint8_t mode, uint32_t* pdigest); - - -/** - * \sha_update - * - * \param [in] pdata Input Data - * \param [in] nblocks Size in blocks - * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start? - * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned - * - * \details Run Hash block on data - */ -extern uint8_t -sha_update(uint32_t* pdata, uint16_t nblocks, uint8_t flags); - - -/** - * \sha_final - * - * \param [in] padbuf Buffer for padding (Twice block size) - * \param [in] total_msg_len Message length in bytes - * \param [in] prem Parameter_Description - * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start? - * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned - * - * \details Run final SHA Calculations and add padding - */ -extern uint8_t -sha_final(uint32_t* padbuf, uint32_t total_msg_len, - const uint8_t* prem, uint8_t flags); - - -/* PKE Miscellaneous */ - -#define PKE_RET_STARTED (0) -#define PKE_RET_OK (0) -#define PKE_RET_ERR_BUSY (1) -#define PKE_RET_ERR_BAD_PARAM (2) -#define PKE_RET_ERR_BAD_ADDR (3) -#define PKE_RET_ERR_UNKNOWN_OP (4) -#define PKE_RET_ERR_INVALID_BIT_LENGTH (5) -#define PKE_RET_ERR_INVALID_MSG_LENGTH (6) - - -/** - * \pke_power - * - * \param [in] pwr_on power on? - * \return None - * - * \details Gate or Ungate power to PKE block - */ -extern void -pke_power(bool pwr_on); - - -/** - * \brief pke_reset - * - * \return None - * - * \details Reset PKE Block - */ -extern void -pke_reset(void); - -/** - * \pke_status - * - * \return Return PKE Status register value - * - * \details Details - */ -extern uint32_t -pke_status(void); - -/** - * \pke_done_status - * - * \param [in] hw_status POinter where PKE Status is updated - * \return True if done, false otherwise - * - * \details Returns the done status of PKE block - */ -extern bool -pke_done_status(uint32_t* hw_status); - -/** - * \pke_start - * - * \param [in] ien Interrupt Enable? - * \return None - * - * \details Start PKE Block - */ -extern void -pke_start(bool ien); - - -/** - * \pke_busy - * - * \return Busy? True if busy, false otherwise - * - * \details Details - */ -extern bool -pke_busy(void); - - -/** - * \pke_clear_scm - * - * \return None - * - * \details Clear the Shared Crypto memory - */ -extern void -pke_clear_scm(void); - -/** - * \pke_scm_clear_slot - * - * \param [in] slot_num Slot number in Shared Crypto Memory - * \return None - * - * \details Clear the specified slot in Shared Crypto Memory - */ -extern void -pke_scm_clear_slot(uint8_t slot_num); - -/** - * \pke_read_scm - * - * \param [in] dest Pointer to where the data is to be read - * \param [in] nbytes Number of bytes to be read - * \param [in] slot_num Slot number from which data is to be read - * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise - * \return Number of bytes Read - * - * \details Read data from specified slot number in Shared Crypto memory - */ -extern uint16_t -pke_read_scm(uint8_t* dest, uint16_t nbytes, - uint8_t slot_num, bool reverse_byte_order); - - -/** - * \pke_write_scm - * - * \param [in] pdata Data to be written - * \param [in] num_bytes Number of bytes to be written - * \param [in] slot_num Slot number to which data ought to be written - * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise - * \return None - * - * \details Write data provided to specified slot in Shared Crypto Memory - */ -extern void -pke_write_scm(const void* pdata, uint16_t num_bytes, - uint8_t slot_num, uint8_t reverse_byte_order); - -/* PKE RSA */ - -/** - * \ rsa_load_key - * - * \param [in] rsa_bit_len 1024, 2048 - * \param [in] private_exponent Pointer to private exponent - * \param [in] public_modulus Pointer to Public modulus - * \param [in] public_exponent Pointer to Public Exponent - * \param [in] public_exponent_byte_len Length in bytes of Public Exponent - * \param [in] msbf Reverse Byte order? True if yes, false otherwise - * \return PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK - * - * \details Load RSA keys into Crypto memory - */ -extern uint8_t -rsa_load_key(uint16_t rsa_bit_len, - const uint8_t* private_exponent, - const uint8_t* public_modulus, - const uint8_t* public_exponent, - uint16_t public_exponent_byte_len, - bool msbf); - - -/** - * \ rsa_encrypt - * - * \param [in] rsa_bit_len 1024, 2048 - * \param [in] mesg Message to be encrypted - * \param [in] mlen length of message - * \param [in] flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting) - * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK - * - * \details Encrypt provided message. Load Keys before this function is called - */ -extern uint8_t -rsa_encrypt(uint16_t rsa_bit_len, - const uint8_t* mesg, - uint16_t mlen, - uint8_t flags); - - - -/** - * \ rsa_decrypt - * - * \param [in] rsa_bit_len 1024, 2048 - * \param [in] encrypted_mesg Encrypted data - * \param [in] mlen length of encrypted message - * \param [in] flags flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting) - * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK - * - * \details Perform decryption on provided encrypted message. load keys before calling this function - */ -extern uint8_t -rsa_decrypt(uint16_t rsa_bit_len, - const uint8_t* encrypted_mesg, - uint16_t mlen, - uint8_t flags); - - - -#ifdef __cplusplus -} -#endif - - -#endif /* INCLUDE_CEC1302_CRYPTO_API_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/MCHP_CEC1302.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/MCHP_CEC1302.h deleted file mode 100644 index b451de0f6..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/MCHP_CEC1302.h +++ /dev/null @@ -1,5745 +0,0 @@ - -/****************************************************************************************************//** - * @file MCHP_CEC1302.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * MCHP_CEC1302 from Microchip Technology Inc.. - * - * @version V1.1 - * @date 6. November 2015 - * - * @note Generated with SVDConv V2.87e - * from CMSIS SVD File 'MCHP_CEC1302.svd' Version 1.1, - * - * @par ARM Limited (ARM) is supplying this software for use with Cortex-M processor based - * microcontroller, but can be equally used for other suitable processor architectures. - * This file can be freely distributed. Modifications to this file shall be clearly marked. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - *******************************************************************************************************/ - - - -/** @addtogroup Microchip Technology Inc. - * @{ - */ - -/** @addtogroup MCHP_CEC1302 - * @{ - */ - -#ifndef MCHP_CEC1302_H -#define MCHP_CEC1302_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ------------------- MCHP_CEC1302 Specific Interrupt Numbers ------------------ */ - I2C0_IRQn = 0, /*!< 0 I2C0 / SMB0 Interrupt ................. Also see GIRQ 12.0 */ - I2C1_IRQn = 1, /*!< 1 I2C1 / SMB1 Interrupt ................. Also see GIRQ 12.1 */ - I2C2_IRQn = 2, /*!< 2 I2C2 / SMB2 Interrupt ................. Also see GIRQ 12.2 */ - I2C3_IRQn = 3, /*!< 3 I2C3 / SMB3 Interrupt ................. Also see GIRQ 12.3 */ - DMA0_IRQn = 4, /*!< 4 DMA_CH0 Interrupt ..................... Also see GIRQ 13.16 */ - DMA1_IRQn = 5, /*!< 5 DMA_CH1 Interrupt ..................... Also see GIRQ 13.17 */ - DMA2_IRQn = 6, /*!< 6 DMA_CH2 Interrupt ..................... Also see GIRQ 13.18 */ - DMA3_IRQn = 7, /*!< 7 DMA_CH3 Interrupt ..................... Also see GIRQ 13.19 */ - DMA4_IRQn = 8, /*!< 8 DMA_CH4 Interrupt ..................... Also see GIRQ 13.20 */ - DMA5_IRQn = 9, /*!< 9 DMA_CH5 Interrupt ..................... Also see GIRQ 13.21 */ - DMA6_IRQn = 10, /*!< 10 DMA_CH6 Interrupt ..................... Also see GIRQ 13.22 */ - DMA7_IRQn = 11, /*!< 11 DMA_CH7 Interrupt ..................... Also see GIRQ 13.23 */ - LPC_IRQn = 12, /*!< 12 LPC Interrupt ......................... Also see GIRQ 14.2 */ - UART_IRQn = 13, /*!< 13 UART Interrupt ........................ Also see GIRQ 15.0 */ - EMI_0_IRQn = 14, /*!< 14 EMI_0 (IMAP) Interrupt ................ Also see GIRQ 15.2 */ - ACPIEC0_IBF_IRQn = 15, /*!< 15 ACPIEC[0] IBF Interrupt ............... Also see GIRQ 15.6 */ - ACPIEC0_OBF_IRQn = 16, /*!< 16 ACPIEC[0] OBF Interrupt ............... Also see GIRQ 15.7 */ - ACPIEC1_IBF_IRQn = 17, /*!< 17 ACPIEC[1] IBF Interrupt ............... Also see GIRQ 15.8 */ - ACPIEC1_OBF_IRQn = 18, /*!< 18 ACPIEC[1] OBF Interrupt ............... Also see GIRQ 15.9 */ - ACPIPM1_CTL_IRQn = 19, /*!< 19 ACPIPM1_CTL Interrupt ................. Also see GIRQ 15.10 */ - ACPIPM1_EN_IRQn = 20, /*!< 20 ACPIPM1_EN Interrupt .................. Also see GIRQ 15.11 */ - ACPIPM1_STS_IRQn = 21, /*!< 21 ACPIPM1_STS Interrupt ................. Also see GIRQ 15.12 */ - KBC8042_OBF_IRQn = 22, /*!< 22 8042EM OBF Interrupt .................. Also see GIRQ 15.13 */ - KBC8042_IBF_IRQn = 23, /*!< 23 8042EM IBF Interrupt .................. Also see GIRQ 15.14 */ - MAILBOX_IRQn = 24, /*!< 24 MAILBOX Interrupt ..................... Also see GIRQ 15.15 */ - PECIHOST_IRQn = 25, /*!< 25 PECIHOST Interrupt .................... Also see GIRQ 16.3 */ - TACH_0_IRQn = 26, /*!< 26 TACH_0 Interrupt ...................... Also see GIRQ 17.0 */ - TACH_1_IRQn = 27, /*!< 27 TACH_1 Interrupt ...................... Also see GIRQ 17.1 */ - ADC_SNGL_IRQn = 28, /*!< 28 ADC_SNGL Interrupt .................... Also see GIRQ 17.10 */ - ADC_RPT_IRQn = 29, /*!< 29 ADC_RPT Interrupt ..................... Also see GIRQ 17.11 */ - ADC2PWM_N1_IRQn = 30, /*!< 30 MCHP Reserved ADC2PWM_INT_N1 .......... Also see GIRQ 17.12 */ - ADC2PWM_N2_IRQn = 31, /*!< 31 MCHP Reserved ADC2PWM_INT_N2 .......... Also see GIRQ 17.13 */ - PS2_0_IRQn = 32, /*!< 32 PS2_0 Interrupt ....................... Also see GIRQ 17.14 */ - PS2_1_IRQn = 33, /*!< 33 PS2_1 Interrupt ....................... Also see GIRQ 17.15 */ - PS2_2_IRQn = 34, /*!< 34 PS2_2 Interrupt ....................... Also see GIRQ 17.16 */ - PS2_3_IRQn = 35, /*!< 35 PS2_3 Interrupt ....................... Also see GIRQ 17.17 */ - SPI0_TX_IRQn = 36, /*!< 36 SPI0 TX Interrupt ..................... Also see GIRQ 18.0 */ - SPI0_RX_IRQn = 37, /*!< 37 SPI0 RX Interrupt ..................... Also see GIRQ 18.1 */ - HTIMER_IRQn = 38, /*!< 38 HTIMER Interrupt ...................... Also see GIRQ 17.20 */ - KEYSCAN_IRQn = 39, /*!< 39 KSC Interrupt ......................... Also see GIRQ 17.21 */ - MAILBOX_DATA_IRQn = 40, /*!< 40 MAILBOX DATA Interrupt ................ Also see GIRQ 15.16 */ - RPM_STALL_IRQn = 41, /*!< 41 RPM_INT Stall Interrupt ............... Also see GIRQ 17.23 */ - RPM_SPIN_IRQn = 42, /*!< 42 RPM_INT Spin Interrupt ................ Also see GIRQ 17.24 */ - PFR_STS_IRQn = 43, /*!< 43 PFR_STS Interrupt ..................... Also see GIRQ 17.25 */ - PWM_WDT0_IRQn = 44, /*!< 44 PWM_WDT0 Interrupt .................... Also see GIRQ 17.26 */ - PWM_WDT1_IRQn = 45, /*!< 45 PWM_WDT1 Interrupt .................... Also see GIRQ 17.27 */ - PWM_WDT2_IRQn = 46, /*!< 46 PWM_WDT2 Interrupt .................... Also see GIRQ 17.28 */ - BCM_ERR_IRQn = 47, /*!< 47 BCM_INT Err Interrupt ................. Also see GIRQ 17.29 */ - BCM_BUSY_IRQn = 48, /*!< 48 BCM_INT Busy Interrupt ................ Also see GIRQ 17.30 */ - TIMER0_IRQn = 49, /*!< 49 TIMER_16_0 Interrupt .................. Also see GIRQ 23.0 */ - TIMER1_IRQn = 50, /*!< 50 TIMER_16_1 Interrupt .................. Also see GIRQ 23.1 */ - TIMER2_IRQn = 51, /*!< 51 TIMER_16_2 Interrupt .................. Also see GIRQ 23.2 */ - TIMER3_IRQn = 52, /*!< 52 TIMER_16_3 Interrupt .................. Also see GIRQ 23.3 */ - TIMER4_IRQn = 53, /*!< 53 TIMER_32_0 Interrupt .................. Also see GIRQ 23.4 */ - TIMER5_IRQn = 54, /*!< 54 TIMER_32_1 Interrupt .................. Also see GIRQ 23.5 */ - SPI1_TX_IRQn = 55, /*!< 55 SPI1 TX Interrupt ..................... Also see GIRQ 18.2 */ - SPI1_RX_IRQn = 56, /*!< 56 SPI1 RX Interrupt ..................... Also see GIRQ 18.3 */ - GIRQ08_IRQn = 57, /*!< 57 GIRQ08 ................................ Interrupt Aggregator */ - GIRQ09_IRQn = 58, /*!< 58 GIRQ09 ................................ Interrupt Aggregator */ - GIRQ10_IRQn = 59, /*!< 59 GIRQ10 ................................ Interrupt Aggregator */ - GIRQ11_IRQn = 60, /*!< 60 GIRQ11 ................................ Interrupt Aggregator */ - GIRQ12_IRQn = 61, /*!< 61 GIRQ12 ................................ Interrupt Aggregator */ - GIRQ13_IRQn = 62, /*!< 62 GIRQ13 ................................ Interrupt Aggregator */ - GIRQ14_IRQn = 63, /*!< 63 GIRQ14 ................................ Interrupt Aggregator */ - GIRQ15_IRQn = 64, /*!< 64 GIRQ15 ................................ Interrupt Aggregator */ - GIRQ16_IRQn = 65, /*!< 65 GIRQ16 ................................ Interrupt Aggregator */ - GIRQ17_IRQn = 66, /*!< 66 GIRQ17 ................................ Interrupt Aggregator */ - GIRQ18_IRQn = 67, /*!< 67 GIRQ18 ................................ Interrupt Aggregator */ - GIRQ19_IRQn = 68, /*!< 68 GIRQ19 ................................ Interrupt Aggregator */ - GIRQ20_IRQn = 69, /*!< 69 GIRQ20 ................................ Interrupt Aggregator */ - GIRQ21_IRQn = 70, /*!< 70 GIRQ21 ................................ Interrupt Aggregator */ - GIRQ22_IRQn = 71, /*!< 71 GIRQ22 ................................ Interrupt Aggregator */ - GIRQ23_IRQn = 72, /*!< 72 GIRQ23 ................................ Interrupt Aggregator */ - DMA8_IRQn = 81, /*!< 81 DMA_CH8 Interrupt ..................... Also see GIRQ 13.24 */ - DMA9_IRQn = 82, /*!< 82 DMA_CH9 Interrupt ..................... Also see GIRQ 13.25 */ - DMA10_IRQn = 83, /*!< 83 DMA_CH10 Interrupt .................... Also see GIRQ 13.26 */ - DMA11_IRQn = 84, /*!< 84 DMA_CH11 Interrupt .................... Also see GIRQ 13.27 */ - PWM_WDT3_IRQn = 85, /*!< 85 PWM_WDT3 Interrupt .................... Also see GIRQ 18.4 */ - RTC_IRQn = 91, /*!< 91 RTC Interrupt ......................... Also see GIRQ 17.18 */ - RTC_ALARM_IRQn = 92, /*!< 92 RTC ALARM Interrupt ................... Also see GIRQ 17.19 */ - MAX_IRQn -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ - -/* ================================================================================ */ -/* ================ Custom Defines (added manually) ================ */ -/* ================================================================================ */ - -/* Register Union */ -typedef union -{ - uint32_t w; - uint16_t h[2]; - uint8_t b[4]; -} REG32_U; - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - -typedef struct { - union { - __IO uint16_t CR; /*!< MEM_BAR Control [15:0] */ - - struct { - __IO uint16_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint16_t FRAME : 6; /*!< Specify a logical device frame number */ - uint16_t : 1; - __IO uint16_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - } CR_b; /*!< BitSize */ - }; - __IO uint16_t HOST_LO_ADDR; /*!< HOST_ADDRESS[15:0] */ - __IO uint16_t HOST_HI_ADDR; /*!< HOST_ADDRESS[31:16] */ -} LPC_CONFIG_MEM_BAR_Type; - -typedef struct { - __IO uint32_t SOURCE; /*!< GIRQx Source Register(R/WC) */ - __IO uint32_t ENABLE_SET; /*!< GIRQx Enable Set Register (R/WS) */ - __I uint32_t RESULT; /*!< GIRQx Result Register */ - __IO uint32_t ENABLE_CLEAR; /*!< GIRQx Enable Clear Register. */ - __I uint32_t RESERVED; -} INTR_IRQ_Type; - -typedef struct { - union { - __IO uint8_t ACTIVATE; /*!< Enable this channel for operation. */ - - struct { - __IO uint8_t EN : 1; /*!< Enable this channel for operation. */ - } ACTIVATE_b; /*!< BitSize */ - }; - __I uint8_t RESERVED1[3]; - __IO uint32_t MEM_START_ADDR; /*!< starting address for the Memory device. */ - __IO uint32_t MEM_END_ADDR; /*!< ending address for the Memory device. */ - __IO uint32_t DEVICE_ADDR; /*!< This is the Master Device address. */ - - union { - __IO uint32_t CONTROL; /*!< DMA Channel N Control */ - - struct { - __IO uint32_t RUN : 1; /*!< 1= enabled and will service transfer requests */ - __I uint32_t REQUEST : 1; /*!< 1= transfer request from the Master Device */ - __I uint32_t DONE : 1; /*!< status signal. 1=Channel is done */ - __I uint32_t STATUS : 2; /*!< 3: Error,2/1: ext/locally done,0:Disabled */ - __IO uint32_t BUSY : 1; /*!< 1=Channel is busy (FSM is not IDLE) */ - uint32_t : 2; - __IO uint32_t TX_DIRECTION: 1; /*!< direction of Transfer. 1=Memory to Device */ - __IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< device as its Hardware Flow Control master. */ - __IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< auto-increment DMA Channel Memory Address. */ - __IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< auto-increment DMA Channel Device Address. */ - __IO uint32_t LOCK : 1; /*!< lock the arbitration of Channel Arbiter */ - __IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< Disable the Hardware Flow Control. */ - __IO uint32_t TRANSFER_SIZE: 3; /*!< transfer size in Bytes of each Data Packet */ - uint32_t : 1; - __IO uint32_t TRANSFER_GO: 1; /*!< Firmware Flow Control DMA transfer. */ - __IO uint32_t TRANSFER_ABORT: 1; /*!< abort the current transfer */ - } CONTROL_b; /*!< BitSize */ - }; - - union { - __IO uint8_t INT_STATUS; /*!< DMA Channel N Interrupt Status */ - - struct { - __IO uint8_t BUS_ERROR : 1; /*!< interrupt source. 1: Error detected.(R/WC) */ - __IO uint8_t FLOW_CONTROL: 1; /*!< Intr source.1=HW Flow Ctrl is requesting */ - __IO uint8_t DONE : 1; /*!< intr source. 1= Start Address equals End */ - } INT_STATUS_b; /*!< BitSize */ - }; - __I uint8_t RESERVED2[3]; - - union { - __IO uint8_t INT_EN; /*!< DMA CHANNEL N INTERRUPT ENABLE */ - - struct { - __IO uint8_t BUS_ERROR : 1; /*!< 1=enable Interrupt:Status AMBA Bus Error. */ - __IO uint8_t FLOW_CONTROL: 1; /*!< 1=enable Interrupt:Status Flow Control Error. */ - __IO uint8_t DONE : 1; /*!< 1=enable Interrupt:Status Done. - */ - } INT_EN_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[7]; -} DMA_CH_Type; - - -/* ================================================================================ */ -/* ================ PCR ================ */ -/* ================================================================================ */ - - -/** - * @brief The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies, - clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR) - */ - -typedef struct { /*!< PCR Structure */ - __IO uint32_t CHIP_SLP_EN; /*!< Chip Sleep Enable Register. (MCHP Reserved) */ - __I uint32_t CHIP_CLK_REQ_STS; /*!< Chip Clock Required Status. (MCHP Reserved) */ - - union { - __IO uint32_t EC_SLP_EN; /*!< EC Sleep Enable Register (EC_SLP_EN) */ - - struct { - __IO uint32_t INT_SLP_EN : 1; /*!< INT Sleep Enable (INT_SLP_EN) */ - __IO uint32_t PECI_SLP_EN: 1; /*!< PECI Sleep Enable (PECI_SLP_EN) */ - __IO uint32_t TACH0_SLP_EN: 1; /*!< TACH0 Sleep Enable (TACH0_SLP_EN) */ - uint32_t : 1; - __IO uint32_t PWM0_SLP_EN: 1; /*!< PWM0 Sleep Enable (PWM0_SLP_EN) */ - __IO uint32_t PMC_SLP_EN : 1; /*!< PMC Sleep Enable (PMC_SLP_EN) */ - __IO uint32_t DMA_SLP_EN : 1; /*!< DMA Sleep Enable (DMA_SLP_EN) */ - __IO uint32_t TFDP_SLP_EN: 1; /*!< TFDP Sleep Enable (TFDP_SLP_EN) */ - __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */ - __IO uint32_t WDT_SLP_EN : 1; /*!< WDT Sleep Enable (WDT_SLP_EN) */ - __IO uint32_t SMB0_SLP_EN: 1; /*!< SMB0 Sleep Enable (SMB0_SLP_EN) */ - __IO uint32_t TACH1_SLP_EN: 1; /*!< TACH1 Sleep Enable (TACH1_SLP_EN) */ - uint32_t : 8; - __IO uint32_t PWM1_SLP_EN: 1; /*!< PWM1 Sleep Enable (PWM1_SLP_EN) */ - __IO uint32_t PWM2_SLP_EN: 1; /*!< PWM2 Sleep Enable (PWM2_SLP_EN) */ - __IO uint32_t PWM3_SLP_EN: 1; /*!< PWM3 Sleep Enable (PWM3_SLP_EN) */ - uint32_t : 6; - __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */ - __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */ - __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */ - } EC_SLP_EN_b; /*!< BitSize */ - }; - - union { - __I uint32_t EC_CLK_REQ_STS; /*!< EC Clock Required Status Registers */ - - struct { - __I uint32_t INT_CLK_REQ: 1; /*!< INT Clock Required (INT_CLK_REQ) */ - __I uint32_t PECI_CLK_REQ: 1; /*!< PECI Clock Required (PECI_CLK_REQ) */ - __I uint32_t TACH0_CLK_REQ: 1; /*!< TACH0 Clock Required (TACH0_CLK_REQ) */ - uint32_t : 1; - __I uint32_t PWM0_CLK_REQ: 1; /*!< PWM0 Clock Required (PWM0_CLK_REQ) */ - __I uint32_t PMC_CLK_REQ: 1; /*!< PMC Clock Required (PMC_CLK_REQ) */ - __I uint32_t DMA_CLK_REQ: 1; /*!< DMA Clock Required (DMA_CLK_REQ) */ - __I uint32_t TFDP_CLK_REQ: 1; /*!< TFDP Clock Required (TFDP_CLK_REQ) */ - __I uint32_t PROCESSOR_CLK_REQ: 1; /*!< PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */ - __I uint32_t WDT_CLK_REQ: 1; /*!< WDT Clock Required (WDT_CLK_REQ) */ - __I uint32_t SMB0_CLK_REQ: 1; /*!< SMB0 Clock Required (SMB0_CLK_REQ) */ - __I uint32_t TACH1_CLK_REQ: 1; /*!< TACH1 Clock Required (TACH1_CLK_REQ) */ - uint32_t : 8; - __I uint32_t PWM1_CLK_REQ: 1; /*!< PWM1 Clock Required (PWM1_CLK_REQ) */ - __I uint32_t PWM2_CLK_REQ: 1; /*!< PWM2 Clock Required (PWM2_CLK_REQ) */ - __I uint32_t PWM3_CLK_REQ: 1; /*!< PWM3 Clock Required (PWM3_CLK_REQ) */ - uint32_t : 6; - __I uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */ - __I uint32_t TIMER16_0_CLK_REQ: 1; /*!< TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */ - __I uint32_t TIMER16_1_CLK_REQ: 1; /*!< TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */ - } EC_CLK_REQ_STS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HOST_SLP_EN; /*!< Host Sleep Enable Register (HOST_SLP_EN) */ - - struct { - __IO uint32_t LPC_SLP_EN : 1; /*!< LPC Sleep Enable (LPC_SLP_EN) */ - __IO uint32_t UART_0_SLP_EN: 1; /*!< UART 0 Sleep Enable (UART_0_SLP_EN) */ - uint32_t : 10; - __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< GLBL_CFG (GLBL_CFG_SLP_EN) */ - __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */ - __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */ - __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */ - __IO uint32_t KBCEM_SLP_EN: 1; /*!< 8042EM Sleep Enable (8042EM_SLP_EN) */ - uint32_t : 1; - __IO uint32_t RTC_SLP_EN : 1; /*!< RTC Sleep Enable (RTC_SLP_EN) */ - } HOST_SLP_EN_b; /*!< BitSize */ - }; - - union { - __I uint32_t HOST_CLK_REQ; /*!< Host Clock Required Status Registers */ - - struct { - __I uint32_t LPC_CLK_REQ: 1; /*!< LPC Clock Required (LPC_CLK_REQ) */ - __I uint32_t UART_0_CLK_REQ: 1; /*!< UART 0 Clock Required (UART_0_CLK_REQ) */ - uint32_t : 10; - __I uint32_t GLBL_CFG_CLK_REQ: 1; /*!< GLBL_CFG Clock Required (GLBL_CFG_CLK_REQ) */ - __I uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */ - __I uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */ - __I uint32_t ACPI_PM1_CLK_REQ: 1; /*!< ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */ - __I uint32_t KBCEM_CLK_REQ: 1; /*!< 8042EM Clock Required (8042EM_CLK_REQ) */ - uint32_t : 1; - __I uint32_t RTC_CLK_REQ: 1; /*!< RTC Clock Required (RTC_CLK_REQ) */ - } HOST_CLK_REQ_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SYS_SLP_CNTRL; /*!< System Sleep Control Register */ - - struct { - __IO uint32_t ROSC_PD : 1; /*!< Ring oscillator power down (ROSC_PD) */ - __IO uint32_t ROSC_GATE : 1; /*!< Ring oscillator output gate (ROSC_GATE) */ - __IO uint32_t REGULATOR_STDBY: 1; /*!< Core regulator standby */ - } SYS_SLP_CNTRL_b; /*!< BitSize */ - }; - __I uint32_t RESERVED; - __IO uint32_t PROC_CLK_CNTRL; /*!< Processor Clock Control Register (PROC_CLK_CNTRL) [7:0] Processor - Clock Divide Value (PROC_DIV) - 1: divide 48 MHz Ring Oscillator by 1. - 4: divide 48 MHz Ring Oscillator by 4.(default) - 16: divide 48 MHz Ring Oscillator by 16. - 48: divide 48 MHz Ring Oscillator by 48. - No other values are supported - --------------------------------------------------------- */ - - union { - __IO uint32_t EC_SLP_EN2; /*!< EC Sleep Enable 2 Register (EC_SLP_EN2) */ - - struct { - uint32_t : 3; - __IO uint32_t ADC_SLP_EN : 1; /*!< ADC Sleep Enable (ADC_SLP_EN) */ - uint32_t : 1; - __IO uint32_t PS2_0_SLP_EN: 1; /*!< PS2_0 Sleep Enable (PS2_0_SLP_EN) */ - __IO uint32_t PS2_1_SLP_EN: 1; /*!< PS2_1 Sleep Enable (PS2_1_SLP_EN) */ - __IO uint32_t PS2_2_SLP_EN: 1; /*!< PS2_2 Sleep Enable (PS2_2_SLP_EN) */ - __IO uint32_t PS2_3_SLP_EN: 1; /*!< PS2_3 Sleep Enable (PS2_3_SLP_EN) */ - __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Sleep Enable (SPI0_SLP_EN) */ - __IO uint32_t HTIMER_SLP_EN: 1; /*!< HTIMER Sleep Enable (HTIMER_SLP_EN) */ - __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */ - __IO uint32_t RPMPWM_SLP_EN: 1; /*!< RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */ - __IO uint32_t SMB1_SLP_EN: 1; /*!< SMB1 Sleep Enable (SMB1_SLP_EN) */ - __IO uint32_t SMB2_SLP_EN: 1; /*!< SMB2 Sleep Enable (SMB2_SLP_EN) */ - __IO uint32_t SMB3_SLP_EN: 1; /*!< SMB3 Sleep Enable (SMB3_SLP_EN) */ - __IO uint32_t LED0_SLP_EN: 1; /*!< LED0 Sleep Enable (LED0_SLP_EN) */ - __IO uint32_t LED1_SLP_EN: 1; /*!< LED1 Sleep Enable (LED1_SLP_EN) */ - __IO uint32_t LED2_SLP_EN: 1; /*!< LED2 Sleep Enable (LED2_SLP_EN) */ - __IO uint32_t BCM_SLP_EN : 1; /*!< BCM Sleep Enable (BCM_SLP_EN) */ - __IO uint32_t SPI1_SLP_EN: 1; /*!< SPI1 Sleep Enable (SPI1_SLP_EN) */ - __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */ - __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */ - __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */ - __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */ - __IO uint32_t LED3_SLP_EN: 1; /*!< LED3 Sleep Enable (LED3_SLP_EN) */ - } EC_SLP_EN2_b; /*!< BitSize */ - }; - - union { - __I uint32_t EC_CLK_REQ2_STS; /*!< EC Clock Required 2 Status Register */ - - struct { - uint32_t : 3; - __I uint32_t ADC_CLK_REQ: 1; /*!< ADC Clock Required (ADC_CLK_REQ) */ - uint32_t : 1; - __I uint32_t PS2_0_SLP_CLK_REQ: 1; /*!< PS2_0 Clock Required (PS2_0_SLP_CLK_REQ) */ - __I uint32_t PS2_1_SLP_CLK_REQ: 1; /*!< PS2_1 Clock Required (PS2_1_SLP_CLK_REQ) */ - __I uint32_t PS2_2_SLP_CLK_REQ: 1; /*!< PS2_2 Clock Required (PS2_2_SLP_CLK_REQ) */ - __I uint32_t PS2_3_SLP_CLK_REQ: 1; /*!< PS2_3 Clock Required (PS2_3_SLP_CLK_REQ) */ - __I uint32_t SPI0_SLP_CLK_REQ: 1; /*!< SPI0 Clock Required (SPI0_SLP_CLK_REQ) */ - __I uint32_t HTIMER_SLP_CLK_REQ: 1; /*!< HTIMER Clock Required (HTIMER_SLP_CLK_REQ) */ - __I uint32_t KEYSCAN_SLP_CLK_REQ: 1; /*!< KEYSCAN Clock Required (KEYSCAN_SLP_CLK_REQ) */ - __I uint32_t RPMPWM_SLP_CLK_REQ: 1; /*!< RPM-PWM Clock Required (RPMPWM_SLP_CLK_REQ) */ - __I uint32_t SMB1_SLP_CLK_REQ: 1; /*!< SMB1 Clock Required (SMB1_SLP_CLK_REQ) */ - __I uint32_t SMB2_SLP_CLK_REQ: 1; /*!< SMB2 Clock Required (SMB2_SLP_CLK_REQ) */ - __I uint32_t SMB3_SLP_CLK_REQ: 1; /*!< SMB3 Clock Required (SMB3_SLP_CLK_REQ) */ - __I uint32_t LED0_SLP_CLK_REQ: 1; /*!< LED0 Clock Required (LED0_SLP_CLK_REQ) */ - __I uint32_t LED1_SLP_CLK_REQ: 1; /*!< LED1 Clock Required (LED1_SLP_CLK_REQ) */ - __I uint32_t LED2_SLP_CLK_REQ: 1; /*!< LED2 Clock Required (LED2_SLP_CLK_REQ) */ - __I uint32_t BCM_SLP_CLK_REQ: 1; /*!< BCM Clock Required (BCM_SLP_CLK_REQ) */ - __I uint32_t SPI1_SLP_CLK_REQ: 1; /*!< SPI1 Clock Required (SPI1_SLP_CLK_REQ) */ - __I uint32_t TIMER16_2_SLP_CLK_REQ: 1; /*!< TIMER16_2_Clock Required (TIMER16_2_SLP_CLK_REQ) */ - __I uint32_t TIMER16_3_SLP_CLK_REQ: 1; /*!< TIMER16_3 Clock Required (TIMER16_3_SLP_CLK_REQ) */ - __I uint32_t TIMER32_0_SLP_CLK_REQ: 1; /*!< TIMER32_0 Clock Required (TIMER32_0_SLP_CLK_REQ) */ - __I uint32_t TIMER32_1_SLP_CLK_REQ: 1; /*!< TIMER32_1 Clock Required (TIMER32_1_SLP_CLK_REQ) */ - __I uint32_t LED3_SLP_CLK_REQ: 1; /*!< LED3 Clock Required (LED3_SLP_CLK_REQ) */ - } EC_CLK_REQ2_STS_b; /*!< BitSize */ - }; - __IO uint32_t SLOW_CLK_CNTRL; /*!< Slow Clock Control Register (SLOW_CLK_CNTRL) Slow Clock (100 - kHz) Divide Value (slow_div) Configures the 100kHz_Clk. - 0: Clock off - n: divide by n. - Note: The default setting is for 100 kHz. - --------------------------------------------------------- */ - - union { - __I uint32_t CHIP_OSC_ID; /*!< Oscillator ID Register (CHIP_OSC_ID) */ - - struct { - uint32_t : 8; - __I uint32_t OSC_LOCK : 1; /*!< OSC_LOCK (OSC_LOCK) */ - } CHIP_OSC_ID_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CHIP_PWR_RST_STS; /*!< PCR chip sub-system power reset status */ - - struct { - uint32_t : 2; - __I uint32_t VCC_nRST : 1; /*!< 0=active, 1=not active (PWRGD asserted). */ - __I uint32_t SIO_nRST : 1; /*!< nSIO_RESET. 0=active, 1=not active. */ - uint32_t : 1; - __IO uint32_t VBAT_RST : 1; /*!< VBAT: 0=No reset, 1=reset occurred.(R/WC) */ - __IO uint32_t VCC1_RST : 1; /*!< VCC1: 0=No reset, 1=reset occurred.(R/WC) */ - uint32_t : 3; - __I uint32_t _32K_ACTIVE: 1; /*!< 32K_ACTIVE (32K_ACTIVE) */ - __I uint32_t PCICLK_ACTIVE: 1; /*!< PCICLK_ACTIVE (PCICLK_ACTIVE) */ - } CHIP_PWR_RST_STS_b; /*!< BitSize */ - }; - __IO uint32_t CHIP_RST_EN; /*!< Chip Reset Enable (MCHP Reserved) */ - - union { - __IO uint32_t HOST_RST_EN; /*!< Host Reset Enable Register */ - - struct { - __IO uint32_t LPC_RST_EN : 1; /*!< LPC Reset Enable (LPC_RST_EN) */ - __IO uint32_t UART_0_RST_EN: 1; /*!< UART 0 Reset Enable */ - uint32_t : 10; - __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< GLBL_CFG Reset Enable */ - __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< ACPI EC 0 Reset Enable */ - __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< ACPI EC 1 Reset Enable */ - __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< ACPI PM1 Reset Enable */ - __IO uint32_t KBCEM_RST_EN: 1; /*!< 8042EM Reset Enable */ - uint32_t : 1; - __IO uint32_t RTC_RST_EN : 1; /*!< RTC Reset Enable (RTC_RST_EN) */ - } HOST_RST_EN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t EC_RST_EN; /*!< EC Reset Enable Register */ - - struct { - __IO uint32_t INT_RST_EN : 1; /*!< INT Reset Enable (INT_RST_EN) */ - __IO uint32_t PECI_RST_EN: 1; /*!< PECI Reset Enable (PECI_RST_EN) */ - __IO uint32_t TACH0_RST_EN: 1; /*!< TACH0 Reset Enable (TACH0_RST_EN) */ - uint32_t : 1; - __IO uint32_t PWM0_RST_EN: 1; /*!< PWM0 Reset Enable (PWM0_RST_EN) */ - __IO uint32_t PMC_RST_EN : 1; /*!< PMC Reset Enable (PMC_RST_EN) */ - __IO uint32_t DMA_RST_EN : 1; /*!< DMA Reset Enable (DMA_RST_EN) */ - __IO uint32_t TFDP_RST_EN: 1; /*!< TFDP Reset Enable (TFDP_RST_EN) */ - __IO uint32_t PROCESSOR_RST_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_RST_EN) */ - __IO uint32_t WDT_RST_EN : 1; /*!< WDT Reset Enable (WDT_RST_EN) */ - __IO uint32_t SMB0_RST_EN: 1; /*!< SMB0 Reset Enable (SMB0_RST_EN) */ - __IO uint32_t TACH1_RST_EN: 1; /*!< TACH1 Reset Enable (TACH1_RST_EN) */ - uint32_t : 8; - __IO uint32_t PWM1_RST_EN: 1; /*!< PWM1 Reset Enable (PWM1_RST_EN) */ - __IO uint32_t PWM2_RST_EN: 1; /*!< PWM2 Reset Enable (PWM2_RST_EN) */ - __IO uint32_t PWM3_RST_EN: 1; /*!< PWM3 Reset Enable (PWM3_RST_EN) */ - uint32_t : 6; - __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */ - __IO uint32_t TIMER16_0_RST_EN: 1; /*!< TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */ - __IO uint32_t TIMER16_1_RST_EN: 1; /*!< TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */ - } EC_RST_EN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t EC_RST_EN2; /*!< EC Reset Enable 2 Register */ - - struct { - uint32_t : 3; - __IO uint32_t ADC_RST_EN : 1; /*!< ADC Reset Enable (ADC_RST_EN) */ - uint32_t : 1; - __IO uint32_t PS2_0_RST_EN: 1; /*!< PS2_0 Reset Enable (PS2_0_RST_EN) */ - __IO uint32_t PS2_1_RST_EN: 1; /*!< PS2_1 Reset Enable (PS2_1_RST_EN) */ - __IO uint32_t PS2_2_RST_EN: 1; /*!< PS2_2 Reset Enable (PS2_2_RST_EN) */ - __IO uint32_t PS2_3_RST_EN: 1; /*!< PS2_3 Reset Enable (PS2_3_RST_EN) */ - __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Reset Enable (SPI0_SLP_EN) */ - __IO uint32_t HTIMER_RST_EN: 1; /*!< HTIMER Reset Enable (HTIMER_RST_EN) */ - __IO uint32_t KEYSCAN_RST_EN: 1; /*!< KEYSCAN Reset Enable (KEYSCAN_RST_EN) */ - __IO uint32_t RPMPWM_RST_EN: 1; /*!< RPM-PWM Reset Enable (RPMPWM_RST_EN) */ - __IO uint32_t SMB1_RST_EN: 1; /*!< SMB1 Reset Enable (SMB1_RST_EN) */ - __IO uint32_t SMB2_RST_EN: 1; /*!< SMB2 Reset Enable (SMB2_RST_EN) */ - __IO uint32_t SMB3_RST_EN: 1; /*!< SMB3 Reset Enable (SMB3_RST_EN) */ - __IO uint32_t LED0_RST_EN: 1; /*!< LED0 Reset Enable (LED0_RST_EN) */ - __IO uint32_t LED1_RST_EN: 1; /*!< LED1 Reset Enable (LED1_RST_EN) */ - __IO uint32_t LED2_RST_EN: 1; /*!< LED2 Reset Enable (LED2_RST_EN) */ - __IO uint32_t BCM_RST_EN : 1; /*!< BCM Reset Enable (BCM_RST_EN) */ - __IO uint32_t SPI1_RST_EN: 1; /*!< SPI1 Reset Enable (SPI1_RST_EN) */ - __IO uint32_t TIMER16_2_RST_EN: 1; /*!< TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */ - __IO uint32_t TIMER16_3_RST_EN: 1; /*!< TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */ - __IO uint32_t TIMER32_0_RST_EN: 1; /*!< TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */ - __IO uint32_t TIMER32_1_RST_EN: 1; /*!< TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */ - __IO uint32_t LED3_RST_EN: 1; /*!< LED3 Reset Enable (LED3_RST_EN) */ - } EC_RST_EN2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWR_RST_CTRL; /*!< Power Reset Control (PWR_RST_CTRL) Register */ - - struct { - __IO uint32_t IRESET_OUT : 1; /*!< iRESET_OUT (IRESET_OUT) */ - } PWR_RST_CTRL_b; /*!< BitSize */ - }; -} PCR_Type; - - -/* ================================================================================ */ -/* ================ VBAT ================ */ -/* ================================================================================ */ - - -/** - * @brief The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers - required the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem. - The VBAT Powered RAM provides a 64 Byte Random Accessed Memory that is operational while the main power rail is operational, - and will retain its values powered by battery power while the main rail is unpowered. (VBAT) - */ - -typedef struct { /*!< VBAT Structure */ - - union { - __IO uint8_t PFR_STS; /*!< Power-Fail and Reset Status Register */ - - struct { - __I uint8_t DET32K_IN : 1; /*!< XTAL[1:2] 0=No clock, 1= Clock detected */ - uint8_t : 4; - __IO uint8_t WDT : 1; /*!< 1=Watch-Dog Timer Forced Reset (R/WC). */ - uint8_t : 1; - __IO uint8_t VBAT_RST : 1; /*!< 1=VBAT_POR is detected.(R/WC) */ - } PFR_STS_b; /*!< BitSize */ - }; - __I uint8_t RESERVED[7]; - - union { - __IO uint32_t CLOCK_EN; /*!< CLOCK ENABLE Control */ - - struct { - __IO uint32_t XOSEL : 1; /*!< 32KHz, 1=single-ended, 0=crystal (default). */ - __IO uint32_t _32K_EN : 1; /*!< 1=32K_ON, 0=OFF (VBAT_POR default) */ - } CLOCK_EN_b; /*!< BitSize */ - }; -} VBAT_Type; - - -/* ================================================================================ */ -/* ================ LPC ================ */ -/* ================================================================================ */ - - -/** - * @brief Section 5.10, "EC-Only Registers"and Section 5.11, "Runtime Registers". (LPC) - */ - -typedef struct { /*!< LPC Structure */ - __IO uint8_t INDEX; /*!< A pointer to a Configuration Reg. Address. */ - __IO uint8_t DATA_REG; /*!< To rd/wt data with the INDEX Register. */ - __I uint16_t RESERVED[129]; - - union { - __I uint32_t BUS_MONITOR; /*!< LPC BUS MONITOR REGISTER */ - - struct { - uint32_t : 1; - __I uint32_t LRESET_STATUS: 1; /*!< Reflects the inverse state of LRESET# pin. */ - } BUS_MONITOR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HOST_BUS_ERROR; /*!< Host Bus Error Register */ - - struct { - __IO uint32_t LPC_ERR : 1; /*!< A BAR conflict or an internal bus error. (R/WC) */ - __IO uint32_t EN_ERR : 1; /*!< Internal bus errors. (R/WC) */ - __IO uint32_t BAR_ERR : 1; /*!< a BAR conflict occurs on an LPC address. (R/WC) */ - __IO uint32_t RUNTIME_ERR: 1; /*!< A BAR is misconfigured. (R/WC) */ - __IO uint32_t CONFIG_ERR : 1; /*!< LPC Config access causes a bus error.(R/WC) */ - __IO uint32_t DMA_ERR : 1; /*!< LPC DMA access causes a bus error. (R/WC) */ - uint32_t : 2; - __I uint32_t ERR_ADDR : 24; /*!< 24-bit internal addr. of LPC transaction */ - } HOST_BUS_ERROR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t EC_SERIRQ; /*!< the interrupt source of EC SERIRQ */ - - struct { - __IO uint32_t EC_IRQ : 1; /*!< interrupt source of a LPC Logical Device */ - } EC_SERIRQ_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CLK_CTRL; /*!< Controls throughput of LPC transactions. */ - - struct { - __IO uint32_t CR : 2; /*!< controls ring oscillator to be shut down. */ - __IO uint32_t HANDSHAKE : 1; /*!< controls throughput of LPC transactions. */ - } CLK_CTRL_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1[3]; - __IO uint32_t BAR_INHIBIT; /*!< The BAR for Logical Device i is disabled */ - __I uint32_t RESERVED2[3]; - __IO uint32_t BAR_INIT; /*!< Init value of LPC BAR at offset 60h on nSIO_RESET. */ -} LPC_Type; - - -/* ================================================================================ */ -/* ================ LPC_CONFIG ================ */ -/* ================================================================================ */ - - -/** - * @brief LPC Configuration Registers. See Section 5.9 (LPC_CONFIG) - */ - -typedef struct { /*!< LPC_CONFIG Structure */ - __I uint32_t RESERVED[12]; - __IO uint8_t ACTIVATE; /*!< 1=LPC Logical Device is powered/functional */ - __I uint8_t RESERVED1[15]; - - union { - __IO uint8_t SIRQ[16]; /*!< 16 SIRQ channels */ - - struct { - __IO uint8_t FRAME : 6; /*!< Six bits select the Logical Device. */ - __IO uint8_t DEVICE : 1; /*!< Set to 0 in order to enable a SERIRQ. */ - __IO uint8_t SELECT : 1; /*!< 1: 1st LD's intr is selected,0: 2nd intr. */ - } SIRQ_b[16]; /*!< BitSize */ - }; - __I uint32_t RESERVED2[4]; - - union { - __IO uint32_t LPC_BAR; /*!< LPC Interface BAR Register */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } LPC_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t EM_BAR; /*!< EM Interface 0 BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } EM_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t UART_BAR; /*!< UART 0 BAR Register */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } UART_BAR_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3[3]; - - union { - __IO uint32_t KBC_BAR; /*!< Keyboard Controller (8042) BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } KBC_BAR_b; /*!< BitSize */ - }; - __I uint32_t RESERVED4[3]; - - union { - __IO uint32_t EC0_BAR; /*!< ACPI EC Interface 0 BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } EC0_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t EC1_BAR; /*!< ACPI EC Interface 1 BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } EC1_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PM1_BAR; /*!< ACPI PM1 Interface BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } PM1_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t LGC_BAR; /*!< Legacy (GATEA20) Interface BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } LGC_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t MBX_BAR; /*!< Mailbox Registers Interface BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } MBX_BAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTC_BAR; /*!< RTC Registers Interface BAR */ - - struct { - __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ - __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ - __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ - __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ - __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ - } RTC_BAR_b; /*!< BitSize */ - }; - __I uint32_t RESERVED5[8]; - - union { - LPC_CONFIG_MEM_BAR_Type MBX_MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */ - LPC_CONFIG_MEM_BAR_Type MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */ - }; - LPC_CONFIG_MEM_BAR_Type EC0_MEM_BAR; /*!< ACPI EC Interface 0 Memory BAR */ - LPC_CONFIG_MEM_BAR_Type EC1_MEM_BAR; /*!< ACPI EC Interface 1 Memory BAR */ - LPC_CONFIG_MEM_BAR_Type EMI_MEM_BAR; /*!< EM Interface 0 Memory BAR */ -} LPC_CONFIG_Type; - - -/* ================================================================================ */ -/* ================ GCR ================ */ -/* ================================================================================ */ - - -/** - * @brief The Logical Device Configuration registers support motherboard designs in which the resources required - by their components are known and assigned by the BIOS at POST. (GCR) - */ - -typedef struct { /*!< GCR Structure */ - __I uint8_t RESERVED[7]; - __IO uint8_t LOGICAL_DEVICE_NUMBER; /*!< Selects the current logical device. */ - __I uint32_t RESERVED1[6]; - __I uint8_t DEVICE_ID; /*!< provides device identification. */ - __I uint8_t DEVICE_REVISION; /*!< provides device revision information. */ -} GCR_Type; - - -/* ================================================================================ */ -/* ================ EMI ================ */ -/* ================================================================================ */ - - -/** - * @brief The Embedded Memory Interface (EMI) provides a standard run-time mechanism for the system host - to communicate with the Embedded Controller (EC) and other logical components. (EMI) - */ - -typedef struct { /*!< EMI Structure */ - __IO uint8_t HOST_EC_MBX; /*!< Host-to-EC Mailbox Register */ - __IO uint8_t EC_HOST_MBX; /*!< EC-to-Host Mailbox Register (R/WC) */ - - union { - __IO uint16_t EC_ADDRESS; /*!< EC Address Access Control Register */ - - struct { - __IO uint16_t ACCESS_TYPE: 2; /*!< defines the type of EC Data rd/wt access */ - __IO uint16_t EC_ADDRESS : 13; /*!< defines bits[14:2] of EC_Address [15:0]. */ - __IO uint16_t REGION : 1; /*!< Selector of two segments. */ - } EC_ADDRESS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t EC_DATA; /*!< EC Data Register */ - __IO uint8_t EC_DATA_BYTE[4]; /*!< EC Data Byte Register */ - }; - - union { - __IO uint16_t EC_SWI; /*!< Notification of EC Software Interrupt */ - - struct { - __I uint16_t EC_WR : 1; /*!< EC Mailbox Write. */ - __IO uint16_t NOTIFICATION: 15; /*!< EC to notify the host of an event(R/WC) */ - } EC_SWI_b; /*!< BitSize */ - }; - __IO uint16_t EC_SWI_EN; /*!< [15:1] enables generation of Event interrupts */ - __IO uint8_t APPLICATION_ID; /*!< Application ID Register */ - __I uint8_t RESERVED[243]; - __IO uint8_t HOST2EC_MBX; /*!< Host-to-EC Mailbox Register(R/WC) */ - __IO uint8_t EC2HOST_MBX; /*!< EC-to-Host Mailbox Register */ - __I uint16_t RESERVED1; - __IO uint32_t MEMORY_BASE_ADDRESS_0; /*!< [31:2] defines the beginning of region 0 */ - __IO uint16_t MEMORY_READ_LIMIT_0; /*!< [14:2]Memory Read Limit 0 Register */ - __IO uint16_t MEMORY_WRITE_LIMIT_0; /*!< [14:2] Memory Write Limit 0 Register */ - __IO uint32_t MEMORY_BASE_ADDRESS_1; /*!< [31:2] defines the beginning of region 1 */ - __IO uint16_t MEMORY_READ_LIMIT_1; /*!< [14:2]Memory Read Limit 1 Register */ - __IO uint16_t MEMORY_WRITE_LIMIT_1; /*!< [14:2] Memory Write Limit 1 Register */ - __IO uint16_t EC_SWI_SET; /*!< [15:1] Interrupt Set Register */ - __IO uint16_t EC_SWI_CLR; /*!< [15:1] Host Clear Enable Register */ -} EMI_Type; - - -/* ================================================================================ */ -/* ================ ACPI_EC0 ================ */ -/* ================================================================================ */ - - -/** - * @brief The ACPI Embedded Controller Interface (ACPI-ECI) provides a four byte full duplex data interface - which is a superset of the standard ACPI Embedded Controller Interface (ACPI-ECI) one byte data interface. The - ACPI Embedded Controller Interface (ACPI-ECI) defaults to the standard one byte interface. (ACPI_EC0) - */ - -typedef struct { /*!< ACPI_EC0 Structure */ - - union { - __IO uint32_t OS_DATA; /*!< ACPI OS Data Register */ - __IO uint8_t OS_DATA_BYTE[4]; /*!< aliased to the OS2EC DATA BYTES[n]. */ - }; - - union { - union { - __I uint8_t OS_STATUS; /*!< aliased to the EC STATUS Register */ - - struct { - __I uint8_t OBF : 1; /*!< Output Buffer Full bit */ - __I uint8_t IBF : 1; /*!< Input Buffer Full bit */ - __I uint8_t UD1B : 1; /*!< User Defined */ - __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */ - __I uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */ - __I uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */ - __I uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */ - __I uint8_t UD0B : 1; /*!< User Defined */ - } OS_STATUS_b; /*!< BitSize */ - }; - __O uint8_t OS_COMMAND; /*!< aliased to the OS2EC Data Byte0 */ - }; - __I uint8_t OS_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */ - __I uint16_t RESERVED[125]; - - union { - __IO uint32_t EC2OS_DATA; /*!< EC2OS Data */ - __IO uint8_t EC2OS_DATA_BYTE[4]; /*!< EC2OS Data Bytes */ - }; - - union { - __IO uint8_t EC_STATUS; /*!< EC STATUS */ - - struct { - __I uint8_t OBF : 1; /*!< Output Buffer Full bit */ - __I uint8_t IBF : 1; /*!< Input Buffer Full bit */ - __I uint8_t UD1A : 1; /*!< User Defined */ - __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */ - __IO uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */ - __IO uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */ - __IO uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */ - __IO uint8_t UD0A : 1; /*!< User Defined */ - } EC_STATUS_b; /*!< BitSize */ - }; - __IO uint8_t EC_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */ - __I uint16_t RESERVED1; - - union { - __IO uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */ - __IO uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */ - }; -} ACPI_EC0_Type; - - -/* ================================================================================ */ -/* ================ KBC ================ */ -/* ================================================================================ */ - - -/** - * @brief The CEC1302 keyboard controller uses the EC to produce a superset of the - features provided by the industry-standard 8042 keyboard controller. The 8042 Emulated - Keyboard Controller is a Host/EC Message Interface with hardware assists to emulate 8042 - behavior and provide Legacy GATEA20 support. (KBC) - */ - -typedef struct { /*!< KBC Structure */ - - union { - __O uint8_t WT_PORT60_DATA; /*!< Host_EC Data Register (=Host Write 60h) */ - __I uint8_t RD_PORT60_DATA; /*!< EC_Host Data/Aux Register (=Host Read 60h) */ - }; - __I uint8_t RESERVED[3]; - - union { - union { - __I uint8_t RD_PORT64_STATUS; /*!< Keyboard Status Register (=Host Read 64h) */ - - struct { - __I uint8_t OBF : 1; /*!< Output Buffer Full. */ - __I uint8_t IBF : 1; /*!< Input Buffer Full. */ - __I uint8_t UD0 : 1; /*!< User-defined data. */ - __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */ - __I uint8_t UD1 : 1; /*!< User-defined data. */ - __I uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */ - __I uint8_t UD2 : 2; /*!< User-defined data. */ - } RD_PORT64_STATUS_b; /*!< BitSize */ - }; - __O uint8_t WT_PORT64_CMD; /*!< Host_EC Command Register (=Host Write 64h) */ - }; - __I uint8_t RESERVED1[251]; - - union { - __O uint8_t EC_DATA; /*!< EC2Host Data Register */ - __I uint8_t HOST2EC_DATA; /*!< Host2EC Data/Cmd Register */ - }; - __I uint8_t RESERVED2[3]; - - union { - __IO uint8_t STATUS; /*!< EC KEYBOARD STATUS REGISTER */ - - struct { - __I uint8_t OBF : 1; /*!< Output Buffer Full. */ - __I uint8_t IBF : 1; /*!< Input Buffer Full. */ - __IO uint8_t UD0 : 1; /*!< User-defined data. */ - __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */ - __IO uint8_t UD1 : 1; /*!< User-defined data. */ - __IO uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */ - __IO uint8_t UD2 : 2; /*!< User-defined data. */ - } STATUS_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[3]; - - union { - __IO uint8_t CONTROL; /*!< Keyboard Control Register */ - - struct { - __IO uint8_t UD3 : 1; /*!< User-defined data. */ - __IO uint8_t SAEN : 1; /*!< Software-assist enable. */ - __IO uint8_t PCOBFEN : 1; /*!< 1=write to PCOBF, 0=writes to EC Data Reg. */ - __IO uint8_t UD4 : 2; /*!< User-defined data. */ - __IO uint8_t OBFEN : 1; /*!< 1=KIRQ is driven by PCOBF and MIRQ */ - __IO uint8_t UD5 : 1; /*!< User-defined data. */ - __IO uint8_t AUXH : 1; /*!< AUX in Hardware. */ - } CONTROL_b; /*!< BitSize */ - }; - __I uint8_t RESERVED4[3]; - __O uint8_t AUX_DATA; /*!< EC_Host Aux Register */ - __I uint8_t RESERVED5[7]; - __IO uint8_t PCOBF; /*!< [0:0] PCOBF Register */ - __I uint8_t RESERVED6[539]; - __IO uint8_t ACTIVATE; /*!< [0:0] 1=8042 I/F is powered/functional */ -} KBC_Type; - - -/* ================================================================================ */ -/* ================ PORT92 ================ */ -/* ================================================================================ */ - - -/** - * @brief The registers listed in the Configuration Register Summary table are for a - single instance of the Legacy Port92 and GATEA20 logic. (PORT92) - */ - -typedef struct { /*!< PORT92 Structure */ - - union { - __IO uint8_t PORT92; /*!< Support GATE_A20 CPU_RESET control */ - - struct { - __IO uint8_t ALT_CPU_RESET: 1; /*!< provides to generate a CPU_RESET pulse. */ - __IO uint8_t ALT_GATE_A20: 1; /*!< provides system to control GATEA20 pin. */ - } PORT92_b; /*!< BitSize */ - }; - __I uint8_t RESERVED[255]; - __IO uint8_t GATEA20; /*!< [0:0] 0=GATEA20 output low, 1=outputn high */ - __I uint8_t RESERVED1[7]; - __O uint8_t SETGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */ - __I uint8_t RESERVED2[3]; - __IO uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */ - __I uint8_t RESERVED3[547]; - __IO uint8_t PORT92_ENABLE; /*!< [0:0] 1= Port92h Register is enabled. */ -} PORT92_Type; - - -/* ================================================================================ */ -/* ================ MBX ================ */ -/* ================================================================================ */ - - -/** - * @brief The Mailbox provides a standard run-time mechanism for the host to - communicate with the Embedded Controller (EC) (MBX) - */ - -typedef struct { /*!< MBX Structure */ - __IO uint8_t INDEX; /*!< MBX_Index Register */ - __IO uint8_t DATA_REG; /*!< MBX_Data_Register */ - __I uint16_t RESERVED[127]; - __IO uint8_t HOST_TO_EC; /*!< HOST-to-EC Mailbox Register */ - __I uint8_t RESERVED1[3]; - __IO uint8_t EC_TO_HOST; /*!< EC-to-Host Mailbox Register */ - __I uint8_t RESERVED2[3]; - - union { - __IO uint8_t SMI_SOURCE; /*!< SMI Interrupt Source Register */ - - struct { - __I uint8_t EC_WR : 1; /*!< EC Mailbox Write (flag). */ - __IO uint8_t EC_SMI : 7; /*!< EC Software Interrupt source control */ - } SMI_SOURCE_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[3]; - - union { - __IO uint8_t SMI_MASK; /*!< SMI Interrupt Mask Register */ - - struct { - __IO uint8_t EC_WR_EN : 1; /*!< EC Mailbox Write Interrupt Enable. */ - __IO uint8_t EC_SMI_EN : 7; /*!< EC Software Interrupt Enable. */ - } SMI_MASK_b; /*!< BitSize */ - }; - __I uint8_t RESERVED4[3]; - __IO uint8_t REG[42]; /*!< Mailbox Register */ -} MBX_Type; - - -/* ================================================================================ */ -/* ================ PM1 ================ */ -/* ================================================================================ */ - - -/** - * @brief The CEC1302 implements the ACPI fixed registers but includes only those bits that apply to the power - button sleep button and RTC alarm events. The ACPI WAK_STS, SLP_TYP, and SLP_EN bits are also supported. (PM1) - */ - -typedef struct { /*!< PM1 Structure */ - __I uint8_t RESERVED; - - union { - __IO uint8_t STS2; /*!< PM1 Status 2 */ - - struct { - __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */ - __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */ - __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */ - __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */ - uint8_t : 3; - __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */ - } STS2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED1; - - union { - __IO uint8_t EN2; /*!< PM1 Enable 2 */ - - struct { - __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */ - } EN2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED2; - - union { - __IO uint8_t CTRL2; /*!< PM1 Control 2 */ - - struct { - uint8_t : 1; - __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */ - } CTRL2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[251]; - - union { - __IO uint8_t STS_2; /*!< PM1 Status 2 */ - - struct { - __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */ - __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */ - __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */ - __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */ - uint8_t : 3; - __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */ - } STS_2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED4; - - union { - __IO uint8_t EN_2; /*!< PM1 Enable 2 */ - - struct { - __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */ - } EN_2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED5; - - union { - __IO uint8_t CTRL_2; /*!< PM1 Control 2 */ - - struct { - uint8_t : 1; - __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */ - __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */ - } CTRL_2_b; /*!< BitSize */ - }; - __I uint16_t RESERVED6[5]; - __IO uint8_t PM_STS; /*!< [0:0]wt 1 interrupt is generated on EC_SCI# */ -} PM1_Type; - - -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ - - -/** - * @brief The 16550 UART (Universal Asynchronous Receiver/Transmitter) is a full-function - Two Pin Serial Port that supports the standard RS-232 Interface. (UART) - */ - -typedef struct { /*!< UART Structure */ - - union { - __O uint8_t TX_DATA; /*!< UART Transmit Buffer Register */ - __I uint8_t RX_DATA; /*!< UART Receive Buffer Register */ - __IO uint8_t BAUDRATE_LSB; /*!< Programmable BAUD Rate Generator (LSB) Reg. */ - }; - - union { - union { - __IO uint8_t INT_EN; /*!< UART Interrupt Enable Register */ - - struct { - __IO uint8_t ERDAI : 1; /*!< enables Received Data Available Interrupt */ - __IO uint8_t ETHREI : 1; /*!< enables Transmitter Holding Empty Interrupt */ - __IO uint8_t ELSI : 1; /*!< enables Received Line Status Interrupt */ - __IO uint8_t EMSI : 1; /*!< enables the MODEM Status Interrupt */ - } INT_EN_b; /*!< BitSize */ - }; - __IO uint8_t BAUDRATE_MSB; /*!< [6:0]BAUD_RATE_DIVISOR_MSB [7]BAUD_CLK_SEL */ - }; - - union { - union { - __I uint8_t INT_ID; /*!< UART Interrupt Identification Register */ - - struct { - __I uint8_t IPEND : 1; /*!< indicate whether an interrupt is pending. */ - __I uint8_t INTID : 3; /*!< highest priority interrupt pending */ - uint8_t : 2; - __I uint8_t FIFO_EN : 2; /*!< two bits are set when FIFO CONTROL bit 0=1 */ - } INT_ID_b; /*!< BitSize */ - }; - - union { - __O uint8_t FIFO_CR; /*!< UART FIFO Control Register */ - - struct { - __O uint8_t EXRF : 1; /*!< Enable XMIT and RECV FIFO. */ - __O uint8_t CLEAR_RECV_FIFO: 1; /*!< clears all bytes in RCVR FIFO, resets counter */ - __O uint8_t CLEAR_XMIT_FIFO: 1; /*!< clears all bytes in XMIT FIFO, resets counter */ - __IO uint8_t DMA_MODE_SELECT: 1; /*!< RXRDY,TXRDY pins functions are reserved. */ - uint8_t : 2; - __IO uint8_t RECV_FIFO_TRIGGER_LEVEL: 2; /*!< set trigger level for RCVR FIFO Intr */ - } FIFO_CR_b; /*!< BitSize */ - }; - }; - - union { - __IO uint8_t LINE_CR; /*!< UART Line Control Register */ - - struct { - __IO uint8_t WORD_LENGTH: 2; /*!< number of bits in transmitted or received */ - __IO uint8_t STOP_BITS : 1; /*!< number of stop bits in transmitted or received */ - __IO uint8_t ENABLE_PARITY: 1; /*!< Parity Enable bit. */ - __IO uint8_t PARITY_SELECT: 1; /*!< Even Parity Select bit. */ - __IO uint8_t STICK_PARITY: 1; /*!< Stick Parity bit. */ - __IO uint8_t BREAK_CONTROL: 1; /*!< Set Break Control bit */ - __IO uint8_t DLAB : 1; /*!< DLAB Divisor Latch Access Bit (DLAB). */ - } LINE_CR_b; /*!< BitSize */ - }; - - union { - __IO uint8_t MODEM_CR; /*!< UART Modem Control Register */ - - struct { - __IO uint8_t DTR : 1; /*!< Data Terminal Ready (nDTR) output. */ - __IO uint8_t RTS : 1; /*!< Request To Send (nRTS) output. */ - __IO uint8_t OUT1 : 1; /*!< controls the Output 1 (OUT1) bit. */ - __IO uint8_t OUT2 : 1; /*!< enable an UART interrupt. */ - __IO uint8_t LOOPBACK : 1; /*!< provides loopback for diagnostic */ - } MODEM_CR_b; /*!< BitSize */ - }; - - union { - __I uint8_t LINE_STS; /*!< UART Line Status Register */ - - struct { - __I uint8_t DATA_READY : 1; /*!< 1= data into Rx Buffer Register or FIFO */ - __I uint8_t OVERRUN : 1; /*!< OVERRUN Overrun Error. */ - __I uint8_t PE : 1; /*!< PARITY ERROR Parity Error. */ - __I uint8_t FRAME_ERROR: 1; /*!< FRAME_ERROR Framing Error. */ - __I uint8_t BREAK_INTERRUPT: 1; /*!< BREAK_INTERRUPT Break Interrupt. */ - __I uint8_t TRANSMIT_EMPTY: 1; /*!< Transmitter Holding Register Empty */ - __I uint8_t TRANSMIT_ERROR: 1; /*!< Transmitter Holding/Shift are both empty. */ - __I uint8_t FIFO_ERROR : 1; /*!< FIFO_ERROR */ - } LINE_STS_b; /*!< BitSize */ - }; - - union { - __I uint8_t MODEM_STS; /*!< UART Modem Status Register */ - - struct { - __I uint8_t CTS : 1; /*!< CTS Delta Clear To Send (DCTS). */ - __I uint8_t DSR : 1; /*!< DSR Delta Data Set Ready (DDSR). */ - __I uint8_t RI : 1; /*!< Trailing Edge of Ring Indicator (TERI). */ - __I uint8_t DCD : 1; /*!< DCD Delta Data Carrier Detect (DDCD). */ - __IO uint8_t nCTS : 1; /*!< complement of Clear To Send (nCTS) input. */ - __IO uint8_t nDSR : 1; /*!< complement of Data Set Ready (nDSR) input. */ - __IO uint8_t nRI : 1; /*!< complement of Ring Indicator (nRI) input. */ - __IO uint8_t nDCD : 1; /*!< complement of Data Carrier Detect (nDCD) input. */ - } MODEM_STS_b; /*!< BitSize */ - }; - __IO uint8_t SCRATCHPAD; /*!< as a scratchpad reg. be used by programmer */ - __I uint32_t RESERVED[202]; - __IO uint8_t ACTIVATE; /*!< [0:0] 1= UART is powered/functional. */ - __I uint8_t RESERVED1[191]; - - union { - __IO uint8_t CONFIG; /*!< UART Config Select Register */ - - struct { - __IO uint8_t CLK_SRC : 1; /*!< 1=Baud Clock from external clock, 0=internal */ - __IO uint8_t POWER : 1; /*!< 1=reset from nSIO_RESET, 0=VCC1_RESET */ - __IO uint8_t POLARITY : 1; /*!< 1=UART_TX and UART_RX pins are inverted */ - } CONFIG_b; /*!< BitSize */ - }; -} UART_Type; - - -/* ================================================================================ */ -/* ================ INTR ================ */ -/* ================================================================================ */ - - -/** - * @brief The interrupt generation logic is made of 16 groups of signals, each of which - consist of a Status register, a Enable register and a Result register. The Status and Enable - are latched registers. The Result register is a bit by bit AND function of the Source and Enable - registers. All the bits of the Result register are OR'ed together and AND'ed with the corresponding - bit in the Block Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTR) - */ - -typedef struct { /*!< INTR Structure */ - INTR_IRQ_Type IRQ[16]; /*!< DEFINITIONS FOR GIRQi SOURCE/ENABLE/RESULT */ - __I uint32_t RESERVED[48]; - __IO uint32_t BLOCK_ENABLE_SET; /*!< [23:8] IRQ Vector Enable Set */ - __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< [23:8] IRQ Vector Enable Clear */ - __I uint32_t IRQ_VECTOR_STATE; /*!< [23:8] reflects current state of IRQi */ -} INTR_Type; - - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - - -/** - * @brief The function of the Watchdog Timer is to provide a mechanism to detect if the - internal embedded controller has failed. When enabled, the Watchdog Timer (WDT) circuit will generate - a WDT Event if the user program fails to reload the WDT within a specified length of time known as the WDT Interval. (WDT) - */ - -typedef struct { /*!< WDT Structure */ - __IO uint16_t LOAD; /*!< Writing to reload Watch Dog Timer counter */ - __I uint16_t RESERVED; - - union { - __IO uint8_t CONTROL; /*!< WDT Control Register */ - - struct { - __IO uint8_t ENABLE : 1; /*!< WDT Block enabled */ - __IO uint8_t STATUS : 1; /*!< last reset was caused by an underflow (R/WC) */ - } CONTROL_b; /*!< BitSize */ - }; - __I uint8_t RESERVED1[3]; - __O uint8_t KICK; /*!< Writes to reload and start decrementing */ - __I uint8_t RESERVED2[3]; - __I uint16_t COUNT; /*!< current WDT count. */ -} WDT_Type; - - -/* ================================================================================ */ -/* ================ TIMER_16_0 ================ */ -/* ================================================================================ */ - - -/** - * @brief This timer block offers a simple mechanism for firmware to maintain a time - base. This timer may be instantiated as 16 bits or 32 bits. (TIMER_16_0) - */ - -typedef struct { /*!< TIMER_16_0 Structure */ - __IO uint32_t COUNT; /*!< Timer counter. may be set by Firmware. */ - __IO uint32_t PRE_LOAD; /*!< Timer pre-load for counter upon restart. */ - __IO uint32_t INTERRUPT_STATUS; /*!< [0:0] Interrupt status (R/WC) */ - __IO uint32_t INTERRUPT_ENABLE; /*!< [0:0] interrupt enable */ - - union { - __IO REG32_U CONTROL; /*!< Timer Control Register */ - - struct { - __IO uint32_t ENABLE : 1; /*!< This enables the block for operation. */ - uint32_t : 1; - __IO uint32_t COUNT_UP : 1; /*!< This selects the counter direction. */ - __IO uint32_t AUTO_RESTART: 1; /*!< select action taken upon completing a count. */ - __IO uint32_t SOFT_RESET : 1; /*!< soft reset. self clearing 1 cycle. */ - __IO uint32_t START : 1; /*!< This bit triggers the timer counter. */ - __IO uint32_t RELOAD : 1; /*!< reloads counter without interrupting. */ - __IO uint32_t HALT : 1; /*!< halt bit. */ - uint32_t : 8; - __IO uint32_t PRE_SCALE : 16; /*!< to divide down system clock */ - } CONTROL_b; /*!< BitSize */ - }; -} TIMER_16_0_Type; - - -/* ================================================================================ */ -/* ================ HTM ================ */ -/* ================================================================================ */ - - -/** - * @brief The Hibernation Timer can generate a wake event to the Embedded Controller (EC) - when it is in a hibernation mode. This block supports wake events up to 2 hours in duration. - The timer is a 16-bit binary count-down timer that can be programmed in 30.5us and 0.125 second - increments for period ranges of 30.5us to 2s or 0.125s to 136.5 minutes, respectively. (HTM) - */ - -typedef struct { /*!< HTM Structure */ - __IO uint16_t PRELOAD; /*!< [15:0] set Hibernation Timer Preload value */ - __I uint16_t RESERVED; - __IO uint16_t CONTROL; /*!< [0:0] 1= resolution 0.125s, 0= 30.5us */ - __I uint16_t RESERVED1; - __I uint16_t COUNT; /*!< Count of the Hibernation Timer. */ -} HTM_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief This is the set of registers that are automatically counted by hardware - every 1 second while the block is enabled to run and to update. These registers are: - Seconds, Minutes, Hours, Day of Week, Day of Month, Month, and Year. (RTC) - */ - -typedef struct { /*!< RTC Structure */ - __IO uint8_t SEC; /*!< Seconds Register */ - __IO uint8_t SEC_ALARM; /*!< Seconds Alarm Register */ - __IO uint8_t MIN; /*!< Minutes Register */ - __IO uint8_t MIN_ALARM; /*!< Minutes Alarm Register */ - __IO uint8_t HR; /*!< Hours Register */ - __IO uint8_t HR_ALARM; /*!< Hours Alarm Register */ - __IO uint8_t DAY_WEEK; /*!< Day of Week Register */ - __IO uint8_t DAY_MONTH; /*!< Day of Month Register */ - __IO uint8_t MONTH; /*!< Month Register */ - __IO uint8_t YEAR; /*!< Year Register */ - __IO uint8_t REG_A; /*!< Register A */ - __IO uint8_t REG_B; /*!< Register B */ - __IO uint8_t REG_C; /*!< Register C */ - __IO uint8_t REG_D; /*!< Register D */ - __I uint16_t RESERVED; - - union { - __IO uint8_t CONTROL; /*!< RTC Control Register */ - - struct { - __IO uint8_t BLOCK_ENABLE: 1; /*!< 1= block to function internally */ - __IO uint8_t SOFT_RESET : 1; /*!< 1= RTC_RST reset (self-clearing no waiting) */ - uint8_t : 1; - __IO uint8_t ALARM_ENABLE: 1; /*!< 1=Enables Alarm, 0=Disables */ - } CONTROL_b; /*!< BitSize */ - }; - __I uint8_t RESERVED1[3]; - __IO uint8_t WEEK_ALARM; /*!< Set value in range 1-7 */ - __I uint8_t RESERVED2[3]; - - union { - __IO uint32_t DAYLIGHT_SAVINGS_FORWARD; /*!< Daylight Savings Forward Register */ - - struct { - __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */ - __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */ - uint32_t : 5; - __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */ - uint32_t : 5; - __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */ - __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */ - } DAYLIGHT_SAVINGS_FORWARD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DAYLIGHT_SAVINGS_BACKWARD; /*!< Daylight Savings Backward Register */ - - struct { - __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */ - __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */ - uint32_t : 5; - __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */ - uint32_t : 5; - __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */ - __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */ - } DAYLIGHT_SAVINGS_BACKWARD_b; /*!< BitSize */ - }; -} RTC_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief The CEC1302/24 GPIO Interface provides general purpose input monitoring and output control, - as well as managing many aspects of pin functionality; including, multi-function Pin Multiplexing Control, GPIO - Direction control, PU/PD (PU_PD) resistors, asynchronous wakeup and synchronous Interrupt Detection (int_det), - GPIO Direction, and Polarity control, as well as control of pin drive strength and slew rate. (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - - union { - __IO uint32_t PIN_CONTROL[160]; /*!< 1st Pin Control Register */ - - struct { - __IO uint32_t PU_PD : 2; /*!< 01= Pull Up, 10= Pull Down, 11/00= None */ - __IO uint32_t PWR : 2; /*!< 00= VCC1, 01= VCC2 Power Rail 1x = Reserved */ - __IO uint32_t INT_DET : 3; /*!< - [7654] -------------------------------------------- - 0 000 = Low Level Sensitive - 0 001 = High Level Sensitive - 0 100 = Interrupt events are disabled - 1 101 = Rising Edge Triggered - 1 110 = Falling Edge Triggered - 1 111 = Either edge triggered - --------------------------------------------------- */ - __IO uint32_t EDGE_EN : 1; /*!< 1= Edge detection enabled */ - __IO uint32_t BUFFER : 1; /*!< Output Buffer Type. 0 = Push-Pull, 1 = Open Drain */ - __IO uint32_t DIR : 1; /*!< GPIO Direction. 0 = Input, 1 = Output */ - __IO uint32_t OUTPUT_WRITE_EN: 1; /*!< 0= Alternative GPIO data write enabled */ - __IO uint32_t POLARITY : 1; /*!< 0 = Non-inverted, 1 = Inverted */ - __IO uint32_t MUX : 2; /*!< 00= GPIO Function, 01/10/11=Func 1/2/3 */ - uint32_t : 2; - __IO uint32_t OUTPUT : 1; /*!< 0: GPIO[x] out = '0', 1: GPIO[x] out = '1' */ - uint32_t : 7; - __I uint32_t INPUT : 1; /*!< reflects the state of GPIO input */ - } PIN_CONTROL_b[160]; /*!< BitSize */ - }; - __IO uint32_t OUTPUT[5]; /*!< Group 0: GPIO[x] out =0, 1: =1 */ - __I uint32_t RESERVED[27]; - __IO uint32_t INPUT[5]; /*!< Group GPIO Input Registers */ - __I uint32_t RESERVED1[123]; - - union { - __IO uint32_t CONTROL2_000_067[56]; /*!< PIN CONTROL REGISTER 2, from 000 - 067 */ - - struct { - __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */ - uint32_t : 3; - __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */ - } CONTROL2_000_067_b[56]; /*!< BitSize */ - }; - - union { - __IO uint32_t CONTROL2_100_167[56]; /*!< PIN CONTROL REGISTER 2, from 100 - 167 */ - - struct { - __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */ - uint32_t : 3; - __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */ - } CONTROL2_100_167_b[56]; /*!< BitSize */ - }; - __I uint32_t RESERVED2[24]; - - union { - __IO uint32_t CONTROL2_200_267[56]; /*!< PIN CONTROL REGISTER 2, from 200 - 267 */ - - struct { - __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */ - uint32_t : 3; - __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */ - } CONTROL2_200_267_b[56]; /*!< BitSize */ - }; -} GPIO_Type; - - -/* ================================================================================ */ -/* ================ DMA ================ */ -/* ================================================================================ */ - - -/** - * @brief The Internal DMA Controller transfers data to/from the source from/to the - destination. The firmware is responsible for setting up each channel. Afterwards either the - firmware or the hardware may perform the flow control. The hardware flow control exists entirely - inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device - supports a transfer of that size. Every device must be on the internal 32-bit address space. (DMA) - */ - -typedef struct { /*!< DMA Structure */ - - union { - __IO uint8_t CONTROL; /*!< Soft reset. Enable the blocks operation. */ - - struct { - __IO uint8_t ACTIVATE : 1; /*!< Enable the blocks operation. (R/WS) */ - __O uint8_t SOFT_RESET : 1; /*!< Soft reset entire module. self-clearing. */ - } CONTROL_b; /*!< BitSize */ - }; - __I uint8_t RESERVED[3]; - __I uint32_t DATA_PACKET; /*!< data from currently active transfer source */ - __I uint32_t RESERVED1[2]; - DMA_CH_Type CH[12]; /*!< registers to determine channel's operation. */ -} DMA_Type; - - -/* ================================================================================ */ -/* ================ SMB0 ================ */ -/* ================================================================================ */ - - -/** - * @brief The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface. (SMB0) - */ - -typedef struct { /*!< SMB0 Structure */ - - union { - union { - __I uint8_t STATUS; /*!< Status Register */ - - struct { - __I uint8_t nBB : 1; /*!< 0= Bus Busy */ - __I uint8_t LAB : 1; /*!< Lost Arbitration Bit */ - __I uint8_t AAS : 1; /*!< Addressed As Slave */ - __I uint8_t LRB_AD0 : 1; /*!< "Last Received Bit"/Address 0 (general call) */ - __I uint8_t BER : 1; /*!< Bus Error (BER) */ - __I uint8_t STS : 1; /*!< 1=ext generated STOP condition is detected. */ - __I uint8_t SAD : 1; /*!< SMBus Address Decoded (SAD) */ - __I uint8_t PIN : 1; /*!< Pending Interrupt bit */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __O uint8_t CONTROL; /*!< Control Register */ - - struct { - __IO uint8_t ACK : 1; /*!< 1= send an acknowledge automatically */ - __IO uint8_t STO : 1; /*!< See STA description */ - __IO uint8_t STA : 1; /*!< generation of repeated Start and Stop condition */ - __IO uint8_t ENI : 1; /*!< Enable Interrupt bit */ - uint8_t : 2; - __IO uint8_t ESO : 1; /*!< enables/disables SMB serial data output */ - __IO uint8_t PIN : 1; /*!< Pending Interrupt Not (PIN) software reset */ - } CONTROL_b; /*!< BitSize */ - }; - }; - __I uint8_t RESERVED[3]; - - union { - __IO uint16_t OWN; /*!< Own Address Reg. wt 55h= AAh addr */ - - struct { - __IO uint16_t ADDRESS_1 : 7; /*!< Own Address 1 addressed as a slave. */ - uint16_t : 1; - __IO uint16_t ADDRESS_2 : 7; /*!< Own Address 2 addressed as a slave. */ - } OWN_b; /*!< BitSize */ - }; - __I uint16_t RESERVED1; - __IO uint8_t DATA_REG; /*!< Data */ - __I uint8_t RESERVED2[3]; - - union { - __IO uint32_t MASTER_COMMAND; /*!< SMBus Master Command Register */ - - struct { - __IO uint32_t MRUN : 1; /*!< 1= transfer bytes over SMBus. */ - __IO uint32_t MPROCEED : 1; /*!< 1:WAIT-BUSBUSY and MRUN-RECEIVE */ - uint32_t : 6; - __IO uint32_t START0 : 1; /*!< 1: send a Start bit on the SMBus */ - __IO uint32_t STARTN : 1; /*!< 1: send a Start before the last byte */ - __IO uint32_t STOP : 1; /*!< 1: send a Stop bit after transaction completes */ - __IO uint32_t PEC_TERM : 1; /*!< 1: PEC is transmitted when WriteCount is 0. */ - __IO uint32_t READM : 1; /*!< 1: ReadCount field is replaced by byte */ - __IO uint32_t READ_PEC : 1; /*!< 1: reading when ReadCount is 0 for one more byte */ - uint32_t : 2; - __IO uint32_t WRITECOUNT : 8; /*!< number of Master Transmit Buffer bytes */ - __IO uint32_t READCOUNT : 8; /*!< number of Master Receive Buffer bytes */ - } MASTER_COMMAND_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SLAVE_COMMAND; /*!< SMBus Slave Command Register */ - - struct { - __IO uint32_t SRUN : 1; /*!< 1:enables the Slave State Machine to operate */ - __IO uint32_t SPROCEED : 1; /*!< Slave to START_WAIT/RECEIVE/TRANSMIT states */ - __IO uint32_t SLAVE_PEC : 1; /*!< 1:PEC is copied to the DATA register */ - uint32_t : 5; - __IO uint32_t SLAVE_WRITECOUNT: 8; /*!< number bytes software expects to send to Master */ - __IO uint32_t SLAVE_READCOUNT: 8; /*!< number copied from DATA to Slave Receive Buffer */ - } SLAVE_COMMAND_b; /*!< BitSize */ - }; - __IO uint8_t PEC; /*!< PEC byte */ - __I uint8_t RESERVED3[3]; - __IO uint8_t DATA_TIMING2; /*!< HOLD TIME (clock) START BIT */ - __I uint8_t RESERVED4[7]; - - union { - __IO uint32_t COMPLETION; /*!< Completion Register */ - - struct { - uint32_t : 2; - __IO uint32_t DTEN : 1; /*!< 1: Device Time-out checking is enabled. */ - __IO uint32_t MCEN : 1; /*!< 1: enable Master Cumulative Time-Out checking */ - __IO uint32_t SCEN : 1; /*!< 1:enable Slave Cumulative Time-Out checking */ - __IO uint32_t BIDEN : 1; /*!< 1:Bus Idle Detect Time-Out checking is enabled */ - __I uint32_t TIMERR : 1; /*!< 1:timeout error detect status are asserted. */ - uint32_t : 1; - __IO uint32_t DTO : 1; /*!< DTO is the Device Time-out bit. (R/WC) */ - __IO uint32_t MCTO : 1; /*!< Master Cumulative Time-out bit. (R/WC) */ - __IO uint32_t SCTO : 1; /*!< SCTO is the Slave Cumulative Time-out bit(R/WC) */ - __IO uint32_t CHDL : 1; /*!< CHDL is the clock high time-out detect bit(R/WC) */ - __IO uint32_t CHDH : 1; /*!< CHDH is the bus idle time-out detect bit(R/WC) */ - __IO uint32_t BER : 1; /*!< 1: BER in Status was set (R/WC) */ - __IO uint32_t LAB : 1; /*!< 1: LAB in Status was set (R/WC) */ - uint32_t : 1; - __IO uint32_t SNAKR : 1; /*!< 1: Slave sent NACK to transmitting Master */ - __I uint32_t STR : 1; /*!< 0: finished receive, 1:finished transmit phase */ - uint32_t : 1; - __IO uint32_t SPROT : 1; /*!< 1: WriteCount in Slave counted down to 0(R/WC) */ - __IO uint32_t REPEAT_READ: 1; /*!< 1: Slave stopped because a Repeat Start for Rd */ - __IO uint32_t REPEAT_WRITE: 1; /*!< 1: Slave stopped because a Repeat Start for Wt */ - uint32_t : 2; - __IO uint32_t MNAKX : 1; /*!< 1: Master received a NACK while transmitting */ - __I uint32_t MTR : 1; /*!< Master finished 0: receive 1: transmit */ - uint32_t : 3; - __IO uint32_t IDLE : 1; /*!< 1: I2C bus becomes idle (R/WC) */ - __IO uint32_t MDONE : 1; /*!< 1: Master completed operation (R/WC) */ - __IO uint32_t SDONE : 1; /*!< 1: Slave completed operation (R/WC) */ - } COMPLETION_b; /*!< BitSize */ - }; - - union { - __IO uint32_t IDLE_SCALING; /*!< Idle Scaling Register */ - - struct { - __IO uint32_t FAIR_BUS_IDLE_MIN: 12; /*!< number ticks to satisfy the fairness protocol */ - uint32_t : 4; - __IO uint32_t FAIR_IDLE_DELAY: 12; /*!< number ticks to program the delay */ - } IDLE_SCALING_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CONFIGURATION; /*!< Configuration Register */ - - struct { - __IO uint32_t PORT_SEL : 4; /*!< determine one of 16 bus ports apply to SDAT/SCLK */ - __IO uint32_t TCEN : 1; /*!< 1: Bus Time-Outs are enabled */ - __I uint32_t SLOW_CLOCK : 1; /*!< 1: Bus Clock multiplied by 4, thus frequency/4 */ - uint32_t : 1; - __IO uint32_t PECEN : 1; /*!< 1: Hardware PEC Support is enabled */ - __IO uint32_t DFEN : 1; /*!< 1: Digital Filter is enabled. 0: bypassed. */ - __IO uint32_t RESET : 1; /*!< 1: initialized to power-on default state. */ - __IO uint32_t ENAB : 1; /*!< 1: normal operation, 0: lowest power */ - __IO uint32_t DSA : 1; /*!< 0: Slave Address I2C Compatibility, 1: SMBus */ - __IO uint32_t FAIR : 1; /*!< 1: MCTP Fairness protocol is in effect. */ - uint32_t : 1; - __I uint32_t GC_DIS : 1; /*!< General Call address 0: enabled, 1: disabled */ - uint32_t : 1; - __O uint32_t FLUSH_SXBUF: 1; /*!< 1: Slave Transmit Buffer to be marked empty. */ - __O uint32_t FLUSH_SRBUF: 1; /*!< 1: Slave Receive Buffer to be marked empty. */ - __O uint32_t FLUSH_MXBUF: 1; /*!< 1: Master Transmit Buffer to be marked empty. */ - __O uint32_t FLUSH_MRBUF: 1; /*!< 1: Master Receive Buffer to be marked empty. */ - uint32_t : 8; - __I uint32_t EN_AAS : 1; /*!< 0: Disable AAS Interrupt, 1: Enable */ - __IO uint32_t ENIDI : 1; /*!< 1: Idle interrupt is enabled. 0: disabled. */ - __IO uint32_t ENMI : 1; /*!< 1: Master Done interrupt is enabled. 0: disabled */ - __IO uint32_t ENSI : 1; /*!< 1: Slave Done interrupt is enabled. 0: disabled */ - } CONFIGURATION_b; /*!< BitSize */ - }; - - union { - __IO uint16_t BUS_CLOCK; /*!< Bus Clock Register */ - - struct { - __IO uint16_t LOW_PERIOD : 8; /*!< number of I2C Baud Clock to make up low phase */ - __IO uint16_t HIGH_PERIOD: 8; /*!< number of I2C Baud Clock to make up high phase */ - } BUS_CLOCK_b; /*!< BitSize */ - }; - __I uint16_t RESERVED5; - __I uint8_t BLOCK_ID; /*!< Block ID Register */ - __I uint8_t RESERVED6[3]; - __I uint8_t REVISION; /*!< Revision Register */ - __I uint8_t RESERVED7[3]; - - union { - __IO uint8_t BIT_BANG_CONTROL; /*!< Bit-Bang Control Register */ - - struct { - __IO uint8_t BBEN : 1; /*!< 1: Bit-Bang Mode Enable. */ - __IO uint8_t CLDIR : 1; /*!< Bit-Bang Clock Direction. 0 - Input, 1 - Output */ - __IO uint8_t DADIR : 1; /*!< Bit-Bang Data Direction. 0 - Input. 1 - Output */ - __IO uint8_t BBCLK : 1; /*!< controls state of SCLK when BBEN = CLDIR = 1 */ - __IO uint8_t BBDAT : 1; /*!< controls state of SDAT when BBEN = DADIR = 1 */ - __I uint8_t BBCLKI : 1; /*!< Bit-Bang Clock In. returns the state of SCLK. */ - __I uint8_t BBDATI : 1; /*!< Bit-Bang Data In. returns the state of SDAT */ - } BIT_BANG_CONTROL_b; /*!< BitSize */ - }; - __I uint8_t RESERVED8[7]; - - union { - __IO uint32_t DATA_TIMING; /*!< Data Timing Register */ - - struct { - __IO uint32_t DATA_HOLD : 8; /*!< SDAT hold time following SCLK driven low. */ - __IO uint32_t RESTART_SETUP: 8; /*!< SDAT setup time for a repeated START condition. */ - __IO uint32_t STOP_SETUP : 8; /*!< SDAT setup time for a STOP condition. */ - __IO uint32_t START_HOLD : 8; /*!< SCLK hold time during a START condition. */ - } DATA_TIMING_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TIME_OUT_SCALING; /*!< Time-Out Scaling Register */ - - struct { - __IO uint32_t CLOCK_HIGH : 8; /*!< = Clock High Time-Out x Baud_Clock_Period x 2 */ - __IO uint32_t SLAVE_CUM : 8; /*!< = Slave Cum Time-Out x Baud_Clock_Period x 1024 */ - __IO uint32_t MASTER_CUM : 8; /*!< = Master Cum Time-Out x Baud_Clock_Periodx 512 */ - __IO uint32_t BUS_IDLE_MIN: 8; /*!< = Bus Idle Min [7:0] x Baud_Clock_Period */ - } TIME_OUT_SCALING_b; /*!< BitSize */ - }; - __IO uint8_t SLAVE_TRANSMIT_BUFFER; /*!< SMBus Slave Transmit Buffer Register */ - __I uint8_t RESERVED9[3]; - __IO uint8_t SLAVE_RECEIVE_BUFFER; /*!< SMBus Slave Receive Buffer Register */ - __I uint8_t RESERVED10[3]; - __IO uint8_t MASTER_TRANSMIT_BUFER; /*!< SMBus Master Transmit Bufer Register */ - __I uint8_t RESERVED11[3]; - __IO uint8_t MASTER_RECEIVE_BUFFER; /*!< SMBus Master Receive Buffer Register */ -} SMB0_Type; - - -/* ================================================================================ */ -/* ================ PECI ================ */ -/* ================================================================================ */ - - -/** - * @brief The CEC1302 includes a PECI Interface to allow the EC to retrieve temperature readings from PECI-compliant devices. (PECI) - */ - -typedef struct { /*!< PECI Structure */ - __IO uint8_t WRITE_DATA; /*!< Tprovides access to a 32-byte Transmit FIFO. */ - __I uint8_t RESERVED[3]; - __IO uint8_t READ_DATA; /*!< provides access to a 32-byte Receive FIFO. */ - __I uint8_t RESERVED1[3]; - - union { - __IO uint8_t CONTROL; /*!< Control Register */ - - struct { - __IO uint8_t PD : 1; /*!< Power Down controls Power Management Interface */ - uint8_t : 2; - __IO uint8_t RST : 1; /*!< RST indicates that the PECI Core should be reset. */ - uint8_t : 1; - __IO uint8_t FRST : 1; /*!< FRST is the FIFO Reset bit. */ - __IO uint8_t TXEN : 1; /*!< TXEN is the Transmit Enable bit. */ - __IO uint8_t MIEN : 1; /*!< MIEN is the Master Interrupt Enable */ - } CONTROL_b; /*!< BitSize */ - }; - __I uint8_t RESERVED2[3]; - - union { - __IO uint8_t STATUS1; /*!< Status Register 1 */ - - struct { - __IO uint8_t BOF : 1; /*!< PECI begins Address Timing Negotiation(R/WC) */ - __IO uint8_t nEOF : 1; /*!< End of Frame asserted following Message Stop(R/WC) */ - __I uint8_t ERR : 1; /*!< error for current transaction has been detected */ - __I uint8_t RDY : 1; /*!< state of the READY signal function */ - __IO uint8_t RDYLO : 1; /*!< 1: falling edge of the READY signal function(R/WC) */ - __IO uint8_t RDYHI : 1; /*!< 1: rising edge of the READY signal function (R/WC) */ - uint8_t : 1; - __I uint8_t MINT : 1; /*!< asserted when any interrupt status is asserted. */ - } STATUS1_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[3]; - - union { - __I uint8_t STATUS2; /*!< Status Register 2 */ - - struct { - __I uint8_t WFF : 1; /*!< Write Data Register FIFO is full. No interrupt. */ - __I uint8_t WFE : 1; /*!< Write Data Register FIFO is empty. */ - __I uint8_t RFF : 1; /*!< RFF indicates Read Data Register FIFO is full. */ - __I uint8_t RFE : 1; /*!< Read Data Register FIFO is empty. No interrupt. */ - uint8_t : 3; - __I uint8_t IDLE : 1; /*!< SST/PECI bus is idle, a new transaction may begin */ - } STATUS2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED4[3]; - - union { - __IO uint8_t ERROR; /*!< Error Register */ - - struct { - __IO uint8_t FERR : 1; /*!< FERR (Frame Check Sequence Error). (R/WC) */ - __IO uint8_t BERR : 1; /*!< reads value different from it has driven (R/WC) */ - uint8_t : 1; - __IO uint8_t REQERR : 1; /*!< READY is not asserted when counts down to zero */ - __IO uint8_t WROV : 1; /*!< WROV (Write Overrun). (R/WC) */ - __IO uint8_t WRUN : 1; /*!< WRUN (Write Underrun). (R/WC) */ - __IO uint8_t RDOV : 1; /*!< indicates read buffer has overflowed (R/WC) */ - __IO uint8_t CLKERR : 1; /*!< READY de-asserted in middle of a transaction(R/WC) */ - } ERROR_b; /*!< BitSize */ - }; - __I uint8_t RESERVED5[3]; - - union { - __IO uint8_t INT_EN1; /*!< Interrupt Enable 1 Register */ - - struct { - __IO uint8_t BIEN : 1; /*!< '1' the BOF interrupt is enabled. */ - __IO uint8_t EIEN : 1; /*!< '1' the EOF interrupt is enabled. */ - __IO uint8_t EREN : 1; /*!< '1' the ERR interrupt is enabled. */ - uint8_t : 1; - __IO uint8_t RLEN : 1; /*!< '1' the RDYLO interrupt is enabled. */ - __IO uint8_t RHEN : 1; /*!< '1' the RDYHI interrupt is enabled. */ - } INT_EN1_b; /*!< BitSize */ - }; - __I uint8_t RESERVED6[3]; - - union { - __IO uint8_t INT_EN2; /*!< Interrupt Enable 2 Register */ - - struct { - uint8_t : 1; - __IO uint8_t ENWFE : 1; /*!< '1' the WFE interrupt is enabled. */ - __IO uint8_t ENRFF : 1; /*!< '1' the RFF interrupt is enabled. */ - } INT_EN2_b; /*!< BitSize */ - }; - __I uint8_t RESERVED7[3]; - __IO uint8_t OBT1; /*!< Optimal Bit Time Register (Low Byte) */ - __I uint8_t RESERVED8[3]; - __IO uint8_t OBT2; /*!< Optimal Bit Time Register (High Byte) */ - __I uint8_t RESERVED9[27]; - __IO uint32_t ID; /*!< Block ID Register */ - __IO uint32_t REV; /*!< Revision Register */ -} PECI_Type; - - -/* ================================================================================ */ -/* ================ TACH_0 ================ */ -/* ================================================================================ */ - - -/** - * @brief This block monitors TACH output signals (or locked rotor signals) from - various types of fans, and determines their speed. (TACH_0) - */ - -typedef struct { /*!< TACH_0 Structure */ - - union { - __IO uint32_t CONTROL; /*!< TACHx Control Register */ - - struct { - __IO uint32_t OUT_LIMIT_ENABLE: 1; /*!< 1=Enable interrupt output from Tach block */ - __IO uint32_t TACH_EN : 1; /*!< 1= TACH Monitoring/ clock enabled, 0= TACH Idle */ - uint32_t : 6; - __IO uint32_t FILTER_EN : 1; /*!< remove high frequency glitches. 1=Filter enabled */ - uint32_t : 1; - __IO uint32_t MODE_SELECT: 1; /*!< 1=Counter is incremented on rising edge */ - __IO uint32_t EDGES : 2; /*!< 00/01/10/11: 2/3/5/9 Tach edges */ - uint32_t : 1; - __IO uint32_t READY_INT_EN: 1; /*!< 1=Enable Count Ready interrupt, 0=Disable */ - __IO uint32_t INPUT_INT_EN: 1; /*!< 1=Enable Tach Input toggle interrupt, 0=Disable */ - __I uint32_t COUNTER : 16; /*!< latched value of the internal Tach pulse counter */ - } CONTROL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t STATUS; /*!< TACHx Status Register */ - - struct { - __IO uint32_t OUT_LIMIT : 1; /*!< 1=Tach is outside of limits (R/WC) */ - __I uint32_t PIN : 1; /*!< 1= Tach Input is high, 0= Input is low */ - __IO uint32_t TOGGLE : 1; /*!< 1=Tach Input changed state, 0= stable (R/WC) */ - __IO uint32_t COUNT_READY: 1; /*!< 1=Reading ready, 0=Reading not ready */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint16_t HIGH_LIMIT; /*!< value is compared with TACHX_COUNTER field. */ - __I uint16_t RESERVED; - __IO uint16_t LOW_LIMIT; /*!< value is compared with TACHX_COUNTER field. */ -} TACH_0_Type; - - -/* ================================================================================ */ -/* ================ PWM_0 ================ */ -/* ================================================================================ */ - - -/** - * @brief This block generates a PWM output that can be used to control 4-wire fans, blinking LEDs, and - other similar devices. Each PWM can generate an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz. - The PWM controller can also used to generate the PROCHOT output and Speaker output. (PWM_0) - */ - -typedef struct { /*!< PWM_0 Structure */ - __IO uint32_t COUNTER_ON_TIME; /*!< determine both frequency and duty cycle */ - __IO uint32_t COUNTER_OFF_TIME; /*!< determine both frequency and duty cycle */ - - union { - __IO uint32_t CONFIG; /*!< PWMx CONFIGURATION REGISTER */ - - struct { - __IO uint32_t EN : 1; /*!< 1=Enabled (default), 0=Disabled */ - __IO uint32_t CLK_SELECT : 1; /*!< determines clock source, 1=CLOCK_LOW, 0=HIGH */ - __IO uint32_t INVERT : 1; /*!< 1= PWM_OUTPUT ON State is active low, 0=high */ - __IO uint32_t CLK_PRE_DIVIDER: 4; /*!< Clock source is divided by Pre-Divider+1 */ - } CONFIG_b; /*!< BitSize */ - }; -} PWM_0_Type; - - -/* ================================================================================ */ -/* ================ RPM_FAN ================ */ -/* ================================================================================ */ - - -/** - * @brief The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors - the fan's speed and automatically adjusts the drive to maintain the desired fan speed. This - RPM based Fan Control Algorithm controls a PWM output based on a tachometer input. (RPM_FAN) - */ - -typedef struct { /*!< RPM_FAN Structure */ - __IO uint8_t SETTING; /*!< Drive = (FAN_SETTING VALUE/255) x 100%. */ - __IO uint8_t PWM_DIVIDE; /*!< PWM_Frequency = base_clk / PWM_DIVIDE */ - - union { - __IO uint16_t CONFIGURATION; /*!< general operation of Fan Control Algorithm */ - - struct { - __IO uint16_t UPDATE : 3; /*!< Determines base time between fan driver updates */ - __IO uint16_t EDGES : 2; /*!< minimum number of edges that must be detected */ - __IO uint16_t RANGE : 2; /*!< Adjusts the range of tachometer reading values. */ - __IO uint16_t EN_ALGO : 1; /*!< Enables the RPM based Fan Control Algorithm. */ - __IO uint16_t POLARITY : 1; /*!< 1: The Polarity of the PWM driver is inverted. */ - __IO uint16_t ERR_RNG : 2; /*!< Control advanced options that affect error window. */ - __IO uint16_t DER_OPT : 2; /*!< Control portion of RPM fan control algorithm */ - __IO uint16_t DIS_GLITCH : 1; /*!< 1: The glitch filter is disabled. */ - __IO uint16_t EN_RRC : 1; /*!< Enables the ramp rate control circuitry */ - } CONFIGURATION_b; /*!< BitSize */ - }; - __I uint8_t RESERVED; - - union { - __IO uint8_t GAIN; /*!< gain for proportional/integral portion */ - - struct { - __IO uint8_t GAINP : 2; /*!< derivative gain term */ - __IO uint8_t GAINI : 2; /*!< derivative gain term */ - __IO uint8_t GAIND : 2; /*!< derivative gain term */ - } GAIN_b; /*!< BitSize */ - }; - - union { - __IO uint8_t SPIN_UP_CONFIGURATION; /*!< settings of Spin Up Routine. */ - - struct { - __IO uint8_t SPINUP_TIME: 2; /*!< maximum Spin Time that Spin Up Routine run */ - __IO uint8_t SPIN_LVL : 3; /*!< final drive level used by the Spin Up Routine */ - __IO uint8_t NOKICK : 1; /*!< 1: Spin Routine will not drive fan to 100% */ - __IO uint8_t DRIVE_FAIL_CNT: 2; /*!< update cycles are used for Drive Fail detection */ - } SPIN_UP_CONFIGURATION_b; /*!< BitSize */ - }; - __IO uint8_t STEP; /*!< max step driver take between update */ - __IO uint8_t MINIMUM_DRIVE; /*!< minimum drive setting for Fan Algorithm. */ - __IO uint8_t VALID_TACH_COUNT; /*!< max value to indicate fan spin properly */ - __IO uint16_t DRIVE_FAIL_BAND; /*!< [15:3]counts for Drive Fail circuitry */ - __IO uint16_t TACH_TARGET; /*!< [12:0] The target tachometer value. */ - __IO uint8_t TACH_READING; /*!< [15:3]current tachometer reading value. */ - __I uint8_t RESERVED1; - __IO uint8_t DRIVER_BASE_FREQUENCY; /*!< [1:0]frequency range of the PWM fan driver */ - - union { - __IO uint8_t STATUS; /*!< The bits are routed to interrupts */ - - struct { - __IO uint8_t FAN_STALL : 1; /*!< 1 - Stalled fan detected. (R/WC) */ - __IO uint8_t FAN_SPIN : 1; /*!< 1: Spin up Routine not detect a valid tachometer */ - uint8_t : 3; - __IO uint8_t DRIVE_FAIL : 1; /*!< 1- cannot drive to target setting (R/WC) */ - } STATUS_b; /*!< BitSize */ - }; -} RPM_FAN_Type; - - -/* ================================================================================ */ -/* ================ SPI_0 ================ */ -/* ================================================================================ */ - - -/** - * @brief The General Purpose Serial Peripheral Interface (GP-SPI) may be used - to communicate with various peripheral devices, e.g., EEPROMS, DACs, ADCs, that use a - standard Serial Peripheral Interface. (SPI_0) - */ - -typedef struct { /*!< SPI_0 Structure */ - __IO uint32_t ENABLE; /*!< [0:0] 1=Enabled. device is fully operational */ - - union { - __IO uint32_t CONTROL; /*!< SPI Control */ - - struct { - __IO uint32_t LSBF : 1; /*!< Least Significant Bit First */ - __IO uint32_t BIOEN : 1; /*!< Bidirectional Output Enable control. */ - __IO uint32_t SPDIN_SELECT: 2; /*!< [3:2]1xb=SPDIN1,SPDIN2. Select Dual Mode */ - __IO uint32_t SOFT_RESET : 1; /*!< Wt 1 to Soft Reset. self-clearing */ - __IO uint32_t AUTO_READ : 1; /*!< Auto Read Enable. */ - __IO uint32_t CE : 1; /*!< SPI Chip Select Enable. */ - } CONTROL_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< SPI Status */ - - struct { - __I uint32_t TXBE : 1; /*!< 1=TX_Data buffer is empty */ - __I uint32_t RXBF : 1; /*!< 1=RX_Data buffer is full */ - __I uint32_t ACTIVE : 1; /*!< ACTIVE status */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint32_t TX_DATA; /*!< [7:0]wt to initiate a SPI transaction. */ - __IO uint32_t RX_DATA; /*!< [7:0]read value returned by ext SPI device */ - - union { - __IO uint32_t CLOCK_Control; /*!< SPI Clock Control. */ - - struct { - __IO uint32_t TCLKPH : 1; /*!< Valid data is clocked out on 1st SPI_CLK */ - __IO uint32_t RCLKPH : 1; /*!< Valid data is expected after 1st SPI_CLK edge */ - __IO uint32_t CLKPOL : 1; /*!< SPI_CLK is high when 1st clock edge falling */ - uint32_t : 1; - __IO uint32_t CLKSRC : 1; /*!< 1=2MHz, 0=48 MHz Ring Oscillator */ - } CLOCK_Control_b; /*!< BitSize */ - }; - __IO uint32_t CLOCK_GENERATOR; /*!< [5:0] PRELOAD SPI Clock Generator Preload value. */ -} SPI_0_Type; - - -/* ================================================================================ */ -/* ================ LED_0 ================ */ -/* ================================================================================ */ - - -/** - * @brief The blinking/breathing hardware is implemented using a PWM. The PWM can be - driven either by the 48 MHz clock or by a 32.768 KHz clock input. When driven by the 48 MHz clock, - the PWM can be used as a standard 8-bit PWM in order to control a fan. When used to drive blinking - or breathing LEDs, the 32.768 KHz clock source is used. (LED_0) - */ - -typedef struct { /*!< LED_0 Structure */ - - union { - __IO uint32_t CONFIG; /*!< LED Configuration */ - - struct { - __IO uint32_t CONTROL : 2; /*!< 3=on,2=blinking,1=breathing,0=off */ - __IO uint32_t CLOCK_SOURCE: 1; /*!< 1=48MHz, 0=32.768 KHz clock */ - __IO uint32_t SYNCHRONIZE: 1; /*!< 1: all LEDs are reset to initial values. */ - __IO uint32_t PWM_SIZE : 2; /*!< 3:reserved, 2:6bit, 1:7bit,0:8bit PWM */ - __IO uint32_t ENABLE_UPDATE: 1; /*!< ENABLE_UPDATE */ - __O uint32_t RESET : 1; /*!< 1 resets PWM to default values self clearing */ - __IO uint32_t WDT_RELOAD : 8; /*!< PWM Watchdog Timer counter reload value */ - __IO uint32_t SYMMETRY : 1; /*!< 1=rising/falling ramp are in Asymmetric mode */ - } CONFIG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t LIMITS; /*!< LED Limits */ - - struct { - __IO uint32_t MINIMUM : 8; /*!< wait in breathing if current cycle less this value */ - __IO uint32_t MAXIMUM : 8; /*!< wait, breathing if current cycle great this value */ - } LIMITS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DELAY; /*!< LED Delay */ - - struct { - __IO uint32_t LOWPULSE : 12; /*!< number to wait before updating current cycle */ - __IO uint32_t HIGHPULSE : 12; /*!< number to wait before updating current cycle */ - } DELAY_b; /*!< BitSize */ - }; - - union { - __IO uint32_t UPDATE_STEPSIZE; /*!< provide amount duty cycle to adjust */ - - struct { - __IO uint32_t STEP0 : 4; /*!< when the segment index is equal to 000. */ - __IO uint32_t STEP1 : 4; /*!< when the segment index is equal to 001. */ - __IO uint32_t STEP2 : 4; /*!< when the segment index is equal to 010. */ - __IO uint32_t STEP3 : 4; /*!< when the segment index is equal to 011. */ - __IO uint32_t STEP4 : 4; /*!< when the segment index is equal to 100. */ - __IO uint32_t STEP5 : 4; /*!< when the segment index is equal to 101 */ - __IO uint32_t STEP6 : 4; /*!< when the segment index is equal to 110. */ - __IO uint32_t STEP7 : 4; /*!< when the segment index is equal to 111. */ - } UPDATE_STEPSIZE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t UPDATE_INTERVAL; /*!< LED Update Interval */ - - struct { - __IO uint32_t INTERVAL0 : 4; /*!< when the segment index is equal to 000b. */ - __IO uint32_t INTERVAL1 : 4; /*!< when the segment index is equal to 001b. */ - __IO uint32_t INTERVAL2 : 4; /*!< when the segment index is equal to 010b. */ - __IO uint32_t INTERVAL3 : 4; /*!< when the segment index is equal to 011b. */ - __IO uint32_t INTERVAL4 : 4; /*!< when the segment index is equal to 100b. */ - __IO uint32_t INTERVAL5 : 4; /*!< when the segment index is equal to 101b. */ - __IO uint32_t INTERVAL6 : 4; /*!< when the segment index is equal to 110b. */ - __IO uint32_t INTERVAL7 : 4; /*!< when the segment index is equal to 111b. */ - } UPDATE_INTERVAL_b; /*!< BitSize */ - }; -} LED_0_Type; - - -/* ================================================================================ */ -/* ================ PS2_0 ================ */ -/* ================================================================================ */ - - -/** - * @brief There are four PS/2 Ports in the MEC1320 which are directly controlled - by the EC. The hardware implementation eliminates the need to bit bang I/O ports to generate - PS/2 traffic, however bit banging is available via the associated GPIO pins. (PS2_0) - */ - -typedef struct { /*!< PS2_0 Structure */ - - union { - __I uint32_t RX_DATA; /*!< Data received from a peripheral */ - __O uint32_t TX_DATA; /*!< Writes to start a transmission */ - }; - - union { - __IO uint32_t CONTROL; /*!< PS2 Control Register */ - - struct { - __IO uint32_t TR : 1; /*!< PS/2 1:Transmit, 0:Receive data */ - __IO uint32_t EN : 1; /*!< 1: PS/2 Enable */ - __IO uint32_t PARITY : 2; /*!< 00b=Receiver expects Odd Parity (default). */ - __IO uint32_t STOP : 2; /*!< 00b=Receiver expects an active high stop bit */ - } CONTROL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t STATUS; /*!< PS2 Status Register */ - - struct { - __I uint32_t RDATA_RDY : 1; /*!< Data Ready. Reading Receive data to clears */ - __IO uint32_t REC_TIMEOUT: 1; /*!< REC_TIMEOUT is cleared when Status is read */ - __IO uint32_t PE : 1; /*!< Parity Error */ - __IO uint32_t FE : 1; /*!< Framing Error */ - __I uint32_t XMIT_IDLE : 1; /*!< 0=actively transmitting PS/2 data. 1=Idle */ - __IO uint32_t XMIT_TIME_OUT: 1; /*!< Transmitter Time-out */ - __I uint32_t RX_BUSY : 1; /*!< 0=actively receiving PS/2 data, 1=Idle */ - __IO uint32_t XMIT_START_TIMEOUT: 1; /*!< Transmit Start Timeout (over 25 ms) */ - } STATUS_b; /*!< BitSize */ - }; -} PS2_0_Type; - - -/* ================================================================================ */ -/* ================ KEYSCAN ================ */ -/* ================================================================================ */ - - -/** - * @brief The Keyboard Scan Interface block provides a register interface to the EC - to directly scan an external keyboard matrix of size up to 18x8. (KEYSCAN) - */ - -typedef struct { /*!< KEYSCAN Structure */ - __I uint32_t RESERVED; - - union { - __IO uint32_t CONTROL; /*!< KSO Select and control */ - - struct { - __IO uint32_t SELECT : 5; /*!< selects a KSO line (00000b=KSO[0] etc.) */ - __IO uint32_t ALL : 1; /*!< 0=KSO_SELECT set KSO, 1=KSO[x] driven high */ - __IO uint32_t KSEN : 1; /*!< 0=Keyboard scan enabled, 1=disabled. */ - __IO uint32_t INVERT : 1; /*!< 0=KSO[x] driven low, 1=high when selected. */ - } CONTROL_b; /*!< BitSize */ - }; - __I uint32_t KSI; /*!< [7:0]returns the current state of KSI pins */ - __IO uint32_t STATUS; /*!< [7:0]set on falling edge of KSI */ - __IO uint32_t INT_EN; /*!< [7:0]enables int due to H2L on a KSI */ - __IO uint32_t EXTENDED_CONTROL; /*!< [0:0] 1=Enable predrive on KSO pins. */ -} KEYSCAN_Type; - - -/* ================================================================================ */ -/* ================ BC_LINK ================ */ -/* ================================================================================ */ - - -/** - * @brief This block provides BC-Link connectivity to a slave device. The BC-Link protocol - includes a start bit to signal the beginning of a message and a turnaround (TAR) period - for bus transfer between the Master and Companion devices. (BC_LINK) - */ - -typedef struct { /*!< BC_LINK Structure */ - - union { - __IO uint32_t STATUS; /*!< BC-Link Status */ - - struct { - __I uint32_t BUSY : 1; /*!< 1: BC is transferring data and on reset */ - uint32_t : 3; - __IO uint32_t BUSY_CLR_INT_EN: 1; /*!< enable for generating an interrupt */ - __IO uint32_t ERR_INT_EN : 1; /*!< enable interrupt when BC_ERR bit set */ - __IO uint32_t ERROR : 1; /*!< indicates a BC Bus Error has occurred. (R/WC) */ - __IO uint32_t RESET : 1; /*!< 1: Reset BC_Link Master Interface */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint32_t ADDRESS; /*!< Address in Companion for BC-Link */ - __IO uint32_t DATA_REG; /*!< hold data used in a BC-Link transaction. */ - __IO uint32_t CLOCK_SELECT; /*!< [7:0] DIVIDER 48MHz/ (Divider +1). */ -} BC_LINK_Type; - - -/* ================================================================================ */ -/* ================ TFDP ================ */ -/* ================================================================================ */ - - -/** - * @brief The TFDP serially transmits Embedded Controller (EC)-originated - diagnostic vectors to an external debug trace system. (TFDP) - */ - -typedef struct { /*!< TFDP Structure */ - __IO uint8_t DATA_REG; /*!< Debug data to be shifted out on TFDP port */ - __I uint8_t RESERVED[3]; - - union { - __IO uint8_t CONTROL; /*!< Debug Control Register */ - - struct { - __IO uint8_t EN : 1; /*!< 1=Clock enabled, 0=Clock is disabled (Default) */ - __IO uint8_t EDGE_SEL : 1; /*!< 1= shifted out on falling edge, 0= rising */ - __IO uint8_t DIVSEL : 2; /*!< Clock Divider Select. */ - __IO uint8_t IP_DELAY : 3; /*!< Inter-packet Delay. */ - } CONTROL_b; /*!< BitSize */ - }; -} TFDP_Type; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief This block is designed to convert external analog voltage readings into digital values. (ADC) - */ - -typedef struct { /*!< ADC Structure */ - - union { - __IO uint32_t CONTROL; /*!< control behavior of ADC */ - - struct { - __IO uint32_t ACTIVATE : 1; /*!< 1: ADC is enabled for operation. */ - __IO uint32_t START_SINGLE: 1; /*!< 1: ADC Single Mode is enabled. self-clearing */ - __IO uint32_t START_REPEAT: 1; /*!< 1: ADC Repeat Mode is enabled. */ - __IO uint32_t POWER_SAVER_DIS: 1; /*!< 0: Power saving enabled. 1: disabled. */ - __IO uint32_t SOFT_RESET : 1; /*!< 1: reset of ADC */ - uint32_t : 1; - __IO uint32_t REPEAT_DONE_STAT: 1; /*!< 1: ADC repeat conversion is completed.(R/WC) */ - __IO uint32_t SINGLE_DONE_STAT: 1; /*!< 1: ADC single conversion is completed.(R/WC) */ - } CONTROL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DELAY; /*!< delay fm set Start_Repeat and conversion */ - - struct { - __IO uint32_t START : 16; /*!< start delay before conv. when Start_Repeat=1 */ - __IO uint32_t REPEAT : 16; /*!< interval between conversion when Start_Repeat=1 */ - } DELAY_b; /*!< BitSize */ - }; - - union { - __IO uint32_t STATUS; /*!< 1: conversion is complete (R/WC) */ - - struct { - __IO uint32_t CH0 : 1; /*!< ADC_Ch0_Status */ - __IO uint32_t CH1 : 1; /*!< ADC_Ch1_Status */ - __IO uint32_t CH2 : 1; /*!< ADC_Ch2_Status */ - __IO uint32_t CH3 : 1; /*!< ADC_Ch3_Status */ - __IO uint32_t CH4 : 1; /*!< ADC_Ch4_Status */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SINGLE_EN; /*!< ADC Single-Sample conversion control */ - - struct { - __IO uint32_t CH0 : 1; /*!< Ch0 single conversions, 1:enabled/0:disabled */ - __IO uint32_t CH1 : 1; /*!< Ch1 single conversions, 1:enabled/0:disabled */ - __IO uint32_t CH2 : 1; /*!< Ch2 single conversions, 1:enabled/0:disabled */ - __IO uint32_t CH3 : 1; /*!< Ch3 single conversions, 1:enabled/0:disabled */ - __IO uint32_t CH4 : 1; /*!< Ch4 single conversions, 1:enabled/0:disabled */ - } SINGLE_EN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t REPEAT; /*!< ADC channels repeat conversion control */ - - struct { - __IO uint32_t CH0 : 1; /*!< Ch0 repeat conversions, 1:enabled/0:disabled */ - __IO uint32_t CH1 : 1; /*!< Ch1 repeat conversions, 1:enabled/0:disabled */ - __IO uint32_t CH2 : 1; /*!< Ch2 repeat conversions, 1:enabled/0:disabled */ - __IO uint32_t CH3 : 1; /*!< Ch3 repeat conversions, 1:enabled/0:disabled */ - __IO uint32_t CH4 : 1; /*!< Ch4 repeat conversions, 1:enabled/0:disabled */ - } REPEAT_b; /*!< BitSize */ - }; - __IO uint32_t READING[5]; /*!< ADC channels 32-bit reading register. */ -} ADC_Type; - - -/* ================================================================================ */ -/* ================ EC_REG_BANK ================ */ -/* ================================================================================ */ - - -/** - * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK) - */ - -typedef struct { /*!< EC_REG_BANK Structure */ - __I uint32_t RESERVED[5]; - __IO uint8_t AHB_ERROR_CONTROL; /*!< 1: EC memory exceptions are disabled. */ - __I uint8_t RESERVED1[3]; - __IO uint32_t INTERRUPT_CONTROL; /*!< 1= Alternate NVIC vectors enabled */ - __IO uint32_t ETM_TRACE_ENABLE; /*!< 1= ARM TRACE port enabled */ - __IO uint32_t JTAG_Enable; /*!< 1= JTAG port enabled. */ - __I uint32_t RESERVED2; - __IO uint32_t WDT_EVENT_COUNT; /*!< [3:0]EC Rd/Wt are cleared to 0 on VCC1 POR */ - __I uint32_t RESERVED3[3]; - __IO uint32_t ADC_VREF_PD; /*!< [0:0] ADC VREF Power down. 0=on 1=off */ -} EC_REG_BANK_Type; - - -/* ================================================================================ */ -/* ================ JTAG ================ */ -/* ================================================================================ */ - - -/** - * @brief The Controller, which is an IEEE compliant JTAG Port, has implemented all - the mandatory JTAG instructions. This interface may be used to access the embedded controller's - test access port (TAP). (JTAG) - */ - -typedef struct { /*!< JTAG Structure */ - __IO uint32_t MESSAGE_OBF; /*!< JTAG Message OBF */ - __IO uint32_t MESSAGE_IBF; /*!< JTAG Message IBF */ - __IO uint8_t OBF_STATUS; /*!< JTAG OBF Status */ - __IO uint8_t IBF_STATUS; /*!< JTAG IBF Status */ - __I uint16_t RESERVED; - __IO uint32_t DBG_CTRL; /*!< JTAG DBG Ctrl */ -} JTAG_Type; - - -/*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/ -/** @addtogroup MEC1322_PKE Public Key Encryption (PKE) - @{ -*/ -typedef struct -{ - __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */ - __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */ - __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */ - __I uint32_t STATUS; /*!< Offset: 0x000C Status */ - __I uint32_t VERSION; /*!< Offset: 0x0010 Version */ - __IO uint32_t LOAD_MICRO_CODE; /*!< Offset: 0x0014 Load Micro Code */ -} PKE_TypeDef; -/*@}*/ /* end of group MEC1322_PKE */ - -/*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/ -/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG) - @{ -*/ -typedef struct -{ - __IO uint32_t CONTROL; /*!< Offset: 0x0000 Control */ - __I uint32_t FIFO_LEVEL; /*!< Offset: 0x0004 FIFO Level */ - __I uint32_t VERSION; /*!< Offset: 0x0008 Version */ -} TRNG_TypeDef; -/*@}*/ /* end of group MEC1322_TRNG */ - -/*------------- Hash Subsystem (HASH) -----------------------------*/ -/** @addtogroup MEC1322_HASH Hash Security (HASH) - @{ -*/ -typedef struct -{ - __IO uint32_t SHA_MODE; /*!< Offset: 0x0000 SHA Mode */ - __IO uint32_t NB_BLOCK; /*!< Offset: 0x0004 NbBlock */ - __IO uint32_t CONTROL; /*!< Offset: 0x0008 Config */ - __I uint32_t STATUS; /*!< Offset: 0x000C Status, Read to clear interrupt */ - __I uint32_t VERSION; /*!< Offset: 0x0010 Version */ - __I uint32_t GENERIC_VALUE; /*!< Offset: 0x0014 Generic Value */ - __IO uint32_t INIT_HASH_ADDR; /*!< Offset: 0x0018 Initial Hash value Address */ - __IO uint32_t DATA_SOURCE_ADDR; /*!< Offset: 0x001C Data to hash Address */ - __IO uint32_t HASH_RESULT_ADDR; /*!< Offset: 0x0020 Hash result address */ -} HASH_TypeDef; -/*@}*/ /* end of group MEC1322_HASH */ - - - -/*------------- Advanced Encryption Subsystem (AES) -----------------------------*/ -/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES) - @{ -*/ - -#define AES_MAX_KEY_WLEN (8) -#define AES_MAX_IV_WLEN (4) - -typedef struct -{ - __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */ - __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */ - __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */ - __I uint32_t STATUS; /*!< Offset: 0x000C Status */ - __I uint32_t VERSION; /*!< Offset: 0x0010 Version */ - __IO uint32_t NB_HEADER; /*!< Offset: 0x0014 Number of Headers */ - __IO uint32_t LAST_HEADER; /*!< Offset: 0x0018 Last Header */ - __IO uint32_t NB_BLOCK; /*!< Offset: 0x001C Number of Blocks */ - __IO uint32_t LAST_BLOCK; /*!< Offset: 0x0020 Last Block */ - __IO uint32_t DMA_IN; /*!< Offset: 0x0024 DMA Input Address */ - __IO uint32_t DMA_OUT; /*!< Offset: 0x0028 DMA Output Address */ - uint32_t RESERVEDA[(0xFC - 0x2C)/4 + 1]; - __IO uint32_t KEY1[AES_MAX_KEY_WLEN];/*!< Offset: 0x0100 KeyIn1[159:128] - !< Offset: 0x0104 KeyIn1[191:160] - !< Offset: 0x0108 KeyIn1[223:192] - !< Offset: 0x010C KeyIn1[255:224] - !< Offset: 0x0110 KeyIn1[31:0] - !< Offset: 0x0114 KeyIn1[63:32] - !< Offset: 0x0118 KeyIn1[95:64] - !< Offset: 0x011C KeyIn1[127:96] */ - __IO uint32_t IV[AES_MAX_IV_WLEN]; /*!< Offset: 0x0120 IV[31:0] - !< Offset: 0x0124 IV[63:32] - !< Offset: 0x0128 IV[95:64] - !< Offset: 0x012C IV[127:96] */ - uint32_t RESERVEDB[4]; - __IO uint32_t KEY2[AES_MAX_KEY_WLEN];/*!< Offset: 0x0140 KeyIn1[159:128] - !< Offset: 0x0144 KeyIn1[191:160] - !< Offset: 0x0148 KeyIn1[223:192] - !< Offset: 0x014C KeyIn1[255:224] - !< Offset: 0x0150 KeyIn1[31:0] - !< Offset: 0x0154 KeyIn1[63:32] - !< Offset: 0x0158 KeyIn1[95:64] - !< Offset: 0x015C KeyIn1[127:96] */ -} AES_TypeDef; -/*@}*/ /* end of group MEC1322_AES */ - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - -/* ================================================================================ */ -/* ================ struct 'PCR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PCR_EC_SLP_EN ------------------------------- */ -#define PCR_EC_SLP_EN_INT_SLP_EN_Pos (0UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bit 0) */ -#define PCR_EC_SLP_EN_INT_SLP_EN_Msk (0x1UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PECI_SLP_EN_Pos (1UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bit 1) */ -#define PCR_EC_SLP_EN_PECI_SLP_EN_Msk (0x2UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_TACH0_SLP_EN_Pos (2UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bit 2) */ -#define PCR_EC_SLP_EN_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PWM0_SLP_EN_Pos (4UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bit 4) */ -#define PCR_EC_SLP_EN_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PMC_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bit 5) */ -#define PCR_EC_SLP_EN_PMC_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_DMA_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bit 6) */ -#define PCR_EC_SLP_EN_DMA_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_TFDP_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bit 7) */ -#define PCR_EC_SLP_EN_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bit 8) */ -#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_WDT_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bit 9) */ -#define PCR_EC_SLP_EN_WDT_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_SMB0_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bit 10) */ -#define PCR_EC_SLP_EN_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_TACH1_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bit 11) */ -#define PCR_EC_SLP_EN_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PWM1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bit 20) */ -#define PCR_EC_SLP_EN_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PWM2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bit 21) */ -#define PCR_EC_SLP_EN_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_PWM3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bit 22) */ -#define PCR_EC_SLP_EN_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bit 29) */ -#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bit 30) */ -#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bit 31) */ -#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- PCR_EC_CLK_REQ_STS ----------------------------- */ -#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Pos (0UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bit 0) */ -#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Msk (0x1UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Pos (1UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bit 1) */ -#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Pos (2UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bit 2) */ -#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Pos (4UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bit 4) */ -#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bit 5) */ -#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bit 6) */ -#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bit 7) */ -#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bit 8) */ -#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bit 9) */ -#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bit 10) */ -#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bit 11) */ -#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bit 20) */ -#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bit 21) */ -#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bit 22) */ -#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bit 29) */ -#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bit 30) */ -#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bit 31) */ -#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PCR_HOST_SLP_EN ------------------------------ */ -#define PCR_HOST_SLP_EN_LPC_SLP_EN_Pos (0UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bit 0) */ -#define PCR_HOST_SLP_EN_LPC_SLP_EN_Msk (0x1UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Pos (1UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bit 1) */ -#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bit 12) */ -#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bit 13) */ -#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bit 14) */ -#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bit 15) */ -#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Pos (16UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bit 16) */ -#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_SLP_EN_RTC_SLP_EN_Pos (18UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bit 18) */ -#define PCR_HOST_SLP_EN_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ PCR_HOST_CLK_REQ ------------------------------ */ -#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Pos (0UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bit 0) */ -#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Pos (1UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bit 1) */ -#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bit 12) */ -#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bit 13) */ -#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bit 14) */ -#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bit 15) */ -#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bit 16) */ -#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Pos (18UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bit 18) */ -#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */ -#define PCR_SYS_SLP_CNTRL_ROSC_PD_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bit 0) */ -#define PCR_SYS_SLP_CNTRL_ROSC_PD_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bitfield-Mask: 0x01) */ -#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Pos (1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bit 1) */ -#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Msk (0x2UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bitfield-Mask: 0x01) */ -#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bit 2) */ -#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PCR_EC_SLP_EN2 ------------------------------- */ -#define PCR_EC_SLP_EN2_ADC_SLP_EN_Pos (3UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bit 3) */ -#define PCR_EC_SLP_EN2_ADC_SLP_EN_Msk (0x8UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bit 5) */ -#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bit 6) */ -#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bit 7) */ -#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bit 8) */ -#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bit 9) */ -#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bit 10) */ -#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bit 11) */ -#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bit 12) */ -#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Pos (13UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bit 13) */ -#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Pos (14UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bit 14) */ -#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Pos (15UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bit 15) */ -#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_LED0_SLP_EN_Pos (16UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bit 16) */ -#define PCR_EC_SLP_EN2_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_LED1_SLP_EN_Pos (17UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bit 17) */ -#define PCR_EC_SLP_EN2_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_LED2_SLP_EN_Pos (18UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bit 18) */ -#define PCR_EC_SLP_EN2_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_BCM_SLP_EN_Pos (19UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bit 19) */ -#define PCR_EC_SLP_EN2_BCM_SLP_EN_Msk (0x80000UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bit 20) */ -#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bit 21) */ -#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bit 22) */ -#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bit 23) */ -#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bit 24) */ -#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_SLP_EN2_LED3_SLP_EN_Pos (25UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bit 25) */ -#define PCR_EC_SLP_EN2_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bitfield-Mask: 0x01) */ - -/* ----------------------------- PCR_EC_CLK_REQ2_STS ---------------------------- */ -#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Pos (3UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bit 3) */ -#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bit 5) */ -#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bit 6) */ -#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bit 7) */ -#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bit 8) */ -#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bit 9) */ -#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bit 10) */ -#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bit 11) */ -#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Pos (12UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bit 12) */ -#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Msk (0x1000UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Pos (13UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bit 13) */ -#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Msk (0x2000UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Pos (14UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bit 14) */ -#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Msk (0x4000UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Pos (15UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bit 15) */ -#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Msk (0x8000UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Pos (16UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bit 16) */ -#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Msk (0x10000UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Pos (17UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bit 17) */ -#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Msk (0x20000UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Pos (18UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bit 18) */ -#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Msk (0x40000UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Pos (19UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bit 19) */ -#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Msk (0x80000UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bit 20) */ -#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bit 21) */ -#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bit 22) */ -#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Pos (23UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bit 23) */ -#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Msk (0x800000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Pos (24UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bit 24) */ -#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Msk (0x1000000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ -#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Pos (25UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bit 25) */ -#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Msk (0x2000000UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PCR_CHIP_OSC_ID ------------------------------ */ -#define PCR_CHIP_OSC_ID_OSC_LOCK_Pos (8UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bit 8) */ -#define PCR_CHIP_OSC_ID_OSC_LOCK_Msk (0x100UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bitfield-Mask: 0x01) */ - -/* ---------------------------- PCR_CHIP_PWR_RST_STS ---------------------------- */ -#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Pos (2UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bit 2) */ -#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Msk (0x4UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bitfield-Mask: 0x01) */ -#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Pos (3UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bit 3) */ -#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Msk (0x8UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bitfield-Mask: 0x01) */ -#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Pos (5UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bit 5) */ -#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Msk (0x20UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bitfield-Mask: 0x01) */ -#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Pos (6UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bit 6) */ -#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Msk (0x40UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bitfield-Mask: 0x01) */ -#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bit 10) */ -#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */ -#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */ -#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PCR_HOST_RST_EN ------------------------------ */ -#define PCR_HOST_RST_EN_LPC_RST_EN_Pos (0UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bit 0) */ -#define PCR_HOST_RST_EN_LPC_RST_EN_Msk (0x1UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_UART_0_RST_EN_Pos (1UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bit 1) */ -#define PCR_HOST_RST_EN_UART_0_RST_EN_Msk (0x2UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bit 12) */ -#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bit 13) */ -#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bit 14) */ -#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bit 15) */ -#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_KBCEM_RST_EN_Pos (16UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bit 16) */ -#define PCR_HOST_RST_EN_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_HOST_RST_EN_RTC_RST_EN_Pos (18UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bit 18) */ -#define PCR_HOST_RST_EN_RTC_RST_EN_Msk (0x40000UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PCR_EC_RST_EN ------------------------------- */ -#define PCR_EC_RST_EN_INT_RST_EN_Pos (0UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bit 0) */ -#define PCR_EC_RST_EN_INT_RST_EN_Msk (0x1UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PECI_RST_EN_Pos (1UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bit 1) */ -#define PCR_EC_RST_EN_PECI_RST_EN_Msk (0x2UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_TACH0_RST_EN_Pos (2UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bit 2) */ -#define PCR_EC_RST_EN_TACH0_RST_EN_Msk (0x4UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PWM0_RST_EN_Pos (4UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bit 4) */ -#define PCR_EC_RST_EN_PWM0_RST_EN_Msk (0x10UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PMC_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bit 5) */ -#define PCR_EC_RST_EN_PMC_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_DMA_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bit 6) */ -#define PCR_EC_RST_EN_DMA_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_TFDP_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bit 7) */ -#define PCR_EC_RST_EN_TFDP_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bit 8) */ -#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_WDT_RST_EN_Pos (9UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bit 9) */ -#define PCR_EC_RST_EN_WDT_RST_EN_Msk (0x200UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_SMB0_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bit 10) */ -#define PCR_EC_RST_EN_SMB0_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_TACH1_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bit 11) */ -#define PCR_EC_RST_EN_TACH1_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PWM1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bit 20) */ -#define PCR_EC_RST_EN_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PWM2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bit 21) */ -#define PCR_EC_RST_EN_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_PWM3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bit 22) */ -#define PCR_EC_RST_EN_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bit 29) */ -#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bit 30) */ -#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bit 31) */ -#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------- PCR_EC_RST_EN2 ------------------------------- */ -#define PCR_EC_RST_EN2_ADC_RST_EN_Pos (3UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bit 3) */ -#define PCR_EC_RST_EN2_ADC_RST_EN_Msk (0x8UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_PS2_0_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bit 5) */ -#define PCR_EC_RST_EN2_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_PS2_1_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bit 6) */ -#define PCR_EC_RST_EN2_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_PS2_2_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bit 7) */ -#define PCR_EC_RST_EN2_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_PS2_3_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bit 8) */ -#define PCR_EC_RST_EN2_PS2_3_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bit 9) */ -#define PCR_EC_RST_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_HTIMER_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bit 10) */ -#define PCR_EC_RST_EN2_HTIMER_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bit 11) */ -#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Pos (12UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bit 12) */ -#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Msk (0x1000UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_SMB1_RST_EN_Pos (13UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bit 13) */ -#define PCR_EC_RST_EN2_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_SMB2_RST_EN_Pos (14UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bit 14) */ -#define PCR_EC_RST_EN2_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_SMB3_RST_EN_Pos (15UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bit 15) */ -#define PCR_EC_RST_EN2_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_LED0_RST_EN_Pos (16UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bit 16) */ -#define PCR_EC_RST_EN2_LED0_RST_EN_Msk (0x10000UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_LED1_RST_EN_Pos (17UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bit 17) */ -#define PCR_EC_RST_EN2_LED1_RST_EN_Msk (0x20000UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_LED2_RST_EN_Pos (18UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bit 18) */ -#define PCR_EC_RST_EN2_LED2_RST_EN_Msk (0x40000UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_BCM_RST_EN_Pos (19UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bit 19) */ -#define PCR_EC_RST_EN2_BCM_RST_EN_Msk (0x80000UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_SPI1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bit 20) */ -#define PCR_EC_RST_EN2_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bit 21) */ -#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bit 22) */ -#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bit 23) */ -#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bit 24) */ -#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */ -#define PCR_EC_RST_EN2_LED3_RST_EN_Pos (25UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bit 25) */ -#define PCR_EC_RST_EN2_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bitfield-Mask: 0x01) */ - -/* ------------------------------ PCR_PWR_RST_CTRL ------------------------------ */ -#define PCR_PWR_RST_CTRL_IRESET_OUT_Pos (0UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bit 0) */ -#define PCR_PWR_RST_CTRL_IRESET_OUT_Msk (0x1UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'VBAT' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- VBAT_PFR_STS -------------------------------- */ -#define VBAT_PFR_STS_DET32K_IN_Pos (0UL) /*!< VBAT PFR_STS: DET32K_IN (Bit 0) */ -#define VBAT_PFR_STS_DET32K_IN_Msk (0x1UL) /*!< VBAT PFR_STS: DET32K_IN (Bitfield-Mask: 0x01) */ -#define VBAT_PFR_STS_WDT_Pos (5UL) /*!< VBAT PFR_STS: WDT (Bit 5) */ -#define VBAT_PFR_STS_WDT_Msk (0x20UL) /*!< VBAT PFR_STS: WDT (Bitfield-Mask: 0x01) */ -#define VBAT_PFR_STS_VBAT_RST_Pos (7UL) /*!< VBAT PFR_STS: VBAT_RST (Bit 7) */ -#define VBAT_PFR_STS_VBAT_RST_Msk (0x80UL) /*!< VBAT PFR_STS: VBAT_RST (Bitfield-Mask: 0x01) */ - -/* -------------------------------- VBAT_CLOCK_EN ------------------------------- */ -#define VBAT_CLOCK_EN_XOSEL_Pos (0UL) /*!< VBAT CLOCK_EN: XOSEL (Bit 0) */ -#define VBAT_CLOCK_EN_XOSEL_Msk (0x1UL) /*!< VBAT CLOCK_EN: XOSEL (Bitfield-Mask: 0x01) */ -#define VBAT_CLOCK_EN__32K_EN_Pos (1UL) /*!< VBAT CLOCK_EN: _32K_EN (Bit 1) */ -#define VBAT_CLOCK_EN__32K_EN_Msk (0x2UL) /*!< VBAT CLOCK_EN: _32K_EN (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'LPC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- LPC_BUS_MONITOR ------------------------------ */ -#define LPC_BUS_MONITOR_LRESET_STATUS_Pos (1UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bit 1) */ -#define LPC_BUS_MONITOR_LRESET_STATUS_Msk (0x2UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bitfield-Mask: 0x01) */ - -/* ----------------------------- LPC_HOST_BUS_ERROR ----------------------------- */ -#define LPC_HOST_BUS_ERROR_LPC_ERR_Pos (0UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bit 0) */ -#define LPC_HOST_BUS_ERROR_LPC_ERR_Msk (0x1UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bitfield-Mask: 0x01) */ -#define LPC_HOST_BUS_ERROR_EN_ERR_Pos (1UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bit 1) */ -#define LPC_HOST_BUS_ERROR_EN_ERR_Msk (0x2UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bitfield-Mask: 0x01) */ -#define LPC_HOST_BUS_ERROR_BAR_ERR_Pos (2UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bit 2) */ -#define LPC_HOST_BUS_ERROR_BAR_ERR_Msk (0x4UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bitfield-Mask: 0x01) */ -#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Pos (3UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bit 3) */ -#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Msk (0x8UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bitfield-Mask: 0x01) */ -#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Pos (4UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bit 4) */ -#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Msk (0x10UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bitfield-Mask: 0x01) */ -#define LPC_HOST_BUS_ERROR_DMA_ERR_Pos (5UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bit 5) */ -#define LPC_HOST_BUS_ERROR_DMA_ERR_Msk (0x20UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bitfield-Mask: 0x01) */ -#define LPC_HOST_BUS_ERROR_ERR_ADDR_Pos (8UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bit 8) */ -#define LPC_HOST_BUS_ERROR_ERR_ADDR_Msk (0xffffff00UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bitfield-Mask: 0xffffff) */ - -/* -------------------------------- LPC_EC_SERIRQ ------------------------------- */ -#define LPC_EC_SERIRQ_EC_IRQ_Pos (0UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bit 0) */ -#define LPC_EC_SERIRQ_EC_IRQ_Msk (0x1UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bitfield-Mask: 0x01) */ - -/* -------------------------------- LPC_CLK_CTRL -------------------------------- */ -#define LPC_CLK_CTRL_CR_Pos (0UL) /*!< LPC CLK_CTRL: CR (Bit 0) */ -#define LPC_CLK_CTRL_CR_Msk (0x3UL) /*!< LPC CLK_CTRL: CR (Bitfield-Mask: 0x03) */ -#define LPC_CLK_CTRL_HANDSHAKE_Pos (2UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bit 2) */ -#define LPC_CLK_CTRL_HANDSHAKE_Msk (0x4UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'LPC_CONFIG' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- LPC_CONFIG_SIRQ ------------------------------ */ -#define LPC_CONFIG_SIRQ_FRAME_Pos (0UL) /*!< LPC_CONFIG SIRQ: FRAME (Bit 0) */ -#define LPC_CONFIG_SIRQ_FRAME_Msk (0x3fUL) /*!< LPC_CONFIG SIRQ: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_SIRQ_DEVICE_Pos (6UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bit 6) */ -#define LPC_CONFIG_SIRQ_DEVICE_Msk (0x40UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_SIRQ_SELECT_Pos (7UL) /*!< LPC_CONFIG SIRQ: SELECT (Bit 7) */ -#define LPC_CONFIG_SIRQ_SELECT_Msk (0x80UL) /*!< LPC_CONFIG SIRQ: SELECT (Bitfield-Mask: 0x01) */ - -/* ----------------------------- LPC_CONFIG_LPC_BAR ----------------------------- */ -#define LPC_CONFIG_LPC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LPC_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_LPC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LPC_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_LPC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_LPC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_LPC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_LPC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_LPC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_LPC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ------------------------------ LPC_CONFIG_EM_BAR ----------------------------- */ -#define LPC_CONFIG_EM_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EM_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_EM_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EM_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_EM_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_EM_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_EM_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_EM_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_EM_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EM_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_EM_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EM_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_UART_BAR ---------------------------- */ -#define LPC_CONFIG_UART_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG UART_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_UART_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG UART_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_UART_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_UART_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_UART_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_UART_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_UART_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG UART_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_UART_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG UART_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_KBC_BAR ----------------------------- */ -#define LPC_CONFIG_KBC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG KBC_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_KBC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG KBC_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_KBC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_KBC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_KBC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_KBC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_KBC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_KBC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_EC0_BAR ----------------------------- */ -#define LPC_CONFIG_EC0_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC0_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_EC0_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC0_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_EC0_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_EC0_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_EC0_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_EC0_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_EC0_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_EC0_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_EC1_BAR ----------------------------- */ -#define LPC_CONFIG_EC1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC1_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_EC1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC1_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_EC1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_EC1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_EC1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_EC1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_EC1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_EC1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_PM1_BAR ----------------------------- */ -#define LPC_CONFIG_PM1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG PM1_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_PM1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG PM1_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_PM1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_PM1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_PM1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_PM1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_PM1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_PM1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_LGC_BAR ----------------------------- */ -#define LPC_CONFIG_LGC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LGC_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_LGC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LGC_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_LGC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_LGC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_LGC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_LGC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_LGC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_LGC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_MBX_BAR ----------------------------- */ -#define LPC_CONFIG_MBX_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG MBX_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_MBX_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG MBX_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_MBX_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_MBX_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_MBX_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_MBX_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_MBX_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_MBX_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - -/* ----------------------------- LPC_CONFIG_RTC_BAR ----------------------------- */ -#define LPC_CONFIG_RTC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG RTC_BAR: MASK (Bit 0) */ -#define LPC_CONFIG_RTC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG RTC_BAR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_RTC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bit 8) */ -#define LPC_CONFIG_RTC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_RTC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bit 14) */ -#define LPC_CONFIG_RTC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_RTC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bit 15) */ -#define LPC_CONFIG_RTC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bitfield-Mask: 0x01) */ -#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bit 16) */ -#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'MEM_BAR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- MEM_BAR_CR --------------------------------- */ -#define MEM_BAR_CR_MASK_Pos (0UL) /*!< MEM_BAR CR: MASK (Bit 0) */ -#define MEM_BAR_CR_MASK_Msk (0xffUL) /*!< MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ -#define MEM_BAR_CR_FRAME_Pos (8UL) /*!< MEM_BAR CR: FRAME (Bit 8) */ -#define MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ -#define MEM_BAR_CR_VALID_Pos (15UL) /*!< MEM_BAR CR: VALID (Bit 15) */ -#define MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'MBX_MEM_BAR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- LPC_CONFIG_MBX_MEM_BAR_CR ------------------------- */ -#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bit 0) */ -#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bit 8) */ -#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bit 15) */ -#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'EC0_MEM_BAR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- LPC_CONFIG_EC0_MEM_BAR_CR ------------------------- */ -#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bit 0) */ -#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bit 8) */ -#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bit 15) */ -#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'EC1_MEM_BAR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- LPC_CONFIG_EC1_MEM_BAR_CR ------------------------- */ -#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bit 0) */ -#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bit 8) */ -#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bit 15) */ -#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'EMI_MEM_BAR' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------- LPC_CONFIG_EMI_MEM_BAR_CR ------------------------- */ -#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bit 0) */ -#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ -#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bit 8) */ -#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ -#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bit 15) */ -#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'EMI' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- EMI_EC_ADDRESS ------------------------------- */ -#define EMI_EC_ADDRESS_ACCESS_TYPE_Pos (0UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bit 0) */ -#define EMI_EC_ADDRESS_ACCESS_TYPE_Msk (0x3UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bitfield-Mask: 0x03) */ -#define EMI_EC_ADDRESS_EC_ADDRESS_Pos (2UL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bit 2) */ -#define EMI_EC_ADDRESS_EC_ADDRESS_Msk (0x7ffcUL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bitfield-Mask: 0x1fff) */ -#define EMI_EC_ADDRESS_REGION_Pos (15UL) /*!< EMI EC_ADDRESS: REGION (Bit 15) */ -#define EMI_EC_ADDRESS_REGION_Msk (0x8000UL) /*!< EMI EC_ADDRESS: REGION (Bitfield-Mask: 0x01) */ - -/* --------------------------------- EMI_EC_SWI --------------------------------- */ -#define EMI_EC_SWI_EC_WR_Pos (0UL) /*!< EMI EC_SWI: EC_WR (Bit 0) */ -#define EMI_EC_SWI_EC_WR_Msk (0x1UL) /*!< EMI EC_SWI: EC_WR (Bitfield-Mask: 0x01) */ -#define EMI_EC_SWI_NOTIFICATION_Pos (1UL) /*!< EMI EC_SWI: NOTIFICATION (Bit 1) */ -#define EMI_EC_SWI_NOTIFICATION_Msk (0xfffeUL) /*!< EMI EC_SWI: NOTIFICATION (Bitfield-Mask: 0x7fff) */ - - -/* ================================================================================ */ -/* ================ struct 'ACPI_EC0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- ACPI_EC0_OS_STATUS ----------------------------- */ -#define ACPI_EC0_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bit 0) */ -#define ACPI_EC0_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bit 1) */ -#define ACPI_EC0_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bit 2) */ -#define ACPI_EC0_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bit 3) */ -#define ACPI_EC0_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bit 4) */ -#define ACPI_EC0_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bit 5) */ -#define ACPI_EC0_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bit 6) */ -#define ACPI_EC0_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bit 7) */ -#define ACPI_EC0_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ACPI_EC0_EC_STATUS ----------------------------- */ -#define ACPI_EC0_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bit 0) */ -#define ACPI_EC0_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bit 1) */ -#define ACPI_EC0_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bit 2) */ -#define ACPI_EC0_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bit 3) */ -#define ACPI_EC0_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bit 4) */ -#define ACPI_EC0_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bit 5) */ -#define ACPI_EC0_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bit 6) */ -#define ACPI_EC0_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC0_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bit 7) */ -#define ACPI_EC0_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'ACPI_EC1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- ACPI_EC1_OS_STATUS ----------------------------- */ -#define ACPI_EC1_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0) */ -#define ACPI_EC1_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1) */ -#define ACPI_EC1_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2) */ -#define ACPI_EC1_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3) */ -#define ACPI_EC1_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4) */ -#define ACPI_EC1_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5) */ -#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6) */ -#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7) */ -#define ACPI_EC1_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */ - -/* ----------------------------- ACPI_EC1_EC_STATUS ----------------------------- */ -#define ACPI_EC1_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0) */ -#define ACPI_EC1_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1) */ -#define ACPI_EC1_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2) */ -#define ACPI_EC1_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3) */ -#define ACPI_EC1_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4) */ -#define ACPI_EC1_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5) */ -#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6) */ -#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ -#define ACPI_EC1_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7) */ -#define ACPI_EC1_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'KBC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- KBC_RD_PORT64_STATUS ---------------------------- */ -#define KBC_RD_PORT64_STATUS_OBF_Pos (0UL) /*!< KBC RD_PORT64_STATUS: OBF (Bit 0) */ -#define KBC_RD_PORT64_STATUS_OBF_Msk (0x1UL) /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01) */ -#define KBC_RD_PORT64_STATUS_IBF_Pos (1UL) /*!< KBC RD_PORT64_STATUS: IBF (Bit 1) */ -#define KBC_RD_PORT64_STATUS_IBF_Msk (0x2UL) /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01) */ -#define KBC_RD_PORT64_STATUS_UD0_Pos (2UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2) */ -#define KBC_RD_PORT64_STATUS_UD0_Msk (0x4UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01) */ -#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos (3UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3) */ -#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01) */ -#define KBC_RD_PORT64_STATUS_UD1_Pos (4UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4) */ -#define KBC_RD_PORT64_STATUS_UD1_Msk (0x10UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01) */ -#define KBC_RD_PORT64_STATUS_AUXOBF_Pos (5UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5) */ -#define KBC_RD_PORT64_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01) */ -#define KBC_RD_PORT64_STATUS_UD2_Pos (6UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6) */ -#define KBC_RD_PORT64_STATUS_UD2_Msk (0xc0UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03) */ - -/* --------------------------------- KBC_STATUS --------------------------------- */ -#define KBC_STATUS_OBF_Pos (0UL) /*!< KBC STATUS: OBF (Bit 0) */ -#define KBC_STATUS_OBF_Msk (0x1UL) /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01) */ -#define KBC_STATUS_IBF_Pos (1UL) /*!< KBC STATUS: IBF (Bit 1) */ -#define KBC_STATUS_IBF_Msk (0x2UL) /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01) */ -#define KBC_STATUS_UD0_Pos (2UL) /*!< KBC STATUS: UD0 (Bit 2) */ -#define KBC_STATUS_UD0_Msk (0x4UL) /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01) */ -#define KBC_STATUS_CMDnDATA_Pos (3UL) /*!< KBC STATUS: CMDnDATA (Bit 3) */ -#define KBC_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01) */ -#define KBC_STATUS_UD1_Pos (4UL) /*!< KBC STATUS: UD1 (Bit 4) */ -#define KBC_STATUS_UD1_Msk (0x10UL) /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01) */ -#define KBC_STATUS_AUXOBF_Pos (5UL) /*!< KBC STATUS: AUXOBF (Bit 5) */ -#define KBC_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01) */ -#define KBC_STATUS_UD2_Pos (6UL) /*!< KBC STATUS: UD2 (Bit 6) */ -#define KBC_STATUS_UD2_Msk (0xc0UL) /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03) */ - -/* --------------------------------- KBC_CONTROL -------------------------------- */ -#define KBC_CONTROL_UD3_Pos (0UL) /*!< KBC CONTROL: UD3 (Bit 0) */ -#define KBC_CONTROL_UD3_Msk (0x1UL) /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01) */ -#define KBC_CONTROL_SAEN_Pos (1UL) /*!< KBC CONTROL: SAEN (Bit 1) */ -#define KBC_CONTROL_SAEN_Msk (0x2UL) /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01) */ -#define KBC_CONTROL_PCOBFEN_Pos (2UL) /*!< KBC CONTROL: PCOBFEN (Bit 2) */ -#define KBC_CONTROL_PCOBFEN_Msk (0x4UL) /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01) */ -#define KBC_CONTROL_UD4_Pos (3UL) /*!< KBC CONTROL: UD4 (Bit 3) */ -#define KBC_CONTROL_UD4_Msk (0x18UL) /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03) */ -#define KBC_CONTROL_OBFEN_Pos (5UL) /*!< KBC CONTROL: OBFEN (Bit 5) */ -#define KBC_CONTROL_OBFEN_Msk (0x20UL) /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01) */ -#define KBC_CONTROL_UD5_Pos (6UL) /*!< KBC CONTROL: UD5 (Bit 6) */ -#define KBC_CONTROL_UD5_Msk (0x40UL) /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01) */ -#define KBC_CONTROL_AUXH_Pos (7UL) /*!< KBC CONTROL: AUXH (Bit 7) */ -#define KBC_CONTROL_AUXH_Msk (0x80UL) /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'PORT92' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PORT92_PORT92 ------------------------------- */ -#define PORT92_PORT92_ALT_CPU_RESET_Pos (0UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0) */ -#define PORT92_PORT92_ALT_CPU_RESET_Msk (0x1UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01) */ -#define PORT92_PORT92_ALT_GATE_A20_Pos (1UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1) */ -#define PORT92_PORT92_ALT_GATE_A20_Msk (0x2UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'MBX' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- MBX_SMI_SOURCE ------------------------------- */ -#define MBX_SMI_SOURCE_EC_WR_Pos (0UL) /*!< MBX SMI_SOURCE: EC_WR (Bit 0) */ -#define MBX_SMI_SOURCE_EC_WR_Msk (0x1UL) /*!< MBX SMI_SOURCE: EC_WR (Bitfield-Mask: 0x01) */ -#define MBX_SMI_SOURCE_EC_SMI_Pos (1UL) /*!< MBX SMI_SOURCE: EC_SMI (Bit 1) */ -#define MBX_SMI_SOURCE_EC_SMI_Msk (0xfeUL) /*!< MBX SMI_SOURCE: EC_SMI (Bitfield-Mask: 0x7f) */ - -/* -------------------------------- MBX_SMI_MASK -------------------------------- */ -#define MBX_SMI_MASK_EC_WR_EN_Pos (0UL) /*!< MBX SMI_MASK: EC_WR_EN (Bit 0) */ -#define MBX_SMI_MASK_EC_WR_EN_Msk (0x1UL) /*!< MBX SMI_MASK: EC_WR_EN (Bitfield-Mask: 0x01) */ -#define MBX_SMI_MASK_EC_SMI_EN_Pos (1UL) /*!< MBX SMI_MASK: EC_SMI_EN (Bit 1) */ -#define MBX_SMI_MASK_EC_SMI_EN_Msk (0xfeUL) /*!< MBX SMI_MASK: EC_SMI_EN (Bitfield-Mask: 0x7f) */ - - -/* ================================================================================ */ -/* ================ struct 'PM1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------------- PM1_STS2 ---------------------------------- */ -#define PM1_STS2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS2: PWRBTN_STS (Bit 0) */ -#define PM1_STS2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS2: PWRBTN_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS2: SLPBTN_STS (Bit 1) */ -#define PM1_STS2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS2: SLPBTN_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS2_RTC_STS_Pos (2UL) /*!< PM1 STS2: RTC_STS (Bit 2) */ -#define PM1_STS2_RTC_STS_Msk (0x4UL) /*!< PM1 STS2: RTC_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS2: PWRBTNOR_STS (Bit 3) */ -#define PM1_STS2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS2_WAK_STS_Pos (7UL) /*!< PM1 STS2: WAK_STS (Bit 7) */ -#define PM1_STS2_WAK_STS_Msk (0x80UL) /*!< PM1 STS2: WAK_STS (Bitfield-Mask: 0x01) */ - -/* ----------------------------------- PM1_EN2 ---------------------------------- */ -#define PM1_EN2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN2: PWRBTN_EN (Bit 0) */ -#define PM1_EN2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN2: PWRBTN_EN (Bitfield-Mask: 0x01) */ -#define PM1_EN2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN2: SLPBTN_EN (Bit 1) */ -#define PM1_EN2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN2: SLPBTN_EN (Bitfield-Mask: 0x01) */ -#define PM1_EN2_RTC_EN_Pos (2UL) /*!< PM1 EN2: RTC_EN (Bit 2) */ -#define PM1_EN2_RTC_EN_Msk (0x4UL) /*!< PM1 EN2: RTC_EN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PM1_CTRL2 --------------------------------- */ -#define PM1_CTRL2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bit 1) */ -#define PM1_CTRL2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */ -#define PM1_CTRL2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL2: SLP_TYP (Bit 2) */ -#define PM1_CTRL2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL2: SLP_TYP (Bitfield-Mask: 0x07) */ -#define PM1_CTRL2_SLP_EN_Pos (5UL) /*!< PM1 CTRL2: SLP_EN (Bit 5) */ -#define PM1_CTRL2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL2: SLP_EN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PM1_STS_2 --------------------------------- */ -#define PM1_STS_2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS_2: PWRBTN_STS (Bit 0) */ -#define PM1_STS_2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS_2: PWRBTN_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS_2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS_2: SLPBTN_STS (Bit 1) */ -#define PM1_STS_2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS_2: SLPBTN_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS_2_RTC_STS_Pos (2UL) /*!< PM1 STS_2: RTC_STS (Bit 2) */ -#define PM1_STS_2_RTC_STS_Msk (0x4UL) /*!< PM1 STS_2: RTC_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS_2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bit 3) */ -#define PM1_STS_2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */ -#define PM1_STS_2_WAK_STS_Pos (7UL) /*!< PM1 STS_2: WAK_STS (Bit 7) */ -#define PM1_STS_2_WAK_STS_Msk (0x80UL) /*!< PM1 STS_2: WAK_STS (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- PM1_EN_2 ---------------------------------- */ -#define PM1_EN_2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN_2: PWRBTN_EN (Bit 0) */ -#define PM1_EN_2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN_2: PWRBTN_EN (Bitfield-Mask: 0x01) */ -#define PM1_EN_2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN_2: SLPBTN_EN (Bit 1) */ -#define PM1_EN_2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN_2: SLPBTN_EN (Bitfield-Mask: 0x01) */ -#define PM1_EN_2_RTC_EN_Pos (2UL) /*!< PM1 EN_2: RTC_EN (Bit 2) */ -#define PM1_EN_2_RTC_EN_Msk (0x4UL) /*!< PM1 EN_2: RTC_EN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PM1_CTRL_2 --------------------------------- */ -#define PM1_CTRL_2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bit 1) */ -#define PM1_CTRL_2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */ -#define PM1_CTRL_2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL_2: SLP_TYP (Bit 2) */ -#define PM1_CTRL_2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL_2: SLP_TYP (Bitfield-Mask: 0x07) */ -#define PM1_CTRL_2_SLP_EN_Pos (5UL) /*!< PM1 CTRL_2: SLP_EN (Bit 5) */ -#define PM1_CTRL_2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL_2: SLP_EN (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'UART' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- UART_INT_EN -------------------------------- */ -#define UART_INT_EN_ERDAI_Pos (0UL) /*!< UART INT_EN: ERDAI (Bit 0) */ -#define UART_INT_EN_ERDAI_Msk (0x1UL) /*!< UART INT_EN: ERDAI (Bitfield-Mask: 0x01) */ -#define UART_INT_EN_ETHREI_Pos (1UL) /*!< UART INT_EN: ETHREI (Bit 1) */ -#define UART_INT_EN_ETHREI_Msk (0x2UL) /*!< UART INT_EN: ETHREI (Bitfield-Mask: 0x01) */ -#define UART_INT_EN_ELSI_Pos (2UL) /*!< UART INT_EN: ELSI (Bit 2) */ -#define UART_INT_EN_ELSI_Msk (0x4UL) /*!< UART INT_EN: ELSI (Bitfield-Mask: 0x01) */ -#define UART_INT_EN_EMSI_Pos (3UL) /*!< UART INT_EN: EMSI (Bit 3) */ -#define UART_INT_EN_EMSI_Msk (0x8UL) /*!< UART INT_EN: EMSI (Bitfield-Mask: 0x01) */ - -/* -------------------------------- UART_FIFO_CR -------------------------------- */ -#define UART_FIFO_CR_EXRF_Pos (0UL) /*!< UART FIFO_CR: EXRF (Bit 0) */ -#define UART_FIFO_CR_EXRF_Msk (0x1UL) /*!< UART FIFO_CR: EXRF (Bitfield-Mask: 0x01) */ -#define UART_FIFO_CR_CLEAR_RECV_FIFO_Pos (1UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bit 1) */ -#define UART_FIFO_CR_CLEAR_RECV_FIFO_Msk (0x2UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bitfield-Mask: 0x01) */ -#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Pos (2UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bit 2) */ -#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Msk (0x4UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bitfield-Mask: 0x01) */ -#define UART_FIFO_CR_DMA_MODE_SELECT_Pos (3UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bit 3) */ -#define UART_FIFO_CR_DMA_MODE_SELECT_Msk (0x8UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bitfield-Mask: 0x01) */ -#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Pos (6UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bit 6) */ -#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Msk (0xc0UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bitfield-Mask: 0x03) */ - -/* --------------------------------- UART_INT_ID -------------------------------- */ -#define UART_INT_ID_IPEND_Pos (0UL) /*!< UART INT_ID: IPEND (Bit 0) */ -#define UART_INT_ID_IPEND_Msk (0x1UL) /*!< UART INT_ID: IPEND (Bitfield-Mask: 0x01) */ -#define UART_INT_ID_INTID_Pos (1UL) /*!< UART INT_ID: INTID (Bit 1) */ -#define UART_INT_ID_INTID_Msk (0xeUL) /*!< UART INT_ID: INTID (Bitfield-Mask: 0x07) */ -#define UART_INT_ID_FIFO_EN_Pos (6UL) /*!< UART INT_ID: FIFO_EN (Bit 6) */ -#define UART_INT_ID_FIFO_EN_Msk (0xc0UL) /*!< UART INT_ID: FIFO_EN (Bitfield-Mask: 0x03) */ - -/* -------------------------------- UART_LINE_CR -------------------------------- */ -#define UART_LINE_CR_WORD_LENGTH_Pos (0UL) /*!< UART LINE_CR: WORD_LENGTH (Bit 0) */ -#define UART_LINE_CR_WORD_LENGTH_Msk (0x3UL) /*!< UART LINE_CR: WORD_LENGTH (Bitfield-Mask: 0x03) */ -#define UART_LINE_CR_STOP_BITS_Pos (2UL) /*!< UART LINE_CR: STOP_BITS (Bit 2) */ -#define UART_LINE_CR_STOP_BITS_Msk (0x4UL) /*!< UART LINE_CR: STOP_BITS (Bitfield-Mask: 0x01) */ -#define UART_LINE_CR_ENABLE_PARITY_Pos (3UL) /*!< UART LINE_CR: ENABLE_PARITY (Bit 3) */ -#define UART_LINE_CR_ENABLE_PARITY_Msk (0x8UL) /*!< UART LINE_CR: ENABLE_PARITY (Bitfield-Mask: 0x01) */ -#define UART_LINE_CR_PARITY_SELECT_Pos (4UL) /*!< UART LINE_CR: PARITY_SELECT (Bit 4) */ -#define UART_LINE_CR_PARITY_SELECT_Msk (0x10UL) /*!< UART LINE_CR: PARITY_SELECT (Bitfield-Mask: 0x01) */ -#define UART_LINE_CR_STICK_PARITY_Pos (5UL) /*!< UART LINE_CR: STICK_PARITY (Bit 5) */ -#define UART_LINE_CR_STICK_PARITY_Msk (0x20UL) /*!< UART LINE_CR: STICK_PARITY (Bitfield-Mask: 0x01) */ -#define UART_LINE_CR_BREAK_CONTROL_Pos (6UL) /*!< UART LINE_CR: BREAK_CONTROL (Bit 6) */ -#define UART_LINE_CR_BREAK_CONTROL_Msk (0x40UL) /*!< UART LINE_CR: BREAK_CONTROL (Bitfield-Mask: 0x01) */ -#define UART_LINE_CR_DLAB_Pos (7UL) /*!< UART LINE_CR: DLAB (Bit 7) */ -#define UART_LINE_CR_DLAB_Msk (0x80UL) /*!< UART LINE_CR: DLAB (Bitfield-Mask: 0x01) */ - -/* -------------------------------- UART_MODEM_CR ------------------------------- */ -#define UART_MODEM_CR_DTR_Pos (0UL) /*!< UART MODEM_CR: DTR (Bit 0) */ -#define UART_MODEM_CR_DTR_Msk (0x1UL) /*!< UART MODEM_CR: DTR (Bitfield-Mask: 0x01) */ -#define UART_MODEM_CR_RTS_Pos (1UL) /*!< UART MODEM_CR: RTS (Bit 1) */ -#define UART_MODEM_CR_RTS_Msk (0x2UL) /*!< UART MODEM_CR: RTS (Bitfield-Mask: 0x01) */ -#define UART_MODEM_CR_OUT1_Pos (2UL) /*!< UART MODEM_CR: OUT1 (Bit 2) */ -#define UART_MODEM_CR_OUT1_Msk (0x4UL) /*!< UART MODEM_CR: OUT1 (Bitfield-Mask: 0x01) */ -#define UART_MODEM_CR_OUT2_Pos (3UL) /*!< UART MODEM_CR: OUT2 (Bit 3) */ -#define UART_MODEM_CR_OUT2_Msk (0x8UL) /*!< UART MODEM_CR: OUT2 (Bitfield-Mask: 0x01) */ -#define UART_MODEM_CR_LOOPBACK_Pos (4UL) /*!< UART MODEM_CR: LOOPBACK (Bit 4) */ -#define UART_MODEM_CR_LOOPBACK_Msk (0x10UL) /*!< UART MODEM_CR: LOOPBACK (Bitfield-Mask: 0x01) */ - -/* -------------------------------- UART_LINE_STS ------------------------------- */ -#define UART_LINE_STS_DATA_READY_Pos (0UL) /*!< UART LINE_STS: DATA_READY (Bit 0) */ -#define UART_LINE_STS_DATA_READY_Msk (0x1UL) /*!< UART LINE_STS: DATA_READY (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_OVERRUN_Pos (1UL) /*!< UART LINE_STS: OVERRUN (Bit 1) */ -#define UART_LINE_STS_OVERRUN_Msk (0x2UL) /*!< UART LINE_STS: OVERRUN (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_PE_Pos (2UL) /*!< UART LINE_STS: PE (Bit 2) */ -#define UART_LINE_STS_PE_Msk (0x4UL) /*!< UART LINE_STS: PE (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_FRAME_ERROR_Pos (3UL) /*!< UART LINE_STS: FRAME_ERROR (Bit 3) */ -#define UART_LINE_STS_FRAME_ERROR_Msk (0x8UL) /*!< UART LINE_STS: FRAME_ERROR (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_BREAK_INTERRUPT_Pos (4UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bit 4) */ -#define UART_LINE_STS_BREAK_INTERRUPT_Msk (0x10UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_TRANSMIT_EMPTY_Pos (5UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bit 5) */ -#define UART_LINE_STS_TRANSMIT_EMPTY_Msk (0x20UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_TRANSMIT_ERROR_Pos (6UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bit 6) */ -#define UART_LINE_STS_TRANSMIT_ERROR_Msk (0x40UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bitfield-Mask: 0x01) */ -#define UART_LINE_STS_FIFO_ERROR_Pos (7UL) /*!< UART LINE_STS: FIFO_ERROR (Bit 7) */ -#define UART_LINE_STS_FIFO_ERROR_Msk (0x80UL) /*!< UART LINE_STS: FIFO_ERROR (Bitfield-Mask: 0x01) */ - -/* ------------------------------- UART_MODEM_STS ------------------------------- */ -#define UART_MODEM_STS_CTS_Pos (0UL) /*!< UART MODEM_STS: CTS (Bit 0) */ -#define UART_MODEM_STS_CTS_Msk (0x1UL) /*!< UART MODEM_STS: CTS (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_DSR_Pos (1UL) /*!< UART MODEM_STS: DSR (Bit 1) */ -#define UART_MODEM_STS_DSR_Msk (0x2UL) /*!< UART MODEM_STS: DSR (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_RI_Pos (2UL) /*!< UART MODEM_STS: RI (Bit 2) */ -#define UART_MODEM_STS_RI_Msk (0x4UL) /*!< UART MODEM_STS: RI (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_DCD_Pos (3UL) /*!< UART MODEM_STS: DCD (Bit 3) */ -#define UART_MODEM_STS_DCD_Msk (0x8UL) /*!< UART MODEM_STS: DCD (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_nCTS_Pos (4UL) /*!< UART MODEM_STS: nCTS (Bit 4) */ -#define UART_MODEM_STS_nCTS_Msk (0x10UL) /*!< UART MODEM_STS: nCTS (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_nDSR_Pos (5UL) /*!< UART MODEM_STS: nDSR (Bit 5) */ -#define UART_MODEM_STS_nDSR_Msk (0x20UL) /*!< UART MODEM_STS: nDSR (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_nRI_Pos (6UL) /*!< UART MODEM_STS: nRI (Bit 6) */ -#define UART_MODEM_STS_nRI_Msk (0x40UL) /*!< UART MODEM_STS: nRI (Bitfield-Mask: 0x01) */ -#define UART_MODEM_STS_nDCD_Pos (7UL) /*!< UART MODEM_STS: nDCD (Bit 7) */ -#define UART_MODEM_STS_nDCD_Msk (0x80UL) /*!< UART MODEM_STS: nDCD (Bitfield-Mask: 0x01) */ - -/* --------------------------------- UART_CONFIG -------------------------------- */ -#define UART_CONFIG_CLK_SRC_Pos (0UL) /*!< UART CONFIG: CLK_SRC (Bit 0) */ -#define UART_CONFIG_CLK_SRC_Msk (0x1UL) /*!< UART CONFIG: CLK_SRC (Bitfield-Mask: 0x01) */ -#define UART_CONFIG_POWER_Pos (1UL) /*!< UART CONFIG: POWER (Bit 1) */ -#define UART_CONFIG_POWER_Msk (0x2UL) /*!< UART CONFIG: POWER (Bitfield-Mask: 0x01) */ -#define UART_CONFIG_POLARITY_Pos (2UL) /*!< UART CONFIG: POLARITY (Bit 2) */ -#define UART_CONFIG_POLARITY_Msk (0x4UL) /*!< UART CONFIG: POLARITY (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'WDT' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- WDT_CONTROL -------------------------------- */ -#define WDT_CONTROL_ENABLE_Pos (0UL) /*!< WDT CONTROL: ENABLE (Bit 0) */ -#define WDT_CONTROL_ENABLE_Msk (0x1UL) /*!< WDT CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define WDT_CONTROL_STATUS_Pos (1UL) /*!< WDT CONTROL: STATUS (Bit 1) */ -#define WDT_CONTROL_STATUS_Msk (0x2UL) /*!< WDT CONTROL: STATUS (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER_16_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TIMER_16_0_CONTROL ----------------------------- */ -#define TIMER_16_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bit 0) */ -#define TIMER_16_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bit 2) */ -#define TIMER_16_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bit 3) */ -#define TIMER_16_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bit 4) */ -#define TIMER_16_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_START_Pos (5UL) /*!< TIMER_16_0 CONTROL: START (Bit 5) */ -#define TIMER_16_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_0 CONTROL: START (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bit 6) */ -#define TIMER_16_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_0 CONTROL: HALT (Bit 7) */ -#define TIMER_16_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_0 CONTROL: HALT (Bitfield-Mask: 0x01) */ -#define TIMER_16_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bit 16) */ -#define TIMER_16_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER_16_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TIMER_16_1_CONTROL ----------------------------- */ -#define TIMER_16_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bit 0) */ -#define TIMER_16_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bit 2) */ -#define TIMER_16_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bit 3) */ -#define TIMER_16_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bit 4) */ -#define TIMER_16_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_START_Pos (5UL) /*!< TIMER_16_1 CONTROL: START (Bit 5) */ -#define TIMER_16_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_1 CONTROL: START (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bit 6) */ -#define TIMER_16_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_1 CONTROL: HALT (Bit 7) */ -#define TIMER_16_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_1 CONTROL: HALT (Bitfield-Mask: 0x01) */ -#define TIMER_16_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bit 16) */ -#define TIMER_16_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER_16_2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TIMER_16_2_CONTROL ----------------------------- */ -#define TIMER_16_2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bit 0) */ -#define TIMER_16_2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bit 2) */ -#define TIMER_16_2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bit 3) */ -#define TIMER_16_2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bit 4) */ -#define TIMER_16_2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_START_Pos (5UL) /*!< TIMER_16_2 CONTROL: START (Bit 5) */ -#define TIMER_16_2_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_2 CONTROL: START (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bit 6) */ -#define TIMER_16_2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_2 CONTROL: HALT (Bit 7) */ -#define TIMER_16_2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_2 CONTROL: HALT (Bitfield-Mask: 0x01) */ -#define TIMER_16_2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bit 16) */ -#define TIMER_16_2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER_16_3' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TIMER_16_3_CONTROL ----------------------------- */ -#define TIMER_16_3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bit 0) */ -#define TIMER_16_3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bit 2) */ -#define TIMER_16_3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bit 3) */ -#define TIMER_16_3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bit 4) */ -#define TIMER_16_3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_START_Pos (5UL) /*!< TIMER_16_3 CONTROL: START (Bit 5) */ -#define TIMER_16_3_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_3 CONTROL: START (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bit 6) */ -#define TIMER_16_3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_3 CONTROL: HALT (Bit 7) */ -#define TIMER_16_3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_3 CONTROL: HALT (Bitfield-Mask: 0x01) */ -#define TIMER_16_3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bit 16) */ -#define TIMER_16_3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER_32_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TIMER_32_0_CONTROL ----------------------------- */ -#define TIMER_32_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bit 0) */ -#define TIMER_32_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bit 2) */ -#define TIMER_32_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bit 3) */ -#define TIMER_32_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bit 4) */ -#define TIMER_32_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_START_Pos (5UL) /*!< TIMER_32_0 CONTROL: START (Bit 5) */ -#define TIMER_32_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_0 CONTROL: START (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bit 6) */ -#define TIMER_32_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_0 CONTROL: HALT (Bit 7) */ -#define TIMER_32_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_0 CONTROL: HALT (Bitfield-Mask: 0x01) */ -#define TIMER_32_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bit 16) */ -#define TIMER_32_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'TIMER_32_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ----------------------------- TIMER_32_1_CONTROL ----------------------------- */ -#define TIMER_32_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bit 0) */ -#define TIMER_32_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bit 2) */ -#define TIMER_32_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bit 3) */ -#define TIMER_32_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bit 4) */ -#define TIMER_32_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_START_Pos (5UL) /*!< TIMER_32_1 CONTROL: START (Bit 5) */ -#define TIMER_32_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_1 CONTROL: START (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bit 6) */ -#define TIMER_32_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_1 CONTROL: HALT (Bit 7) */ -#define TIMER_32_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_1 CONTROL: HALT (Bitfield-Mask: 0x01) */ -#define TIMER_32_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bit 16) */ -#define TIMER_32_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ - - -/* ================================================================================ */ -/* ================ struct 'RTC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- RTC_CONTROL -------------------------------- */ -#define RTC_CONTROL_BLOCK_ENABLE_Pos (0UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bit 0) */ -#define RTC_CONTROL_BLOCK_ENABLE_Msk (0x1UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bitfield-Mask: 0x01) */ -#define RTC_CONTROL_SOFT_RESET_Pos (1UL) /*!< RTC CONTROL: SOFT_RESET (Bit 1) */ -#define RTC_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< RTC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define RTC_CONTROL_ALARM_ENABLE_Pos (3UL) /*!< RTC CONTROL: ALARM_ENABLE (Bit 3) */ -#define RTC_CONTROL_ALARM_ENABLE_Msk (0x8UL) /*!< RTC CONTROL: ALARM_ENABLE (Bitfield-Mask: 0x01) */ - -/* ------------------------ RTC_DAYLIGHT_SAVINGS_FORWARD ------------------------ */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bit 0) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bitfield-Mask: 0xff) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bit 8) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bit 16) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bitfield-Mask: 0x07) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bit 24) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bitfield-Mask: 0x7f) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bit 31) */ -#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bitfield-Mask: 0x01) */ - -/* ------------------------ RTC_DAYLIGHT_SAVINGS_BACKWARD ----------------------- */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bit 0) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bitfield-Mask: 0xff) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bit 8) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bit 16) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bitfield-Mask: 0x07) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bit 24) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bitfield-Mask: 0x7f) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bit 31) */ -#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'GPIO' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------ GPIO_PIN_CONTROL ------------------------------ */ -#define GPIO_PIN_CONTROL_PU_PD_Pos (0UL) /*!< GPIO PIN_CONTROL: PU_PD (Bit 0) */ -#define GPIO_PIN_CONTROL_PU_PD_Msk (0x3UL) /*!< GPIO PIN_CONTROL: PU_PD (Bitfield-Mask: 0x03) */ -#define GPIO_PIN_CONTROL_PWR_Pos (2UL) /*!< GPIO PIN_CONTROL: PWR (Bit 2) */ -#define GPIO_PIN_CONTROL_PWR_Msk (0xcUL) /*!< GPIO PIN_CONTROL: PWR (Bitfield-Mask: 0x03) */ -#define GPIO_PIN_CONTROL_INT_DET_Pos (4UL) /*!< GPIO PIN_CONTROL: INT_DET (Bit 4) */ -#define GPIO_PIN_CONTROL_INT_DET_Msk (0x70UL) /*!< GPIO PIN_CONTROL: INT_DET (Bitfield-Mask: 0x07) */ -#define GPIO_PIN_CONTROL_EDGE_EN_Pos (7UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bit 7) */ -#define GPIO_PIN_CONTROL_EDGE_EN_Msk (0x80UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bitfield-Mask: 0x01) */ -#define GPIO_PIN_CONTROL_BUFFER_Pos (8UL) /*!< GPIO PIN_CONTROL: BUFFER (Bit 8) */ -#define GPIO_PIN_CONTROL_BUFFER_Msk (0x100UL) /*!< GPIO PIN_CONTROL: BUFFER (Bitfield-Mask: 0x01) */ -#define GPIO_PIN_CONTROL_DIR_Pos (9UL) /*!< GPIO PIN_CONTROL: DIR (Bit 9) */ -#define GPIO_PIN_CONTROL_DIR_Msk (0x200UL) /*!< GPIO PIN_CONTROL: DIR (Bitfield-Mask: 0x01) */ -#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Pos (10UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bit 10) */ -#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Msk (0x400UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bitfield-Mask: 0x01) */ -#define GPIO_PIN_CONTROL_POLARITY_Pos (11UL) /*!< GPIO PIN_CONTROL: POLARITY (Bit 11) */ -#define GPIO_PIN_CONTROL_POLARITY_Msk (0x800UL) /*!< GPIO PIN_CONTROL: POLARITY (Bitfield-Mask: 0x01) */ -#define GPIO_PIN_CONTROL_MUX_Pos (12UL) /*!< GPIO PIN_CONTROL: MUX (Bit 12) */ -#define GPIO_PIN_CONTROL_MUX_Msk (0x3000UL) /*!< GPIO PIN_CONTROL: MUX (Bitfield-Mask: 0x03) */ -#define GPIO_PIN_CONTROL_OUTPUT_Pos (16UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bit 16) */ -#define GPIO_PIN_CONTROL_OUTPUT_Msk (0x10000UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bitfield-Mask: 0x01) */ -#define GPIO_PIN_CONTROL_INPUT_Pos (24UL) /*!< GPIO PIN_CONTROL: INPUT (Bit 24) */ -#define GPIO_PIN_CONTROL_INPUT_Msk (0x1000000UL) /*!< GPIO PIN_CONTROL: INPUT (Bitfield-Mask: 0x01) */ - -/* ---------------------------- GPIO_CONTROL2_000_067 --------------------------- */ -#define GPIO_CONTROL2_000_067_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bit 0) */ -#define GPIO_CONTROL2_000_067_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bitfield-Mask: 0x01) */ -#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bit 4) */ -#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */ - -/* ---------------------------- GPIO_CONTROL2_100_167 --------------------------- */ -#define GPIO_CONTROL2_100_167_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bit 0) */ -#define GPIO_CONTROL2_100_167_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bitfield-Mask: 0x01) */ -#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bit 4) */ -#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */ - -/* ---------------------------- GPIO_CONTROL2_200_267 --------------------------- */ -#define GPIO_CONTROL2_200_267_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bit 0) */ -#define GPIO_CONTROL2_200_267_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bitfield-Mask: 0x01) */ -#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bit 4) */ -#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */ - - -/* ================================================================================ */ -/* ================ struct 'DMA' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- DMA_CONTROL -------------------------------- */ -#define DMA_CONTROL_ACTIVATE_Pos (0UL) /*!< DMA CONTROL: ACTIVATE (Bit 0) */ -#define DMA_CONTROL_ACTIVATE_Msk (0x1UL) /*!< DMA CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */ -#define DMA_CONTROL_SOFT_RESET_Pos (1UL) /*!< DMA CONTROL: SOFT_RESET (Bit 1) */ -#define DMA_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< DMA CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'CH' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- CH_ACTIVATE -------------------------------- */ -#define CH_ACTIVATE_EN_Pos (0UL) /*!< CH ACTIVATE: EN (Bit 0) */ -#define CH_ACTIVATE_EN_Msk (0x1UL) /*!< CH ACTIVATE: EN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- CH_CONTROL --------------------------------- */ -#define CH_CONTROL_RUN_Pos (0UL) /*!< CH CONTROL: RUN (Bit 0) */ -#define CH_CONTROL_RUN_Msk (0x1UL) /*!< CH CONTROL: RUN (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_REQUEST_Pos (1UL) /*!< CH CONTROL: REQUEST (Bit 1) */ -#define CH_CONTROL_REQUEST_Msk (0x2UL) /*!< CH CONTROL: REQUEST (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_DONE_Pos (2UL) /*!< CH CONTROL: DONE (Bit 2) */ -#define CH_CONTROL_DONE_Msk (0x4UL) /*!< CH CONTROL: DONE (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_STATUS_Pos (3UL) /*!< CH CONTROL: STATUS (Bit 3) */ -#define CH_CONTROL_STATUS_Msk (0x18UL) /*!< CH CONTROL: STATUS (Bitfield-Mask: 0x03) */ -#define CH_CONTROL_BUSY_Pos (5UL) /*!< CH CONTROL: BUSY (Bit 5) */ -#define CH_CONTROL_BUSY_Msk (0x20UL) /*!< CH CONTROL: BUSY (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_TX_DIRECTION_Pos (8UL) /*!< CH CONTROL: TX_DIRECTION (Bit 8) */ -#define CH_CONTROL_TX_DIRECTION_Msk (0x100UL) /*!< CH CONTROL: TX_DIRECTION (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Pos (9UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bit 9) */ -#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Msk (0xfe00UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bitfield-Mask: 0x7f) */ -#define CH_CONTROL_INCREMENT_MEM_ADDR_Pos (16UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bit 16) */ -#define CH_CONTROL_INCREMENT_MEM_ADDR_Msk (0x10000UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Pos (17UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bit 17) */ -#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Msk (0x20000UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_LOCK_Pos (18UL) /*!< CH CONTROL: LOCK (Bit 18) */ -#define CH_CONTROL_LOCK_Msk (0x40000UL) /*!< CH CONTROL: LOCK (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Pos (19UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bit 19) */ -#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Msk (0x80000UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_TRANSFER_SIZE_Pos (20UL) /*!< CH CONTROL: TRANSFER_SIZE (Bit 20) */ -#define CH_CONTROL_TRANSFER_SIZE_Msk (0x700000UL) /*!< CH CONTROL: TRANSFER_SIZE (Bitfield-Mask: 0x07) */ -#define CH_CONTROL_TRANSFER_GO_Pos (24UL) /*!< CH CONTROL: TRANSFER_GO (Bit 24) */ -#define CH_CONTROL_TRANSFER_GO_Msk (0x1000000UL) /*!< CH CONTROL: TRANSFER_GO (Bitfield-Mask: 0x01) */ -#define CH_CONTROL_TRANSFER_ABORT_Pos (25UL) /*!< CH CONTROL: TRANSFER_ABORT (Bit 25) */ -#define CH_CONTROL_TRANSFER_ABORT_Msk (0x2000000UL) /*!< CH CONTROL: TRANSFER_ABORT (Bitfield-Mask: 0x01) */ - -/* -------------------------------- CH_INT_STATUS ------------------------------- */ -#define CH_INT_STATUS_BUS_ERROR_Pos (0UL) /*!< CH INT_STATUS: BUS_ERROR (Bit 0) */ -#define CH_INT_STATUS_BUS_ERROR_Msk (0x1UL) /*!< CH INT_STATUS: BUS_ERROR (Bitfield-Mask: 0x01) */ -#define CH_INT_STATUS_FLOW_CONTROL_Pos (1UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bit 1) */ -#define CH_INT_STATUS_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bitfield-Mask: 0x01) */ -#define CH_INT_STATUS_DONE_Pos (2UL) /*!< CH INT_STATUS: DONE (Bit 2) */ -#define CH_INT_STATUS_DONE_Msk (0x4UL) /*!< CH INT_STATUS: DONE (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- CH_INT_EN --------------------------------- */ -#define CH_INT_EN_BUS_ERROR_Pos (0UL) /*!< CH INT_EN: BUS_ERROR (Bit 0) */ -#define CH_INT_EN_BUS_ERROR_Msk (0x1UL) /*!< CH INT_EN: BUS_ERROR (Bitfield-Mask: 0x01) */ -#define CH_INT_EN_FLOW_CONTROL_Pos (1UL) /*!< CH INT_EN: FLOW_CONTROL (Bit 1) */ -#define CH_INT_EN_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_EN: FLOW_CONTROL (Bitfield-Mask: 0x01) */ -#define CH_INT_EN_DONE_Pos (2UL) /*!< CH INT_EN: DONE (Bit 2) */ -#define CH_INT_EN_DONE_Msk (0x4UL) /*!< CH INT_EN: DONE (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'SMB0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- SMB0_CONTROL -------------------------------- */ -#define SMB0_CONTROL_ACK_Pos (0UL) /*!< SMB0 CONTROL: ACK (Bit 0) */ -#define SMB0_CONTROL_ACK_Msk (0x1UL) /*!< SMB0 CONTROL: ACK (Bitfield-Mask: 0x01) */ -#define SMB0_CONTROL_STO_Pos (1UL) /*!< SMB0 CONTROL: STO (Bit 1) */ -#define SMB0_CONTROL_STO_Msk (0x2UL) /*!< SMB0 CONTROL: STO (Bitfield-Mask: 0x01) */ -#define SMB0_CONTROL_STA_Pos (2UL) /*!< SMB0 CONTROL: STA (Bit 2) */ -#define SMB0_CONTROL_STA_Msk (0x4UL) /*!< SMB0 CONTROL: STA (Bitfield-Mask: 0x01) */ -#define SMB0_CONTROL_ENI_Pos (3UL) /*!< SMB0 CONTROL: ENI (Bit 3) */ -#define SMB0_CONTROL_ENI_Msk (0x8UL) /*!< SMB0 CONTROL: ENI (Bitfield-Mask: 0x01) */ -#define SMB0_CONTROL_ESO_Pos (6UL) /*!< SMB0 CONTROL: ESO (Bit 6) */ -#define SMB0_CONTROL_ESO_Msk (0x40UL) /*!< SMB0 CONTROL: ESO (Bitfield-Mask: 0x01) */ -#define SMB0_CONTROL_PIN_Pos (7UL) /*!< SMB0 CONTROL: PIN (Bit 7) */ -#define SMB0_CONTROL_PIN_Msk (0x80UL) /*!< SMB0 CONTROL: PIN (Bitfield-Mask: 0x01) */ - -/* --------------------------------- SMB0_STATUS -------------------------------- */ -#define SMB0_STATUS_nBB_Pos (0UL) /*!< SMB0 STATUS: nBB (Bit 0) */ -#define SMB0_STATUS_nBB_Msk (0x1UL) /*!< SMB0 STATUS: nBB (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_LAB_Pos (1UL) /*!< SMB0 STATUS: LAB (Bit 1) */ -#define SMB0_STATUS_LAB_Msk (0x2UL) /*!< SMB0 STATUS: LAB (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_AAS_Pos (2UL) /*!< SMB0 STATUS: AAS (Bit 2) */ -#define SMB0_STATUS_AAS_Msk (0x4UL) /*!< SMB0 STATUS: AAS (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_LRB_AD0_Pos (3UL) /*!< SMB0 STATUS: LRB_AD0 (Bit 3) */ -#define SMB0_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB0 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_BER_Pos (4UL) /*!< SMB0 STATUS: BER (Bit 4) */ -#define SMB0_STATUS_BER_Msk (0x10UL) /*!< SMB0 STATUS: BER (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_STS_Pos (5UL) /*!< SMB0 STATUS: STS (Bit 5) */ -#define SMB0_STATUS_STS_Msk (0x20UL) /*!< SMB0 STATUS: STS (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_SAD_Pos (6UL) /*!< SMB0 STATUS: SAD (Bit 6) */ -#define SMB0_STATUS_SAD_Msk (0x40UL) /*!< SMB0 STATUS: SAD (Bitfield-Mask: 0x01) */ -#define SMB0_STATUS_PIN_Pos (7UL) /*!< SMB0 STATUS: PIN (Bit 7) */ -#define SMB0_STATUS_PIN_Msk (0x80UL) /*!< SMB0 STATUS: PIN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- SMB0_OWN ---------------------------------- */ -#define SMB0_OWN_ADDRESS_1_Pos (0UL) /*!< SMB0 OWN: ADDRESS_1 (Bit 0) */ -#define SMB0_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB0 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ -#define SMB0_OWN_ADDRESS_2_Pos (8UL) /*!< SMB0 OWN: ADDRESS_2 (Bit 8) */ -#define SMB0_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB0 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ - -/* ----------------------------- SMB0_MASTER_COMMAND ---------------------------- */ -#define SMB0_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bit 0) */ -#define SMB0_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bit 1) */ -#define SMB0_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB0 MASTER_COMMAND: START0 (Bit 8) */ -#define SMB0_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB0 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bit 9) */ -#define SMB0_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB0 MASTER_COMMAND: STOP (Bit 10) */ -#define SMB0_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB0 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bit 11) */ -#define SMB0_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB0 MASTER_COMMAND: READM (Bit 12) */ -#define SMB0_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB0 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bit 13) */ -#define SMB0_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ -#define SMB0_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bit 16) */ -#define SMB0_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB0_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bit 24) */ -#define SMB0_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ - -/* ----------------------------- SMB0_SLAVE_COMMAND ----------------------------- */ -#define SMB0_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bit 0) */ -#define SMB0_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ -#define SMB0_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bit 1) */ -#define SMB0_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ -#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ -#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ -#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ -#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ -#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ - -/* ------------------------------- SMB0_COMPLETION ------------------------------ */ -#define SMB0_COMPLETION_DTEN_Pos (2UL) /*!< SMB0 COMPLETION: DTEN (Bit 2) */ -#define SMB0_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB0 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_MCEN_Pos (3UL) /*!< SMB0 COMPLETION: MCEN (Bit 3) */ -#define SMB0_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB0 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_SCEN_Pos (4UL) /*!< SMB0 COMPLETION: SCEN (Bit 4) */ -#define SMB0_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB0 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_BIDEN_Pos (5UL) /*!< SMB0 COMPLETION: BIDEN (Bit 5) */ -#define SMB0_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB0 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_TIMERR_Pos (6UL) /*!< SMB0 COMPLETION: TIMERR (Bit 6) */ -#define SMB0_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB0 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_DTO_Pos (8UL) /*!< SMB0 COMPLETION: DTO (Bit 8) */ -#define SMB0_COMPLETION_DTO_Msk (0x100UL) /*!< SMB0 COMPLETION: DTO (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_MCTO_Pos (9UL) /*!< SMB0 COMPLETION: MCTO (Bit 9) */ -#define SMB0_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB0 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_SCTO_Pos (10UL) /*!< SMB0 COMPLETION: SCTO (Bit 10) */ -#define SMB0_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB0 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_CHDL_Pos (11UL) /*!< SMB0 COMPLETION: CHDL (Bit 11) */ -#define SMB0_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB0 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_CHDH_Pos (12UL) /*!< SMB0 COMPLETION: CHDH (Bit 12) */ -#define SMB0_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB0 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_BER_Pos (13UL) /*!< SMB0 COMPLETION: BER (Bit 13) */ -#define SMB0_COMPLETION_BER_Msk (0x2000UL) /*!< SMB0 COMPLETION: BER (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_LAB_Pos (14UL) /*!< SMB0 COMPLETION: LAB (Bit 14) */ -#define SMB0_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB0 COMPLETION: LAB (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_SNAKR_Pos (16UL) /*!< SMB0 COMPLETION: SNAKR (Bit 16) */ -#define SMB0_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB0 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_STR_Pos (17UL) /*!< SMB0 COMPLETION: STR (Bit 17) */ -#define SMB0_COMPLETION_STR_Msk (0x20000UL) /*!< SMB0 COMPLETION: STR (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_SPROT_Pos (19UL) /*!< SMB0 COMPLETION: SPROT (Bit 19) */ -#define SMB0_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB0 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bit 20) */ -#define SMB0_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bit 21) */ -#define SMB0_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_MNAKX_Pos (24UL) /*!< SMB0 COMPLETION: MNAKX (Bit 24) */ -#define SMB0_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB0 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_MTR_Pos (25UL) /*!< SMB0 COMPLETION: MTR (Bit 25) */ -#define SMB0_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB0 COMPLETION: MTR (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_IDLE_Pos (29UL) /*!< SMB0 COMPLETION: IDLE (Bit 29) */ -#define SMB0_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB0 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_MDONE_Pos (30UL) /*!< SMB0 COMPLETION: MDONE (Bit 30) */ -#define SMB0_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB0 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ -#define SMB0_COMPLETION_SDONE_Pos (31UL) /*!< SMB0 COMPLETION: SDONE (Bit 31) */ -#define SMB0_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB0 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB0_IDLE_SCALING ----------------------------- */ -#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ -#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ -#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ -#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ - -/* ----------------------------- SMB0_CONFIGURATION ----------------------------- */ -#define SMB0_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bit 0) */ -#define SMB0_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ -#define SMB0_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB0 CONFIGURATION: TCEN (Bit 4) */ -#define SMB0_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB0 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bit 5) */ -#define SMB0_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB0 CONFIGURATION: PECEN (Bit 7) */ -#define SMB0_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB0 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB0 CONFIGURATION: DFEN (Bit 8) */ -#define SMB0_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB0 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_RESET_Pos (9UL) /*!< SMB0 CONFIGURATION: RESET (Bit 9) */ -#define SMB0_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB0 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB0 CONFIGURATION: ENAB (Bit 10) */ -#define SMB0_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB0 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_DSA_Pos (11UL) /*!< SMB0 CONFIGURATION: DSA (Bit 11) */ -#define SMB0_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB0 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB0 CONFIGURATION: FAIR (Bit 12) */ -#define SMB0_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB0 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bit 14) */ -#define SMB0_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ -#define SMB0_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ -#define SMB0_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ -#define SMB0_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ -#define SMB0_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bit 28) */ -#define SMB0_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB0 CONFIGURATION: ENIDI (Bit 29) */ -#define SMB0_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB0 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB0 CONFIGURATION: ENMI (Bit 30) */ -#define SMB0_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB0 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ -#define SMB0_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB0 CONFIGURATION: ENSI (Bit 31) */ -#define SMB0_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB0 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SMB0_BUS_CLOCK ------------------------------- */ -#define SMB0_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bit 0) */ -#define SMB0_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ -#define SMB0_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ -#define SMB0_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB0_BIT_BANG_CONTROL --------------------------- */ -#define SMB0_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bit 0) */ -#define SMB0_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ -#define SMB0_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bit 1) */ -#define SMB0_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ -#define SMB0_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bit 2) */ -#define SMB0_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ -#define SMB0_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bit 3) */ -#define SMB0_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ -#define SMB0_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bit 4) */ -#define SMB0_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ -#define SMB0_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ -#define SMB0_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ -#define SMB0_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bit 6) */ -#define SMB0_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB0_DATA_TIMING ------------------------------ */ -#define SMB0_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bit 0) */ -#define SMB0_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ -#define SMB0_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bit 8) */ -#define SMB0_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ -#define SMB0_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bit 16) */ -#define SMB0_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ -#define SMB0_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bit 24) */ -#define SMB0_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB0_TIME_OUT_SCALING --------------------------- */ -#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ -#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ -#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ -#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ -#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ -#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ -#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ -#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'SMB1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- SMB1_STATUS -------------------------------- */ -#define SMB1_STATUS_nBB_Pos (0UL) /*!< SMB1 STATUS: nBB (Bit 0) */ -#define SMB1_STATUS_nBB_Msk (0x1UL) /*!< SMB1 STATUS: nBB (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_LAB_Pos (1UL) /*!< SMB1 STATUS: LAB (Bit 1) */ -#define SMB1_STATUS_LAB_Msk (0x2UL) /*!< SMB1 STATUS: LAB (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_AAS_Pos (2UL) /*!< SMB1 STATUS: AAS (Bit 2) */ -#define SMB1_STATUS_AAS_Msk (0x4UL) /*!< SMB1 STATUS: AAS (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_LRB_AD0_Pos (3UL) /*!< SMB1 STATUS: LRB_AD0 (Bit 3) */ -#define SMB1_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB1 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_BER_Pos (4UL) /*!< SMB1 STATUS: BER (Bit 4) */ -#define SMB1_STATUS_BER_Msk (0x10UL) /*!< SMB1 STATUS: BER (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_STS_Pos (5UL) /*!< SMB1 STATUS: STS (Bit 5) */ -#define SMB1_STATUS_STS_Msk (0x20UL) /*!< SMB1 STATUS: STS (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_SAD_Pos (6UL) /*!< SMB1 STATUS: SAD (Bit 6) */ -#define SMB1_STATUS_SAD_Msk (0x40UL) /*!< SMB1 STATUS: SAD (Bitfield-Mask: 0x01) */ -#define SMB1_STATUS_PIN_Pos (7UL) /*!< SMB1 STATUS: PIN (Bit 7) */ -#define SMB1_STATUS_PIN_Msk (0x80UL) /*!< SMB1 STATUS: PIN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- SMB1_CONTROL -------------------------------- */ -#define SMB1_CONTROL_ACK_Pos (0UL) /*!< SMB1 CONTROL: ACK (Bit 0) */ -#define SMB1_CONTROL_ACK_Msk (0x1UL) /*!< SMB1 CONTROL: ACK (Bitfield-Mask: 0x01) */ -#define SMB1_CONTROL_STO_Pos (1UL) /*!< SMB1 CONTROL: STO (Bit 1) */ -#define SMB1_CONTROL_STO_Msk (0x2UL) /*!< SMB1 CONTROL: STO (Bitfield-Mask: 0x01) */ -#define SMB1_CONTROL_STA_Pos (2UL) /*!< SMB1 CONTROL: STA (Bit 2) */ -#define SMB1_CONTROL_STA_Msk (0x4UL) /*!< SMB1 CONTROL: STA (Bitfield-Mask: 0x01) */ -#define SMB1_CONTROL_ENI_Pos (3UL) /*!< SMB1 CONTROL: ENI (Bit 3) */ -#define SMB1_CONTROL_ENI_Msk (0x8UL) /*!< SMB1 CONTROL: ENI (Bitfield-Mask: 0x01) */ -#define SMB1_CONTROL_ESO_Pos (6UL) /*!< SMB1 CONTROL: ESO (Bit 6) */ -#define SMB1_CONTROL_ESO_Msk (0x40UL) /*!< SMB1 CONTROL: ESO (Bitfield-Mask: 0x01) */ -#define SMB1_CONTROL_PIN_Pos (7UL) /*!< SMB1 CONTROL: PIN (Bit 7) */ -#define SMB1_CONTROL_PIN_Msk (0x80UL) /*!< SMB1 CONTROL: PIN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- SMB1_OWN ---------------------------------- */ -#define SMB1_OWN_ADDRESS_1_Pos (0UL) /*!< SMB1 OWN: ADDRESS_1 (Bit 0) */ -#define SMB1_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB1 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ -#define SMB1_OWN_ADDRESS_2_Pos (8UL) /*!< SMB1 OWN: ADDRESS_2 (Bit 8) */ -#define SMB1_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB1 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ - -/* ----------------------------- SMB1_MASTER_COMMAND ---------------------------- */ -#define SMB1_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bit 0) */ -#define SMB1_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bit 1) */ -#define SMB1_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB1 MASTER_COMMAND: START0 (Bit 8) */ -#define SMB1_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB1 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bit 9) */ -#define SMB1_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB1 MASTER_COMMAND: STOP (Bit 10) */ -#define SMB1_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB1 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bit 11) */ -#define SMB1_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB1 MASTER_COMMAND: READM (Bit 12) */ -#define SMB1_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB1 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bit 13) */ -#define SMB1_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ -#define SMB1_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bit 16) */ -#define SMB1_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB1_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bit 24) */ -#define SMB1_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ - -/* ----------------------------- SMB1_SLAVE_COMMAND ----------------------------- */ -#define SMB1_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bit 0) */ -#define SMB1_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ -#define SMB1_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bit 1) */ -#define SMB1_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ -#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ -#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ -#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ -#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ -#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ - -/* ------------------------------- SMB1_COMPLETION ------------------------------ */ -#define SMB1_COMPLETION_DTEN_Pos (2UL) /*!< SMB1 COMPLETION: DTEN (Bit 2) */ -#define SMB1_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB1 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_MCEN_Pos (3UL) /*!< SMB1 COMPLETION: MCEN (Bit 3) */ -#define SMB1_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB1 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_SCEN_Pos (4UL) /*!< SMB1 COMPLETION: SCEN (Bit 4) */ -#define SMB1_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB1 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_BIDEN_Pos (5UL) /*!< SMB1 COMPLETION: BIDEN (Bit 5) */ -#define SMB1_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB1 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_TIMERR_Pos (6UL) /*!< SMB1 COMPLETION: TIMERR (Bit 6) */ -#define SMB1_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB1 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_DTO_Pos (8UL) /*!< SMB1 COMPLETION: DTO (Bit 8) */ -#define SMB1_COMPLETION_DTO_Msk (0x100UL) /*!< SMB1 COMPLETION: DTO (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_MCTO_Pos (9UL) /*!< SMB1 COMPLETION: MCTO (Bit 9) */ -#define SMB1_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB1 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_SCTO_Pos (10UL) /*!< SMB1 COMPLETION: SCTO (Bit 10) */ -#define SMB1_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB1 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_CHDL_Pos (11UL) /*!< SMB1 COMPLETION: CHDL (Bit 11) */ -#define SMB1_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB1 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_CHDH_Pos (12UL) /*!< SMB1 COMPLETION: CHDH (Bit 12) */ -#define SMB1_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB1 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_BER_Pos (13UL) /*!< SMB1 COMPLETION: BER (Bit 13) */ -#define SMB1_COMPLETION_BER_Msk (0x2000UL) /*!< SMB1 COMPLETION: BER (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_LAB_Pos (14UL) /*!< SMB1 COMPLETION: LAB (Bit 14) */ -#define SMB1_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB1 COMPLETION: LAB (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_SNAKR_Pos (16UL) /*!< SMB1 COMPLETION: SNAKR (Bit 16) */ -#define SMB1_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB1 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_STR_Pos (17UL) /*!< SMB1 COMPLETION: STR (Bit 17) */ -#define SMB1_COMPLETION_STR_Msk (0x20000UL) /*!< SMB1 COMPLETION: STR (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_SPROT_Pos (19UL) /*!< SMB1 COMPLETION: SPROT (Bit 19) */ -#define SMB1_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB1 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bit 20) */ -#define SMB1_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bit 21) */ -#define SMB1_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_MNAKX_Pos (24UL) /*!< SMB1 COMPLETION: MNAKX (Bit 24) */ -#define SMB1_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB1 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_MTR_Pos (25UL) /*!< SMB1 COMPLETION: MTR (Bit 25) */ -#define SMB1_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB1 COMPLETION: MTR (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_IDLE_Pos (29UL) /*!< SMB1 COMPLETION: IDLE (Bit 29) */ -#define SMB1_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB1 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_MDONE_Pos (30UL) /*!< SMB1 COMPLETION: MDONE (Bit 30) */ -#define SMB1_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB1 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ -#define SMB1_COMPLETION_SDONE_Pos (31UL) /*!< SMB1 COMPLETION: SDONE (Bit 31) */ -#define SMB1_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB1 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB1_IDLE_SCALING ----------------------------- */ -#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ -#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ -#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ -#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ - -/* ----------------------------- SMB1_CONFIGURATION ----------------------------- */ -#define SMB1_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bit 0) */ -#define SMB1_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ -#define SMB1_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB1 CONFIGURATION: TCEN (Bit 4) */ -#define SMB1_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB1 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bit 5) */ -#define SMB1_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB1 CONFIGURATION: PECEN (Bit 7) */ -#define SMB1_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB1 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB1 CONFIGURATION: DFEN (Bit 8) */ -#define SMB1_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB1 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_RESET_Pos (9UL) /*!< SMB1 CONFIGURATION: RESET (Bit 9) */ -#define SMB1_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB1 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB1 CONFIGURATION: ENAB (Bit 10) */ -#define SMB1_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB1 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_DSA_Pos (11UL) /*!< SMB1 CONFIGURATION: DSA (Bit 11) */ -#define SMB1_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB1 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB1 CONFIGURATION: FAIR (Bit 12) */ -#define SMB1_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB1 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bit 14) */ -#define SMB1_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ -#define SMB1_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ -#define SMB1_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ -#define SMB1_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ -#define SMB1_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bit 28) */ -#define SMB1_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB1 CONFIGURATION: ENIDI (Bit 29) */ -#define SMB1_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB1 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB1 CONFIGURATION: ENMI (Bit 30) */ -#define SMB1_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB1 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ -#define SMB1_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB1 CONFIGURATION: ENSI (Bit 31) */ -#define SMB1_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB1 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SMB1_BUS_CLOCK ------------------------------- */ -#define SMB1_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bit 0) */ -#define SMB1_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ -#define SMB1_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ -#define SMB1_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB1_BIT_BANG_CONTROL --------------------------- */ -#define SMB1_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bit 0) */ -#define SMB1_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ -#define SMB1_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bit 1) */ -#define SMB1_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ -#define SMB1_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bit 2) */ -#define SMB1_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ -#define SMB1_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bit 3) */ -#define SMB1_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ -#define SMB1_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bit 4) */ -#define SMB1_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ -#define SMB1_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ -#define SMB1_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ -#define SMB1_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bit 6) */ -#define SMB1_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB1_DATA_TIMING ------------------------------ */ -#define SMB1_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bit 0) */ -#define SMB1_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ -#define SMB1_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bit 8) */ -#define SMB1_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ -#define SMB1_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bit 16) */ -#define SMB1_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ -#define SMB1_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bit 24) */ -#define SMB1_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB1_TIME_OUT_SCALING --------------------------- */ -#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ -#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ -#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ -#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ -#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ -#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ -#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ -#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'SMB2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- SMB2_STATUS -------------------------------- */ -#define SMB2_STATUS_nBB_Pos (0UL) /*!< SMB2 STATUS: nBB (Bit 0) */ -#define SMB2_STATUS_nBB_Msk (0x1UL) /*!< SMB2 STATUS: nBB (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_LAB_Pos (1UL) /*!< SMB2 STATUS: LAB (Bit 1) */ -#define SMB2_STATUS_LAB_Msk (0x2UL) /*!< SMB2 STATUS: LAB (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_AAS_Pos (2UL) /*!< SMB2 STATUS: AAS (Bit 2) */ -#define SMB2_STATUS_AAS_Msk (0x4UL) /*!< SMB2 STATUS: AAS (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_LRB_AD0_Pos (3UL) /*!< SMB2 STATUS: LRB_AD0 (Bit 3) */ -#define SMB2_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB2 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_BER_Pos (4UL) /*!< SMB2 STATUS: BER (Bit 4) */ -#define SMB2_STATUS_BER_Msk (0x10UL) /*!< SMB2 STATUS: BER (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_STS_Pos (5UL) /*!< SMB2 STATUS: STS (Bit 5) */ -#define SMB2_STATUS_STS_Msk (0x20UL) /*!< SMB2 STATUS: STS (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_SAD_Pos (6UL) /*!< SMB2 STATUS: SAD (Bit 6) */ -#define SMB2_STATUS_SAD_Msk (0x40UL) /*!< SMB2 STATUS: SAD (Bitfield-Mask: 0x01) */ -#define SMB2_STATUS_PIN_Pos (7UL) /*!< SMB2 STATUS: PIN (Bit 7) */ -#define SMB2_STATUS_PIN_Msk (0x80UL) /*!< SMB2 STATUS: PIN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- SMB2_CONTROL -------------------------------- */ -#define SMB2_CONTROL_ACK_Pos (0UL) /*!< SMB2 CONTROL: ACK (Bit 0) */ -#define SMB2_CONTROL_ACK_Msk (0x1UL) /*!< SMB2 CONTROL: ACK (Bitfield-Mask: 0x01) */ -#define SMB2_CONTROL_STO_Pos (1UL) /*!< SMB2 CONTROL: STO (Bit 1) */ -#define SMB2_CONTROL_STO_Msk (0x2UL) /*!< SMB2 CONTROL: STO (Bitfield-Mask: 0x01) */ -#define SMB2_CONTROL_STA_Pos (2UL) /*!< SMB2 CONTROL: STA (Bit 2) */ -#define SMB2_CONTROL_STA_Msk (0x4UL) /*!< SMB2 CONTROL: STA (Bitfield-Mask: 0x01) */ -#define SMB2_CONTROL_ENI_Pos (3UL) /*!< SMB2 CONTROL: ENI (Bit 3) */ -#define SMB2_CONTROL_ENI_Msk (0x8UL) /*!< SMB2 CONTROL: ENI (Bitfield-Mask: 0x01) */ -#define SMB2_CONTROL_ESO_Pos (6UL) /*!< SMB2 CONTROL: ESO (Bit 6) */ -#define SMB2_CONTROL_ESO_Msk (0x40UL) /*!< SMB2 CONTROL: ESO (Bitfield-Mask: 0x01) */ -#define SMB2_CONTROL_PIN_Pos (7UL) /*!< SMB2 CONTROL: PIN (Bit 7) */ -#define SMB2_CONTROL_PIN_Msk (0x80UL) /*!< SMB2 CONTROL: PIN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- SMB2_OWN ---------------------------------- */ -#define SMB2_OWN_ADDRESS_1_Pos (0UL) /*!< SMB2 OWN: ADDRESS_1 (Bit 0) */ -#define SMB2_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB2 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ -#define SMB2_OWN_ADDRESS_2_Pos (8UL) /*!< SMB2 OWN: ADDRESS_2 (Bit 8) */ -#define SMB2_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB2 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ - -/* ----------------------------- SMB2_MASTER_COMMAND ---------------------------- */ -#define SMB2_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bit 0) */ -#define SMB2_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bit 1) */ -#define SMB2_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB2 MASTER_COMMAND: START0 (Bit 8) */ -#define SMB2_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB2 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bit 9) */ -#define SMB2_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB2 MASTER_COMMAND: STOP (Bit 10) */ -#define SMB2_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB2 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bit 11) */ -#define SMB2_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB2 MASTER_COMMAND: READM (Bit 12) */ -#define SMB2_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB2 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bit 13) */ -#define SMB2_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ -#define SMB2_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bit 16) */ -#define SMB2_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB2_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bit 24) */ -#define SMB2_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ - -/* ----------------------------- SMB2_SLAVE_COMMAND ----------------------------- */ -#define SMB2_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bit 0) */ -#define SMB2_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ -#define SMB2_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bit 1) */ -#define SMB2_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ -#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ -#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ -#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ -#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ -#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ - -/* ------------------------------- SMB2_COMPLETION ------------------------------ */ -#define SMB2_COMPLETION_DTEN_Pos (2UL) /*!< SMB2 COMPLETION: DTEN (Bit 2) */ -#define SMB2_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB2 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_MCEN_Pos (3UL) /*!< SMB2 COMPLETION: MCEN (Bit 3) */ -#define SMB2_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB2 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_SCEN_Pos (4UL) /*!< SMB2 COMPLETION: SCEN (Bit 4) */ -#define SMB2_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB2 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_BIDEN_Pos (5UL) /*!< SMB2 COMPLETION: BIDEN (Bit 5) */ -#define SMB2_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB2 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_TIMERR_Pos (6UL) /*!< SMB2 COMPLETION: TIMERR (Bit 6) */ -#define SMB2_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB2 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_DTO_Pos (8UL) /*!< SMB2 COMPLETION: DTO (Bit 8) */ -#define SMB2_COMPLETION_DTO_Msk (0x100UL) /*!< SMB2 COMPLETION: DTO (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_MCTO_Pos (9UL) /*!< SMB2 COMPLETION: MCTO (Bit 9) */ -#define SMB2_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB2 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_SCTO_Pos (10UL) /*!< SMB2 COMPLETION: SCTO (Bit 10) */ -#define SMB2_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB2 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_CHDL_Pos (11UL) /*!< SMB2 COMPLETION: CHDL (Bit 11) */ -#define SMB2_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB2 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_CHDH_Pos (12UL) /*!< SMB2 COMPLETION: CHDH (Bit 12) */ -#define SMB2_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB2 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_BER_Pos (13UL) /*!< SMB2 COMPLETION: BER (Bit 13) */ -#define SMB2_COMPLETION_BER_Msk (0x2000UL) /*!< SMB2 COMPLETION: BER (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_LAB_Pos (14UL) /*!< SMB2 COMPLETION: LAB (Bit 14) */ -#define SMB2_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB2 COMPLETION: LAB (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_SNAKR_Pos (16UL) /*!< SMB2 COMPLETION: SNAKR (Bit 16) */ -#define SMB2_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB2 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_STR_Pos (17UL) /*!< SMB2 COMPLETION: STR (Bit 17) */ -#define SMB2_COMPLETION_STR_Msk (0x20000UL) /*!< SMB2 COMPLETION: STR (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_SPROT_Pos (19UL) /*!< SMB2 COMPLETION: SPROT (Bit 19) */ -#define SMB2_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB2 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bit 20) */ -#define SMB2_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bit 21) */ -#define SMB2_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_MNAKX_Pos (24UL) /*!< SMB2 COMPLETION: MNAKX (Bit 24) */ -#define SMB2_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB2 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_MTR_Pos (25UL) /*!< SMB2 COMPLETION: MTR (Bit 25) */ -#define SMB2_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB2 COMPLETION: MTR (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_IDLE_Pos (29UL) /*!< SMB2 COMPLETION: IDLE (Bit 29) */ -#define SMB2_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB2 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_MDONE_Pos (30UL) /*!< SMB2 COMPLETION: MDONE (Bit 30) */ -#define SMB2_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB2 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ -#define SMB2_COMPLETION_SDONE_Pos (31UL) /*!< SMB2 COMPLETION: SDONE (Bit 31) */ -#define SMB2_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB2 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB2_IDLE_SCALING ----------------------------- */ -#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ -#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ -#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ -#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ - -/* ----------------------------- SMB2_CONFIGURATION ----------------------------- */ -#define SMB2_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bit 0) */ -#define SMB2_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ -#define SMB2_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB2 CONFIGURATION: TCEN (Bit 4) */ -#define SMB2_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB2 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bit 5) */ -#define SMB2_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB2 CONFIGURATION: PECEN (Bit 7) */ -#define SMB2_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB2 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB2 CONFIGURATION: DFEN (Bit 8) */ -#define SMB2_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB2 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_RESET_Pos (9UL) /*!< SMB2 CONFIGURATION: RESET (Bit 9) */ -#define SMB2_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB2 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB2 CONFIGURATION: ENAB (Bit 10) */ -#define SMB2_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB2 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_DSA_Pos (11UL) /*!< SMB2 CONFIGURATION: DSA (Bit 11) */ -#define SMB2_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB2 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB2 CONFIGURATION: FAIR (Bit 12) */ -#define SMB2_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB2 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bit 14) */ -#define SMB2_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ -#define SMB2_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ -#define SMB2_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ -#define SMB2_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ -#define SMB2_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bit 28) */ -#define SMB2_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB2 CONFIGURATION: ENIDI (Bit 29) */ -#define SMB2_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB2 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB2 CONFIGURATION: ENMI (Bit 30) */ -#define SMB2_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB2 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ -#define SMB2_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB2 CONFIGURATION: ENSI (Bit 31) */ -#define SMB2_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB2 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SMB2_BUS_CLOCK ------------------------------- */ -#define SMB2_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bit 0) */ -#define SMB2_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ -#define SMB2_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ -#define SMB2_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB2_BIT_BANG_CONTROL --------------------------- */ -#define SMB2_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bit 0) */ -#define SMB2_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ -#define SMB2_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bit 1) */ -#define SMB2_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ -#define SMB2_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bit 2) */ -#define SMB2_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ -#define SMB2_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bit 3) */ -#define SMB2_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ -#define SMB2_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bit 4) */ -#define SMB2_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ -#define SMB2_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ -#define SMB2_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ -#define SMB2_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bit 6) */ -#define SMB2_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB2_DATA_TIMING ------------------------------ */ -#define SMB2_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bit 0) */ -#define SMB2_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ -#define SMB2_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bit 8) */ -#define SMB2_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ -#define SMB2_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bit 16) */ -#define SMB2_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ -#define SMB2_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bit 24) */ -#define SMB2_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB2_TIME_OUT_SCALING --------------------------- */ -#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ -#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ -#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ -#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ -#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ -#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ -#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ -#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'SMB3' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- SMB3_STATUS -------------------------------- */ -#define SMB3_STATUS_nBB_Pos (0UL) /*!< SMB3 STATUS: nBB (Bit 0) */ -#define SMB3_STATUS_nBB_Msk (0x1UL) /*!< SMB3 STATUS: nBB (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_LAB_Pos (1UL) /*!< SMB3 STATUS: LAB (Bit 1) */ -#define SMB3_STATUS_LAB_Msk (0x2UL) /*!< SMB3 STATUS: LAB (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_AAS_Pos (2UL) /*!< SMB3 STATUS: AAS (Bit 2) */ -#define SMB3_STATUS_AAS_Msk (0x4UL) /*!< SMB3 STATUS: AAS (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_LRB_AD0_Pos (3UL) /*!< SMB3 STATUS: LRB_AD0 (Bit 3) */ -#define SMB3_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB3 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_BER_Pos (4UL) /*!< SMB3 STATUS: BER (Bit 4) */ -#define SMB3_STATUS_BER_Msk (0x10UL) /*!< SMB3 STATUS: BER (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_STS_Pos (5UL) /*!< SMB3 STATUS: STS (Bit 5) */ -#define SMB3_STATUS_STS_Msk (0x20UL) /*!< SMB3 STATUS: STS (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_SAD_Pos (6UL) /*!< SMB3 STATUS: SAD (Bit 6) */ -#define SMB3_STATUS_SAD_Msk (0x40UL) /*!< SMB3 STATUS: SAD (Bitfield-Mask: 0x01) */ -#define SMB3_STATUS_PIN_Pos (7UL) /*!< SMB3 STATUS: PIN (Bit 7) */ -#define SMB3_STATUS_PIN_Msk (0x80UL) /*!< SMB3 STATUS: PIN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- SMB3_CONTROL -------------------------------- */ -#define SMB3_CONTROL_ACK_Pos (0UL) /*!< SMB3 CONTROL: ACK (Bit 0) */ -#define SMB3_CONTROL_ACK_Msk (0x1UL) /*!< SMB3 CONTROL: ACK (Bitfield-Mask: 0x01) */ -#define SMB3_CONTROL_STO_Pos (1UL) /*!< SMB3 CONTROL: STO (Bit 1) */ -#define SMB3_CONTROL_STO_Msk (0x2UL) /*!< SMB3 CONTROL: STO (Bitfield-Mask: 0x01) */ -#define SMB3_CONTROL_STA_Pos (2UL) /*!< SMB3 CONTROL: STA (Bit 2) */ -#define SMB3_CONTROL_STA_Msk (0x4UL) /*!< SMB3 CONTROL: STA (Bitfield-Mask: 0x01) */ -#define SMB3_CONTROL_ENI_Pos (3UL) /*!< SMB3 CONTROL: ENI (Bit 3) */ -#define SMB3_CONTROL_ENI_Msk (0x8UL) /*!< SMB3 CONTROL: ENI (Bitfield-Mask: 0x01) */ -#define SMB3_CONTROL_ESO_Pos (6UL) /*!< SMB3 CONTROL: ESO (Bit 6) */ -#define SMB3_CONTROL_ESO_Msk (0x40UL) /*!< SMB3 CONTROL: ESO (Bitfield-Mask: 0x01) */ -#define SMB3_CONTROL_PIN_Pos (7UL) /*!< SMB3 CONTROL: PIN (Bit 7) */ -#define SMB3_CONTROL_PIN_Msk (0x80UL) /*!< SMB3 CONTROL: PIN (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- SMB3_OWN ---------------------------------- */ -#define SMB3_OWN_ADDRESS_1_Pos (0UL) /*!< SMB3 OWN: ADDRESS_1 (Bit 0) */ -#define SMB3_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB3 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ -#define SMB3_OWN_ADDRESS_2_Pos (8UL) /*!< SMB3 OWN: ADDRESS_2 (Bit 8) */ -#define SMB3_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB3 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ - -/* ----------------------------- SMB3_MASTER_COMMAND ---------------------------- */ -#define SMB3_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bit 0) */ -#define SMB3_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bit 1) */ -#define SMB3_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB3 MASTER_COMMAND: START0 (Bit 8) */ -#define SMB3_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB3 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bit 9) */ -#define SMB3_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB3 MASTER_COMMAND: STOP (Bit 10) */ -#define SMB3_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB3 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bit 11) */ -#define SMB3_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB3 MASTER_COMMAND: READM (Bit 12) */ -#define SMB3_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB3 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bit 13) */ -#define SMB3_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ -#define SMB3_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bit 16) */ -#define SMB3_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB3_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bit 24) */ -#define SMB3_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ - -/* ----------------------------- SMB3_SLAVE_COMMAND ----------------------------- */ -#define SMB3_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bit 0) */ -#define SMB3_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ -#define SMB3_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bit 1) */ -#define SMB3_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ -#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ -#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ -#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ -#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ -#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ -#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ - -/* ------------------------------- SMB3_COMPLETION ------------------------------ */ -#define SMB3_COMPLETION_DTEN_Pos (2UL) /*!< SMB3 COMPLETION: DTEN (Bit 2) */ -#define SMB3_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB3 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_MCEN_Pos (3UL) /*!< SMB3 COMPLETION: MCEN (Bit 3) */ -#define SMB3_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB3 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_SCEN_Pos (4UL) /*!< SMB3 COMPLETION: SCEN (Bit 4) */ -#define SMB3_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB3 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_BIDEN_Pos (5UL) /*!< SMB3 COMPLETION: BIDEN (Bit 5) */ -#define SMB3_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB3 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_TIMERR_Pos (6UL) /*!< SMB3 COMPLETION: TIMERR (Bit 6) */ -#define SMB3_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB3 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_DTO_Pos (8UL) /*!< SMB3 COMPLETION: DTO (Bit 8) */ -#define SMB3_COMPLETION_DTO_Msk (0x100UL) /*!< SMB3 COMPLETION: DTO (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_MCTO_Pos (9UL) /*!< SMB3 COMPLETION: MCTO (Bit 9) */ -#define SMB3_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB3 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_SCTO_Pos (10UL) /*!< SMB3 COMPLETION: SCTO (Bit 10) */ -#define SMB3_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB3 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_CHDL_Pos (11UL) /*!< SMB3 COMPLETION: CHDL (Bit 11) */ -#define SMB3_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB3 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_CHDH_Pos (12UL) /*!< SMB3 COMPLETION: CHDH (Bit 12) */ -#define SMB3_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB3 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_BER_Pos (13UL) /*!< SMB3 COMPLETION: BER (Bit 13) */ -#define SMB3_COMPLETION_BER_Msk (0x2000UL) /*!< SMB3 COMPLETION: BER (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_LAB_Pos (14UL) /*!< SMB3 COMPLETION: LAB (Bit 14) */ -#define SMB3_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB3 COMPLETION: LAB (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_SNAKR_Pos (16UL) /*!< SMB3 COMPLETION: SNAKR (Bit 16) */ -#define SMB3_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB3 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_STR_Pos (17UL) /*!< SMB3 COMPLETION: STR (Bit 17) */ -#define SMB3_COMPLETION_STR_Msk (0x20000UL) /*!< SMB3 COMPLETION: STR (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_SPROT_Pos (19UL) /*!< SMB3 COMPLETION: SPROT (Bit 19) */ -#define SMB3_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB3 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bit 20) */ -#define SMB3_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bit 21) */ -#define SMB3_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_MNAKX_Pos (24UL) /*!< SMB3 COMPLETION: MNAKX (Bit 24) */ -#define SMB3_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB3 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_MTR_Pos (25UL) /*!< SMB3 COMPLETION: MTR (Bit 25) */ -#define SMB3_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB3 COMPLETION: MTR (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_IDLE_Pos (29UL) /*!< SMB3 COMPLETION: IDLE (Bit 29) */ -#define SMB3_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB3 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_MDONE_Pos (30UL) /*!< SMB3 COMPLETION: MDONE (Bit 30) */ -#define SMB3_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB3 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ -#define SMB3_COMPLETION_SDONE_Pos (31UL) /*!< SMB3 COMPLETION: SDONE (Bit 31) */ -#define SMB3_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB3 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB3_IDLE_SCALING ----------------------------- */ -#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ -#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ -#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ -#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ - -/* ----------------------------- SMB3_CONFIGURATION ----------------------------- */ -#define SMB3_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bit 0) */ -#define SMB3_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ -#define SMB3_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB3 CONFIGURATION: TCEN (Bit 4) */ -#define SMB3_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB3 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bit 5) */ -#define SMB3_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB3 CONFIGURATION: PECEN (Bit 7) */ -#define SMB3_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB3 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB3 CONFIGURATION: DFEN (Bit 8) */ -#define SMB3_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB3 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_RESET_Pos (9UL) /*!< SMB3 CONFIGURATION: RESET (Bit 9) */ -#define SMB3_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB3 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB3 CONFIGURATION: ENAB (Bit 10) */ -#define SMB3_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB3 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_DSA_Pos (11UL) /*!< SMB3 CONFIGURATION: DSA (Bit 11) */ -#define SMB3_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB3 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB3 CONFIGURATION: FAIR (Bit 12) */ -#define SMB3_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB3 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bit 14) */ -#define SMB3_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ -#define SMB3_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ -#define SMB3_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ -#define SMB3_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ -#define SMB3_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bit 28) */ -#define SMB3_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB3 CONFIGURATION: ENIDI (Bit 29) */ -#define SMB3_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB3 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB3 CONFIGURATION: ENMI (Bit 30) */ -#define SMB3_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB3 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ -#define SMB3_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB3 CONFIGURATION: ENSI (Bit 31) */ -#define SMB3_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB3 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ - -/* ------------------------------- SMB3_BUS_CLOCK ------------------------------- */ -#define SMB3_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bit 0) */ -#define SMB3_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ -#define SMB3_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ -#define SMB3_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB3_BIT_BANG_CONTROL --------------------------- */ -#define SMB3_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bit 0) */ -#define SMB3_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ -#define SMB3_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bit 1) */ -#define SMB3_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ -#define SMB3_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bit 2) */ -#define SMB3_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ -#define SMB3_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bit 3) */ -#define SMB3_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ -#define SMB3_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bit 4) */ -#define SMB3_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ -#define SMB3_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ -#define SMB3_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ -#define SMB3_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bit 6) */ -#define SMB3_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ - -/* ------------------------------ SMB3_DATA_TIMING ------------------------------ */ -#define SMB3_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bit 0) */ -#define SMB3_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ -#define SMB3_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bit 8) */ -#define SMB3_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ -#define SMB3_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bit 16) */ -#define SMB3_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ -#define SMB3_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bit 24) */ -#define SMB3_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ - -/* ---------------------------- SMB3_TIME_OUT_SCALING --------------------------- */ -#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ -#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ -#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ -#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ -#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ -#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ -#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ -#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ - - -/* ================================================================================ */ -/* ================ struct 'PECI' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PECI_CONTROL -------------------------------- */ -#define PECI_CONTROL_PD_Pos (0UL) /*!< PECI CONTROL: PD (Bit 0) */ -#define PECI_CONTROL_PD_Msk (0x1UL) /*!< PECI CONTROL: PD (Bitfield-Mask: 0x01) */ -#define PECI_CONTROL_RST_Pos (3UL) /*!< PECI CONTROL: RST (Bit 3) */ -#define PECI_CONTROL_RST_Msk (0x8UL) /*!< PECI CONTROL: RST (Bitfield-Mask: 0x01) */ -#define PECI_CONTROL_FRST_Pos (5UL) /*!< PECI CONTROL: FRST (Bit 5) */ -#define PECI_CONTROL_FRST_Msk (0x20UL) /*!< PECI CONTROL: FRST (Bitfield-Mask: 0x01) */ -#define PECI_CONTROL_TXEN_Pos (6UL) /*!< PECI CONTROL: TXEN (Bit 6) */ -#define PECI_CONTROL_TXEN_Msk (0x40UL) /*!< PECI CONTROL: TXEN (Bitfield-Mask: 0x01) */ -#define PECI_CONTROL_MIEN_Pos (7UL) /*!< PECI CONTROL: MIEN (Bit 7) */ -#define PECI_CONTROL_MIEN_Msk (0x80UL) /*!< PECI CONTROL: MIEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PECI_STATUS1 -------------------------------- */ -#define PECI_STATUS1_BOF_Pos (0UL) /*!< PECI STATUS1: BOF (Bit 0) */ -#define PECI_STATUS1_BOF_Msk (0x1UL) /*!< PECI STATUS1: BOF (Bitfield-Mask: 0x01) */ -#define PECI_STATUS1_EOF_Pos (1UL) /*!< PECI STATUS1: EOF (Bit 1) */ -#define PECI_STATUS1_EOF_Msk (0x2UL) /*!< PECI STATUS1: EOF (Bitfield-Mask: 0x01) */ -#define PECI_STATUS1_ERR_Pos (2UL) /*!< PECI STATUS1: ERR (Bit 2) */ -#define PECI_STATUS1_ERR_Msk (0x4UL) /*!< PECI STATUS1: ERR (Bitfield-Mask: 0x01) */ -#define PECI_STATUS1_RDY_Pos (3UL) /*!< PECI STATUS1: RDY (Bit 3) */ -#define PECI_STATUS1_RDY_Msk (0x8UL) /*!< PECI STATUS1: RDY (Bitfield-Mask: 0x01) */ -#define PECI_STATUS1_RDYLO_Pos (4UL) /*!< PECI STATUS1: RDYLO (Bit 4) */ -#define PECI_STATUS1_RDYLO_Msk (0x10UL) /*!< PECI STATUS1: RDYLO (Bitfield-Mask: 0x01) */ -#define PECI_STATUS1_RDYHI_Pos (5UL) /*!< PECI STATUS1: RDYHI (Bit 5) */ -#define PECI_STATUS1_RDYHI_Msk (0x20UL) /*!< PECI STATUS1: RDYHI (Bitfield-Mask: 0x01) */ -#define PECI_STATUS1_MINT_Pos (7UL) /*!< PECI STATUS1: MINT (Bit 7) */ -#define PECI_STATUS1_MINT_Msk (0x80UL) /*!< PECI STATUS1: MINT (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PECI_STATUS2 -------------------------------- */ -#define PECI_STATUS2_WFF_Pos (0UL) /*!< PECI STATUS2: WFF (Bit 0) */ -#define PECI_STATUS2_WFF_Msk (0x1UL) /*!< PECI STATUS2: WFF (Bitfield-Mask: 0x01) */ -#define PECI_STATUS2_WFE_Pos (1UL) /*!< PECI STATUS2: WFE (Bit 1) */ -#define PECI_STATUS2_WFE_Msk (0x2UL) /*!< PECI STATUS2: WFE (Bitfield-Mask: 0x01) */ -#define PECI_STATUS2_RFF_Pos (2UL) /*!< PECI STATUS2: RFF (Bit 2) */ -#define PECI_STATUS2_RFF_Msk (0x4UL) /*!< PECI STATUS2: RFF (Bitfield-Mask: 0x01) */ -#define PECI_STATUS2_RFE_Pos (3UL) /*!< PECI STATUS2: RFE (Bit 3) */ -#define PECI_STATUS2_RFE_Msk (0x8UL) /*!< PECI STATUS2: RFE (Bitfield-Mask: 0x01) */ -#define PECI_STATUS2_IDLE_Pos (7UL) /*!< PECI STATUS2: IDLE (Bit 7) */ -#define PECI_STATUS2_IDLE_Msk (0x80UL) /*!< PECI STATUS2: IDLE (Bitfield-Mask: 0x01) */ - -/* --------------------------------- PECI_ERROR --------------------------------- */ -#define PECI_ERROR_FERR_Pos (0UL) /*!< PECI ERROR: FERR (Bit 0) */ -#define PECI_ERROR_FERR_Msk (0x1UL) /*!< PECI ERROR: FERR (Bitfield-Mask: 0x01) */ -#define PECI_ERROR_BERR_Pos (1UL) /*!< PECI ERROR: BERR (Bit 1) */ -#define PECI_ERROR_BERR_Msk (0x2UL) /*!< PECI ERROR: BERR (Bitfield-Mask: 0x01) */ -#define PECI_ERROR_REQERR_Pos (3UL) /*!< PECI ERROR: REQERR (Bit 3) */ -#define PECI_ERROR_REQERR_Msk (0x8UL) /*!< PECI ERROR: REQERR (Bitfield-Mask: 0x01) */ -#define PECI_ERROR_WROV_Pos (4UL) /*!< PECI ERROR: WROV (Bit 4) */ -#define PECI_ERROR_WROV_Msk (0x10UL) /*!< PECI ERROR: WROV (Bitfield-Mask: 0x01) */ -#define PECI_ERROR_WRUN_Pos (5UL) /*!< PECI ERROR: WRUN (Bit 5) */ -#define PECI_ERROR_WRUN_Msk (0x20UL) /*!< PECI ERROR: WRUN (Bitfield-Mask: 0x01) */ -#define PECI_ERROR_RDOV_Pos (6UL) /*!< PECI ERROR: RDOV (Bit 6) */ -#define PECI_ERROR_RDOV_Msk (0x40UL) /*!< PECI ERROR: RDOV (Bitfield-Mask: 0x01) */ -#define PECI_ERROR_CLKERR_Pos (7UL) /*!< PECI ERROR: CLKERR (Bit 7) */ -#define PECI_ERROR_CLKERR_Msk (0x80UL) /*!< PECI ERROR: CLKERR (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PECI_INT_EN1 -------------------------------- */ -#define PECI_INT_EN1_BIEN_Pos (0UL) /*!< PECI INT_EN1: BIEN (Bit 0) */ -#define PECI_INT_EN1_BIEN_Msk (0x1UL) /*!< PECI INT_EN1: BIEN (Bitfield-Mask: 0x01) */ -#define PECI_INT_EN1_EIEN_Pos (1UL) /*!< PECI INT_EN1: EIEN (Bit 1) */ -#define PECI_INT_EN1_EIEN_Msk (0x2UL) /*!< PECI INT_EN1: EIEN (Bitfield-Mask: 0x01) */ -#define PECI_INT_EN1_EREN_Pos (2UL) /*!< PECI INT_EN1: EREN (Bit 2) */ -#define PECI_INT_EN1_EREN_Msk (0x4UL) /*!< PECI INT_EN1: EREN (Bitfield-Mask: 0x01) */ -#define PECI_INT_EN1_RLEN_Pos (4UL) /*!< PECI INT_EN1: RLEN (Bit 4) */ -#define PECI_INT_EN1_RLEN_Msk (0x10UL) /*!< PECI INT_EN1: RLEN (Bitfield-Mask: 0x01) */ -#define PECI_INT_EN1_RHEN_Pos (5UL) /*!< PECI INT_EN1: RHEN (Bit 5) */ -#define PECI_INT_EN1_RHEN_Msk (0x20UL) /*!< PECI INT_EN1: RHEN (Bitfield-Mask: 0x01) */ - -/* -------------------------------- PECI_INT_EN2 -------------------------------- */ -#define PECI_INT_EN2_ENWFE_Pos (1UL) /*!< PECI INT_EN2: ENWFE (Bit 1) */ -#define PECI_INT_EN2_ENWFE_Msk (0x2UL) /*!< PECI INT_EN2: ENWFE (Bitfield-Mask: 0x01) */ -#define PECI_INT_EN2_ENRFF_Pos (2UL) /*!< PECI INT_EN2: ENRFF (Bit 2) */ -#define PECI_INT_EN2_ENRFF_Msk (0x4UL) /*!< PECI INT_EN2: ENRFF (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'TACH_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- TACH_0_CONTROL ------------------------------- */ -#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */ -#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */ -#define TACH_0_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_0 CONTROL: TACH_EN (Bit 1) */ -#define TACH_0_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_0 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */ -#define TACH_0_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_0 CONTROL: FILTER_EN (Bit 8) */ -#define TACH_0_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_0 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */ -#define TACH_0_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bit 10) */ -#define TACH_0_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */ -#define TACH_0_CONTROL_EDGES_Pos (11UL) /*!< TACH_0 CONTROL: EDGES (Bit 11) */ -#define TACH_0_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_0 CONTROL: EDGES (Bitfield-Mask: 0x03) */ -#define TACH_0_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bit 14) */ -#define TACH_0_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */ -#define TACH_0_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bit 15) */ -#define TACH_0_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */ -#define TACH_0_CONTROL_COUNTER_Pos (16UL) /*!< TACH_0 CONTROL: COUNTER (Bit 16) */ -#define TACH_0_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_0 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- TACH_0_STATUS ------------------------------- */ -#define TACH_0_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bit 0) */ -#define TACH_0_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */ -#define TACH_0_STATUS_PIN_Pos (1UL) /*!< TACH_0 STATUS: PIN (Bit 1) */ -#define TACH_0_STATUS_PIN_Msk (0x2UL) /*!< TACH_0 STATUS: PIN (Bitfield-Mask: 0x01) */ -#define TACH_0_STATUS_TOGGLE_Pos (2UL) /*!< TACH_0 STATUS: TOGGLE (Bit 2) */ -#define TACH_0_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_0 STATUS: TOGGLE (Bitfield-Mask: 0x01) */ -#define TACH_0_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_0 STATUS: COUNT_READY (Bit 3) */ -#define TACH_0_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_0 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'TACH_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- TACH_1_CONTROL ------------------------------- */ -#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */ -#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */ -#define TACH_1_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_1 CONTROL: TACH_EN (Bit 1) */ -#define TACH_1_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_1 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */ -#define TACH_1_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_1 CONTROL: FILTER_EN (Bit 8) */ -#define TACH_1_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_1 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */ -#define TACH_1_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bit 10) */ -#define TACH_1_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */ -#define TACH_1_CONTROL_EDGES_Pos (11UL) /*!< TACH_1 CONTROL: EDGES (Bit 11) */ -#define TACH_1_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_1 CONTROL: EDGES (Bitfield-Mask: 0x03) */ -#define TACH_1_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bit 14) */ -#define TACH_1_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */ -#define TACH_1_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bit 15) */ -#define TACH_1_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */ -#define TACH_1_CONTROL_COUNTER_Pos (16UL) /*!< TACH_1 CONTROL: COUNTER (Bit 16) */ -#define TACH_1_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_1 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */ - -/* -------------------------------- TACH_1_STATUS ------------------------------- */ -#define TACH_1_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bit 0) */ -#define TACH_1_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */ -#define TACH_1_STATUS_PIN_Pos (1UL) /*!< TACH_1 STATUS: PIN (Bit 1) */ -#define TACH_1_STATUS_PIN_Msk (0x2UL) /*!< TACH_1 STATUS: PIN (Bitfield-Mask: 0x01) */ -#define TACH_1_STATUS_TOGGLE_Pos (2UL) /*!< TACH_1 STATUS: TOGGLE (Bit 2) */ -#define TACH_1_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_1 STATUS: TOGGLE (Bitfield-Mask: 0x01) */ -#define TACH_1_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_1 STATUS: COUNT_READY (Bit 3) */ -#define TACH_1_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_1 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'PWM_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PWM_0_CONFIG -------------------------------- */ -#define PWM_0_CONFIG_EN_Pos (0UL) /*!< PWM_0 CONFIG: EN (Bit 0) */ -#define PWM_0_CONFIG_EN_Msk (0x1UL) /*!< PWM_0 CONFIG: EN (Bitfield-Mask: 0x01) */ -#define PWM_0_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bit 1) */ -#define PWM_0_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ -#define PWM_0_CONFIG_INVERT_Pos (2UL) /*!< PWM_0 CONFIG: INVERT (Bit 2) */ -#define PWM_0_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_0 CONFIG: INVERT (Bitfield-Mask: 0x01) */ -#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ -#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'PWM_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PWM_1_CONFIG -------------------------------- */ -#define PWM_1_CONFIG_EN_Pos (0UL) /*!< PWM_1 CONFIG: EN (Bit 0) */ -#define PWM_1_CONFIG_EN_Msk (0x1UL) /*!< PWM_1 CONFIG: EN (Bitfield-Mask: 0x01) */ -#define PWM_1_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bit 1) */ -#define PWM_1_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ -#define PWM_1_CONFIG_INVERT_Pos (2UL) /*!< PWM_1 CONFIG: INVERT (Bit 2) */ -#define PWM_1_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_1 CONFIG: INVERT (Bitfield-Mask: 0x01) */ -#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ -#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'PWM_2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PWM_2_CONFIG -------------------------------- */ -#define PWM_2_CONFIG_EN_Pos (0UL) /*!< PWM_2 CONFIG: EN (Bit 0) */ -#define PWM_2_CONFIG_EN_Msk (0x1UL) /*!< PWM_2 CONFIG: EN (Bitfield-Mask: 0x01) */ -#define PWM_2_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bit 1) */ -#define PWM_2_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ -#define PWM_2_CONFIG_INVERT_Pos (2UL) /*!< PWM_2 CONFIG: INVERT (Bit 2) */ -#define PWM_2_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_2 CONFIG: INVERT (Bitfield-Mask: 0x01) */ -#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ -#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'PWM_3' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PWM_3_CONFIG -------------------------------- */ -#define PWM_3_CONFIG_EN_Pos (0UL) /*!< PWM_3 CONFIG: EN (Bit 0) */ -#define PWM_3_CONFIG_EN_Msk (0x1UL) /*!< PWM_3 CONFIG: EN (Bitfield-Mask: 0x01) */ -#define PWM_3_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bit 1) */ -#define PWM_3_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ -#define PWM_3_CONFIG_INVERT_Pos (2UL) /*!< PWM_3 CONFIG: INVERT (Bit 2) */ -#define PWM_3_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_3 CONFIG: INVERT (Bitfield-Mask: 0x01) */ -#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ -#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'RPM_FAN' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ---------------------------- RPM_FAN_CONFIGURATION --------------------------- */ -#define RPM_FAN_CONFIGURATION_UPDATE_Pos (0UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bit 0) */ -#define RPM_FAN_CONFIGURATION_UPDATE_Msk (0x7UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bitfield-Mask: 0x07) */ -#define RPM_FAN_CONFIGURATION_EDGES_Pos (3UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bit 3) */ -#define RPM_FAN_CONFIGURATION_EDGES_Msk (0x18UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bitfield-Mask: 0x03) */ -#define RPM_FAN_CONFIGURATION_RANGE_Pos (5UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bit 5) */ -#define RPM_FAN_CONFIGURATION_RANGE_Msk (0x60UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bitfield-Mask: 0x03) */ -#define RPM_FAN_CONFIGURATION_EN_ALGO_Pos (7UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bit 7) */ -#define RPM_FAN_CONFIGURATION_EN_ALGO_Msk (0x80UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bitfield-Mask: 0x01) */ -#define RPM_FAN_CONFIGURATION_POLARITY_Pos (8UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bit 8) */ -#define RPM_FAN_CONFIGURATION_POLARITY_Msk (0x100UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bitfield-Mask: 0x01) */ -#define RPM_FAN_CONFIGURATION_ERR_RNG_Pos (9UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bit 9) */ -#define RPM_FAN_CONFIGURATION_ERR_RNG_Msk (0x600UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bitfield-Mask: 0x03) */ -#define RPM_FAN_CONFIGURATION_DER_OPT_Pos (11UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bit 11) */ -#define RPM_FAN_CONFIGURATION_DER_OPT_Msk (0x1800UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bitfield-Mask: 0x03) */ -#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Pos (13UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bit 13) */ -#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Msk (0x2000UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bitfield-Mask: 0x01) */ -#define RPM_FAN_CONFIGURATION_EN_RRC_Pos (14UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bit 14) */ -#define RPM_FAN_CONFIGURATION_EN_RRC_Msk (0x4000UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bitfield-Mask: 0x01) */ - -/* -------------------------------- RPM_FAN_GAIN -------------------------------- */ -#define RPM_FAN_GAIN_GAINP_Pos (0UL) /*!< RPM_FAN GAIN: GAINP (Bit 0) */ -#define RPM_FAN_GAIN_GAINP_Msk (0x3UL) /*!< RPM_FAN GAIN: GAINP (Bitfield-Mask: 0x03) */ -#define RPM_FAN_GAIN_GAINI_Pos (2UL) /*!< RPM_FAN GAIN: GAINI (Bit 2) */ -#define RPM_FAN_GAIN_GAINI_Msk (0xcUL) /*!< RPM_FAN GAIN: GAINI (Bitfield-Mask: 0x03) */ -#define RPM_FAN_GAIN_GAIND_Pos (4UL) /*!< RPM_FAN GAIN: GAIND (Bit 4) */ -#define RPM_FAN_GAIN_GAIND_Msk (0x30UL) /*!< RPM_FAN GAIN: GAIND (Bitfield-Mask: 0x03) */ - -/* ------------------------ RPM_FAN_SPIN_UP_CONFIGURATION ----------------------- */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Pos (0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bit 0) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Msk (0x3UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bitfield-Mask: 0x03) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Pos (2UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bit 2) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Msk (0x1cUL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bitfield-Mask: 0x07) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Pos (5UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bit 5) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Msk (0x20UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bitfield-Mask: 0x01) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Pos (6UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bit 6) */ -#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Msk (0xc0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bitfield-Mask: 0x03) */ - -/* ------------------------------- RPM_FAN_STATUS ------------------------------- */ -#define RPM_FAN_STATUS_FAN_STALL_Pos (0UL) /*!< RPM_FAN STATUS: FAN_STALL (Bit 0) */ -#define RPM_FAN_STATUS_FAN_STALL_Msk (0x1UL) /*!< RPM_FAN STATUS: FAN_STALL (Bitfield-Mask: 0x01) */ -#define RPM_FAN_STATUS_FAN_SPIN_Pos (1UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bit 1) */ -#define RPM_FAN_STATUS_FAN_SPIN_Msk (0x2UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bitfield-Mask: 0x01) */ -#define RPM_FAN_STATUS_DRIVE_FAIL_Pos (5UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bit 5) */ -#define RPM_FAN_STATUS_DRIVE_FAIL_Msk (0x20UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'SPI_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- SPI_0_CONTROL ------------------------------- */ -#define SPI_0_CONTROL_LSBF_Pos (0UL) /*!< SPI_0 CONTROL: LSBF (Bit 0) */ -#define SPI_0_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_0 CONTROL: LSBF (Bitfield-Mask: 0x01) */ -#define SPI_0_CONTROL_BIOEN_Pos (1UL) /*!< SPI_0 CONTROL: BIOEN (Bit 1) */ -#define SPI_0_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_0 CONTROL: BIOEN (Bitfield-Mask: 0x01) */ -#define SPI_0_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bit 2) */ -#define SPI_0_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */ -#define SPI_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bit 4) */ -#define SPI_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define SPI_0_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_0 CONTROL: AUTO_READ (Bit 5) */ -#define SPI_0_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_0 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */ -#define SPI_0_CONTROL_CE_Pos (6UL) /*!< SPI_0 CONTROL: CE (Bit 6) */ -#define SPI_0_CONTROL_CE_Msk (0x40UL) /*!< SPI_0 CONTROL: CE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- SPI_0_STATUS -------------------------------- */ -#define SPI_0_STATUS_TXBE_Pos (0UL) /*!< SPI_0 STATUS: TXBE (Bit 0) */ -#define SPI_0_STATUS_TXBE_Msk (0x1UL) /*!< SPI_0 STATUS: TXBE (Bitfield-Mask: 0x01) */ -#define SPI_0_STATUS_RXBF_Pos (1UL) /*!< SPI_0 STATUS: RXBF (Bit 1) */ -#define SPI_0_STATUS_RXBF_Msk (0x2UL) /*!< SPI_0 STATUS: RXBF (Bitfield-Mask: 0x01) */ -#define SPI_0_STATUS_ACTIVE_Pos (2UL) /*!< SPI_0 STATUS: ACTIVE (Bit 2) */ -#define SPI_0_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_0 STATUS: ACTIVE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SPI_0_CLOCK_Control ---------------------------- */ -#define SPI_0_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bit 0) */ -#define SPI_0_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */ -#define SPI_0_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bit 1) */ -#define SPI_0_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */ -#define SPI_0_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bit 2) */ -#define SPI_0_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */ -#define SPI_0_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bit 4) */ -#define SPI_0_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'SPI_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- SPI_1_CONTROL ------------------------------- */ -#define SPI_1_CONTROL_LSBF_Pos (0UL) /*!< SPI_1 CONTROL: LSBF (Bit 0) */ -#define SPI_1_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_1 CONTROL: LSBF (Bitfield-Mask: 0x01) */ -#define SPI_1_CONTROL_BIOEN_Pos (1UL) /*!< SPI_1 CONTROL: BIOEN (Bit 1) */ -#define SPI_1_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_1 CONTROL: BIOEN (Bitfield-Mask: 0x01) */ -#define SPI_1_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bit 2) */ -#define SPI_1_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */ -#define SPI_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bit 4) */ -#define SPI_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define SPI_1_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_1 CONTROL: AUTO_READ (Bit 5) */ -#define SPI_1_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_1 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */ -#define SPI_1_CONTROL_CE_Pos (6UL) /*!< SPI_1 CONTROL: CE (Bit 6) */ -#define SPI_1_CONTROL_CE_Msk (0x40UL) /*!< SPI_1 CONTROL: CE (Bitfield-Mask: 0x01) */ - -/* -------------------------------- SPI_1_STATUS -------------------------------- */ -#define SPI_1_STATUS_TXBE_Pos (0UL) /*!< SPI_1 STATUS: TXBE (Bit 0) */ -#define SPI_1_STATUS_TXBE_Msk (0x1UL) /*!< SPI_1 STATUS: TXBE (Bitfield-Mask: 0x01) */ -#define SPI_1_STATUS_RXBF_Pos (1UL) /*!< SPI_1 STATUS: RXBF (Bit 1) */ -#define SPI_1_STATUS_RXBF_Msk (0x2UL) /*!< SPI_1 STATUS: RXBF (Bitfield-Mask: 0x01) */ -#define SPI_1_STATUS_ACTIVE_Pos (2UL) /*!< SPI_1 STATUS: ACTIVE (Bit 2) */ -#define SPI_1_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_1 STATUS: ACTIVE (Bitfield-Mask: 0x01) */ - -/* ----------------------------- SPI_1_CLOCK_Control ---------------------------- */ -#define SPI_1_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bit 0) */ -#define SPI_1_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */ -#define SPI_1_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bit 1) */ -#define SPI_1_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */ -#define SPI_1_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bit 2) */ -#define SPI_1_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */ -#define SPI_1_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bit 4) */ -#define SPI_1_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'LED_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- LED_0_CONFIG -------------------------------- */ -#define LED_0_CONFIG_CONTROL_Pos (0UL) /*!< LED_0 CONFIG: CONTROL (Bit 0) */ -#define LED_0_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_0 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ -#define LED_0_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bit 2) */ -#define LED_0_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ -#define LED_0_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bit 3) */ -#define LED_0_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ -#define LED_0_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_0 CONFIG: PWM_SIZE (Bit 4) */ -#define LED_0_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_0 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ -#define LED_0_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bit 6) */ -#define LED_0_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ -#define LED_0_CONFIG_RESET_Pos (7UL) /*!< LED_0 CONFIG: RESET (Bit 7) */ -#define LED_0_CONFIG_RESET_Msk (0x80UL) /*!< LED_0 CONFIG: RESET (Bitfield-Mask: 0x01) */ -#define LED_0_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bit 8) */ -#define LED_0_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ -#define LED_0_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_0 CONFIG: SYMMETRY (Bit 16) */ -#define LED_0_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_0 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ - -/* -------------------------------- LED_0_LIMITS -------------------------------- */ -#define LED_0_LIMITS_MINIMUM_Pos (0UL) /*!< LED_0 LIMITS: MINIMUM (Bit 0) */ -#define LED_0_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_0 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ -#define LED_0_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_0 LIMITS: MAXIMUM (Bit 8) */ -#define LED_0_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_0 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ - -/* --------------------------------- LED_0_DELAY -------------------------------- */ -#define LED_0_DELAY_LOW_Pos (0UL) /*!< LED_0 DELAY: LOW (Bit 0) */ -#define LED_0_DELAY_LOW_Msk (0xfffUL) /*!< LED_0 DELAY: LOW (Bitfield-Mask: 0xfff) */ -#define LED_0_DELAY_HIGH_Pos (12UL) /*!< LED_0 DELAY: HIGH (Bit 12) */ -#define LED_0_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_0 DELAY: HIGH (Bitfield-Mask: 0xfff) */ - -/* ---------------------------- LED_0_UPDATE_STEPSIZE --------------------------- */ -#define LED_0_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bit 0) */ -#define LED_0_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bit 4) */ -#define LED_0_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bit 8) */ -#define LED_0_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bit 12) */ -#define LED_0_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bit 16) */ -#define LED_0_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bit 20) */ -#define LED_0_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bit 24) */ -#define LED_0_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bit 28) */ -#define LED_0_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- LED_0_UPDATE_INTERVAL --------------------------- */ -#define LED_0_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ -#define LED_0_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'LED_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- LED_1_CONFIG -------------------------------- */ -#define LED_1_CONFIG_CONTROL_Pos (0UL) /*!< LED_1 CONFIG: CONTROL (Bit 0) */ -#define LED_1_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_1 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ -#define LED_1_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bit 2) */ -#define LED_1_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ -#define LED_1_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bit 3) */ -#define LED_1_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ -#define LED_1_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_1 CONFIG: PWM_SIZE (Bit 4) */ -#define LED_1_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_1 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ -#define LED_1_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bit 6) */ -#define LED_1_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ -#define LED_1_CONFIG_RESET_Pos (7UL) /*!< LED_1 CONFIG: RESET (Bit 7) */ -#define LED_1_CONFIG_RESET_Msk (0x80UL) /*!< LED_1 CONFIG: RESET (Bitfield-Mask: 0x01) */ -#define LED_1_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bit 8) */ -#define LED_1_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ -#define LED_1_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_1 CONFIG: SYMMETRY (Bit 16) */ -#define LED_1_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_1 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ - -/* -------------------------------- LED_1_LIMITS -------------------------------- */ -#define LED_1_LIMITS_MINIMUM_Pos (0UL) /*!< LED_1 LIMITS: MINIMUM (Bit 0) */ -#define LED_1_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_1 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ -#define LED_1_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_1 LIMITS: MAXIMUM (Bit 8) */ -#define LED_1_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_1 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ - -/* --------------------------------- LED_1_DELAY -------------------------------- */ -#define LED_1_DELAY_LOW_Pos (0UL) /*!< LED_1 DELAY: LOW (Bit 0) */ -#define LED_1_DELAY_LOW_Msk (0xfffUL) /*!< LED_1 DELAY: LOW (Bitfield-Mask: 0xfff) */ -#define LED_1_DELAY_HIGH_Pos (12UL) /*!< LED_1 DELAY: HIGH (Bit 12) */ -#define LED_1_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_1 DELAY: HIGH (Bitfield-Mask: 0xfff) */ - -/* ---------------------------- LED_1_UPDATE_STEPSIZE --------------------------- */ -#define LED_1_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bit 0) */ -#define LED_1_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bit 4) */ -#define LED_1_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bit 8) */ -#define LED_1_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bit 12) */ -#define LED_1_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bit 16) */ -#define LED_1_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bit 20) */ -#define LED_1_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bit 24) */ -#define LED_1_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bit 28) */ -#define LED_1_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- LED_1_UPDATE_INTERVAL --------------------------- */ -#define LED_1_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ -#define LED_1_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'LED_2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- LED_2_CONFIG -------------------------------- */ -#define LED_2_CONFIG_CONTROL_Pos (0UL) /*!< LED_2 CONFIG: CONTROL (Bit 0) */ -#define LED_2_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_2 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ -#define LED_2_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bit 2) */ -#define LED_2_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ -#define LED_2_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bit 3) */ -#define LED_2_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ -#define LED_2_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_2 CONFIG: PWM_SIZE (Bit 4) */ -#define LED_2_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_2 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ -#define LED_2_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bit 6) */ -#define LED_2_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ -#define LED_2_CONFIG_RESET_Pos (7UL) /*!< LED_2 CONFIG: RESET (Bit 7) */ -#define LED_2_CONFIG_RESET_Msk (0x80UL) /*!< LED_2 CONFIG: RESET (Bitfield-Mask: 0x01) */ -#define LED_2_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bit 8) */ -#define LED_2_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ -#define LED_2_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_2 CONFIG: SYMMETRY (Bit 16) */ -#define LED_2_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_2 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ - -/* -------------------------------- LED_2_LIMITS -------------------------------- */ -#define LED_2_LIMITS_MINIMUM_Pos (0UL) /*!< LED_2 LIMITS: MINIMUM (Bit 0) */ -#define LED_2_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_2 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ -#define LED_2_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_2 LIMITS: MAXIMUM (Bit 8) */ -#define LED_2_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_2 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ - -/* --------------------------------- LED_2_DELAY -------------------------------- */ -#define LED_2_DELAY_LOW_Pos (0UL) /*!< LED_2 DELAY: LOW (Bit 0) */ -#define LED_2_DELAY_LOW_Msk (0xfffUL) /*!< LED_2 DELAY: LOW (Bitfield-Mask: 0xfff) */ -#define LED_2_DELAY_HIGH_Pos (12UL) /*!< LED_2 DELAY: HIGH (Bit 12) */ -#define LED_2_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_2 DELAY: HIGH (Bitfield-Mask: 0xfff) */ - -/* ---------------------------- LED_2_UPDATE_STEPSIZE --------------------------- */ -#define LED_2_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bit 0) */ -#define LED_2_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bit 4) */ -#define LED_2_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bit 8) */ -#define LED_2_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bit 12) */ -#define LED_2_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bit 16) */ -#define LED_2_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bit 20) */ -#define LED_2_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bit 24) */ -#define LED_2_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bit 28) */ -#define LED_2_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- LED_2_UPDATE_INTERVAL --------------------------- */ -#define LED_2_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ -#define LED_2_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'LED_3' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- LED_3_CONFIG -------------------------------- */ -#define LED_3_CONFIG_CONTROL_Pos (0UL) /*!< LED_3 CONFIG: CONTROL (Bit 0) */ -#define LED_3_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_3 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ -#define LED_3_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bit 2) */ -#define LED_3_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ -#define LED_3_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bit 3) */ -#define LED_3_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ -#define LED_3_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_3 CONFIG: PWM_SIZE (Bit 4) */ -#define LED_3_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_3 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ -#define LED_3_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bit 6) */ -#define LED_3_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ -#define LED_3_CONFIG_RESET_Pos (7UL) /*!< LED_3 CONFIG: RESET (Bit 7) */ -#define LED_3_CONFIG_RESET_Msk (0x80UL) /*!< LED_3 CONFIG: RESET (Bitfield-Mask: 0x01) */ -#define LED_3_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bit 8) */ -#define LED_3_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ -#define LED_3_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_3 CONFIG: SYMMETRY (Bit 16) */ -#define LED_3_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_3 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ - -/* -------------------------------- LED_3_LIMITS -------------------------------- */ -#define LED_3_LIMITS_MINIMUM_Pos (0UL) /*!< LED_3 LIMITS: MINIMUM (Bit 0) */ -#define LED_3_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_3 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ -#define LED_3_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_3 LIMITS: MAXIMUM (Bit 8) */ -#define LED_3_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_3 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ - -/* --------------------------------- LED_3_DELAY -------------------------------- */ -#define LED_3_DELAY_LOW_Pos (0UL) /*!< LED_3 DELAY: LOW (Bit 0) */ -#define LED_3_DELAY_LOW_Msk (0xfffUL) /*!< LED_3 DELAY: LOW (Bitfield-Mask: 0xfff) */ -#define LED_3_DELAY_HIGH_Pos (12UL) /*!< LED_3 DELAY: HIGH (Bit 12) */ -#define LED_3_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_3 DELAY: HIGH (Bitfield-Mask: 0xfff) */ - -/* ---------------------------- LED_3_UPDATE_STEPSIZE --------------------------- */ -#define LED_3_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bit 0) */ -#define LED_3_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bit 4) */ -#define LED_3_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bit 8) */ -#define LED_3_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bit 12) */ -#define LED_3_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bit 16) */ -#define LED_3_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bit 20) */ -#define LED_3_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bit 24) */ -#define LED_3_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bit 28) */ -#define LED_3_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ - -/* ---------------------------- LED_3_UPDATE_INTERVAL --------------------------- */ -#define LED_3_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ -#define LED_3_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ - - -/* ================================================================================ */ -/* ================ struct 'PS2_0' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PS2_0_CONTROL ------------------------------- */ -#define PS2_0_CONTROL_TR_Pos (0UL) /*!< PS2_0 CONTROL: TR (Bit 0) */ -#define PS2_0_CONTROL_TR_Msk (0x1UL) /*!< PS2_0 CONTROL: TR (Bitfield-Mask: 0x01) */ -#define PS2_0_CONTROL_EN_Pos (1UL) /*!< PS2_0 CONTROL: EN (Bit 1) */ -#define PS2_0_CONTROL_EN_Msk (0x2UL) /*!< PS2_0 CONTROL: EN (Bitfield-Mask: 0x01) */ -#define PS2_0_CONTROL_PARITY_Pos (2UL) /*!< PS2_0 CONTROL: PARITY (Bit 2) */ -#define PS2_0_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_0 CONTROL: PARITY (Bitfield-Mask: 0x03) */ -#define PS2_0_CONTROL_STOP_Pos (4UL) /*!< PS2_0 CONTROL: STOP (Bit 4) */ -#define PS2_0_CONTROL_STOP_Msk (0x30UL) /*!< PS2_0 CONTROL: STOP (Bitfield-Mask: 0x03) */ - -/* -------------------------------- PS2_0_STATUS -------------------------------- */ -#define PS2_0_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_0 STATUS: RDATA_RDY (Bit 0) */ -#define PS2_0_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_0 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bit 1) */ -#define PS2_0_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_PE_Pos (2UL) /*!< PS2_0 STATUS: PE (Bit 2) */ -#define PS2_0_STATUS_PE_Msk (0x4UL) /*!< PS2_0 STATUS: PE (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_FE_Pos (3UL) /*!< PS2_0 STATUS: FE (Bit 3) */ -#define PS2_0_STATUS_FE_Msk (0x8UL) /*!< PS2_0 STATUS: FE (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bit 4) */ -#define PS2_0_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bit 5) */ -#define PS2_0_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_0 STATUS: RX_BUSY (Bit 6) */ -#define PS2_0_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_0 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ -#define PS2_0_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bit 7) */ -#define PS2_0_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'PS2_1' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PS2_1_CONTROL ------------------------------- */ -#define PS2_1_CONTROL_TR_Pos (0UL) /*!< PS2_1 CONTROL: TR (Bit 0) */ -#define PS2_1_CONTROL_TR_Msk (0x1UL) /*!< PS2_1 CONTROL: TR (Bitfield-Mask: 0x01) */ -#define PS2_1_CONTROL_EN_Pos (1UL) /*!< PS2_1 CONTROL: EN (Bit 1) */ -#define PS2_1_CONTROL_EN_Msk (0x2UL) /*!< PS2_1 CONTROL: EN (Bitfield-Mask: 0x01) */ -#define PS2_1_CONTROL_PARITY_Pos (2UL) /*!< PS2_1 CONTROL: PARITY (Bit 2) */ -#define PS2_1_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_1 CONTROL: PARITY (Bitfield-Mask: 0x03) */ -#define PS2_1_CONTROL_STOP_Pos (4UL) /*!< PS2_1 CONTROL: STOP (Bit 4) */ -#define PS2_1_CONTROL_STOP_Msk (0x30UL) /*!< PS2_1 CONTROL: STOP (Bitfield-Mask: 0x03) */ - -/* -------------------------------- PS2_1_STATUS -------------------------------- */ -#define PS2_1_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_1 STATUS: RDATA_RDY (Bit 0) */ -#define PS2_1_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_1 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bit 1) */ -#define PS2_1_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_PE_Pos (2UL) /*!< PS2_1 STATUS: PE (Bit 2) */ -#define PS2_1_STATUS_PE_Msk (0x4UL) /*!< PS2_1 STATUS: PE (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_FE_Pos (3UL) /*!< PS2_1 STATUS: FE (Bit 3) */ -#define PS2_1_STATUS_FE_Msk (0x8UL) /*!< PS2_1 STATUS: FE (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bit 4) */ -#define PS2_1_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bit 5) */ -#define PS2_1_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_1 STATUS: RX_BUSY (Bit 6) */ -#define PS2_1_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_1 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ -#define PS2_1_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bit 7) */ -#define PS2_1_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'PS2_2' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PS2_2_CONTROL ------------------------------- */ -#define PS2_2_CONTROL_TR_Pos (0UL) /*!< PS2_2 CONTROL: TR (Bit 0) */ -#define PS2_2_CONTROL_TR_Msk (0x1UL) /*!< PS2_2 CONTROL: TR (Bitfield-Mask: 0x01) */ -#define PS2_2_CONTROL_EN_Pos (1UL) /*!< PS2_2 CONTROL: EN (Bit 1) */ -#define PS2_2_CONTROL_EN_Msk (0x2UL) /*!< PS2_2 CONTROL: EN (Bitfield-Mask: 0x01) */ -#define PS2_2_CONTROL_PARITY_Pos (2UL) /*!< PS2_2 CONTROL: PARITY (Bit 2) */ -#define PS2_2_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_2 CONTROL: PARITY (Bitfield-Mask: 0x03) */ -#define PS2_2_CONTROL_STOP_Pos (4UL) /*!< PS2_2 CONTROL: STOP (Bit 4) */ -#define PS2_2_CONTROL_STOP_Msk (0x30UL) /*!< PS2_2 CONTROL: STOP (Bitfield-Mask: 0x03) */ - -/* -------------------------------- PS2_2_STATUS -------------------------------- */ -#define PS2_2_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_2 STATUS: RDATA_RDY (Bit 0) */ -#define PS2_2_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_2 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bit 1) */ -#define PS2_2_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_PE_Pos (2UL) /*!< PS2_2 STATUS: PE (Bit 2) */ -#define PS2_2_STATUS_PE_Msk (0x4UL) /*!< PS2_2 STATUS: PE (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_FE_Pos (3UL) /*!< PS2_2 STATUS: FE (Bit 3) */ -#define PS2_2_STATUS_FE_Msk (0x8UL) /*!< PS2_2 STATUS: FE (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bit 4) */ -#define PS2_2_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bit 5) */ -#define PS2_2_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_2 STATUS: RX_BUSY (Bit 6) */ -#define PS2_2_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_2 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ -#define PS2_2_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bit 7) */ -#define PS2_2_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'PS2_3' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- PS2_3_CONTROL ------------------------------- */ -#define PS2_3_CONTROL_TR_Pos (0UL) /*!< PS2_3 CONTROL: TR (Bit 0) */ -#define PS2_3_CONTROL_TR_Msk (0x1UL) /*!< PS2_3 CONTROL: TR (Bitfield-Mask: 0x01) */ -#define PS2_3_CONTROL_EN_Pos (1UL) /*!< PS2_3 CONTROL: EN (Bit 1) */ -#define PS2_3_CONTROL_EN_Msk (0x2UL) /*!< PS2_3 CONTROL: EN (Bitfield-Mask: 0x01) */ -#define PS2_3_CONTROL_PARITY_Pos (2UL) /*!< PS2_3 CONTROL: PARITY (Bit 2) */ -#define PS2_3_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_3 CONTROL: PARITY (Bitfield-Mask: 0x03) */ -#define PS2_3_CONTROL_STOP_Pos (4UL) /*!< PS2_3 CONTROL: STOP (Bit 4) */ -#define PS2_3_CONTROL_STOP_Msk (0x30UL) /*!< PS2_3 CONTROL: STOP (Bitfield-Mask: 0x03) */ - -/* -------------------------------- PS2_3_STATUS -------------------------------- */ -#define PS2_3_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_3 STATUS: RDATA_RDY (Bit 0) */ -#define PS2_3_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_3 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bit 1) */ -#define PS2_3_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_PE_Pos (2UL) /*!< PS2_3 STATUS: PE (Bit 2) */ -#define PS2_3_STATUS_PE_Msk (0x4UL) /*!< PS2_3 STATUS: PE (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_FE_Pos (3UL) /*!< PS2_3 STATUS: FE (Bit 3) */ -#define PS2_3_STATUS_FE_Msk (0x8UL) /*!< PS2_3 STATUS: FE (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bit 4) */ -#define PS2_3_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bit 5) */ -#define PS2_3_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_3 STATUS: RX_BUSY (Bit 6) */ -#define PS2_3_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_3 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ -#define PS2_3_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bit 7) */ -#define PS2_3_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'KEYSCAN' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- KEYSCAN_CONTROL ------------------------------ */ -#define KEYSCAN_CONTROL_SELECT_Pos (0UL) /*!< KEYSCAN CONTROL: SELECT (Bit 0) */ -#define KEYSCAN_CONTROL_SELECT_Msk (0x1fUL) /*!< KEYSCAN CONTROL: SELECT (Bitfield-Mask: 0x1f) */ -#define KEYSCAN_CONTROL_ALL_Pos (5UL) /*!< KEYSCAN CONTROL: ALL (Bit 5) */ -#define KEYSCAN_CONTROL_ALL_Msk (0x20UL) /*!< KEYSCAN CONTROL: ALL (Bitfield-Mask: 0x01) */ -#define KEYSCAN_CONTROL_KSEN_Pos (6UL) /*!< KEYSCAN CONTROL: KSEN (Bit 6) */ -#define KEYSCAN_CONTROL_KSEN_Msk (0x40UL) /*!< KEYSCAN CONTROL: KSEN (Bitfield-Mask: 0x01) */ -#define KEYSCAN_CONTROL_INVERT_Pos (7UL) /*!< KEYSCAN CONTROL: INVERT (Bit 7) */ -#define KEYSCAN_CONTROL_INVERT_Msk (0x80UL) /*!< KEYSCAN CONTROL: INVERT (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'BC_LINK' Position & Mask ================ */ -/* ================================================================================ */ - - -/* ------------------------------- BC_LINK_STATUS ------------------------------- */ -#define BC_LINK_STATUS_BUSY_Pos (0UL) /*!< BC_LINK STATUS: BUSY (Bit 0) */ -#define BC_LINK_STATUS_BUSY_Msk (0x1UL) /*!< BC_LINK STATUS: BUSY (Bitfield-Mask: 0x01) */ -#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Pos (4UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bit 4) */ -#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Msk (0x10UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bitfield-Mask: 0x01) */ -#define BC_LINK_STATUS_ERR_INT_EN_Pos (5UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bit 5) */ -#define BC_LINK_STATUS_ERR_INT_EN_Msk (0x20UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bitfield-Mask: 0x01) */ -#define BC_LINK_STATUS_ERROR_Pos (6UL) /*!< BC_LINK STATUS: ERROR (Bit 6) */ -#define BC_LINK_STATUS_ERROR_Msk (0x40UL) /*!< BC_LINK STATUS: ERROR (Bitfield-Mask: 0x01) */ -#define BC_LINK_STATUS_RESET_Pos (7UL) /*!< BC_LINK STATUS: RESET (Bit 7) */ -#define BC_LINK_STATUS_RESET_Msk (0x80UL) /*!< BC_LINK STATUS: RESET (Bitfield-Mask: 0x01) */ - - -/* ================================================================================ */ -/* ================ struct 'TFDP' Position & Mask ================ */ -/* ================================================================================ */ - - -/* -------------------------------- TFDP_CONTROL -------------------------------- */ -#define TFDP_CONTROL_EN_Pos (0UL) /*!< TFDP CONTROL: EN (Bit 0) */ -#define TFDP_CONTROL_EN_Msk (0x1UL) /*!< TFDP CONTROL: EN (Bitfield-Mask: 0x01) */ -#define TFDP_CONTROL_EDGE_SEL_Pos (1UL) /*!< TFDP CONTROL: EDGE_SEL (Bit 1) */ -#define TFDP_CONTROL_EDGE_SEL_Msk (0x2UL) /*!< TFDP CONTROL: EDGE_SEL (Bitfield-Mask: 0x01) */ -#define TFDP_CONTROL_DIVSEL_Pos (2UL) /*!< TFDP CONTROL: DIVSEL (Bit 2) */ -#define TFDP_CONTROL_DIVSEL_Msk (0xcUL) /*!< TFDP CONTROL: DIVSEL (Bitfield-Mask: 0x03) */ -#define TFDP_CONTROL_IP_DELAY_Pos (4UL) /*!< TFDP CONTROL: IP_DELAY (Bit 4) */ -#define TFDP_CONTROL_IP_DELAY_Msk (0x70UL) /*!< TFDP CONTROL: IP_DELAY (Bitfield-Mask: 0x07) */ - - -/* ================================================================================ */ -/* ================ struct 'ADC' Position & Mask ================ */ -/* ================================================================================ */ - - -/* --------------------------------- ADC_CONTROL -------------------------------- */ -#define ADC_CONTROL_ACTIVATE_Pos (0UL) /*!< ADC CONTROL: ACTIVATE (Bit 0) */ -#define ADC_CONTROL_ACTIVATE_Msk (0x1UL) /*!< ADC CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */ -#define ADC_CONTROL_START_SINGLE_Pos (1UL) /*!< ADC CONTROL: START_SINGLE (Bit 1) */ -#define ADC_CONTROL_START_SINGLE_Msk (0x2UL) /*!< ADC CONTROL: START_SINGLE (Bitfield-Mask: 0x01) */ -#define ADC_CONTROL_START_REPEAT_Pos (2UL) /*!< ADC CONTROL: START_REPEAT (Bit 2) */ -#define ADC_CONTROL_START_REPEAT_Msk (0x4UL) /*!< ADC CONTROL: START_REPEAT (Bitfield-Mask: 0x01) */ -#define ADC_CONTROL_POWER_SAVER_DIS_Pos (3UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bit 3) */ -#define ADC_CONTROL_POWER_SAVER_DIS_Msk (0x8UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bitfield-Mask: 0x01) */ -#define ADC_CONTROL_SOFT_RESET_Pos (4UL) /*!< ADC CONTROL: SOFT_RESET (Bit 4) */ -#define ADC_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< ADC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ -#define ADC_CONTROL_REPEAT_DONE_STAT_Pos (6UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bit 6) */ -#define ADC_CONTROL_REPEAT_DONE_STAT_Msk (0x40UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bitfield-Mask: 0x01) */ -#define ADC_CONTROL_SINGLE_DONE_STAT_Pos (7UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bit 7) */ -#define ADC_CONTROL_SINGLE_DONE_STAT_Msk (0x80UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bitfield-Mask: 0x01) */ - -/* ---------------------------------- ADC_DELAY --------------------------------- */ -#define ADC_DELAY_START_Pos (0UL) /*!< ADC DELAY: START (Bit 0) */ -#define ADC_DELAY_START_Msk (0xffffUL) /*!< ADC DELAY: START (Bitfield-Mask: 0xffff) */ -#define ADC_DELAY_REPEAT_Pos (16UL) /*!< ADC DELAY: REPEAT (Bit 16) */ -#define ADC_DELAY_REPEAT_Msk (0xffff0000UL) /*!< ADC DELAY: REPEAT (Bitfield-Mask: 0xffff) */ - -/* --------------------------------- ADC_STATUS --------------------------------- */ -#define ADC_STATUS_CH0_Pos (0UL) /*!< ADC STATUS: CH0 (Bit 0) */ -#define ADC_STATUS_CH0_Msk (0x1UL) /*!< ADC STATUS: CH0 (Bitfield-Mask: 0x01) */ -#define ADC_STATUS_CH1_Pos (1UL) /*!< ADC STATUS: CH1 (Bit 1) */ -#define ADC_STATUS_CH1_Msk (0x2UL) /*!< ADC STATUS: CH1 (Bitfield-Mask: 0x01) */ -#define ADC_STATUS_CH2_Pos (2UL) /*!< ADC STATUS: CH2 (Bit 2) */ -#define ADC_STATUS_CH2_Msk (0x4UL) /*!< ADC STATUS: CH2 (Bitfield-Mask: 0x01) */ -#define ADC_STATUS_CH3_Pos (3UL) /*!< ADC STATUS: CH3 (Bit 3) */ -#define ADC_STATUS_CH3_Msk (0x8UL) /*!< ADC STATUS: CH3 (Bitfield-Mask: 0x01) */ -#define ADC_STATUS_CH4_Pos (4UL) /*!< ADC STATUS: CH4 (Bit 4) */ -#define ADC_STATUS_CH4_Msk (0x10UL) /*!< ADC STATUS: CH4 (Bitfield-Mask: 0x01) */ - -/* -------------------------------- ADC_SINGLE_EN ------------------------------- */ -#define ADC_SINGLE_EN_CH0_Pos (0UL) /*!< ADC SINGLE_EN: CH0 (Bit 0) */ -#define ADC_SINGLE_EN_CH0_Msk (0x1UL) /*!< ADC SINGLE_EN: CH0 (Bitfield-Mask: 0x01) */ -#define ADC_SINGLE_EN_CH1_Pos (1UL) /*!< ADC SINGLE_EN: CH1 (Bit 1) */ -#define ADC_SINGLE_EN_CH1_Msk (0x2UL) /*!< ADC SINGLE_EN: CH1 (Bitfield-Mask: 0x01) */ -#define ADC_SINGLE_EN_CH2_Pos (2UL) /*!< ADC SINGLE_EN: CH2 (Bit 2) */ -#define ADC_SINGLE_EN_CH2_Msk (0x4UL) /*!< ADC SINGLE_EN: CH2 (Bitfield-Mask: 0x01) */ -#define ADC_SINGLE_EN_CH3_Pos (3UL) /*!< ADC SINGLE_EN: CH3 (Bit 3) */ -#define ADC_SINGLE_EN_CH3_Msk (0x8UL) /*!< ADC SINGLE_EN: CH3 (Bitfield-Mask: 0x01) */ -#define ADC_SINGLE_EN_CH4_Pos (4UL) /*!< ADC SINGLE_EN: CH4 (Bit 4) */ -#define ADC_SINGLE_EN_CH4_Msk (0x10UL) /*!< ADC SINGLE_EN: CH4 (Bitfield-Mask: 0x01) */ - -/* --------------------------------- ADC_REPEAT --------------------------------- */ -#define ADC_REPEAT_CH0_Pos (0UL) /*!< ADC REPEAT: CH0 (Bit 0) */ -#define ADC_REPEAT_CH0_Msk (0x1UL) /*!< ADC REPEAT: CH0 (Bitfield-Mask: 0x01) */ -#define ADC_REPEAT_CH1_Pos (1UL) /*!< ADC REPEAT: CH1 (Bit 1) */ -#define ADC_REPEAT_CH1_Msk (0x2UL) /*!< ADC REPEAT: CH1 (Bitfield-Mask: 0x01) */ -#define ADC_REPEAT_CH2_Pos (2UL) /*!< ADC REPEAT: CH2 (Bit 2) */ -#define ADC_REPEAT_CH2_Msk (0x4UL) /*!< ADC REPEAT: CH2 (Bitfield-Mask: 0x01) */ -#define ADC_REPEAT_CH3_Pos (3UL) /*!< ADC REPEAT: CH3 (Bit 3) */ -#define ADC_REPEAT_CH3_Msk (0x8UL) /*!< ADC REPEAT: CH3 (Bitfield-Mask: 0x01) */ -#define ADC_REPEAT_CH4_Pos (4UL) /*!< ADC REPEAT: CH4 (Bit 4) */ -#define ADC_REPEAT_CH4_Msk (0x10UL) /*!< ADC REPEAT: CH4 (Bitfield-Mask: 0x01) */ - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define PCR_BASE 0x40080100UL -#define VBAT_BASE 0x4000A400UL -#define LPC_BASE 0x400F3000UL -#define LPC_CONFIG_BASE 0x400F3300UL -#define GCR_BASE 0x400FFF00UL -#define EMI_BASE 0x400F0000UL -#define ACPI_EC0_BASE 0x400F0C00UL -#define ACPI_EC1_BASE 0x400F1000UL -#define KBC_BASE 0x400F0400UL -#define PORT92_BASE 0x400F1800UL -#define MBX_BASE 0x400F2400UL -#define PM1_BASE 0x400F1400UL -#define UART_BASE 0x400F1C00UL -#define INTR_BASE 0x4000C000UL -#define WDT_BASE 0x40000400UL -#define TIMER_16_0_BASE 0x40000C00UL -#define TIMER_16_1_BASE 0x40000C20UL -#define TIMER_16_2_BASE 0x40000C40UL -#define TIMER_16_3_BASE 0x40000C60UL -#define TIMER_32_0_BASE 0x40000C80UL -#define TIMER_32_1_BASE 0x40000CA0UL -#define HTM_BASE 0x40009800UL -#define RTC_BASE 0x400F2C00UL -#define GPIO_BASE 0x40081000UL -#define DMA_BASE 0x40002400UL -#define SMB0_BASE 0x40001800UL -#define SMB1_BASE 0x4000AC00UL -#define SMB2_BASE 0x4000B000UL -#define SMB3_BASE 0x4000B400UL -#define PECI_BASE 0x40006400UL -#define TACH_0_BASE 0x40006000UL -#define TACH_1_BASE 0x40006100UL -#define PWM_0_BASE 0x40005800UL -#define PWM_1_BASE 0x40005810UL -#define PWM_2_BASE 0x40005820UL -#define PWM_3_BASE 0x40005830UL -#define RPM_FAN_BASE 0x4000A000UL -#define SPI_0_BASE 0x40009400UL -#define SPI_1_BASE 0x40009480UL -#define LED_0_BASE 0x4000B800UL -#define LED_1_BASE 0x4000B900UL -#define LED_2_BASE 0x4000BA00UL -#define LED_3_BASE 0x4000BB00UL -#define PS2_0_BASE 0x40009000UL -#define PS2_1_BASE 0x40009040UL -#define PS2_2_BASE 0x40009080UL -#define PS2_3_BASE 0x400090C0UL -#define KEYSCAN_BASE 0x40009C00UL -#define BC_LINK_BASE 0x4000BC00UL -#define TFDP_BASE 0x40008C00UL -#define ADC_BASE 0x40007C00UL -#define EC_REG_BANK_BASE 0x4000FC00UL -#define JTAG_BASE 0x40080000UL -#define PKE_BASE 0x4000BD00UL -#define TRNG_BASE 0x4000BE00UL -#define HASH_BASE 0x4000D000UL -#define AES_BASE 0x4000D200UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define CEC1302_PCR ((PCR_Type *) PCR_BASE) -#define CEC1302_VBAT ((VBAT_Type *) VBAT_BASE) -#define CEC1302_LPC ((LPC_Type *) LPC_BASE) -#define CEC1302_LPC_CONFIG ((LPC_CONFIG_Type *) LPC_CONFIG_BASE) -#define CEC1302_GCR ((GCR_Type *) GCR_BASE) -#define CEC1302_EMI ((EMI_Type *) EMI_BASE) -#define CEC1302_ACPI_EC0 ((ACPI_EC0_Type *) ACPI_EC0_BASE) -#define CEC1302_ACPI_EC1 ((ACPI_EC0_Type *) ACPI_EC1_BASE) -#define CEC1302_KBC ((KBC_Type *) KBC_BASE) -#define CEC1302_PORT92 ((PORT92_Type *) PORT92_BASE) -#define CEC1302_MBX ((MBX_Type *) MBX_BASE) -#define CEC1302_PM1 ((PM1_Type *) PM1_BASE) -#define CEC1302_UART ((UART_Type *) UART_BASE) -#define CEC1302_INTR ((INTR_Type *) INTR_BASE) -#define CEC1302_WDT ((WDT_Type *) WDT_BASE) -#define CEC1302_TIMER_16_0 ((TIMER_16_0_Type *) TIMER_16_0_BASE) -#define CEC1302_TIMER_16_1 ((TIMER_16_0_Type *) TIMER_16_1_BASE) -#define CEC1302_TIMER_16_2 ((TIMER_16_0_Type *) TIMER_16_2_BASE) -#define CEC1302_TIMER_16_3 ((TIMER_16_0_Type *) TIMER_16_3_BASE) -#define CEC1302_TIMER_32_0 ((TIMER_16_0_Type *) TIMER_32_0_BASE) -#define CEC1302_TIMER_32_1 ((TIMER_16_0_Type *) TIMER_32_1_BASE) -#define CEC1302_HTM ((HTM_Type *) HTM_BASE) -#define CEC1302_RTC ((RTC_Type *) RTC_BASE) -#define CEC1302_GPIO ((GPIO_Type *) GPIO_BASE) -#define CEC1302_DMA ((DMA_Type *) DMA_BASE) -#define CEC1302_SMB0 ((SMB0_Type *) SMB0_BASE) -#define CEC1302_SMB1 ((SMB0_Type *) SMB1_BASE) -#define CEC1302_SMB2 ((SMB0_Type *) SMB2_BASE) -#define CEC1302_SMB3 ((SMB0_Type *) SMB3_BASE) -#define CEC1302_PECI ((PECI_Type *) PECI_BASE) -#define CEC1302_TACH_0 ((TACH_0_Type *) TACH_0_BASE) -#define CEC1302_TACH_1 ((TACH_0_Type *) TACH_1_BASE) -#define CEC1302_PWM_0 ((PWM_0_Type *) PWM_0_BASE) -#define CEC1302_PWM_1 ((PWM_0_Type *) PWM_1_BASE) -#define CEC1302_PWM_2 ((PWM_0_Type *) PWM_2_BASE) -#define CEC1302_PWM_3 ((PWM_0_Type *) PWM_3_BASE) -#define CEC1302_RPM_FAN ((RPM_FAN_Type *) RPM_FAN_BASE) -#define CEC1302_SPI_0 ((SPI_0_Type *) SPI_0_BASE) -#define CEC1302_SPI_1 ((SPI_0_Type *) SPI_1_BASE) -#define CEC1302_LED_0 ((LED_0_Type *) LED_0_BASE) -#define CEC1302_LED_1 ((LED_0_Type *) LED_1_BASE) -#define CEC1302_LED_2 ((LED_0_Type *) LED_2_BASE) -#define CEC1302_LED_3 ((LED_0_Type *) LED_3_BASE) -#define CEC1302_PS2_0 ((PS2_0_Type *) PS2_0_BASE) -#define CEC1302_PS2_1 ((PS2_0_Type *) PS2_1_BASE) -#define CEC1302_PS2_2 ((PS2_0_Type *) PS2_2_BASE) -#define CEC1302_PS2_3 ((PS2_0_Type *) PS2_3_BASE) -#define CEC1302_KEYSCAN ((KEYSCAN_Type *) KEYSCAN_BASE) -#define CEC1302_BC_LINK ((BC_LINK_Type *) BC_LINK_BASE) -#define CEC1302_TFDP ((TFDP_Type *) TFDP_BASE) -#define CEC1302_ADC ((ADC_Type *) ADC_BASE) -#define CEC1302_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE) -#define CEC1302_JTAG ((JTAG_Type *) JTAG_BASE) -#define CEC1302_PKE ((PKE_TypeDef *) PKE_BASE) -#define CEC1302_TRNG ((TRNG_TypeDef *) TRNG_BASE) -#define CEC1302_HASH ((HASH_TypeDef *) HASH_BASE) -#define CEC1302_AES ((AES_TypeDef *) AES_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group MCHP_CEC1302 */ -/** @} */ /* End of group Microchip Technology Inc. */ - -#ifdef __cplusplus -} -#endif - - -#endif /* MCHP_CEC1302_H */ - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/MEC1322.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/MEC1322.h deleted file mode 100644 index 91f3c8ead..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/MEC1322.h +++ /dev/null @@ -1,2862 +0,0 @@ -/******************************************************************************* -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -******************************************************************************** - -Version Control Information (Perforce) -$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $ -******************************************************************************** -$Revision: #1 $ -$DateTime: 2015/12/23 15:37:58 $ -$Author: akrishnan $ - Change Description: Initial revision for MEC1322 -******************************************************************************/ -/** @file smscmmcr.h -* brief the mmcr definitions -* -******************************************************************************/ -#ifndef SMSCMMCR_H_ -#define SMSCMMCR_H_ - -//NOTE: Please Don't edit this File, this is extrated from the Spread sheet -// : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv -typedef volatile unsigned char VUINT8; -typedef volatile unsigned short int VUINT16; -typedef volatile unsigned long int VUINT32; - -/*************************************************************** -* PWM -***************************************************************/ -#define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800 -#define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME)) - -#define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804 -#define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME)) - -#define ADDR_PWM_0_CONFIGURATION 0x40005808 -#define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION)) - -#define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810 -#define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME)) - -#define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814 -#define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME)) - -#define ADDR_PWM_1_CONFIGURATION 0x40005818 -#define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION)) - -#define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820 -#define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME)) - -#define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824 -#define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME)) - -#define ADDR_PWM_2_CONFIGURATION 0x40005828 -#define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION)) - -#define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830 -#define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME)) - -#define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834 -#define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME)) - -#define ADDR_PWM_3_CONFIGURATION 0x40005838 -#define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION)) - -/*************************************************************** -* PECI -***************************************************************/ -#define ADDR_PECI_WRITE_DATA 0x40006400 -#define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA)) - -#define ADDR_PECI_READ_DATA 0x40006404 -#define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA)) - -#define ADDR_PECI_CONTROL 0x40006408 -#define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL)) - -#define ADDR_PECI_STATUS_1 0x4000640C -#define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1)) - -#define ADDR_PECI_STATUS_2 0x40006410 -#define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2)) - -#define ADDR_PECI_ERROR 0x40006414 -#define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR)) - -#define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418 -#define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1)) - -#define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C -#define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2)) - -#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420 -#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE)) - -#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424 -#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE)) - -#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428 -#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE)) - -#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C -#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE)) - -#define ADDR_PECI_BLOCK_ID 0x40006440 -#define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID)) - -#define ADDR_PECI_BLOCK_REVISION 0x40006444 -#define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION)) - -/*************************************************************** -* ACPI EC Interface -***************************************************************/ -#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00 -#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0)) - -#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01 -#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1)) - -#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02 -#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2)) - -#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03 -#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3)) - -#define ADDR_ACPI_0_STATUS_EC 0x400F0D04 -#define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC)) - -#define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05 -#define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC)) - -#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08 -#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0)) - -#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08 -#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0)) - -#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09 -#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1)) - -#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A -#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2)) - -#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B -#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3)) - -#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100 -#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0)) - -#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101 -#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1)) - -#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102 -#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2)) - -#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103 -#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3)) - -#define ADDR_ACPI_1_STATUS_EC 0x400F1104 -#define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC)) - -#define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105 -#define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC)) - -#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108 -#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0)) - -#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108 -#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0)) - -#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109 -#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1)) - -#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A -#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2)) - -#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B -#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3)) - -/*************************************************************** -* Keyboard Matrix Scan Support -***************************************************************/ -#define ADDR_KEYBOARD_KSO_SELECT 0x40009C04 -#define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT)) - -#define ADDR_KEYBOARD_KSI_INPUT 0x40009C08 -#define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT)) - -#define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C -#define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS)) - -#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10 -#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE)) - -#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14 -#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL)) - -/*************************************************************** -* PS/2 Device Interface -***************************************************************/ -#define ADDR_PS2_3_STATUS 0x400090C8 -#define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS)) - -#define ADDR_PS2_3_CONTROL 0x400090C4 -#define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL)) - -#define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0 -#define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER)) - -#define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0 -#define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER)) - -#define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000 -#define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER)) - -#define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000 -#define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER)) - -#define ADDR_PS2_0_CONTROL 0x40009004 -#define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL)) - -#define ADDR_PS2_0_STATUS 0x40009008 -#define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS)) - -#define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040 -#define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER)) - -#define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040 -#define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER)) - -#define ADDR_PS2_1_CONTROL 0x40009044 -#define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL)) - -#define ADDR_PS2_1_STATUS 0x40009048 -#define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS)) - -#define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080 -#define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER)) - -#define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080 -#define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER)) - -#define ADDR_PS2_2_CONTROL 0x40009084 -#define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL)) - -#define ADDR_PS2_2_STATUS 0x40009088 -#define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS)) - -/*************************************************************** -* 8042 Host Interface -***************************************************************/ -#define ADDR_8042_ACTIVATE 0x400F0730 -#define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE)) - -#define ADDR_8042_HOST_EC_DATACMD 0x400F0500 -#define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD)) - -#define ADDR_8042_EC_HOST_DATA 0x400F0500 -#define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA)) - -#define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504 -#define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ)) - -#define ADDR_8042_KEYBOARD_CONTROL 0x400F0508 -#define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL)) - -#define ADDR_8042_EC_HOST_AUX 0x400F050C -#define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX)) - -#define ADDR_8042_PCOBF 0x400F0514 -#define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF)) - -#define ADDR_8042_PORT92_ENABLE 0x400F1B30 -#define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE)) - -#define ADDR_8042_GATEA20_CONTROL 0x400F1900 -#define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL)) - -#define ADDR_8042_SETGA20L 0x400F1908 -#define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L)) - -#define ADDR_8042_RSTGA20L 0x400F190C -#define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L)) - -/*************************************************************** -* SMBus -***************************************************************/ -#define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C -#define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB)) - -#define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458 -#define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C)) - -#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454 -#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER)) - -#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450 -#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER)) - -#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C -#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER)) - -#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448 -#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER)) - -#define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444 -#define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING)) - -#define ADDR_SMB_3_DATA_TIMING 0x4000B440 -#define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING)) - -#define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C -#define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC)) - -#define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438 -#define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL)) - -#define ADDR_SMB_3_REVISION 0x4000B434 -#define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION)) - -#define ADDR_SMB_3_BLOCK_ID 0x4000B430 -#define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID)) - -#define ADDR_SMB_3_BUS_CLOCK 0x4000B42C -#define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK)) - -#define ADDR_SMB_3_CONFIGURATION 0x4000B428 -#define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION)) - -#define ADDR_SMB_3_IDLE_SCALING 0x4000B424 -#define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING)) - -#define ADDR_SMB_3_COMPLETION 0x4000B420 -#define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION)) - -#define ADDR_SMB_3_DATA_TIMING2 0x4000B418 -#define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2)) - -#define ADDR_SMB_3_PEC 0x4000B414 -#define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC)) - -#define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410 -#define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND)) - -#define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C -#define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND)) - -#define ADDR_SMB_3_DATA 0x4000B408 -#define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA)) - -#define ADDR_SMB_3_OWN_ADDRESS 0x4000B404 -#define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS)) - -#define ADDR_SMB_3_STATUS 0x4000B400 -#define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS)) - -#define ADDR_SMB_3_CONTROL 0x4000B400 -#define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL)) - -#define ADDR_SMB_2_CONTROL 0x4000B000 -#define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL)) - -#define ADDR_SMB_2_STATUS 0x4000B000 -#define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS)) - -#define ADDR_SMB_2_OWN_ADDRESS 0x4000B004 -#define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS)) - -#define ADDR_SMB_2_DATA 0x4000B008 -#define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA)) - -#define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C -#define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND)) - -#define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010 -#define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND)) - -#define ADDR_SMB_2_PEC 0x4000B014 -#define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC)) - -#define ADDR_SMB_2_DATA_TIMING2 0x4000B018 -#define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2)) - -#define ADDR_SMB_2_COMPLETION 0x4000B020 -#define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION)) - -#define ADDR_SMB_2_IDLE_SCALING 0x4000B024 -#define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING)) - -#define ADDR_SMB_2_CONFIGURATION 0x4000B028 -#define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION)) - -#define ADDR_SMB_2_BUS_CLOCK 0x4000B02C -#define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK)) - -#define ADDR_SMB_2_BLOCK_ID 0x4000B030 -#define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID)) - -#define ADDR_SMB_2_REVISION 0x4000B034 -#define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION)) - -#define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038 -#define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL)) - -#define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C -#define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC)) - -#define ADDR_SMB_2_DATA_TIMING 0x4000B040 -#define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING)) - -#define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044 -#define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING)) - -#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048 -#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER)) - -#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C -#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER)) - -#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050 -#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER)) - -#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054 -#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER)) - -#define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058 -#define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C)) - -#define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C -#define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB)) - -#define ADDR_SMB_1_CONTROL 0x4000AC00 -#define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL)) - -#define ADDR_SMB_1_STATUS 0x4000AC00 -#define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS)) - -#define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04 -#define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS)) - -#define ADDR_SMB_1_DATA 0x4000AC08 -#define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA)) - -#define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C -#define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND)) - -#define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10 -#define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND)) - -#define ADDR_SMB_1_PEC 0x4000AC14 -#define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC)) - -#define ADDR_SMB_1_DATA_TIMING2 0x4000AC18 -#define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2)) - -#define ADDR_SMB_1_COMPLETION 0x4000AC20 -#define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION)) - -#define ADDR_SMB_1_IDLE_SCALING 0x4000AC24 -#define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING)) - -#define ADDR_SMB_1_CONFIGURATION 0x4000AC28 -#define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION)) - -#define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C -#define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK)) - -#define ADDR_SMB_1_BLOCK_ID 0x4000AC30 -#define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID)) - -#define ADDR_SMB_1_REVISION 0x4000AC34 -#define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION)) - -#define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38 -#define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL)) - -#define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C -#define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC)) - -#define ADDR_SMB_1_DATA_TIMING 0x4000AC40 -#define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING)) - -#define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44 -#define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING)) - -#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48 -#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER)) - -#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C -#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER)) - -#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50 -#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER)) - -#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54 -#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER)) - -#define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58 -#define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C)) - -#define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C -#define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB)) - -#define ADDR_SMB_0_STATUS 0x40001800 -#define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS)) - -#define ADDR_SMB_0_CONTROL 0x40001800 -#define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL)) - -#define ADDR_SMB_0_OWN_ADDRESS 0x40001804 -#define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS)) - -#define ADDR_SMB_0_DATA 0x40001808 -#define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA)) - -#define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C -#define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND)) - -#define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810 -#define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND)) - -#define ADDR_SMB_0_PEC 0x40001814 -#define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC)) - -#define ADDR_SMB_0_DATA_TIMING2 0x40001818 -#define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2)) - -#define ADDR_SMB_0_COMPLETION 0x40001820 -#define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION)) - -#define ADDR_SMB_0_IDLE_SCALING 0x40001824 -#define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING)) - -#define ADDR_SMB_0_CONFIGURATION 0x40001828 -#define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION)) - -#define ADDR_SMB_0_BUS_CLOCK 0x4000182C -#define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK)) - -#define ADDR_SMB_0_BLOCK_ID 0x40001830 -#define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID)) - -#define ADDR_SMB_0_REVISION 0x40001834 -#define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION)) - -#define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838 -#define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL)) - -#define ADDR_SMB_0_CLOCK_SYNC 0x4000183C -#define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC)) - -#define ADDR_SMB_0_DATA_TIMING 0x40001840 -#define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING)) - -#define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844 -#define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING)) - -#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848 -#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER)) - -#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C -#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER)) - -#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850 -#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER)) - -#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854 -#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER)) - -#define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858 -#define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C)) - -#define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C -#define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB)) - -/*************************************************************** -* Watchdog Timer Interface -***************************************************************/ -#define ADDR_WATCHDOG_WDT_LOAD 0x40000400 -#define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD)) - -#define ADDR_WATCHDOG_WDT_CONTROL 0x40000404 -#define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL)) - -#define ADDR_WATCHDOG_WDT_KICK 0x40000408 -#define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK)) - -#define ADDR_WATCHDOG_WDT_COUNT 0x4000040C -#define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT)) - -/*************************************************************** -* ACPI PM1 -***************************************************************/ -#define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500 -#define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1)) - -#define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501 -#define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2)) - -#define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502 -#define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1)) - -#define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503 -#define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2)) - -#define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504 -#define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1)) - -#define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505 -#define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2)) - -#define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506 -#define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1)) - -#define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507 -#define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2)) - -#define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510 -#define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS)) - -/*************************************************************** -* EC GP-SPI -***************************************************************/ -#define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498 -#define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR)) - -#define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494 -#define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL)) - -#define ADDR_EC_1_SPI_RX_DATA 0x40009490 -#define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA)) - -#define ADDR_EC_1_SPI_TX_DATA 0x4000948C -#define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA)) - -#define ADDR_EC_1_SPI_STATUS 0x40009488 -#define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS)) - -#define ADDR_EC_1_SPI_CONTROL 0x40009484 -#define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL)) - -#define ADDR_EC_1_SPI_ENABLE 0x40009480 -#define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE)) - -#define ADDR_EC_0_SPI_ENABLE 0x40009400 -#define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE)) - -#define ADDR_EC_0_SPI_CONTROL 0x40009404 -#define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL)) - -#define ADDR_EC_0_SPI_STATUS 0x40009408 -#define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS)) - -#define ADDR_EC_0_SPI_TX_DATA 0x4000940C -#define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA)) - -#define ADDR_EC_0_SPI_RX_DATA 0x40009410 -#define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA)) - -#define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414 -#define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL)) - -#define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418 -#define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR)) - -/*************************************************************** -* Mailbox Registers Interface -***************************************************************/ -#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500 -#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX)) - -#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504 -#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX)) - -#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508 -#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE)) - -#define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C -#define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK)) - -#define ADDR_MAILBOX_3_0 0x400F2510 -#define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0)) - -#define ADDR_MAILBOX_7_4 0x400F2514 -#define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4)) - -#define ADDR_MAILBOX_BH_8 0x400F2518 -#define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8)) - -#define ADDR_MAILBOX_FH_CH 0x400F251C -#define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH)) - -#define ADDR_MAILBOX_13H_10H 0x400F2520 -#define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H)) - -#define ADDR_MAILBOX_17H_14H 0x400F2524 -#define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H)) - -#define ADDR_MAILBOX_1BH_18H 0x400F2528 -#define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H)) - -#define ADDR_MAILBOX_1FH_1CH 0x400F252C -#define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH)) - -/*************************************************************** -* Hibernation Timer -***************************************************************/ -#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800 -#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD)) - -#define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804 -#define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL)) - -#define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808 -#define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT)) - -/*************************************************************** -* UART -***************************************************************/ -#define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30 -#define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE)) - -#define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0 -#define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT)) - -#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00 -#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB)) - -#define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00 -#define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER)) - -#define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00 -#define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER)) - -#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01 -#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB)) - -#define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01 -#define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE)) - -#define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02 -#define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL)) - -#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02 -#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION)) - -#define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03 -#define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL)) - -#define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04 -#define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL)) - -#define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05 -#define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS)) - -#define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06 -#define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS)) - -#define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07 -#define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD)) - -/*************************************************************** -* TACH -***************************************************************/ -#define ADDR_TACH_0_CONTROL 0x40006000 -#define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL)) - -#define ADDR_TACH_0_STATUS 0x40006004 -#define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS)) - -#define ADDR_TACH_0_HIGH_LIMIT 0x40006008 -#define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT)) - -#define ADDR_TACH_0_LOW_LIMIT 0x4000600C -#define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT)) - -#define ADDR_TACH_1_CONTROL 0x40006010 -#define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL)) - -#define ADDR_TACH_1_STATUS 0x40006014 -#define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS)) - -#define ADDR_TACH_1_HIGH_LIMIT 0x40006018 -#define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT)) - -#define ADDR_TACH_1_LOW_LIMIT 0x4000601C -#define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT)) - -/*************************************************************** -* Global Config Regs Basic -***************************************************************/ -#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07 -#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER)) - -#define ADDR_GLOBAL_DEVICE_ID 0x400FFF20 -#define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID)) - -#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21 -#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED)) - -#define ADDR_GLOBAL_GCR_BUILD 0x400FFF28 -#define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD)) - -#define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C -#define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH)) - -/*************************************************************** -* Trace FIFO Debug Port -***************************************************************/ -#define ADDR_TRACE_DATA 0x40008C00 -#define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA)) - -#define ADDR_TRACE_CONTROL 0x40008C04 -#define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL)) - -/*************************************************************** -* STAP -***************************************************************/ -#define ADDR_STAP_MESSAGE_OBF 0x40080000 -#define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF)) - -#define ADDR_STAP_MESSAGE_IBF 0x40080004 -#define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF)) - -#define ADDR_STAP_OBF_STATUS 0x40080008 -#define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS)) - -#define ADDR_STAP_IBF_STATUS 0x40080009 -#define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS)) - -#define ADDR_STAP_DBG_CTRL 0x4008000C -#define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL)) - -/*************************************************************** -* EMI -***************************************************************/ -#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100 -#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX)) - -#define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101 -#define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX)) - -#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104 -#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0)) - -#define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108 -#define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0)) - -#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A -#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0)) - -#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C -#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1)) - -#define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110 -#define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1)) - -#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112 -#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1)) - -#define ADDR_IMAP_INTERRUPT_SET 0x400F0114 -#define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET)) - -#define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116 -#define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE)) - -/*************************************************************** -* Blinking/Breathing PWM -***************************************************************/ -#define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10 -#define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL)) - -#define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C -#define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE)) - -#define ADDR_LED_3_DELAY 0x4000BB08 -#define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY)) - -#define ADDR_LED_3_LIMITS 0x4000BB04 -#define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS)) - -#define ADDR_LED_3_CONFIGURATION 0x4000BB00 -#define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION)) - -#define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10 -#define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL)) - -#define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C -#define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE)) - -#define ADDR_LED_2_DELAY 0x4000BA08 -#define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY)) - -#define ADDR_LED_2_LIMITS 0x4000BA04 -#define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS)) - -#define ADDR_LED_2_CONFIGURATION 0x4000BA00 -#define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION)) - -#define ADDR_LED_1_CONFIGURATION 0x4000B900 -#define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION)) - -#define ADDR_LED_1_LIMITS 0x4000B904 -#define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS)) - -#define ADDR_LED_1_DELAY 0x4000B908 -#define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY)) - -#define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C -#define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE)) - -#define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910 -#define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL)) - -#define ADDR_LED_0_CONFIGURATION 0x4000B800 -#define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION)) - -#define ADDR_LED_0_LIMITS 0x4000B804 -#define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS)) - -#define ADDR_LED_0_DELAY 0x4000B808 -#define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY)) - -#define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C -#define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE)) - -#define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810 -#define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL)) - -/*************************************************************** -* SMSC BC-Link Master -***************************************************************/ -#define ADDR_BC_LINK_STATUS 0x4000BC00 -#define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS)) - -#define ADDR_BC_LINK_ADDRESS 0x4000BC04 -#define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS)) - -#define ADDR_BC_LINK_DATA 0x4000BC08 -#define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA)) - -#define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C -#define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT)) - -/*************************************************************** -* Basic Timer -***************************************************************/ -#define ADDR_BASIC_0_TIMER_COUNT 0x40000C00 -#define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT)) - -#define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04 -#define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD)) - -#define ADDR_BASIC_0_TIMER_STATUS 0x40000C08 -#define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS)) - -#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C -#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE)) - -#define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10 -#define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL)) - -#define ADDR_BASIC_1_TIMER_COUNT 0x40000C20 -#define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT)) - -#define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24 -#define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD)) - -#define ADDR_BASIC_1_TIMER_STATUS 0x40000C28 -#define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS)) - -#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C -#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE)) - -#define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30 -#define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL)) - -#define ADDR_BASIC_2_TIMER_COUNT 0x40000C40 -#define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT)) - -#define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44 -#define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD)) - -#define ADDR_BASIC_2_TIMER_STATUS 0x40000C48 -#define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS)) - -#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C -#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE)) - -#define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50 -#define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL)) - -#define ADDR_BASIC_3_TIMER_COUNT 0x40000C60 -#define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT)) - -#define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64 -#define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD)) - -#define ADDR_BASIC_3_TIMER_STATUS 0x40000C68 -#define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS)) - -#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C -#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE)) - -#define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70 -#define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL)) - -#define ADDR_BASIC_4_TIMER_COUNT 0x40000C80 -#define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT)) - -#define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84 -#define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD)) - -#define ADDR_BASIC_4_TIMER_STATUS 0x40000C88 -#define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS)) - -#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C -#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE)) - -#define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90 -#define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL)) - -#define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0 -#define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT)) - -#define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4 -#define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD)) - -#define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8 -#define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS)) - -#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC -#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE)) - -#define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0 -#define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL)) - -/*************************************************************** -* INTS -***************************************************************/ -#define ADDR_EC_GIRQ8_SOURCE 0x4000C000 -#define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE)) - -#define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004 -#define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET)) - -#define ADDR_EC_GIRQ8_RESULT 0x4000C008 -#define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT)) - -#define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C -#define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ9_SOURCE 0x4000C014 -#define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE)) - -#define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018 -#define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET)) - -#define ADDR_EC_GIRQ9_RESULT 0x4000C01C -#define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT)) - -#define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020 -#define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ10_SOURCE 0x4000C028 -#define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE)) - -#define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C -#define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET)) - -#define ADDR_EC_GIRQ10_RESULT 0x4000C030 -#define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT)) - -#define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034 -#define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ11_SOURCE 0x4000C03C -#define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE)) - -#define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040 -#define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET)) - -#define ADDR_EC_GIRQ11_RESULT 0x4000C044 -#define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT)) - -#define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048 -#define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ12_SOURCE 0x4000C050 -#define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE)) - -#define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054 -#define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET)) - -#define ADDR_EC_GIRQ12_RESULT 0x4000C058 -#define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT)) - -#define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C -#define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ13_SOURCE 0x4000C064 -#define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE)) - -#define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068 -#define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET)) - -#define ADDR_EC_GIRQ13_RESULT 0x4000C06C -#define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT)) - -#define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070 -#define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ14_SOURCE 0x4000C078 -#define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE)) - -#define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C -#define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET)) - -#define ADDR_EC_GIRQ14_RESULT 0x4000C080 -#define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT)) - -#define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084 -#define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ15_SOURCE 0x4000C08C -#define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE)) - -#define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090 -#define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET)) - -#define ADDR_EC_GIRQ15_RESULT 0x4000C094 -#define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT)) - -#define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098 -#define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0 -#define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE)) - -#define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4 -#define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET)) - -#define ADDR_EC_GIRQ16_RESULT 0x4000C0A8 -#define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT)) - -#define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC -#define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4 -#define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE)) - -#define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8 -#define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET)) - -#define ADDR_EC_GIRQ17_RESULT 0x4000C0BC -#define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT)) - -#define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0 -#define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8 -#define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE)) - -#define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC -#define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET)) - -#define ADDR_EC_GIRQ18_RESULT 0x4000C0D0 -#define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT)) - -#define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4 -#define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC -#define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE)) - -#define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0 -#define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET)) - -#define ADDR_EC_GIRQ19_RESULT 0x4000C0E4 -#define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT)) - -#define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8 -#define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0 -#define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE)) - -#define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4 -#define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET)) - -#define ADDR_EC_GIRQ20_RESULT 0x4000C0F8 -#define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT)) - -#define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC -#define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ21_SOURCE 0x4000C104 -#define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE)) - -#define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108 -#define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET)) - -#define ADDR_EC_GIRQ21_RESULT 0x4000C10C -#define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT)) - -#define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110 -#define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ22_SOURCE 0x4000C118 -#define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE)) - -#define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C -#define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET)) - -#define ADDR_EC_GIRQ22_RESULT 0x4000C120 -#define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT)) - -#define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124 -#define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR)) - -#define ADDR_EC_GIRQ23_SOURCE 0x4000C12C -#define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE)) - -#define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130 -#define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET)) - -#define ADDR_EC_GIRQ23_RESULT 0x4000C134 -#define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT)) - -#define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138 -#define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR)) - -#define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200 -#define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET)) - -#define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204 -#define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR)) - -#define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208 -#define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR)) - -/*************************************************************** -* RPM Fan Control -***************************************************************/ -#define ADDR_RPM_FAN_SETTING 0x4000A000 -#define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING)) - -#define ADDR_RPM_PWM_DIVIDE 0x4000A001 -#define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE)) - -#define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002 -#define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1)) - -#define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003 -#define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2)) - -#define ADDR_RPM_GAIN 0x4000A005 -#define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN)) - -#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006 -#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION)) - -#define ADDR_RPM_FAN_STEP 0x4000A007 -#define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP)) - -#define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008 -#define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE)) - -#define ADDR_RPM_VALID_TACH_COUNT 0x4000A009 -#define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT)) - -#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A -#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE)) - -#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B -#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE)) - -#define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C -#define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE)) - -#define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D -#define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE)) - -#define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E -#define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE)) - -#define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F -#define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE)) - -#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010 -#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY)) - -#define ADDR_RPM_FAN_STATUS 0x4000A011 -#define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS)) - -#define ADDR_RPM_FAN_TEST 0x4000A014 -#define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST)) - -#define ADDR_RPM_FAN_TEST1 0x4000A015 -#define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1)) - -#define ADDR_RPM_FAN_TEST2 0x4000A016 -#define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2)) - -#define ADDR_RPM_FAN_TEST3 0x4000A017 -#define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3)) - -/*************************************************************** -* V2P (HP ckt#1) 32bit_aligned -***************************************************************/ -#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80 -#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY)) - -#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84 -#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW)) - -#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88 -#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH)) - -#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C -#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA)) - -#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90 -#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS)) - -#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94 -#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1)) - -#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98 -#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2)) - -#define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C -#define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL)) - -#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0 -#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY)) - -#define ADDR_V2P_TEST 0x40007CA4 -#define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST)) - -#define ADDR_V2P_NOTICE_DATA 0x40007CA8 -#define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA)) - -#define ADDR_V2P_TEST_DATA 0x40007CAC -#define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA)) - -#define ADDR_V2P_COUNTER_START 0x40007CB0 -#define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START)) - -#define ADDR_V2P_HYSTERESIS 0x40007CB4 -#define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS)) - -#define ADDR_V2P_BIAS 0x40007CB8 -#define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS)) - -#define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC -#define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL)) - -/*************************************************************** -* VBAT_REGS (1322) -***************************************************************/ -#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400 -#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS)) - -#define ADDR_VBAT_CONTROL 0x4000A404 -#define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL)) - -#define ADDR_VBAT_CLOCK_ENABLE 0x4000A408 -#define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE)) - -/*************************************************************** -* EC_REG_BANK (1322) -***************************************************************/ -#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04 -#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS)) - -#define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08 -#define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0)) - -#define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C -#define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1)) - -#define ADDR_EC_REG_BANK_ID 0x4000FC10 -#define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID)) - -#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14 -#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL)) - -#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18 -#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL)) - -#define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C -#define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE)) - -#define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20 -#define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE)) - -#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24 -#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK)) - -#define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28 -#define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT)) - -#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C -#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL)) - -#define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30 -#define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM)) - -#define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34 -#define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM)) - -#define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38 -#define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD)) - -#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C -#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST)) - -#define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40 -#define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM)) - -/*************************************************************** -* PCR -***************************************************************/ -#define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100 -#define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE)) - -#define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104 -#define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED)) - -#define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108 -#define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES)) - -#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C -#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS)) - -#define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110 -#define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES)) - -#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114 -#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS)) - -#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118 -#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0)) - -#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 -#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) - -#define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124 -#define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2)) - -#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128 -#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS)) - -#define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C -#define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL)) - -#define ADDR_PCR_OSCILLATOR_ID 0x40080130 -#define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID)) - -#define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138 -#define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE)) - -#define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C -#define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE)) - -#define ADDR_PCR_EC_RESET_ENABLE 0x40080140 -#define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE)) - -#define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144 -#define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2)) - -#define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148 -#define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL)) - -/*************************************************************** -* Public Key Crypto Engine -***************************************************************/ -#define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00 -#define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG)) - -#define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04 -#define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG)) - -#define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08 -#define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG)) - -#define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C -#define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG)) - -#define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10 -#define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG)) - -#define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14 -#define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG)) - -/*************************************************************** -* Non Deterministic Random Number Generator -***************************************************************/ -#define ADDR_NON_CONTROLREG 0x4000BE00 -#define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG)) - -#define ADDR_NON_FIFOLEVELREG 0x4000BE04 -#define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG)) - -#define ADDR_NON_VERSIONREG 0x4000BE08 -#define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG)) - -/*************************************************************** -* RTC -***************************************************************/ -#define ADDR_RTC_SECONDS 0x400F2800 -#define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS)) - -#define ADDR_RTC_SECONDS_ALARM 0x400F2801 -#define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM)) - -#define ADDR_RTC_MINUTES 0x400F2802 -#define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES)) - -#define ADDR_RTC_MINUTES_ALARM 0x400F2803 -#define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM)) - -#define ADDR_RTC_HOURS 0x400F2804 -#define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS)) - -#define ADDR_RTC_HOURS_ALARM 0x400F2805 -#define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM)) - -#define ADDR_RTC_DAY_OF_WEEK 0x400F2806 -#define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK)) - -#define ADDR_RTC_DAY_OF_MONTH 0x400F2807 -#define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH)) - -#define ADDR_RTC_MONTH 0x400F2808 -#define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH)) - -#define ADDR_RTC_YEAR 0x400F2809 -#define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR)) - -#define ADDR_RTC_A 0x400F280A -#define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A)) - -#define ADDR_RTC_B 0x400F280B -#define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B)) - -#define ADDR_RTC_C 0x400F280C -#define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C)) - -#define ADDR_RTC_D 0x400F280D -#define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D)) - -#define ADDR_RTC_CONTROL 0x400F2810 -#define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL)) - -#define ADDR_RTC_WEEK_ALARM 0x400F2814 -#define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM)) - -#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818 -#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD)) - -#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C -#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD)) - -#define ADDR_RTC_TEST_MODE 0x400F2820 -#define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE)) - -/*************************************************************** -* Analog to Digital Converter (ADC) -***************************************************************/ -#define ADDR_ADC_CONTROL 0x40007C00 -#define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL)) - -#define ADDR_ADC_DELAY 0x40007C04 -#define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY)) - -#define ADDR_ADC_STATUS 0x40007C08 -#define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS)) - -#define ADDR_ADC_SINGLE 0x40007C0C -#define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE)) - -#define ADDR_ADC_REPEAT 0x40007C10 -#define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT)) - -#define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14 -#define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS)) - -#define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18 -#define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS)) - -#define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C -#define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS)) - -#define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20 -#define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS)) - -#define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24 -#define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS)) - -#define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54 -#define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE)) - -#define ADDR_ADC_TEST 0x40007C78 -#define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST)) - -#define ADDR_ADC_CONFIGURATION 0x40007C7C -#define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION)) - -/*************************************************************** -* eFUSE -***************************************************************/ -#define ADDR_EFUSE_CONTROL 0x40082000 -#define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL)) - -#define ADDR_EFUSE_MANUAL_CONTROL 0x40082004 -#define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL)) - -#define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006 -#define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS)) - -#define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C -#define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA)) - -/*************************************************************** -* AES Crypto Engine & Hash Function -***************************************************************/ -#define ADDR_AES_CONFIGREG 0x4000D200 -#define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG)) - -#define ADDR_AES_COMMANDREG 0x4000D204 -#define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG)) - -#define ADDR_AES_CONTROLREG 0x4000D208 -#define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG)) - -#define ADDR_AES_STATUSREG 0x4000D20C -#define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG)) - -#define ADDR_AES_VERSIONREG 0x4000D210 -#define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG)) - -#define ADDR_AES_NBHEADERREG 0x4000D214 -#define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG)) - -#define ADDR_AES_LASTHEADERREG 0x4000D218 -#define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG)) - -#define ADDR_AES_NBBLOCKREG 0x4000D21C -#define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG)) - -#define ADDR_AES_LASTBLOCKREG 0x4000D220 -#define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG)) - -#define ADDR_AES_DMAINREG 0x4000D224 -#define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG)) - -#define ADDR_AES_DMAOUTREG 0x4000D228 -#define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG)) - -#define ADDR_AES_SHAMODE_REGISTER 0x4000D000 -#define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER)) - -#define ADDR_AES_NBBLOCK_REGISTER 0x4000D004 -#define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER)) - -#define ADDR_AES_CONTROL 0x4000D008 -#define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL)) - -#define ADDR_AES_STATUS 0x4000D00C -#define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS)) - -#define ADDR_AES_VERSION 0x4000D010 -#define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION)) - -#define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014 -#define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER)) - -#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018 -#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS)) - -#define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C -#define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS)) - -#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020 -#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS)) - -/*************************************************************** -* LPC -***************************************************************/ -#define ADDR_LPC_ACTIVATE 0x400F3330 -#define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE)) - -#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340 -#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341 -#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342 -#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343 -#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344 -#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345 -#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346 -#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347 -#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348 -#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349 -#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A -#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B -#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C -#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D -#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E -#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F -#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION)) - -#define ADDR_LPC_INTERFACE_BAR 0x400F3360 -#define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR)) - -#define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364 -#define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR)) - -#define ADDR_LPC_UART_0_BAR 0x400F3368 -#define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR)) - -#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378 -#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR)) - -#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388 -#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR)) - -#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C -#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR)) - -#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390 -#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR)) - -#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394 -#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR)) - -#define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398 -#define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR)) - -#define ADDR_LPC_BUS_MONITOR 0x400F3104 -#define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR)) - -#define ADDR_LPC_HOST_BUS_ERROR 0x400F3108 -#define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR)) - -#define ADDR_LPC_EC_SERIRQ 0x400F310C -#define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ)) - -#define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110 -#define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL)) - -#define ADDR_LPC_BAR_INHIBIT 0x400F3120 -#define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT)) - -#define ADDR_LPC_BAR_INIT 0x400F3130 -#define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT)) - -#define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC -#define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION)) - -/*************************************************************** -* GPIO -***************************************************************/ -#define ADDR_GPIO000_PIN_CONTROL 0x40081000 -#define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL)) - -#define ADDR_GPIO001_PIN_CONTROL 0x40081004 -#define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL)) - -#define ADDR_GPIO002_PIN_CONTROL 0x40081008 -#define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL)) - -#define ADDR_GPIO003_PIN_CONTROL 0x4008100C -#define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL)) - -#define ADDR_GPIO004_PIN_CONTROL 0x40081010 -#define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL)) - -#define ADDR_GPIO005_PIN_CONTROL 0x40081014 -#define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL)) - -#define ADDR_GPIO006_PIN_CONTROL 0x40081018 -#define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL)) - -#define ADDR_GPIO007_PIN_CONTROL 0x4008101C -#define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL)) - -#define ADDR_GPIO010_PIN_CONTROL 0x40081020 -#define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL)) - -#define ADDR_GPIO011_PIN_CONTROL 0x40081024 -#define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL)) - -#define ADDR_GPIO012_PIN_CONTROL 0x40081028 -#define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL)) - -#define ADDR_GPIO013_PIN_CONTROL 0x4008102C -#define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL)) - -#define ADDR_GPIO014_PIN_CONTROL 0x40081030 -#define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL)) - -#define ADDR_GPIO015_PIN_CONTROL 0x40081034 -#define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL)) - -#define ADDR_GPIO016_PIN_CONTROL 0x40081038 -#define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL)) - -#define ADDR_GPIO017_PIN_CONTROL 0x4008103C -#define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL)) - -#define ADDR_GPIO020_PIN_CONTROL 0x40081040 -#define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL)) - -#define ADDR_GPIO021_PIN_CONTROL 0x40081044 -#define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL)) - -#define ADDR_GPIO022_PIN_CONTROL 0x40081048 -#define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL)) - -#define ADDR_GPIO023_PIN_CONTROL 0x4008104C -#define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL)) - -#define ADDR_GPIO024_PIN_CONTROL 0x40081050 -#define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL)) - -#define ADDR_GPIO025_PIN_CONTROL 0x40081054 -#define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL)) - -#define ADDR_GPIO026_PIN_CONTROL 0x40081058 -#define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL)) - -#define ADDR_GPIO027_PIN_CONTROL 0x4008105C -#define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL)) - -#define ADDR_GPIO030_PIN_CONTROL 0x40081060 -#define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL)) - -#define ADDR_GPIO031_PIN_CONTROL 0x40081064 -#define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL)) - -#define ADDR_GPIO032_PIN_CONTROL 0x40081068 -#define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL)) - -#define ADDR_GPIO033_PIN_CONTROL 0x4008106C -#define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL)) - -#define ADDR_GPIO034_PIN_CONTROL 0x40081070 -#define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL)) - -#define ADDR_GPIO035_PIN_CONTROL 0x40081074 -#define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL)) - -#define ADDR_GPIO036_PIN_CONTROL 0x40081078 -#define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL)) - -#define ADDR_GPIO040_PIN_CONTROL 0x40081080 -#define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL)) - -#define ADDR_GPIO041_PIN_CONTROL 0x40081084 -#define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL)) - -#define ADDR_GPIO042_PIN_CONTROL 0x40081088 -#define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL)) - -#define ADDR_GPIO043_PIN_CONTROL 0x4008108C -#define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL)) - -#define ADDR_GPIO044_PIN_CONTROL 0x40081090 -#define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL)) - -#define ADDR_GPIO045_PIN_CONTROL 0x40081094 -#define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL)) - -#define ADDR_GPIO046_PIN_CONTROL 0x40081098 -#define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL)) - -#define ADDR_GPIO047_PIN_CONTROL 0x4008109C -#define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL)) - -#define ADDR_GPIO050_PIN_CONTROL 0x400810A0 -#define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL)) - -#define ADDR_GPIO051_PIN_CONTROL 0x400810A4 -#define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL)) - -#define ADDR_GPIO052_PIN_CONTROL 0x400810A8 -#define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL)) - -#define ADDR_GPIO053_PIN_CONTROL 0x400810AC -#define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL)) - -#define ADDR_GPIO054_PIN_CONTROL 0x400810B0 -#define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL)) - -#define ADDR_GPIO055_PIN_CONTROL 0x400810B4 -#define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL)) - -#define ADDR_GPIO056_PIN_CONTROL 0x400810B8 -#define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL)) - -#define ADDR_GPIO057_PIN_CONTROL 0x400810BC -#define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL)) - -#define ADDR_GPIO060_PIN_CONTROL 0x400810C0 -#define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL)) - -#define ADDR_GPIO061_PIN_CONTROL 0x400810C4 -#define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL)) - -#define ADDR_GPIO062_PIN_CONTROL 0x400810C8 -#define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL)) - -#define ADDR_GPIO063_PIN_CONTROL 0x400810CC -#define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL)) - -#define ADDR_GPIO064_PIN_CONTROL 0x400810D0 -#define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL)) - -#define ADDR_GPIO065_PIN_CONTROL 0x400810D4 -#define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL)) - -#define ADDR_GPIO066_PIN_CONTROL 0x400810D8 -#define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL)) - -#define ADDR_GPIO067_PIN_CONTROL 0x400810DC -#define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL)) - -#define ADDR_GPIO100_PIN_CONTROL 0x40081100 -#define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL)) - -#define ADDR_GPIO101_PIN_CONTROL 0x40081104 -#define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL)) - -#define ADDR_GPIO102_PIN_CONTROL 0x40081108 -#define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL)) - -#define ADDR_GPIO103_PIN_CONTROL 0x4008110C -#define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL)) - -#define ADDR_GPIO104_PIN_CONTROL 0x40081110 -#define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL)) - -#define ADDR_GPIO105_PIN_CONTROL 0x40081114 -#define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL)) - -#define ADDR_GPIO106_PIN_CONTROL 0x40081118 -#define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL)) - -#define ADDR_GPIO107_PIN_CONTROL 0x4008111C -#define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL)) - -#define ADDR_GPIO110_PIN_CONTROL 0x40081120 -#define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL)) - -#define ADDR_GPIO111_PIN_CONTROL 0x40081124 -#define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL)) - -#define ADDR_GPIO112_PIN_CONTROL 0x40081128 -#define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL)) - -#define ADDR_GPIO113_PIN_CONTROL 0x4008112C -#define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL)) - -#define ADDR_GPIO114_PIN_CONTROL 0x40081130 -#define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL)) - -#define ADDR_GPIO115_PIN_CONTROL 0x40081134 -#define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL)) - -#define ADDR_GPIO116_PIN_CONTROL 0x40081138 -#define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL)) - -#define ADDR_GPIO117_PIN_CONTROL 0x4008113C -#define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL)) - -#define ADDR_GPIO120_PIN_CONTROL 0x40081140 -#define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL)) - -#define ADDR_GPIO121_PIN_CONTROL 0x40081144 -#define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL)) - -#define ADDR_GPIO122_PIN_CONTROL 0x40081148 -#define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL)) - -#define ADDR_GPIO123_PIN_CONTROL 0x4008114C -#define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL)) - -#define ADDR_GPIO124_PIN_CONTROL 0x40081150 -#define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL)) - -#define ADDR_GPIO125_PIN_CONTROL 0x40081154 -#define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL)) - -#define ADDR_GPIO126_PIN_CONTROL 0x40081158 -#define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL)) - -#define ADDR_GPIO127_PIN_CONTROL 0x4008115C -#define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL)) - -#define ADDR_GPIO130_PIN_CONTROL 0x40081160 -#define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL)) - -#define ADDR_GPIO131_PIN_CONTROL 0x40081164 -#define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL)) - -#define ADDR_GPIO132_PIN_CONTROL 0x40081168 -#define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL)) - -#define ADDR_GPIO133_PIN_CONTROL 0x4008116C -#define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL)) - -#define ADDR_GPIO134_PIN_CONTROL 0x40081170 -#define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL)) - -#define ADDR_GPIO135_PIN_CONTROL 0x40081174 -#define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL)) - -#define ADDR_GPIO136_PIN_CONTROL 0x40081178 -#define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL)) - -#define ADDR_GPIO140_PIN_CONTROL 0x40081180 -#define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL)) - -#define ADDR_GPIO141_PIN_CONTROL 0x40081184 -#define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL)) - -#define ADDR_GPIO142_PIN_CONTROL 0x40081188 -#define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL)) - -#define ADDR_GPIO143_PIN_CONTROL 0x4008118C -#define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL)) - -#define ADDR_GPIO144_PIN_CONTROL 0x40081190 -#define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL)) - -#define ADDR_GPIO145_PIN_CONTROL 0x40081194 -#define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL)) - -#define ADDR_GPIO146_PIN_CONTROL 0x40081198 -#define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL)) - -#define ADDR_GPIO147_PIN_CONTROL 0x4008119C -#define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL)) - -#define ADDR_GPIO150_PIN_CONTROL 0x400811A0 -#define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL)) - -#define ADDR_GPIO151_PIN_CONTROL 0x400811A4 -#define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL)) - -#define ADDR_GPIO152_PIN_CONTROL 0x400811A8 -#define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL)) - -#define ADDR_GPIO153_PIN_CONTROL 0x400811AC -#define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL)) - -#define ADDR_GPIO154_PIN_CONTROL 0x400811B0 -#define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL)) - -#define ADDR_GPIO155_PIN_CONTROL 0x400811B4 -#define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL)) - -#define ADDR_GPIO156_PIN_CONTROL 0x400811B8 -#define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL)) - -#define ADDR_GPIO157_PIN_CONTROL 0x400811BC -#define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL)) - -#define ADDR_GPIO160_PIN_CONTROL 0x400811C0 -#define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL)) - -#define ADDR_GPIO161_PIN_CONTROL 0x400811C4 -#define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL)) - -#define ADDR_GPIO162_PIN_CONTROL 0x400811C8 -#define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL)) - -#define ADDR_GPIO163_PIN_CONTROL 0x400811CC -#define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL)) - -#define ADDR_GPIO164_PIN_CONTROL 0x400811D0 -#define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL)) - -#define ADDR_GPIO165_PIN_CONTROL 0x400811D4 -#define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL)) - -#define ADDR_GPIO200_PIN_CONTROL 0x40081200 -#define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL)) - -#define ADDR_GPIO201_PIN_CONTROL 0x40081204 -#define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL)) - -#define ADDR_GPIO202_PIN_CONTROL 0x40081208 -#define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL)) - -#define ADDR_GPIO203_PIN_CONTROL 0x4008120C -#define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL)) - -#define ADDR_GPIO204_PIN_CONTROL 0x40081210 -#define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL)) - -#define ADDR_GPIO206_PIN_CONTROL 0x40081218 -#define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL)) - -#define ADDR_GPIO210_PIN_CONTROL 0x40081220 -#define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL)) - -#define ADDR_GPIO211_PIN_CONTROL 0x40081224 -#define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL)) - -#define ADDR_GPIO212_PIN_CONTROL 0x40081228 -#define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL)) - -#define ADDR_GPIO213_PIN_CONTROL 0x4008122C -#define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL)) - -#define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280 -#define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036)) - -#define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284 -#define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076)) - -#define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288 -#define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136)) - -#define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C -#define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176)) - -#define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290 -#define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236)) - -#define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300 -#define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036)) - -#define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304 -#define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076)) - -#define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308 -#define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136)) - -#define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C -#define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176)) - -#define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310 -#define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236)) - -#define ADDR_GPIO_LOCK_4 0x400813EC -#define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4)) - -#define ADDR_GPIO_LOCK_3 0x400813F0 -#define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3)) - -#define ADDR_GPIO_LOCK_2 0x400813F4 -#define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2)) - -#define ADDR_GPIO_LOCK_1 0x400813F8 -#define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1)) - -#define ADDR_GPIO_LOCK_0 0x400813FC -#define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0)) - -#define ADDR_GPIO000_PIN_CONTROL_2 0x40081500 -#define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2)) - -#define ADDR_GPIO001_PIN_CONTROL_2 0x40081504 -#define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2)) - -#define ADDR_GPIO002_PIN_CONTROL_2 0x40081508 -#define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2)) - -#define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C -#define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2)) - -#define ADDR_GPIO004_PIN_CONTROL_2 0x40081510 -#define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2)) - -#define ADDR_GPIO005_PIN_CONTROL_2 0x40081514 -#define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2)) - -#define ADDR_GPIO006_PIN_CONTROL_2 0x40081518 -#define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2)) - -#define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C -#define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2)) - -#define ADDR_GPIO010_PIN_CONTROL_2 0x40081520 -#define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2)) - -#define ADDR_GPIO011_PIN_CONTROL_2 0x40081524 -#define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2)) - -#define ADDR_GPIO012_PIN_CONTROL_2 0x40081528 -#define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2)) - -#define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C -#define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2)) - -#define ADDR_GPIO014_PIN_CONTROL_2 0x40081530 -#define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2)) - -#define ADDR_GPIO015_PIN_CONTROL_2 0x40081534 -#define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2)) - -#define ADDR_GPIO016_PIN_CONTROL_2 0x40081538 -#define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2)) - -#define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C -#define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2)) - -#define ADDR_GPIO020_PIN_CONTROL_2 0x40081540 -#define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2)) - -#define ADDR_GPIO021_PIN_CONTROL_2 0x40081544 -#define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2)) - -#define ADDR_GPIO022_PIN_CONTROL_2 0x40081548 -#define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2)) - -#define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C -#define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2)) - -#define ADDR_GPIO024_PIN_CONTROL_2 0x40081550 -#define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2)) - -#define ADDR_GPIO025_PIN_CONTROL_2 0x40081554 -#define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2)) - -#define ADDR_GPIO026_PIN_CONTROL_2 0x40081558 -#define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2)) - -#define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C -#define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2)) - -#define ADDR_GPIO030_PIN_CONTROL_2 0x40081560 -#define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2)) - -#define ADDR_GPIO031_PIN_CONTROL_2 0x40081564 -#define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2)) - -#define ADDR_GPIO032_PIN_CONTROL_2 0x40081568 -#define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2)) - -#define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C -#define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2)) - -#define ADDR_GPIO034_PIN_CONTROL_2 0x40081570 -#define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2)) - -#define ADDR_GPIO035_PIN_CONTROL_2 0x40081574 -#define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2)) - -#define ADDR_GPIO036_PIN_CONTROL_2 0x40081578 -#define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2)) - -#define ADDR_GPIO040_PIN_CONTROL_2 0x40081580 -#define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2)) - -#define ADDR_GPIO041_PIN_CONTROL_2 0x40081584 -#define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2)) - -#define ADDR_GPIO042_PIN_CONTROL_2 0x40081588 -#define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2)) - -#define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C -#define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2)) - -#define ADDR_GPIO044_PIN_CONTROL_2 0x40081590 -#define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2)) - -#define ADDR_GPIO045_PIN_CONTROL_2 0x40081594 -#define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2)) - -#define ADDR_GPIO046_PIN_CONTROL_2 0x40081598 -#define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2)) - -#define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C -#define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2)) - -#define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0 -#define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2)) - -#define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4 -#define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2)) - -#define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8 -#define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2)) - -#define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC -#define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2)) - -#define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0 -#define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2)) - -#define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4 -#define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2)) - -#define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8 -#define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2)) - -#define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC -#define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2)) - -#define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0 -#define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2)) - -#define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4 -#define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2)) - -#define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8 -#define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2)) - -#define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC -#define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2)) - -#define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0 -#define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2)) - -#define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4 -#define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2)) - -#define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8 -#define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2)) - -#define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC -#define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2)) - -#define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0 -#define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2)) - -#define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4 -#define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2)) - -#define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8 -#define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2)) - -#define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC -#define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2)) - -#define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0 -#define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2)) - -#define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4 -#define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2)) - -#define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8 -#define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2)) - -#define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC -#define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2)) - -#define ADDR_GPIO110_PIN_CONTROL_2 0x40081600 -#define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2)) - -#define ADDR_GPIO111_PIN_CONTROL_2 0x40081604 -#define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2)) - -#define ADDR_GPIO112_PIN_CONTROL_2 0x40081608 -#define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2)) - -#define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C -#define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2)) - -#define ADDR_GPIO114_PIN_CONTROL_2 0x40081610 -#define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2)) - -#define ADDR_GPIO115_PIN_CONTROL_2 0x40081614 -#define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2)) - -#define ADDR_GPIO116_PIN_CONTROL_2 0x40081618 -#define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2)) - -#define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C -#define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2)) - -#define ADDR_GPIO120_PIN_CONTROL_2 0x40081620 -#define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2)) - -#define ADDR_GPIO121_PIN_CONTROL_2 0x40081624 -#define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2)) - -#define ADDR_GPIO122_PIN_CONTROL_2 0x40081628 -#define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2)) - -#define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C -#define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2)) - -#define ADDR_GPIO124_PIN_CONTROL_2 0x40081630 -#define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2)) - -#define ADDR_GPIO125_PIN_CONTROL_2 0x40081634 -#define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2)) - -#define ADDR_GPIO126_PIN_CONTROL_2 0x40081638 -#define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2)) - -#define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C -#define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2)) - -#define ADDR_GPIO130_PIN_CONTROL_2 0x40081640 -#define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2)) - -#define ADDR_GPIO131_PIN_CONTROL_2 0x40081644 -#define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2)) - -#define ADDR_GPIO132_PIN_CONTROL_2 0x40081648 -#define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2)) - -#define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C -#define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2)) - -#define ADDR_GPIO134_PIN_CONTROL_2 0x40081650 -#define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2)) - -#define ADDR_GPIO135_PIN_CONTROL_2 0x40081654 -#define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2)) - -#define ADDR_GPIO136_PIN_CONTROL_2 0x40081658 -#define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2)) - -#define ADDR_GPIO140_PIN_CONTROL_2 0x40081660 -#define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2)) - -#define ADDR_GPIO141_PIN_CONTROL_2 0x40081664 -#define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2)) - -#define ADDR_GPIO142_PIN_CONTROL_2 0x40081668 -#define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2)) - -#define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C -#define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2)) - -#define ADDR_GPIO144_PIN_CONTROL_2 0x40081670 -#define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2)) - -#define ADDR_GPIO145_PIN_CONTROL_2 0x40081674 -#define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2)) - -#define ADDR_GPIO146_PIN_CONTROL_2 0x40081678 -#define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2)) - -#define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C -#define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2)) - -#define ADDR_GPIO150_PIN_CONTROL_2 0x40081680 -#define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2)) - -#define ADDR_GPIO151_PIN_CONTROL_2 0x40081684 -#define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2)) - -#define ADDR_GPIO152_PIN_CONTROL_2 0x40081688 -#define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2)) - -#define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C -#define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2)) - -#define ADDR_GPIO154_PIN_CONTROL_2 0x40081690 -#define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2)) - -#define ADDR_GPIO155_PIN_CONTROL_2 0x40081694 -#define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2)) - -#define ADDR_GPIO156_PIN_CONTROL_2 0x40081698 -#define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2)) - -#define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C -#define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2)) - -#define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0 -#define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2)) - -#define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4 -#define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2)) - -#define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8 -#define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2)) - -#define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC -#define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2)) - -#define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0 -#define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2)) - -#define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4 -#define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2)) - -#define ADDR_GPIO200_PIN_CONTROL_2 0x40081720 -#define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2)) - -#define ADDR_GPIO201_PIN_CONTROL_2 0x40081724 -#define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2)) - -#define ADDR_GPIO202_PIN_CONTROL_2 0x40081728 -#define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2)) - -#define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C -#define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2)) - -#define ADDR_GPIO204_PIN_CONTROL_2 0x40081730 -#define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2)) - -#define ADDR_GPIO206_PIN_CONTROL_2 0x40081738 -#define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2)) - -#define ADDR_GPIO210_PIN_CONTROL_2 0x40081740 -#define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2)) - -#define ADDR_GPIO211_PIN_CONTROL_2 0x40081744 -#define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2)) - -#define ADDR_GPIO212_PIN_CONTROL_2 0x40081748 -#define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2)) - -#define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C -#define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2)) - -/*************************************************************** -* DMA -***************************************************************/ -#define ADDR_DMA_MAIN_CONTROL 0x40002400 -#define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL)) - -#define ADDR_DMA_AFIFO_DATA 0x40002404 -#define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA)) - -#define ADDR_DMA_MAIN_DEBUG 0x40002408 -#define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG)) - -#define ADDR_DMA_CH0_ACTIVATE 0x40002410 -#define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE)) - -#define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414 -#define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418 -#define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C -#define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS)) - -#define ADDR_DMA_CH0_CONTROL 0x40002420 -#define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL)) - -#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424 -#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428 -#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH0_TEST 0x4000242C -#define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST)) - -#define ADDR_DMA_CH1_ACTIVATE 0x40002430 -#define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE)) - -#define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434 -#define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438 -#define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C -#define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS)) - -#define ADDR_DMA_CH1_CONTROL 0x40002440 -#define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL)) - -#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444 -#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448 -#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH1_TEST 0x4000244C -#define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST)) - -#define ADDR_DMA_CH10_ACTIVATE 0x40002550 -#define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE)) - -#define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554 -#define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558 -#define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C -#define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS)) - -#define ADDR_DMA_CH10_CONTROL 0x40002560 -#define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL)) - -#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564 -#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568 -#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH10_TEST 0x4000256C -#define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST)) - -#define ADDR_DMA_CH11_ACTIVATE 0x40002570 -#define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE)) - -#define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574 -#define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578 -#define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C -#define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS)) - -#define ADDR_DMA_CH11_CONTROL 0x40002580 -#define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL)) - -#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584 -#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588 -#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH11_TEST 0x4000258C -#define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST)) - -#define ADDR_DMA_CH2_ACTIVATE 0x40002450 -#define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE)) - -#define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454 -#define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458 -#define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C -#define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS)) - -#define ADDR_DMA_CH2_CONTROL 0x40002460 -#define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL)) - -#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464 -#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468 -#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH2_TEST 0x4000246C -#define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST)) - -#define ADDR_DMA_CH3_ACTIVATE 0x40002470 -#define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE)) - -#define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474 -#define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478 -#define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C -#define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS)) - -#define ADDR_DMA_CH3_CONTROL 0x40002480 -#define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL)) - -#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484 -#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488 -#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH3_TEST 0x4000248C -#define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST)) - -#define ADDR_DMA_CH4_ACTIVATE 0x40002490 -#define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE)) - -#define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494 -#define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498 -#define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C -#define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS)) - -#define ADDR_DMA_CH4_CONTROL 0x400024A0 -#define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL)) - -#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4 -#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8 -#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH4_TEST 0x400024AC -#define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST)) - -#define ADDR_DMA_CH5_ACTIVATE 0x400024B0 -#define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE)) - -#define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4 -#define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8 -#define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC -#define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS)) - -#define ADDR_DMA_CH5_CONTROL 0x400024C0 -#define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL)) - -#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4 -#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8 -#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH5_TEST 0x400024CC -#define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST)) - -#define ADDR_DMA_CH6_ACTIVATE 0x400024D0 -#define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE)) - -#define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4 -#define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8 -#define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC -#define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS)) - -#define ADDR_DMA_CH6_CONTROL 0x4.00E+05 -#define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL)) - -#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09 -#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13 -#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH6_TEST 0x400024EC -#define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST)) - -#define ADDR_DMA_CH7_ACTIVATE 0x400024F0 -#define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE)) - -#define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4 -#define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8 -#define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC -#define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS)) - -#define ADDR_DMA_CH7_CONTROL 0x40002500 -#define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL)) - -#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504 -#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508 -#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH7_TEST 0x4000250C -#define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST)) - -#define ADDR_DMA_CH8_ACTIVATE 0x40002510 -#define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE)) - -#define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514 -#define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518 -#define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C -#define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS)) - -#define ADDR_DMA_CH8_CONTROL 0x40002520 -#define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL)) - -#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524 -#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528 -#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH8_TEST 0x4000252C -#define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST)) - -#define ADDR_DMA_CH9_ACTIVATE 0x40002530 -#define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE)) - -#define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534 -#define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS)) - -#define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538 -#define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS)) - -#define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C -#define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS)) - -#define ADDR_DMA_CH9_CONTROL 0x40002540 -#define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL)) - -#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544 -#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS)) - -#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548 -#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE)) - -#define ADDR_DMA_CH9_TEST 0x4000254C -#define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST)) - -#endif /*SMSCMMCR_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer.h deleted file mode 100644 index 129f5f2f5..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer.h +++ /dev/null @@ -1,409 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/11/22 06:01:28 $ -$Author: amohandas $ -Last Change: Updated with unit testing feedbacks -******************************************************************************/ -/** @file btimer.h -* \brief Basic Timer Peripheral Header file -* \author jvasanth -* -* This file is the header file for Basic Timer Peripheral -******************************************************************************/ - -/** @defgroup Basic_Timer - * @{ - */ - -#ifndef _BTIMER_H -#define _BTIMER_H - -/******************************************************************************/ -/** Logical Timer ID for APIs. - * This is the timer IDs passed to Basic Timer API function calls - *******************************************************************************/ -enum _PID_BTIMER_ -{ - PID_BTIMER_0, - PID_BTIMER_1, - PID_BTIMER_2, - PID_BTIMER_3, - PID_BTIMER_4, - PID_BTIMER_5, - PID_BTIMER_MAX -}; - -/* ---------------------------------------------------------------------- */ -/* Logical flags for Timer Control */ -/* ---------------------------------------------------------------------- */ -//This is for tmr_cntl parameter in btimer_init function -#define BTIMER_AUTO_RESTART (0x08u) -#define BTIMER_ONE_SHOT (0u) -#define BTIMER_COUNT_UP (0x04u) -#define BTIMER_COUNT_DOWN (0u) -#define BTIMER_INT_EN (0x01u) -#define BTIMER_NO_INT (0u) -/* ---------------------------------------------------------------------- */ - - -//Timer Block Hardware Bits and Masks -#define BTIMER_CNTL_HALT (0x80UL) -#define BTIMER_CNTL_RELOAD (0x40UL) -#define BTIMER_CNTL_START (0x20UL) -#define BTIMER_CNTL_SOFT_RESET (0x10UL) -#define BTIMER_CNTL_AUTO_RESTART (0x08UL) -#define BTIMER_CNTL_COUNT_UP (0x04UL) -#define BTIMER_CNTL_ENABLE (0x01UL) - -#define BTIMER_CNTL_HALT_BIT (7U) -#define BTIMER_CNTL_RELOAD_BIT (6U) -#define BTIMER_CNTL_START_BIT (5U) -#define BTIMER_CNTRL_SOFT_RESET_BIT (4U) -#define BTIMER_CNTL_AUTO_RESTART_BIT (3U) -#define BTIMER_CNTL_COUNT_DIR_BIT (2U) -#define BTIMER_CNTL_ENABLE_BIT (0U) - -#define BTIMER_GIRQ MEC_GIRQ23_ID -#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX - - -/* ---------------------------------------------------------------------- */ -/* API - Basic Timer Intitialization function */ -/* ---------------------------------------------------------------------- */ - -/** Initialize specified timer - * @param btimer_id Basic Timer ID - * @param tmr_cntl Logical flags for Timer Control - * @param initial_count Initial Count - * @param preload_count Preload Count - * @note Performs a soft reset of the timer before configuration - */ -void btimer_init(uint8_t btimer_id, - uint16_t tmr_cntl, - uint16_t prescaler, - uint32_t initial_count, - uint32_t preload_count); - -/* ---------------------------------------------------------------------- */ -/* API - Functions to program and read the Basic Timer Counter */ -/* ---------------------------------------------------------------------- */ -/** Program timer's counter register. - * @param btimer_id Basic Timer ID - * @param count new counter value - * @note Timer hardware may implement a 16-bit or 32-bit - * hardware counter. If the timer is 16-bit only the lower - * 16-bits of the count paramter are used. - */ -void btimer_count_set(uint8_t btimer_id, uint32_t count); - -/** Return current value of timer's count register. - * @param btimer_id Basic Timer ID. - * @return uint32_t timer count may be 32 or 16 bits depending - * upon the hardware. Timers 0-3 are 16-bit - * and Timers 4-5 are 32-bit. - */ -uint32_t btimer_count_get(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Function to reload counter from Preload Register */ -/* ---------------------------------------------------------------------- */ -/** Force timer to reload counter from preload - * register. - * @param btimer_id Basic Timer ID. - * @note Hardware will only reload counter if timer is running. - */ -void btimer_reload(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Functions for stopping and starting the basic Timer */ -/* ---------------------------------------------------------------------- */ -/** Start timer counting. - * @param btimer_id Basic Timer ID. - */ -void btimer_start(uint8_t btimer_id); - -/** Stop timer. - * @param btimer_id Basic Timer ID. - * @note When a stopped timer is started again it will reload - * the count register from preload value. - */ -void btimer_stop(uint8_t btimer_id); - -/** Return state of timer's START bit. - * @param btimer_id Basic Timer ID. - * @return uint8_t 0(timer not started), 1 (timer started) - */ -uint8_t btimer_is_started(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Function to perform basic timer soft reset */ -/* ---------------------------------------------------------------------- */ -/** Peform soft reset of specified timer. - * @param btimer_id Basic Timer ID - * @note Soft reset set all registers to POR values. - * Spins 256 times waiting on hardware to clear reset bit. - */ -void btimer_reset(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Functions to halt/unhalt the timer counting */ -/* ---------------------------------------------------------------------- */ -/** Halt timer counting with no reload on unhalt. - * @param btimer_id Basic Timer ID. - * @note A halted timer will not reload the count register when - * unhalted, it will continue counting from the current - * count value. - */ -void btimer_halt(uint8_t btimer_id); - -/** Unhalt timer counting. - * @param btimer_id Basic Timer ID. - */ -void btimer_unhalt(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Functions for Basic Timer interrupt */ -/* ---------------------------------------------------------------------- */ -/** Enable specified timer's interrupt from the block. - * @param btimer_id Basic Timer ID. - * @param ien Non-zero enable interrupt in timer block, 0 - * disable. - */ -void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien); - -/** Read Timer interrupt status and clear if set - * @param btimer_id Basic Timer ID. - * @return uint8_t 1 (Timer interrupt status set) else 0. - * @note If timer interrupt status is set then clear it before - * returning. - */ -uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Functions for Basic Timer GIRQ */ -/* ---------------------------------------------------------------------- */ -/** Enables GIRQ enable bit for the timer - * @param btimer_id Basic Timer ID. - */ -void btimer_girq_enable_set(uint8_t btimer_id); - -/** Clears GIRQ enable bit for the timer - * @param btimer_id Basic Timer ID. - */ -void btimer_girq_enable_clr(uint8_t btimer_id); - -/** Returns GIRQ source bit for the timer - * @param btimer_id Basic Timer ID. - * @return uint8_t 0(src bit not set), Non-zero (src bit set) - */ -uint8_t btimer_girq_src_get(uint8_t btimer_id); - -/** Clears GIRQ source bit for the timer - * @param btimer_id Basic Timer ID. - */ -void btimer_girq_src_clr(uint8_t btimer_id); - -/** Returns GIRQ result bit for the timer - * @param btimer_id Basic Timer ID. - * @return uint8_t 0(result bit not set), Non-zero (result bit set) - */ -uint8_t btimer_girq_result_get(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* API - Functions for Basic Timer Sleep */ -/* ---------------------------------------------------------------------- */ -/** Enable/Disable clock gating on idle of a timer - * @param btimer_id Basic Timer ID. - * @param sleep_en 1 = Sleep enable, 0 = Sleep disable - */ -void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en); - -/** Returns clk required status for the timer block - * @param btimer_id Basic Timer ID. - * @return Non-zero if clk required, else 0 - */ -uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id); - -/** Enable/Disable reset on sleep for the timer block - * @param btimer_id Basic Timer ID. - * @param reset_en 1 to enable, 0 to disable - */ -void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Functions to set and read Timer Counter Register */ -/* ---------------------------------------------------------------------- */ -/** Sets timer counter - * @param btimer_id Basic Timer ID - * @param count - 32-bit counter - */ -void p_btimer_count_set(uint8_t btimer_id, uint32_t count); - -/** Read the timer counter - * @param btimer_id Basic Timer ID - * @return count - 32-bit counter - */ -uint32_t p_btimer_count_get(uint8_t btimer_id); - - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Function to program the Preload */ -/* ---------------------------------------------------------------------- */ -/** Sets preload for the counter - * @param btimer_id Basic Timer ID - * @param preload_count - 32-bit pre-load value - */ -void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Functions - Functions for basic timer interrupts */ -/* ---------------------------------------------------------------------- */ -/** Reads the interrupt status bit in the timer block - * @param btimer_id Basic Timer ID - * @return status - 1 if interrupt status set, else 0 - */ -uint8_t p_btimer_int_status_get(uint8_t btimer_id); - -/** Clears interrupt status bit in the timer block - * @param btimer_id Basic Timer ID - */ -void p_btimer_int_status_clr(uint8_t btimer_id); - -/** Sets interrupt enable bit in the timer block - * @param btimer_id Basic Timer ID - */ -void p_btimer_int_enable_set(uint8_t btimer_id); - -/** Clears interrupt enable bit for the timer block - * @param btimer_id Basic Timer ID - */ -void p_btimer_int_enable_clr(uint8_t btimer_id); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Functions - Functions for Control Register */ -/* ---------------------------------------------------------------------- */ -/** Writes the control register 32-bits - * @param btimer_id Basic Timer ID - * @param value - 32-bit value to program - */ -void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value); - -/** Reads the control register - * @param btimer_id Basic Timer ID - * @return uint32_t - 32-bit value - */ -uint32_t p_btimer_ctrl_read(uint8_t btimer_id); - -/** Clears enable bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_enable_set(uint8_t btimer_id); - -/** Clears enable bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_enable_clr(uint8_t btimer_id); - -/** Sets counter direction bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id); - -/** Clears counter direction bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id); - -/** Sets auto restart bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id); - -/** Clears auto resetart bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id); - -/** Sets soft reset bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id); - -/** Read Soft Reset bit - * @param btimer_id Basic Timer ID - * @return 0 if soft reset status bit cleared; else non-zero value - */ -uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id); - -/** Sets start bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_start_set(uint8_t btimer_id); - -/** Read start bit in the control register - * @param btimer_id Basic Timer ID - * @return 0 if start bit not set; else non-zero value - */ -uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id); - -/** Clears start bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_start_clr(uint8_t btimer_id); - -/** Sets reload bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_reload_set(uint8_t btimer_id); - -/** Clears reload bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_reload_clr(uint8_t btimer_id); - -/** Sets halt bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_halt_set(uint8_t btimer_id); - -/** Clears halt bit in the control register - * @param btimer_id Basic Timer ID - */ - -void p_btimer_ctrl_halt_clr(uint8_t btimer_id); - -/** Sets prescale value - * @param btimer_id Basic Timer ID - * @param prescaler - 16-bit pre-scale value - */ -void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler); - - -#endif // #ifndef _BTIMER_H - -/* end btimer_perphl.c */ - -/** @} //Peripherals Basic_Timer - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer_api.c deleted file mode 100644 index d4cfea3e2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer_api.c +++ /dev/null @@ -1,473 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #2 $ -$DateTime: 2015/11/24 06:27:00 $ -$Author: amohandas $ -Last Change: Updated for tabs -******************************************************************************/ -/** @file btimer_api.c -* \brief Basic Timer APIs Source file -* \author jvasanth -* -* This file implements the Basic Timer API functions -******************************************************************************/ - -/** @defgroup Basic_Timer - * @{ - */ - -#include "common_lib.h" -#include "btimer.h" -#include "..\pcr\pcr.h" - -/** Basic Timer Sleep Registers & Bit Positions */ -static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = { - PCR_BTIMER0, - PCR_BTIMER1, - PCR_BTIMER2, - PCR_BTIMER3, - PCR_BTIMER4, - PCR_BTIMER5 -}; - -#ifdef PLIB_BTIMER_CHECK_ID - -/** Local helper that checks if logical Timer ID is valid. - * @param btimer_id Basic Timer ID - * @return uint8_t Non-zero(VALID), 0(Invalid) - */ -static uint8_t btmr_valid(uint8_t btimer_id) -{ - if ( btimer_id < (PID_BTIMER_MAX ) ) { - return true; - } - return false; -} - -#else - - -/** This version of tmr_valid skips checking always returning 1. - * Compiler may optimize it out. - * @param btimer_id Basic Timer ID - * @return uint8_t 1(VALID) - */ -static uint8_t btmr_valid(uint8_t btimer_id) { return 1; } - -#endif - - -/* ---------------------------------------------------------------------- */ -/* Basic Timer Intitialization function */ -/* ---------------------------------------------------------------------- */ - -/** Initialize specified timer - * @param btimer_id Basic Timer ID - * @param tmr_cntl Logical flags for Timer Control - * @param initial_count Initial Count - * @param preload_count Preload Count - * @note Performs a soft reset of the timer before configuration - */ -void btimer_init(uint8_t btimer_id, - uint16_t tmr_cntl, - uint16_t prescaler, - uint32_t initial_count, - uint32_t preload_count) -{ - uint32_t value; - - if (btmr_valid(btimer_id)) { - - btimer_reset(btimer_id); - - // Ungate timer clocks and program prescale - value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); - p_btimer_ctrl_write(btimer_id, value); - - // Program Preload & initial counter value - p_btimer_preload_set(btimer_id, preload_count); - p_btimer_count_set(btimer_id, initial_count); - - // Program control register, interrupt enable, and clear status - if (tmr_cntl & BTIMER_COUNT_UP) { - p_btimer_ctrl_counter_dir_set(btimer_id); - } - if (tmr_cntl & BTIMER_AUTO_RESTART) { - p_btimer_ctrl_auto_restart_set(btimer_id); - } - if (tmr_cntl & BTIMER_INT_EN) { - p_btimer_int_enable_set(btimer_id); // enable first - p_btimer_int_status_clr(btimer_id); // clear status - } - } -} - -/* ---------------------------------------------------------------------- */ -/* Functions to program and read the Basic Timer Counter */ -/* ---------------------------------------------------------------------- */ - -/** Program timer's counter register. - * @param btimer_id Basic Timer ID - * @param count new counter value - * @note Timer hardware may implement a 16-bit or 32-bit - * hardware counter. If the timer is 16-bit only the lower - * 16-bits of the count paramter are used. - */ -void btimer_count_set(uint8_t btimer_id, uint32_t count) -{ - if ( btmr_valid(btimer_id) ) { - - p_btimer_count_set(btimer_id, count); - } -} - -/** Return current value of timer's count register. - * @param btimer_id Basic Timer ID. - * @return uint32_t timer count may be 32 or 16 bits depending - * upon the hardware. Timers 0-3 are 16-bit - * and Timers 4-5 are 32-bit. - */ -uint32_t btimer_count_get(uint8_t btimer_id) -{ - uint32_t cnt; - - cnt = 0ul; - if ( btmr_valid(btimer_id) ) { - - cnt = p_btimer_count_get(btimer_id); - } - - return cnt; -} - -/* ---------------------------------------------------------------------- */ -/* Function to reload counter from Preload Register */ -/* ---------------------------------------------------------------------- */ - -/** Force timer to reload counter from preload - * register. - * @param btimer_id Basic Timer ID. - * @note Hardware will only reload counter if timer is running. - */ -void btimer_reload(uint8_t btimer_id) -{ - if ( btmr_valid(btimer_id) ) { - - if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running - { - p_btimer_ctrl_reload_set(btimer_id); - } - } -} - -/* ---------------------------------------------------------------------- */ -/* Functions for stopping and starting the basic Timer */ -/* ---------------------------------------------------------------------- */ - -/** Start timer counting. - * @param btimer_id Basic Timer ID. - */ -void btimer_start(uint8_t btimer_id) -{ - if ( btmr_valid(btimer_id) ) { - - p_btimer_ctrl_start_set(btimer_id); - } -} - -/** Stop timer. - * @param btimer_id Basic Timer ID. - * @note When a stopped timer is started again it will reload - * the count register from preload value. - */ -void btimer_stop(uint8_t btimer_id) -{ - if ( btmr_valid(btimer_id) ) { - - p_btimer_ctrl_start_clr(btimer_id); - - } -} - -/** Return state of timer's START bit. - * @param btimer_id Basic Timer ID. - * @return uint8_t 0(timer not started), 1 (timer started) - */ -uint8_t btimer_is_started(uint8_t btimer_id) -{ - uint8_t sts; - - sts = 0; - if ( btmr_valid(btimer_id) ) { - - if (p_btimer_ctrl_start_get(btimer_id)) - { - sts = 1; - } - } - return sts; -} - -/* ---------------------------------------------------------------------- */ -/* Function to perform basic timer soft reset */ -/* ---------------------------------------------------------------------- */ - -/** Peform soft reset of specified timer. - * @param btimer_id Basic Timer ID - * @note Soft reset set all registers to POR values. - * Spins 256 times waiting on hardware to clear reset bit. - */ -void btimer_reset(uint8_t btimer_id) -{ - uint32_t wait_cnt; - uint8_t soft_reset_sts; - - if (btmr_valid(btimer_id)) { - - p_btimer_ctrl_soft_reset_set(btimer_id); - - wait_cnt = 256ul; - do { - soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id); - - if (0 == soft_reset_sts){ - break; - } - } - while ( wait_cnt-- ); - } -} - -/* ---------------------------------------------------------------------- */ -/* Functions to halt/unhalt the timer counting */ -/* ---------------------------------------------------------------------- */ - -/** Halt timer counting with no reload on unhalt. - * @param btimer_id Basic Timer ID. - * @note A halted timer will not reload the count register when - * unhalted, it will continue counting from the current - * count value. - */ -void btimer_halt(uint8_t btimer_id) -{ - if ( btmr_valid(btimer_id) ) { - - p_btimer_ctrl_halt_set(btimer_id); - } -} - -/** Unhalt timer counting. - * @param btimer_id Basic Timer ID. - */ -void btimer_unhalt(uint8_t btimer_id) -{ - if ( btmr_valid(btimer_id) ) { - - p_btimer_ctrl_halt_clr(btimer_id); - } -} - -/* ---------------------------------------------------------------------- */ -/* Functions for Basic Timer interrupt */ -/* ---------------------------------------------------------------------- */ - -/** Enable specified timer's interrupt from the block. - * @param btimer_id Basic Timer ID. - * @param ien Non-zero enable interrupt in timer block, 0 - * disable. - */ -void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien) -{ - if (btmr_valid(btimer_id)) { - - p_btimer_int_enable_set(btimer_id); - - if (ien) { - p_btimer_int_enable_set(btimer_id); - } else { - p_btimer_int_enable_clr(btimer_id); - } - } -} - -/** Read Timer interrupt status and clear if set - * @param btimer_id Basic Timer ID. - * @return uint8_t 1 (Timer interrupt status set) else 0. - * @note If timer interrupt status is set then clear it before - * returning. - */ -uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id) -{ - uint8_t sts; - - sts = 0; - if (btmr_valid(btimer_id)) { - - sts = p_btimer_int_status_get(btimer_id); - if (sts) { - p_btimer_int_status_clr(btimer_id); - } - } - return sts; -} - -#if 0 //Temporary disable until interrupt module - -/* ---------------------------------------------------------------------- */ -/* Functions for Basic Timer GIRQ */ -/* ---------------------------------------------------------------------- */ - -/** Enables GIRQ enable bit for the timer - * @param btimer_id Basic Timer ID. - */ -void btimer_girq_enable_set(uint8_t btimer_id) -{ - if (btmr_valid(btimer_id)) - { - //Note: Bit Position is same as Timer ID - p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id); - } -} - -/** Clears GIRQ enable bit for the timer - * @param btimer_id Basic Timer ID. - */ -void btimer_girq_enable_clr(uint8_t btimer_id) -{ - if (btmr_valid(btimer_id)) - { - //Note: Bit Position is same as Timer ID - p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id); - } - -} - -/** Returns GIRQ source bit for the timer - * @param btimer_id Basic Timer ID. - * @return uint8_t 0(src bit not set), Non-zero (src bit set) - */ -uint8_t btimer_girq_src_get(uint8_t btimer_id) -{ - uint8_t retVal; - - retVal = 0; - if (btmr_valid(btimer_id)) - { - //Note: Bit Position is same as Timer ID - retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); - } - - return retVal; -} - -/** Clears GIRQ source bit for the timer - * @param btimer_id Basic Timer ID. - */ -void btimer_girq_src_clr(uint8_t btimer_id) -{ - if (btmr_valid(btimer_id)) - { - //Note: Bit Position is same as Timer ID - p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); - } -} - -/** Returns GIRQ result bit for the timer - * @param btimer_id Basic Timer ID. - * @return uint8_t 0(result bit not set), Non-zero (result bit set) - */ -uint8_t btimer_girq_result_get(uint8_t btimer_id) -{ - uint8_t retVal; - - retVal = 0; - if (btmr_valid(btimer_id)) - { - //Note: Bit Position is same as Timer ID - retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); - } - - return retVal; -} -#endif - -/* ---------------------------------------------------------------------- */ -/* Functions for Basic Timer Sleep */ -/* ---------------------------------------------------------------------- */ - -/** Enable/Disable clock gating on idle of a timer - * @param btimer_id Basic Timer ID. - * @param sleep_en 1 = Sleep enable, 0 = Sleep disable - */ -void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en) -{ - uint32_t pcr_blk_id; - - if ( btmr_valid(btimer_id) ) - { - pcr_blk_id = btmr_pcr_id[btimer_id]; - - pcr_sleep_enable(pcr_blk_id, sleep_en); - } -} - -/** Returns clk required status for the timer block - * @param btimer_id Basic Timer ID. - * @return Non-zero if clk required, else 0 - */ -uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id) -{ - uint32_t retVal; - uint32_t pcr_blk_id; - - retVal = 0ul; - if ( btmr_valid(btimer_id) ) - { - pcr_blk_id = btmr_pcr_id[btimer_id]; - - retVal = pcr_clock_reqd_status_get(pcr_blk_id); - } - - return retVal; -} - -/** Enable/Disable reset on sleep for the timer block - * @param btimer_id Basic Timer ID. - * @param reset_en 1 to enable, 0 to disable - */ -void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en) -{ - uint32_t pcr_blk_id; - - if ( btmr_valid(btimer_id) ) - { - pcr_blk_id = btmr_pcr_id[btimer_id]; - - pcr_reset_enable(pcr_blk_id, reset_en); - } -} - -/* end btimer_api.c */ - -/** @} //Peripheral Basic_Timer - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer_perphl.c deleted file mode 100644 index b2c9b97bc..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/basic_timer/btimer_perphl.c +++ /dev/null @@ -1,287 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #2 $ -$DateTime: 2015/11/24 06:27:00 $ -$Author: amohandas $ -Last Change: Updated for tabs -******************************************************************************/ -/** @file btimer_perphl.c -* \brief Basic Timer Peripheral Source file -* \author jvasanth -* -* This file implements the Basic Timer Peripheral functions -******************************************************************************/ - -/** @defgroup Basic_Timer - * @{ - */ - -#include "common_lib.h" -#include "btimer.h" - -/** Basic Timer Instance base addresses */ -static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = { - CEC1302_TIMER_16_0, - CEC1302_TIMER_16_1, - CEC1302_TIMER_16_2, - CEC1302_TIMER_16_3, - CEC1302_TIMER_32_0, - CEC1302_TIMER_32_1 -}; - -/* ---------------------------------------------------------------------- */ -/* Functions to set and read Timer Counter Register */ -/* ---------------------------------------------------------------------- */ - -/** Sets timer counter - * @param btimer_id Basic Timer ID - * @param count - 32-bit counter - */ -void p_btimer_count_set(uint8_t btimer_id, uint32_t count) -{ - btmr_inst[btimer_id]->COUNT = count; -} - -/** Read the timer counter - * @param btimer_id Basic Timer ID - * @return count - 32-bit counter - */ -uint32_t p_btimer_count_get(uint8_t btimer_id) -{ - return btmr_inst[btimer_id]->COUNT; -} - -/* ---------------------------------------------------------------------- */ -/* Function to program the Preload */ -/* ---------------------------------------------------------------------- */ - -/** Sets preload for the counter - * @param btimer_id Basic Timer ID - * @param preload_count - 32-bit pre-load value - */ -void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count) -{ - btmr_inst[btimer_id]->PRE_LOAD = preload_count; -} - -/* ---------------------------------------------------------------------- */ -/* Functions for basic timer interrupts */ -/* ---------------------------------------------------------------------- */ - -/** Reads the interrupt status bit in the timer block - * @param btimer_id Basic Timer ID - * @return status - 1 if interrupt status set, else 0 - */ -uint8_t p_btimer_int_status_get(uint8_t btimer_id) -{ - return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS); -} - -/** Clears interrupt status bit in the timer block - * @param btimer_id Basic Timer ID - */ -void p_btimer_int_status_clr(uint8_t btimer_id) -{ - // Write 1 to clear - btmr_inst[btimer_id]->INTERRUPT_STATUS = 1; -} - -/** Sets interrupt enable bit in the timer block - * @param btimer_id Basic Timer ID - */ -void p_btimer_int_enable_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1; -} - -/** Clears interrupt enable bit for the timer block - * @param btimer_id Basic Timer ID - */ -void p_btimer_int_enable_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0; -} - -/* ---------------------------------------------------------------------- */ -/* Functions for Control Register */ -/* ---------------------------------------------------------------------- */ - -/** Writes the control register 32-bits - * @param btimer_id Basic Timer ID - * @param value - 32-bit value to program - */ -void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value) -{ - btmr_inst[btimer_id]->CONTROL.w = value; -} - -/** Reads the control register - * @param btimer_id Basic Timer ID - * @return uint32_t - 32-bit value - */ -uint32_t p_btimer_ctrl_read(uint8_t btimer_id) -{ - uint32_t retVal; - - retVal = btmr_inst[btimer_id]->CONTROL.w; - - return retVal; -} - -/** Sets enable bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_enable_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE; -} - -/** Clears enable bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_enable_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE; -} - -/** Sets counter direction bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP; -} - -/** Clears counter direction bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP; -} - -/** Sets auto restart bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART; -} - -/** Clears auto resetart bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART; -} - -/** Sets soft reset bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET; -} - -/** Read Soft Reset bit - * @param btimer_id Basic Timer ID - * @return 0 if soft reset status bit cleared; else non-zero value - */ -uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id) -{ - return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET); -} - -/** Sets start bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_start_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START; -} - -/** Read start bit in the control register - * @param btimer_id Basic Timer ID - * @return 0 if start bit not set; else non-zero value - */ -uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id) -{ - return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START); -} - -/** Clears start bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_start_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START; -} - -/** Sets reload bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_reload_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD; -} - -/** Clears reload bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_reload_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD; -} - -/** Sets halt bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_halt_set(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT; -} - -/** Clears halt bit in the control register - * @param btimer_id Basic Timer ID - */ -void p_btimer_ctrl_halt_clr(uint8_t btimer_id) -{ - btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT; -} - -/** Sets prescale value - * @param btimer_id Basic Timer ID - * @param prescaler - 16-bit pre-scale value - */ -void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler) -{ - btmr_inst[btimer_id]->CONTROL.h[1] = prescaler; -} - - -/* end btimer_perphl.c */ - -/** @} //Peripheral Basic_Timer - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/common.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/common.h deleted file mode 100644 index f8fc613b6..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/common.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - ********************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. - ********************************************************************************** - * common.h - * This is the header file including common headers from various modules - ********************************************************************************** - * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $ - * Description: added ict module - ********************************************************************************** - * #xx - ********************************************************************************** - * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $ - */ - -/*********************************************************************************/ -/** @defgroup common common - * @{ - */ - -/** @file common.h -* \brief header file including common headers from various modules -* \author App Firmware Team -* -**********************************************************************************/ -#ifndef _COMMON_H_ -#define _COMMON_H_ - -// Include common headers from various modules -// !!! The include order is important !!! -#include "cfg.h" -#include "platform.h" -#include "MCHP_CEC1302.h" -#include "ARM_REG.h" -/* Cortex-M4 processor and core peripherals */ -#include "core_cm4.h" -#include "MEC1322.h" - -#include "defs.h" -#include "string.h" - -#include "kernel.h" -#include "..\system\system.h" -#include "..\debug\trace.h" -#include "..\interrupt\interrupt.h" -#include "..\timer\timer_app.h" - -#include "cec1302_crypto_api.h" - -#endif /*_COMMON_H_*/ - -/** @} - */ - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/common_lib.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/common_lib.h deleted file mode 100644 index b97c5015e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/common_lib.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - ********************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. - ********************************************************************************** - * common.h - * This is the header file including common headers from various modules - ********************************************************************************** - * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $ - * Description: added ict module - ********************************************************************************** - * #xx - ********************************************************************************** - * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $ - */ - -/*********************************************************************************/ -/** @defgroup common common - * @{ - */ - -/** @file common.h -* \brief header file including common headers from various modules -* \author App Firmware Team -* -**********************************************************************************/ -#ifndef _COMMON_LIB_H_ -#define _COMMON_LIB_H_ - -// Include common headers from various modules -// !!! The include order is important !!! -#include "platform.h" -#include "ARM_REG.h" -#include "MCHP_CEC1302.h" -/* Cortex-M4 processor and core peripherals */ -#include "core_cm4.h" -#include "MEC1322.h" -#include "defs.h" -#include "string.h" -//_RB_#include "build.h" -//_RB_#include "..\system\system.h" -//_RB_#include "..\debug\trace.h" -#include -#endif /*_COMMON_LIB_H_*/ - -/** @} - */ - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/defs.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/defs.h deleted file mode 100644 index d900fab29..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/defs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - ********************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. - ********************************************************************************** - * defs.h - * This is the definition header file for generic usages - ********************************************************************************** - * #xx - ********************************************************************************** - * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $ - */ - - -/*********************************************************************************/ -/** @defgroup defs defs - * @{ - */ - -/** @file defs.h -* \brief definition header file for generic usages -* \author App Firmware Team -* -**********************************************************************************/ -#ifndef _DEFS_H_ -#define _DEFS_H_ - -/* bit operation MACRO, xvar could be byte, word or dword */ -#define mSET_BIT(x, xvar) ( xvar |= x ) -#define mCLR_BIT(x, xvar) ( xvar &= ~x ) -#define mGET_BIT(x, xvar) ( xvar & x ) -#define mCLR_SRC_BIT(x, xvar) ( xvar = x ) -#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}} - -#endif /*_DEFS_H_*/ - -/** @} - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer.h deleted file mode 100644 index cf94dd5eb..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer.h +++ /dev/null @@ -1,111 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/12/17 01:09:00 $ -$Author: snakka $ -Last Change: Updated for peripheral functions prefix p_ -******************************************************************************/ -/** @file btimer.h -* \brief Hibernation Timer Peripheral Header file -* \author jvasanth -* -* This file is the header file for Hibernation Timer Peripheral -******************************************************************************/ - -/** @defgroup Hibernation_Timer - * @{ - */ - -#ifndef _HTIMER_H -#define _HTIMER_H - -/******************************************************************************/ -/** Logical Timer ID for APIs. - * This is the timer IDs passed to Hibernation Timer function calls - *******************************************************************************/ -enum _PID_HTIMER_ -{ - PID_HTIMER_0, - PID_HTIMER_MAX -}; - -#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX - -/* -------------------------------------------------------------------- */ -/* Hibernation Timer APIs */ -/* -------------------------------------------------------------------- */ -/** Enables hibernation timer - * @param htimer_id Hibernation Timer ID - * @param preload_value - 16-bit preload value - * @param resolution_mode 0 - resolution of 30.5us per LSB, - * 1 - resolution of 0.125s per LSB - */ -void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode); - -/** Disables the hibernation timer by programming the prelaod value as 0 - * @param htimer_id Hibernation Timer ID - */ -void htimer_disable(uint8_t htimer_id); - - -/** Reloads new preload value for the hibernation timer - * @param htimer_id Hibernation Timer ID - * @param reload_value - 16-bit preload value - */ -void htimer_reload(uint8_t htimer_id, uint16_t reload_value); - - -/* -------------------------------------------------------------------- */ -/* Hibernation Timer Peripheral Functions */ -/* -------------------------------------------------------------------- */ -/** Sets hibernation timer preload value - * @param htimer_id Hibernation Timer ID - * @param preload_value - 16-bit preload value - */ -void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value); - -/*_RB_ Added by RB. */ -uint16_t p_htimer_preload_get(uint8_t htimer_id); - -/** Sets hibernation timer resolution - * @param htimer_id Hibernation Timer ID - * @param resolution_mode 0 - resolution of 30.5us per LSB, - * 1 - resolution of 0.125s per LSB - */ -void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode); - - -/** Returns the Hibernation Timer current count value - * @param htimer_id Hibernation Timer ID - * @return 16-bit count value - */ -uint16_t p_htimer_count_get(uint8_t htimer_id); - - -#endif // #ifndef _HTIMER_H - -/* end htimer.h */ - -/** @} //Peripherals Hibernation_Timer - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer_api.c deleted file mode 100644 index 1441bcf36..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer_api.c +++ /dev/null @@ -1,112 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/12/17 01:09:00 $ -$Author: snakka $ -Last Change: Updated for peripheral functions prefix p_ -******************************************************************************/ -/** @file btimer_perphl.c -* \brief Hibernation Timer API Source file -* \author jvasanth -* -* This file implements Hibernation Timer APIs -******************************************************************************/ - -/** @defgroup Hibernation_Timer - * @{ - */ - -#include "common_lib.h" -#include "htimer.h" - -#ifdef PLIB_HTIMER_CHECK_ID - -/** Local helper that checks if logical Timer ID is valid. - * @param htimer_id Hibernation Timer ID - * @return uint8_t Non-zero(VALID), 0(Invalid) - */ -static uint8_t htmr_valid(uint8_t htimer_id) -{ - if ( htimer_id < (PID_HTIMER_MAX ) ) { - return 1; - } - return 0; -} - -#else - - -/** This version of tmr_valid skips checking always returning 1. - * Compiler may optimize it out. - * @param htimer_id Hibernation Timer ID - * @return uint8_t 1(VALID) - */ -static uint8_t htmr_valid(uint8_t htimer_id) { return 1; } - -#endif - - -/** Enables hibernation timer - * @param htimer_id Hibernation Timer ID - * @param preload_value - 16-bit preload value - * @param resolution_mode 0 - resolution of 30.5us per LSB, - * 1 - resolution of 0.125s per LSB - */ -void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode) -{ - if (htmr_valid(htimer_id)) - { - p_htimer_preload_set(htimer_id, preload_value); - - p_htimer_resolution_set(htimer_id, resolution_mode); - } -} - -/** Disables the hibernation timer by programming the prelaod value as 0 - * @param htimer_id Hibernation Timer ID - */ -void htimer_disable(uint8_t htimer_id) -{ - if (htmr_valid(htimer_id)) - { - p_htimer_preload_set(htimer_id, 0); - } -} - -/** Reloads new preload value for the hibernation timer - * @param htimer_id Hibernation Timer ID - * @param reload_value - 16-bit preload value - */ -void htimer_reload(uint8_t htimer_id, uint16_t reload_value) -{ - if ( htmr_valid(htimer_id)) - { - p_htimer_preload_set(htimer_id, reload_value); - } -} - -/* end htimer_api.c */ - -/** @} //APIs Hibernation_Timer - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer_perphl.c deleted file mode 100644 index 64d632649..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/htimer/htimer_perphl.c +++ /dev/null @@ -1,93 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/12/17 01:09:00 $ -$Author: snakka $ -Last Change: Updated for peripheral functions prefix p_ -******************************************************************************/ -/** @file btimer_perphl.c -* \brief Hibernation Timer Peripheral Source file -* \author jvasanth -* -* This file implements Hibernation Timer Peripheral functions -******************************************************************************/ - -/** @defgroup Hibernation_Timer - * @{ - */ - -#include "common_lib.h" -#include "htimer.h" - -/** Hibernation Timer Instance base addresses */ -static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = { - CEC1302_HTM -}; - -/** Sets hibernation timer preload value - * @param htimer_id Hibernation Timer ID - * @param preload_value - 16-bit preload value - * @note Setting the preload with a non-zero value starts - * the hibernation timer to down count. Setting the preload - * to 0 disables the hibernation counter - */ -void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value) -{ - htmr_inst[htimer_id]->PRELOAD = preload_value; -} - -/** Sets hibernation timer resolution - * @param htimer_id Hibernation Timer ID - * @param resolution_mode 0 - resolution of 30.5us per LSB, - * 1 - resolution of 0.125s per LSB - */ -void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode) -{ - htmr_inst[htimer_id]->CONTROL = resolution_mode; -} - -/** Returns the Hibernation Timer current count value - * @param htimer_id Hibernation Timer ID - * @return 16-bit count value - */ -uint16_t p_htimer_count_get(uint8_t htimer_id) -{ - uint16_t htimer_count; - - htimer_count = htmr_inst[htimer_id]->COUNT; - - return htimer_count; -} - -/*_RB_ Added by RB. */ -uint16_t p_htimer_preload_get(uint8_t htimer_id) -{ - return htmr_inst[htimer_id]->PRELOAD; -} - - -/* end htimer_perphl.c */ - -/** @} //Peripheral Hibernation_Timer - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/interrupt/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/interrupt/interrupt.h deleted file mode 100644 index 2b30af9eb..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/interrupt/interrupt.h +++ /dev/null @@ -1,1176 +0,0 @@ -/**************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -*/ - -/** @defgroup interrupt interrupt - * @{ - */ -/** @file interrupt.h - \brief This is the header file for interrupt.c - This program is designed to allow the other C programs to be able to use this component - - There are entry points for all C wrapper API implementation - -Platform: This is ARC-based component - -Toolset: Metaware IDE(8.5.1) -Reference: smsc_reusable_fw_requirement.doc */ - -/******************************************************************************* - * SMSC version control information (Perforce): - * - * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $ - * REVISION: $Revision: #1 $ - * DATETIME: $DateTime: 2015/12/23 15:37:58 $ - * AUTHOR: $Author: akrishnan $ - * - * Revision history (latest first): - * #xx - *********************************************************************************** - */ - -#ifndef _INTERRUPT_H_ -#define _INTERRUPT_H_ - - -/* public function prototypes */ -void interrupt_block_init(void); -void null_handler(void); - -/* macro for interrupt control */ -/* 16-bit timers interrupt control */ -#define sbit_TIMER0 ( 1UL << 0UL ) -#define sbit_TIMER1 ( 1UL << 1UL ) -#define sbit_TIMER2 ( 1UL << 2UL ) -#define sbit_TIMER3 ( 1UL << 3Ul ) - -#define disable_timer0_irq() mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_timer0_irq() mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_timer0_source() mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE) -#define get_timer0_source() mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE) - -#define disable_timer1_irq() mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_timer1_irq() mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_timer1_source() mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE) -#define get_timer1_source() mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE) - -#define disable_timer2_irq() mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_timer2_irq() mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_timer2_source() mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE) -#define get_timer2_source() mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE) - -#define disable_timer3_irq() mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_timer3_irq() mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_timer3_source() mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE) -#define get_timer3_source() mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE) - - -/* hibernation timers interrupt control */ -#define sbit_HTIMER0 ( 1UL << 20 ) -#define sbit_HTIMER1 b_bit14 - -#define disable_htimer0_irq() mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET) -#define enable_htimer0_irq() mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET) -#define clear_htimer0_source() mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE) -#define get_htimer0_source() mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE) - -#define disable_htimer1_irq() mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_htimer1_irq() mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_htimer1_source() mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE) -#define get_htimer1_source() mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE) - -/* RTC interrupt control */ -#define b_bit18 (1 << 18) -#define b_bit19 (1 << 19) -#define sbit_RTC_INT b_bit18 -#define disable_rtc_irq() mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) -#define enable_rtc_irq() mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) -#define clear_rtc_irq_source() mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) -#define get_rtc_irq_source() mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) -/* RTC alarm interrupt control */ -#define sbit_RTC_ALM_INT b_bit19 -#define disable_rtc_alm_irq() mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) -#define enable_rtc_alm_irq() mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) -#define clear_rtc_irq_alm_source() mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) -#define get_rtc_irq_alm_source() mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) - -/* week timer interrupt control */ -#define sbit_WKTIMER b_bit7 - -#define disable_wktimer_irq() mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_wktimer_irq() mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_wktimer_source() mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE) -#define get_wktimer_source() mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE) - - -/* scan matrix interrupt control */ -#define sbit_SCANNER b_bit16 -#define disable_scanner_irq() mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET) -#define enable_scanner_irq() mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET) -#define clear_scanner_source() mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE) -#define get_scanner_source() mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE) - - -/* PS2 interrupt control */ -/* PS2 activity interrupt */ -#define sbit_PS2_ACT_0 b_bit13 -#define sbit_PS2_ACT_1 b_bit14 -#define sbit_PS2_ACT_2 b_bit15 -/* PS2 wakeup interrupt: detect start bit */ -#define sbit_PS2_WK_0A b_bit17 -#define sbit_PS2_WK_1B b_bit20 -#define sbit_PS2_WK_2 b_bit21 - -/* PS2 activity interrupt control */ -#define disable_ps2_act_0_irq() mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET) -#define enable_ps2_act_0_irq() mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET) -#define clear_ps2_act_0_source() mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE) -#define get_ps2_act_0_source() mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE) - -#define disable_ps2_act_1_irq() mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET) -#define enable_ps2_act_1_irq() mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET) -#define clear_ps2_act_1_source() mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE) -#define get_ps2_act_1_source() mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE) - -#define disable_ps2_act_2_irq() mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET) -#define enable_ps2_act_2_irq() mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET) -#define clear_ps2_act_2_source() mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE) -#define get_ps2_act_2_source() mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE) - -/* PS2 wakeup interrupt control */ -#define disable_ps2_wk_0_irq() mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET) -#define enable_ps2_wk_0_irq() mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET) -#define clear_ps2_wk_0_source() mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE) -#define get_ps2_wk_0_source() mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE) - -#define disable_ps2_wk_1_irq() mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET) -#define enable_ps2_wk_1_irq() mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET) -#define clear_ps2_wk_1_source() mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE) -#define get_ps2_wk_1_source() mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE) - -#define disable_ps2_wk_2_irq() mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET) -#define enable_ps2_wk_2_irq() mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET) -#define clear_ps2_wk_2_source() mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE) -#define get_ps2_wk_2_source() mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE) - - -/* ICT interrupt control */ -/* capture 0~5 interrupt */ -#define sbit_ICT_CAPTURE0 b_bit17 -#define sbit_ICT_CAPTURE1 b_bit18 -#define sbit_ICT_CAPTURE2 b_bit19 -#define sbit_ICT_CAPTURE3 b_bit20 -#define sbit_ICT_CAPTURE4 b_bit21 -#define sbit_ICT_CAPTURE5 b_bit22 - -/* capture 0 interrupt control */ -#define disable_capture0_irq() mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET) -#define enable_capture0_irq() mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET) -#define clear_capture0_source() mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE) -#define get_capture0_source() mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE) - - -/* SMBus interrupt control */ - - -/* GPIO interrupt control */ - - -/* BC link interrupt control */ -/* bclink A~D interrupt */ -#define sbit_BCLINK_A_BUSY b_bit0 -#define sbit_BCLINK_A_ERR b_bit1 -#define sbit_BCLINK_A_INT b_bit2 -#define sbit_BCLINK_B_BUSY b_bit3 -#define sbit_BCLINK_B_ERR b_bit4 -#define sbit_BCLINK_B_INT b_bit5 -#define sbit_BCLINK_C_BUSY b_bit6 -#define sbit_BCLINK_C_ERR b_bit7 -#define sbit_BCLINK_C_INT b_bit8 -#define sbit_BCLINK_D_BUSY b_bit9 -#define sbit_BCLINK_D_ERR b_bit10 -#define sbit_BCLINK_D_INT b_bit11 - -/* bclink B interrupt control */ -#define disable_bclink_b_busy_irq() mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET) -#define enable_bclink_b_busy_irq() mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET) -#define clear_bclink_b_busy_source() mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE) -#define get_bclink_b_busy_source() mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE) - -#define disable_bclink_b_err_irq() mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET) -#define enable_bclink_b_err_irq() mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET) -#define clear_bclink_b_err_source() mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE) -#define get_bclink_b_err_source() mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE) - -#define disable_bclink_b_int_irq() mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET) -#define enable_bclink_b_int_irq() mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET) -#define clear_bclink_b_int_source() mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE) -#define get_bclink_b_int_source() mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE) - -/* UART interrupt control */ -#define sbit_UART_INT b_bit0 - -#define disable_uart_irq() mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET) -#define enable_uart_irq() mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET) -#define clear_uart_irq_source() mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE) -#define get_uart_irq_source() mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE) - -// GIRQ IDs for EC Interrupt Aggregator -enum MEC_GIRQ_IDS -{ - MEC_GIRQ08_ID = 0, - MEC_GIRQ09_ID, - MEC_GIRQ10_ID, - MEC_GIRQ11_ID, - MEC_GIRQ12_ID, - MEC_GIRQ13_ID, - MEC_GIRQ14_ID, - MEC_GIRQ15_ID, - MEC_GIRQ16_ID, - MEC_GIRQ17_ID, - MEC_GIRQ18_ID, - MEC_GIRQ19_ID, - MEC_GIRQ20_ID, - MEC_GIRQ21_ID, - MEC_GIRQ22_ID, - MEC_GIRQ23_ID, - MEC_GIRQ_ID_MAX -}; - -//Bitmask of GIRQ in ECIA Block Registers -#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8)) -#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) -#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) -#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) -#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) -#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) -#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) -#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) -#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) -#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) -#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) -#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) -#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) -#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) -#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) -#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) - -#define INTERRUPT_MODE_ALL_AGGREGATED (0u) -#define INTERRUPT_MODE_DIRECT (1u) - -// Bit map of GIRQs whose sources can be directly connected to the NVIC -// GIRQs 12 - 18, 23 -#define ECIA_GIRQ_DIRECT_BITMAP (0x0087F000ul) - -/* - * n = b[7:0] = zero-based direct mapped NVIC ID - * m = b[15:8] = zero-based aggregated NVIC ID - * a = b[23:16] = block Aggregator register block ID - * b = b[31:24] = block bit position in Aggregator registers -*/ -#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \ - (((uint32_t)(m)&0xFFul)<<8u) + \ - ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \ - (((uint32_t)(b)&0x1Ful)<<24)) - -#define ECIA_NVIC_ID_BITPOS (0u) -#define ECIA_IA_NVIC_ID_BITPOS (8u) -#define ECIA_GIRQ_ID_BITPOS (16u) -#define ECIA_GIRQ_BIT_BITPOS (24u) - -// -// GIRQ08 -// -#define GPIO_0140_IROUTE IROUTE(0,8,57,57) -#define GPIO_0141_IROUTE IROUTE(1,8,57,57) -#define GPIO_0142_IROUTE IROUTE(2,8,57,57) -#define GPIO_0143_IROUTE IROUTE(3,8,57,57) -#define GPIO_0144_IROUTE IROUTE(4,8,57,57) -#define GPIO_0145_IROUTE IROUTE(5,8,57,57) -#define GPIO_0147_IROUTE IROUTE(7,8,57,57) -// -#define GPIO_0150_IROUTE IROUTE(8,8,57,57) -#define GPIO_0151_IROUTE IROUTE(9,8,57,57) -#define GPIO_0152_IROUTE IROUTE(10,8,57,57) -#define GPIO_0153_IROUTE IROUTE(11,8,57,57) -#define GPIO_0154_IROUTE IROUTE(12,8,57,57) -#define GPIO_0155_IROUTE IROUTE(13,8,57,57) -#define GPIO_0156_IROUTE IROUTE(14,8,57,57) -#define GPIO_0157_IROUTE IROUTE(15,8,57,57) -// -#define GPIO_0160_IROUTE IROUTE(16,8,57,57) -#define GPIO_0161_IROUTE IROUTE(17,8,57,57) -#define GPIO_0162_IROUTE IROUTE(18,8,57,57) -#define GPIO_0163_IROUTE IROUTE(19,8,57,57) -#define GPIO_0164_IROUTE IROUTE(20,8,57,57) -#define GPIO_0165_IROUTE IROUTE(21,8,57,57) -#define GPIO_0166_IROUTE IROUTE(22,8,57,57) -#define GPIO_0167_IROUTE IROUTE(23,8,57,57) - -// -// GIRQ09 -// -#define GPIO_0100_IROUTE IROUTE(0,9,58,58) -#define GPIO_0101_IROUTE IROUTE(1,9,58,58) -#define GPIO_0102_IROUTE IROUTE(2,9,58,58) -#define GPIO_0103_IROUTE IROUTE(3,9,58,58) -#define GPIO_0104_IROUTE IROUTE(4,9,58,58) -#define GPIO_0105_IROUTE IROUTE(5,9,58,58) -#define GPIO_0105_IROUTE IROUTE(5,9,58,58) -#define GPIO_0107_IROUTE IROUTE(7,9,58,58) -// -#define GPIO_0110_IROUTE IROUTE(8,9,58,58) -#define GPIO_0111_IROUTE IROUTE(9,9,58,58) -#define GPIO_0112_IROUTE IROUTE(10,9,58,58) -#define GPIO_0113_IROUTE IROUTE(11,9,58,58) -#define GPIO_0114_IROUTE IROUTE(12,9,58,58) -#define GPIO_0115_IROUTE IROUTE(13,9,58,58) -#define GPIO_0116_IROUTE IROUTE(14,9,58,58) -#define GPIO_0117_IROUTE IROUTE(15,9,58,58) -// -#define GPIO_0120_IROUTE IROUTE(16,9,58,58) -#define GPIO_0121_IROUTE IROUTE(17,9,58,58) -#define GPIO_0122_IROUTE IROUTE(18,9,58,58) -#define GPIO_0124_IROUTE IROUTE(20,9,58,58) -#define GPIO_0125_IROUTE IROUTE(21,9,58,58) -#define GPIO_0126_IROUTE IROUTE(22,9,58,58) -#define GPIO_0127_IROUTE IROUTE(23,9,58,58) -// -#define GPIO_0130_IROUTE IROUTE(24,9,58,58) -#define GPIO_0131_IROUTE IROUTE(25,9,58,58) -#define GPIO_0132_IROUTE IROUTE(26,9,58,58) -#define GPIO_0133_IROUTE IROUTE(27,9,58,58) -#define GPIO_0134_IROUTE IROUTE(28,9,58,58) -#define GPIO_0135_IROUTE IROUTE(29,9,58,58) -#define GPIO_0136_IROUTE IROUTE(30,9,58,58) - -// -// GIRQ10 -// -#define GPIO_0040_IROUTE IROUTE(0,10,59,59) -#define GPIO_0041_IROUTE IROUTE(1,10,59,59) -#define GPIO_0042_IROUTE IROUTE(2,10,59,59) -#define GPIO_0043_IROUTE IROUTE(3,10,59,59) -#define GPIO_0044_IROUTE IROUTE(4,10,59,59) -#define GPIO_0045_IROUTE IROUTE(5,10,59,59) -#define GPIO_0045_IROUTE IROUTE(5,10,59,59) -#define GPIO_0047_IROUTE IROUTE(7,10,59,59) -// -#define GPIO_0050_IROUTE IROUTE(8,10,59,59) -#define GPIO_0051_IROUTE IROUTE(9,10,59,59) -#define GPIO_0052_IROUTE IROUTE(10,10,59,59) -#define GPIO_0053_IROUTE IROUTE(11,10,59,59) -#define GPIO_0054_IROUTE IROUTE(12,10,59,59) -#define GPIO_0055_IROUTE IROUTE(13,10,59,59) -#define GPIO_0056_IROUTE IROUTE(14,10,59,59) -#define GPIO_0057_IROUTE IROUTE(15,10,59,59) -// -#define GPIO_0060_IROUTE IROUTE(16,10,59,59) -#define GPIO_0061_IROUTE IROUTE(17,10,59,59) -#define GPIO_0062_IROUTE IROUTE(18,10,59,59) -#define GPIO_0063_IROUTE IROUTE(19,10,59,59) -#define GPIO_0064_IROUTE IROUTE(20,10,59,59) -#define GPIO_0065_IROUTE IROUTE(21,10,59,59) -#define GPIO_0066_IROUTE IROUTE(22,10,59,59) -#define GPIO_0067_IROUTE IROUTE(23,10,59,59) -// -#define GPIO_0070_IROUTE IROUTE(24,10,59,59) -#define GPIO_0071_IROUTE IROUTE(25,10,59,59) -#define GPIO_0072_IROUTE IROUTE(26,10,59,59) -#define GPIO_0073_IROUTE IROUTE(27,10,59,59) -#define GPIO_0074_IROUTE IROUTE(28,10,59,59) -#define GPIO_0075_IROUTE IROUTE(29,10,59,59) -#define GPIO_0076_IROUTE IROUTE(30,10,59,59) - -// -// GIRQ11 -// -#define GPIO_0000_IROUTE IROUTE(0,11,60,60) -#define GPIO_0001_IROUTE IROUTE(1,11,60,60) -#define GPIO_0002_IROUTE IROUTE(2,11,60,60) -#define GPIO_0003_IROUTE IROUTE(3,11,60,60) -#define GPIO_0004_IROUTE IROUTE(4,11,60,60) -#define GPIO_0005_IROUTE IROUTE(5,11,60,60) -#define GPIO_0006_IROUTE IROUTE(6,11,60,60) -#define GPIO_0007_IROUTE IROUTE(7,11,60,60) -// -#define GPIO_0010_IROUTE IROUTE(8,11,60,60) -#define GPIO_0011_IROUTE IROUTE(9,11,60,60) -#define GPIO_0012_IROUTE IROUTE(10,11,60,60) -#define GPIO_0013_IROUTE IROUTE(11,11,60,60) -#define GPIO_0014_IROUTE IROUTE(12,11,60,60) -#define GPIO_0015_IROUTE IROUTE(13,11,60,60) -#define GPIO_0016_IROUTE IROUTE(14,11,60,60) -#define GPIO_0017_IROUTE IROUTE(15,11,60,60) -// -#define GPIO_0020_IROUTE IROUTE(16,11,60,60) -#define GPIO_0021_IROUTE IROUTE(17,11,60,60) -#define GPIO_0022_IROUTE IROUTE(18,11,60,60) -#define GPIO_0023_IROUTE IROUTE(19,11,60,60) -#define GPIO_0024_IROUTE IROUTE(20,11,60,60) -#define GPIO_0025_IROUTE IROUTE(21,11,60,60) -#define GPIO_0026_IROUTE IROUTE(22,11,60,60) -#define GPIO_0027_IROUTE IROUTE(23,11,60,60) -// -#define GPIO_0030_IROUTE IROUTE(24,11,60,60) -#define GPIO_0031_IROUTE IROUTE(25,11,60,60) -#define GPIO_0032_IROUTE IROUTE(26,11,60,60) -#define GPIO_0033_IROUTE IROUTE(27,11,60,60) -#define GPIO_0034_IROUTE IROUTE(28,11,60,60) -#define GPIO_0035_IROUTE IROUTE(29,11,60,60) -#define GPIO_0036_IROUTE IROUTE(30,11,60,60) - -// -// GIRQ12 -// -#define SMB0_IROUTE IROUTE(0,12,61,0) -#define SMB1_IROUTE IROUTE(1,12,61,1) -#define SMB2_IROUTE IROUTE(2,12,61,2) -#define SMB3_IROUTE IROUTE(3,12,61,3) -// SMB wakes have no direct connection to NVIC, always aggregated -#define SMB0_WAKE_IROUTE IROUTE(4,12,61,61) -#define SMB1_WAKE_IROUTE IROUTE(5,12,61,61) -#define SMB2_WAKE_IROUTE IROUTE(6,12,61,61) -#define SMB3_WAKE_IROUTE IROUTE(7,12,61,61) -#define SMB4_WAKE_IROUTE IROUTE(8,12,61,61) - -// -// GIRQ13 -// -#define DMA0_IROUTE IROUTE(16,13,62,4) -#define DMA1_IROUTE IROUTE(17,13,62,5) -#define DMA2_IROUTE IROUTE(18,13,62,6) -#define DMA3_IROUTE IROUTE(19,13,62,7) -#define DMA4_IROUTE IROUTE(20,13,62,8) -#define DMA5_IROUTE IROUTE(21,13,62,9) -#define DMA6_IROUTE IROUTE(22,13,62,10) -#define DMA7_IROUTE IROUTE(23,13,62,11) -#define DMA8_IROUTE IROUTE(24,13,62,81) -#define DMA9_IROUTE IROUTE(25,13,62,82) -#define DMA10_IROUTE IROUTE(26,13,62,83) -#define DMA11_IROUTE IROUTE(27,13,62,84) - -// -// GIRQ14 -// -#define LPC_BERR_IROUTE IROUTE(2,14,63,12) - -// -// GIRQ15 -// -#define UART0_IROUTE IROUTE(0,15,64,13) -#define EMI0_IROUTE IROUTE(2,15,64,14) -#define ACPI_EC0_IBF_IROUTE IROUTE(6,15,64,15) -#define ACPI_EC0_OBF_IROUTE IROUTE(7,15,64,16) -#define ACPI_EC1_IBF_IROUTE IROUTE(8,15,64,17) -#define ACPI_EC1_OBF_IROUTE IROUTE(9,15,64,18) -#define ACPI_PM1_CTL_IROUTE IROUTE(10,15,64,19) -#define ACPI_PM1_EN_IROUTE IROUTE(11,15,64,20) -#define ACPI_PM1_STS_IROUTE IROUTE(12,15,64,21) -#define EM8042_OBF_IROUTE IROUTE(13,15,64,22) -#define EM8042_IBF_IROUTE IROUTE(14,15,64,23) -#define MBOX_IROUTE IROUTE(15,15,64,24) -#define MBOX_DATA_IROUTE IROUTE(16,15,64,40) - -// -// GIRQ16 -// -#define PECI_IROUTE IROUTE(3,16,65,25) - -// -// GIRQ17 -// -#define TACH0_IROUTE IROUTE(0,17,66,26) -#define TACH1_IROUTE IROUTE(1,17,66,27) -#define PS2_0_WAKE_IROUTE IROUTE(2,17,66,66) -#define PS2_1_WAKE_IROUTE IROUTE(3,17,66,66) -#define PS2_2_WAKE_IROUTE IROUTE(4,17,66,66) -#define PS2_3_WAKE_IROUTE IROUTE(5,17,66,66) -#define BC_WAKE_IROUTE IROUTE(6,17,66,66) -#define ADC_SNGL_IROUTE IROUTE(10,17,66,28) -#define ADC_RPT_IROUTE IROUTE(11,17,66,29) -#define ADC2PWM1_IROUTE IROUTE(12,17,66,30) -#define ADC2PWM2_IROUTE IROUTE(13,17,66,31) -#define PS2_0_IROUTE IROUTE(14,17,66,32) -#define PS2_1_IROUTE IROUTE(15,17,66,33) -#define PS2_2_IROUTE IROUTE(16,17,66,34) -#define PS2_3_IROUTE IROUTE(17,17,66,35) -#define RTC_IROUTE IROUTE(18,17,66,91) -#define RTC_ALARM_IROUTE IROUTE(19,17,66,92) -#define HTIMER_IROUTE IROUTE(20,17,66,38) -#define KSC_IROUTE IROUTE(21,17,66,39) -#define KSC_WAKE_IROUTE IROUTE(22,17,66,66) -#define RPM_STALL_IROUTE IROUTE(23,17,66,41) -#define RPM_SPIN_IROUTE IROUTE(24,17,66,42) -#define PFR_IROUTE IROUTE(25,17,66,43) -#define LED0_IROUTE IROUTE(26,17,66,44) -#define LED1_IROUTE IROUTE(27,17,66,45) -#define LED2_IROUTE IROUTE(28,17,66,46) -#define BCM_ERR_IROUTE IROUTE(29,17,66,47) -#define BCM_BUSY_IROUTE IROUTE(30,17,66,48) - -// -// GIRQ18 -// -#define SPI0_TX_IROUTE IROUTE(0,18,67,36) -#define SPI0_RX_IROUTE IROUTE(1,18,67,37) -#define SPI1_TX_IROUTE IROUTE(2,18,67,55) -#define SPI1_RX_IROUTE IROUTE(3,18,67,56) -#define LED3_IROUTE IROUTE(4,18,67,85) -#define PKE_ERR_IROUTE IROUTE(5,18,67,86) -#define PKE_END_IROUTE IROUTE(6,18,67,87) -#define NDRNG_IROUTE IROUTE(7,18,67,88) -#define AES_IROUTE IROUTE(8,18,67,89) -#define HASH_IROUTE IROUTE(9,18,67,90) - -// -// GIRQ19, Aggregated only -// -#define LRESET_IROUTE IROUTE(0,19,68,68) -#define VCC_PWRGD_IROUTE IROUTE(1,19,68,68) - -// -// GIRQ20, Aggregated only -// -#define GPIO_0200_IROUTE IROUTE(0,20,69,69) -#define GPIO_0201_IROUTE IROUTE(1,20,69,69) -#define GPIO_0202_IROUTE IROUTE(2,20,69,69) -#define GPIO_0203_IROUTE IROUTE(3,20,69,69) -#define GPIO_0204_IROUTE IROUTE(4,20,69,69) -#define GPIO_0206_IROUTE IROUTE(6,20,69,69) -// -#define GPIO_0210_IROUTE IROUTE(8,20,69,69) -#define GPIO_0211_IROUTE IROUTE(9,20,69,69) -#define GPIO_0212_IROUTE IROUTE(10,20,69,69) -#define GPIO_0213_IROUTE IROUTE(11,20,69,69) - -// -// GIRQ21 -// -// No sources - -// -// GIRQ22 -// -// No sources - -// -// GIRQ23 -// -#define BTMR0_IROUTE IROUTE(0,23,72,49) -#define BTMR1_IROUTE IROUTE(1,23,72,50) -#define BTMR2_IROUTE IROUTE(2,23,72,51) -#define BTMR3_IROUTE IROUTE(3,23,72,52) -#define BTMR4_IROUTE IROUTE(4,23,72,53) -#define BTMR5_IROUTE IROUTE(5,23,72,54) - -// GIRQ08 Bit Positions -#define GIRQ08_GPIO_0140_BITPOS (0) -#define GIRQ08_GPIO_0141_BITPOS (1) -#define GIRQ08_GPIO_0142_BITPOS (2) -#define GIRQ08_GPIO_0143_BITPOS (3) -#define GIRQ08_GPIO_0144_BITPOS (4) -#define GIRQ08_GPIO_0145_BITPOS (5) -//#define GIRQ08_GPIO_0146_BITPOS (6) RESERVED -#define GIRQ08_GPIO_0147_BITPOS (7) -// -#define GIRQ08_GPIO_0150_BITPOS (8) -#define GIRQ08_GPIO_0151_BITPOS (9) -#define GIRQ08_GPIO_0152_BITPOS (10) -#define GIRQ08_GPIO_0153_BITPOS (11) -#define GIRQ08_GPIO_0154_BITPOS (12) -#define GIRQ08_GPIO_0155_BITPOS (13) -#define GIRQ08_GPIO_0156_BITPOS (14) -#define GIRQ08_GPIO_0157_BITPOS (15) -// -#define GIRQ08_GPIO_0160_BITPOS (16) -#define GIRQ08_GPIO_0161_BITPOS (17) -#define GIRQ08_GPIO_0162_BITPOS (18) -#define GIRQ08_GPIO_0163_BITPOS (19) -#define GIRQ08_GPIO_0164_BITPOS (20) -#define GIRQ08_GPIO_0165_BITPOS (21) -#define GIRQ08_GPIO_0166_BITPOS (22) -#define GIRQ08_GPIO_0167_BITPOS (23) -// -#define GIRQ08_MASK (0x00FFFFBFul) -#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul) -// - -// GIRQ09 Bit Positions -#define GIRQ09_GPIO_0100_BITPOS (0) -#define GIRQ09_GPIO_0101_BITPOS (1) -#define GIRQ09_GPIO_0102_BITPOS (2) -#define GIRQ09_GPIO_0103_BITPOS (3) -#define GIRQ09_GPIO_0104_BITPOS (4) -#define GIRQ09_GPIO_0105_BITPOS (5) -#define GIRQ09_GPIO_0106_BITPOS (6) -#define GIRQ09_GPIO_0107_BITPOS (7) -// -#define GIRQ09_GPIO_0110_BITPOS (8) -#define GIRQ09_GPIO_0111_BITPOS (9) -#define GIRQ09_GPIO_0112_BITPOS (10) -#define GIRQ09_GPIO_0113_BITPOS (11) -#define GIRQ09_GPIO_0114_BITPOS (12) -#define GIRQ09_GPIO_0115_BITPOS (13) -#define GIRQ09_GPIO_0116_BITPOS (14) -#define GIRQ09_GPIO_0117_BITPOS (15) -// -#define GIRQ09_GPIO_0120_BITPOS (16) -#define GIRQ09_GPIO_0121_BITPOS (17) -#define GIRQ09_GPIO_0122_BITPOS (18) -//#define GIRQ09_GPIO_0123_BITPOS (19) RESERVED -#define GIRQ09_GPIO_0124_BITPOS (20) -#define GIRQ09_GPIO_0125_BITPOS (21) -#define GIRQ09_GPIO_0126_BITPOS (22) -#define GIRQ09_GPIO_0127_BITPOS (23) -// -#define GIRQ09_GPIO_0130_BITPOS (24) -#define GIRQ09_GPIO_0131_BITPOS (25) -#define GIRQ09_GPIO_0132_BITPOS (26) -#define GIRQ09_GPIO_0133_BITPOS (27) -#define GIRQ09_GPIO_0134_BITPOS (28) -#define GIRQ09_GPIO_0135_BITPOS (29) -#define GIRQ09_GPIO_0136_BITPOS (30) -//#define GIRQ09_GPIO_0137_BITPOS (31) RESERVED -// -#define GIRQ09_MASK (0x7FF7FFFFul) -#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul) -// - -// GIRQ10 Bit Positions -#define GIRQ10_GPIO_0040_BITPOS (0) -#define GIRQ10_GPIO_0041_BITPOS (1) -#define GIRQ10_GPIO_0042_BITPOS (2) -#define GIRQ10_GPIO_0043_BITPOS (3) -#define GIRQ10_GPIO_0044_BITPOS (4) -#define GIRQ10_GPIO_0045_BITPOS (5) -#define GIRQ10_GPIO_0046_BITPOS (6) -#define GIRQ10_GPIO_0047_BITPOS (7) -// -#define GIRQ10_GPIO_0050_BITPOS (8) -#define GIRQ10_GPIO_0051_BITPOS (9) -#define GIRQ10_GPIO_0052_BITPOS (10) -#define GIRQ10_GPIO_0053_BITPOS (11) -#define GIRQ10_GPIO_0054_BITPOS (12) -#define GIRQ10_GPIO_0055_BITPOS (13) -#define GIRQ10_GPIO_0056_BITPOS (14) -#define GIRQ10_GPIO_0057_BITPOS (15) -// -#define GIRQ10_GPIO_0060_BITPOS (16) -#define GIRQ10_GPIO_0061_BITPOS (17) -#define GIRQ10_GPIO_0062_BITPOS (18) -#define GIRQ10_GPIO_0063_BITPOS (19) -#define GIRQ10_GPIO_0064_BITPOS (20) -#define GIRQ10_GPIO_0065_BITPOS (21) -#define GIRQ10_GPIO_0066_BITPOS (22) -#define GIRQ10_GPIO_0067_BITPOS (23) -// -#define GIRQ10_GPIO_0070_BITPOS (24) -#define GIRQ10_GPIO_0071_BITPOS (25) -#define GIRQ10_GPIO_0072_BITPOS (26) -#define GIRQ10_GPIO_0073_BITPOS (27) -#define GIRQ10_GPIO_0074_BITPOS (28) -#define GIRQ10_GPIO_0075_BITPOS (29) -#define GIRQ10_GPIO_0076_BITPOS (30) -//#define GIRQ10_GPIO_0077_BITPOS (31) RESERVED -// -#define GIRQ10_MASK (0x7FFFFFFFul) -#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul) -// - -// GIRQ11 Bit Positions -#define GIRQ11_GPIO_0000_BITPOS (0) -#define GIRQ11_GPIO_0001_BITPOS (1) -#define GIRQ11_GPIO_0002_BITPOS (2) -#define GIRQ11_GPIO_0003_BITPOS (3) -#define GIRQ11_GPIO_0004_BITPOS (4) -#define GIRQ11_GPIO_0005_BITPOS (5) -#define GIRQ11_GPIO_0006_BITPOS (6) -#define GIRQ11_GPIO_0007_BITPOS (7) -// -#define GIRQ11_GPIO_0010_BITPOS (8) -#define GIRQ11_GPIO_0011_BITPOS (9) -#define GIRQ11_GPIO_0012_BITPOS (10) -#define GIRQ11_GPIO_0013_BITPOS (11) -#define GIRQ11_GPIO_0014_BITPOS (12) -#define GIRQ11_GPIO_0015_BITPOS (13) -#define GIRQ11_GPIO_0016_BITPOS (14) -#define GIRQ11_GPIO_0017_BITPOS (15) -// -#define GIRQ11_GPIO_0020_BITPOS (16) -#define GIRQ11_GPIO_0021_BITPOS (17) -#define GIRQ11_GPIO_0022_BITPOS (18) -#define GIRQ11_GPIO_0023_BITPOS (19) -#define GIRQ11_GPIO_0024_BITPOS (20) -#define GIRQ11_GPIO_0025_BITPOS (21) -#define GIRQ11_GPIO_0026_BITPOS (22) -#define GIRQ11_GPIO_0027_BITPOS (23) -// -#define GIRQ11_GPIO_0030_BITPOS (24) -#define GIRQ11_GPIO_0031_BITPOS (25) -#define GIRQ11_GPIO_0032_BITPOS (26) -#define GIRQ11_GPIO_0033_BITPOS (27) -#define GIRQ11_GPIO_0034_BITPOS (28) -#define GIRQ11_GPIO_0035_BITPOS (29) -#define GIRQ11_GPIO_0036_BITPOS (30) -//#define GIRQ11_GPIO_0037_BITPOS (31) RESERVED -// -#define GIRQ11_MASK (0x7FFFFFFFul) -#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul) -// - -// GIRQ12 Bit Positions -#define GIRQ12_SMBUS0_BITPOS (0) -#define GIRQ12_SMBUS1_BITPOS (1) -#define GIRQ12_SMBUS2_BITPOS (2) -#define GIRQ12_SMBUS3_BITPOS (3) -#define GIRQ12_SMBUS0_WAKE_BITPOS (4) -#define GIRQ12_SMBUS1_WAKE_BITPOS (5) -#define GIRQ12_SMBUS2_WAKE_BITPOS (6) -#define GIRQ12_SMBUS3_WAKE_BITPOS (7) -#define GIRQ12_SMBUS4_WAKE_BITPOS (8) -// RESERVED bits[31:9] -#define GIRQ12_MASK (0x01FFul) -#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul) -// - -// GIRQ13 Bit Positions -#define GIRQ13_DMA0_BITPOS (16) -#define GIRQ13_DMA1_BITPOS (17) -#define GIRQ13_DMA2_BITPOS (18) -#define GIRQ13_DMA3_BITPOS (19) -#define GIRQ13_DMA4_BITPOS (20) -#define GIRQ13_DMA5_BITPOS (21) -#define GIRQ13_DMA6_BITPOS (22) -#define GIRQ13_DMA7_BITPOS (23) -#define GIRQ13_DMA8_BITPOS (24) -#define GIRQ13_DMA9_BITPOS (25) -#define GIRQ13_DMA10_BITPOS (26) -#define GIRQ13_DMA11_BITPOS (27) -// -#define GIRQ13_MASK (0x0FFF0000ul) -#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul) -// - -// GIRQ14 Bit Positions -#define GIRQ14_LPC_BITPOS (2) -// -#define GIRQ14_MASK (0x04ul) -#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul) -// - -// GIRQ15 Bit Positions -#define GIRQ15_UART0_BITPOS (0) -#define GIRQ15_IMAP_BITPOS (2) -#define GIRQ15_KBD_K_BITPOS (3) -#define GIRQ15_KBD_M_BITPOS (4) -#define GIRQ15_ACPI0_IBF_BITPOS (6) -#define GIRQ15_ACPI0_OBF_BITPOS (7) -#define GIRQ15_ACPI1_IBF_BITPOS (8) -#define GIRQ15_ACPI1_OBF_BITPOS (9) -#define GIRQ15_ACPI_PM1CTL_BITPOS (10) -#define GIRQ15_ACPI_PM1EN_BITPOS (11) -#define GIRQ15_ACPI_PM1STS_BITPOS (12) -#define GIRQ15_MF8042_OBF_BITPOS (13) -#define GIRQ15_MF8042_IBF_BITPOS (14) -#define GIRQ15_MAILBOX_BITPOS (15) -#define GIRQ15_MAILBOX_DATA_BITPOS (16) -// -#define GIRQ15_MASK (0x01FFDDul) -#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul) -// - -// GIRQ16 Bit Positions -#define GIRQ16_PECI_BITPOS (3) -// -#define GIRQ16_MASK (0x08ul) -#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul) -// - -// GIRQ17 Bit Positions -#define GIRQ17_TACH0_BITPOS (0) -#define GIRQ17_TACH1_BITPOS (1) -#define GIRQ17_PS2_0_WAKE_BITPOS (2) -#define GIRQ17_PS2_1_WAKE_BITPOS (3) -#define GIRQ17_PS2_2_WAKE_BITPOS (4) -#define GIRQ17_PS2_3_WAKE_BITPOS (5) -#define GIRQ17_BC_WAKE_BITPOS (6) -// RESERVED b[9:7] -#define GIRQ17_ADC_INT0_BITPOS (10) -#define GIRQ17_ADC_INT1_BITPOS (11) -#define GIRQ17_V2P_INT0_BITPOS (12) -#define GIRQ17_V2P_INT1_BITPOS (13) -#define GIRQ17_PS2_0_BITPOS (14) -#define GIRQ17_PS2_1_BITPOS (15) -#define GIRQ17_PS2_2_BITPOS (16) -#define GIRQ17_PS2_3_BITPOS (17) -// RESERVED b[19:18] -#define GIRQ17_HIBTMR_BITPOS (20) -#define GIRQ17_KEY_INT_BITPOS (21) -#define GIRQ17_KEY_INT_WAKE_BITPOS (22) -#define GIRQ17_RPM_STALL_BITPOS (23) -#define GIRQ17_RPM_SPIN_BITPOS (24) -#define GIRQ17_VBAT_BITPOS (25) -#define GIRQ17_LED0_BITPOS (26) -#define GIRQ17_LED1_BITPOS (27) -#define GIRQ17_LED2_BITPOS (28) -#define GIRQ17_MBC_ERR_BITPOS (29) -#define GIRQ17_MBC_BUSY_BITPOS (30) -// -#define GIRQ17_MASK (0x7FF3FC7Ful) -#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul) -// - -// GIRQ18 Bit Positions -#define GIRQ18_SPI0_TX_BITPOS (0) -#define GIRQ18_SPI0_RX_BITPOS (1) -#define GIRQ18_SPI1_TX_BITPOS (2) -#define GIRQ18_SPI1_RX_BITPOS (3) -#define GIRQ18_LED3_BITPOS (4) // NVIC 85 -#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86 -#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87 -#define GIRQ18_TRNG_BITPOS (7) // NVIC 88 -#define GIRQ18_AES_BITPOS (8) // NVIC 89 -#define GIRQ18_HASH_BITPOS (9) // NVIC 90 -// -#define GIRQ18_MASK (0x0FFul) -#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul) -// - -// GIRQ19 Bit Positions -#define GIRQ19_LRESET_BITPOS (0) -#define GIRQ19_VCC_PWRGD_BITPOS (1) -// -#define GIRQ19_MASK (0x03ul) -#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul) -// - -// GIRQ20 Bit Positions -#define GIRQ20_GPIO_0200_BITPOS (0) -#define GIRQ20_GPIO_0201_BITPOS (1) -#define GIRQ20_GPIO_0202_BITPOS (2) -#define GIRQ20_GPIO_0203_BITPOS (3) -#define GIRQ20_GPIO_0204_BITPOS (4) -//#define GIRQ20_GPIO_0205_BITPOS (5) -#define GIRQ20_GPIO_0206_BITPOS (6) -//#define GIRQ20_GPIO_0207_BITPOS (7) -// -#define GIRQ20_GPIO_0210_BITPOS (8) -#define GIRQ20_GPIO_0211_BITPOS (9) -#define GIRQ20_GPIO_0212_BITPOS (10) -#define GIRQ20_GPIO_0213_BITPOS (11) -// -#define GIRQ20_MASK (0x0F5Ful) -#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful) -// - -// GIRQ21 Bit Positions -#define GIRQ21_MASK (0x00ul) -#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul) - -// GIRQ22 Bit Positions -#define GIRQ22_MASK (0x00ul) -#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul) - -// GIRQ23 Bit Positions -#define GIRQ23_TMR0_BITPOS (0) -#define GIRQ23_TMR1_BITPOS (1) -#define GIRQ23_TMR2_BITPOS (2) -#define GIRQ23_TMR3_BITPOS (3) -#define GIRQ23_TMR4_BITPOS (4) -#define GIRQ23_TMR5_BITPOS (5) -// -#define GIRQ23_MASK (0x03Ful) -#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul) -// - -/* ------------------------------------------------------------------------------- */ -/* NVIC,ECIA Routing Policy for Direct Mode */ -/* ------------------------------------------------------------------------------- */ -/* In Direct Mode, some interrupts could be configured to be used as aggregated. - * Configuration: - * 1. Always set ECS Interrupt Direct enable bit. - * 2. If GIRQn aggregated set Block Enable bit. - * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs. - * Switching issues: - * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers. - * Also requires set/clear of individual NVIC Enables. - * - * Note: interrupt_is_girq_direct() internal function uses this policy to detect - * if any interrupt is configured as direct or aggregated -*/ - -/** Initialize EC Interrupt Aggregator - * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode - * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated - * This parameter is only applicable in direct mode. - * @note All GPIO's and wake capable sources are always - * aggregated! GPIO's interrupts will still work in direct mode. - * Block wakes are not be routed to the processor in direct - * mode. - * Note2: This function disables and enables global interrupt - */ -void interrupt_init(uint8_t mode, uint32_t girq_bitmask); - -/** Set interrupt routing mode to aggregated or direct. - * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated - * @note In direct mode, one could enable certain GIRQs as aggregated using - * p_interrupt_ecia_block_enable_set function - */ -void interrupt_mode_set(uint8_t mode); - -/** Clears all individual interrupts Enables and Source in ECIA, - * and Clears all NVIC external enables and pending bits - */ -void interrupt_reset(void); - -/** Enables interrupt for a device - * @param dev_iroute - source IROUTING information - * @note This function disables and enables global interrupt - */ -void interrupt_device_enable(uint32_t dev_iroute); - -/** Disables interrupt for a device - * @param dev_iroute - source IROUTING information - * @note This function disables and enables global interrupt - */ -void interrupt_device_disable(uint32_t dev_iroute); - -/* ------------------------------------------------------------------------------- */ -/* ECIA APIs using device IROUTE() as input */ -/* ------------------------------------------------------------------------------- */ - -/** Clear Source in the ECIA for the device - * @param devi - device IROUTING value - */ -void interrupt_device_ecia_source_clear(const uint32_t dev_iroute); - -/** Get the Source bit in the ECIA for the device - * @param devi - device IROUTING value - * @return 0 if source bit not set; else non-zero value - */ -uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute); - -/** Get the Result bit in the ECIA for the device - * @param devi - device IROUTING value - * @return 0 if result bit not set; else non-zero value - */ -uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute); - -/* ------------------------------------------------------------------------------- */ -/* NVIC APIs using device IROUTE() as input */ -/* ------------------------------------------------------------------------------- */ -/* Note that if the device interrupt is aggregated, then these APIs would affect the - * NVIC corresponding to the aggregated GIRQ - */ - -/** Enable/Disable the NVIC (in the NVIC controller) for the device - * @param dev_iroute : source IROUTING information (encoded in a uint32_t) - * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ - * @note Recommended to use interrupt_device_enable, interrupt_device_disable - * to enable/disable interrupts for the device, since those APIs configure ECIA as well - */ -void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag); - -/** Set NVIC priority for specified peripheral interrupt source - * @param dev_iroute - source IROUTING information (encoded in a uint32_t) - * @param nvic_pri - NVIC Priority - * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt - * sources in the GIRQ. - * 2. This function disables and enables global interrupt - */ -void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri); - -/** Return NVIC priority for interrupt source - * @param dev_iroute - source IROUTING information - * @return uint32_t NVIC priority - */ -uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute); - -/** Return NVIC pending for interrupt source - * @param dev_iroute - source IROUTING information - * @return uint8_t 0(not pending), 1 (pending in NVIC) - * - */ -uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute); - -/** Set NVIC pending for interrupt source - * @param dev_iroute - source IROUTING information - */ -void interrupt_device_nvic_pending_set(const uint32_t dev_iroute); - -/** Clears NVIC pending for interrupt source - * @param dev_iroute - source IROUTING information - * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear - * @note This function disables and enables global interrupt - */ -uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute); - -/* ------------------------------------------------------------------------------- */ -/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear * - * and Status Register */ -/* ------------------------------------------------------------------------------- */ - -/** Enable specified GIRQ in ECIA block - * @param girq_id - enum MEC_GIRQ_IDS - */ - void p_interrupt_ecia_block_enable_set(uint8_t girq_id); - - /** Enable GIRQs in ECIA Block - * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block - */ -void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask); - -/** Check if specified GIRQ block enabled or not - * @param girq_id - enum MEC_GIRQ_IDS - * @return retVal - 1 if the particular GIRQ block enabled, else 0 - */ -uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id); - -/** Set all GIRQ block enables */ -void p_interrupt_ecia_block_enable_all_set(void); - -/** Clear specified GIRQ in ECIA Block - * @param girq_id - enum MEC_GIRQ_IDS - */ -void p_interrupt_ecia_block_enable_clr(uint8_t girq_id); - -/** Clear GIRQs in ECIA Block - * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block - */ -void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask); - -/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */ -void p_interrupt_ecia_block_enable_all_clr(void); - - /** Get status of GIRQ in ECIA Block - * @param girq_id - enum MEC_GIRQ_IDS - * @return 0 if status bit not set; else non-zero value - */ -uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id); - -/** Reads the Block IRQ Vector Register - * @return 32-bit value - */ -uint32_t p_interrupt_ecia_block_irq_all_status_get(void); - -/* ---------------------------------------------------------------------------- */ -/* Peripheral Functions - Operations on GIRQx Source, Enable, Result * - * and Enable Registers */ -/* ---------------------------------------------------------------------------- */ - -/** Clear specified interrupt source bit in GIRQx - * @param girq_id - enum MEC_GIRQ_IDS - * @param bitnum -[0, 31] - */ -void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum); - -/** Read the specified interrupt source bit in GIRQx - * @param girq_id - enum MEC_GIRQ_IDS - * @param bitnum -[0, 31] - * @return 0 if source bit not set; else non-zero value - */ -uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum); - -/** Enable the specified interrupt in GIRQx - * girq_id - enum MEC_GIRQ_IDS - * bitnum = [0, 31] - */ -void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum); - -/** Disable the specified interrupt in GIRQx - * girq_id - enum MEC_GIRQ_IDS - * bitnum = [0, 31] - */ -void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum); - -/** Read the status of the specified interrupt in GIRQx - * girq_id - enum MEC_GIRQ_IDS - * bitnum = [0, 31] - * @return 0 if enable bit not set; else non-zero value - */ -uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum); - -/** Read the result bit of the interrupt in GIRQx - * @param girq_id - enum MEC_GIRQ_IDS - * @param bitnum -[0, 31] - * @return 0 if enable bit not set; else non-zero value - */ -uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum); - -/* ------------------------------------------------------------------------------- */ -/* Peripheral Function - Operations on all GIRQs */ -/* ------------------------------------------------------------------------------- */ - -/** Clear all aggregator GIRQn status registers */ -void p_interrupt_ecia_girqs_source_reset(void); - -/** Clear all aggregator GIRQn enables */ - void p_interrupt_ecia_girqs_enable_reset(void); - -/* ------------------------------------------------------------------------------- */ -/* Peripheral Function - Function to set interrupt control */ -/* ------------------------------------------------------------------------------- */ - -/** Set interrupt control - * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled - */ - void p_interrupt_control_set(uint8_t nvic_en_flag); - - /** Read interrupt control - * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled - */ -uint8_t p_interrupt_control_get(void); - -/* ------------------------------------------------------------------------------- */ -/* Peripheral Functions - NVIC */ -/* ------------------------------------------------------------------------------- */ - -/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller - * @param nvic_num : NVIC number (see enum IRQn_Type) - * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ - * @note Application should perform this operation - */ - void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag); - - /** ecia_nvic_clr_en - Clear all NVIC external enables */ -void p_interrupt_nvic_extEnables_clr(void); - -/** Clear all NVIC external enables and pending bits */ -void p_interrupt_nvic_enpend_clr(void); - -/** Set NVIC external priorities to POR value */ -void p_interrupt_nvic_priorities_default_set(void); - -/** Set NVIC external priorities to specified priority (0 - 7) - * @param zero-based 3-bit priority value: 0=highest, 7=lowest. - * @note NVIC highest priority is the value 0, lowest is all 1's. - * Each external interrupt has an 8-bit register and the priority - * is left justified in the registers. MECxxx implements 8 priority - * levels or bits [7:5] in the register. Lowest priority = 0xE0 - */ -void p_interrupt_nvic_priorities_set(uint8_t new_pri); - -#endif /*_INTERRUPT_H_*/ - -/** @} - */ - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr.h deleted file mode 100644 index 10710ead3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr.h +++ /dev/null @@ -1,462 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/11/24 06:28:28 $ -$Author: amohandas $ -Last Change: Updated for tabs -******************************************************************************/ -/** @file pcr.h -* \brief Power, Clocks, and Resets Header file -* \author jvasanth -* -* This file is the PCR header file -******************************************************************************/ - -/** @defgroup PCR - * @{ - */ - -#ifndef _PCR_H -#define _PCR_H - - -/******************************************************************************/ -/** PCR Register IDS - *******************************************************************************/ -enum _PCR_REGSET_ID_ -{ - PCR_REG_CHIP_SLEEP_ENABLE =0, - PCR_REG_CHIP_CLK_REQD_STS, - PCR_REG_EC_SLEEP_ENABLE, - PCR_REG_EC_CLK_REQD_STS, - PCR_REG_HOST_SLEEP_ENABLE, - PCR_REG_HOST_CLK_REQD_STS, - PCR_REG_SYSTEM_SLEEP_CTRL, - PCR_REG_PROCESSOR_CLK_CTRL = 8, - PCR_REG_EC_SLEEP_ENABLE_2, - PCR_REG_EC_CLK_REQD_STS_2, - PCR_REG_SLOW_CLK_CTRL, - PCR_REG_OSCILLATOR_ID, - PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS, - PCR_REG_CHIP_RESET_ENABLE, - PCR_REG_HOST_RESET_ENABLE, - PCR_REG_EC_RESET_ENABLE, - PCR_REG_EC_RESET_ENABLE_2, - PCR_REG_PWR_RESET_CTRL -}; -/* ---------------------------------------------------------------------- */ - -// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable -//PCR register group 0 - CHIP -#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \ - (((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \ - (((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u)) - -//PCR register group 1 - EC -#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \ - (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \ - (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u)) - -//PCR register group 2 - HOST -#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \ - (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \ - (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u)) - -//PCR register group 3 - EC 2 -#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \ - (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \ - (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u)) - - -//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions -#define PCR1_EC_INT_BITPOS (0u) -#define PCR1_EC_PECI_BITPOS (1u) -#define PCR1_EC_TACH0_BITPOS (2u) -#define PCR1_EC_PWM0_BITPOS (4u) -#define PCR1_EC_PMC_BITPOS (5u) -#define PCR1_EC_DMA_BITPOS (6u) -#define PCR1_EC_TFDP_BITPOS (7u) -#define PCR1_EC_CPU_BITPOS (8u) -#define PCR1_EC_WDT_BITPOS (9u) -#define PCR1_EC_SMB0_BITPOS (10u) -#define PCR1_EC_TACH1_BITPOS (11u) -#define PCR1_EC_PWM1_BITPOS (20u) -#define PCR1_EC_PWM2_BITPOS (21u) -#define PCR1_EC_PWM3_BITPOS (22u) -#define PCR1_EC_REG_BITPOS (29u) -#define PCR1_EC_BTIMER0_BITPOS (30u) -#define PCR1_EC_BTIMER1_BITPOS (31u) - -//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions -#define PCR2_HOST_LPC_BITPOS (0u) -#define PCR2_HOST_UART0_BITPOS (1u) -#define PCR2_HOST_GLBL_CFG_BITPOS (12u) -#define PCR2_HOST_ACPI_EC0_BITPOS (13u) -#define PCR2_HOST_ACPI_EC1_BITPOS (14u) -#define PCR2_HOST_ACPI_PM1_BITPOS (15u) -#define PCR2_HOST_8042EM_BITPOS (16u) -#define PCR2_HOST_RTC_BITPOS (18u) - -//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions -#define PCR3_EC2_ADC_BITPOS (3u) -#define PCR3_EC2_PS2_0_BITPOS (5u) -#define PCR3_EC2_PS2_1_BITPOS (6u) -#define PCR3_EC2_PS2_2_BITPOS (7u) -#define PCR3_EC2_PS2_3_BITPOS (8u) -#define PCR3_EC2_SPI0_BITPOS (9u) -#define PCR3_EC2_HTIMER_BITPOS (10u) -#define PCR3_EC2_KEYSCAN_BITPOS (11u) -#define PCR3_EC2_RPM_PWM_BITPOS (12u) -#define PCR3_EC2_SMB1_BITPOS (13u) -#define PCR3_EC2_SMB2_BITPOS (14u) -#define PCR3_EC2_SMB3_BITPOS (15u) -#define PCR3_EC2_LED0_BITPOS (16u) -#define PCR3_EC2_LED1_BITPOS (17u) -#define PCR3_EC2_LED2_BITPOS (18u) -#define PCR3_EC2_BCM_BITPOS (19u) -#define PCR3_EC2_SPI1_BITPOS (20u) -#define PCR3_EC2_BTIMER2_BITPOS (21u) -#define PCR3_EC2_BTIMER3_BITPOS (22u) -#define PCR3_EC2_BTIMER4_BITPOS (23u) -#define PCR3_EC2_BTIMER5_BITPOS (24u) -#define PCR3_EC2_LED3_BITPOS (25u) - -/* - * n = b[7:0] = PCR Reg Bit Position - * m = b[31:8] = PCRx Regs IDs - */ -//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) - -//PCRx_REGS_BIT positions -#define PCRx_REGS_POS_SLEEP_ENABLE (8u) -#define PCRx_REGS_POS_CLK_REQD_STS (16u) -#define PCRx_REGS_POS_RESET_ENABLE (24u) - - -/******************************************************************************/ -/** PCR Block IDS. - * These IDs are used to directly refer to a block - *******************************************************************************/ -typedef enum { - PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), - PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), - PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), - PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), - PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), - PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), - PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), - PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), - PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), - PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), - PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), - PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), - PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), - PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), - PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), - PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), - PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), - PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)), - PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)), - PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)), - PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)), - PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)), - PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)), - PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)), - PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)), - PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)), - PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)), - PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)), - PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)), - PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)), - PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)), - PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)), - PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)), - PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)), - PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)), - PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)), - PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)), - PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)), - PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)), - PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)), - PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)), - PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)), - PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)), - PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)), - PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)), - PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)), - PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)), -} PCR_BLK_ID; - - -/******************************************************************************/ -/** PCR Processor ClK Divide Values - *******************************************************************************/ -enum PROCESSOR_CLK_DIVIDE_VALUE -{ - PCR_CPU_CLK_DIVIDE_1 = 1, - PCR_CPU_CLK_DIVIDE_4 = 4, - PCR_CPU_CLK_DIVIDE_16 = 16, - PCR_CPU_CLK_DIVIDE_48 = 48 -}; - -/******************************************************************************/ -/** System Sleep Modes - *******************************************************************************/ -enum SYSTEM_SLEEP_MODES -{ - SYSTEM_HEAVY_SLEEP_1 = 0, - SYSTEM_HEAVY_SLEEP_3 = 1, - SYSTEM_HEAVY_SLEEP_2 = 2, - SYSTEM_DEEPEST_SLEEP = 5 -}; - -/* Bitmask for System Sleep Control Register */ -#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0) -#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1) -#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2) - -/* Bitmask for Chip Sub-system Power Reset Status Register */ -#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2) -#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3) -#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5) -#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6) -#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10) -#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11) - -/* Bitmask for Processor Clock Control Register */ -#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8) - -/* Bitmask for Power Reset Control Register */ -#define PCR_iRESET_OUT_BITMASK (1UL<<0) - -/* ---------------------------------------------------------------------- */ -/* API - Functions to program Sleep Enable, CLK Reqd Status, * - * Reset Enable for a block * - * ---------------------------------------------------------------------- */ - /** Sets or Clears block specific bit in PCR Sleep Enable Register - * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT - * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register - */ -void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag); - -/** Get Clock Required Status for the block - * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT - * @return uint8_t - 1 if Clock Required Status set, else 0 - */ -uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id); - -/** Sets or Clears Reset Enable register bit for the block - * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT - * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register - */ -void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag); - -/* ---------------------------------------------------------------------- */ -/* API - Functions for entering low power modes */ -/* ---------------------------------------------------------------------- */ -/** Instructs all blocks to sleep by setting the Sleep Enable bits */ -void pcr_all_blocks_sleep(void); - -/** Clears the Sleep Enable bits for all blocks */ -void pcr_all_blocks_wake(void); - -/** Programs required sleep mode in System Sleep Control Register - * @param sleep_mode - see enum SYSTEM_SLEEP_MODES - */ -void pcr_system_sleep(uint8_t sleep_mode); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Functions to program and read 32-bit values * - * from PCR Registers * - * ---------------------------------------------------------------------- */ - /** Write 32-bit value in the PCR Register - * @param pcr_reg_id - pcr register id - * @param value - 32-bit value - */ -void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value); - -/** Reads 32-bit value from the PCR Register - * @param pcr_reg_id - pcr register id - * @return value - 32-bit value - */ -uint32_t p_pcr_reg_read(uint8_t pcr_reg_id); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Functions to set, clr and get bits in * - * PCR Registers * - * ---------------------------------------------------------------------- */ - /** Sets bits in a PCR Register - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to set - */ -void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask); - -/** Clears bits in a PCR Register - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to clear - */ -void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask); - -/** Read bits in a PCR Register - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to read - * @return value - 32-bit value - */ -uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask); - -/** Sets or Clears bits in a PCR Register - Helper Function - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to set or clear - * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register - */ -void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag); - -//Functions to operate on System Sleep Control Register - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Functions to operate on System Sleep Control * - * Register * - * ---------------------------------------------------------------------- */ -/** Sets/Clears the Ring oscillator power down bit - * in System Sleep Control Register - * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit - */ -void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag); - -/** Sets/Clears the Ring oscillator output gate bit - * in System Sleep Control Register - * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit - */ -void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag); - -/** Sets/Clears the Core regulator standby bit - * in System Sleep Control Register - * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit - */ -void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag); - -/** Writes required sleep mode in System Sleep Control Register - * @param sleep_value - System Sleep control value - [D2, D1, D0] - */ -void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value); - -/** Reads the System Sleep Control PCR Register - * @return value - byte 0 of the system sleep control PCR register - */ -uint8_t p_pcr_system_sleep_ctrl_read(void); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Function to program to CLK Divide Value * - * ---------------------------------------------------------------------- */ - /** Writes the clock divide value in the Processor Clock Control Register - * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE - */ -void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Function to program the Slow Clock Control * - * Register * - * ---------------------------------------------------------------------- */ - /** Write the slow clock divide value in the Slow Clock Control Register - * @param slow_clk_divide_value - slow clk divide value - */ -void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Function to read the Oscillator Lock Status */ -/* ---------------------------------------------------------------------- */ -/** Reads the Oscillator Lock status bit in the Oscillator ID Register - * @return 1 if Oscillator Lock Status bit is set, else 0 - */ -uint8_t p_pcr_oscillator_lock_sts_get(void); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Functions to read various power status in * - * Chip Sub-System register * - * ---------------------------------------------------------------------- */ - /** Reads the VCC Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if VCC Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void); - -/** Reads the SIO Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if SIO Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void); - -/** Reads the VBAT Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if VBAT Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void); - -/** Clears the VBAT Reset Status bit - * in the Chip Subsystem Power Reset Status Register - */ -void p_pcr_chip_subsystem_vbat_reset_sts_clr(void); - -/** Reads the VCC1 Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if VCC1 Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void); - -/** Clears the VCC1 Reset Status bit - * in the Chip Subsystem Power Reset Status Register - */ -void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void); - -/** Reads the 32K_ACTIVE status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if 32_ACTIVE bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void); - -/** Reads the PCICLK_ACTIVE status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if CICLK_ACTIVE bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void); - -/* ---------------------------------------------------------------------- */ -/* Peripheral Function - Functions for Power Reset Control Register */ -/* ---------------------------------------------------------------------- */ -/** Reads the iRESET_OUT bit in the Power Reset Control Register - * @return 1 if iRESET_OUT bit is set, else 0 - */ -uint8_t p_pcr_iReset_Out_get(void); - -/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register - * @param 1 Set iRESET_OUT bit; 0 - Clear the bit - */ -void p_pcr_iReset_Out(uint8_t set_clr_flag); - -#endif // #ifndef _PCR_H -/* end pcr.h */ -/** @} - */ - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr_api.c deleted file mode 100644 index e7454d84e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr_api.c +++ /dev/null @@ -1,133 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/11/24 06:28:28 $ -$Author: amohandas $ -Last Change: Updated for tabs -******************************************************************************/ -/** @file pcr_api.c -* \brief Power, Clocks, and Resets API Source file -* \author jvasanth -* -* This file implements the PCR APIs -******************************************************************************/ - -/** @defgroup PCR - * @{ - */ - -#include "common_lib.h" -#include "pcr.h" - - -/* ------------------------------------------------------------------------------- */ -/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */ -/* ------------------------------------------------------------------------------- */ - -/** Sets or Clears block specific bit in PCR Sleep Enable Register - * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT - * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register - */ -void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag) -{ - uint32_t bit_mask; - uint8_t pcr_reg_id; - - bit_mask = 1UL<<(pcr_block_id & 0xFFu); - pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu); - - p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); -} - - -/** Get Clock Required Status for the block - * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT - * @return uint8_t - 1 if Clock Required Status set, else 0 - */ -uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id) -{ - uint32_t bit_mask; - uint8_t pcr_reg_id, retVal; - - bit_mask = 1UL<<(pcr_block_id & 0xFFu); - pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu); - - retVal = 0; - if (p_pcr_reg_get(pcr_reg_id, bit_mask)) - { - retVal = 1; - } - - return retVal; -} - -/** Sets or Clears Reset Enable register bit for the block - * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT - * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register - */ -void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag) -{ - uint32_t bit_mask; - uint8_t pcr_reg_id; - - bit_mask = 1UL<<(pcr_block_id & 0xFFu); - pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu); - - p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); -} - - -/* ------------------------------------------------------------------------------- */ -/* Functions for entering low power modes */ -/* ------------------------------------------------------------------------------- */ - -/** Instructs all blocks to sleep by setting the Sleep Enable bits */ -void pcr_all_blocks_sleep(void) -{ - p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF); - p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF); - p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF); - p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF); -} - -/** Clears the Sleep Enable bits for all blocks */ - void pcr_all_blocks_wake(void) -{ - p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0); - p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0); - p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0); - p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0); -} - -/** Programs required sleep mode in System Sleep Control Register - * @param sleep_mode - see enum SYSTEM_SLEEP_MODES - */ -void pcr_system_sleep(uint8_t sleep_mode) -{ - p_pcr_system_sleep_ctrl_write(sleep_mode); -} - - -/* end pcr_api.c */ -/** @} - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr_perphl.c deleted file mode 100644 index af43e5df4..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/pcr/pcr_perphl.c +++ /dev/null @@ -1,490 +0,0 @@ -/***************************************************************************** -* © 2015 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -****************************************************************************** - -Version Control Information (Perforce) -****************************************************************************** -$Revision: #1 $ -$DateTime: 2015/11/24 06:28:28 $ -$Author: amohandas $ -Last Change: Updated for tabs -******************************************************************************/ -/** @file pcr_perphl.c -* \brief Power, Clocks, and Resets Peripheral Source file -* \author jvasanth -* -* This file implements the PCR Peripheral functions -******************************************************************************/ - -/** @defgroup PCR - * @{ - */ - -#include "common_lib.h" -#include "pcr.h" - -/* ---------------------------------------------------------------------- */ -/* Generic functions to program and read 32-bit values from PCR Registers */ -/* ---------------------------------------------------------------------- */ -/** Writes 32-bit value in the PCR Register - * @param pcr_reg_id - pcr register id - * @param value - 32-bit value - */ -void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE); - - pPCR_Reg += pcr_reg_id; - - *pPCR_Reg = value; -} - -/** Reads 32-bit value from the PCR Register - * @param pcr_reg_id - pcr register id - * @return value - 32-bit value - */ -uint32_t p_pcr_reg_read(uint8_t pcr_reg_id) -{ - __IO uint32_t *pPCR_Reg; - uint32_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE); - - pPCR_Reg += pcr_reg_id; - - retVal = *pPCR_Reg; - - return retVal; -} - -/* ---------------------------------------------------------------------- */ -/* Functions to set, clr and get bits in PCR Registers */ -/* ---------------------------------------------------------------------- */ - -/** Sets bits in a PCR Register - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to set - */ -void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE); - - pPCR_Reg += pcr_reg_id; - - *pPCR_Reg |= bit_mask; -} - -/** Clears bits in a PCR Register - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to clear - */ -void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE); - - pPCR_Reg += pcr_reg_id; - - *pPCR_Reg &= ~bit_mask; -} - -/** Read bits in a PCR Register - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to read - * @return value - 32-bit value - */ -uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask) -{ - __IO uint32_t *pPCR_Reg; - uint32_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE); - - pPCR_Reg += pcr_reg_id; - - retVal = (*pPCR_Reg) & bit_mask; - - return retVal; -} - -/** Sets or Clears bits in a PCR Register - Helper Function - * @param pcr_reg_id - pcr register id - * @param bit_mask - Bit mask of bits to set or clear - * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register - */ -void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag) -{ - if (set_clr_flag) - { - p_pcr_reg_set(pcr_reg_id, bit_mask); - } - else - { - p_pcr_reg_clr(pcr_reg_id, bit_mask); - } -} - -/* ---------------------------------------------------------------------- */ -/* Functions to operate on System Sleep Control Register */ -/* ---------------------------------------------------------------------- */ - -/** - * Sets/Clears the Ring oscillator power down bit - * in System Sleep Control Register - * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit - */ -void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; - - if (set_clr_flag) - { - *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; - } - else - { - *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; - } -} - -/** Sets/Clears the Ring oscillator output gate bit - * in System Sleep Control Register - * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit - */ -void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; - - if (set_clr_flag) - { - *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; - } - else - { - *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; - } -} - -/** Sets/Clears the Core regulator standby bit - * in System Sleep Control Register - * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit - */ -void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; - - if (set_clr_flag) - { - *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; - } - else - { - *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; - } -} - -/** Writes required sleep mode in System Sleep Control Register - * @param sleep_value - System Sleep control value - [D2, D1, D0] - */ -void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; - - *pPCR_Reg = (sleep_value & 0x7); -} - -/** Reads the System Sleep Control PCR Register - * @return value - byte 0 of the system sleep control PCR register - */ -uint8_t p_pcr_system_sleep_ctrl_read(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; - - retVal = (uint8_t)((*pPCR_Reg) & 0xFF); - - return retVal; -} - - - -/* ---------------------------------------------------------------------- */ -/* Function to program to CLK Divide Value */ -/* ---------------------------------------------------------------------- */ - -/** Writes the clock divide value in the Processor Clock Control Register - * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE - */ -void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; - - *pPCR_Reg = (clk_divide_value & 0xFF); - -} - -/* ---------------------------------------------------------------------- */ -/* Function to program the slow clock divide value */ -/* ---------------------------------------------------------------------- */ - -/** Write the slow clock divide value in the Slow Clock Control Register - * @param slow_clk_divide_value - slow clk divide value - */ -void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; - - *pPCR_Reg = (slow_clk_divide_value & 0x3FF); - -} - -/* ---------------------------------------------------------------------- */ -/* Function to read the Oscillator Lock Status */ -/* ---------------------------------------------------------------------- */ - -/** Reads the Oscillator Lock status bit in the Oscillator ID Register - * @return 1 if Oscillator Lock Status bit is set, else 0 - */ -uint8_t p_pcr_oscillator_lock_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; - - retVal = 0; - if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK) - { - retVal = 1; - } - - return retVal; - -} - -/* ---------------------------------------------------------------------- */ -/* Functions to read various power status in Chip Sub-System register */ -/* ---------------------------------------------------------------------- */ - -/** Reads the VCC Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if VCC Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - retVal = 0; - if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK) - { - retVal = 1; - } - - return retVal; -} - -/** Reads the SIO Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if SIO Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - retVal = 0; - if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK) - { - retVal = 1; - } - - return retVal; -} - -/** Reads the VBAT Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if VBAT Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - retVal = 0; - if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK) - { - retVal = 1; - } - - return retVal; -} - -/** Clears the VBAT Reset Status bit - * in the Chip Subsystem Power Reset Status Register - */ -void p_pcr_chip_subsystem_vbat_reset_sts_clr(void) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - // Write to clear - *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK; - -} - -/** Reads the VCC1 Reset Status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if VCC1 Reset Status bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - retVal = 0; - if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK) - { - retVal = 1; - } - - return retVal; -} - -/** Clears the VCC1 Reset Status bit - * in the Chip Subsystem Power Reset Status Register - */ -void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - // Write to clear - *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK; - -} - -/** Reads the 32K_ACTIVE status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if 32_ACTIVE bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - retVal = 0; - if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK) - { - retVal = 1; - } - - return retVal; -} - -/** Reads the PCICLK_ACTIVE status bit - * in the Chip Subsystem Power Reset Status Register - * @return 1 if CICLK_ACTIVE bit is set, else 0 - */ -uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; - - retVal = 0; - if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK) - { - retVal = 1; - } - return retVal; -} - -/* ---------------------------------------------------------------------- */ -/* Functions for Power Reset Control Register */ -/* ---------------------------------------------------------------------- */ - -/** Reads the iRESET_OUT bit in the Power Reset Control Register - * @return 1 if iRESET_OUT bit is set, else 0 - */ -uint8_t p_pcr_iReset_Out_get(void) -{ - __IO uint32_t *pPCR_Reg; - uint8_t retVal; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; - - retVal = 0; - if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK) - { - retVal = 1; - } - - return retVal; - -} - -/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register - * @param 1 Set iRESET_OUT bit; 0 - Clear the bit - */ -void p_pcr_iReset_Out(uint8_t set_clr_flag) -{ - __IO uint32_t *pPCR_Reg; - - pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; - - *pPCR_Reg = (set_clr_flag & 0x1); -} - - -/* end pcr_perphl.c */ -/** @} - */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/platform.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/platform.h deleted file mode 100644 index 2db4163c7..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil/peripheral_library/platform.h +++ /dev/null @@ -1,390 +0,0 @@ -/**************************************************************************** -* © 2013 Microchip Technology Inc. and its subsidiaries. -* You may use this software and any derivatives exclusively with -* Microchip products. -* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". -* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, -* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, -* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP -* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. -* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, -* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND -* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS -* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. -* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL -* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF -* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. -* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE -* OF THESE TERMS. -*/ - -/** @defgroup pwm pwm_c_wrapper - * @{ - */ -/** @file pwm_c_wrapper.cpp - \brief the pwm component C wrapper - This program is designed to allow the other C programs to be able to use this component - - There are entry points for all C wrapper API implementation - -Platform: This is ARC-based component - -Toolset: Metaware IDE(8.5.1) -Reference: smsc_reusable_fw_requirement.doc */ - -/******************************************************************************* - * SMSC version control information (Perforce): - * - * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $ - * REVISION: $Revision: #1 $ - * DATETIME: $DateTime: 2015/12/23 15:37:58 $ - * AUTHOR: $Author: akrishnan $ - * - * Revision history (latest first): - * #xx - *********************************************************************************** - */ - -#ifndef _PLATFORM_H_ -#define _PLATFORM_H_ -#include -/* Platform Configuration PreProcessor Conditions */ -#define TOOLKEIL 1 -#define TOOLPC 2 -#define TOOLMW 3 -#define TOOLMDK 4 - -#define PCLINT 9 //added to satisfy PC Lint's need for a value here - -#ifdef __CC_ARM // Keil ARM MDK -#define TOOLSET TOOLMDK -#endif - -#if 0 -#ifdef _WIN32 //always defined by visual c++ -#define TOOLSET TOOLPC -#endif - -#ifdef __WIN32__ //always defined by borland -#define TOOLSET TOOLPC -#endif -#endif - - -#ifdef _ARC -#define TOOLSET TOOLMW // ARC Metaware -#endif - -#ifndef TOOLSET -//#error "ERROR: cfg.h TOOLSET not defined!" -#endif - -#if TOOLSET == TOOLMDK -#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */ -#define _KEIL_ 0 /* Make 1 for Keil Compiler */ -#define _PC_ 0 -#define _ARC_CORE_ 0 -#endif - -#if TOOLSET == TOOLKEIL -#define _KEIL_ARM_ 0 -#define _KEIL_ 1 /* Make 1 for Keil Compiler */ -#define _PC_ 0 -#define _ARC_CORE_ 0 -#endif - -#if TOOLSET == TOOLPC -#define _KEIL_ARM_ 0 -#define _KEIL_ 0 -#define _PC_ 1 /* Make 1 for PC Environment */ -#define _ARC_CORE_ 0 -#endif - -#if TOOLSET == TOOLMW -#define _KEIL_ARM_ 0 -#define _KEIL_ 0 -#define _PC_ 0 -#define _ARC_CORE_ 1 -#endif - -/* Short form for Standard Data Types */ -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned long UINT32; - -typedef volatile unsigned char REG8; - -typedef unsigned char BYTE; -typedef unsigned short WORD; -typedef unsigned long DWORD; - -typedef unsigned char UCHAR; -typedef unsigned short USHORT; -typedef unsigned long ULONG; - -typedef unsigned char BOOL; -typedef unsigned int UINT; - -/* signed types */ -typedef signed char INT8; -typedef signed short INT16; -typedef signed long INT32; - -typedef void VOID; - -/* union types */ -typedef union _BITS_8 -{ - UINT8 byte; - struct - { - UINT8 bit0: 1; - UINT8 bit1: 1; - UINT8 bit2: 1; - UINT8 bit3: 1; - UINT8 bit4: 1; - UINT8 bit5: 1; - UINT8 bit6: 1; - UINT8 bit7: 1; - }bit; -}BITS_8; - - -/* MACROS FOR Platform Portability */ - -/* macro for defining MMCR register */ -/* add MMCRARRAY() & EXTERNMMCRARRAY() */ -#if _KEIL_ -#define MMCR(name,address) volatile unsigned char xdata name _at_ address -#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address -#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address -#define EXTERNMMCR(name) extern volatile unsigned char xdata name -#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[] -#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name -#define SFR(name,address) sfr name = address -#define SFRBIT(name,address) sbit name = address -#define EXTERNSFR(name) -#define BITADDRESSTYPE(name) bit name -#define XDATA xdata -#define CODE code -#define DATA data -#define IDATA idata -#define INTERRUPT(x) interrupt x -#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;) -#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;) -#define NULLPTR (char *)(0) -#define PLATFORM_TRIM_OSC() // TODO -#define PNOP() -#define DISABLE_INTERRUPTS() sfrIE_EAbit=0 -#define ENABLE_INTERRUPTS() sfrIE_EAbit=1 -#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; } -#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; } -#define ATOMIC_CPU_SLEEP() -#define NUM_IRQ_VECTORS 12 // DW-8051 -#define IRQ_VECTOR_SIZE 8 -#define USE_INLINE_PATCHER 1 -#define IRQ_VECTABLE_IN_RAM 0 -#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start -#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start -#define FUNC_NEVER_RETURNS -#define BEGIN_SMALL_DATA_BLOCK(x) -#define END_SMALL_DATA_BLOCK() -UINT32 soft_norm(UINT32 val); -#define NORM(x) soft_norm(x) -// -#define USE_FUNC_REPLACEMENT 0 -#endif - -#if _PC_ -#define MMCR(name,address) volatile unsigned char name -#define MMCRARRAY(name,length,address) volatile unsigned char name[length] -#define MMCRTYPE(name,dtype,address) volatile dtype name -#define EXTERNMMCR(name) extern volatile unsigned char name -#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] -#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name -#define SFR(name,address) volatile unsigned char name -#define SFRBIT(name,address) volatile unsigned char name -#define EXTERNSFR(name) extern volatile unsigned char name -#define BITADDRESSTYPE(name) volatile unsigned char name -#define XDATA -#define CODE -#define DATA -#define IDATA -#define INTERRUPT(x) -#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;) -#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;) -#define NULLPTR (char *)(0) -#define PLATFORM_TRIM_OSC() // TODO -#define PNOP() -#define DISABLE_INTERRUPTS() -#define ENABLE_INTERRUPTS() -#define SAVE_DIS_INTERRUPTS(x) -#define RESTORE_INTERRUPTS(x) -#define ATOMIC_CPU_SLEEP() -#define NUM_IRQ_VECTORS 24 -#define IRQ_VECTOR_SIZE 8 -#define USE_INLINE_PATCHER 1 -#define IRQ_VECTABLE_IN_RAM 0 -#define FUNC_NEVER_RETURNS -#define BEGIN_SMALL_DATA_BLOCK(x) -#define END_SMALL_DATA_BLOCK() -UINT32 soft_norm(UINT32 val); -#define NORM(x) soft_norm(x) -// -#define USE_FUNC_REPLACEMENT 0 -#endif - -#if _ARC_CORE_ -// ARC C has no equivalent operator to specify address of a variable -// ARC MMCR's are 32-bit registers -#define MMCR(name,address) volatile unsigned char name -#define MMCRARRAY(name,length,address) volatile unsigned char name[length] -#define MMCRTYPE(name,dtype,address) volatile dtype name -#define EXTERNMMCR(name) extern volatile unsigned char name -#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] -#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name -#define SFR(name,address) volatile unsigned char name -#define SFRBIT(name,address) volatile unsigned char name -#define EXTERNSFR(name) extern volatile unsigned char name -#define BITADDRESSTYPE(name) -#define XDATA -#define CODE -#define DATA -#define IDATA -#define INTERRUPT(x) -#define SET_GLOBAL_INTR_ENABLE() (_enable()) -#define CLR_GLOBAL_INTR_ENABLE() (_disable()) -#define NULLPTR (char *)(0) -#define NULLVOIDPTR (void *)(0) -#define NULLFPTR (void (*)(void))0 -#define PLATFORM_TRIM_OSC() // TODO -#define PNOP() _nop() -#define DISABLE_INTERRUPTS() _disable() -#define ENABLE_INTERRUPTS() _enable() -#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); } -#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); } -#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop(); -#define NUM_IRQ_VECTORS 24 -#define IRQ_VECTOR_SIZE 8 -#define USE_INLINE_PATCHER 0 -#define DCCM_CODE_ALIAS_ADDR 0x00060000 -#define PLAT_ROM_IRQ_VECTOR_BASE 0 -#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR) -/// y #define IRQ_VECTABLE_IN_RAM 1 -#define IRQ_VECTABLE_IN_RAM 0 -#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS) -#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x) -#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data() -#define NORM(x) _norm(x) - -#define INLINE_FUNCTION(x) #pragma On_inline(x) - -// -#define USE_FUNC_REPLACEMENT 0 -#endif - -#if _KEIL_ARM_ -// For ARM MDK compiler -// ARM MMCR's are 32-bit registers -#define MMCR(name,address) volatile unsigned char name -#define MMCRARRAY(name,length,address) volatile unsigned char name[length] -#define MMCRTYPE(name,dtype,address) volatile dtype name -#define EXTERNMMCR(name) extern volatile unsigned char name -#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] -#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name -#define SFR(name,address) volatile unsigned char name -#define SFRBIT(name,address) volatile unsigned char name -#define EXTERNSFR(name) extern volatile unsigned char name -#define BITADDRESSTYPE(name) -#define XDATA -#define CODE -#define DATA -#define IDATA -#define INTERRUPT(x) -#define SET_GLOBAL_INTR_ENABLE() (__enable_irq()) -#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq()) -#define NULLPTR (char *)(0) -#define NULLVOIDPTR (void *)(0) -#define NULLFPTR (void (*)(void))0 -#define PLATFORM_TRIM_OSC() // TODO -#define PNOP() __NOP() -#define DISABLE_INTERRUPTS() __disable_irq() -#define ENABLE_INTERRUPTS() __enable_irq() -#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop(); - -#if 0 /* need further efforts if needed */ -#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); } -#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); } -#define NUM_IRQ_VECTORS 24 -#define IRQ_VECTOR_SIZE 8 -#define USE_INLINE_PATCHER 0 -#define DCCM_CODE_ALIAS_ADDR 0x00060000 -#define PLAT_ROM_IRQ_VECTOR_BASE 0 -#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR) -/// y #define IRQ_VECTABLE_IN_RAM 1 -#define IRQ_VECTABLE_IN_RAM 0 -#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x) -#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data() -#define INLINE_FUNCTION(x) #pragma On_inline(x) -#define USE_FUNC_REPLACEMENT 0 -#endif - -#if 0 -#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS) -#define NORM(x) _norm(x) -#else -/* for ARM MDK */ -#define FUNC_NEVER_RETURNS -UINT32 soft_norm(UINT32 val); -#define NORM(x) soft_norm(x) -#endif -#endif - -/* General Constants */ -#define FALSE 0x00 -#define TRUE !FALSE - -#define BIT_n_MASK(n) (1U << (n)) -#define BIT_0_MASK (1<<0) -#define BIT_1_MASK (1<<1) -#define BIT_2_MASK (1<<2) -#define BIT_3_MASK (1<<3) -#define BIT_4_MASK (1<<4) -#define BIT_5_MASK (1<<5) -#define BIT_6_MASK (1<<6) -#define BIT_7_MASK (1<<7) -#define BIT_8_MASK ((UINT16)1<<8) -#define BIT_9_MASK ((UINT16)1<<9) -#define BIT_10_MASK ((UINT16)1<<10) -#define BIT_11_MASK ((UINT16)1<<11) -#define BIT_12_MASK ((UINT16)1<<12) -#define BIT_13_MASK ((UINT16)1<<13) -#define BIT_14_MASK ((UINT16)1<<14) -#define BIT_15_MASK ((UINT16)1<<15) -#define BIT_16_MASK ((UINT32)1<<16) -#define BIT_17_MASK ((UINT32)1<<17) -#define BIT_18_MASK ((UINT32)1<<18) -#define BIT_19_MASK ((UINT32)1<<19) -#define BIT_20_MASK ((UINT32)1<<20) -#define BIT_21_MASK ((UINT32)1<<21) -#define BIT_22_MASK ((UINT32)1<<22) -#define BIT_23_MASK ((UINT32)1<<23) -#define BIT_24_MASK ((UINT32)1<<24) -#define BIT_25_MASK ((UINT32)1<<25) -#define BIT_26_MASK ((UINT32)1<<26) -#define BIT_27_MASK ((UINT32)1<<27) -#define BIT_28_MASK ((UINT32)1<<28) -#define BIT_29_MASK ((UINT32)1<<29) -#define BIT_30_MASK ((UINT32)1<<30) -#define BIT_31_MASK ((UINT32)1<<31) - - -/* For CEC application */ -#define ON 1 -#define OFF 0 - -#endif /*_PLATFORM_H_*/ - -/** @} - */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/cmsis_armcc.h new file mode 100644 index 000000000..f2bb66a09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/cmsis_gcc.h new file mode 100644 index 000000000..a144be795 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/cmsis_gcc.h @@ -0,0 +1,1366 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */ + + +#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((defined (__CORTEX_M ) && (__CORTEX_M >= 3U)) || \ + (defined (__CORTEX_SC) && (__CORTEX_SC >= 300U)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (defined (__CORTEX_M) && (__CORTEX_M >= 4U)) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cm4.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cm4.h new file mode 100644 index 000000000..01cb73bf3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmFunc.h new file mode 100644 index 000000000..ca319a55c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmInstr.h new file mode 100644 index 000000000..a0a506458 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmSimd.h new file mode 100644 index 000000000..4d76bf901 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/CMSIS/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h new file mode 100644 index 000000000..625a39c20 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/FreeRTOSConfig.h @@ -0,0 +1,224 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + + +/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky demo low power +example, or 1 to run the more comprehensive test and demo application. See +the comments at the top of main.c for more information. */ +#define configCREATE_LOW_POWER_DEMO 1 + +/* Some configuration is dependent on the demo being built. */ +#if( configCREATE_LOW_POWER_DEMO == 1 ) + + /* The low power demo uses a slow low power clock, so the SysTick clock, + which is used by default by Cortex-M ports, is not used to generate the + tick interrupt. */ + #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1 + + /* The slow clock used to generate the tick interrupt in the low power demo + runs at 32768Hz. Ensure the clock is a multiple of the tick rate. */ + #define configTICK_RATE_HZ ( 128 ) + + /* The low power demo uses the tickless idle feature. */ + #define configUSE_TICKLESS_IDLE 1 + +#else + + /* Some of the standard demo test tasks assume a tick rate of 1KHz, even + though that is faster than would normally be warranted by a real + application. */ + #define configTICK_RATE_HZ ( 1000 ) + + /* The full demo always has tasks to run so the tick will never be turned + off. The blinky demo will use the default tickless idle implementation to + turn the tick off. */ + #define configUSE_TICKLESS_IDLE 0 + +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ 48000000 +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 28 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 0 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configSUPPORT_STATIC_ALLOCATION 1 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x7 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler +#define xPortSysTickHandler SysTick_Handler + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* LED not used at present, so just increment a variable to keep a count of the +number of times the LED would otherwise have been toggled. */ +#define configTOGGLE_LED() ulLED++ + + +#ifdef __cplusplus +} +#endif +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/JLinkLog.txt b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/JLinkLog.txt new file mode 100644 index 000000000..d6b5ccdce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/JLinkLog.txt @@ -0,0 +1,492 @@ + +T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total) +T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total) +T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total) +T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total) +T220C 000:298 JLINK_OpenEx(...) +Firmware: J-Link V9 compiled Oct 9 2015 20:34:47 +Hardware: V9.10 +S/N: 59101789 +Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total) +T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total) +T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total) +T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total) +T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) +T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total) +T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) +T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total) +T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total) +T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total) +T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) + -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) + -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0) +ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total) +T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total) +T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total) +T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total) +T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total) +T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total) +T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total) +T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total) +T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total) +T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total) +T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total) +T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total) +T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total) +T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total) +T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total) +T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total) +T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total) +T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total) +T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total) +T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total) +T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total) +T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total) +T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total) +T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) + -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) + -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total) +T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total) +T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total) +T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total) +T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total) +T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total) +T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total) +T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total) +T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total) +T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total) +T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total) +T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total) +T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total) +T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total) +T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total) +T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total) +T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total) +T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total) +T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total) +T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total) +T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total) +T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total) +T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total) +T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total) +T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total) +T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total) +T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total) +T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total) +T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total) +T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total) +T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) +T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total) +T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total) +T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total) +T220C 027:508 (0005ms, 2544ms total) +T220C 027:508 Closed (0005ms, 2544ms total) diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/JLinkSettings.ini new file mode 100644 index 000000000..706cf39a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Unspecified" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri new file mode 100644 index 000000000..111b4c0a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvguix.barryri @@ -0,0 +1,2601 @@ + + + + -5.1 + +
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+ + + + 0 + 1920 + 1200 + + + + + + 1 + 0 + + 100 + 0 + + ..\main.c + 0 + 66 + 141 + 1 + + 0 + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx new file mode 100644 index 000000000..e4186479a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvoptx @@ -0,0 +1,610 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c;*.S + + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RTOSDemo_GCC + 0x3 + ARM-GNU + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + + + + + + + + + + init_app.ini + BIN\UL2CM3.DLL + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + -UV1115SAE -O2983 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0100000 -FL018000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) + + + + + 0 + 0 + 0 + 0 +
38
+ 0 + 0 + 0 + 0 + 0 + 1 + + + 0x00000026 + + + + + 0 + 1 + ulLED + + + + + 1 + 2 + 0x100000 + 4 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + + + + + System + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\system.c + system.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\startup_ARMCM4.S + startup_ARMCM4.S + 0 + 0 + + + + + main_and_config + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\main.c + main.c + 0 + 0 + + + 2 + 4 + 5 + 0 + 0 + 0 + ..\FreeRTOSConfig.h + FreeRTOSConfig.h + 0 + 0 + + + + + FreeRTOS_Source + 1 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\Source\event_groups.c + event_groups.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Source\list.c + list.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Source\queue.c + queue.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Source\tasks.c + tasks.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Source\timers.c + timers.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Source\portable\MemMang\heap_4.c + heap_4.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\Source\portable\GCC\ARM_CM4F\port.c + port.c + 0 + 0 + + + + + main_low_power + 1 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\main_low_power\main_low_power.c + main_low_power.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\main_low_power\low_power_tick_config.c + low_power_tick_config.c + 0 + 0 + + + + + main_full + 1 + 0 + 0 + 0 + + 5 + 14 + 1 + 0 + 0 + 0 + ..\main_full\main_full.c + main_full.c + 0 + 0 + + + 5 + 15 + 1 + 0 + 0 + 0 + .\RegTest.c + RegTest.c + 0 + 0 + + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\flop.c + flop.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\EventGroupsDemo.c + EventGroupsDemo.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\TaskNotify.c + TaskNotify.c + 0 + 0 + + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\blocktim.c + blocktim.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\dynamic.c + dynamic.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\GenQTest.c + GenQTest.c + 0 + 0 + + + 5 + 22 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\TimerDemo.c + TimerDemo.c + 0 + 0 + + + 5 + 23 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\IntQueue.c + IntQueue.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + ..\main_full\IntQueueTimer.c + IntQueueTimer.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\countsem.c + countsem.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\semtest.c + semtest.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\death.c + death.c + 0 + 0 + + + + + peripheral_library + 1 + 0 + 0 + 0 + + 6 + 28 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_api.c + btimer_api.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_perphl.c + btimer_perphl.c + 0 + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx new file mode 100644 index 000000000..8f0f31a6c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RTOSDemo.uvprojx @@ -0,0 +1,453 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RTOSDemo_GCC + 0x3 + ARM-GNU + 5060061::V5.06 update 1 (build 61)::ARMCC + + + ARMCM4_FP + ARM + ARM.CMSIS.4.5.0 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + RTOSDemo + 1 + 0 + 0 + 1 + 0 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 2 + 1 + + -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -ffunction-sections -fdata-sections -O0 -g + + + ..;..\..\..\Source\include;..\..\..\Source\portable\GCC\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full + + + + 0 + 1 + + + + + + + + + 1 + 0 + 1 + 0 + 1 + + + + + + -Xlinker --gc-sections + .\sections.ld + + + + + + System + + + system.c + 1 + .\system.c + + + startup_ARMCM4.S + 2 + .\startup_ARMCM4.S + + + + + main_and_config + + + main.c + 1 + ..\main.c + + + FreeRTOSConfig.h + 5 + ..\FreeRTOSConfig.h + + + + + FreeRTOS_Source + + + event_groups.c + 1 + ..\..\..\Source\event_groups.c + + + list.c + 1 + ..\..\..\Source\list.c + + + queue.c + 1 + ..\..\..\Source\queue.c + + + tasks.c + 1 + ..\..\..\Source\tasks.c + + + timers.c + 1 + ..\..\..\Source\timers.c + + + heap_4.c + 1 + ..\..\..\Source\portable\MemMang\heap_4.c + + + port.c + 1 + ..\..\..\Source\portable\GCC\ARM_CM4F\port.c + + + + + main_low_power + + + main_low_power.c + 1 + ..\main_low_power\main_low_power.c + + + low_power_tick_config.c + 1 + ..\main_low_power\low_power_tick_config.c + + + + + main_full + + + main_full.c + 1 + ..\main_full\main_full.c + + + RegTest.c + 1 + .\RegTest.c + + + flop.c + 1 + ..\..\Common\Minimal\flop.c + + + EventGroupsDemo.c + 1 + ..\..\Common\Minimal\EventGroupsDemo.c + + + TaskNotify.c + 1 + ..\..\Common\Minimal\TaskNotify.c + + + blocktim.c + 1 + ..\..\Common\Minimal\blocktim.c + + + dynamic.c + 1 + ..\..\Common\Minimal\dynamic.c + + + GenQTest.c + 1 + ..\..\Common\Minimal\GenQTest.c + + + TimerDemo.c + 1 + ..\..\Common\Minimal\TimerDemo.c + + + IntQueue.c + 1 + ..\..\Common\Minimal\IntQueue.c + + + IntQueueTimer.c + 1 + ..\main_full\IntQueueTimer.c + + + countsem.c + 1 + ..\..\Common\Minimal\countsem.c + + + semtest.c + 1 + ..\..\Common\Minimal\semtest.c + + + death.c + 1 + ..\..\Common\Minimal\death.c + + + + + peripheral_library + + + btimer_api.c + 1 + ..\peripheral_library\basic_timer\btimer_api.c + + + btimer_perphl.c + 1 + ..\peripheral_library\basic_timer\btimer_perphl.c + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c new file mode 100644 index 000000000..dd82dd892 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/RegTest.c @@ -0,0 +1,457 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + +void vRegTest1Implementation( void ) __attribute__ ((naked)); +void vRegTest2Implementation( void ) __attribute__ ((naked)); + +void vRegTest1Implementation( void ) +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + "/* Fill the core registers with known values. */ \n" + "mov r0, #100 \n" + "mov r1, #101 \n" + "mov r2, #102 \n" + "mov r3, #103 \n" + "mov r4, #104 \n" + "mov r5, #105 \n" + "mov r6, #106 \n" + "mov r7, #107 \n" + "mov r8, #108 \n" + "mov r9, #109 \n" + "mov r10, #110 \n" + "mov r11, #111 \n" + "mov r12, #112 \n" + + "/* Fill the VFP registers with known values. */ \n" + "vmov d0, r0, r1 \n" + "vmov d1, r2, r3 \n" + "vmov d2, r4, r5 \n" + "vmov d3, r6, r7 \n" + "vmov d4, r8, r9 \n" + "vmov d5, r10, r11 \n" + "vmov d6, r0, r1 \n" + "vmov d7, r2, r3 \n" + "vmov d8, r4, r5 \n" + "vmov d9, r6, r7 \n" + "vmov d10, r8, r9 \n" + "vmov d11, r10, r11 \n" + "vmov d12, r0, r1 \n" + "vmov d13, r2, r3 \n" + "vmov d14, r4, r5 \n" + "vmov d15, r6, r7 \n" + + "reg1_loop: \n" + "/* Check all the VFP registers still contain the values set above. \n" + "First save registers that are clobbered by the test. */ \n" + "push { r0-r1 } \n" + + "vmov r0, r1, d0 \n" + "cmp r0, #100 \n" + "bne reg1_error_loopf \n" + "cmp r1, #101 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d1 \n" + "cmp r0, #102 \n" + "bne reg1_error_loopf \n" + "cmp r1, #103 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d2 \n" + "cmp r0, #104 \n" + "bne reg1_error_loopf \n" + "cmp r1, #105 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d3 \n" + "cmp r0, #106 \n" + "bne reg1_error_loopf \n" + "cmp r1, #107 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d4 \n" + "cmp r0, #108 \n" + "bne reg1_error_loopf \n" + "cmp r1, #109 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d5 \n" + "cmp r0, #110 \n" + "bne reg1_error_loopf \n" + "cmp r1, #111 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d6 \n" + "cmp r0, #100 \n" + "bne reg1_error_loopf \n" + "cmp r1, #101 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d7 \n" + "cmp r0, #102 \n" + "bne reg1_error_loopf \n" + "cmp r1, #103 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d8 \n" + "cmp r0, #104 \n" + "bne reg1_error_loopf \n" + "cmp r1, #105 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d9 \n" + "cmp r0, #106 \n" + "bne reg1_error_loopf \n" + "cmp r1, #107 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d10 \n" + "cmp r0, #108 \n" + "bne reg1_error_loopf \n" + "cmp r1, #109 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d11 \n" + "cmp r0, #110 \n" + "bne reg1_error_loopf \n" + "cmp r1, #111 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d12 \n" + "cmp r0, #100 \n" + "bne reg1_error_loopf \n" + "cmp r1, #101 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d13 \n" + "cmp r0, #102 \n" + "bne reg1_error_loopf \n" + "cmp r1, #103 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d14 \n" + "cmp r0, #104 \n" + "bne reg1_error_loopf \n" + "cmp r1, #105 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d15 \n" + "cmp r0, #106 \n" + "bne reg1_error_loopf \n" + "cmp r1, #107 \n" + "bne reg1_error_loopf \n" + + "/* Restore the registers that were clobbered by the test. */ \n" + "pop {r0-r1} \n" + + "/* VFP register test passed. Jump to the core register test. */ \n" + "b reg1_loopf_pass \n" + + "reg1_error_loopf: \n" + "/* If this line is hit then a VFP register value was found to be incorrect. */ \n" + "b reg1_error_loopf \n" + + "reg1_loopf_pass: \n" + + "cmp r0, #100 \n" + "bne reg1_error_loop \n" + "cmp r1, #101 \n" + "bne reg1_error_loop \n" + "cmp r2, #102 \n" + "bne reg1_error_loop \n" + "cmp r3, #103 \n" + "bne reg1_error_loop \n" + "cmp r4, #104 \n" + "bne reg1_error_loop \n" + "cmp r5, #105 \n" + "bne reg1_error_loop \n" + "cmp r6, #106 \n" + "bne reg1_error_loop \n" + "cmp r7, #107 \n" + "bne reg1_error_loop \n" + "cmp r8, #108 \n" + "bne reg1_error_loop \n" + "cmp r9, #109 \n" + "bne reg1_error_loop \n" + "cmp r10, #110 \n" + "bne reg1_error_loop \n" + "cmp r11, #111 \n" + "bne reg1_error_loop \n" + "cmp r12, #112 \n" + "bne reg1_error_loop \n" + + "/* Everything passed, increment the loop counter. */ \n" + "push { r0-r1 } \n" + "ldr r0, =ulRegTest1LoopCounter \n" + "ldr r1, [r0] \n" + "adds r1, r1, #1 \n" + "str r1, [r0] \n" + "pop { r0-r1 } \n" + + "/* Start again. */ \n" + "b reg1_loop \n" + + "reg1_error_loop: \n" + "/* If this line is hit then there was an error in a core register value. \n" + "The loop ensures the loop counter stops incrementing. */ \n" + "b reg1_error_loop \n" + "nop " + ); /* __asm volatile. */ +} +/*-----------------------------------------------------------*/ + +void vRegTest2Implementation( void ) +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + "/* Set all the core registers to known values. */ \n" + "mov r0, #-1 \n" + "mov r1, #1 \n" + "mov r2, #2 \n" + "mov r3, #3 \n" + "mov r4, #4 \n" + "mov r5, #5 \n" + "mov r6, #6 \n" + "mov r7, #7 \n" + "mov r8, #8 \n" + "mov r9, #9 \n" + "mov r10, #10 \n" + "mov r11, #11 \n" + "mov r12, #12 \n" + + "/* Set all the VFP to known values. */ \n" + "vmov d0, r0, r1 \n" + "vmov d1, r2, r3 \n" + "vmov d2, r4, r5 \n" + "vmov d3, r6, r7 \n" + "vmov d4, r8, r9 \n" + "vmov d5, r10, r11 \n" + "vmov d6, r0, r1 \n" + "vmov d7, r2, r3 \n" + "vmov d8, r4, r5 \n" + "vmov d9, r6, r7 \n" + "vmov d10, r8, r9 \n" + "vmov d11, r10, r11 \n" + "vmov d12, r0, r1 \n" + "vmov d13, r2, r3 \n" + "vmov d14, r4, r5 \n" + "vmov d15, r6, r7 \n" + + "reg2_loop: \n" + + "/* Check all the VFP registers still contain the values set above. \n" + "First save registers that are clobbered by the test. */ \n" + "push { r0-r1 } \n" + + "vmov r0, r1, d0 \n" + "cmp r0, #-1 \n" + "bne reg2_error_loopf \n" + "cmp r1, #1 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d1 \n" + "cmp r0, #2 \n" + "bne reg2_error_loopf \n" + "cmp r1, #3 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d2 \n" + "cmp r0, #4 \n" + "bne reg2_error_loopf \n" + "cmp r1, #5 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d3 \n" + "cmp r0, #6 \n" + "bne reg2_error_loopf \n" + "cmp r1, #7 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d4 \n" + "cmp r0, #8 \n" + "bne reg2_error_loopf \n" + "cmp r1, #9 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d5 \n" + "cmp r0, #10 \n" + "bne reg2_error_loopf \n" + "cmp r1, #11 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d6 \n" + "cmp r0, #-1 \n" + "bne reg2_error_loopf \n" + "cmp r1, #1 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d7 \n" + "cmp r0, #2 \n" + "bne reg2_error_loopf \n" + "cmp r1, #3 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d8 \n" + "cmp r0, #4 \n" + "bne reg2_error_loopf \n" + "cmp r1, #5 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d9 \n" + "cmp r0, #6 \n" + "bne reg2_error_loopf \n" + "cmp r1, #7 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d10 \n" + "cmp r0, #8 \n" + "bne reg2_error_loopf \n" + "cmp r1, #9 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d11 \n" + "cmp r0, #10 \n" + "bne reg2_error_loopf \n" + "cmp r1, #11 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d12 \n" + "cmp r0, #-1 \n" + "bne reg2_error_loopf \n" + "cmp r1, #1 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d13 \n" + "cmp r0, #2 \n" + "bne reg2_error_loopf \n" + "cmp r1, #3 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d14 \n" + "cmp r0, #4 \n" + "bne reg2_error_loopf \n" + "cmp r1, #5 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d15 \n" + "cmp r0, #6 \n" + "bne reg2_error_loopf \n" + "cmp r1, #7 \n" + "bne reg2_error_loopf \n" + + "/* Restore the registers that were clobbered by the test. */ \n" + "pop {r0-r1} \n" + + "/* VFP register test passed. Jump to the core register test. */ \n" + "b reg2_loopf_pass \n" + + "reg2_error_loopf: \n" + "/* If this line is hit then a VFP register value was found to be \n" + "incorrect. */ \n" + "b reg2_error_loopf \n" + + "reg2_loopf_pass: \n" + + "cmp r0, #-1 \n" + "bne reg2_error_loop \n" + "cmp r1, #1 \n" + "bne reg2_error_loop \n" + "cmp r2, #2 \n" + "bne reg2_error_loop \n" + "cmp r3, #3 \n" + "bne reg2_error_loop \n" + "cmp r4, #4 \n" + "bne reg2_error_loop \n" + "cmp r5, #5 \n" + "bne reg2_error_loop \n" + "cmp r6, #6 \n" + "bne reg2_error_loop \n" + "cmp r7, #7 \n" + "bne reg2_error_loop \n" + "cmp r8, #8 \n" + "bne reg2_error_loop \n" + "cmp r9, #9 \n" + "bne reg2_error_loop \n" + "cmp r10, #10 \n" + "bne reg2_error_loop \n" + "cmp r11, #11 \n" + "bne reg2_error_loop \n" + "cmp r12, #12 \n" + "bne reg2_error_loop \n" + + "/* Increment the loop counter to indicate this test is still functioning \n" + "correctly. */ \n" + "push { r0-r1 } \n" + "ldr r0, =ulRegTest2LoopCounter \n" + "ldr r1, [r0] \n" + "adds r1, r1, #1 \n" + "str r1, [r0] \n" + + "/* Yield to increase test coverage. */ \n" + "movs r0, #0x01 \n" + "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n" + "lsl r0, r0, #28 /* Shift to PendSV bit */ \n" + "str r0, [r1] \n" + "dsb \n" + + "pop { r0-r1 } \n" + + "/* Start again. */ \n" + "b reg2_loop \n" + + "reg2_error_loop: \n" + "/* If this line is hit then there was an error in a core register value. \n" + "This loop ensures the loop counter variable stops incrementing. */ \n" + "b reg2_error_loop \n" + ); /* __asm volatile */ +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/init_app.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/init_app.ini new file mode 100644 index 000000000..a98d32f13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/init_app.ini @@ -0,0 +1,8 @@ +//Initialization file for the application code +RESET +T +T +T +//eval PC = *(&(__isr_vector) + 1) ; // startup code loc to the Jump routine +eval PC = Reset_Handler; +T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/mem.ld b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/mem.ld new file mode 100644 index 000000000..f9b07a691 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/mem.ld @@ -0,0 +1,19 @@ +/* + * Memory Spaces Definitions. + * + * Need modifying for a specific board. + * FLASH.ORIGIN: starting address of flash + * FLASH.LENGTH: length of flash + * RAM.ORIGIN: starting address of RAM bank 0 + * RAM.LENGTH: length of RAM bank 0 + * + * The values below can be addressed in further linker scripts + * using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'. + */ + +MEMORY +{ + ROM (rx) : ORIGIN = 0x100000, LENGTH = 0x18000 + RAM (rw) : ORIGIN = 0x118000, LENGTH = 0x8000 +} + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld new file mode 100644 index 000000000..95e1da65d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/sections.ld @@ -0,0 +1,401 @@ +/* + * Default linker script for GCC MEC1322 + * Based upon linker scripts from GNU ARM Eclipse plug-in + */ + +INCLUDE mem.ld + +/* + * The '__stack' definition is required by crt0, do not remove it. + */ +/* Place top of stack immediate before ROM Log + *__stack = ORIGIN(RAM) + LENGTH(RAM); + */ +__stack = ORIGIN(RAM) + LENGTH(RAM); + +_estack = __stack; + +/* + * Default stack sizes. + * These are used by the startup in order to allocate stacks + * for the different modes. + */ + +__Main_Stack_Size = 2048 ; + +PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ; + +__Main_Stack_Limit = __stack - __Main_Stack_Size ; + +/*"PROVIDE" allows to easily override these values from an object file or the command line. */ +PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ; + +/* + * There will be a link error if there is not this amount of + * RAM free at the end. + */ +_Minimum_Stack_Size = 256 ; + +/* + * Default heap definitions. + * The heap start immediately after the last statically allocated + * .sbss/.noinit section, and extends up to the main stack limit. + */ +PROVIDE ( _Heap_Begin = _end_noinit ) ; +PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ; + +/* + * The entry point is informative, for debuggers and simulators, + * since the Cortex-M vector points to it anyway. + */ +ENTRY(_start) + +/* Sections Definitions */ + +SECTIONS +{ + /* + * For Cortex-M devices, the beginning of the startup code is stored in + * the .isr_vector section, which goes to ROM + */ + + .isr_vector : + { + . = ALIGN(4); + _isr_vector = .; + KEEP(*(.isr_vector)) + . = ALIGN(4); + } >ROM + + + .text : + { + . = ALIGN(4); + + /* + * This section is here for convenience, to store the + * startup code at the beginning of the flash area, hoping that + * this will increase the readability of the listing. + */ + KEEP(*(.after_vectors .after_vectors.*)) /* Startup code and ISR */ + + . = ALIGN(4); + + /* + * These are the old initialisation sections, intended to contain + * naked code, with the prologue/epilogue added by crti.o/crtn.o + * when linking with startup files. The standalone startup code + * currently does not run these, better use the init arrays below. + */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + + /* + * The preinit code, i.e. an array of pointers to initialisation + * functions to be performed before constructors. + */ + PROVIDE_HIDDEN (__preinit_array_start = .); + + /* + * Used to run the SystemInit() before anything else. + */ + KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*)) + + /* + * Used for other platform inits. + */ + KEEP(*(.preinit_array_platform .preinit_array_platform.*)) + + /* + * The application inits. If you need to enforce some order in + * execution, create new sections, as before. + */ + KEEP(*(.preinit_array .preinit_array.*)) + + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + + /* + * The init code, i.e. an array of pointers to static constructors. + */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + + /* + * The fini code, i.e. an array of pointers to static destructors. + */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + + . = ALIGN(4); + + *(.text*) /* all remaining code */ + + *(vtable) /* C++ virtual tables */ + + } >ROM + + .rodata : + { + *(.rodata*) /* read-only data (constants) */ + } >ROM + + .glue : + { + KEEP(*(.eh_frame*)) + + /* + * Stub sections generated by the linker, to glue together + * ARM and Thumb code. .glue_7 is used for ARM code calling + * Thumb code, and .glue_7t is used for Thumb code calling + * ARM code. Apparently always generated by the linker, for some + * architectures, so better leave them here. + */ + *(.glue_7) + *(.glue_7t) + } >ROM + + /* ARM magic sections */ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM + __exidx_end = .; + + . = ALIGN(4); + _etext = .; + __etext = .; + + /* + * This address is used by the startup code to + * initialise the .data section. + */ + _sidata = _etext; + + /* MEMORY_ARRAY */ + /* + .ROarraySection : + { + *(.ROarraySection .ROarraySection.*) + } >MEMORY_ARRAY + */ + /* + * The initialised data section. + * The program executes knowing that the data is in the RAM + * but the loader puts the initial values in the ROM (inidata). + * It is one task of the startup to copy the initial values from + * ROM to RAM. + */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + + /* This is used by the startup code to initialise the .data section */ + _sdata = . ; /* STM specific definition */ + __data_start__ = . ; + *(.data_begin .data_begin.*) + + *(.data .data.*) + + *(.data_end .data_end.*) + . = ALIGN(4); + + /* This is used by the startup code to initialise the .data section */ + _edata = . ; /* STM specific definition */ + __data_end__ = . ; + + } >RAM + + + /* + * The uninitialised data section. NOLOAD is used to avoid + * the "section `.bss' type changed to PROGBITS" warning + */ + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; /* standard newlib definition */ + _sbss = .; /* STM specific definition */ + *(.bss_begin .bss_begin.*) + + *(.bss .bss.*) + *(COMMON) + + *(.bss_end .bss_end.*) + . = ALIGN(4); + __bss_end__ = .; /* standard newlib definition */ + _ebss = . ; /* STM specific definition */ + } >RAM + + .noinit (NOLOAD) : + { + . = ALIGN(4); + _noinit = .; + + *(.noinit .noinit.*) + + . = ALIGN(4) ; + _end_noinit = .; + } > RAM + + /* Mandatory to be word aligned, _sbrk assumes this */ + PROVIDE ( end = _end_noinit ); /* was _ebss */ + PROVIDE ( _end = _end_noinit ); + PROVIDE ( __end = _end_noinit ); + PROVIDE ( __end__ = _end_noinit ); + PROVIDE ( ROM_DATA_START = __data_start__ ); + + /* + * Used for validation only, do not allocate anything here! + * + * This is just to check that there is enough RAM left for the Main + * stack. It should generate an error if it's full. + */ + ._check_stack : + { + . = ALIGN(4); + + . = . + _Minimum_Stack_Size ; + + . = ALIGN(4); + } >RAM + + ._check_rom_log : + { + . = ALIGN(4); + +/* . = . + __ROM_Log_Size ; */ + + . = ALIGN(4); + } >RAM + +/* + .bss_CCMRAM : ALIGN(4) + { + *(.bss.CCMRAM .bss.CCMRAM.*) + } > CCMRAM +*/ + /* + * The ROM Bank1. + * The C or assembly source must explicitly place the code + * or data there using the "section" attribute. + */ + + + /* remaining code */ + /* read-only data (constants) */ +/* + .b1text : + { + *(.b1text) + *(.b1rodata) + *(.b1rodata.*) + } >ROMB1 +*/ + /* + * The EXTMEM. + * The C or assembly source must explicitly place the code or data there + * using the "section" attribute. + */ + + /* EXTMEM Bank0 */ +/* + .eb0text : + { + *(.eb0text) + *(.eb0rodata) + *(.eb0rodata.*) + } >EXTMEMB0 +*/ + /* EXTMEM Bank1 */ +/* + .eb1text : + { + *(.eb1text) + *(.eb1rodata) + *(.eb1rodata.*) + } >EXTMEMB1 +*/ + /* EXTMEM Bank2 */ +/* + .eb2text : + { + *(.eb2text) + *(.eb2rodata) + *(.eb2rodata.*) + } >EXTMEMB2 +*/ + /* EXTMEM Bank0 */ +/* + .eb3text : + { + *(.eb3text) + *(.eb3rodata) + *(.eb3rodata.*) + } >EXTMEMB3 +*/ + + /* After that there are only debugging sections. */ + + /* This can remove the debugging information from the standard libraries */ + /* + DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S new file mode 100644 index 000000000..5178bec41 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S @@ -0,0 +1,383 @@ +/* File: startup_ARMCM4.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.0 + * Date: 16 August 2013 + * +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + .syntax unified + .arch armv7e-m + + .section .stack + .align 3 + + .equ ulMainStackSize, 200 * 4 + .equ Stack_Size, 0x004 + .globl __StackTop + .globl __StackLimit + .extern ulMainStack +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector,"a",%progbits + .global __Vectors + .type __Vectors, %object + .size __Vectors, .-__Vectors +__Vectors: + .long ulMainStack + ulMainStackSize /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long NVIC_Handler_I2C0 + .long NVIC_Handler_I2C1 + .long NVIC_Handler_I2C2 + .long NVIC_Handler_I2C3 + .long NVIC_Handler_DMA0 + .long NVIC_Handler_DMA1 + .long NVIC_Handler_DMA2 + .long NVIC_Handler_DMA3 + .long NVIC_Handler_DMA4 + .long NVIC_Handler_DMA5 + .long NVIC_Handler_DMA6 + .long NVIC_Handler_DMA7 + .long NVIC_Handler_LPCBERR + .long NVIC_Handler_UART0 + .long NVIC_Handler_IMAP0 + .long NVIC_Handler_EC0_IBF + .long NVIC_Handler_EC0_OBF + .long NVIC_Handler_EC1_IBF + .long NVIC_Handler_EC1_OBF + .long NVIC_Handler_PM1_CTL + .long NVIC_Handler_PM1_EN + .long NVIC_Handler_PM1_STS + .long NVIC_Handler_MIF8042_OBF + .long NVIC_Handler_MIF8042_IBF + .long NVIC_Handler_MAILBOX + .long NVIC_Handler_PECI + .long NVIC_Handler_TACH0 + .long NVIC_Handler_TACH1 + .long NVIC_Handler_ADC_SNGL + .long NVIC_Handler_ADC_RPT + .long NVIC_Handler_V2P_INT0 + .long NVIC_Handler_V2P_INT1 + .long NVIC_Handler_PS2_CH0 + .long NVIC_Handler_PS2_CH1 + .long NVIC_Handler_PS2_CH2 + .long NVIC_Handler_PS2_CH3 + .long NVIC_Handler_SPI0_TX + .long NVIC_Handler_SPI0_RX + .long NVIC_Handler_HIB_TMR + .long NVIC_Handler_KEY_INT + .long NVIC_Handler_KEY_WAKE + .long NVIC_Handler_RPM_STALL + .long NVIC_Handler_RPM_SPIN + .long NVIC_Handler_VBAT + .long NVIC_Handler_LED0 + .long NVIC_Handler_LED1 + .long NVIC_Handler_LED2 + .long NVIC_Handler_MBC_ERR + .long NVIC_Handler_MBC_BUSY + .long NVIC_Handler_TMR0 + .long NVIC_Handler_TMR1 + .long NVIC_Handler_TMR2 + .long NVIC_Handler_TMR3 + .long NVIC_Handler_TMR4 + .long NVIC_Handler_TMR5 + .long NVIC_Handler_SPI1_TX + .long NVIC_Handler_SPI1_RX + .long NVIC_Handler_GIRQ08 + .long NVIC_Handler_GIRQ09 + .long NVIC_Handler_GIRQ10 + .long NVIC_Handler_GIRQ11 + ;.long NVIC_Handler_GIRQ12 + .long interrupt_irq12 + ;.long NVIC_Handler_GIRQ13 + .long NVIC_Handler_GIRQ13 + .long NVIC_Handler_GIRQ14 + .long NVIC_Handler_GIRQ15 + .long NVIC_Handler_GIRQ16 + .long NVIC_Handler_GIRQ17 + .long NVIC_Handler_GIRQ18 + .long NVIC_Handler_GIRQ19 + .long NVIC_Handler_GIRQ20 + .long NVIC_Handler_GIRQ21 + .long NVIC_Handler_GIRQ22 + .long NVIC_Handler_GIRQ23 + .long NVIC_Handler_073 + .long NVIC_Handler_074 + .long NVIC_Handler_075 + .long NVIC_Handler_076 + .long NVIC_Handler_077 + .long NVIC_Handler_078 + .long NVIC_Handler_079 + .long NVIC_Handler_080 + .long NVIC_Handler_DMA8 + .long NVIC_Handler_DMA9 + .long NVIC_Handler_DMA10 + .long NVIC_Handler_DMA11 + .long NVIC_Handler_LED3 + .long NVIC_Handler_PKE_ERR + .long NVIC_Handler_PKE_END + .long NVIC_Handler_TRNG + .long NVIC_Handler_AES + .long NVIC_Handler_HASH + + + .text + .thumb + .thumb_func + .align 2 + .globl _start + .extern main + .globl Reset_Handler + .type Reset_Handler, %function +_start: +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr sp, =ulMainStack + ulMainStackSize + sub sp, sp, #4 + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ + + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 + +#ifndef __NO_SYSTEM_INIT +/* bl SystemInit */ +#endif + + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler +/* def_irq_handler SVC_Handler */ + def_irq_handler DebugMon_Handler +/* def_irq_handler PendSV_Handler */ +/* def_irq_handler SysTick_Handler */ + def_irq_handler DEF_IRQHandler + + def_irq_handler NVIC_Handler_I2C0 + def_irq_handler NVIC_Handler_I2C1 + def_irq_handler NVIC_Handler_I2C2 + def_irq_handler NVIC_Handler_I2C3 + def_irq_handler NVIC_Handler_DMA0 + def_irq_handler NVIC_Handler_DMA1 + def_irq_handler NVIC_Handler_DMA2 + def_irq_handler NVIC_Handler_DMA3 + def_irq_handler NVIC_Handler_DMA4 + def_irq_handler NVIC_Handler_DMA5 + def_irq_handler NVIC_Handler_DMA6 + def_irq_handler NVIC_Handler_DMA7 + def_irq_handler NVIC_Handler_LPCBERR + def_irq_handler NVIC_Handler_UART0 + def_irq_handler NVIC_Handler_IMAP0 + def_irq_handler NVIC_Handler_EC0_IBF + def_irq_handler NVIC_Handler_EC0_OBF + def_irq_handler NVIC_Handler_EC1_IBF + def_irq_handler NVIC_Handler_EC1_OBF + def_irq_handler NVIC_Handler_PM1_CTL + def_irq_handler NVIC_Handler_PM1_EN + def_irq_handler NVIC_Handler_PM1_STS + def_irq_handler NVIC_Handler_MIF8042_OBF + def_irq_handler NVIC_Handler_MIF8042_IBF + def_irq_handler NVIC_Handler_MAILBOX + def_irq_handler NVIC_Handler_PECI + def_irq_handler NVIC_Handler_TACH0 + def_irq_handler NVIC_Handler_TACH1 + def_irq_handler NVIC_Handler_ADC_SNGL + def_irq_handler NVIC_Handler_ADC_RPT + def_irq_handler NVIC_Handler_V2P_INT0 + def_irq_handler NVIC_Handler_V2P_INT1 + def_irq_handler NVIC_Handler_PS2_CH0 + def_irq_handler NVIC_Handler_PS2_CH1 + def_irq_handler NVIC_Handler_PS2_CH2 + def_irq_handler NVIC_Handler_PS2_CH3 + def_irq_handler NVIC_Handler_SPI0_TX + def_irq_handler NVIC_Handler_SPI0_RX + def_irq_handler NVIC_Handler_HIB_TMR + def_irq_handler NVIC_Handler_KEY_INT + def_irq_handler NVIC_Handler_KEY_WAKE + def_irq_handler NVIC_Handler_RPM_STALL + def_irq_handler NVIC_Handler_RPM_SPIN + def_irq_handler NVIC_Handler_VBAT + def_irq_handler NVIC_Handler_LED0 + def_irq_handler NVIC_Handler_LED1 + def_irq_handler NVIC_Handler_LED2 + def_irq_handler NVIC_Handler_MBC_ERR + def_irq_handler NVIC_Handler_MBC_BUSY + def_irq_handler NVIC_Handler_TMR0 + def_irq_handler NVIC_Handler_TMR1 + def_irq_handler NVIC_Handler_TMR2 + def_irq_handler NVIC_Handler_TMR3 + def_irq_handler NVIC_Handler_TMR4 + def_irq_handler NVIC_Handler_TMR5 + def_irq_handler NVIC_Handler_SPI1_TX + def_irq_handler NVIC_Handler_SPI1_RX + def_irq_handler NVIC_Handler_GIRQ08 + def_irq_handler NVIC_Handler_GIRQ09 + def_irq_handler NVIC_Handler_GIRQ10 + def_irq_handler NVIC_Handler_GIRQ11 + ;def_irq_handler NVIC_Handler_GIRQ12 + def_irq_handler interrupt_irq12 + ;def_irq_handler NVIC_Handler_GIRQ13 + def_irq_handler interrupt_irq13 + def_irq_handler NVIC_Handler_GIRQ14 + def_irq_handler NVIC_Handler_GIRQ15 + def_irq_handler NVIC_Handler_GIRQ16 + def_irq_handler NVIC_Handler_GIRQ17 + def_irq_handler NVIC_Handler_GIRQ18 + def_irq_handler NVIC_Handler_GIRQ19 + def_irq_handler NVIC_Handler_GIRQ20 + def_irq_handler NVIC_Handler_GIRQ21 + def_irq_handler NVIC_Handler_GIRQ22 + def_irq_handler NVIC_Handler_GIRQ23 + def_irq_handler NVIC_Handler_073 + def_irq_handler NVIC_Handler_074 + def_irq_handler NVIC_Handler_075 + def_irq_handler NVIC_Handler_076 + def_irq_handler NVIC_Handler_077 + def_irq_handler NVIC_Handler_078 + def_irq_handler NVIC_Handler_079 + def_irq_handler NVIC_Handler_080 + def_irq_handler NVIC_Handler_DMA8 + def_irq_handler NVIC_Handler_DMA9 + def_irq_handler NVIC_Handler_DMA10 + def_irq_handler NVIC_Handler_DMA11 + def_irq_handler NVIC_Handler_LED3 + def_irq_handler NVIC_Handler_PKE_ERR + def_irq_handler NVIC_Handler_PKE_END + def_irq_handler NVIC_Handler_TRNG + def_irq_handler NVIC_Handler_AES + def_irq_handler NVIC_Handler_HASH + + .end diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c new file mode 100644 index 000000000..9ecd3201d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/system.c @@ -0,0 +1,79 @@ +/**************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*/ + +/** @defgroup pwm pwm_c_wrapper + * @{ + */ +/** @file pwm_c_wrapper.cpp + \brief the pwm component C wrapper + This program is designed to allow the other C programs to be able to use this component + + There are entry points for all C wrapper API implementation + +Platform: This is ARC-based component + +Toolset: Metaware IDE(8.5.1) +Reference: smsc_reusable_fw_requirement.doc */ + +/******************************************************************************* + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2015/12/23 15:37:58 $ + * AUTHOR: $Author: akrishnan $ + * + * Revision history (latest first): + * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) + * #2 2011/03/25 martin_y support FPGA build 058 apps + * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200 + *********************************************************************************** + */ +/* Imported Header File */ +//#include "common.h" +//#include "build.h" +#include + +#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 +#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) +#define CPU_CLOCK_DIVIDER 1 + +/* The start up code is configured to use the following array as the stack used +by main(), which will then also get used by FreeRTOS interrupt handlers after +the scheduler has been started. */ +#warning If the array size is modified here then ulMainStackSize must also be modified in startup_ARMCM4.S. +volatile uint32_t ulMainStack[ 200 ]; + +/******************************************************************************/ +/** system_set_ec_clock +* Set CPU speed +* @param void +* @return void +*******************************************************************************/ + +void system_set_ec_clock(void) +{ + + /* Set ARC CPU Clock Divider to determine the CPU speed */ + /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */ + MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER; + +} /* End system_set_ec_clock() */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/JLinkLog.txt b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/JLinkLog.txt new file mode 100644 index 000000000..d6b5ccdce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/JLinkLog.txt @@ -0,0 +1,492 @@ + +T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total) +T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total) +T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total) +T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total) +T220C 000:298 JLINK_OpenEx(...) +Firmware: J-Link V9 compiled Oct 9 2015 20:34:47 +Hardware: V9.10 +S/N: 59101789 +Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total) +T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total) +T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total) +T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total) +T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) +T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total) +T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total) +T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total) +T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total) +T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total) +T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total) +T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) + -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) + -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0) +ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total) +T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total) +T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total) +T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total) +T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total) +T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total) +T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total) +T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total) +T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total) +T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total) +T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total) +T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total) +T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total) +T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total) +T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total) +T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total) +T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total) +T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total) +T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total) +T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total) +T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total) +T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total) +T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total) +T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) + -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) + -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total) +T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total) +T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total) +T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total) +T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total) +T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total) +T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total) +T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total) +T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total) +T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total) +T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total) +T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total) +T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total) +T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total) +T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total) +T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total) +T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total) +T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total) +T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total) +T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total) +T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total) +T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total) +T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total) +T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total) +T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total) +T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total) +T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total) +T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total) +T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total) +T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total) +T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total) +T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total) +T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) +T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total) +T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total) +T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total) +T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total) +T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total) +T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total) +T220C 027:508 (0005ms, 2544ms total) +T220C 027:508 Closed (0005ms, 2544ms total) diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/JLinkSettings.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/JLinkSettings.ini new file mode 100644 index 000000000..706cf39a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/JLinkSettings.ini @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Unspecified" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.sct b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.sct new file mode 100644 index 000000000..fe37a40a3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.sct @@ -0,0 +1,28 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + + +LR_IROM1 0x00100000 0x00020000 { ; load region size_region + ER_IROM1 0x00000000 0x00000000 { ; load address = execution address + } + RW_IRAM1 0x00100000 0x00020000 { ; RW data + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+RW +ZI) + } +} + + +;LR_IROM1 0x00100000 0x00018000 { ; load region size_region +; ER_IROM1 0x00100000 0x00018000 { ; load address = execution address +; *.o (RESET, +First) +; *(InRoot$$Sections) +; .ANY (+RO) +; } +; RW_IRAM1 0x00118000 0x00008000 { ; RW data +; .ANY (+RW +ZI) +; } +;} + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx new file mode 100644 index 000000000..f4f0cce03 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvoptx @@ -0,0 +1,622 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RTOSDemo + 0x4 + ARM-ADS + + 48000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + + + + + + + + + + init_app.ini + BIN\UL2CM3.DLL + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + -UV1115SAE -O2983 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0100000 -FL018000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM) + + + + + + 0 + 1 + ulLED,0x0A + + + + + 1 + 2 + 0xe000e284 + 4 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + + 0 + + + + + System + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\startup_CEC1302.s + startup_CEC1302.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\system.c + system.c + 0 + 0 + + + + + main_and_config + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\main.c + main.c + 0 + 0 + + + 2 + 4 + 5 + 0 + 0 + 0 + ..\FreeRTOSConfig.h + FreeRTOSConfig.h + 0 + 0 + + + + + FreeRTOS_Source + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\Source\event_groups.c + event_groups.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\Source\list.c + list.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\Source\queue.c + queue.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\Source\tasks.c + tasks.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\Source\timers.c + timers.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\Source\portable\MemMang\heap_4.c + heap_4.c + 0 + 0 + + + 3 + 11 + 1 + 1 + 0 + 0 + ..\..\..\Source\portable\RVDS\ARM_CM4F\port.c + port.c + 0 + 0 + + + + + main_low_power + 0 + 0 + 0 + 0 + + 4 + 12 + 1 + 0 + 0 + 0 + ..\main_low_power\main_low_power.c + main_low_power.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\main_low_power\low_power_tick_config.c + low_power_tick_config.c + 0 + 0 + + + + + main_full + 0 + 0 + 0 + 0 + + 5 + 14 + 1 + 1 + 0 + 0 + ..\main_full\main_full.c + main_full.c + 0 + 0 + + + 5 + 15 + 1 + 0 + 0 + 0 + .\RegTest.c + RegTest.c + 0 + 0 + + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\flop.c + flop.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\EventGroupsDemo.c + EventGroupsDemo.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\TaskNotify.c + TaskNotify.c + 0 + 0 + + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\blocktim.c + blocktim.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\dynamic.c + dynamic.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\GenQTest.c + GenQTest.c + 0 + 0 + + + 5 + 22 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\TimerDemo.c + TimerDemo.c + 0 + 0 + + + 5 + 23 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\IntQueue.c + IntQueue.c + 0 + 0 + + + 5 + 24 + 1 + 0 + 0 + 0 + ..\main_full\IntQueueTimer.c + IntQueueTimer.c + 0 + 0 + + + 5 + 25 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\countsem.c + countsem.c + 0 + 0 + + + 5 + 26 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\semtest.c + semtest.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\Common\Minimal\death.c + death.c + 0 + 0 + + + + + peripheral_library + 0 + 0 + 0 + 0 + + 6 + 28 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_api.c + btimer_api.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\peripheral_library\basic_timer\btimer_perphl.c + btimer_perphl.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\peripheral_library\pcr\pcr_perphl.c + pcr_perphl.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\peripheral_library\pcr\pcr_api.c + pcr_api.c + 0 + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx new file mode 100644 index 000000000..c0cb1e1eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RTOSDemo.uvprojx @@ -0,0 +1,628 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RTOSDemo + 0x4 + ARM-ADS + 5060061::V5.06 update 1 (build 61)::ARMCC + + + ARMCM4_FP + ARM + ARM.CMSIS.4.5.0 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + RTOSDemo + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x100000 + 0x18000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x118000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + RTOSDemo.sct + + + + + + + + + + + System + + + startup_CEC1302.s + 2 + .\startup_CEC1302.s + + + system.c + 1 + .\system.c + + + + + main_and_config + + + main.c + 1 + ..\main.c + + + FreeRTOSConfig.h + 5 + ..\FreeRTOSConfig.h + + + + + FreeRTOS_Source + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 0 + 0 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + event_groups.c + 1 + ..\..\..\Source\event_groups.c + + + list.c + 1 + ..\..\..\Source\list.c + + + queue.c + 1 + ..\..\..\Source\queue.c + + + tasks.c + 1 + ..\..\..\Source\tasks.c + + + timers.c + 1 + ..\..\..\Source\timers.c + + + heap_4.c + 1 + ..\..\..\Source\portable\MemMang\heap_4.c + + + port.c + 1 + ..\..\..\Source\portable\RVDS\ARM_CM4F\port.c + + + + + main_low_power + + + main_low_power.c + 1 + ..\main_low_power\main_low_power.c + + + low_power_tick_config.c + 1 + ..\main_low_power\low_power_tick_config.c + + + + + main_full + + + main_full.c + 1 + ..\main_full\main_full.c + + + RegTest.c + 1 + .\RegTest.c + + + flop.c + 1 + ..\..\Common\Minimal\flop.c + + + EventGroupsDemo.c + 1 + ..\..\Common\Minimal\EventGroupsDemo.c + + + TaskNotify.c + 1 + ..\..\Common\Minimal\TaskNotify.c + + + blocktim.c + 1 + ..\..\Common\Minimal\blocktim.c + + + dynamic.c + 1 + ..\..\Common\Minimal\dynamic.c + + + GenQTest.c + 1 + ..\..\Common\Minimal\GenQTest.c + + + TimerDemo.c + 1 + ..\..\Common\Minimal\TimerDemo.c + + + IntQueue.c + 1 + ..\..\Common\Minimal\IntQueue.c + + + IntQueueTimer.c + 1 + ..\main_full\IntQueueTimer.c + + + countsem.c + 1 + ..\..\Common\Minimal\countsem.c + + + semtest.c + 1 + ..\..\Common\Minimal\semtest.c + + + death.c + 1 + ..\..\Common\Minimal\death.c + + + + + peripheral_library + + + btimer_api.c + 1 + ..\peripheral_library\basic_timer\btimer_api.c + + + btimer_perphl.c + 1 + ..\peripheral_library\basic_timer\btimer_perphl.c + + + pcr_perphl.c + 1 + ..\peripheral_library\pcr\pcr_perphl.c + + + pcr_api.c + 1 + ..\peripheral_library\pcr\pcr_api.c + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c new file mode 100644 index 000000000..e0bd936d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/RegTest.c @@ -0,0 +1,454 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + + +__asm void vRegTest1Implementation( void ) +{ + PRESERVE8 + IMPORT ulRegTest1LoopCounter + + /* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the VFP registers with known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg1_loop + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop +} +/*-----------------------------------------------------------*/ + +__asm void vRegTest2Implementation( void ) +{ + PRESERVE8 + IMPORT ulRegTest2LoopCounter + + /* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + + /* Set all the VFP to known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg2_loop + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/init_app.ini b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/init_app.ini new file mode 100644 index 000000000..6a0e39168 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/init_app.ini @@ -0,0 +1,7 @@ +//Initialization file for the application code +RESET +T +T +T +eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine +T diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s new file mode 100644 index 000000000..17984f30e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/startup_CEC1302.s @@ -0,0 +1,496 @@ +;/* +;****************************************************************************** +;* © 2013 Microchip Technology Inc. and its subsidiaries. +;* You may use this software and any derivatives exclusively with +;* Microchip products. +;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +;* OF THESE TERMS. +;****************************************************************************** +; */ +;/** @file startup_MEC1322.s +; *MEC1322 API Test: startup and vector table +; */ +;/** @defgroup startup_MEC1322 +; * @{ +; */ + + IMPORT __main + IMPORT |Image$$RW_IRAM1$$Base| + IMPORT |Image$$RW_IRAM1$$Limit| + IMPORT |Image$$RW_IRAM1$$Length| + IMPORT |Image$$RW_IRAM1$$ZI$$Base| + IMPORT |Image$$RW_IRAM1$$ZI$$Limit| + IMPORT |Image$$ER_IROM1$$Base| + IMPORT |Image$$ER_IROM1$$Limit| + IMPORT main + IMPORT system_set_ec_clock + + EXPORT Reset_Handler + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __stack_bottom +__stack_bottom +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __tx_vectors +__tx_vectors +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; MEC1322 External Interrupts + DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0 + DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1 + DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2 + DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3 + DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0 + DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1 + DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2 + DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3 + DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4 + DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5 + DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6 + DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7 + DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error + DCD NVIC_Handler_UART0 ; 74h: 13, UART0 + DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0 + DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF + DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF + DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF + DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF + DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL + DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN + DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS + DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF + DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF + DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox + DCD NVIC_Handler_PECI ; A4h: 25, PECI + DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0 + DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1 + DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL + DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT + DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0 + DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1 + DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0 + DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1 + DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2 + DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3 + DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX + DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX + DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR + DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT + DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE + DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL + DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN + DCD NVIC_Handler_VBAT ; ECh: 43, VBAT + DCD NVIC_Handler_LED0 ; F0h: 44, LED0 + DCD NVIC_Handler_LED1 ; F4h: 45, LED1 + DCD NVIC_Handler_LED2 ; F8h: 46, LED2 + DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR + DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY + DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0 + DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1 + DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2 + DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3 + DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4 + DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5 + DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX + DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX + DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08 + DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09 + DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10 + DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11 + DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12 + DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13 + DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14 + DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15 + DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16 + DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17 + DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18 + DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19 + DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20 + DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21 + DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22 + DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23 + DCD NVIC_Handler_073 ; 164h: 73, unknown + DCD NVIC_Handler_074 ; 168h: 74, unknown + DCD NVIC_Handler_075 ; 16Ch: 75, unknown + DCD NVIC_Handler_076 ; 170h: 76, unknown + DCD NVIC_Handler_077 ; 174h: 77, unknown + DCD NVIC_Handler_078 ; 178h: 78, unknown + DCD NVIC_Handler_079 ; 17Ch: 79, unknown + DCD NVIC_Handler_080 ; 180h: 80, unknown + DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8 + DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9 + DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10 + DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11 + DCD NVIC_Handler_LED3 ; 194h: 85, LED3 + DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error + DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End + DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen + DCD NVIC_Handler_AES ; 1A4h: 89, AES + DCD NVIC_Handler_HASH ; 1A8h: 90, HASH + + + AREA ROMTABLE, CODE, READONLY + THUMB +; ---------- ROM API ---------- +; Jump table to ROM API C functions +; +; +; ---------- ROM API End ------ +; Reset Handler + + AREA |.text|, CODE, READONLY + THUMB + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + + CPSID i + + ; support code is loaded from ROM loader + LDR SP, =__initial_sp + ; configure CPU speed + LDR R0, =system_set_ec_clock + BLX R0 + + LDR SP, =__initial_sp + + ; support FPU + IF {CPU} = "Cortex-M4.fp" + LDR R0, =0xE000ED88 ; Enable CP10,CP11 + LDR R1,[R0] + ORR R1,R1,#(0xF << 20) + STR R1,[R0] + ENDIF + + ; Enter Keil startup code which calls our main + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + MOV R7,#1 + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + MOV R7,#2 + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + MOV R7,#3 + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + MOV R7,#4 + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + MOV R7,#5 + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + MOV R7,#6 + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + MOV R7,#7 + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + MOV R7,#8 + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + MOV R7,#9 + B . + ENDP + +Default_Handler PROC + + ; External MEC1322 NVIC Interrupt Inputs + EXPORT NVIC_Handler_I2C0 [WEAK] + EXPORT NVIC_Handler_I2C1 [WEAK] + EXPORT NVIC_Handler_I2C2 [WEAK] + EXPORT NVIC_Handler_I2C3 [WEAK] + EXPORT NVIC_Handler_DMA0 [WEAK] + EXPORT NVIC_Handler_DMA1 [WEAK] + EXPORT NVIC_Handler_DMA2 [WEAK] + EXPORT NVIC_Handler_DMA3 [WEAK] + EXPORT NVIC_Handler_DMA4 [WEAK] + EXPORT NVIC_Handler_DMA5 [WEAK] + EXPORT NVIC_Handler_DMA6 [WEAK] + EXPORT NVIC_Handler_DMA7 [WEAK] + EXPORT NVIC_Handler_LPCBERR [WEAK] + EXPORT NVIC_Handler_UART0 [WEAK] + EXPORT NVIC_Handler_IMAP0 [WEAK] + EXPORT NVIC_Handler_EC0_IBF [WEAK] + EXPORT NVIC_Handler_EC0_OBF [WEAK] + EXPORT NVIC_Handler_EC1_IBF [WEAK] + EXPORT NVIC_Handler_EC1_OBF [WEAK] + EXPORT NVIC_Handler_PM1_CTL [WEAK] + EXPORT NVIC_Handler_PM1_EN [WEAK] + EXPORT NVIC_Handler_PM1_STS [WEAK] + EXPORT NVIC_Handler_MIF8042_OBF [WEAK] + EXPORT NVIC_Handler_MIF8042_IBF [WEAK] + EXPORT NVIC_Handler_MAILBOX [WEAK] + EXPORT NVIC_Handler_PECI [WEAK] + EXPORT NVIC_Handler_TACH0 [WEAK] + EXPORT NVIC_Handler_TACH1 [WEAK] + EXPORT NVIC_Handler_ADC_SNGL [WEAK] + EXPORT NVIC_Handler_ADC_RPT [WEAK] + EXPORT NVIC_Handler_V2P_INT0 [WEAK] + EXPORT NVIC_Handler_V2P_INT1 [WEAK] + EXPORT NVIC_Handler_PS2_CH0 [WEAK] + EXPORT NVIC_Handler_PS2_CH1 [WEAK] + EXPORT NVIC_Handler_PS2_CH2 [WEAK] + EXPORT NVIC_Handler_PS2_CH3 [WEAK] + EXPORT NVIC_Handler_SPI0_TX [WEAK] + EXPORT NVIC_Handler_SPI0_RX [WEAK] + EXPORT NVIC_Handler_HIB_TMR [WEAK] + EXPORT NVIC_Handler_KEY_INT [WEAK] + EXPORT NVIC_Handler_KEY_WAKE [WEAK] + EXPORT NVIC_Handler_RPM_STALL [WEAK] + EXPORT NVIC_Handler_RPM_SPIN [WEAK] + EXPORT NVIC_Handler_VBAT [WEAK] + EXPORT NVIC_Handler_LED0 [WEAK] + EXPORT NVIC_Handler_LED1 [WEAK] + EXPORT NVIC_Handler_LED2 [WEAK] + EXPORT NVIC_Handler_MBC_ERR [WEAK] + EXPORT NVIC_Handler_MBC_BUSY [WEAK] + EXPORT NVIC_Handler_TMR0 [WEAK] + EXPORT NVIC_Handler_TMR1 [WEAK] + EXPORT NVIC_Handler_TMR2 [WEAK] + EXPORT NVIC_Handler_TMR3 [WEAK] + EXPORT NVIC_Handler_TMR4 [WEAK] + EXPORT NVIC_Handler_TMR5 [WEAK] + EXPORT NVIC_Handler_SPI1_TX [WEAK] + EXPORT NVIC_Handler_SPI1_RX [WEAK] + EXPORT NVIC_Handler_GIRQ08 [WEAK] + EXPORT NVIC_Handler_GIRQ09 [WEAK] + EXPORT NVIC_Handler_GIRQ10 [WEAK] + EXPORT NVIC_Handler_GIRQ11 [WEAK] + EXPORT NVIC_Handler_GIRQ12 [WEAK] + EXPORT NVIC_Handler_GIRQ13 [WEAK] + EXPORT NVIC_Handler_GIRQ14 [WEAK] + EXPORT NVIC_Handler_GIRQ15 [WEAK] + EXPORT NVIC_Handler_GIRQ16 [WEAK] + EXPORT NVIC_Handler_GIRQ17 [WEAK] + EXPORT NVIC_Handler_GIRQ18 [WEAK] + EXPORT NVIC_Handler_GIRQ19 [WEAK] + EXPORT NVIC_Handler_GIRQ20 [WEAK] + EXPORT NVIC_Handler_GIRQ21 [WEAK] + EXPORT NVIC_Handler_GIRQ22 [WEAK] + EXPORT NVIC_Handler_GIRQ23 [WEAK] + EXPORT NVIC_Handler_073 [WEAK] + EXPORT NVIC_Handler_074 [WEAK] + EXPORT NVIC_Handler_075 [WEAK] + EXPORT NVIC_Handler_076 [WEAK] + EXPORT NVIC_Handler_077 [WEAK] + EXPORT NVIC_Handler_078 [WEAK] + EXPORT NVIC_Handler_079 [WEAK] + EXPORT NVIC_Handler_080 [WEAK] + EXPORT NVIC_Handler_DMA8 [WEAK] + EXPORT NVIC_Handler_DMA9 [WEAK] + EXPORT NVIC_Handler_DMA10 [WEAK] + EXPORT NVIC_Handler_DMA11 [WEAK] + EXPORT NVIC_Handler_LED3 [WEAK] + EXPORT NVIC_Handler_PKE_ERR [WEAK] + EXPORT NVIC_Handler_PKE_END [WEAK] + EXPORT NVIC_Handler_TRNG [WEAK] + EXPORT NVIC_Handler_AES [WEAK] + EXPORT NVIC_Handler_HASH [WEAK] + +NVIC_Handler_I2C0 +NVIC_Handler_I2C1 +NVIC_Handler_I2C2 +NVIC_Handler_I2C3 +NVIC_Handler_DMA0 +NVIC_Handler_DMA1 +NVIC_Handler_DMA2 +NVIC_Handler_DMA3 +NVIC_Handler_DMA4 +NVIC_Handler_DMA5 +NVIC_Handler_DMA6 +NVIC_Handler_DMA7 +NVIC_Handler_LPCBERR +NVIC_Handler_UART0 +NVIC_Handler_IMAP0 +NVIC_Handler_EC0_IBF +NVIC_Handler_EC0_OBF +NVIC_Handler_EC1_IBF +NVIC_Handler_EC1_OBF +NVIC_Handler_PM1_CTL +NVIC_Handler_PM1_EN +NVIC_Handler_PM1_STS +NVIC_Handler_MIF8042_OBF +NVIC_Handler_MIF8042_IBF +NVIC_Handler_MAILBOX +NVIC_Handler_PECI +NVIC_Handler_TACH0 +NVIC_Handler_TACH1 +NVIC_Handler_ADC_SNGL +NVIC_Handler_ADC_RPT +NVIC_Handler_V2P_INT0 +NVIC_Handler_V2P_INT1 +NVIC_Handler_PS2_CH0 +NVIC_Handler_PS2_CH1 +NVIC_Handler_PS2_CH2 +NVIC_Handler_PS2_CH3 +NVIC_Handler_SPI0_TX +NVIC_Handler_SPI0_RX +NVIC_Handler_HIB_TMR +NVIC_Handler_KEY_INT +NVIC_Handler_KEY_WAKE +NVIC_Handler_RPM_STALL +NVIC_Handler_RPM_SPIN +NVIC_Handler_VBAT +NVIC_Handler_LED0 +NVIC_Handler_LED1 +NVIC_Handler_LED2 +NVIC_Handler_MBC_ERR +NVIC_Handler_MBC_BUSY +NVIC_Handler_TMR0 +NVIC_Handler_TMR1 +NVIC_Handler_TMR2 +NVIC_Handler_TMR3 +NVIC_Handler_TMR4 +NVIC_Handler_TMR5 +NVIC_Handler_SPI1_TX +NVIC_Handler_SPI1_RX +NVIC_Handler_GIRQ08 +NVIC_Handler_GIRQ09 +NVIC_Handler_GIRQ10 +NVIC_Handler_GIRQ11 +NVIC_Handler_GIRQ12 +NVIC_Handler_GIRQ13 +NVIC_Handler_GIRQ14 +NVIC_Handler_GIRQ15 +NVIC_Handler_GIRQ16 +NVIC_Handler_GIRQ17 +NVIC_Handler_GIRQ18 +NVIC_Handler_GIRQ19 +NVIC_Handler_GIRQ20 +NVIC_Handler_GIRQ21 +NVIC_Handler_GIRQ22 +NVIC_Handler_GIRQ23 +NVIC_Handler_073 +NVIC_Handler_074 +NVIC_Handler_075 +NVIC_Handler_076 +NVIC_Handler_077 +NVIC_Handler_078 +NVIC_Handler_079 +NVIC_Handler_080 +NVIC_Handler_DMA8 +NVIC_Handler_DMA9 +NVIC_Handler_DMA10 +NVIC_Handler_DMA11 +NVIC_Handler_LED3 +NVIC_Handler_PKE_ERR +NVIC_Handler_PKE_END +NVIC_Handler_TRNG +NVIC_Handler_AES +NVIC_Handler_HASH + B . + + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + EXPORT __stack_bottom + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;/** @} +; */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/system.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/system.c new file mode 100644 index 000000000..a41b64f3b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/Keil_Specific/system.c @@ -0,0 +1,73 @@ +/**************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*/ + +/** @defgroup pwm pwm_c_wrapper + * @{ + */ +/** @file pwm_c_wrapper.cpp + \brief the pwm component C wrapper + This program is designed to allow the other C programs to be able to use this component + + There are entry points for all C wrapper API implementation + +Platform: This is ARC-based component + +Toolset: Metaware IDE(8.5.1) +Reference: smsc_reusable_fw_requirement.doc */ + +/******************************************************************************* + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2015/12/23 15:37:58 $ + * AUTHOR: $Author: akrishnan $ + * + * Revision history (latest first): + * #3 2011/05/09 martin_y update to Metaware IDE(8.5.1) + * #2 2011/03/25 martin_y support FPGA build 058 apps + * #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200 + *********************************************************************************** + */ +/* Imported Header File */ +//#include "common.h" +//#include "build.h" +#include + +#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 +#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) +#define CPU_CLOCK_DIVIDER 1 + +/******************************************************************************/ +/** system_set_ec_clock +* Set CPU speed +* @param void +* @return void +*******************************************************************************/ + +void system_set_ec_clock(void) +{ + + /* Set ARC CPU Clock Divider to determine the CPU speed */ + /* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */ + MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER; + +} /* End system_set_ec_clock() */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c new file mode 100644 index 000000000..37ada5990 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main.c @@ -0,0 +1,286 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project + * that demonstrates low power tickless functionality, and a more comprehensive + * test and demo application. The configCREATE_LOW_POWER_DEMO setting, which is + * defined in FreeRTOSConfig.h, is used to select between the two. The simply + * blinky low power demo is implemented and described in main_low_power.c. The + * more comprehensive test and demo application is implemented and described in + * main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and standard FreeRTOS hook functions. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware register addresses. */ +#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 ) +#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 ) + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1. + * main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0. + */ +#if( configCREATE_LOW_POWER_DEMO == 1 ) + + extern void main_low_power( void ); + +#else + + extern void main_full( void ); + + /* Some of the tests and examples executed as part of the full demo make use + of the tick hook to call API functions from an interrupt context. */ + extern void vFullDemoTickHook( void ); + +#endif /* #if configCREATE_LOW_POWER_DEMO == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* The variable that is incremented to represent each LED toggle. On the +clicker hardware the LED state is set to the value of the least significant bit +of this variable. On other hardware, where an LED is not used, the LED just +keeps a count of the number of times the LED would otherwise have been toggled. +See the comments in main_low_power.c and main_full.c for information on the +expected LED toggle rate). */ +volatile uint32_t ulLED = 0; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The configCREATE_LOW_POWER_DEMO setting is described at the top + of this file. */ + #if( configCREATE_LOW_POWER_DEMO == 1 ) + { + main_low_power(); + } + #else + { + main_full(); + } + #endif + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +extern void system_set_ec_clock( void ); +extern unsigned long __Vectors[]; + + /* Disable M4 write buffer: fix MEC1322 hardware bug. */ + mainNVIC_AUX_ACTLR |= 0x07; + + system_set_ec_clock(); + + /* Assuming downloading code via the debugger - so ensure the hardware + is using the vector table downloaded with the application. */ + mainVTOR = ( uint32_t ) __Vectors; +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + /* The full demo includes tests that run from the tick hook. */ + #if( configCREATE_LOW_POWER_DEMO == 0 ) + { + /* Some of the tests and demo tasks executed by the full demo include + interaction from an interrupt - for which the tick interrupt is used + via the tick hook function. */ + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an +implementation of vApplicationGetIdleTaskMemory() to provide the memory that is +used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) +{ +/* If the buffers to be provided to the Idle task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xIdleTaskTCB; +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the +application must provide an implementation of vApplicationGetTimerTaskMemory() +to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xTimerTaskTCB; +static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c new file mode 100644 index 000000000..bdc8e3d69 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.c @@ -0,0 +1,210 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file initialises three timers as follows: + * + * Basic timer channels 0 and 1 provide the interrupts that are used with the + * IntQ standard demo tasks, which test interrupt nesting and using queues from + * interrupts. The interrupts use slightly different frequencies so will + * occasionally nest. + * + * Basic timer channel 2 provides a much higher frequency timer that tests the + * nesting of interrupts that don't use the FreeRTOS API. + * + * All the timers can nest with the tick interrupt - creating a maximum + * interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the + * tick interrupt does not increment the nesting count variable). + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Library includes. */ +#include "common_lib.h" +#include "peripheral_library/interrupt/interrupt.h" +#include "peripheral_library/basic_timer/btimer.h" + +/* The frequencies at which the first two timers expire are slightly offset to +ensure they don't remain synchronised. The frequency of the highest priority +interrupt is 20 times faster so really hammers the interrupt entry and exit +code. */ +#define tmrTIMER_0_FREQUENCY ( 2000UL ) +#define tmrTIMER_1_FREQUENCY ( 2003UL ) +#define tmrTIMER_2_FREQUENCY ( 20000UL ) + +/* The basic timer channels used for generating the three interrupts. */ +#define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */ +#define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */ +#define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */ + +/* The high frequency interrupt is given a priority above the maximum at which +interrupt safe FreeRTOS calls can be made. The priority of the lower frequency +timers must still be above the tick interrupt priority. */ +#define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 ) +#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 ) +#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) + +/* Hardware register locations. */ +#define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 ) +#define tmrMMCR_EC_INTERRUPT_CONTROL ( * ( volatile uint8_t * ) 0x4000FC18 ) + +#define tmrRECORD_NESTING_DEPTH() \ + ulNestingDepth++; \ + if( ulNestingDepth > ulMaxRecordedNestingDepth ) \ + { \ + ulMaxRecordedNestingDepth = ulNestingDepth; \ + } + +/* Used to count the nesting depth, and record the maximum nesting depth. */ +volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0; + +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForIntQueueTest( void ) +{ +const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY; +const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY; +const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY; + + tmrGIRQ23_ENABLE_SET = 0x03; + tmrMMCR_EC_INTERRUPT_CONTROL = 1; + + /* Initialise the three timers as described at the top of this file, and + enable their interrupts in the NVIC. */ + btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count ); + btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 ); + enable_timer0_irq(); + NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431 + NVIC_ClearPendingIRQ( TIMER0_IRQn ); + NVIC_EnableIRQ( TIMER0_IRQn ); + btimer_start( tmrTIMER_CHANNEL_0 ); + + btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count ); + btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 ); + enable_timer1_irq(); + NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432 + NVIC_ClearPendingIRQ( TIMER1_IRQn ); + NVIC_EnableIRQ( TIMER1_IRQn ); + btimer_start( tmrTIMER_CHANNEL_1 ); + + btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count ); + btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 ); + enable_timer2_irq(); + NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY ); + NVIC_ClearPendingIRQ( TIMER2_IRQn ); + NVIC_EnableIRQ( TIMER2_IRQn ); + btimer_start( tmrTIMER_CHANNEL_2 ); +} +/*-----------------------------------------------------------*/ + +/* The TMR0 interrupt is used for different purposes by the low power and full +demos respectively. */ +#if( configCREATE_LOW_POWER_DEMO == 0 ) + + void NVIC_Handler_TMR0( void ) + { + tmrRECORD_NESTING_DEPTH(); + + /* Call the IntQ test function for this channel. */ + portYIELD_FROM_ISR( xFirstTimerHandler() ); + + ulNestingDepth--; + } + +#endif /* configCREATE_LOW_POWER_DEMO */ +/*-----------------------------------------------------------*/ + +void NVIC_Handler_TMR1( void ) +{ + tmrRECORD_NESTING_DEPTH(); + + /* Just testing the xPortIsInsideInterrupt() functionality. */ + configASSERT( xPortIsInsideInterrupt() == pdTRUE ); + + /* Call the IntQ test function for this channel. */ + portYIELD_FROM_ISR( xSecondTimerHandler() ); + + ulNestingDepth--; +} +/*-----------------------------------------------------------*/ + +void NVIC_Handler_TMR2( void ) +{ + tmrRECORD_NESTING_DEPTH(); + ulNestingDepth--; +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h new file mode 100644 index 000000000..5c133ff23 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +BaseType_t xTimer0Handler( void ); +BaseType_t xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c new file mode 100644 index 000000000..a2deb7adc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_full/main_full.c @@ -0,0 +1,422 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project that demonstrates the tickless low power features of FreeRTOS, and a + * more comprehensive test and demo application. The configCREATE_LOW_POWER_DEMO + * setting in FreeRTOSConifg.h is used to select between the two. See the notes + * on using conifgCREATE_LOW_POWER_DEMO in main.c. This file implements the + * comprehensive test and demo version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "death.h" +#include "TimerDemo.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period of the check task, in ms, provided no errors have been reported by +any of the standard demo tasks. ms are converted to the equivalent in ticks +using the pdMS_TO_TICKS() macro constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL ) + +/* The period of the check task, in ms, if an error has been reported in one of +the standard demo tasks. ms are converted to the equivalent in ticks using the +pdMS_TO_TICKS() macro. */ +#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 200UL ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main() to run the full demo (as opposed to the blinky demo) when + * configCREATE_LOW_POWER_DEMO is set to 0. + */ +void main_full( void ); + +/* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Some of the tests and demo tasks executed by the full demo include + * interaction from an interrupt - for which the tick interrupt is used via the + * tick hook function. + */ +void vFullDemoTickHook( void ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* The variable that is incremented to represent each LED toggle. On the +clicker hardware the LED state is set to the value of the least significant bit +of this variable. On other hardware, where an LED is not used, the LED just +keeps a count of the number of times the LED would otherwise have been toggled. +See the comments at the top of this file for information on the expected LED +toggle rate. */ +extern volatile uint32_t ulLED; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptQueueTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 2UL; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 4UL; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 5UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS ) + { + ulErrorFound = 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 10UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + + configASSERT( ulErrorFound == pdFALSE ); + + /* Just testing the xPortIsInsideInterrupt() functionality. */ + configASSERT( xPortIsInsideInterrupt() == pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check task will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check task will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* Some of the tests and demo tasks executed by the full demo include + interaction from an interrupt - for which the tick interrupt is used via + the tick hook function. */ + + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); +} diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c new file mode 100644 index 000000000..dbc969d72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/low_power_tick_config.c @@ -0,0 +1,418 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "common_lib.h" + +/* This file contains functions that will override the default implementations +in the RTOS port layer. Therefore only build this file if the low power demo +is being built. */ +#if( configCREATE_LOW_POWER_DEMO == 1 ) + +/* ID of the hibernation timer used to generate the tick. */ +#define mainTICK_HTIMER_ID 0 + +/* Written to the hibernation timer control register to configure the timer for +its higher resolution. */ +#define mainHTIMER_HIGH_RESOLUTION 0 + +/* The frequency of the hibernation timer when it is running at its higher +resolution and low resolution respectively. */ +#define mainHIGHER_RESOLUTION_TIMER_HZ ( 32787UL ) /* (1000000us / 30.5us) as each LSB is 30.5us. */ +#define mainLOW_RESOLUTION_TIMER_HZ ( 8UL ) /* ( 1000ms / 125ms ) as each LSB is 0.125s. */ + +/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate +interrupts at a low frequency. The purpose being to bring the CPU out of its +sleep mode by an interrupt other than the tick interrupt, and therefore +allowing an additional paths through the code to be tested. */ +#define lpINCLUDE_TEST_TIMER 0 + +/* Some registers are accessed directly as the library is not compatible with +all the compilers used. */ +#define lpHTIMER_PRELOAD_REGISTER ( * ( volatile uint16_t * ) 0x40009800 ) +#define lpHTIMER_CONTROL_REGISTER ( * ( volatile uint16_t * ) 0x40009804 ) +#define lpHTIMER_COUNT_REGISTER ( * ( volatile uint16_t * ) 0x40009808 ) +#define lpEC_GIRQ17_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C0B8 ) +#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL ) + +/* + * The low power demo does not use the SysTick, so override the + * vPortSetupTickInterrupt() function with an implementation that configures + * the low power clock. NOTE: This function name must not be changed as it + * is called from the RTOS portable layer. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * To fully test the low power tick processing it is necessary to sometimes + * bring the MCU out of its sleep state by a method other than the tick + * interrupt. Interrupts generated from a basic timer are used for this + * purpose. + */ +#if( lpINCLUDE_TEST_TIMER == 1 ) + static void prvSetupBasicTimer( void ); +#endif + +/*-----------------------------------------------------------*/ + +/* The reload value to use in the timer to generate the tick interrupt - +assumes the timer is running at its higher resolution. */ +static const uint32_t ulHighResolutionReloadValue = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ ); + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulReloadValueForOneHighResolutionTick = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ ); +//static const uint32_t usReloadValueForOneLowResolutionTick = ( mainLOW_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ ); + +/* Calculate the maximum number of ticks that can be suppressed when using the +high resolution clock and low resolution clock respectively. */ +static uint32_t ulMaximumPossibleSuppressedHighResolutionTicks = 0; +//static const uint16_t usMaximumPossibleSuppressedLowResolutionTicks = USHRT_MAX / usReloadValueForOneLowResolutionTick; + +/* As the clock is only 2KHz, it is likely a value of 1 will be too much, so +use zero - but leave the value here to assist porting to different clock +speeds. */ +static const uint32_t ulStoppedTimerCompensation = 0UL; + +/* Flag set from the tick interrupt to allow the sleep processing to know if +sleep mode was exited because of an timer interrupt or a different interrupt. */ +static volatile uint32_t ulTickFlag = pdFALSE; + +/*-----------------------------------------------------------*/ + +void NVIC_Handler_HIB_TMR( void ) +{ + lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue; + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; +} +/*-----------------------------------------------------------*/ + +#if( lpINCLUDE_TEST_TIMER == 1 ) + + #define GIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 ) + + static void prvSetupBasicTimer( void ) + { + const uint8_t ucTimerChannel = 0; + const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10; + + GIRQ23_ENABLE_SET = 0x03; + *(unsigned int*)0x4000FC18 = 1; + + /* To fully test the low power tick processing it is necessary to sometimes + bring the MCU out of its sleep state by a method other than the tick + interrupt. Interrupts generated from a basic timer are used for this + purpose. */ + btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count ); + btimer_interrupt_status_get_clr( ucTimerChannel ); + enable_timer0_irq(); + NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel ); + NVIC_ClearPendingIRQ( TIMER0_IRQn ); + NVIC_EnableIRQ( TIMER0_IRQn ); + btimer_start( ucTimerChannel ); + } + +#endif /* lpINCLUDE_TEST_TIMER */ +/*-----------------------------------------------------------*/ + +void vPortSetupTimerInterrupt( void ) +{ + ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick; + + /* Set up the hibernation timer to start at the value required by the + tick interrupt. Equivalent to the following libarary call. The library + is not used as it is not compatible with all the compilers used: + htimer_enable( mainTICK_HTIMER_ID, ulHighResolutionReloadValue, mainHTIMER_HIGH_RESOLUTION ); */ + lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue; + lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION; + + /* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */ + lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT; + + /* The hibernation timer is not an auto-reload timer, so gets reset + from within the ISR itself. For that reason it's interrupt is set + to the highest possible priority to ensure clock slippage is minimised. */ + NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_ClearPendingIRQ( HTIMER_IRQn ); + NVIC_EnableIRQ( HTIMER_IRQn ); + + /* A basic timer is also started, purely for test purposes. Its only + purpose is to bring the CPU out of its sleep mode by an interrupt other + than the tick interrupt in order to get more code test coverage. */ + #if( lpINCLUDE_TEST_TIMER == 1 ) + { + prvSetupBasicTimer(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* Override the default definition of vPortSuppressTicksAndSleep() that is +weakly defined in the FreeRTOS Cortex-M port layer with a version that manages +the hibernation timer, as the tick is generated from the low power hibernation +timer and not the SysTick as would normally be the case on a Cortex-M. */ +void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) +{ +uint32_t ulCompleteTickPeriods, ulReloadValue, ulCompletedTimerDecrements, ulCountAfterSleep, ulCountBeforeSleep; +eSleepModeStatus eSleepAction; +TickType_t xModifiableIdleTime; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the hibernation timer reload value does not overflow the + counter. */ + if( xExpectedIdleTime > ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks ) + { + xExpectedIdleTime = ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks; + } + + /* Stop the timer momentarily. The time the timer is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the kernel + with respect to calendar time. Take the count value first as clearing + the preload value also seems to clear the count. */ + ulCountBeforeSleep = ( uint32_t ) lpHTIMER_COUNT_REGISTER; + lpHTIMER_PRELOAD_REGISTER = 0; + + /* Calculate the reload value required to wait xExpectedIdleTime tick + periods. -1 is used as the current time slice will already be part way + through, the part value coming from the current timer count value. */ + ulReloadValue = ulCountBeforeSleep + ( ulReloadValueForOneHighResolutionTick * ( xExpectedIdleTime - 1UL ) ); + + if( ulReloadValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the timer is going to be stopped + momentarily. */ + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() method as + that will mask interrupts that should exit sleep mode. */ + __asm volatile( "cpsid i" ); + __asm volatile( "dsb" ); + __asm volatile( "isb" ); + + /* The tick flag is set to false before sleeping. If it is true when sleep + mode is exited then sleep mode was probably exited because the tick was + suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + the context switch might have been pended by an external interrupt that + requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) + { + /* Resetart the timer from whatever remains in the counter register, + but 0 is not a valid value. */ + ulReloadValue = ulCountBeforeSleep - ulStoppedTimerCompensation; + + if( ulReloadValue == 0 ) + { + ulReloadValue = ulReloadValueForOneHighResolutionTick; + ulCompleteTickPeriods = 1UL; + } + else + { + ulCompleteTickPeriods = 0UL; + } + + lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue; + + /* Re-enable interrupts - see comments above the cpsid instruction() + above. */ + __asm volatile( "cpsie i" ); + __asm volatile( "dsb" ); + __asm volatile( "isb" ); + } + else + { + /* Write the calculated reload value, which will also start the + timer. */ + lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue; + + /* Allow the application to define some pre-sleep processing. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + means the application defined code has already executed the sleep + instructions. */ + if( xModifiableIdleTime > 0 ) + { + __asm volatile( "dsb" ); + __asm volatile( "wfi" ); + __asm volatile( "isb" ); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xModifiableIdleTime ); + + /* Stop the hibernation timer. Again, the time the tiemr is stopped + for is accounted for as best it can be, but using the tickless mode + will inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. Take the count value first as + setting the preload to zero also seems to clear the count. */ + ulCountAfterSleep = lpHTIMER_COUNT_REGISTER; + lpHTIMER_PRELOAD_REGISTER = 0; + + /* Re-enable interrupts - see comments above the cpsid instruction() + above. */ + __asm volatile( "cpsie i" ); + __asm volatile( "dsb" ); + __asm volatile( "isb" ); + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because this + function is called with the scheduler suspended the actual tick + processing will not occur until after this function has exited. + The timer has already been reloaded to count in ticks, and can just + continue counting down from its current value. */ + ulReloadValue = ulCountAfterSleep; + + /* Sanity check that the timer's reload value has indeed been + reset. */ + configASSERT( ( uint32_t ) lpHTIMER_PRELOAD_REGISTER == ulReloadValueForOneHighResolutionTick ); + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be processed as + soon as this function exits, the tick value maintained by the tick + is stepped forward by one less than the time spent sleeping. The + actual stepping of the tick appears later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. How + many complete tick periods passed while the processor was + sleeping? */ + ulCompletedTimerDecrements = ulReloadValue - ulCountAfterSleep; + + /* Undo the adjustment that was made to the reload value to account + for the fact that a time slice was part way through when this + function was called before working out how many complete tick + periods this represents. (could have used [ulExpectedIdleTime * + ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on + the previous line, but this way avoids the multiplication). */ + ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep ); + ulCompleteTickPeriods = ulCompletedTimerDecrements / ulReloadValueForOneHighResolutionTick; + + /* The reload value is set to whatever fraction of a single tick + period remains. */ + ulReloadValue = ( ( ulCompleteTickPeriods + 1UL ) * ulReloadValueForOneHighResolutionTick ) - ulCompletedTimerDecrements; + } + + /* Cannot use a reload value of 0 - it will not start the timer. */ + if( ulReloadValue == 0 ) + { + /* There is no fraction remaining. */ + ulReloadValue = ulReloadValueForOneHighResolutionTick; + ulCompleteTickPeriods++; + } + + /* Restart the timer so it runs down from the reload value. The reload + value will get set to the value required to generate exactly one tick + period the next time the tick interrupt executes. */ + lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue; + } + + /* Wind the tick forward by the number of tick periods that the CPU + remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); +} +/*-----------------------------------------------------------*/ + +void NVIC_Handler_TMR0( void ) +{ + /* This timer is used for test purposes. Its only function is to + generate interrupts while the MCU is sleeping, so the MCU is sometimes + brought out of sleep by a means other than the tick interrupt. */ +} +/*-----------------------------------------------------------*/ + + +#endif /* configCREATE_LOW_POWER_DEMO */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c new file mode 100644 index 000000000..26659dedf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/main_low_power/main_low_power.c @@ -0,0 +1,237 @@ +/* + FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky demo + * that demonstrates tickless low power operation, and a more comprehensive + * test and demo application. The configCREATE_LOW_POWER_DEMO setting in + * FreeRTOSConfig.h is used to select between the two. See the notes on using + * configCREATE_LOW_POWER_DEMO in main.c. This file implements the low power + * version. + * + * NOTE 2: This file only contains the source code that is specific to the + * low power demo. Generic functions, such FreeRTOS hook functions, and + * functions required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_low_power() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It sends the value 100 to the queue every second. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() blocks on the queue, blipping (quickly + * turn on then off again) the LED each time it received the value 100 from the + * queue send task. The queue send task writes to the queue every second, so + * the LED will blip once a second. + * + * The RTOS tick is turned off when the queue send task and queue receive task + * are both in the Blocked state. + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when configCREATE_LOW_POWER_DEMO is set to 1 in + * main.c. + */ +void main_low_power( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/* The variable that is incremented to represent each LED toggle. On the +clicker hardware the LED state is set to the value of the least significant bit +of this variable. On other hardware, where an LED is not used, the LED just +keeps a count of the number of times the LED would otherwise have been toggled. +See the comments at the top of this file for information on the expected LED +toggle rate. */ +extern volatile uint32_t ulLED; + +/*-----------------------------------------------------------*/ + +void main_low_power( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the Idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details on the FreeRTOS heap + http://www.freertos.org/a00111.html. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const uint32_t ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +uint32_t ulReceivedValue; +const uint32_t ulExpectedValue = 100UL; +const TickType_t xShortDelay = pdMS_TO_TICKS( 10 ); + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + /* Blip the LED briefly to show the demo is running, but without + leaving the LED on too long as energy is being conserved. */ + configTOGGLE_LED(); + vTaskDelay( xShortDelay ); + configTOGGLE_LED(); + + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h new file mode 100644 index 000000000..035a10875 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/ARM_REG.h @@ -0,0 +1,194 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * ARM_REG.h + * This is the header to define Cortex-M3 system control & status registers + ********************************************************************************** + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2015/12/23 15:37:58 $ + * AUTHOR: $Author: akrishnan $ + * + * Revision history (latest first): + * #xx + *********************************************************************************** + */ + +/******************************************************************************/ +/** @defgroup ARM_REG ARM_REG + * @{ + */ + +/** @file ARM_REG.h +* \brief ARM Cortex-M3 registers header file +* \author KBCEC Team +* +* This file contains ARM Cortex-M3 system control & status registers. +******************************************************************************/ +#ifndef ARM_REG_H_ +#define ARM_REG_H_ + +#define REG8(x) (*((volatile unsigned char *)(x))) +#define REG16(x) (*((volatile unsigned short *)(x))) +#define REG32(x) (*((volatile unsigned long *)(x))) + +/* NVIC Registers */ +#define NVIC_INT_TYPE REG32(0xE000E004) +#define NVIC_AUX_ACTLR REG32(0xE000E008) + #define WR_BUF_DISABLE (1 << 1) +#define NVIC_ST_CTRL REG32(0xE000E010) + #define ST_ENABLE (1 << 0) + #define ST_TICKINT (1 << 1) + #define ST_CLKSOURCE (1 << 2) + #define ST_COUNTFLAG (1 << 3) +#define NVIC_ST_RELOAD REG32(0xE000E014) +#define NVIC_ST_CURRENT REG32(0xE000E018) +#define NVIC_ST_CALIB REG32(0xE000E01C) +#define NVIC_ENABLE0 REG32(0xE000E100) +#define NVIC_ENABLE1 REG32(0xE000E104) +#define NVIC_ENABLE2 REG32(0xE000E108) +#define NVIC_ENABLE3 REG32(0xE000E10C) +#define NVIC_ENABLE4 REG32(0xE000E110) +#define NVIC_ENABLE5 REG32(0xE000E114) +#define NVIC_ENABLE6 REG32(0xE000E118) +#define NVIC_ENABLE7 REG32(0xE000E11C) +#define NVIC_DISABLE0 REG32(0xE000E180) +#define NVIC_DISABLE1 REG32(0xE000E184) +#define NVIC_DISABLE2 REG32(0xE000E188) +#define NVIC_DISABLE3 REG32(0xE000E18C) +#define NVIC_DISABLE4 REG32(0xE000E190) +#define NVIC_DISABLE5 REG32(0xE000E194) +#define NVIC_DISABLE6 REG32(0xE000E198) +#define NVIC_DISABLE7 REG32(0xE000E19C) +#define NVIC_PEND0 REG32(0xE000E200) +#define NVIC_PEND1 REG32(0xE000E204) +#define NVIC_PEND2 REG32(0xE000E208) +#define NVIC_PEND3 REG32(0xE000E20C) +#define NVIC_PEND4 REG32(0xE000E210) +#define NVIC_PEND5 REG32(0xE000E214) +#define NVIC_PEND6 REG32(0xE000E218) +#define NVIC_PEND7 REG32(0xE000E21C) +#define NVIC_UNPEND0 REG32(0xE000E280) +#define NVIC_UNPEND1 REG32(0xE000E284) +#define NVIC_UNPEND2 REG32(0xE000E288) +#define NVIC_UNPEND3 REG32(0xE000E28C) +#define NVIC_UNPEND4 REG32(0xE000E290) +#define NVIC_UNPEND5 REG32(0xE000E294) +#define NVIC_UNPEND6 REG32(0xE000E298) +#define NVIC_UNPEND7 REG32(0xE000E29C) +#define NVIC_ACTIVE0 REG32(0xE000E300) +#define NVIC_ACTIVE1 REG32(0xE000E304) +#define NVIC_ACTIVE2 REG32(0xE000E308) +#define NVIC_ACTIVE3 REG32(0xE000E30C) +#define NVIC_ACTIVE4 REG32(0xE000E310) +#define NVIC_ACTIVE5 REG32(0xE000E314) +#define NVIC_ACTIVE6 REG32(0xE000E318) +#define NVIC_ACTIVE7 REG32(0xE000E31C) +#define NVIC_PRI0 REG32(0xE000E400) +#define NVIC_PRI1 REG32(0xE000E404) +#define NVIC_PRI2 REG32(0xE000E408) +#define NVIC_PRI3 REG32(0xE000E40C) +#define NVIC_PRI4 REG32(0xE000E410) +#define NVIC_PRI5 REG32(0xE000E414) +#define NVIC_PRI6 REG32(0xE000E418) +#define NVIC_PRI7 REG32(0xE000E41C) +#define NVIC_PRI8 REG32(0xE000E420) +#define NVIC_PRI9 REG32(0xE000E424) +#define NVIC_PRI10 REG32(0xE000E428) +#define NVIC_PRI11 REG32(0xE000E42C) +#define NVIC_PRI12 REG32(0xE000E430) +#define NVIC_PRI13 REG32(0xE000E434) +#define NVIC_PRI14 REG32(0xE000E438) +#define NVIC_PRI15 REG32(0xE000E43C) +#define NVIC_PRI16 REG32(0xE000E440) +#define NVIC_PRI17 REG32(0xE000E444) +#define NVIC_PRI18 REG32(0xE000E448) +#define NVIC_PRI19 REG32(0xE000E44C) +#define NVIC_PRI20 REG32(0xE000E450) +#define NVIC_PRI21 REG32(0xE000E454) +#define NVIC_PRI22 REG32(0xE000E458) +#define NVIC_PRI23 REG32(0xE000E45C) +#define NVIC_PRI24 REG32(0xE000E460) +#define NVIC_PRI25 REG32(0xE000E464) +#define NVIC_PRI26 REG32(0xE000E468) +#define NVIC_PRI27 REG32(0xE000E46C) +#define NVIC_PRI28 REG32(0xE000E470) +#define NVIC_PRI29 REG32(0xE000E474) +#define NVIC_PRI30 REG32(0xE000E478) +#define NVIC_PRI31 REG32(0xE000E47C) +#define NVIC_PRI32 REG32(0xE000E480) +#define NVIC_PRI33 REG32(0xE000E484) +#define NVIC_PRI34 REG32(0xE000E488) +#define NVIC_PRI35 REG32(0xE000E48C) +#define NVIC_PRI36 REG32(0xE000E490) +#define NVIC_PRI37 REG32(0xE000E494) +#define NVIC_PRI38 REG32(0xE000E498) +#define NVIC_PRI39 REG32(0xE000E49C) +#define NVIC_PRI40 REG32(0xE000E4A0) +#define NVIC_PRI41 REG32(0xE000E4A4) +#define NVIC_PRI42 REG32(0xE000E4A8) +#define NVIC_PRI43 REG32(0xE000E4AC) +#define NVIC_PRI44 REG32(0xE000E4B0) +#define NVIC_PRI45 REG32(0xE000E4B4) +#define NVIC_PRI46 REG32(0xE000E4B8) +#define NVIC_PRI47 REG32(0xE000E4BC) +#define NVIC_PRI48 REG32(0xE000E4C0) +#define NVIC_PRI49 REG32(0xE000E4C4) +#define NVIC_PRI50 REG32(0xE000E4C8) +#define NVIC_PRI51 REG32(0xE000E4CC) +#define NVIC_PRI52 REG32(0xE000E4D0) +#define NVIC_PRI53 REG32(0xE000E4D4) +#define NVIC_PRI54 REG32(0xE000E4D8) +#define NVIC_PRI55 REG32(0xE000E4DC) +#define NVIC_PRI56 REG32(0xE000E4E0) +#define NVIC_PRI57 REG32(0xE000E4E4) +#define NVIC_PRI58 REG32(0xE000E4E8) +#define NVIC_PRI59 REG32(0xE000E4EC) +#define NVIC_CPUID REG32(0xE000ED00) +#define NVIC_INT_CTRL REG32(0xE000ED04) +#define NVIC_VECT_TABLE REG32(0xE000ED08) +#define NVIC_AP_INT_RST REG32(0xE000ED0C) +#define NVIC_SYS_CTRL REG32(0xE000ED10) +#define NVIC_CFG_CTRL REG32(0xE000ED14) +#define NVIC_SYS_H_PRI1 REG32(0xE000ED18) +#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C) +#define NVIC_SYS_H_PRI3 REG32(0xE000ED20) +#define NVIC_SYS_H_CTRL REG32(0xE000ED24) +#define NVIC_FAULT_STA REG32(0xE000ED28) +#define NVIC_HARD_F_STA REG32(0xE000ED2C) +#define NVIC_DBG_F_STA REG32(0xE000ED30) +#define NVIC_MM_F_ADR REG32(0xE000ED34) +#define NVIC_BUS_F_ADR REG32(0xE000ED38) +#define NVIC_SW_TRIG REG32(0xE000EF00) + +/* MPU Registers */ +#define MPU_TYPE REG32(0xE000ED90) +#define MPU_CTRL REG32(0xE000ED94) +#define MPU_RG_NUM REG32(0xE000ED98) +#define MPU_RG_ADDR REG32(0xE000ED9C) +#define MPU_RG_AT_SZ REG32(0xE000EDA0) + + +#endif /* #ifndef ARM_REG_H_ */ + +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/CEC1302_crypto_api.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/CEC1302_crypto_api.h new file mode 100644 index 000000000..d62569240 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/CEC1302_crypto_api.h @@ -0,0 +1,691 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*****************************************************************************/ + + + +#ifndef INCLUDE_CEC1302_CRYPTO_API_H_ +#define INCLUDE_CEC1302_CRYPTO_API_H_ + +#include +#include +#ifdef __cplusplus +extern "C" { +#endif + +/* Misc. */ + +/* RNG */ +/** + * \rng_power + * + * \param [in] pwr_on Power On? + * \return none + * + * \details Gate clocks on/off to NDRNG block + */ +extern void +rng_power(bool pwr_on); + + +/** + * \rng_reset + * + * \return Reset NDRNG block + * + * \details + */ +extern void +rng_reset(void); + + +/** + * \rng_mode + * + * \param [in] mode tmode_pseudo 0(asynchronous/true random mode), + * Non-zero(pseudo-random mode) + * \return None + * + * \details Set NDRNG random number generation mode + */ +extern void +rng_mode(uint8_t mode); + + +/** + * \rng_is_on + * + * \return is NDRNG Block powered on? True if yes, false otherwise + * + * \details Check if NDRNG block is powered on. + */ +extern bool +rng_is_on(void); + + +/** + * \rng_start + * + * \return None + * + * \details Start NDRNG engine + */ +extern void +rng_start(void); + +/** + * \rng_stop + * + * \return Void + * + * \details Stop NDRNG engine + */ +extern void +rng_stop(void); + + +/** + * \rng_get_fifo_level + * + * \return actual number of 32-bit words in the NDRNG FIFO. + * + * \details return the number of 32-bit words of random data + * currently in the FIFO. + */ +extern uint32_t +rng_get_fifo_level(void); + + +/** + * \rng_get_bytes + * + * \param [in] pbuff Output Buffer + * \param [in] nbytes Number of bytes to be read + * \return Number of bytes retrieved + * + * \details read bytes from the NDRNG FIFO + */ +extern uint32_t +rng_get_bytes(uint8_t* pbuff, uint32_t nbytes); + + +/** + * \rng_get_words + * + * \param [in] pwords Pointer to output buffer + * \param [in] nwords Number of words to read + * \return actual number of words read + * + * \details Details + */ +extern uint32_t +rng_get_words(uint32_t* pwords, uint32_t nwords); + + +/* AES */ +/** + * \aes_hash_power + * + * \param [in] pwr_on Gate/Ungate clocks to block + * \return None + * + * \details Enable/Disable AES and HASH H/W Block + */ +extern void +aes_hash_power(uint8_t pwr_on); + +/** + * \aes_hash_reset + * + * \return None + * + * \details Stop AES and HASH + */ +extern void +aes_hash_reset(void); + +/** + * \aes_busy + * + * \return Is AES Block Running? True if yes, false Otherwise. + * + * \details Is AES Block Running? + */ +extern bool +aes_busy(void); + + +/** + * \aes_status + * + * \return Status of AES Block + * + * \details Returns the Status of AES Block + */ +extern uint32_t +aes_status(void); + +/** + * \aes_done_status + * + * \param [in] hw_status Pointer to where the status value will be updated + * \return True if done, false otherwise + * + * \details Returns the done status of AES block + */ +extern bool +aes_done_status(uint32_t* hw_status); + +/** + * \aes_stop + * + * \return Return aes_busy() Status + * + * \details Stop AES Operations + */ +extern bool +aes_stop(void); + +/** + * \aes_start + * + * \param [in] ien Enable interrupts? + * \return None + * + * \details Start AES block with or without interrupts + */ +extern void +aes_start(bool ien); + +/** + * \aes_iclr + * + * \return Status of the AES Block + * + * \details Clears AES Hash Interrupts + */ +extern uint32_t +aes_iclr(void); + + +/** + * \brief Brief + * + * \param [in] pkey Aligned buffer with AES Key + * \param [in] piv Aligned buffer with AES initialization + * \param [in] key_len AES_KEYLEN_128, AES_KEYLEN_192, AES_KEYLEN_256 + * \param [in] msbf Most Significant Byte order first? + * \return AES_ERR_BAD_POINTER, AES_ERR_BAD_KEY_LEN, AES_OK + * + * \details Load AES Accelerator with key and optional Initialization vector + */ +extern uint8_t +aes_set_key(const uint32_t* pkey, + const uint32_t* piv, + uint8_t key_len, bool msbf); + +/** + * \aes_crypt + * + * \param [in] data_in Aligned input data Buffer + * \param [in] data_out Aligned output data buffer + * \param [in] num_128bit_blocks Size of input in 16-byte blocks + * \param [in] mode AES Encryption/Decryption Mode + * \return AES_OK, AES_ERR_BAD_POINTER, + * + * \details Program specified AES Operation using currently programmed key + */ +extern uint8_t +aes_crypt(const uint32_t* data_in, + uint32_t* data_out, + uint32_t num_128bit_blocks, uint8_t mode); + + +/* SHA */ +#define SHA1_BLEN (20u) +#define SHA1_WLEN (5u) +#define SHA2_BLEN (32u) +#define SHA2_WLEN (8u) +#define SHA12_BLOCK_BLEN (64u) +#define SHA12_BLOCK_WLEN (16u) +#define SHA3_BLEN (48u) +#define SHA3_WLEN (12u) +#define SHA5_BLEN (64u) +#define SHA5_WLEN (16u) + +/* return values */ +#define SHA_RET_OK (0) /* OK */ +#define SHA_RET_START (1) /* OK, SHA Engine started */ +#define SHA_RET_ERROR (0x80) /* b[7]==1 indicates an error */ +#define SHA_RET_ERR_BUSY (0x80) +#define SHA_RET_ERR_BAD_ADDR (0x81) +#define SHA_RET_ERR_TIMEOUT (0x82) +#define SHA_RET_ERR_MAX_LEN (0x83) +#define SHA_RET_ERR_UNSUPPORTED (0x84) + +#define SHA_MODE_MD5 (0) // Not supported by HW +#define SHA_MODE_1 (1) +#define SHA_MODE_224 (2) // Not supported by HW +#define SHA_MODE_256 (3) +#define SHA_MODE_384 (4) // Not supported by HW +#define SHA_MODE_512 (5) // Not supported by HW + +#define HASH_START_IEN (1u) +#define HASH_START_NOIEN (0u) + +typedef union { + uint32_t w[SHA2_WLEN]; + uint8_t b[SHA2_BLEN]; +} SHA12_DIGEST_U; + + +/* + * !!! SHA-1 & SHA-256 + * HW Engine requires alignment >= 4-byte boundary !!! + */ +typedef struct sha12_context_s SHA12_CONTEXT_T; +struct sha12_context_s { + SHA12_DIGEST_U hash; + union { + uint32_t w[(SHA12_BLOCK_WLEN) * 2]; + uint8_t b[(SHA12_BLOCK_BLEN) * 2]; + } block; + uint8_t mode; + uint8_t block_len; + uint8_t rsvd[2]; + uint32_t total_msg_len; +}; + + +/** + * \hash_busy + * + * \return is busy? True if yes, Flase other wise + * + * \details returns the busy status of Hash Block + */ +extern bool hash_busy(void); + +/** + * \hash_start + * + * \param [in] ien enable/disable interrupts + * \return None + * + * \details start hash block + */ +extern void +hash_start(bool ien); + +/** + * \hash_done_status + * + * \param [in] hw_status Hash Status Register Value + * \return true if done, false otherwise + * + * \details reflects the done status of HASH black and updates + * status regsiter value into the input variable + */ +extern bool +hash_done_status(uint32_t* hw_status); + +/** + * \sha12_init + * + * \param [in] psha12_ctx Data Structure for Input data and Output Digest + * \param [in] mode SHA_MODE_1 or SHA_MODE_256 + * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_UNSPPORTED ,SHA_RET_OK + * + * \details Initializes the Data structure provided + */ +extern uint8_t +sha12_init(SHA12_CONTEXT_T* psha12_ctx, uint8_t mode); + +/** + * \sha12_update + * + * \param [in] psha12_ctx Data Structure for Input data and Output Digest + * \param [in] pdata Input Data to Hash Block + * \param [in] num_bytes Byte length of input data + * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY, SHA_RET_ERR_MAX_LEN, SHA_RET_OK + * + * \details Run hash block on data and if data greater than block size, put remaining bytes back into the data structure + */ +extern uint8_t +sha12_update(SHA12_CONTEXT_T* psha12_ctx, + const uint32_t* pdata, uint32_t num_bytes); + +/** + * \sha12_finalize + * + * \param [in] psha12_ctx Data Structure for Input data and Output Digest + * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START + * + * \details Apply FIPS padding to SHA256 and perform final hash calculation. + */ +extern uint8_t +sha12_finalize(SHA12_CONTEXT_T* psha12_ctx); + +/** + * \sha256_pad_fill + * + * \param [in] pblock64 Aligned Memory buffer of atleast 64 bytes + * \param [in] msg_byte_len Length of Message in bytes + * \return None + * + * \details Zero and fill a 64-byte SHA256 pad block with FIP padding values + */ +extern void +sha256_pad_fill(uint32_t* pblock64, uint32_t msg_byte_len); + + +/** + * \sha256_raw + * + * \param [in] pdata Input Message + * \param [in] pdigest Pointer to biffer where digest will be written + * \param [in] num64byte_blocks size of input data in blocks + * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START + * + * \details Calculate SHA256 on data + */ +extern uint8_t +sha256_raw(uint32_t* pdata, uint32_t* pdigest, uint32_t num64byte_blocks); + +/** + * \sha256_raw_init + * + * \param [in] psha256_digest Pointer to buffer where digest will be written + * \return None + * + * \details Initialize the SHA256 Digest data block + */ +extern void +sha256_raw_init(uint32_t* psha256_digest); + +/** + * \sha256_raw_update + * + * \param [in] pdata Message on which HASH block is to be called + * \param [in] pdigest Pointer to where the digest will be stored + * \param [in] num64byte_blocks size of input data in blocks + * \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START + * + * \details run Hash block on data + */ +extern uint8_t +sha256_raw_update(uint32_t* pdata, + uint32_t* pdigest, uint32_t num64byte_blocks); + +/** + * \hash_iclr + * + * \return Hash Block status + * + * \details Clear Hash Interrupt + */ +extern uint32_t +hash_iclr(void); + + +/** + * \sha_init + * + * \param [in] mode SHA_MODE_1, SHA_MODE_256, SHA_MODE_512 + * \param [in] pdigest Address where digest will be stored + * \return * 0 = Success + * 1 = Hash Engine busy + * 2 = Unsupported SHA operation + * 3 = Bad digest pointer, NULL or mis-aligned. + * \details Initialize Hash engine for SHA operation. + * Programs supported SHA operation's initial value, digest address, + * and operation + */ +extern uint8_t +sha_init(uint8_t mode, uint32_t* pdigest); + + +/** + * \sha_update + * + * \param [in] pdata Input Data + * \param [in] nblocks Size in blocks + * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start? + * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned + * + * \details Run Hash block on data + */ +extern uint8_t +sha_update(uint32_t* pdata, uint16_t nblocks, uint8_t flags); + + +/** + * \sha_final + * + * \param [in] padbuf Buffer for padding (Twice block size) + * \param [in] total_msg_len Message length in bytes + * \param [in] prem Parameter_Description + * \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start? + * \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned + * + * \details Run final SHA Calculations and add padding + */ +extern uint8_t +sha_final(uint32_t* padbuf, uint32_t total_msg_len, + const uint8_t* prem, uint8_t flags); + + +/* PKE Miscellaneous */ + +#define PKE_RET_STARTED (0) +#define PKE_RET_OK (0) +#define PKE_RET_ERR_BUSY (1) +#define PKE_RET_ERR_BAD_PARAM (2) +#define PKE_RET_ERR_BAD_ADDR (3) +#define PKE_RET_ERR_UNKNOWN_OP (4) +#define PKE_RET_ERR_INVALID_BIT_LENGTH (5) +#define PKE_RET_ERR_INVALID_MSG_LENGTH (6) + + +/** + * \pke_power + * + * \param [in] pwr_on power on? + * \return None + * + * \details Gate or Ungate power to PKE block + */ +extern void +pke_power(bool pwr_on); + + +/** + * \brief pke_reset + * + * \return None + * + * \details Reset PKE Block + */ +extern void +pke_reset(void); + +/** + * \pke_status + * + * \return Return PKE Status register value + * + * \details Details + */ +extern uint32_t +pke_status(void); + +/** + * \pke_done_status + * + * \param [in] hw_status POinter where PKE Status is updated + * \return True if done, false otherwise + * + * \details Returns the done status of PKE block + */ +extern bool +pke_done_status(uint32_t* hw_status); + +/** + * \pke_start + * + * \param [in] ien Interrupt Enable? + * \return None + * + * \details Start PKE Block + */ +extern void +pke_start(bool ien); + + +/** + * \pke_busy + * + * \return Busy? True if busy, false otherwise + * + * \details Details + */ +extern bool +pke_busy(void); + + +/** + * \pke_clear_scm + * + * \return None + * + * \details Clear the Shared Crypto memory + */ +extern void +pke_clear_scm(void); + +/** + * \pke_scm_clear_slot + * + * \param [in] slot_num Slot number in Shared Crypto Memory + * \return None + * + * \details Clear the specified slot in Shared Crypto Memory + */ +extern void +pke_scm_clear_slot(uint8_t slot_num); + +/** + * \pke_read_scm + * + * \param [in] dest Pointer to where the data is to be read + * \param [in] nbytes Number of bytes to be read + * \param [in] slot_num Slot number from which data is to be read + * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise + * \return Number of bytes Read + * + * \details Read data from specified slot number in Shared Crypto memory + */ +extern uint16_t +pke_read_scm(uint8_t* dest, uint16_t nbytes, + uint8_t slot_num, bool reverse_byte_order); + + +/** + * \pke_write_scm + * + * \param [in] pdata Data to be written + * \param [in] num_bytes Number of bytes to be written + * \param [in] slot_num Slot number to which data ought to be written + * \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise + * \return None + * + * \details Write data provided to specified slot in Shared Crypto Memory + */ +extern void +pke_write_scm(const void* pdata, uint16_t num_bytes, + uint8_t slot_num, uint8_t reverse_byte_order); + +/* PKE RSA */ + +/** + * \ rsa_load_key + * + * \param [in] rsa_bit_len 1024, 2048 + * \param [in] private_exponent Pointer to private exponent + * \param [in] public_modulus Pointer to Public modulus + * \param [in] public_exponent Pointer to Public Exponent + * \param [in] public_exponent_byte_len Length in bytes of Public Exponent + * \param [in] msbf Reverse Byte order? True if yes, false otherwise + * \return PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK + * + * \details Load RSA keys into Crypto memory + */ +extern uint8_t +rsa_load_key(uint16_t rsa_bit_len, + const uint8_t* private_exponent, + const uint8_t* public_modulus, + const uint8_t* public_exponent, + uint16_t public_exponent_byte_len, + bool msbf); + + +/** + * \ rsa_encrypt + * + * \param [in] rsa_bit_len 1024, 2048 + * \param [in] mesg Message to be encrypted + * \param [in] mlen length of message + * \param [in] flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting) + * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK + * + * \details Encrypt provided message. Load Keys before this function is called + */ +extern uint8_t +rsa_encrypt(uint16_t rsa_bit_len, + const uint8_t* mesg, + uint16_t mlen, + uint8_t flags); + + + +/** + * \ rsa_decrypt + * + * \param [in] rsa_bit_len 1024, 2048 + * \param [in] encrypted_mesg Encrypted data + * \param [in] mlen length of encrypted message + * \param [in] flags flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting) + * \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK + * + * \details Perform decryption on provided encrypted message. load keys before calling this function + */ +extern uint8_t +rsa_decrypt(uint16_t rsa_bit_len, + const uint8_t* encrypted_mesg, + uint16_t mlen, + uint8_t flags); + + + +#ifdef __cplusplus +} +#endif + + +#endif /* INCLUDE_CEC1302_CRYPTO_API_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h new file mode 100644 index 000000000..b451de0f6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MCHP_CEC1302.h @@ -0,0 +1,5745 @@ + +/****************************************************************************************************//** + * @file MCHP_CEC1302.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * MCHP_CEC1302 from Microchip Technology Inc.. + * + * @version V1.1 + * @date 6. November 2015 + * + * @note Generated with SVDConv V2.87e + * from CMSIS SVD File 'MCHP_CEC1302.svd' Version 1.1, + * + * @par ARM Limited (ARM) is supplying this software for use with Cortex-M processor based + * microcontroller, but can be equally used for other suitable processor architectures. + * This file can be freely distributed. Modifications to this file shall be clearly marked. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *******************************************************************************************************/ + + + +/** @addtogroup Microchip Technology Inc. + * @{ + */ + +/** @addtogroup MCHP_CEC1302 + * @{ + */ + +#ifndef MCHP_CEC1302_H +#define MCHP_CEC1302_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ------------------- MCHP_CEC1302 Specific Interrupt Numbers ------------------ */ + I2C0_IRQn = 0, /*!< 0 I2C0 / SMB0 Interrupt ................. Also see GIRQ 12.0 */ + I2C1_IRQn = 1, /*!< 1 I2C1 / SMB1 Interrupt ................. Also see GIRQ 12.1 */ + I2C2_IRQn = 2, /*!< 2 I2C2 / SMB2 Interrupt ................. Also see GIRQ 12.2 */ + I2C3_IRQn = 3, /*!< 3 I2C3 / SMB3 Interrupt ................. Also see GIRQ 12.3 */ + DMA0_IRQn = 4, /*!< 4 DMA_CH0 Interrupt ..................... Also see GIRQ 13.16 */ + DMA1_IRQn = 5, /*!< 5 DMA_CH1 Interrupt ..................... Also see GIRQ 13.17 */ + DMA2_IRQn = 6, /*!< 6 DMA_CH2 Interrupt ..................... Also see GIRQ 13.18 */ + DMA3_IRQn = 7, /*!< 7 DMA_CH3 Interrupt ..................... Also see GIRQ 13.19 */ + DMA4_IRQn = 8, /*!< 8 DMA_CH4 Interrupt ..................... Also see GIRQ 13.20 */ + DMA5_IRQn = 9, /*!< 9 DMA_CH5 Interrupt ..................... Also see GIRQ 13.21 */ + DMA6_IRQn = 10, /*!< 10 DMA_CH6 Interrupt ..................... Also see GIRQ 13.22 */ + DMA7_IRQn = 11, /*!< 11 DMA_CH7 Interrupt ..................... Also see GIRQ 13.23 */ + LPC_IRQn = 12, /*!< 12 LPC Interrupt ......................... Also see GIRQ 14.2 */ + UART_IRQn = 13, /*!< 13 UART Interrupt ........................ Also see GIRQ 15.0 */ + EMI_0_IRQn = 14, /*!< 14 EMI_0 (IMAP) Interrupt ................ Also see GIRQ 15.2 */ + ACPIEC0_IBF_IRQn = 15, /*!< 15 ACPIEC[0] IBF Interrupt ............... Also see GIRQ 15.6 */ + ACPIEC0_OBF_IRQn = 16, /*!< 16 ACPIEC[0] OBF Interrupt ............... Also see GIRQ 15.7 */ + ACPIEC1_IBF_IRQn = 17, /*!< 17 ACPIEC[1] IBF Interrupt ............... Also see GIRQ 15.8 */ + ACPIEC1_OBF_IRQn = 18, /*!< 18 ACPIEC[1] OBF Interrupt ............... Also see GIRQ 15.9 */ + ACPIPM1_CTL_IRQn = 19, /*!< 19 ACPIPM1_CTL Interrupt ................. Also see GIRQ 15.10 */ + ACPIPM1_EN_IRQn = 20, /*!< 20 ACPIPM1_EN Interrupt .................. Also see GIRQ 15.11 */ + ACPIPM1_STS_IRQn = 21, /*!< 21 ACPIPM1_STS Interrupt ................. Also see GIRQ 15.12 */ + KBC8042_OBF_IRQn = 22, /*!< 22 8042EM OBF Interrupt .................. Also see GIRQ 15.13 */ + KBC8042_IBF_IRQn = 23, /*!< 23 8042EM IBF Interrupt .................. Also see GIRQ 15.14 */ + MAILBOX_IRQn = 24, /*!< 24 MAILBOX Interrupt ..................... Also see GIRQ 15.15 */ + PECIHOST_IRQn = 25, /*!< 25 PECIHOST Interrupt .................... Also see GIRQ 16.3 */ + TACH_0_IRQn = 26, /*!< 26 TACH_0 Interrupt ...................... Also see GIRQ 17.0 */ + TACH_1_IRQn = 27, /*!< 27 TACH_1 Interrupt ...................... Also see GIRQ 17.1 */ + ADC_SNGL_IRQn = 28, /*!< 28 ADC_SNGL Interrupt .................... Also see GIRQ 17.10 */ + ADC_RPT_IRQn = 29, /*!< 29 ADC_RPT Interrupt ..................... Also see GIRQ 17.11 */ + ADC2PWM_N1_IRQn = 30, /*!< 30 MCHP Reserved ADC2PWM_INT_N1 .......... Also see GIRQ 17.12 */ + ADC2PWM_N2_IRQn = 31, /*!< 31 MCHP Reserved ADC2PWM_INT_N2 .......... Also see GIRQ 17.13 */ + PS2_0_IRQn = 32, /*!< 32 PS2_0 Interrupt ....................... Also see GIRQ 17.14 */ + PS2_1_IRQn = 33, /*!< 33 PS2_1 Interrupt ....................... Also see GIRQ 17.15 */ + PS2_2_IRQn = 34, /*!< 34 PS2_2 Interrupt ....................... Also see GIRQ 17.16 */ + PS2_3_IRQn = 35, /*!< 35 PS2_3 Interrupt ....................... Also see GIRQ 17.17 */ + SPI0_TX_IRQn = 36, /*!< 36 SPI0 TX Interrupt ..................... Also see GIRQ 18.0 */ + SPI0_RX_IRQn = 37, /*!< 37 SPI0 RX Interrupt ..................... Also see GIRQ 18.1 */ + HTIMER_IRQn = 38, /*!< 38 HTIMER Interrupt ...................... Also see GIRQ 17.20 */ + KEYSCAN_IRQn = 39, /*!< 39 KSC Interrupt ......................... Also see GIRQ 17.21 */ + MAILBOX_DATA_IRQn = 40, /*!< 40 MAILBOX DATA Interrupt ................ Also see GIRQ 15.16 */ + RPM_STALL_IRQn = 41, /*!< 41 RPM_INT Stall Interrupt ............... Also see GIRQ 17.23 */ + RPM_SPIN_IRQn = 42, /*!< 42 RPM_INT Spin Interrupt ................ Also see GIRQ 17.24 */ + PFR_STS_IRQn = 43, /*!< 43 PFR_STS Interrupt ..................... Also see GIRQ 17.25 */ + PWM_WDT0_IRQn = 44, /*!< 44 PWM_WDT0 Interrupt .................... Also see GIRQ 17.26 */ + PWM_WDT1_IRQn = 45, /*!< 45 PWM_WDT1 Interrupt .................... Also see GIRQ 17.27 */ + PWM_WDT2_IRQn = 46, /*!< 46 PWM_WDT2 Interrupt .................... Also see GIRQ 17.28 */ + BCM_ERR_IRQn = 47, /*!< 47 BCM_INT Err Interrupt ................. Also see GIRQ 17.29 */ + BCM_BUSY_IRQn = 48, /*!< 48 BCM_INT Busy Interrupt ................ Also see GIRQ 17.30 */ + TIMER0_IRQn = 49, /*!< 49 TIMER_16_0 Interrupt .................. Also see GIRQ 23.0 */ + TIMER1_IRQn = 50, /*!< 50 TIMER_16_1 Interrupt .................. Also see GIRQ 23.1 */ + TIMER2_IRQn = 51, /*!< 51 TIMER_16_2 Interrupt .................. Also see GIRQ 23.2 */ + TIMER3_IRQn = 52, /*!< 52 TIMER_16_3 Interrupt .................. Also see GIRQ 23.3 */ + TIMER4_IRQn = 53, /*!< 53 TIMER_32_0 Interrupt .................. Also see GIRQ 23.4 */ + TIMER5_IRQn = 54, /*!< 54 TIMER_32_1 Interrupt .................. Also see GIRQ 23.5 */ + SPI1_TX_IRQn = 55, /*!< 55 SPI1 TX Interrupt ..................... Also see GIRQ 18.2 */ + SPI1_RX_IRQn = 56, /*!< 56 SPI1 RX Interrupt ..................... Also see GIRQ 18.3 */ + GIRQ08_IRQn = 57, /*!< 57 GIRQ08 ................................ Interrupt Aggregator */ + GIRQ09_IRQn = 58, /*!< 58 GIRQ09 ................................ Interrupt Aggregator */ + GIRQ10_IRQn = 59, /*!< 59 GIRQ10 ................................ Interrupt Aggregator */ + GIRQ11_IRQn = 60, /*!< 60 GIRQ11 ................................ Interrupt Aggregator */ + GIRQ12_IRQn = 61, /*!< 61 GIRQ12 ................................ Interrupt Aggregator */ + GIRQ13_IRQn = 62, /*!< 62 GIRQ13 ................................ Interrupt Aggregator */ + GIRQ14_IRQn = 63, /*!< 63 GIRQ14 ................................ Interrupt Aggregator */ + GIRQ15_IRQn = 64, /*!< 64 GIRQ15 ................................ Interrupt Aggregator */ + GIRQ16_IRQn = 65, /*!< 65 GIRQ16 ................................ Interrupt Aggregator */ + GIRQ17_IRQn = 66, /*!< 66 GIRQ17 ................................ Interrupt Aggregator */ + GIRQ18_IRQn = 67, /*!< 67 GIRQ18 ................................ Interrupt Aggregator */ + GIRQ19_IRQn = 68, /*!< 68 GIRQ19 ................................ Interrupt Aggregator */ + GIRQ20_IRQn = 69, /*!< 69 GIRQ20 ................................ Interrupt Aggregator */ + GIRQ21_IRQn = 70, /*!< 70 GIRQ21 ................................ Interrupt Aggregator */ + GIRQ22_IRQn = 71, /*!< 71 GIRQ22 ................................ Interrupt Aggregator */ + GIRQ23_IRQn = 72, /*!< 72 GIRQ23 ................................ Interrupt Aggregator */ + DMA8_IRQn = 81, /*!< 81 DMA_CH8 Interrupt ..................... Also see GIRQ 13.24 */ + DMA9_IRQn = 82, /*!< 82 DMA_CH9 Interrupt ..................... Also see GIRQ 13.25 */ + DMA10_IRQn = 83, /*!< 83 DMA_CH10 Interrupt .................... Also see GIRQ 13.26 */ + DMA11_IRQn = 84, /*!< 84 DMA_CH11 Interrupt .................... Also see GIRQ 13.27 */ + PWM_WDT3_IRQn = 85, /*!< 85 PWM_WDT3 Interrupt .................... Also see GIRQ 18.4 */ + RTC_IRQn = 91, /*!< 91 RTC Interrupt ......................... Also see GIRQ 17.18 */ + RTC_ALARM_IRQn = 92, /*!< 92 RTC ALARM Interrupt ................... Also see GIRQ 17.19 */ + MAX_IRQn +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + +/* ================================================================================ */ +/* ================ Custom Defines (added manually) ================ */ +/* ================================================================================ */ + +/* Register Union */ +typedef union +{ + uint32_t w; + uint16_t h[2]; + uint8_t b[4]; +} REG32_U; + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + +typedef struct { + union { + __IO uint16_t CR; /*!< MEM_BAR Control [15:0] */ + + struct { + __IO uint16_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint16_t FRAME : 6; /*!< Specify a logical device frame number */ + uint16_t : 1; + __IO uint16_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + } CR_b; /*!< BitSize */ + }; + __IO uint16_t HOST_LO_ADDR; /*!< HOST_ADDRESS[15:0] */ + __IO uint16_t HOST_HI_ADDR; /*!< HOST_ADDRESS[31:16] */ +} LPC_CONFIG_MEM_BAR_Type; + +typedef struct { + __IO uint32_t SOURCE; /*!< GIRQx Source Register(R/WC) */ + __IO uint32_t ENABLE_SET; /*!< GIRQx Enable Set Register (R/WS) */ + __I uint32_t RESULT; /*!< GIRQx Result Register */ + __IO uint32_t ENABLE_CLEAR; /*!< GIRQx Enable Clear Register. */ + __I uint32_t RESERVED; +} INTR_IRQ_Type; + +typedef struct { + union { + __IO uint8_t ACTIVATE; /*!< Enable this channel for operation. */ + + struct { + __IO uint8_t EN : 1; /*!< Enable this channel for operation. */ + } ACTIVATE_b; /*!< BitSize */ + }; + __I uint8_t RESERVED1[3]; + __IO uint32_t MEM_START_ADDR; /*!< starting address for the Memory device. */ + __IO uint32_t MEM_END_ADDR; /*!< ending address for the Memory device. */ + __IO uint32_t DEVICE_ADDR; /*!< This is the Master Device address. */ + + union { + __IO uint32_t CONTROL; /*!< DMA Channel N Control */ + + struct { + __IO uint32_t RUN : 1; /*!< 1= enabled and will service transfer requests */ + __I uint32_t REQUEST : 1; /*!< 1= transfer request from the Master Device */ + __I uint32_t DONE : 1; /*!< status signal. 1=Channel is done */ + __I uint32_t STATUS : 2; /*!< 3: Error,2/1: ext/locally done,0:Disabled */ + __IO uint32_t BUSY : 1; /*!< 1=Channel is busy (FSM is not IDLE) */ + uint32_t : 2; + __IO uint32_t TX_DIRECTION: 1; /*!< direction of Transfer. 1=Memory to Device */ + __IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< device as its Hardware Flow Control master. */ + __IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< auto-increment DMA Channel Memory Address. */ + __IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< auto-increment DMA Channel Device Address. */ + __IO uint32_t LOCK : 1; /*!< lock the arbitration of Channel Arbiter */ + __IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< Disable the Hardware Flow Control. */ + __IO uint32_t TRANSFER_SIZE: 3; /*!< transfer size in Bytes of each Data Packet */ + uint32_t : 1; + __IO uint32_t TRANSFER_GO: 1; /*!< Firmware Flow Control DMA transfer. */ + __IO uint32_t TRANSFER_ABORT: 1; /*!< abort the current transfer */ + } CONTROL_b; /*!< BitSize */ + }; + + union { + __IO uint8_t INT_STATUS; /*!< DMA Channel N Interrupt Status */ + + struct { + __IO uint8_t BUS_ERROR : 1; /*!< interrupt source. 1: Error detected.(R/WC) */ + __IO uint8_t FLOW_CONTROL: 1; /*!< Intr source.1=HW Flow Ctrl is requesting */ + __IO uint8_t DONE : 1; /*!< intr source. 1= Start Address equals End */ + } INT_STATUS_b; /*!< BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __IO uint8_t INT_EN; /*!< DMA CHANNEL N INTERRUPT ENABLE */ + + struct { + __IO uint8_t BUS_ERROR : 1; /*!< 1=enable Interrupt:Status AMBA Bus Error. */ + __IO uint8_t FLOW_CONTROL: 1; /*!< 1=enable Interrupt:Status Flow Control Error. */ + __IO uint8_t DONE : 1; /*!< 1=enable Interrupt:Status Done. + */ + } INT_EN_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[7]; +} DMA_CH_Type; + + +/* ================================================================================ */ +/* ================ PCR ================ */ +/* ================================================================================ */ + + +/** + * @brief The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies, + clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. (PCR) + */ + +typedef struct { /*!< PCR Structure */ + __IO uint32_t CHIP_SLP_EN; /*!< Chip Sleep Enable Register. (MCHP Reserved) */ + __I uint32_t CHIP_CLK_REQ_STS; /*!< Chip Clock Required Status. (MCHP Reserved) */ + + union { + __IO uint32_t EC_SLP_EN; /*!< EC Sleep Enable Register (EC_SLP_EN) */ + + struct { + __IO uint32_t INT_SLP_EN : 1; /*!< INT Sleep Enable (INT_SLP_EN) */ + __IO uint32_t PECI_SLP_EN: 1; /*!< PECI Sleep Enable (PECI_SLP_EN) */ + __IO uint32_t TACH0_SLP_EN: 1; /*!< TACH0 Sleep Enable (TACH0_SLP_EN) */ + uint32_t : 1; + __IO uint32_t PWM0_SLP_EN: 1; /*!< PWM0 Sleep Enable (PWM0_SLP_EN) */ + __IO uint32_t PMC_SLP_EN : 1; /*!< PMC Sleep Enable (PMC_SLP_EN) */ + __IO uint32_t DMA_SLP_EN : 1; /*!< DMA Sleep Enable (DMA_SLP_EN) */ + __IO uint32_t TFDP_SLP_EN: 1; /*!< TFDP Sleep Enable (TFDP_SLP_EN) */ + __IO uint32_t PROCESSOR_SLP_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_SLP_EN) */ + __IO uint32_t WDT_SLP_EN : 1; /*!< WDT Sleep Enable (WDT_SLP_EN) */ + __IO uint32_t SMB0_SLP_EN: 1; /*!< SMB0 Sleep Enable (SMB0_SLP_EN) */ + __IO uint32_t TACH1_SLP_EN: 1; /*!< TACH1 Sleep Enable (TACH1_SLP_EN) */ + uint32_t : 8; + __IO uint32_t PWM1_SLP_EN: 1; /*!< PWM1 Sleep Enable (PWM1_SLP_EN) */ + __IO uint32_t PWM2_SLP_EN: 1; /*!< PWM2 Sleep Enable (PWM2_SLP_EN) */ + __IO uint32_t PWM3_SLP_EN: 1; /*!< PWM3 Sleep Enable (PWM3_SLP_EN) */ + uint32_t : 6; + __IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< EC_REG_BANK Sleep Enable (EC_REG_BANK_SLP_EN) */ + __IO uint32_t TIMER16_0_SLP_EN: 1; /*!< TIMER16_0 Sleep Enable (TIMER16_0_SLP_EN) */ + __IO uint32_t TIMER16_1_SLP_EN: 1; /*!< TIMER16_1 Sleep Enable (TIMER16_1_SLP_EN) */ + } EC_SLP_EN_b; /*!< BitSize */ + }; + + union { + __I uint32_t EC_CLK_REQ_STS; /*!< EC Clock Required Status Registers */ + + struct { + __I uint32_t INT_CLK_REQ: 1; /*!< INT Clock Required (INT_CLK_REQ) */ + __I uint32_t PECI_CLK_REQ: 1; /*!< PECI Clock Required (PECI_CLK_REQ) */ + __I uint32_t TACH0_CLK_REQ: 1; /*!< TACH0 Clock Required (TACH0_CLK_REQ) */ + uint32_t : 1; + __I uint32_t PWM0_CLK_REQ: 1; /*!< PWM0 Clock Required (PWM0_CLK_REQ) */ + __I uint32_t PMC_CLK_REQ: 1; /*!< PMC Clock Required (PMC_CLK_REQ) */ + __I uint32_t DMA_CLK_REQ: 1; /*!< DMA Clock Required (DMA_CLK_REQ) */ + __I uint32_t TFDP_CLK_REQ: 1; /*!< TFDP Clock Required (TFDP_CLK_REQ) */ + __I uint32_t PROCESSOR_CLK_REQ: 1; /*!< PROCESSOR Clock Required (PROCESSOR_CLK_REQ) */ + __I uint32_t WDT_CLK_REQ: 1; /*!< WDT Clock Required (WDT_CLK_REQ) */ + __I uint32_t SMB0_CLK_REQ: 1; /*!< SMB0 Clock Required (SMB0_CLK_REQ) */ + __I uint32_t TACH1_CLK_REQ: 1; /*!< TACH1 Clock Required (TACH1_CLK_REQ) */ + uint32_t : 8; + __I uint32_t PWM1_CLK_REQ: 1; /*!< PWM1 Clock Required (PWM1_CLK_REQ) */ + __I uint32_t PWM2_CLK_REQ: 1; /*!< PWM2 Clock Required (PWM2_CLK_REQ) */ + __I uint32_t PWM3_CLK_REQ: 1; /*!< PWM3 Clock Required (PWM3_CLK_REQ) */ + uint32_t : 6; + __I uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< EC_REG_BANK Clock Required (EC_REG_BANK_CLK_REQ) */ + __I uint32_t TIMER16_0_CLK_REQ: 1; /*!< TIMER16_0 Clock Required (TIMER16_0_CLK_REQ) */ + __I uint32_t TIMER16_1_CLK_REQ: 1; /*!< TIMER16_1 Clock Required (TIMER16_1_CLK_REQ) */ + } EC_CLK_REQ_STS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HOST_SLP_EN; /*!< Host Sleep Enable Register (HOST_SLP_EN) */ + + struct { + __IO uint32_t LPC_SLP_EN : 1; /*!< LPC Sleep Enable (LPC_SLP_EN) */ + __IO uint32_t UART_0_SLP_EN: 1; /*!< UART 0 Sleep Enable (UART_0_SLP_EN) */ + uint32_t : 10; + __IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< GLBL_CFG (GLBL_CFG_SLP_EN) */ + __IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_EN) */ + __IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_EN) */ + __IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN) */ + __IO uint32_t KBCEM_SLP_EN: 1; /*!< 8042EM Sleep Enable (8042EM_SLP_EN) */ + uint32_t : 1; + __IO uint32_t RTC_SLP_EN : 1; /*!< RTC Sleep Enable (RTC_SLP_EN) */ + } HOST_SLP_EN_b; /*!< BitSize */ + }; + + union { + __I uint32_t HOST_CLK_REQ; /*!< Host Clock Required Status Registers */ + + struct { + __I uint32_t LPC_CLK_REQ: 1; /*!< LPC Clock Required (LPC_CLK_REQ) */ + __I uint32_t UART_0_CLK_REQ: 1; /*!< UART 0 Clock Required (UART_0_CLK_REQ) */ + uint32_t : 10; + __I uint32_t GLBL_CFG_CLK_REQ: 1; /*!< GLBL_CFG Clock Required (GLBL_CFG_CLK_REQ) */ + __I uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< ACPI EC 0 Clock Required (ACPI_EC_0_CLK_REQ) */ + __I uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< ACPI EC 1 Clock Required (ACPI_EC_1_CLK_REQ) */ + __I uint32_t ACPI_PM1_CLK_REQ: 1; /*!< ACPI PM1 Clock Required (ACPI_PM1_CLK_REQ) */ + __I uint32_t KBCEM_CLK_REQ: 1; /*!< 8042EM Clock Required (8042EM_CLK_REQ) */ + uint32_t : 1; + __I uint32_t RTC_CLK_REQ: 1; /*!< RTC Clock Required (RTC_CLK_REQ) */ + } HOST_CLK_REQ_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SYS_SLP_CNTRL; /*!< System Sleep Control Register */ + + struct { + __IO uint32_t ROSC_PD : 1; /*!< Ring oscillator power down (ROSC_PD) */ + __IO uint32_t ROSC_GATE : 1; /*!< Ring oscillator output gate (ROSC_GATE) */ + __IO uint32_t REGULATOR_STDBY: 1; /*!< Core regulator standby */ + } SYS_SLP_CNTRL_b; /*!< BitSize */ + }; + __I uint32_t RESERVED; + __IO uint32_t PROC_CLK_CNTRL; /*!< Processor Clock Control Register (PROC_CLK_CNTRL) [7:0] Processor + Clock Divide Value (PROC_DIV) + 1: divide 48 MHz Ring Oscillator by 1. + 4: divide 48 MHz Ring Oscillator by 4.(default) + 16: divide 48 MHz Ring Oscillator by 16. + 48: divide 48 MHz Ring Oscillator by 48. + No other values are supported + --------------------------------------------------------- */ + + union { + __IO uint32_t EC_SLP_EN2; /*!< EC Sleep Enable 2 Register (EC_SLP_EN2) */ + + struct { + uint32_t : 3; + __IO uint32_t ADC_SLP_EN : 1; /*!< ADC Sleep Enable (ADC_SLP_EN) */ + uint32_t : 1; + __IO uint32_t PS2_0_SLP_EN: 1; /*!< PS2_0 Sleep Enable (PS2_0_SLP_EN) */ + __IO uint32_t PS2_1_SLP_EN: 1; /*!< PS2_1 Sleep Enable (PS2_1_SLP_EN) */ + __IO uint32_t PS2_2_SLP_EN: 1; /*!< PS2_2 Sleep Enable (PS2_2_SLP_EN) */ + __IO uint32_t PS2_3_SLP_EN: 1; /*!< PS2_3 Sleep Enable (PS2_3_SLP_EN) */ + __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Sleep Enable (SPI0_SLP_EN) */ + __IO uint32_t HTIMER_SLP_EN: 1; /*!< HTIMER Sleep Enable (HTIMER_SLP_EN) */ + __IO uint32_t KEYSCAN_SLP_EN: 1; /*!< KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) */ + __IO uint32_t RPMPWM_SLP_EN: 1; /*!< RPM-PWM Sleep Enable (RPMPWM_SLP_EN) */ + __IO uint32_t SMB1_SLP_EN: 1; /*!< SMB1 Sleep Enable (SMB1_SLP_EN) */ + __IO uint32_t SMB2_SLP_EN: 1; /*!< SMB2 Sleep Enable (SMB2_SLP_EN) */ + __IO uint32_t SMB3_SLP_EN: 1; /*!< SMB3 Sleep Enable (SMB3_SLP_EN) */ + __IO uint32_t LED0_SLP_EN: 1; /*!< LED0 Sleep Enable (LED0_SLP_EN) */ + __IO uint32_t LED1_SLP_EN: 1; /*!< LED1 Sleep Enable (LED1_SLP_EN) */ + __IO uint32_t LED2_SLP_EN: 1; /*!< LED2 Sleep Enable (LED2_SLP_EN) */ + __IO uint32_t BCM_SLP_EN : 1; /*!< BCM Sleep Enable (BCM_SLP_EN) */ + __IO uint32_t SPI1_SLP_EN: 1; /*!< SPI1 Sleep Enable (SPI1_SLP_EN) */ + __IO uint32_t TIMER16_2_SLP_EN: 1; /*!< TIMER16_2_Sleep Enable (TIMER16_2_SLP_EN) */ + __IO uint32_t TIMER16_3_SLP_EN: 1; /*!< TIMER16_3 Sleep Enable (TIMER16_3_SLP_EN) */ + __IO uint32_t TIMER32_0_SLP_EN: 1; /*!< TIMER32_0 Sleep Enable (TIMER32_0_SLP_EN) */ + __IO uint32_t TIMER32_1_SLP_EN: 1; /*!< TIMER32_1 Sleep Enable (TIMER32_1_SLP_EN) */ + __IO uint32_t LED3_SLP_EN: 1; /*!< LED3 Sleep Enable (LED3_SLP_EN) */ + } EC_SLP_EN2_b; /*!< BitSize */ + }; + + union { + __I uint32_t EC_CLK_REQ2_STS; /*!< EC Clock Required 2 Status Register */ + + struct { + uint32_t : 3; + __I uint32_t ADC_CLK_REQ: 1; /*!< ADC Clock Required (ADC_CLK_REQ) */ + uint32_t : 1; + __I uint32_t PS2_0_SLP_CLK_REQ: 1; /*!< PS2_0 Clock Required (PS2_0_SLP_CLK_REQ) */ + __I uint32_t PS2_1_SLP_CLK_REQ: 1; /*!< PS2_1 Clock Required (PS2_1_SLP_CLK_REQ) */ + __I uint32_t PS2_2_SLP_CLK_REQ: 1; /*!< PS2_2 Clock Required (PS2_2_SLP_CLK_REQ) */ + __I uint32_t PS2_3_SLP_CLK_REQ: 1; /*!< PS2_3 Clock Required (PS2_3_SLP_CLK_REQ) */ + __I uint32_t SPI0_SLP_CLK_REQ: 1; /*!< SPI0 Clock Required (SPI0_SLP_CLK_REQ) */ + __I uint32_t HTIMER_SLP_CLK_REQ: 1; /*!< HTIMER Clock Required (HTIMER_SLP_CLK_REQ) */ + __I uint32_t KEYSCAN_SLP_CLK_REQ: 1; /*!< KEYSCAN Clock Required (KEYSCAN_SLP_CLK_REQ) */ + __I uint32_t RPMPWM_SLP_CLK_REQ: 1; /*!< RPM-PWM Clock Required (RPMPWM_SLP_CLK_REQ) */ + __I uint32_t SMB1_SLP_CLK_REQ: 1; /*!< SMB1 Clock Required (SMB1_SLP_CLK_REQ) */ + __I uint32_t SMB2_SLP_CLK_REQ: 1; /*!< SMB2 Clock Required (SMB2_SLP_CLK_REQ) */ + __I uint32_t SMB3_SLP_CLK_REQ: 1; /*!< SMB3 Clock Required (SMB3_SLP_CLK_REQ) */ + __I uint32_t LED0_SLP_CLK_REQ: 1; /*!< LED0 Clock Required (LED0_SLP_CLK_REQ) */ + __I uint32_t LED1_SLP_CLK_REQ: 1; /*!< LED1 Clock Required (LED1_SLP_CLK_REQ) */ + __I uint32_t LED2_SLP_CLK_REQ: 1; /*!< LED2 Clock Required (LED2_SLP_CLK_REQ) */ + __I uint32_t BCM_SLP_CLK_REQ: 1; /*!< BCM Clock Required (BCM_SLP_CLK_REQ) */ + __I uint32_t SPI1_SLP_CLK_REQ: 1; /*!< SPI1 Clock Required (SPI1_SLP_CLK_REQ) */ + __I uint32_t TIMER16_2_SLP_CLK_REQ: 1; /*!< TIMER16_2_Clock Required (TIMER16_2_SLP_CLK_REQ) */ + __I uint32_t TIMER16_3_SLP_CLK_REQ: 1; /*!< TIMER16_3 Clock Required (TIMER16_3_SLP_CLK_REQ) */ + __I uint32_t TIMER32_0_SLP_CLK_REQ: 1; /*!< TIMER32_0 Clock Required (TIMER32_0_SLP_CLK_REQ) */ + __I uint32_t TIMER32_1_SLP_CLK_REQ: 1; /*!< TIMER32_1 Clock Required (TIMER32_1_SLP_CLK_REQ) */ + __I uint32_t LED3_SLP_CLK_REQ: 1; /*!< LED3 Clock Required (LED3_SLP_CLK_REQ) */ + } EC_CLK_REQ2_STS_b; /*!< BitSize */ + }; + __IO uint32_t SLOW_CLK_CNTRL; /*!< Slow Clock Control Register (SLOW_CLK_CNTRL) Slow Clock (100 + kHz) Divide Value (slow_div) Configures the 100kHz_Clk. + 0: Clock off + n: divide by n. + Note: The default setting is for 100 kHz. + --------------------------------------------------------- */ + + union { + __I uint32_t CHIP_OSC_ID; /*!< Oscillator ID Register (CHIP_OSC_ID) */ + + struct { + uint32_t : 8; + __I uint32_t OSC_LOCK : 1; /*!< OSC_LOCK (OSC_LOCK) */ + } CHIP_OSC_ID_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CHIP_PWR_RST_STS; /*!< PCR chip sub-system power reset status */ + + struct { + uint32_t : 2; + __I uint32_t VCC_nRST : 1; /*!< 0=active, 1=not active (PWRGD asserted). */ + __I uint32_t SIO_nRST : 1; /*!< nSIO_RESET. 0=active, 1=not active. */ + uint32_t : 1; + __IO uint32_t VBAT_RST : 1; /*!< VBAT: 0=No reset, 1=reset occurred.(R/WC) */ + __IO uint32_t VCC1_RST : 1; /*!< VCC1: 0=No reset, 1=reset occurred.(R/WC) */ + uint32_t : 3; + __I uint32_t _32K_ACTIVE: 1; /*!< 32K_ACTIVE (32K_ACTIVE) */ + __I uint32_t PCICLK_ACTIVE: 1; /*!< PCICLK_ACTIVE (PCICLK_ACTIVE) */ + } CHIP_PWR_RST_STS_b; /*!< BitSize */ + }; + __IO uint32_t CHIP_RST_EN; /*!< Chip Reset Enable (MCHP Reserved) */ + + union { + __IO uint32_t HOST_RST_EN; /*!< Host Reset Enable Register */ + + struct { + __IO uint32_t LPC_RST_EN : 1; /*!< LPC Reset Enable (LPC_RST_EN) */ + __IO uint32_t UART_0_RST_EN: 1; /*!< UART 0 Reset Enable */ + uint32_t : 10; + __IO uint32_t GLBL_CFG_RST_EN: 1; /*!< GLBL_CFG Reset Enable */ + __IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< ACPI EC 0 Reset Enable */ + __IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< ACPI EC 1 Reset Enable */ + __IO uint32_t ACPI_PM1_RST_EN: 1; /*!< ACPI PM1 Reset Enable */ + __IO uint32_t KBCEM_RST_EN: 1; /*!< 8042EM Reset Enable */ + uint32_t : 1; + __IO uint32_t RTC_RST_EN : 1; /*!< RTC Reset Enable (RTC_RST_EN) */ + } HOST_RST_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t EC_RST_EN; /*!< EC Reset Enable Register */ + + struct { + __IO uint32_t INT_RST_EN : 1; /*!< INT Reset Enable (INT_RST_EN) */ + __IO uint32_t PECI_RST_EN: 1; /*!< PECI Reset Enable (PECI_RST_EN) */ + __IO uint32_t TACH0_RST_EN: 1; /*!< TACH0 Reset Enable (TACH0_RST_EN) */ + uint32_t : 1; + __IO uint32_t PWM0_RST_EN: 1; /*!< PWM0 Reset Enable (PWM0_RST_EN) */ + __IO uint32_t PMC_RST_EN : 1; /*!< PMC Reset Enable (PMC_RST_EN) */ + __IO uint32_t DMA_RST_EN : 1; /*!< DMA Reset Enable (DMA_RST_EN) */ + __IO uint32_t TFDP_RST_EN: 1; /*!< TFDP Reset Enable (TFDP_RST_EN) */ + __IO uint32_t PROCESSOR_RST_EN: 1; /*!< PROCESSOR Sleep Enable (PROCESSOR_RST_EN) */ + __IO uint32_t WDT_RST_EN : 1; /*!< WDT Reset Enable (WDT_RST_EN) */ + __IO uint32_t SMB0_RST_EN: 1; /*!< SMB0 Reset Enable (SMB0_RST_EN) */ + __IO uint32_t TACH1_RST_EN: 1; /*!< TACH1 Reset Enable (TACH1_RST_EN) */ + uint32_t : 8; + __IO uint32_t PWM1_RST_EN: 1; /*!< PWM1 Reset Enable (PWM1_RST_EN) */ + __IO uint32_t PWM2_RST_EN: 1; /*!< PWM2 Reset Enable (PWM2_RST_EN) */ + __IO uint32_t PWM3_RST_EN: 1; /*!< PWM3 Reset Enable (PWM3_RST_EN) */ + uint32_t : 6; + __IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< EC_REG_BANK Reset Enable (EC_REG_BANK_RST_EN) */ + __IO uint32_t TIMER16_0_RST_EN: 1; /*!< TIMER16_0 Reset Enable (TIMER16_0_RST_EN) */ + __IO uint32_t TIMER16_1_RST_EN: 1; /*!< TIMER16_1 Reset Enable (TIMER16_1_RST_EN) */ + } EC_RST_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t EC_RST_EN2; /*!< EC Reset Enable 2 Register */ + + struct { + uint32_t : 3; + __IO uint32_t ADC_RST_EN : 1; /*!< ADC Reset Enable (ADC_RST_EN) */ + uint32_t : 1; + __IO uint32_t PS2_0_RST_EN: 1; /*!< PS2_0 Reset Enable (PS2_0_RST_EN) */ + __IO uint32_t PS2_1_RST_EN: 1; /*!< PS2_1 Reset Enable (PS2_1_RST_EN) */ + __IO uint32_t PS2_2_RST_EN: 1; /*!< PS2_2 Reset Enable (PS2_2_RST_EN) */ + __IO uint32_t PS2_3_RST_EN: 1; /*!< PS2_3 Reset Enable (PS2_3_RST_EN) */ + __IO uint32_t SPI0_SLP_EN: 1; /*!< SPI0 Reset Enable (SPI0_SLP_EN) */ + __IO uint32_t HTIMER_RST_EN: 1; /*!< HTIMER Reset Enable (HTIMER_RST_EN) */ + __IO uint32_t KEYSCAN_RST_EN: 1; /*!< KEYSCAN Reset Enable (KEYSCAN_RST_EN) */ + __IO uint32_t RPMPWM_RST_EN: 1; /*!< RPM-PWM Reset Enable (RPMPWM_RST_EN) */ + __IO uint32_t SMB1_RST_EN: 1; /*!< SMB1 Reset Enable (SMB1_RST_EN) */ + __IO uint32_t SMB2_RST_EN: 1; /*!< SMB2 Reset Enable (SMB2_RST_EN) */ + __IO uint32_t SMB3_RST_EN: 1; /*!< SMB3 Reset Enable (SMB3_RST_EN) */ + __IO uint32_t LED0_RST_EN: 1; /*!< LED0 Reset Enable (LED0_RST_EN) */ + __IO uint32_t LED1_RST_EN: 1; /*!< LED1 Reset Enable (LED1_RST_EN) */ + __IO uint32_t LED2_RST_EN: 1; /*!< LED2 Reset Enable (LED2_RST_EN) */ + __IO uint32_t BCM_RST_EN : 1; /*!< BCM Reset Enable (BCM_RST_EN) */ + __IO uint32_t SPI1_RST_EN: 1; /*!< SPI1 Reset Enable (SPI1_RST_EN) */ + __IO uint32_t TIMER16_2_RST_EN: 1; /*!< TIMER16_2_Reset Enable (TIMER16_2_RST_EN) */ + __IO uint32_t TIMER16_3_RST_EN: 1; /*!< TIMER16_3 Reset Enable (TIMER16_3_RST_EN) */ + __IO uint32_t TIMER32_0_RST_EN: 1; /*!< TIMER32_0 Reset Enable (TIMER32_0_RST_EN) */ + __IO uint32_t TIMER32_1_RST_EN: 1; /*!< TIMER32_1 Reset Enable (TIMER32_1_RST_EN) */ + __IO uint32_t LED3_RST_EN: 1; /*!< LED3 Reset Enable (LED3_RST_EN) */ + } EC_RST_EN2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWR_RST_CTRL; /*!< Power Reset Control (PWR_RST_CTRL) Register */ + + struct { + __IO uint32_t IRESET_OUT : 1; /*!< iRESET_OUT (IRESET_OUT) */ + } PWR_RST_CTRL_b; /*!< BitSize */ + }; +} PCR_Type; + + +/* ================================================================================ */ +/* ================ VBAT ================ */ +/* ================================================================================ */ + + +/** + * @brief The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers + required the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem. + The VBAT Powered RAM provides a 64 Byte Random Accessed Memory that is operational while the main power rail is operational, + and will retain its values powered by battery power while the main rail is unpowered. (VBAT) + */ + +typedef struct { /*!< VBAT Structure */ + + union { + __IO uint8_t PFR_STS; /*!< Power-Fail and Reset Status Register */ + + struct { + __I uint8_t DET32K_IN : 1; /*!< XTAL[1:2] 0=No clock, 1= Clock detected */ + uint8_t : 4; + __IO uint8_t WDT : 1; /*!< 1=Watch-Dog Timer Forced Reset (R/WC). */ + uint8_t : 1; + __IO uint8_t VBAT_RST : 1; /*!< 1=VBAT_POR is detected.(R/WC) */ + } PFR_STS_b; /*!< BitSize */ + }; + __I uint8_t RESERVED[7]; + + union { + __IO uint32_t CLOCK_EN; /*!< CLOCK ENABLE Control */ + + struct { + __IO uint32_t XOSEL : 1; /*!< 32KHz, 1=single-ended, 0=crystal (default). */ + __IO uint32_t _32K_EN : 1; /*!< 1=32K_ON, 0=OFF (VBAT_POR default) */ + } CLOCK_EN_b; /*!< BitSize */ + }; +} VBAT_Type; + + +/* ================================================================================ */ +/* ================ LPC ================ */ +/* ================================================================================ */ + + +/** + * @brief Section 5.10, "EC-Only Registers"and Section 5.11, "Runtime Registers". (LPC) + */ + +typedef struct { /*!< LPC Structure */ + __IO uint8_t INDEX; /*!< A pointer to a Configuration Reg. Address. */ + __IO uint8_t DATA_REG; /*!< To rd/wt data with the INDEX Register. */ + __I uint16_t RESERVED[129]; + + union { + __I uint32_t BUS_MONITOR; /*!< LPC BUS MONITOR REGISTER */ + + struct { + uint32_t : 1; + __I uint32_t LRESET_STATUS: 1; /*!< Reflects the inverse state of LRESET# pin. */ + } BUS_MONITOR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HOST_BUS_ERROR; /*!< Host Bus Error Register */ + + struct { + __IO uint32_t LPC_ERR : 1; /*!< A BAR conflict or an internal bus error. (R/WC) */ + __IO uint32_t EN_ERR : 1; /*!< Internal bus errors. (R/WC) */ + __IO uint32_t BAR_ERR : 1; /*!< a BAR conflict occurs on an LPC address. (R/WC) */ + __IO uint32_t RUNTIME_ERR: 1; /*!< A BAR is misconfigured. (R/WC) */ + __IO uint32_t CONFIG_ERR : 1; /*!< LPC Config access causes a bus error.(R/WC) */ + __IO uint32_t DMA_ERR : 1; /*!< LPC DMA access causes a bus error. (R/WC) */ + uint32_t : 2; + __I uint32_t ERR_ADDR : 24; /*!< 24-bit internal addr. of LPC transaction */ + } HOST_BUS_ERROR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t EC_SERIRQ; /*!< the interrupt source of EC SERIRQ */ + + struct { + __IO uint32_t EC_IRQ : 1; /*!< interrupt source of a LPC Logical Device */ + } EC_SERIRQ_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CLK_CTRL; /*!< Controls throughput of LPC transactions. */ + + struct { + __IO uint32_t CR : 2; /*!< controls ring oscillator to be shut down. */ + __IO uint32_t HANDSHAKE : 1; /*!< controls throughput of LPC transactions. */ + } CLK_CTRL_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[3]; + __IO uint32_t BAR_INHIBIT; /*!< The BAR for Logical Device i is disabled */ + __I uint32_t RESERVED2[3]; + __IO uint32_t BAR_INIT; /*!< Init value of LPC BAR at offset 60h on nSIO_RESET. */ +} LPC_Type; + + +/* ================================================================================ */ +/* ================ LPC_CONFIG ================ */ +/* ================================================================================ */ + + +/** + * @brief LPC Configuration Registers. See Section 5.9 (LPC_CONFIG) + */ + +typedef struct { /*!< LPC_CONFIG Structure */ + __I uint32_t RESERVED[12]; + __IO uint8_t ACTIVATE; /*!< 1=LPC Logical Device is powered/functional */ + __I uint8_t RESERVED1[15]; + + union { + __IO uint8_t SIRQ[16]; /*!< 16 SIRQ channels */ + + struct { + __IO uint8_t FRAME : 6; /*!< Six bits select the Logical Device. */ + __IO uint8_t DEVICE : 1; /*!< Set to 0 in order to enable a SERIRQ. */ + __IO uint8_t SELECT : 1; /*!< 1: 1st LD's intr is selected,0: 2nd intr. */ + } SIRQ_b[16]; /*!< BitSize */ + }; + __I uint32_t RESERVED2[4]; + + union { + __IO uint32_t LPC_BAR; /*!< LPC Interface BAR Register */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } LPC_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t EM_BAR; /*!< EM Interface 0 BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } EM_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t UART_BAR; /*!< UART 0 BAR Register */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } UART_BAR_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[3]; + + union { + __IO uint32_t KBC_BAR; /*!< Keyboard Controller (8042) BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } KBC_BAR_b; /*!< BitSize */ + }; + __I uint32_t RESERVED4[3]; + + union { + __IO uint32_t EC0_BAR; /*!< ACPI EC Interface 0 BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } EC0_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t EC1_BAR; /*!< ACPI EC Interface 1 BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } EC1_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PM1_BAR; /*!< ACPI PM1 Interface BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } PM1_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t LGC_BAR; /*!< Legacy (GATEA20) Interface BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } LGC_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MBX_BAR; /*!< Mailbox Registers Interface BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } MBX_BAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTC_BAR; /*!< RTC Registers Interface BAR */ + + struct { + __IO uint32_t MASK : 8; /*!< Mask off LPC I/O address bits */ + __IO uint32_t FRAME : 6; /*!< Specify a logical device frame number */ + __IO uint32_t DEVICE : 1; /*!< combined w FRAME Logical Device Number. */ + __IO uint32_t VALID : 1; /*!< 1=the BAR is valid, 0= BAR is ignored */ + __IO uint32_t LPC_HOST_ADDR: 16; /*!< To match LPC I/O addresses */ + } RTC_BAR_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5[8]; + + union { + LPC_CONFIG_MEM_BAR_Type MBX_MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */ + LPC_CONFIG_MEM_BAR_Type MEM_BAR; /*!< Mailbox Registers I/F Memory BAR */ + }; + LPC_CONFIG_MEM_BAR_Type EC0_MEM_BAR; /*!< ACPI EC Interface 0 Memory BAR */ + LPC_CONFIG_MEM_BAR_Type EC1_MEM_BAR; /*!< ACPI EC Interface 1 Memory BAR */ + LPC_CONFIG_MEM_BAR_Type EMI_MEM_BAR; /*!< EM Interface 0 Memory BAR */ +} LPC_CONFIG_Type; + + +/* ================================================================================ */ +/* ================ GCR ================ */ +/* ================================================================================ */ + + +/** + * @brief The Logical Device Configuration registers support motherboard designs in which the resources required + by their components are known and assigned by the BIOS at POST. (GCR) + */ + +typedef struct { /*!< GCR Structure */ + __I uint8_t RESERVED[7]; + __IO uint8_t LOGICAL_DEVICE_NUMBER; /*!< Selects the current logical device. */ + __I uint32_t RESERVED1[6]; + __I uint8_t DEVICE_ID; /*!< provides device identification. */ + __I uint8_t DEVICE_REVISION; /*!< provides device revision information. */ +} GCR_Type; + + +/* ================================================================================ */ +/* ================ EMI ================ */ +/* ================================================================================ */ + + +/** + * @brief The Embedded Memory Interface (EMI) provides a standard run-time mechanism for the system host + to communicate with the Embedded Controller (EC) and other logical components. (EMI) + */ + +typedef struct { /*!< EMI Structure */ + __IO uint8_t HOST_EC_MBX; /*!< Host-to-EC Mailbox Register */ + __IO uint8_t EC_HOST_MBX; /*!< EC-to-Host Mailbox Register (R/WC) */ + + union { + __IO uint16_t EC_ADDRESS; /*!< EC Address Access Control Register */ + + struct { + __IO uint16_t ACCESS_TYPE: 2; /*!< defines the type of EC Data rd/wt access */ + __IO uint16_t EC_ADDRESS : 13; /*!< defines bits[14:2] of EC_Address [15:0]. */ + __IO uint16_t REGION : 1; /*!< Selector of two segments. */ + } EC_ADDRESS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t EC_DATA; /*!< EC Data Register */ + __IO uint8_t EC_DATA_BYTE[4]; /*!< EC Data Byte Register */ + }; + + union { + __IO uint16_t EC_SWI; /*!< Notification of EC Software Interrupt */ + + struct { + __I uint16_t EC_WR : 1; /*!< EC Mailbox Write. */ + __IO uint16_t NOTIFICATION: 15; /*!< EC to notify the host of an event(R/WC) */ + } EC_SWI_b; /*!< BitSize */ + }; + __IO uint16_t EC_SWI_EN; /*!< [15:1] enables generation of Event interrupts */ + __IO uint8_t APPLICATION_ID; /*!< Application ID Register */ + __I uint8_t RESERVED[243]; + __IO uint8_t HOST2EC_MBX; /*!< Host-to-EC Mailbox Register(R/WC) */ + __IO uint8_t EC2HOST_MBX; /*!< EC-to-Host Mailbox Register */ + __I uint16_t RESERVED1; + __IO uint32_t MEMORY_BASE_ADDRESS_0; /*!< [31:2] defines the beginning of region 0 */ + __IO uint16_t MEMORY_READ_LIMIT_0; /*!< [14:2]Memory Read Limit 0 Register */ + __IO uint16_t MEMORY_WRITE_LIMIT_0; /*!< [14:2] Memory Write Limit 0 Register */ + __IO uint32_t MEMORY_BASE_ADDRESS_1; /*!< [31:2] defines the beginning of region 1 */ + __IO uint16_t MEMORY_READ_LIMIT_1; /*!< [14:2]Memory Read Limit 1 Register */ + __IO uint16_t MEMORY_WRITE_LIMIT_1; /*!< [14:2] Memory Write Limit 1 Register */ + __IO uint16_t EC_SWI_SET; /*!< [15:1] Interrupt Set Register */ + __IO uint16_t EC_SWI_CLR; /*!< [15:1] Host Clear Enable Register */ +} EMI_Type; + + +/* ================================================================================ */ +/* ================ ACPI_EC0 ================ */ +/* ================================================================================ */ + + +/** + * @brief The ACPI Embedded Controller Interface (ACPI-ECI) provides a four byte full duplex data interface + which is a superset of the standard ACPI Embedded Controller Interface (ACPI-ECI) one byte data interface. The + ACPI Embedded Controller Interface (ACPI-ECI) defaults to the standard one byte interface. (ACPI_EC0) + */ + +typedef struct { /*!< ACPI_EC0 Structure */ + + union { + __IO uint32_t OS_DATA; /*!< ACPI OS Data Register */ + __IO uint8_t OS_DATA_BYTE[4]; /*!< aliased to the OS2EC DATA BYTES[n]. */ + }; + + union { + union { + __I uint8_t OS_STATUS; /*!< aliased to the EC STATUS Register */ + + struct { + __I uint8_t OBF : 1; /*!< Output Buffer Full bit */ + __I uint8_t IBF : 1; /*!< Input Buffer Full bit */ + __I uint8_t UD1B : 1; /*!< User Defined */ + __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */ + __I uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */ + __I uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */ + __I uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */ + __I uint8_t UD0B : 1; /*!< User Defined */ + } OS_STATUS_b; /*!< BitSize */ + }; + __O uint8_t OS_COMMAND; /*!< aliased to the OS2EC Data Byte0 */ + }; + __I uint8_t OS_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */ + __I uint16_t RESERVED[125]; + + union { + __IO uint32_t EC2OS_DATA; /*!< EC2OS Data */ + __IO uint8_t EC2OS_DATA_BYTE[4]; /*!< EC2OS Data Bytes */ + }; + + union { + __IO uint8_t EC_STATUS; /*!< EC STATUS */ + + struct { + __I uint8_t OBF : 1; /*!< Output Buffer Full bit */ + __I uint8_t IBF : 1; /*!< Input Buffer Full bit */ + __I uint8_t UD1A : 1; /*!< User Defined */ + __I uint8_t CMD : 1; /*!< OS2EC Data contains a command byte */ + __IO uint8_t BURST : 1; /*!< set when the ACPI_EC is in Burst Mode */ + __IO uint8_t SCI_EVT : 1; /*!< set when an SCI event is pending */ + __IO uint8_t SMI_EVT : 1; /*!< set when an SMI event is pending */ + __IO uint8_t UD0A : 1; /*!< User Defined */ + } EC_STATUS_b; /*!< BitSize */ + }; + __IO uint8_t EC_BYTE_CONTROL; /*!< OS Control [0:0] FOUR_BYTE_ACCESS */ + __I uint16_t RESERVED1; + + union { + __IO uint32_t OS2EC_DATA; /*!< OS2EC Data EC-Register */ + __IO uint8_t OS2EC_DATA_BYTE[4]; /*!< OS2EC Data Bytes */ + }; +} ACPI_EC0_Type; + + +/* ================================================================================ */ +/* ================ KBC ================ */ +/* ================================================================================ */ + + +/** + * @brief The CEC1302 keyboard controller uses the EC to produce a superset of the + features provided by the industry-standard 8042 keyboard controller. The 8042 Emulated + Keyboard Controller is a Host/EC Message Interface with hardware assists to emulate 8042 + behavior and provide Legacy GATEA20 support. (KBC) + */ + +typedef struct { /*!< KBC Structure */ + + union { + __O uint8_t WT_PORT60_DATA; /*!< Host_EC Data Register (=Host Write 60h) */ + __I uint8_t RD_PORT60_DATA; /*!< EC_Host Data/Aux Register (=Host Read 60h) */ + }; + __I uint8_t RESERVED[3]; + + union { + union { + __I uint8_t RD_PORT64_STATUS; /*!< Keyboard Status Register (=Host Read 64h) */ + + struct { + __I uint8_t OBF : 1; /*!< Output Buffer Full. */ + __I uint8_t IBF : 1; /*!< Input Buffer Full. */ + __I uint8_t UD0 : 1; /*!< User-defined data. */ + __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */ + __I uint8_t UD1 : 1; /*!< User-defined data. */ + __I uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */ + __I uint8_t UD2 : 2; /*!< User-defined data. */ + } RD_PORT64_STATUS_b; /*!< BitSize */ + }; + __O uint8_t WT_PORT64_CMD; /*!< Host_EC Command Register (=Host Write 64h) */ + }; + __I uint8_t RESERVED1[251]; + + union { + __O uint8_t EC_DATA; /*!< EC2Host Data Register */ + __I uint8_t HOST2EC_DATA; /*!< Host2EC Data/Cmd Register */ + }; + __I uint8_t RESERVED2[3]; + + union { + __IO uint8_t STATUS; /*!< EC KEYBOARD STATUS REGISTER */ + + struct { + __I uint8_t OBF : 1; /*!< Output Buffer Full. */ + __I uint8_t IBF : 1; /*!< Input Buffer Full. */ + __IO uint8_t UD0 : 1; /*!< User-defined data. */ + __I uint8_t CMDnDATA : 1; /*!< data register contains data(0) or command(1) */ + __IO uint8_t UD1 : 1; /*!< User-defined data. */ + __IO uint8_t AUXOBF : 1; /*!< Auxiliary Output Buffer Full. */ + __IO uint8_t UD2 : 2; /*!< User-defined data. */ + } STATUS_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __IO uint8_t CONTROL; /*!< Keyboard Control Register */ + + struct { + __IO uint8_t UD3 : 1; /*!< User-defined data. */ + __IO uint8_t SAEN : 1; /*!< Software-assist enable. */ + __IO uint8_t PCOBFEN : 1; /*!< 1=write to PCOBF, 0=writes to EC Data Reg. */ + __IO uint8_t UD4 : 2; /*!< User-defined data. */ + __IO uint8_t OBFEN : 1; /*!< 1=KIRQ is driven by PCOBF and MIRQ */ + __IO uint8_t UD5 : 1; /*!< User-defined data. */ + __IO uint8_t AUXH : 1; /*!< AUX in Hardware. */ + } CONTROL_b; /*!< BitSize */ + }; + __I uint8_t RESERVED4[3]; + __O uint8_t AUX_DATA; /*!< EC_Host Aux Register */ + __I uint8_t RESERVED5[7]; + __IO uint8_t PCOBF; /*!< [0:0] PCOBF Register */ + __I uint8_t RESERVED6[539]; + __IO uint8_t ACTIVATE; /*!< [0:0] 1=8042 I/F is powered/functional */ +} KBC_Type; + + +/* ================================================================================ */ +/* ================ PORT92 ================ */ +/* ================================================================================ */ + + +/** + * @brief The registers listed in the Configuration Register Summary table are for a + single instance of the Legacy Port92 and GATEA20 logic. (PORT92) + */ + +typedef struct { /*!< PORT92 Structure */ + + union { + __IO uint8_t PORT92; /*!< Support GATE_A20 CPU_RESET control */ + + struct { + __IO uint8_t ALT_CPU_RESET: 1; /*!< provides to generate a CPU_RESET pulse. */ + __IO uint8_t ALT_GATE_A20: 1; /*!< provides system to control GATEA20 pin. */ + } PORT92_b; /*!< BitSize */ + }; + __I uint8_t RESERVED[255]; + __IO uint8_t GATEA20; /*!< [0:0] 0=GATEA20 output low, 1=outputn high */ + __I uint8_t RESERVED1[7]; + __O uint8_t SETGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */ + __I uint8_t RESERVED2[3]; + __IO uint8_t RSTGA20L; /*!< write to set GATEA20 in GATEA20 Control Reg */ + __I uint8_t RESERVED3[547]; + __IO uint8_t PORT92_ENABLE; /*!< [0:0] 1= Port92h Register is enabled. */ +} PORT92_Type; + + +/* ================================================================================ */ +/* ================ MBX ================ */ +/* ================================================================================ */ + + +/** + * @brief The Mailbox provides a standard run-time mechanism for the host to + communicate with the Embedded Controller (EC) (MBX) + */ + +typedef struct { /*!< MBX Structure */ + __IO uint8_t INDEX; /*!< MBX_Index Register */ + __IO uint8_t DATA_REG; /*!< MBX_Data_Register */ + __I uint16_t RESERVED[127]; + __IO uint8_t HOST_TO_EC; /*!< HOST-to-EC Mailbox Register */ + __I uint8_t RESERVED1[3]; + __IO uint8_t EC_TO_HOST; /*!< EC-to-Host Mailbox Register */ + __I uint8_t RESERVED2[3]; + + union { + __IO uint8_t SMI_SOURCE; /*!< SMI Interrupt Source Register */ + + struct { + __I uint8_t EC_WR : 1; /*!< EC Mailbox Write (flag). */ + __IO uint8_t EC_SMI : 7; /*!< EC Software Interrupt source control */ + } SMI_SOURCE_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __IO uint8_t SMI_MASK; /*!< SMI Interrupt Mask Register */ + + struct { + __IO uint8_t EC_WR_EN : 1; /*!< EC Mailbox Write Interrupt Enable. */ + __IO uint8_t EC_SMI_EN : 7; /*!< EC Software Interrupt Enable. */ + } SMI_MASK_b; /*!< BitSize */ + }; + __I uint8_t RESERVED4[3]; + __IO uint8_t REG[42]; /*!< Mailbox Register */ +} MBX_Type; + + +/* ================================================================================ */ +/* ================ PM1 ================ */ +/* ================================================================================ */ + + +/** + * @brief The CEC1302 implements the ACPI fixed registers but includes only those bits that apply to the power + button sleep button and RTC alarm events. The ACPI WAK_STS, SLP_TYP, and SLP_EN bits are also supported. (PM1) + */ + +typedef struct { /*!< PM1 Structure */ + __I uint8_t RESERVED; + + union { + __IO uint8_t STS2; /*!< PM1 Status 2 */ + + struct { + __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */ + __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */ + __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */ + __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */ + uint8_t : 3; + __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */ + } STS2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED1; + + union { + __IO uint8_t EN2; /*!< PM1 Enable 2 */ + + struct { + __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */ + } EN2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED2; + + union { + __IO uint8_t CTRL2; /*!< PM1 Control 2 */ + + struct { + uint8_t : 1; + __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */ + } CTRL2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[251]; + + union { + __IO uint8_t STS_2; /*!< PM1 Status 2 */ + + struct { + __IO uint8_t PWRBTN_STS : 1; /*!< simulate a Power button status (R/WC) */ + __IO uint8_t SLPBTN_STS : 1; /*!< simulate a Sleep button status (R/WC) */ + __IO uint8_t RTC_STS : 1; /*!< simulate a RTC status. (R/WC) */ + __IO uint8_t PWRBTNOR_STS: 1; /*!< simulate a Power button override status(R/WC) */ + uint8_t : 3; + __IO uint8_t WAK_STS : 1; /*!< Host writing a one to this bit. (R/WC) */ + } STS_2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED4; + + union { + __IO uint8_t EN_2; /*!< PM1 Enable 2 */ + + struct { + __IO uint8_t PWRBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t SLPBTN_EN : 1; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t RTC_EN : 1; /*!< Controlled by Host. read by the EC. */ + } EN_2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED5; + + union { + __IO uint8_t CTRL_2; /*!< PM1 Control 2 */ + + struct { + uint8_t : 1; + __IO uint8_t PWRBTNOR_EN: 1; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t SLP_TYP : 3; /*!< Controlled by Host. read by the EC. */ + __IO uint8_t SLP_EN : 1; /*!< Host Wt 1 to set, EC wt 1 to Clr */ + } CTRL_2_b; /*!< BitSize */ + }; + __I uint16_t RESERVED6[5]; + __IO uint8_t PM_STS; /*!< [0:0]wt 1 interrupt is generated on EC_SCI# */ +} PM1_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief The 16550 UART (Universal Asynchronous Receiver/Transmitter) is a full-function + Two Pin Serial Port that supports the standard RS-232 Interface. (UART) + */ + +typedef struct { /*!< UART Structure */ + + union { + __O uint8_t TX_DATA; /*!< UART Transmit Buffer Register */ + __I uint8_t RX_DATA; /*!< UART Receive Buffer Register */ + __IO uint8_t BAUDRATE_LSB; /*!< Programmable BAUD Rate Generator (LSB) Reg. */ + }; + + union { + union { + __IO uint8_t INT_EN; /*!< UART Interrupt Enable Register */ + + struct { + __IO uint8_t ERDAI : 1; /*!< enables Received Data Available Interrupt */ + __IO uint8_t ETHREI : 1; /*!< enables Transmitter Holding Empty Interrupt */ + __IO uint8_t ELSI : 1; /*!< enables Received Line Status Interrupt */ + __IO uint8_t EMSI : 1; /*!< enables the MODEM Status Interrupt */ + } INT_EN_b; /*!< BitSize */ + }; + __IO uint8_t BAUDRATE_MSB; /*!< [6:0]BAUD_RATE_DIVISOR_MSB [7]BAUD_CLK_SEL */ + }; + + union { + union { + __I uint8_t INT_ID; /*!< UART Interrupt Identification Register */ + + struct { + __I uint8_t IPEND : 1; /*!< indicate whether an interrupt is pending. */ + __I uint8_t INTID : 3; /*!< highest priority interrupt pending */ + uint8_t : 2; + __I uint8_t FIFO_EN : 2; /*!< two bits are set when FIFO CONTROL bit 0=1 */ + } INT_ID_b; /*!< BitSize */ + }; + + union { + __O uint8_t FIFO_CR; /*!< UART FIFO Control Register */ + + struct { + __O uint8_t EXRF : 1; /*!< Enable XMIT and RECV FIFO. */ + __O uint8_t CLEAR_RECV_FIFO: 1; /*!< clears all bytes in RCVR FIFO, resets counter */ + __O uint8_t CLEAR_XMIT_FIFO: 1; /*!< clears all bytes in XMIT FIFO, resets counter */ + __IO uint8_t DMA_MODE_SELECT: 1; /*!< RXRDY,TXRDY pins functions are reserved. */ + uint8_t : 2; + __IO uint8_t RECV_FIFO_TRIGGER_LEVEL: 2; /*!< set trigger level for RCVR FIFO Intr */ + } FIFO_CR_b; /*!< BitSize */ + }; + }; + + union { + __IO uint8_t LINE_CR; /*!< UART Line Control Register */ + + struct { + __IO uint8_t WORD_LENGTH: 2; /*!< number of bits in transmitted or received */ + __IO uint8_t STOP_BITS : 1; /*!< number of stop bits in transmitted or received */ + __IO uint8_t ENABLE_PARITY: 1; /*!< Parity Enable bit. */ + __IO uint8_t PARITY_SELECT: 1; /*!< Even Parity Select bit. */ + __IO uint8_t STICK_PARITY: 1; /*!< Stick Parity bit. */ + __IO uint8_t BREAK_CONTROL: 1; /*!< Set Break Control bit */ + __IO uint8_t DLAB : 1; /*!< DLAB Divisor Latch Access Bit (DLAB). */ + } LINE_CR_b; /*!< BitSize */ + }; + + union { + __IO uint8_t MODEM_CR; /*!< UART Modem Control Register */ + + struct { + __IO uint8_t DTR : 1; /*!< Data Terminal Ready (nDTR) output. */ + __IO uint8_t RTS : 1; /*!< Request To Send (nRTS) output. */ + __IO uint8_t OUT1 : 1; /*!< controls the Output 1 (OUT1) bit. */ + __IO uint8_t OUT2 : 1; /*!< enable an UART interrupt. */ + __IO uint8_t LOOPBACK : 1; /*!< provides loopback for diagnostic */ + } MODEM_CR_b; /*!< BitSize */ + }; + + union { + __I uint8_t LINE_STS; /*!< UART Line Status Register */ + + struct { + __I uint8_t DATA_READY : 1; /*!< 1= data into Rx Buffer Register or FIFO */ + __I uint8_t OVERRUN : 1; /*!< OVERRUN Overrun Error. */ + __I uint8_t PE : 1; /*!< PARITY ERROR Parity Error. */ + __I uint8_t FRAME_ERROR: 1; /*!< FRAME_ERROR Framing Error. */ + __I uint8_t BREAK_INTERRUPT: 1; /*!< BREAK_INTERRUPT Break Interrupt. */ + __I uint8_t TRANSMIT_EMPTY: 1; /*!< Transmitter Holding Register Empty */ + __I uint8_t TRANSMIT_ERROR: 1; /*!< Transmitter Holding/Shift are both empty. */ + __I uint8_t FIFO_ERROR : 1; /*!< FIFO_ERROR */ + } LINE_STS_b; /*!< BitSize */ + }; + + union { + __I uint8_t MODEM_STS; /*!< UART Modem Status Register */ + + struct { + __I uint8_t CTS : 1; /*!< CTS Delta Clear To Send (DCTS). */ + __I uint8_t DSR : 1; /*!< DSR Delta Data Set Ready (DDSR). */ + __I uint8_t RI : 1; /*!< Trailing Edge of Ring Indicator (TERI). */ + __I uint8_t DCD : 1; /*!< DCD Delta Data Carrier Detect (DDCD). */ + __IO uint8_t nCTS : 1; /*!< complement of Clear To Send (nCTS) input. */ + __IO uint8_t nDSR : 1; /*!< complement of Data Set Ready (nDSR) input. */ + __IO uint8_t nRI : 1; /*!< complement of Ring Indicator (nRI) input. */ + __IO uint8_t nDCD : 1; /*!< complement of Data Carrier Detect (nDCD) input. */ + } MODEM_STS_b; /*!< BitSize */ + }; + __IO uint8_t SCRATCHPAD; /*!< as a scratchpad reg. be used by programmer */ + __I uint32_t RESERVED[202]; + __IO uint8_t ACTIVATE; /*!< [0:0] 1= UART is powered/functional. */ + __I uint8_t RESERVED1[191]; + + union { + __IO uint8_t CONFIG; /*!< UART Config Select Register */ + + struct { + __IO uint8_t CLK_SRC : 1; /*!< 1=Baud Clock from external clock, 0=internal */ + __IO uint8_t POWER : 1; /*!< 1=reset from nSIO_RESET, 0=VCC1_RESET */ + __IO uint8_t POLARITY : 1; /*!< 1=UART_TX and UART_RX pins are inverted */ + } CONFIG_b; /*!< BitSize */ + }; +} UART_Type; + + +/* ================================================================================ */ +/* ================ INTR ================ */ +/* ================================================================================ */ + + +/** + * @brief The interrupt generation logic is made of 16 groups of signals, each of which + consist of a Status register, a Enable register and a Result register. The Status and Enable + are latched registers. The Result register is a bit by bit AND function of the Source and Enable + registers. All the bits of the Result register are OR'ed together and AND'ed with the corresponding + bit in the Block Select register to form the interrupt signal that is routed to the ARM interrupt controller. (INTR) + */ + +typedef struct { /*!< INTR Structure */ + INTR_IRQ_Type IRQ[16]; /*!< DEFINITIONS FOR GIRQi SOURCE/ENABLE/RESULT */ + __I uint32_t RESERVED[48]; + __IO uint32_t BLOCK_ENABLE_SET; /*!< [23:8] IRQ Vector Enable Set */ + __IO uint32_t BLOCK_ENABLE_CLEAR; /*!< [23:8] IRQ Vector Enable Clear */ + __I uint32_t IRQ_VECTOR_STATE; /*!< [23:8] reflects current state of IRQi */ +} INTR_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ + + +/** + * @brief The function of the Watchdog Timer is to provide a mechanism to detect if the + internal embedded controller has failed. When enabled, the Watchdog Timer (WDT) circuit will generate + a WDT Event if the user program fails to reload the WDT within a specified length of time known as the WDT Interval. (WDT) + */ + +typedef struct { /*!< WDT Structure */ + __IO uint16_t LOAD; /*!< Writing to reload Watch Dog Timer counter */ + __I uint16_t RESERVED; + + union { + __IO uint8_t CONTROL; /*!< WDT Control Register */ + + struct { + __IO uint8_t ENABLE : 1; /*!< WDT Block enabled */ + __IO uint8_t STATUS : 1; /*!< last reset was caused by an underflow (R/WC) */ + } CONTROL_b; /*!< BitSize */ + }; + __I uint8_t RESERVED1[3]; + __O uint8_t KICK; /*!< Writes to reload and start decrementing */ + __I uint8_t RESERVED2[3]; + __I uint16_t COUNT; /*!< current WDT count. */ +} WDT_Type; + + +/* ================================================================================ */ +/* ================ TIMER_16_0 ================ */ +/* ================================================================================ */ + + +/** + * @brief This timer block offers a simple mechanism for firmware to maintain a time + base. This timer may be instantiated as 16 bits or 32 bits. (TIMER_16_0) + */ + +typedef struct { /*!< TIMER_16_0 Structure */ + __IO uint32_t COUNT; /*!< Timer counter. may be set by Firmware. */ + __IO uint32_t PRE_LOAD; /*!< Timer pre-load for counter upon restart. */ + __IO uint32_t INTERRUPT_STATUS; /*!< [0:0] Interrupt status (R/WC) */ + __IO uint32_t INTERRUPT_ENABLE; /*!< [0:0] interrupt enable */ + + union { + __IO REG32_U CONTROL; /*!< Timer Control Register */ + + struct { + __IO uint32_t ENABLE : 1; /*!< This enables the block for operation. */ + uint32_t : 1; + __IO uint32_t COUNT_UP : 1; /*!< This selects the counter direction. */ + __IO uint32_t AUTO_RESTART: 1; /*!< select action taken upon completing a count. */ + __IO uint32_t SOFT_RESET : 1; /*!< soft reset. self clearing 1 cycle. */ + __IO uint32_t START : 1; /*!< This bit triggers the timer counter. */ + __IO uint32_t RELOAD : 1; /*!< reloads counter without interrupting. */ + __IO uint32_t HALT : 1; /*!< halt bit. */ + uint32_t : 8; + __IO uint32_t PRE_SCALE : 16; /*!< to divide down system clock */ + } CONTROL_b; /*!< BitSize */ + }; +} TIMER_16_0_Type; + + +/* ================================================================================ */ +/* ================ HTM ================ */ +/* ================================================================================ */ + + +/** + * @brief The Hibernation Timer can generate a wake event to the Embedded Controller (EC) + when it is in a hibernation mode. This block supports wake events up to 2 hours in duration. + The timer is a 16-bit binary count-down timer that can be programmed in 30.5us and 0.125 second + increments for period ranges of 30.5us to 2s or 0.125s to 136.5 minutes, respectively. (HTM) + */ + +typedef struct { /*!< HTM Structure */ + __IO uint16_t PRELOAD; /*!< [15:0] set Hibernation Timer Preload value */ + __I uint16_t RESERVED; + __IO uint16_t CONTROL; /*!< [0:0] 1= resolution 0.125s, 0= 30.5us */ + __I uint16_t RESERVED1; + __I uint16_t COUNT; /*!< Count of the Hibernation Timer. */ +} HTM_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief This is the set of registers that are automatically counted by hardware + every 1 second while the block is enabled to run and to update. These registers are: + Seconds, Minutes, Hours, Day of Week, Day of Month, Month, and Year. (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IO uint8_t SEC; /*!< Seconds Register */ + __IO uint8_t SEC_ALARM; /*!< Seconds Alarm Register */ + __IO uint8_t MIN; /*!< Minutes Register */ + __IO uint8_t MIN_ALARM; /*!< Minutes Alarm Register */ + __IO uint8_t HR; /*!< Hours Register */ + __IO uint8_t HR_ALARM; /*!< Hours Alarm Register */ + __IO uint8_t DAY_WEEK; /*!< Day of Week Register */ + __IO uint8_t DAY_MONTH; /*!< Day of Month Register */ + __IO uint8_t MONTH; /*!< Month Register */ + __IO uint8_t YEAR; /*!< Year Register */ + __IO uint8_t REG_A; /*!< Register A */ + __IO uint8_t REG_B; /*!< Register B */ + __IO uint8_t REG_C; /*!< Register C */ + __IO uint8_t REG_D; /*!< Register D */ + __I uint16_t RESERVED; + + union { + __IO uint8_t CONTROL; /*!< RTC Control Register */ + + struct { + __IO uint8_t BLOCK_ENABLE: 1; /*!< 1= block to function internally */ + __IO uint8_t SOFT_RESET : 1; /*!< 1= RTC_RST reset (self-clearing no waiting) */ + uint8_t : 1; + __IO uint8_t ALARM_ENABLE: 1; /*!< 1=Enables Alarm, 0=Disables */ + } CONTROL_b; /*!< BitSize */ + }; + __I uint8_t RESERVED1[3]; + __IO uint8_t WEEK_ALARM; /*!< Set value in range 1-7 */ + __I uint8_t RESERVED2[3]; + + union { + __IO uint32_t DAYLIGHT_SAVINGS_FORWARD; /*!< Daylight Savings Forward Register */ + + struct { + __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */ + __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */ + uint32_t : 5; + __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */ + uint32_t : 5; + __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */ + __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */ + } DAYLIGHT_SAVINGS_FORWARD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DAYLIGHT_SAVINGS_BACKWARD; /*!< Daylight Savings Backward Register */ + + struct { + __IO uint32_t DST_MONTH : 8; /*!< This field matches the Month Register. */ + __IO uint32_t DST_DAY_OF_WEEK: 3; /*!< matches the Day of Week Register bits[2:0]. */ + uint32_t : 5; + __IO uint32_t DST_WEEK : 3; /*!< week number (1,,5) within current month. */ + uint32_t : 5; + __IO uint32_t DST_HOUR : 7; /*!< matching value for bits[6:0] of Hours register */ + __IO uint32_t DST_AM_PM : 1; /*!< This bit selects AM vs. PM. */ + } DAYLIGHT_SAVINGS_BACKWARD_b; /*!< BitSize */ + }; +} RTC_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief The CEC1302/24 GPIO Interface provides general purpose input monitoring and output control, + as well as managing many aspects of pin functionality; including, multi-function Pin Multiplexing Control, GPIO + Direction control, PU/PD (PU_PD) resistors, asynchronous wakeup and synchronous Interrupt Detection (int_det), + GPIO Direction, and Polarity control, as well as control of pin drive strength and slew rate. (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + + union { + __IO uint32_t PIN_CONTROL[160]; /*!< 1st Pin Control Register */ + + struct { + __IO uint32_t PU_PD : 2; /*!< 01= Pull Up, 10= Pull Down, 11/00= None */ + __IO uint32_t PWR : 2; /*!< 00= VCC1, 01= VCC2 Power Rail 1x = Reserved */ + __IO uint32_t INT_DET : 3; /*!< + [7654] -------------------------------------------- + 0 000 = Low Level Sensitive + 0 001 = High Level Sensitive + 0 100 = Interrupt events are disabled + 1 101 = Rising Edge Triggered + 1 110 = Falling Edge Triggered + 1 111 = Either edge triggered + --------------------------------------------------- */ + __IO uint32_t EDGE_EN : 1; /*!< 1= Edge detection enabled */ + __IO uint32_t BUFFER : 1; /*!< Output Buffer Type. 0 = Push-Pull, 1 = Open Drain */ + __IO uint32_t DIR : 1; /*!< GPIO Direction. 0 = Input, 1 = Output */ + __IO uint32_t OUTPUT_WRITE_EN: 1; /*!< 0= Alternative GPIO data write enabled */ + __IO uint32_t POLARITY : 1; /*!< 0 = Non-inverted, 1 = Inverted */ + __IO uint32_t MUX : 2; /*!< 00= GPIO Function, 01/10/11=Func 1/2/3 */ + uint32_t : 2; + __IO uint32_t OUTPUT : 1; /*!< 0: GPIO[x] out = '0', 1: GPIO[x] out = '1' */ + uint32_t : 7; + __I uint32_t INPUT : 1; /*!< reflects the state of GPIO input */ + } PIN_CONTROL_b[160]; /*!< BitSize */ + }; + __IO uint32_t OUTPUT[5]; /*!< Group 0: GPIO[x] out =0, 1: =1 */ + __I uint32_t RESERVED[27]; + __IO uint32_t INPUT[5]; /*!< Group GPIO Input Registers */ + __I uint32_t RESERVED1[123]; + + union { + __IO uint32_t CONTROL2_000_067[56]; /*!< PIN CONTROL REGISTER 2, from 000 - 067 */ + + struct { + __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */ + uint32_t : 3; + __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */ + } CONTROL2_000_067_b[56]; /*!< BitSize */ + }; + + union { + __IO uint32_t CONTROL2_100_167[56]; /*!< PIN CONTROL REGISTER 2, from 100 - 167 */ + + struct { + __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */ + uint32_t : 3; + __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */ + } CONTROL2_100_167_b[56]; /*!< BitSize */ + }; + __I uint32_t RESERVED2[24]; + + union { + __IO uint32_t CONTROL2_200_267[56]; /*!< PIN CONTROL REGISTER 2, from 200 - 267 */ + + struct { + __IO uint32_t SLEW_RATE : 1; /*!< slew rate 0= slow (half freq), 1= fast */ + uint32_t : 3; + __IO uint32_t DRIVE_STRENGTH: 2; /*!< drive strength 00=2, 01=4, 10=8, 11=12(mA) */ + } CONTROL2_200_267_b[56]; /*!< BitSize */ + }; +} GPIO_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + + +/** + * @brief The Internal DMA Controller transfers data to/from the source from/to the + destination. The firmware is responsible for setting up each channel. Afterwards either the + firmware or the hardware may perform the flow control. The hardware flow control exists entirely + inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device + supports a transfer of that size. Every device must be on the internal 32-bit address space. (DMA) + */ + +typedef struct { /*!< DMA Structure */ + + union { + __IO uint8_t CONTROL; /*!< Soft reset. Enable the blocks operation. */ + + struct { + __IO uint8_t ACTIVATE : 1; /*!< Enable the blocks operation. (R/WS) */ + __O uint8_t SOFT_RESET : 1; /*!< Soft reset entire module. self-clearing. */ + } CONTROL_b; /*!< BitSize */ + }; + __I uint8_t RESERVED[3]; + __I uint32_t DATA_PACKET; /*!< data from currently active transfer source */ + __I uint32_t RESERVED1[2]; + DMA_CH_Type CH[12]; /*!< registers to determine channel's operation. */ +} DMA_Type; + + +/* ================================================================================ */ +/* ================ SMB0 ================ */ +/* ================================================================================ */ + + +/** + * @brief The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface. (SMB0) + */ + +typedef struct { /*!< SMB0 Structure */ + + union { + union { + __I uint8_t STATUS; /*!< Status Register */ + + struct { + __I uint8_t nBB : 1; /*!< 0= Bus Busy */ + __I uint8_t LAB : 1; /*!< Lost Arbitration Bit */ + __I uint8_t AAS : 1; /*!< Addressed As Slave */ + __I uint8_t LRB_AD0 : 1; /*!< "Last Received Bit"/Address 0 (general call) */ + __I uint8_t BER : 1; /*!< Bus Error (BER) */ + __I uint8_t STS : 1; /*!< 1=ext generated STOP condition is detected. */ + __I uint8_t SAD : 1; /*!< SMBus Address Decoded (SAD) */ + __I uint8_t PIN : 1; /*!< Pending Interrupt bit */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __O uint8_t CONTROL; /*!< Control Register */ + + struct { + __IO uint8_t ACK : 1; /*!< 1= send an acknowledge automatically */ + __IO uint8_t STO : 1; /*!< See STA description */ + __IO uint8_t STA : 1; /*!< generation of repeated Start and Stop condition */ + __IO uint8_t ENI : 1; /*!< Enable Interrupt bit */ + uint8_t : 2; + __IO uint8_t ESO : 1; /*!< enables/disables SMB serial data output */ + __IO uint8_t PIN : 1; /*!< Pending Interrupt Not (PIN) software reset */ + } CONTROL_b; /*!< BitSize */ + }; + }; + __I uint8_t RESERVED[3]; + + union { + __IO uint16_t OWN; /*!< Own Address Reg. wt 55h= AAh addr */ + + struct { + __IO uint16_t ADDRESS_1 : 7; /*!< Own Address 1 addressed as a slave. */ + uint16_t : 1; + __IO uint16_t ADDRESS_2 : 7; /*!< Own Address 2 addressed as a slave. */ + } OWN_b; /*!< BitSize */ + }; + __I uint16_t RESERVED1; + __IO uint8_t DATA_REG; /*!< Data */ + __I uint8_t RESERVED2[3]; + + union { + __IO uint32_t MASTER_COMMAND; /*!< SMBus Master Command Register */ + + struct { + __IO uint32_t MRUN : 1; /*!< 1= transfer bytes over SMBus. */ + __IO uint32_t MPROCEED : 1; /*!< 1:WAIT-BUSBUSY and MRUN-RECEIVE */ + uint32_t : 6; + __IO uint32_t START0 : 1; /*!< 1: send a Start bit on the SMBus */ + __IO uint32_t STARTN : 1; /*!< 1: send a Start before the last byte */ + __IO uint32_t STOP : 1; /*!< 1: send a Stop bit after transaction completes */ + __IO uint32_t PEC_TERM : 1; /*!< 1: PEC is transmitted when WriteCount is 0. */ + __IO uint32_t READM : 1; /*!< 1: ReadCount field is replaced by byte */ + __IO uint32_t READ_PEC : 1; /*!< 1: reading when ReadCount is 0 for one more byte */ + uint32_t : 2; + __IO uint32_t WRITECOUNT : 8; /*!< number of Master Transmit Buffer bytes */ + __IO uint32_t READCOUNT : 8; /*!< number of Master Receive Buffer bytes */ + } MASTER_COMMAND_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SLAVE_COMMAND; /*!< SMBus Slave Command Register */ + + struct { + __IO uint32_t SRUN : 1; /*!< 1:enables the Slave State Machine to operate */ + __IO uint32_t SPROCEED : 1; /*!< Slave to START_WAIT/RECEIVE/TRANSMIT states */ + __IO uint32_t SLAVE_PEC : 1; /*!< 1:PEC is copied to the DATA register */ + uint32_t : 5; + __IO uint32_t SLAVE_WRITECOUNT: 8; /*!< number bytes software expects to send to Master */ + __IO uint32_t SLAVE_READCOUNT: 8; /*!< number copied from DATA to Slave Receive Buffer */ + } SLAVE_COMMAND_b; /*!< BitSize */ + }; + __IO uint8_t PEC; /*!< PEC byte */ + __I uint8_t RESERVED3[3]; + __IO uint8_t DATA_TIMING2; /*!< HOLD TIME (clock) START BIT */ + __I uint8_t RESERVED4[7]; + + union { + __IO uint32_t COMPLETION; /*!< Completion Register */ + + struct { + uint32_t : 2; + __IO uint32_t DTEN : 1; /*!< 1: Device Time-out checking is enabled. */ + __IO uint32_t MCEN : 1; /*!< 1: enable Master Cumulative Time-Out checking */ + __IO uint32_t SCEN : 1; /*!< 1:enable Slave Cumulative Time-Out checking */ + __IO uint32_t BIDEN : 1; /*!< 1:Bus Idle Detect Time-Out checking is enabled */ + __I uint32_t TIMERR : 1; /*!< 1:timeout error detect status are asserted. */ + uint32_t : 1; + __IO uint32_t DTO : 1; /*!< DTO is the Device Time-out bit. (R/WC) */ + __IO uint32_t MCTO : 1; /*!< Master Cumulative Time-out bit. (R/WC) */ + __IO uint32_t SCTO : 1; /*!< SCTO is the Slave Cumulative Time-out bit(R/WC) */ + __IO uint32_t CHDL : 1; /*!< CHDL is the clock high time-out detect bit(R/WC) */ + __IO uint32_t CHDH : 1; /*!< CHDH is the bus idle time-out detect bit(R/WC) */ + __IO uint32_t BER : 1; /*!< 1: BER in Status was set (R/WC) */ + __IO uint32_t LAB : 1; /*!< 1: LAB in Status was set (R/WC) */ + uint32_t : 1; + __IO uint32_t SNAKR : 1; /*!< 1: Slave sent NACK to transmitting Master */ + __I uint32_t STR : 1; /*!< 0: finished receive, 1:finished transmit phase */ + uint32_t : 1; + __IO uint32_t SPROT : 1; /*!< 1: WriteCount in Slave counted down to 0(R/WC) */ + __IO uint32_t REPEAT_READ: 1; /*!< 1: Slave stopped because a Repeat Start for Rd */ + __IO uint32_t REPEAT_WRITE: 1; /*!< 1: Slave stopped because a Repeat Start for Wt */ + uint32_t : 2; + __IO uint32_t MNAKX : 1; /*!< 1: Master received a NACK while transmitting */ + __I uint32_t MTR : 1; /*!< Master finished 0: receive 1: transmit */ + uint32_t : 3; + __IO uint32_t IDLE : 1; /*!< 1: I2C bus becomes idle (R/WC) */ + __IO uint32_t MDONE : 1; /*!< 1: Master completed operation (R/WC) */ + __IO uint32_t SDONE : 1; /*!< 1: Slave completed operation (R/WC) */ + } COMPLETION_b; /*!< BitSize */ + }; + + union { + __IO uint32_t IDLE_SCALING; /*!< Idle Scaling Register */ + + struct { + __IO uint32_t FAIR_BUS_IDLE_MIN: 12; /*!< number ticks to satisfy the fairness protocol */ + uint32_t : 4; + __IO uint32_t FAIR_IDLE_DELAY: 12; /*!< number ticks to program the delay */ + } IDLE_SCALING_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CONFIGURATION; /*!< Configuration Register */ + + struct { + __IO uint32_t PORT_SEL : 4; /*!< determine one of 16 bus ports apply to SDAT/SCLK */ + __IO uint32_t TCEN : 1; /*!< 1: Bus Time-Outs are enabled */ + __I uint32_t SLOW_CLOCK : 1; /*!< 1: Bus Clock multiplied by 4, thus frequency/4 */ + uint32_t : 1; + __IO uint32_t PECEN : 1; /*!< 1: Hardware PEC Support is enabled */ + __IO uint32_t DFEN : 1; /*!< 1: Digital Filter is enabled. 0: bypassed. */ + __IO uint32_t RESET : 1; /*!< 1: initialized to power-on default state. */ + __IO uint32_t ENAB : 1; /*!< 1: normal operation, 0: lowest power */ + __IO uint32_t DSA : 1; /*!< 0: Slave Address I2C Compatibility, 1: SMBus */ + __IO uint32_t FAIR : 1; /*!< 1: MCTP Fairness protocol is in effect. */ + uint32_t : 1; + __I uint32_t GC_DIS : 1; /*!< General Call address 0: enabled, 1: disabled */ + uint32_t : 1; + __O uint32_t FLUSH_SXBUF: 1; /*!< 1: Slave Transmit Buffer to be marked empty. */ + __O uint32_t FLUSH_SRBUF: 1; /*!< 1: Slave Receive Buffer to be marked empty. */ + __O uint32_t FLUSH_MXBUF: 1; /*!< 1: Master Transmit Buffer to be marked empty. */ + __O uint32_t FLUSH_MRBUF: 1; /*!< 1: Master Receive Buffer to be marked empty. */ + uint32_t : 8; + __I uint32_t EN_AAS : 1; /*!< 0: Disable AAS Interrupt, 1: Enable */ + __IO uint32_t ENIDI : 1; /*!< 1: Idle interrupt is enabled. 0: disabled. */ + __IO uint32_t ENMI : 1; /*!< 1: Master Done interrupt is enabled. 0: disabled */ + __IO uint32_t ENSI : 1; /*!< 1: Slave Done interrupt is enabled. 0: disabled */ + } CONFIGURATION_b; /*!< BitSize */ + }; + + union { + __IO uint16_t BUS_CLOCK; /*!< Bus Clock Register */ + + struct { + __IO uint16_t LOW_PERIOD : 8; /*!< number of I2C Baud Clock to make up low phase */ + __IO uint16_t HIGH_PERIOD: 8; /*!< number of I2C Baud Clock to make up high phase */ + } BUS_CLOCK_b; /*!< BitSize */ + }; + __I uint16_t RESERVED5; + __I uint8_t BLOCK_ID; /*!< Block ID Register */ + __I uint8_t RESERVED6[3]; + __I uint8_t REVISION; /*!< Revision Register */ + __I uint8_t RESERVED7[3]; + + union { + __IO uint8_t BIT_BANG_CONTROL; /*!< Bit-Bang Control Register */ + + struct { + __IO uint8_t BBEN : 1; /*!< 1: Bit-Bang Mode Enable. */ + __IO uint8_t CLDIR : 1; /*!< Bit-Bang Clock Direction. 0 - Input, 1 - Output */ + __IO uint8_t DADIR : 1; /*!< Bit-Bang Data Direction. 0 - Input. 1 - Output */ + __IO uint8_t BBCLK : 1; /*!< controls state of SCLK when BBEN = CLDIR = 1 */ + __IO uint8_t BBDAT : 1; /*!< controls state of SDAT when BBEN = DADIR = 1 */ + __I uint8_t BBCLKI : 1; /*!< Bit-Bang Clock In. returns the state of SCLK. */ + __I uint8_t BBDATI : 1; /*!< Bit-Bang Data In. returns the state of SDAT */ + } BIT_BANG_CONTROL_b; /*!< BitSize */ + }; + __I uint8_t RESERVED8[7]; + + union { + __IO uint32_t DATA_TIMING; /*!< Data Timing Register */ + + struct { + __IO uint32_t DATA_HOLD : 8; /*!< SDAT hold time following SCLK driven low. */ + __IO uint32_t RESTART_SETUP: 8; /*!< SDAT setup time for a repeated START condition. */ + __IO uint32_t STOP_SETUP : 8; /*!< SDAT setup time for a STOP condition. */ + __IO uint32_t START_HOLD : 8; /*!< SCLK hold time during a START condition. */ + } DATA_TIMING_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TIME_OUT_SCALING; /*!< Time-Out Scaling Register */ + + struct { + __IO uint32_t CLOCK_HIGH : 8; /*!< = Clock High Time-Out x Baud_Clock_Period x 2 */ + __IO uint32_t SLAVE_CUM : 8; /*!< = Slave Cum Time-Out x Baud_Clock_Period x 1024 */ + __IO uint32_t MASTER_CUM : 8; /*!< = Master Cum Time-Out x Baud_Clock_Periodx 512 */ + __IO uint32_t BUS_IDLE_MIN: 8; /*!< = Bus Idle Min [7:0] x Baud_Clock_Period */ + } TIME_OUT_SCALING_b; /*!< BitSize */ + }; + __IO uint8_t SLAVE_TRANSMIT_BUFFER; /*!< SMBus Slave Transmit Buffer Register */ + __I uint8_t RESERVED9[3]; + __IO uint8_t SLAVE_RECEIVE_BUFFER; /*!< SMBus Slave Receive Buffer Register */ + __I uint8_t RESERVED10[3]; + __IO uint8_t MASTER_TRANSMIT_BUFER; /*!< SMBus Master Transmit Bufer Register */ + __I uint8_t RESERVED11[3]; + __IO uint8_t MASTER_RECEIVE_BUFFER; /*!< SMBus Master Receive Buffer Register */ +} SMB0_Type; + + +/* ================================================================================ */ +/* ================ PECI ================ */ +/* ================================================================================ */ + + +/** + * @brief The CEC1302 includes a PECI Interface to allow the EC to retrieve temperature readings from PECI-compliant devices. (PECI) + */ + +typedef struct { /*!< PECI Structure */ + __IO uint8_t WRITE_DATA; /*!< Tprovides access to a 32-byte Transmit FIFO. */ + __I uint8_t RESERVED[3]; + __IO uint8_t READ_DATA; /*!< provides access to a 32-byte Receive FIFO. */ + __I uint8_t RESERVED1[3]; + + union { + __IO uint8_t CONTROL; /*!< Control Register */ + + struct { + __IO uint8_t PD : 1; /*!< Power Down controls Power Management Interface */ + uint8_t : 2; + __IO uint8_t RST : 1; /*!< RST indicates that the PECI Core should be reset. */ + uint8_t : 1; + __IO uint8_t FRST : 1; /*!< FRST is the FIFO Reset bit. */ + __IO uint8_t TXEN : 1; /*!< TXEN is the Transmit Enable bit. */ + __IO uint8_t MIEN : 1; /*!< MIEN is the Master Interrupt Enable */ + } CONTROL_b; /*!< BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __IO uint8_t STATUS1; /*!< Status Register 1 */ + + struct { + __IO uint8_t BOF : 1; /*!< PECI begins Address Timing Negotiation(R/WC) */ + __IO uint8_t nEOF : 1; /*!< End of Frame asserted following Message Stop(R/WC) */ + __I uint8_t ERR : 1; /*!< error for current transaction has been detected */ + __I uint8_t RDY : 1; /*!< state of the READY signal function */ + __IO uint8_t RDYLO : 1; /*!< 1: falling edge of the READY signal function(R/WC) */ + __IO uint8_t RDYHI : 1; /*!< 1: rising edge of the READY signal function (R/WC) */ + uint8_t : 1; + __I uint8_t MINT : 1; /*!< asserted when any interrupt status is asserted. */ + } STATUS1_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __I uint8_t STATUS2; /*!< Status Register 2 */ + + struct { + __I uint8_t WFF : 1; /*!< Write Data Register FIFO is full. No interrupt. */ + __I uint8_t WFE : 1; /*!< Write Data Register FIFO is empty. */ + __I uint8_t RFF : 1; /*!< RFF indicates Read Data Register FIFO is full. */ + __I uint8_t RFE : 1; /*!< Read Data Register FIFO is empty. No interrupt. */ + uint8_t : 3; + __I uint8_t IDLE : 1; /*!< SST/PECI bus is idle, a new transaction may begin */ + } STATUS2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED4[3]; + + union { + __IO uint8_t ERROR; /*!< Error Register */ + + struct { + __IO uint8_t FERR : 1; /*!< FERR (Frame Check Sequence Error). (R/WC) */ + __IO uint8_t BERR : 1; /*!< reads value different from it has driven (R/WC) */ + uint8_t : 1; + __IO uint8_t REQERR : 1; /*!< READY is not asserted when counts down to zero */ + __IO uint8_t WROV : 1; /*!< WROV (Write Overrun). (R/WC) */ + __IO uint8_t WRUN : 1; /*!< WRUN (Write Underrun). (R/WC) */ + __IO uint8_t RDOV : 1; /*!< indicates read buffer has overflowed (R/WC) */ + __IO uint8_t CLKERR : 1; /*!< READY de-asserted in middle of a transaction(R/WC) */ + } ERROR_b; /*!< BitSize */ + }; + __I uint8_t RESERVED5[3]; + + union { + __IO uint8_t INT_EN1; /*!< Interrupt Enable 1 Register */ + + struct { + __IO uint8_t BIEN : 1; /*!< '1' the BOF interrupt is enabled. */ + __IO uint8_t EIEN : 1; /*!< '1' the EOF interrupt is enabled. */ + __IO uint8_t EREN : 1; /*!< '1' the ERR interrupt is enabled. */ + uint8_t : 1; + __IO uint8_t RLEN : 1; /*!< '1' the RDYLO interrupt is enabled. */ + __IO uint8_t RHEN : 1; /*!< '1' the RDYHI interrupt is enabled. */ + } INT_EN1_b; /*!< BitSize */ + }; + __I uint8_t RESERVED6[3]; + + union { + __IO uint8_t INT_EN2; /*!< Interrupt Enable 2 Register */ + + struct { + uint8_t : 1; + __IO uint8_t ENWFE : 1; /*!< '1' the WFE interrupt is enabled. */ + __IO uint8_t ENRFF : 1; /*!< '1' the RFF interrupt is enabled. */ + } INT_EN2_b; /*!< BitSize */ + }; + __I uint8_t RESERVED7[3]; + __IO uint8_t OBT1; /*!< Optimal Bit Time Register (Low Byte) */ + __I uint8_t RESERVED8[3]; + __IO uint8_t OBT2; /*!< Optimal Bit Time Register (High Byte) */ + __I uint8_t RESERVED9[27]; + __IO uint32_t ID; /*!< Block ID Register */ + __IO uint32_t REV; /*!< Revision Register */ +} PECI_Type; + + +/* ================================================================================ */ +/* ================ TACH_0 ================ */ +/* ================================================================================ */ + + +/** + * @brief This block monitors TACH output signals (or locked rotor signals) from + various types of fans, and determines their speed. (TACH_0) + */ + +typedef struct { /*!< TACH_0 Structure */ + + union { + __IO uint32_t CONTROL; /*!< TACHx Control Register */ + + struct { + __IO uint32_t OUT_LIMIT_ENABLE: 1; /*!< 1=Enable interrupt output from Tach block */ + __IO uint32_t TACH_EN : 1; /*!< 1= TACH Monitoring/ clock enabled, 0= TACH Idle */ + uint32_t : 6; + __IO uint32_t FILTER_EN : 1; /*!< remove high frequency glitches. 1=Filter enabled */ + uint32_t : 1; + __IO uint32_t MODE_SELECT: 1; /*!< 1=Counter is incremented on rising edge */ + __IO uint32_t EDGES : 2; /*!< 00/01/10/11: 2/3/5/9 Tach edges */ + uint32_t : 1; + __IO uint32_t READY_INT_EN: 1; /*!< 1=Enable Count Ready interrupt, 0=Disable */ + __IO uint32_t INPUT_INT_EN: 1; /*!< 1=Enable Tach Input toggle interrupt, 0=Disable */ + __I uint32_t COUNTER : 16; /*!< latched value of the internal Tach pulse counter */ + } CONTROL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t STATUS; /*!< TACHx Status Register */ + + struct { + __IO uint32_t OUT_LIMIT : 1; /*!< 1=Tach is outside of limits (R/WC) */ + __I uint32_t PIN : 1; /*!< 1= Tach Input is high, 0= Input is low */ + __IO uint32_t TOGGLE : 1; /*!< 1=Tach Input changed state, 0= stable (R/WC) */ + __IO uint32_t COUNT_READY: 1; /*!< 1=Reading ready, 0=Reading not ready */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint16_t HIGH_LIMIT; /*!< value is compared with TACHX_COUNTER field. */ + __I uint16_t RESERVED; + __IO uint16_t LOW_LIMIT; /*!< value is compared with TACHX_COUNTER field. */ +} TACH_0_Type; + + +/* ================================================================================ */ +/* ================ PWM_0 ================ */ +/* ================================================================================ */ + + +/** + * @brief This block generates a PWM output that can be used to control 4-wire fans, blinking LEDs, and + other similar devices. Each PWM can generate an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz. + The PWM controller can also used to generate the PROCHOT output and Speaker output. (PWM_0) + */ + +typedef struct { /*!< PWM_0 Structure */ + __IO uint32_t COUNTER_ON_TIME; /*!< determine both frequency and duty cycle */ + __IO uint32_t COUNTER_OFF_TIME; /*!< determine both frequency and duty cycle */ + + union { + __IO uint32_t CONFIG; /*!< PWMx CONFIGURATION REGISTER */ + + struct { + __IO uint32_t EN : 1; /*!< 1=Enabled (default), 0=Disabled */ + __IO uint32_t CLK_SELECT : 1; /*!< determines clock source, 1=CLOCK_LOW, 0=HIGH */ + __IO uint32_t INVERT : 1; /*!< 1= PWM_OUTPUT ON State is active low, 0=high */ + __IO uint32_t CLK_PRE_DIVIDER: 4; /*!< Clock source is divided by Pre-Divider+1 */ + } CONFIG_b; /*!< BitSize */ + }; +} PWM_0_Type; + + +/* ================================================================================ */ +/* ================ RPM_FAN ================ */ +/* ================================================================================ */ + + +/** + * @brief The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors + the fan's speed and automatically adjusts the drive to maintain the desired fan speed. This + RPM based Fan Control Algorithm controls a PWM output based on a tachometer input. (RPM_FAN) + */ + +typedef struct { /*!< RPM_FAN Structure */ + __IO uint8_t SETTING; /*!< Drive = (FAN_SETTING VALUE/255) x 100%. */ + __IO uint8_t PWM_DIVIDE; /*!< PWM_Frequency = base_clk / PWM_DIVIDE */ + + union { + __IO uint16_t CONFIGURATION; /*!< general operation of Fan Control Algorithm */ + + struct { + __IO uint16_t UPDATE : 3; /*!< Determines base time between fan driver updates */ + __IO uint16_t EDGES : 2; /*!< minimum number of edges that must be detected */ + __IO uint16_t RANGE : 2; /*!< Adjusts the range of tachometer reading values. */ + __IO uint16_t EN_ALGO : 1; /*!< Enables the RPM based Fan Control Algorithm. */ + __IO uint16_t POLARITY : 1; /*!< 1: The Polarity of the PWM driver is inverted. */ + __IO uint16_t ERR_RNG : 2; /*!< Control advanced options that affect error window. */ + __IO uint16_t DER_OPT : 2; /*!< Control portion of RPM fan control algorithm */ + __IO uint16_t DIS_GLITCH : 1; /*!< 1: The glitch filter is disabled. */ + __IO uint16_t EN_RRC : 1; /*!< Enables the ramp rate control circuitry */ + } CONFIGURATION_b; /*!< BitSize */ + }; + __I uint8_t RESERVED; + + union { + __IO uint8_t GAIN; /*!< gain for proportional/integral portion */ + + struct { + __IO uint8_t GAINP : 2; /*!< derivative gain term */ + __IO uint8_t GAINI : 2; /*!< derivative gain term */ + __IO uint8_t GAIND : 2; /*!< derivative gain term */ + } GAIN_b; /*!< BitSize */ + }; + + union { + __IO uint8_t SPIN_UP_CONFIGURATION; /*!< settings of Spin Up Routine. */ + + struct { + __IO uint8_t SPINUP_TIME: 2; /*!< maximum Spin Time that Spin Up Routine run */ + __IO uint8_t SPIN_LVL : 3; /*!< final drive level used by the Spin Up Routine */ + __IO uint8_t NOKICK : 1; /*!< 1: Spin Routine will not drive fan to 100% */ + __IO uint8_t DRIVE_FAIL_CNT: 2; /*!< update cycles are used for Drive Fail detection */ + } SPIN_UP_CONFIGURATION_b; /*!< BitSize */ + }; + __IO uint8_t STEP; /*!< max step driver take between update */ + __IO uint8_t MINIMUM_DRIVE; /*!< minimum drive setting for Fan Algorithm. */ + __IO uint8_t VALID_TACH_COUNT; /*!< max value to indicate fan spin properly */ + __IO uint16_t DRIVE_FAIL_BAND; /*!< [15:3]counts for Drive Fail circuitry */ + __IO uint16_t TACH_TARGET; /*!< [12:0] The target tachometer value. */ + __IO uint8_t TACH_READING; /*!< [15:3]current tachometer reading value. */ + __I uint8_t RESERVED1; + __IO uint8_t DRIVER_BASE_FREQUENCY; /*!< [1:0]frequency range of the PWM fan driver */ + + union { + __IO uint8_t STATUS; /*!< The bits are routed to interrupts */ + + struct { + __IO uint8_t FAN_STALL : 1; /*!< 1 - Stalled fan detected. (R/WC) */ + __IO uint8_t FAN_SPIN : 1; /*!< 1: Spin up Routine not detect a valid tachometer */ + uint8_t : 3; + __IO uint8_t DRIVE_FAIL : 1; /*!< 1- cannot drive to target setting (R/WC) */ + } STATUS_b; /*!< BitSize */ + }; +} RPM_FAN_Type; + + +/* ================================================================================ */ +/* ================ SPI_0 ================ */ +/* ================================================================================ */ + + +/** + * @brief The General Purpose Serial Peripheral Interface (GP-SPI) may be used + to communicate with various peripheral devices, e.g., EEPROMS, DACs, ADCs, that use a + standard Serial Peripheral Interface. (SPI_0) + */ + +typedef struct { /*!< SPI_0 Structure */ + __IO uint32_t ENABLE; /*!< [0:0] 1=Enabled. device is fully operational */ + + union { + __IO uint32_t CONTROL; /*!< SPI Control */ + + struct { + __IO uint32_t LSBF : 1; /*!< Least Significant Bit First */ + __IO uint32_t BIOEN : 1; /*!< Bidirectional Output Enable control. */ + __IO uint32_t SPDIN_SELECT: 2; /*!< [3:2]1xb=SPDIN1,SPDIN2. Select Dual Mode */ + __IO uint32_t SOFT_RESET : 1; /*!< Wt 1 to Soft Reset. self-clearing */ + __IO uint32_t AUTO_READ : 1; /*!< Auto Read Enable. */ + __IO uint32_t CE : 1; /*!< SPI Chip Select Enable. */ + } CONTROL_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< SPI Status */ + + struct { + __I uint32_t TXBE : 1; /*!< 1=TX_Data buffer is empty */ + __I uint32_t RXBF : 1; /*!< 1=RX_Data buffer is full */ + __I uint32_t ACTIVE : 1; /*!< ACTIVE status */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint32_t TX_DATA; /*!< [7:0]wt to initiate a SPI transaction. */ + __IO uint32_t RX_DATA; /*!< [7:0]read value returned by ext SPI device */ + + union { + __IO uint32_t CLOCK_Control; /*!< SPI Clock Control. */ + + struct { + __IO uint32_t TCLKPH : 1; /*!< Valid data is clocked out on 1st SPI_CLK */ + __IO uint32_t RCLKPH : 1; /*!< Valid data is expected after 1st SPI_CLK edge */ + __IO uint32_t CLKPOL : 1; /*!< SPI_CLK is high when 1st clock edge falling */ + uint32_t : 1; + __IO uint32_t CLKSRC : 1; /*!< 1=2MHz, 0=48 MHz Ring Oscillator */ + } CLOCK_Control_b; /*!< BitSize */ + }; + __IO uint32_t CLOCK_GENERATOR; /*!< [5:0] PRELOAD SPI Clock Generator Preload value. */ +} SPI_0_Type; + + +/* ================================================================================ */ +/* ================ LED_0 ================ */ +/* ================================================================================ */ + + +/** + * @brief The blinking/breathing hardware is implemented using a PWM. The PWM can be + driven either by the 48 MHz clock or by a 32.768 KHz clock input. When driven by the 48 MHz clock, + the PWM can be used as a standard 8-bit PWM in order to control a fan. When used to drive blinking + or breathing LEDs, the 32.768 KHz clock source is used. (LED_0) + */ + +typedef struct { /*!< LED_0 Structure */ + + union { + __IO uint32_t CONFIG; /*!< LED Configuration */ + + struct { + __IO uint32_t CONTROL : 2; /*!< 3=on,2=blinking,1=breathing,0=off */ + __IO uint32_t CLOCK_SOURCE: 1; /*!< 1=48MHz, 0=32.768 KHz clock */ + __IO uint32_t SYNCHRONIZE: 1; /*!< 1: all LEDs are reset to initial values. */ + __IO uint32_t PWM_SIZE : 2; /*!< 3:reserved, 2:6bit, 1:7bit,0:8bit PWM */ + __IO uint32_t ENABLE_UPDATE: 1; /*!< ENABLE_UPDATE */ + __O uint32_t RESET : 1; /*!< 1 resets PWM to default values self clearing */ + __IO uint32_t WDT_RELOAD : 8; /*!< PWM Watchdog Timer counter reload value */ + __IO uint32_t SYMMETRY : 1; /*!< 1=rising/falling ramp are in Asymmetric mode */ + } CONFIG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t LIMITS; /*!< LED Limits */ + + struct { + __IO uint32_t MINIMUM : 8; /*!< wait in breathing if current cycle less this value */ + __IO uint32_t MAXIMUM : 8; /*!< wait, breathing if current cycle great this value */ + } LIMITS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DELAY; /*!< LED Delay */ + + struct { + __IO uint32_t LOWPULSE : 12; /*!< number to wait before updating current cycle */ + __IO uint32_t HIGHPULSE : 12; /*!< number to wait before updating current cycle */ + } DELAY_b; /*!< BitSize */ + }; + + union { + __IO uint32_t UPDATE_STEPSIZE; /*!< provide amount duty cycle to adjust */ + + struct { + __IO uint32_t STEP0 : 4; /*!< when the segment index is equal to 000. */ + __IO uint32_t STEP1 : 4; /*!< when the segment index is equal to 001. */ + __IO uint32_t STEP2 : 4; /*!< when the segment index is equal to 010. */ + __IO uint32_t STEP3 : 4; /*!< when the segment index is equal to 011. */ + __IO uint32_t STEP4 : 4; /*!< when the segment index is equal to 100. */ + __IO uint32_t STEP5 : 4; /*!< when the segment index is equal to 101 */ + __IO uint32_t STEP6 : 4; /*!< when the segment index is equal to 110. */ + __IO uint32_t STEP7 : 4; /*!< when the segment index is equal to 111. */ + } UPDATE_STEPSIZE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t UPDATE_INTERVAL; /*!< LED Update Interval */ + + struct { + __IO uint32_t INTERVAL0 : 4; /*!< when the segment index is equal to 000b. */ + __IO uint32_t INTERVAL1 : 4; /*!< when the segment index is equal to 001b. */ + __IO uint32_t INTERVAL2 : 4; /*!< when the segment index is equal to 010b. */ + __IO uint32_t INTERVAL3 : 4; /*!< when the segment index is equal to 011b. */ + __IO uint32_t INTERVAL4 : 4; /*!< when the segment index is equal to 100b. */ + __IO uint32_t INTERVAL5 : 4; /*!< when the segment index is equal to 101b. */ + __IO uint32_t INTERVAL6 : 4; /*!< when the segment index is equal to 110b. */ + __IO uint32_t INTERVAL7 : 4; /*!< when the segment index is equal to 111b. */ + } UPDATE_INTERVAL_b; /*!< BitSize */ + }; +} LED_0_Type; + + +/* ================================================================================ */ +/* ================ PS2_0 ================ */ +/* ================================================================================ */ + + +/** + * @brief There are four PS/2 Ports in the MEC1320 which are directly controlled + by the EC. The hardware implementation eliminates the need to bit bang I/O ports to generate + PS/2 traffic, however bit banging is available via the associated GPIO pins. (PS2_0) + */ + +typedef struct { /*!< PS2_0 Structure */ + + union { + __I uint32_t RX_DATA; /*!< Data received from a peripheral */ + __O uint32_t TX_DATA; /*!< Writes to start a transmission */ + }; + + union { + __IO uint32_t CONTROL; /*!< PS2 Control Register */ + + struct { + __IO uint32_t TR : 1; /*!< PS/2 1:Transmit, 0:Receive data */ + __IO uint32_t EN : 1; /*!< 1: PS/2 Enable */ + __IO uint32_t PARITY : 2; /*!< 00b=Receiver expects Odd Parity (default). */ + __IO uint32_t STOP : 2; /*!< 00b=Receiver expects an active high stop bit */ + } CONTROL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t STATUS; /*!< PS2 Status Register */ + + struct { + __I uint32_t RDATA_RDY : 1; /*!< Data Ready. Reading Receive data to clears */ + __IO uint32_t REC_TIMEOUT: 1; /*!< REC_TIMEOUT is cleared when Status is read */ + __IO uint32_t PE : 1; /*!< Parity Error */ + __IO uint32_t FE : 1; /*!< Framing Error */ + __I uint32_t XMIT_IDLE : 1; /*!< 0=actively transmitting PS/2 data. 1=Idle */ + __IO uint32_t XMIT_TIME_OUT: 1; /*!< Transmitter Time-out */ + __I uint32_t RX_BUSY : 1; /*!< 0=actively receiving PS/2 data, 1=Idle */ + __IO uint32_t XMIT_START_TIMEOUT: 1; /*!< Transmit Start Timeout (over 25 ms) */ + } STATUS_b; /*!< BitSize */ + }; +} PS2_0_Type; + + +/* ================================================================================ */ +/* ================ KEYSCAN ================ */ +/* ================================================================================ */ + + +/** + * @brief The Keyboard Scan Interface block provides a register interface to the EC + to directly scan an external keyboard matrix of size up to 18x8. (KEYSCAN) + */ + +typedef struct { /*!< KEYSCAN Structure */ + __I uint32_t RESERVED; + + union { + __IO uint32_t CONTROL; /*!< KSO Select and control */ + + struct { + __IO uint32_t SELECT : 5; /*!< selects a KSO line (00000b=KSO[0] etc.) */ + __IO uint32_t ALL : 1; /*!< 0=KSO_SELECT set KSO, 1=KSO[x] driven high */ + __IO uint32_t KSEN : 1; /*!< 0=Keyboard scan enabled, 1=disabled. */ + __IO uint32_t INVERT : 1; /*!< 0=KSO[x] driven low, 1=high when selected. */ + } CONTROL_b; /*!< BitSize */ + }; + __I uint32_t KSI; /*!< [7:0]returns the current state of KSI pins */ + __IO uint32_t STATUS; /*!< [7:0]set on falling edge of KSI */ + __IO uint32_t INT_EN; /*!< [7:0]enables int due to H2L on a KSI */ + __IO uint32_t EXTENDED_CONTROL; /*!< [0:0] 1=Enable predrive on KSO pins. */ +} KEYSCAN_Type; + + +/* ================================================================================ */ +/* ================ BC_LINK ================ */ +/* ================================================================================ */ + + +/** + * @brief This block provides BC-Link connectivity to a slave device. The BC-Link protocol + includes a start bit to signal the beginning of a message and a turnaround (TAR) period + for bus transfer between the Master and Companion devices. (BC_LINK) + */ + +typedef struct { /*!< BC_LINK Structure */ + + union { + __IO uint32_t STATUS; /*!< BC-Link Status */ + + struct { + __I uint32_t BUSY : 1; /*!< 1: BC is transferring data and on reset */ + uint32_t : 3; + __IO uint32_t BUSY_CLR_INT_EN: 1; /*!< enable for generating an interrupt */ + __IO uint32_t ERR_INT_EN : 1; /*!< enable interrupt when BC_ERR bit set */ + __IO uint32_t ERROR : 1; /*!< indicates a BC Bus Error has occurred. (R/WC) */ + __IO uint32_t RESET : 1; /*!< 1: Reset BC_Link Master Interface */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint32_t ADDRESS; /*!< Address in Companion for BC-Link */ + __IO uint32_t DATA_REG; /*!< hold data used in a BC-Link transaction. */ + __IO uint32_t CLOCK_SELECT; /*!< [7:0] DIVIDER 48MHz/ (Divider +1). */ +} BC_LINK_Type; + + +/* ================================================================================ */ +/* ================ TFDP ================ */ +/* ================================================================================ */ + + +/** + * @brief The TFDP serially transmits Embedded Controller (EC)-originated + diagnostic vectors to an external debug trace system. (TFDP) + */ + +typedef struct { /*!< TFDP Structure */ + __IO uint8_t DATA_REG; /*!< Debug data to be shifted out on TFDP port */ + __I uint8_t RESERVED[3]; + + union { + __IO uint8_t CONTROL; /*!< Debug Control Register */ + + struct { + __IO uint8_t EN : 1; /*!< 1=Clock enabled, 0=Clock is disabled (Default) */ + __IO uint8_t EDGE_SEL : 1; /*!< 1= shifted out on falling edge, 0= rising */ + __IO uint8_t DIVSEL : 2; /*!< Clock Divider Select. */ + __IO uint8_t IP_DELAY : 3; /*!< Inter-packet Delay. */ + } CONTROL_b; /*!< BitSize */ + }; +} TFDP_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + + +/** + * @brief This block is designed to convert external analog voltage readings into digital values. (ADC) + */ + +typedef struct { /*!< ADC Structure */ + + union { + __IO uint32_t CONTROL; /*!< control behavior of ADC */ + + struct { + __IO uint32_t ACTIVATE : 1; /*!< 1: ADC is enabled for operation. */ + __IO uint32_t START_SINGLE: 1; /*!< 1: ADC Single Mode is enabled. self-clearing */ + __IO uint32_t START_REPEAT: 1; /*!< 1: ADC Repeat Mode is enabled. */ + __IO uint32_t POWER_SAVER_DIS: 1; /*!< 0: Power saving enabled. 1: disabled. */ + __IO uint32_t SOFT_RESET : 1; /*!< 1: reset of ADC */ + uint32_t : 1; + __IO uint32_t REPEAT_DONE_STAT: 1; /*!< 1: ADC repeat conversion is completed.(R/WC) */ + __IO uint32_t SINGLE_DONE_STAT: 1; /*!< 1: ADC single conversion is completed.(R/WC) */ + } CONTROL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DELAY; /*!< delay fm set Start_Repeat and conversion */ + + struct { + __IO uint32_t START : 16; /*!< start delay before conv. when Start_Repeat=1 */ + __IO uint32_t REPEAT : 16; /*!< interval between conversion when Start_Repeat=1 */ + } DELAY_b; /*!< BitSize */ + }; + + union { + __IO uint32_t STATUS; /*!< 1: conversion is complete (R/WC) */ + + struct { + __IO uint32_t CH0 : 1; /*!< ADC_Ch0_Status */ + __IO uint32_t CH1 : 1; /*!< ADC_Ch1_Status */ + __IO uint32_t CH2 : 1; /*!< ADC_Ch2_Status */ + __IO uint32_t CH3 : 1; /*!< ADC_Ch3_Status */ + __IO uint32_t CH4 : 1; /*!< ADC_Ch4_Status */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SINGLE_EN; /*!< ADC Single-Sample conversion control */ + + struct { + __IO uint32_t CH0 : 1; /*!< Ch0 single conversions, 1:enabled/0:disabled */ + __IO uint32_t CH1 : 1; /*!< Ch1 single conversions, 1:enabled/0:disabled */ + __IO uint32_t CH2 : 1; /*!< Ch2 single conversions, 1:enabled/0:disabled */ + __IO uint32_t CH3 : 1; /*!< Ch3 single conversions, 1:enabled/0:disabled */ + __IO uint32_t CH4 : 1; /*!< Ch4 single conversions, 1:enabled/0:disabled */ + } SINGLE_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t REPEAT; /*!< ADC channels repeat conversion control */ + + struct { + __IO uint32_t CH0 : 1; /*!< Ch0 repeat conversions, 1:enabled/0:disabled */ + __IO uint32_t CH1 : 1; /*!< Ch1 repeat conversions, 1:enabled/0:disabled */ + __IO uint32_t CH2 : 1; /*!< Ch2 repeat conversions, 1:enabled/0:disabled */ + __IO uint32_t CH3 : 1; /*!< Ch3 repeat conversions, 1:enabled/0:disabled */ + __IO uint32_t CH4 : 1; /*!< Ch4 repeat conversions, 1:enabled/0:disabled */ + } REPEAT_b; /*!< BitSize */ + }; + __IO uint32_t READING[5]; /*!< ADC channels 32-bit reading register. */ +} ADC_Type; + + +/* ================================================================================ */ +/* ================ EC_REG_BANK ================ */ +/* ================================================================================ */ + + +/** + * @brief This block is designed to be accessed internally by the EC via the register interface. (EC_REG_BANK) + */ + +typedef struct { /*!< EC_REG_BANK Structure */ + __I uint32_t RESERVED[5]; + __IO uint8_t AHB_ERROR_CONTROL; /*!< 1: EC memory exceptions are disabled. */ + __I uint8_t RESERVED1[3]; + __IO uint32_t INTERRUPT_CONTROL; /*!< 1= Alternate NVIC vectors enabled */ + __IO uint32_t ETM_TRACE_ENABLE; /*!< 1= ARM TRACE port enabled */ + __IO uint32_t JTAG_Enable; /*!< 1= JTAG port enabled. */ + __I uint32_t RESERVED2; + __IO uint32_t WDT_EVENT_COUNT; /*!< [3:0]EC Rd/Wt are cleared to 0 on VCC1 POR */ + __I uint32_t RESERVED3[3]; + __IO uint32_t ADC_VREF_PD; /*!< [0:0] ADC VREF Power down. 0=on 1=off */ +} EC_REG_BANK_Type; + + +/* ================================================================================ */ +/* ================ JTAG ================ */ +/* ================================================================================ */ + + +/** + * @brief The Controller, which is an IEEE compliant JTAG Port, has implemented all + the mandatory JTAG instructions. This interface may be used to access the embedded controller's + test access port (TAP). (JTAG) + */ + +typedef struct { /*!< JTAG Structure */ + __IO uint32_t MESSAGE_OBF; /*!< JTAG Message OBF */ + __IO uint32_t MESSAGE_IBF; /*!< JTAG Message IBF */ + __IO uint8_t OBF_STATUS; /*!< JTAG OBF Status */ + __IO uint8_t IBF_STATUS; /*!< JTAG IBF Status */ + __I uint16_t RESERVED; + __IO uint32_t DBG_CTRL; /*!< JTAG DBG Ctrl */ +} JTAG_Type; + + +/*------------- Public Key Encryption Subsystem (PKE) -----------------------------*/ +/** @addtogroup MEC1322_PKE Public Key Encryption (PKE) + @{ +*/ +typedef struct +{ + __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */ + __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */ + __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */ + __I uint32_t STATUS; /*!< Offset: 0x000C Status */ + __I uint32_t VERSION; /*!< Offset: 0x0010 Version */ + __IO uint32_t LOAD_MICRO_CODE; /*!< Offset: 0x0014 Load Micro Code */ +} PKE_TypeDef; +/*@}*/ /* end of group MEC1322_PKE */ + +/*------------- Random Number Generator Subsystem (TRNG) -----------------------------*/ +/** @addtogroup MEC1322_TRNG Random Number Generator (TRNG) + @{ +*/ +typedef struct +{ + __IO uint32_t CONTROL; /*!< Offset: 0x0000 Control */ + __I uint32_t FIFO_LEVEL; /*!< Offset: 0x0004 FIFO Level */ + __I uint32_t VERSION; /*!< Offset: 0x0008 Version */ +} TRNG_TypeDef; +/*@}*/ /* end of group MEC1322_TRNG */ + +/*------------- Hash Subsystem (HASH) -----------------------------*/ +/** @addtogroup MEC1322_HASH Hash Security (HASH) + @{ +*/ +typedef struct +{ + __IO uint32_t SHA_MODE; /*!< Offset: 0x0000 SHA Mode */ + __IO uint32_t NB_BLOCK; /*!< Offset: 0x0004 NbBlock */ + __IO uint32_t CONTROL; /*!< Offset: 0x0008 Config */ + __I uint32_t STATUS; /*!< Offset: 0x000C Status, Read to clear interrupt */ + __I uint32_t VERSION; /*!< Offset: 0x0010 Version */ + __I uint32_t GENERIC_VALUE; /*!< Offset: 0x0014 Generic Value */ + __IO uint32_t INIT_HASH_ADDR; /*!< Offset: 0x0018 Initial Hash value Address */ + __IO uint32_t DATA_SOURCE_ADDR; /*!< Offset: 0x001C Data to hash Address */ + __IO uint32_t HASH_RESULT_ADDR; /*!< Offset: 0x0020 Hash result address */ +} HASH_TypeDef; +/*@}*/ /* end of group MEC1322_HASH */ + + + +/*------------- Advanced Encryption Subsystem (AES) -----------------------------*/ +/** @addtogroup MEC1322_AES Advanced Encryption Subsys (AES) + @{ +*/ + +#define AES_MAX_KEY_WLEN (8) +#define AES_MAX_IV_WLEN (4) + +typedef struct +{ + __IO uint32_t CONFIG; /*!< Offset: 0x0000 Configuration */ + __IO uint32_t COMMAND; /*!< Offset: 0x0004 Command */ + __IO uint32_t CONTROL; /*!< Offset: 0x0008 Control */ + __I uint32_t STATUS; /*!< Offset: 0x000C Status */ + __I uint32_t VERSION; /*!< Offset: 0x0010 Version */ + __IO uint32_t NB_HEADER; /*!< Offset: 0x0014 Number of Headers */ + __IO uint32_t LAST_HEADER; /*!< Offset: 0x0018 Last Header */ + __IO uint32_t NB_BLOCK; /*!< Offset: 0x001C Number of Blocks */ + __IO uint32_t LAST_BLOCK; /*!< Offset: 0x0020 Last Block */ + __IO uint32_t DMA_IN; /*!< Offset: 0x0024 DMA Input Address */ + __IO uint32_t DMA_OUT; /*!< Offset: 0x0028 DMA Output Address */ + uint32_t RESERVEDA[(0xFC - 0x2C)/4 + 1]; + __IO uint32_t KEY1[AES_MAX_KEY_WLEN];/*!< Offset: 0x0100 KeyIn1[159:128] + !< Offset: 0x0104 KeyIn1[191:160] + !< Offset: 0x0108 KeyIn1[223:192] + !< Offset: 0x010C KeyIn1[255:224] + !< Offset: 0x0110 KeyIn1[31:0] + !< Offset: 0x0114 KeyIn1[63:32] + !< Offset: 0x0118 KeyIn1[95:64] + !< Offset: 0x011C KeyIn1[127:96] */ + __IO uint32_t IV[AES_MAX_IV_WLEN]; /*!< Offset: 0x0120 IV[31:0] + !< Offset: 0x0124 IV[63:32] + !< Offset: 0x0128 IV[95:64] + !< Offset: 0x012C IV[127:96] */ + uint32_t RESERVEDB[4]; + __IO uint32_t KEY2[AES_MAX_KEY_WLEN];/*!< Offset: 0x0140 KeyIn1[159:128] + !< Offset: 0x0144 KeyIn1[191:160] + !< Offset: 0x0148 KeyIn1[223:192] + !< Offset: 0x014C KeyIn1[255:224] + !< Offset: 0x0150 KeyIn1[31:0] + !< Offset: 0x0154 KeyIn1[63:32] + !< Offset: 0x0158 KeyIn1[95:64] + !< Offset: 0x015C KeyIn1[127:96] */ +} AES_TypeDef; +/*@}*/ /* end of group MEC1322_AES */ + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ struct 'PCR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PCR_EC_SLP_EN ------------------------------- */ +#define PCR_EC_SLP_EN_INT_SLP_EN_Pos (0UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bit 0) */ +#define PCR_EC_SLP_EN_INT_SLP_EN_Msk (0x1UL) /*!< PCR EC_SLP_EN: INT_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PECI_SLP_EN_Pos (1UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bit 1) */ +#define PCR_EC_SLP_EN_PECI_SLP_EN_Msk (0x2UL) /*!< PCR EC_SLP_EN: PECI_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_TACH0_SLP_EN_Pos (2UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bit 2) */ +#define PCR_EC_SLP_EN_TACH0_SLP_EN_Msk (0x4UL) /*!< PCR EC_SLP_EN: TACH0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PWM0_SLP_EN_Pos (4UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bit 4) */ +#define PCR_EC_SLP_EN_PWM0_SLP_EN_Msk (0x10UL) /*!< PCR EC_SLP_EN: PWM0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PMC_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bit 5) */ +#define PCR_EC_SLP_EN_PMC_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN: PMC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_DMA_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bit 6) */ +#define PCR_EC_SLP_EN_DMA_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN: DMA_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_TFDP_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bit 7) */ +#define PCR_EC_SLP_EN_TFDP_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN: TFDP_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bit 8) */ +#define PCR_EC_SLP_EN_PROCESSOR_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN: PROCESSOR_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_WDT_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bit 9) */ +#define PCR_EC_SLP_EN_WDT_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN: WDT_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_SMB0_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bit 10) */ +#define PCR_EC_SLP_EN_SMB0_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN: SMB0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_TACH1_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bit 11) */ +#define PCR_EC_SLP_EN_TACH1_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN: TACH1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PWM1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bit 20) */ +#define PCR_EC_SLP_EN_PWM1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN: PWM1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PWM2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bit 21) */ +#define PCR_EC_SLP_EN_PWM2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN: PWM2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_PWM3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bit 22) */ +#define PCR_EC_SLP_EN_PWM3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN: PWM3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Pos (29UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bit 29) */ +#define PCR_EC_SLP_EN_EC_REG_BANK_SLP_EN_Msk (0x20000000UL) /*!< PCR EC_SLP_EN: EC_REG_BANK_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Pos (30UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bit 30) */ +#define PCR_EC_SLP_EN_TIMER16_0_SLP_EN_Msk (0x40000000UL) /*!< PCR EC_SLP_EN: TIMER16_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Pos (31UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bit 31) */ +#define PCR_EC_SLP_EN_TIMER16_1_SLP_EN_Msk (0x80000000UL) /*!< PCR EC_SLP_EN: TIMER16_1_SLP_EN (Bitfield-Mask: 0x01) */ + +/* ----------------------------- PCR_EC_CLK_REQ_STS ----------------------------- */ +#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Pos (0UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bit 0) */ +#define PCR_EC_CLK_REQ_STS_INT_CLK_REQ_Msk (0x1UL) /*!< PCR EC_CLK_REQ_STS: INT_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Pos (1UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bit 1) */ +#define PCR_EC_CLK_REQ_STS_PECI_CLK_REQ_Msk (0x2UL) /*!< PCR EC_CLK_REQ_STS: PECI_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Pos (2UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bit 2) */ +#define PCR_EC_CLK_REQ_STS_TACH0_CLK_REQ_Msk (0x4UL) /*!< PCR EC_CLK_REQ_STS: TACH0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Pos (4UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bit 4) */ +#define PCR_EC_CLK_REQ_STS_PWM0_CLK_REQ_Msk (0x10UL) /*!< PCR EC_CLK_REQ_STS: PWM0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bit 5) */ +#define PCR_EC_CLK_REQ_STS_PMC_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ_STS: PMC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bit 6) */ +#define PCR_EC_CLK_REQ_STS_DMA_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ_STS: DMA_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bit 7) */ +#define PCR_EC_CLK_REQ_STS_TFDP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ_STS: TFDP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bit 8) */ +#define PCR_EC_CLK_REQ_STS_PROCESSOR_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ_STS: PROCESSOR_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bit 9) */ +#define PCR_EC_CLK_REQ_STS_WDT_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ_STS: WDT_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bit 10) */ +#define PCR_EC_CLK_REQ_STS_SMB0_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ_STS: SMB0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bit 11) */ +#define PCR_EC_CLK_REQ_STS_TACH1_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ_STS: TACH1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bit 20) */ +#define PCR_EC_CLK_REQ_STS_PWM1_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ_STS: PWM1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bit 21) */ +#define PCR_EC_CLK_REQ_STS_PWM2_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ_STS: PWM2_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bit 22) */ +#define PCR_EC_CLK_REQ_STS_PWM3_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ_STS: PWM3_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Pos (29UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bit 29) */ +#define PCR_EC_CLK_REQ_STS_EC_REG_BANK_CLK_REQ_Msk (0x20000000UL) /*!< PCR EC_CLK_REQ_STS: EC_REG_BANK_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Pos (30UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bit 30) */ +#define PCR_EC_CLK_REQ_STS_TIMER16_0_CLK_REQ_Msk (0x40000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Pos (31UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bit 31) */ +#define PCR_EC_CLK_REQ_STS_TIMER16_1_CLK_REQ_Msk (0x80000000UL) /*!< PCR EC_CLK_REQ_STS: TIMER16_1_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PCR_HOST_SLP_EN ------------------------------ */ +#define PCR_HOST_SLP_EN_LPC_SLP_EN_Pos (0UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bit 0) */ +#define PCR_HOST_SLP_EN_LPC_SLP_EN_Msk (0x1UL) /*!< PCR HOST_SLP_EN: LPC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Pos (1UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bit 1) */ +#define PCR_HOST_SLP_EN_UART_0_SLP_EN_Msk (0x2UL) /*!< PCR HOST_SLP_EN: UART_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Pos (12UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bit 12) */ +#define PCR_HOST_SLP_EN_GLBL_CFG_SLP_EN_Msk (0x1000UL) /*!< PCR HOST_SLP_EN: GLBL_CFG_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Pos (13UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bit 13) */ +#define PCR_HOST_SLP_EN_ACPI_EC_0_SLP_EN_Msk (0x2000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Pos (14UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bit 14) */ +#define PCR_HOST_SLP_EN_ACPI_EC_1_SLP_EN_Msk (0x4000UL) /*!< PCR HOST_SLP_EN: ACPI_EC_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Pos (15UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bit 15) */ +#define PCR_HOST_SLP_EN_ACPI_PM1_SLP_EN_Msk (0x8000UL) /*!< PCR HOST_SLP_EN: ACPI_PM1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Pos (16UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bit 16) */ +#define PCR_HOST_SLP_EN_KBCEM_SLP_EN_Msk (0x10000UL) /*!< PCR HOST_SLP_EN: KBCEM_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_SLP_EN_RTC_SLP_EN_Pos (18UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bit 18) */ +#define PCR_HOST_SLP_EN_RTC_SLP_EN_Msk (0x40000UL) /*!< PCR HOST_SLP_EN: RTC_SLP_EN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ PCR_HOST_CLK_REQ ------------------------------ */ +#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Pos (0UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bit 0) */ +#define PCR_HOST_CLK_REQ_LPC_CLK_REQ_Msk (0x1UL) /*!< PCR HOST_CLK_REQ: LPC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Pos (1UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bit 1) */ +#define PCR_HOST_CLK_REQ_UART_0_CLK_REQ_Msk (0x2UL) /*!< PCR HOST_CLK_REQ: UART_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Pos (12UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bit 12) */ +#define PCR_HOST_CLK_REQ_GLBL_CFG_CLK_REQ_Msk (0x1000UL) /*!< PCR HOST_CLK_REQ: GLBL_CFG_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Pos (13UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bit 13) */ +#define PCR_HOST_CLK_REQ_ACPI_EC_0_CLK_REQ_Msk (0x2000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_0_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Pos (14UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bit 14) */ +#define PCR_HOST_CLK_REQ_ACPI_EC_1_CLK_REQ_Msk (0x4000UL) /*!< PCR HOST_CLK_REQ: ACPI_EC_1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Pos (15UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bit 15) */ +#define PCR_HOST_CLK_REQ_ACPI_PM1_CLK_REQ_Msk (0x8000UL) /*!< PCR HOST_CLK_REQ: ACPI_PM1_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Pos (16UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bit 16) */ +#define PCR_HOST_CLK_REQ_KBCEM_CLK_REQ_Msk (0x10000UL) /*!< PCR HOST_CLK_REQ: KBCEM_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Pos (18UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bit 18) */ +#define PCR_HOST_CLK_REQ_RTC_CLK_REQ_Msk (0x40000UL) /*!< PCR HOST_CLK_REQ: RTC_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* ------------------------------ PCR_SYS_SLP_CNTRL ----------------------------- */ +#define PCR_SYS_SLP_CNTRL_ROSC_PD_Pos (0UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bit 0) */ +#define PCR_SYS_SLP_CNTRL_ROSC_PD_Msk (0x1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_PD (Bitfield-Mask: 0x01) */ +#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Pos (1UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bit 1) */ +#define PCR_SYS_SLP_CNTRL_ROSC_GATE_Msk (0x2UL) /*!< PCR SYS_SLP_CNTRL: ROSC_GATE (Bitfield-Mask: 0x01) */ +#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Pos (2UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bit 2) */ +#define PCR_SYS_SLP_CNTRL_REGULATOR_STDBY_Msk (0x4UL) /*!< PCR SYS_SLP_CNTRL: REGULATOR_STDBY (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PCR_EC_SLP_EN2 ------------------------------- */ +#define PCR_EC_SLP_EN2_ADC_SLP_EN_Pos (3UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bit 3) */ +#define PCR_EC_SLP_EN2_ADC_SLP_EN_Msk (0x8UL) /*!< PCR EC_SLP_EN2: ADC_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Pos (5UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bit 5) */ +#define PCR_EC_SLP_EN2_PS2_0_SLP_EN_Msk (0x20UL) /*!< PCR EC_SLP_EN2: PS2_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Pos (6UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bit 6) */ +#define PCR_EC_SLP_EN2_PS2_1_SLP_EN_Msk (0x40UL) /*!< PCR EC_SLP_EN2: PS2_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Pos (7UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bit 7) */ +#define PCR_EC_SLP_EN2_PS2_2_SLP_EN_Msk (0x80UL) /*!< PCR EC_SLP_EN2: PS2_2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Pos (8UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bit 8) */ +#define PCR_EC_SLP_EN2_PS2_3_SLP_EN_Msk (0x100UL) /*!< PCR EC_SLP_EN2: PS2_3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bit 9) */ +#define PCR_EC_SLP_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_SLP_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Pos (10UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bit 10) */ +#define PCR_EC_SLP_EN2_HTIMER_SLP_EN_Msk (0x400UL) /*!< PCR EC_SLP_EN2: HTIMER_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Pos (11UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bit 11) */ +#define PCR_EC_SLP_EN2_KEYSCAN_SLP_EN_Msk (0x800UL) /*!< PCR EC_SLP_EN2: KEYSCAN_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Pos (12UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bit 12) */ +#define PCR_EC_SLP_EN2_RPMPWM_SLP_EN_Msk (0x1000UL) /*!< PCR EC_SLP_EN2: RPMPWM_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Pos (13UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bit 13) */ +#define PCR_EC_SLP_EN2_SMB1_SLP_EN_Msk (0x2000UL) /*!< PCR EC_SLP_EN2: SMB1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Pos (14UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bit 14) */ +#define PCR_EC_SLP_EN2_SMB2_SLP_EN_Msk (0x4000UL) /*!< PCR EC_SLP_EN2: SMB2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Pos (15UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bit 15) */ +#define PCR_EC_SLP_EN2_SMB3_SLP_EN_Msk (0x8000UL) /*!< PCR EC_SLP_EN2: SMB3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_LED0_SLP_EN_Pos (16UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bit 16) */ +#define PCR_EC_SLP_EN2_LED0_SLP_EN_Msk (0x10000UL) /*!< PCR EC_SLP_EN2: LED0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_LED1_SLP_EN_Pos (17UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bit 17) */ +#define PCR_EC_SLP_EN2_LED1_SLP_EN_Msk (0x20000UL) /*!< PCR EC_SLP_EN2: LED1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_LED2_SLP_EN_Pos (18UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bit 18) */ +#define PCR_EC_SLP_EN2_LED2_SLP_EN_Msk (0x40000UL) /*!< PCR EC_SLP_EN2: LED2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_BCM_SLP_EN_Pos (19UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bit 19) */ +#define PCR_EC_SLP_EN2_BCM_SLP_EN_Msk (0x80000UL) /*!< PCR EC_SLP_EN2: BCM_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Pos (20UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bit 20) */ +#define PCR_EC_SLP_EN2_SPI1_SLP_EN_Msk (0x100000UL) /*!< PCR EC_SLP_EN2: SPI1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Pos (21UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bit 21) */ +#define PCR_EC_SLP_EN2_TIMER16_2_SLP_EN_Msk (0x200000UL) /*!< PCR EC_SLP_EN2: TIMER16_2_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Pos (22UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bit 22) */ +#define PCR_EC_SLP_EN2_TIMER16_3_SLP_EN_Msk (0x400000UL) /*!< PCR EC_SLP_EN2: TIMER16_3_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Pos (23UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bit 23) */ +#define PCR_EC_SLP_EN2_TIMER32_0_SLP_EN_Msk (0x800000UL) /*!< PCR EC_SLP_EN2: TIMER32_0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Pos (24UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bit 24) */ +#define PCR_EC_SLP_EN2_TIMER32_1_SLP_EN_Msk (0x1000000UL) /*!< PCR EC_SLP_EN2: TIMER32_1_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_SLP_EN2_LED3_SLP_EN_Pos (25UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bit 25) */ +#define PCR_EC_SLP_EN2_LED3_SLP_EN_Msk (0x2000000UL) /*!< PCR EC_SLP_EN2: LED3_SLP_EN (Bitfield-Mask: 0x01) */ + +/* ----------------------------- PCR_EC_CLK_REQ2_STS ---------------------------- */ +#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Pos (3UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bit 3) */ +#define PCR_EC_CLK_REQ2_STS_ADC_CLK_REQ_Msk (0x8UL) /*!< PCR EC_CLK_REQ2_STS: ADC_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Pos (5UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bit 5) */ +#define PCR_EC_CLK_REQ2_STS_PS2_0_SLP_CLK_REQ_Msk (0x20UL) /*!< PCR EC_CLK_REQ2_STS: PS2_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Pos (6UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bit 6) */ +#define PCR_EC_CLK_REQ2_STS_PS2_1_SLP_CLK_REQ_Msk (0x40UL) /*!< PCR EC_CLK_REQ2_STS: PS2_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Pos (7UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bit 7) */ +#define PCR_EC_CLK_REQ2_STS_PS2_2_SLP_CLK_REQ_Msk (0x80UL) /*!< PCR EC_CLK_REQ2_STS: PS2_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Pos (8UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bit 8) */ +#define PCR_EC_CLK_REQ2_STS_PS2_3_SLP_CLK_REQ_Msk (0x100UL) /*!< PCR EC_CLK_REQ2_STS: PS2_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Pos (9UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bit 9) */ +#define PCR_EC_CLK_REQ2_STS_SPI0_SLP_CLK_REQ_Msk (0x200UL) /*!< PCR EC_CLK_REQ2_STS: SPI0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Pos (10UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bit 10) */ +#define PCR_EC_CLK_REQ2_STS_HTIMER_SLP_CLK_REQ_Msk (0x400UL) /*!< PCR EC_CLK_REQ2_STS: HTIMER_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Pos (11UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bit 11) */ +#define PCR_EC_CLK_REQ2_STS_KEYSCAN_SLP_CLK_REQ_Msk (0x800UL) /*!< PCR EC_CLK_REQ2_STS: KEYSCAN_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Pos (12UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bit 12) */ +#define PCR_EC_CLK_REQ2_STS_RPMPWM_SLP_CLK_REQ_Msk (0x1000UL) /*!< PCR EC_CLK_REQ2_STS: RPMPWM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Pos (13UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bit 13) */ +#define PCR_EC_CLK_REQ2_STS_SMB1_SLP_CLK_REQ_Msk (0x2000UL) /*!< PCR EC_CLK_REQ2_STS: SMB1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Pos (14UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bit 14) */ +#define PCR_EC_CLK_REQ2_STS_SMB2_SLP_CLK_REQ_Msk (0x4000UL) /*!< PCR EC_CLK_REQ2_STS: SMB2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Pos (15UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bit 15) */ +#define PCR_EC_CLK_REQ2_STS_SMB3_SLP_CLK_REQ_Msk (0x8000UL) /*!< PCR EC_CLK_REQ2_STS: SMB3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Pos (16UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bit 16) */ +#define PCR_EC_CLK_REQ2_STS_LED0_SLP_CLK_REQ_Msk (0x10000UL) /*!< PCR EC_CLK_REQ2_STS: LED0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Pos (17UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bit 17) */ +#define PCR_EC_CLK_REQ2_STS_LED1_SLP_CLK_REQ_Msk (0x20000UL) /*!< PCR EC_CLK_REQ2_STS: LED1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Pos (18UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bit 18) */ +#define PCR_EC_CLK_REQ2_STS_LED2_SLP_CLK_REQ_Msk (0x40000UL) /*!< PCR EC_CLK_REQ2_STS: LED2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Pos (19UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bit 19) */ +#define PCR_EC_CLK_REQ2_STS_BCM_SLP_CLK_REQ_Msk (0x80000UL) /*!< PCR EC_CLK_REQ2_STS: BCM_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Pos (20UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bit 20) */ +#define PCR_EC_CLK_REQ2_STS_SPI1_SLP_CLK_REQ_Msk (0x100000UL) /*!< PCR EC_CLK_REQ2_STS: SPI1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Pos (21UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bit 21) */ +#define PCR_EC_CLK_REQ2_STS_TIMER16_2_SLP_CLK_REQ_Msk (0x200000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_2_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Pos (22UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bit 22) */ +#define PCR_EC_CLK_REQ2_STS_TIMER16_3_SLP_CLK_REQ_Msk (0x400000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER16_3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Pos (23UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bit 23) */ +#define PCR_EC_CLK_REQ2_STS_TIMER32_0_SLP_CLK_REQ_Msk (0x800000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_0_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Pos (24UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bit 24) */ +#define PCR_EC_CLK_REQ2_STS_TIMER32_1_SLP_CLK_REQ_Msk (0x1000000UL) /*!< PCR EC_CLK_REQ2_STS: TIMER32_1_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ +#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Pos (25UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bit 25) */ +#define PCR_EC_CLK_REQ2_STS_LED3_SLP_CLK_REQ_Msk (0x2000000UL) /*!< PCR EC_CLK_REQ2_STS: LED3_SLP_CLK_REQ (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PCR_CHIP_OSC_ID ------------------------------ */ +#define PCR_CHIP_OSC_ID_OSC_LOCK_Pos (8UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bit 8) */ +#define PCR_CHIP_OSC_ID_OSC_LOCK_Msk (0x100UL) /*!< PCR CHIP_OSC_ID: OSC_LOCK (Bitfield-Mask: 0x01) */ + +/* ---------------------------- PCR_CHIP_PWR_RST_STS ---------------------------- */ +#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Pos (2UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bit 2) */ +#define PCR_CHIP_PWR_RST_STS_VCC_nRST_Msk (0x4UL) /*!< PCR CHIP_PWR_RST_STS: VCC_nRST (Bitfield-Mask: 0x01) */ +#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Pos (3UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bit 3) */ +#define PCR_CHIP_PWR_RST_STS_SIO_nRST_Msk (0x8UL) /*!< PCR CHIP_PWR_RST_STS: SIO_nRST (Bitfield-Mask: 0x01) */ +#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Pos (5UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bit 5) */ +#define PCR_CHIP_PWR_RST_STS_VBAT_RST_Msk (0x20UL) /*!< PCR CHIP_PWR_RST_STS: VBAT_RST (Bitfield-Mask: 0x01) */ +#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Pos (6UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bit 6) */ +#define PCR_CHIP_PWR_RST_STS_VCC1_RST_Msk (0x40UL) /*!< PCR CHIP_PWR_RST_STS: VCC1_RST (Bitfield-Mask: 0x01) */ +#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Pos (10UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bit 10) */ +#define PCR_CHIP_PWR_RST_STS__32K_ACTIVE_Msk (0x400UL) /*!< PCR CHIP_PWR_RST_STS: _32K_ACTIVE (Bitfield-Mask: 0x01) */ +#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Pos (11UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bit 11) */ +#define PCR_CHIP_PWR_RST_STS_PCICLK_ACTIVE_Msk (0x800UL) /*!< PCR CHIP_PWR_RST_STS: PCICLK_ACTIVE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PCR_HOST_RST_EN ------------------------------ */ +#define PCR_HOST_RST_EN_LPC_RST_EN_Pos (0UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bit 0) */ +#define PCR_HOST_RST_EN_LPC_RST_EN_Msk (0x1UL) /*!< PCR HOST_RST_EN: LPC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_UART_0_RST_EN_Pos (1UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bit 1) */ +#define PCR_HOST_RST_EN_UART_0_RST_EN_Msk (0x2UL) /*!< PCR HOST_RST_EN: UART_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Pos (12UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bit 12) */ +#define PCR_HOST_RST_EN_GLBL_CFG_RST_EN_Msk (0x1000UL) /*!< PCR HOST_RST_EN: GLBL_CFG_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Pos (13UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bit 13) */ +#define PCR_HOST_RST_EN_ACPI_EC_0_RST_EN_Msk (0x2000UL) /*!< PCR HOST_RST_EN: ACPI_EC_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Pos (14UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bit 14) */ +#define PCR_HOST_RST_EN_ACPI_EC_1_RST_EN_Msk (0x4000UL) /*!< PCR HOST_RST_EN: ACPI_EC_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Pos (15UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bit 15) */ +#define PCR_HOST_RST_EN_ACPI_PM1_RST_EN_Msk (0x8000UL) /*!< PCR HOST_RST_EN: ACPI_PM1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_KBCEM_RST_EN_Pos (16UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bit 16) */ +#define PCR_HOST_RST_EN_KBCEM_RST_EN_Msk (0x10000UL) /*!< PCR HOST_RST_EN: KBCEM_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_HOST_RST_EN_RTC_RST_EN_Pos (18UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bit 18) */ +#define PCR_HOST_RST_EN_RTC_RST_EN_Msk (0x40000UL) /*!< PCR HOST_RST_EN: RTC_RST_EN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PCR_EC_RST_EN ------------------------------- */ +#define PCR_EC_RST_EN_INT_RST_EN_Pos (0UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bit 0) */ +#define PCR_EC_RST_EN_INT_RST_EN_Msk (0x1UL) /*!< PCR EC_RST_EN: INT_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PECI_RST_EN_Pos (1UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bit 1) */ +#define PCR_EC_RST_EN_PECI_RST_EN_Msk (0x2UL) /*!< PCR EC_RST_EN: PECI_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_TACH0_RST_EN_Pos (2UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bit 2) */ +#define PCR_EC_RST_EN_TACH0_RST_EN_Msk (0x4UL) /*!< PCR EC_RST_EN: TACH0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PWM0_RST_EN_Pos (4UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bit 4) */ +#define PCR_EC_RST_EN_PWM0_RST_EN_Msk (0x10UL) /*!< PCR EC_RST_EN: PWM0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PMC_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bit 5) */ +#define PCR_EC_RST_EN_PMC_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN: PMC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_DMA_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bit 6) */ +#define PCR_EC_RST_EN_DMA_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN: DMA_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_TFDP_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bit 7) */ +#define PCR_EC_RST_EN_TFDP_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN: TFDP_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bit 8) */ +#define PCR_EC_RST_EN_PROCESSOR_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN: PROCESSOR_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_WDT_RST_EN_Pos (9UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bit 9) */ +#define PCR_EC_RST_EN_WDT_RST_EN_Msk (0x200UL) /*!< PCR EC_RST_EN: WDT_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_SMB0_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bit 10) */ +#define PCR_EC_RST_EN_SMB0_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN: SMB0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_TACH1_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bit 11) */ +#define PCR_EC_RST_EN_TACH1_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN: TACH1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PWM1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bit 20) */ +#define PCR_EC_RST_EN_PWM1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN: PWM1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PWM2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bit 21) */ +#define PCR_EC_RST_EN_PWM2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN: PWM2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_PWM3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bit 22) */ +#define PCR_EC_RST_EN_PWM3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN: PWM3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Pos (29UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bit 29) */ +#define PCR_EC_RST_EN_EC_REG_BANK_RST_EN_Msk (0x20000000UL) /*!< PCR EC_RST_EN: EC_REG_BANK_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Pos (30UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bit 30) */ +#define PCR_EC_RST_EN_TIMER16_0_RST_EN_Msk (0x40000000UL) /*!< PCR EC_RST_EN: TIMER16_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Pos (31UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bit 31) */ +#define PCR_EC_RST_EN_TIMER16_1_RST_EN_Msk (0x80000000UL) /*!< PCR EC_RST_EN: TIMER16_1_RST_EN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PCR_EC_RST_EN2 ------------------------------- */ +#define PCR_EC_RST_EN2_ADC_RST_EN_Pos (3UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bit 3) */ +#define PCR_EC_RST_EN2_ADC_RST_EN_Msk (0x8UL) /*!< PCR EC_RST_EN2: ADC_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_PS2_0_RST_EN_Pos (5UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bit 5) */ +#define PCR_EC_RST_EN2_PS2_0_RST_EN_Msk (0x20UL) /*!< PCR EC_RST_EN2: PS2_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_PS2_1_RST_EN_Pos (6UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bit 6) */ +#define PCR_EC_RST_EN2_PS2_1_RST_EN_Msk (0x40UL) /*!< PCR EC_RST_EN2: PS2_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_PS2_2_RST_EN_Pos (7UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bit 7) */ +#define PCR_EC_RST_EN2_PS2_2_RST_EN_Msk (0x80UL) /*!< PCR EC_RST_EN2: PS2_2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_PS2_3_RST_EN_Pos (8UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bit 8) */ +#define PCR_EC_RST_EN2_PS2_3_RST_EN_Msk (0x100UL) /*!< PCR EC_RST_EN2: PS2_3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_SPI0_SLP_EN_Pos (9UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bit 9) */ +#define PCR_EC_RST_EN2_SPI0_SLP_EN_Msk (0x200UL) /*!< PCR EC_RST_EN2: SPI0_SLP_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_HTIMER_RST_EN_Pos (10UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bit 10) */ +#define PCR_EC_RST_EN2_HTIMER_RST_EN_Msk (0x400UL) /*!< PCR EC_RST_EN2: HTIMER_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Pos (11UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bit 11) */ +#define PCR_EC_RST_EN2_KEYSCAN_RST_EN_Msk (0x800UL) /*!< PCR EC_RST_EN2: KEYSCAN_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Pos (12UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bit 12) */ +#define PCR_EC_RST_EN2_RPMPWM_RST_EN_Msk (0x1000UL) /*!< PCR EC_RST_EN2: RPMPWM_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_SMB1_RST_EN_Pos (13UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bit 13) */ +#define PCR_EC_RST_EN2_SMB1_RST_EN_Msk (0x2000UL) /*!< PCR EC_RST_EN2: SMB1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_SMB2_RST_EN_Pos (14UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bit 14) */ +#define PCR_EC_RST_EN2_SMB2_RST_EN_Msk (0x4000UL) /*!< PCR EC_RST_EN2: SMB2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_SMB3_RST_EN_Pos (15UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bit 15) */ +#define PCR_EC_RST_EN2_SMB3_RST_EN_Msk (0x8000UL) /*!< PCR EC_RST_EN2: SMB3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_LED0_RST_EN_Pos (16UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bit 16) */ +#define PCR_EC_RST_EN2_LED0_RST_EN_Msk (0x10000UL) /*!< PCR EC_RST_EN2: LED0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_LED1_RST_EN_Pos (17UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bit 17) */ +#define PCR_EC_RST_EN2_LED1_RST_EN_Msk (0x20000UL) /*!< PCR EC_RST_EN2: LED1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_LED2_RST_EN_Pos (18UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bit 18) */ +#define PCR_EC_RST_EN2_LED2_RST_EN_Msk (0x40000UL) /*!< PCR EC_RST_EN2: LED2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_BCM_RST_EN_Pos (19UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bit 19) */ +#define PCR_EC_RST_EN2_BCM_RST_EN_Msk (0x80000UL) /*!< PCR EC_RST_EN2: BCM_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_SPI1_RST_EN_Pos (20UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bit 20) */ +#define PCR_EC_RST_EN2_SPI1_RST_EN_Msk (0x100000UL) /*!< PCR EC_RST_EN2: SPI1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Pos (21UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bit 21) */ +#define PCR_EC_RST_EN2_TIMER16_2_RST_EN_Msk (0x200000UL) /*!< PCR EC_RST_EN2: TIMER16_2_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Pos (22UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bit 22) */ +#define PCR_EC_RST_EN2_TIMER16_3_RST_EN_Msk (0x400000UL) /*!< PCR EC_RST_EN2: TIMER16_3_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Pos (23UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bit 23) */ +#define PCR_EC_RST_EN2_TIMER32_0_RST_EN_Msk (0x800000UL) /*!< PCR EC_RST_EN2: TIMER32_0_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Pos (24UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bit 24) */ +#define PCR_EC_RST_EN2_TIMER32_1_RST_EN_Msk (0x1000000UL) /*!< PCR EC_RST_EN2: TIMER32_1_RST_EN (Bitfield-Mask: 0x01) */ +#define PCR_EC_RST_EN2_LED3_RST_EN_Pos (25UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bit 25) */ +#define PCR_EC_RST_EN2_LED3_RST_EN_Msk (0x2000000UL) /*!< PCR EC_RST_EN2: LED3_RST_EN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ PCR_PWR_RST_CTRL ------------------------------ */ +#define PCR_PWR_RST_CTRL_IRESET_OUT_Pos (0UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bit 0) */ +#define PCR_PWR_RST_CTRL_IRESET_OUT_Msk (0x1UL) /*!< PCR PWR_RST_CTRL: IRESET_OUT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'VBAT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- VBAT_PFR_STS -------------------------------- */ +#define VBAT_PFR_STS_DET32K_IN_Pos (0UL) /*!< VBAT PFR_STS: DET32K_IN (Bit 0) */ +#define VBAT_PFR_STS_DET32K_IN_Msk (0x1UL) /*!< VBAT PFR_STS: DET32K_IN (Bitfield-Mask: 0x01) */ +#define VBAT_PFR_STS_WDT_Pos (5UL) /*!< VBAT PFR_STS: WDT (Bit 5) */ +#define VBAT_PFR_STS_WDT_Msk (0x20UL) /*!< VBAT PFR_STS: WDT (Bitfield-Mask: 0x01) */ +#define VBAT_PFR_STS_VBAT_RST_Pos (7UL) /*!< VBAT PFR_STS: VBAT_RST (Bit 7) */ +#define VBAT_PFR_STS_VBAT_RST_Msk (0x80UL) /*!< VBAT PFR_STS: VBAT_RST (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VBAT_CLOCK_EN ------------------------------- */ +#define VBAT_CLOCK_EN_XOSEL_Pos (0UL) /*!< VBAT CLOCK_EN: XOSEL (Bit 0) */ +#define VBAT_CLOCK_EN_XOSEL_Msk (0x1UL) /*!< VBAT CLOCK_EN: XOSEL (Bitfield-Mask: 0x01) */ +#define VBAT_CLOCK_EN__32K_EN_Pos (1UL) /*!< VBAT CLOCK_EN: _32K_EN (Bit 1) */ +#define VBAT_CLOCK_EN__32K_EN_Msk (0x2UL) /*!< VBAT CLOCK_EN: _32K_EN (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'LPC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- LPC_BUS_MONITOR ------------------------------ */ +#define LPC_BUS_MONITOR_LRESET_STATUS_Pos (1UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bit 1) */ +#define LPC_BUS_MONITOR_LRESET_STATUS_Msk (0x2UL) /*!< LPC BUS_MONITOR: LRESET_STATUS (Bitfield-Mask: 0x01) */ + +/* ----------------------------- LPC_HOST_BUS_ERROR ----------------------------- */ +#define LPC_HOST_BUS_ERROR_LPC_ERR_Pos (0UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bit 0) */ +#define LPC_HOST_BUS_ERROR_LPC_ERR_Msk (0x1UL) /*!< LPC HOST_BUS_ERROR: LPC_ERR (Bitfield-Mask: 0x01) */ +#define LPC_HOST_BUS_ERROR_EN_ERR_Pos (1UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bit 1) */ +#define LPC_HOST_BUS_ERROR_EN_ERR_Msk (0x2UL) /*!< LPC HOST_BUS_ERROR: EN_ERR (Bitfield-Mask: 0x01) */ +#define LPC_HOST_BUS_ERROR_BAR_ERR_Pos (2UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bit 2) */ +#define LPC_HOST_BUS_ERROR_BAR_ERR_Msk (0x4UL) /*!< LPC HOST_BUS_ERROR: BAR_ERR (Bitfield-Mask: 0x01) */ +#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Pos (3UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bit 3) */ +#define LPC_HOST_BUS_ERROR_RUNTIME_ERR_Msk (0x8UL) /*!< LPC HOST_BUS_ERROR: RUNTIME_ERR (Bitfield-Mask: 0x01) */ +#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Pos (4UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bit 4) */ +#define LPC_HOST_BUS_ERROR_CONFIG_ERR_Msk (0x10UL) /*!< LPC HOST_BUS_ERROR: CONFIG_ERR (Bitfield-Mask: 0x01) */ +#define LPC_HOST_BUS_ERROR_DMA_ERR_Pos (5UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bit 5) */ +#define LPC_HOST_BUS_ERROR_DMA_ERR_Msk (0x20UL) /*!< LPC HOST_BUS_ERROR: DMA_ERR (Bitfield-Mask: 0x01) */ +#define LPC_HOST_BUS_ERROR_ERR_ADDR_Pos (8UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bit 8) */ +#define LPC_HOST_BUS_ERROR_ERR_ADDR_Msk (0xffffff00UL) /*!< LPC HOST_BUS_ERROR: ERR_ADDR (Bitfield-Mask: 0xffffff) */ + +/* -------------------------------- LPC_EC_SERIRQ ------------------------------- */ +#define LPC_EC_SERIRQ_EC_IRQ_Pos (0UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bit 0) */ +#define LPC_EC_SERIRQ_EC_IRQ_Msk (0x1UL) /*!< LPC EC_SERIRQ: EC_IRQ (Bitfield-Mask: 0x01) */ + +/* -------------------------------- LPC_CLK_CTRL -------------------------------- */ +#define LPC_CLK_CTRL_CR_Pos (0UL) /*!< LPC CLK_CTRL: CR (Bit 0) */ +#define LPC_CLK_CTRL_CR_Msk (0x3UL) /*!< LPC CLK_CTRL: CR (Bitfield-Mask: 0x03) */ +#define LPC_CLK_CTRL_HANDSHAKE_Pos (2UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bit 2) */ +#define LPC_CLK_CTRL_HANDSHAKE_Msk (0x4UL) /*!< LPC CLK_CTRL: HANDSHAKE (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'LPC_CONFIG' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- LPC_CONFIG_SIRQ ------------------------------ */ +#define LPC_CONFIG_SIRQ_FRAME_Pos (0UL) /*!< LPC_CONFIG SIRQ: FRAME (Bit 0) */ +#define LPC_CONFIG_SIRQ_FRAME_Msk (0x3fUL) /*!< LPC_CONFIG SIRQ: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_SIRQ_DEVICE_Pos (6UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bit 6) */ +#define LPC_CONFIG_SIRQ_DEVICE_Msk (0x40UL) /*!< LPC_CONFIG SIRQ: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_SIRQ_SELECT_Pos (7UL) /*!< LPC_CONFIG SIRQ: SELECT (Bit 7) */ +#define LPC_CONFIG_SIRQ_SELECT_Msk (0x80UL) /*!< LPC_CONFIG SIRQ: SELECT (Bitfield-Mask: 0x01) */ + +/* ----------------------------- LPC_CONFIG_LPC_BAR ----------------------------- */ +#define LPC_CONFIG_LPC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LPC_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_LPC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LPC_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_LPC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_LPC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LPC_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_LPC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_LPC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LPC_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_LPC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_LPC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LPC_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_LPC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LPC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ LPC_CONFIG_EM_BAR ----------------------------- */ +#define LPC_CONFIG_EM_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EM_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_EM_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EM_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_EM_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_EM_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EM_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_EM_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_EM_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EM_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_EM_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EM_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_EM_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EM_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_EM_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EM_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_UART_BAR ---------------------------- */ +#define LPC_CONFIG_UART_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG UART_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_UART_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG UART_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_UART_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_UART_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG UART_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_UART_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_UART_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG UART_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_UART_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG UART_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_UART_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG UART_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_UART_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG UART_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_KBC_BAR ----------------------------- */ +#define LPC_CONFIG_KBC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG KBC_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_KBC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG KBC_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_KBC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_KBC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG KBC_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_KBC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_KBC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG KBC_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_KBC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_KBC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG KBC_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_KBC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG KBC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_EC0_BAR ----------------------------- */ +#define LPC_CONFIG_EC0_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC0_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_EC0_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC0_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_EC0_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_EC0_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC0_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_EC0_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_EC0_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC0_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_EC0_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_EC0_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC0_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_EC0_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC0_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_EC1_BAR ----------------------------- */ +#define LPC_CONFIG_EC1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG EC1_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_EC1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG EC1_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_EC1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_EC1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG EC1_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_EC1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_EC1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG EC1_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_EC1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_EC1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG EC1_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_EC1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG EC1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_PM1_BAR ----------------------------- */ +#define LPC_CONFIG_PM1_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG PM1_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_PM1_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG PM1_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_PM1_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_PM1_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG PM1_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_PM1_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_PM1_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG PM1_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_PM1_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_PM1_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG PM1_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_PM1_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG PM1_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_LGC_BAR ----------------------------- */ +#define LPC_CONFIG_LGC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG LGC_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_LGC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG LGC_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_LGC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_LGC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG LGC_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_LGC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_LGC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG LGC_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_LGC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_LGC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG LGC_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_LGC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG LGC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_MBX_BAR ----------------------------- */ +#define LPC_CONFIG_MBX_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG MBX_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_MBX_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG MBX_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_MBX_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_MBX_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG MBX_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_MBX_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_MBX_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG MBX_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_MBX_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_MBX_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG MBX_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_MBX_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG MBX_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- LPC_CONFIG_RTC_BAR ----------------------------- */ +#define LPC_CONFIG_RTC_BAR_MASK_Pos (0UL) /*!< LPC_CONFIG RTC_BAR: MASK (Bit 0) */ +#define LPC_CONFIG_RTC_BAR_MASK_Msk (0xffUL) /*!< LPC_CONFIG RTC_BAR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_RTC_BAR_FRAME_Pos (8UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bit 8) */ +#define LPC_CONFIG_RTC_BAR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG RTC_BAR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_RTC_BAR_DEVICE_Pos (14UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bit 14) */ +#define LPC_CONFIG_RTC_BAR_DEVICE_Msk (0x4000UL) /*!< LPC_CONFIG RTC_BAR: DEVICE (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_RTC_BAR_VALID_Pos (15UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bit 15) */ +#define LPC_CONFIG_RTC_BAR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG RTC_BAR: VALID (Bitfield-Mask: 0x01) */ +#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Pos (16UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bit 16) */ +#define LPC_CONFIG_RTC_BAR_LPC_HOST_ADDR_Msk (0xffff0000UL) /*!< LPC_CONFIG RTC_BAR: LPC_HOST_ADDR (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'MEM_BAR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- MEM_BAR_CR --------------------------------- */ +#define MEM_BAR_CR_MASK_Pos (0UL) /*!< MEM_BAR CR: MASK (Bit 0) */ +#define MEM_BAR_CR_MASK_Msk (0xffUL) /*!< MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ +#define MEM_BAR_CR_FRAME_Pos (8UL) /*!< MEM_BAR CR: FRAME (Bit 8) */ +#define MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ +#define MEM_BAR_CR_VALID_Pos (15UL) /*!< MEM_BAR CR: VALID (Bit 15) */ +#define MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'MBX_MEM_BAR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------- LPC_CONFIG_MBX_MEM_BAR_CR ------------------------- */ +#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bit 0) */ +#define LPC_CONFIG_MBX_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bit 8) */ +#define LPC_CONFIG_MBX_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bit 15) */ +#define LPC_CONFIG_MBX_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_MBX_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'EC0_MEM_BAR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------- LPC_CONFIG_EC0_MEM_BAR_CR ------------------------- */ +#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bit 0) */ +#define LPC_CONFIG_EC0_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bit 8) */ +#define LPC_CONFIG_EC0_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bit 15) */ +#define LPC_CONFIG_EC0_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC0_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'EC1_MEM_BAR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------- LPC_CONFIG_EC1_MEM_BAR_CR ------------------------- */ +#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bit 0) */ +#define LPC_CONFIG_EC1_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bit 8) */ +#define LPC_CONFIG_EC1_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bit 15) */ +#define LPC_CONFIG_EC1_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EC1_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'EMI_MEM_BAR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------- LPC_CONFIG_EMI_MEM_BAR_CR ------------------------- */ +#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Pos (0UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bit 0) */ +#define LPC_CONFIG_EMI_MEM_BAR_CR_MASK_Msk (0xffUL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: MASK (Bitfield-Mask: 0xff) */ +#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Pos (8UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bit 8) */ +#define LPC_CONFIG_EMI_MEM_BAR_CR_FRAME_Msk (0x3f00UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: FRAME (Bitfield-Mask: 0x3f) */ +#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Pos (15UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bit 15) */ +#define LPC_CONFIG_EMI_MEM_BAR_CR_VALID_Msk (0x8000UL) /*!< LPC_CONFIG_EMI_MEM_BAR CR: VALID (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'EMI' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- EMI_EC_ADDRESS ------------------------------- */ +#define EMI_EC_ADDRESS_ACCESS_TYPE_Pos (0UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bit 0) */ +#define EMI_EC_ADDRESS_ACCESS_TYPE_Msk (0x3UL) /*!< EMI EC_ADDRESS: ACCESS_TYPE (Bitfield-Mask: 0x03) */ +#define EMI_EC_ADDRESS_EC_ADDRESS_Pos (2UL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bit 2) */ +#define EMI_EC_ADDRESS_EC_ADDRESS_Msk (0x7ffcUL) /*!< EMI EC_ADDRESS: EC_ADDRESS (Bitfield-Mask: 0x1fff) */ +#define EMI_EC_ADDRESS_REGION_Pos (15UL) /*!< EMI EC_ADDRESS: REGION (Bit 15) */ +#define EMI_EC_ADDRESS_REGION_Msk (0x8000UL) /*!< EMI EC_ADDRESS: REGION (Bitfield-Mask: 0x01) */ + +/* --------------------------------- EMI_EC_SWI --------------------------------- */ +#define EMI_EC_SWI_EC_WR_Pos (0UL) /*!< EMI EC_SWI: EC_WR (Bit 0) */ +#define EMI_EC_SWI_EC_WR_Msk (0x1UL) /*!< EMI EC_SWI: EC_WR (Bitfield-Mask: 0x01) */ +#define EMI_EC_SWI_NOTIFICATION_Pos (1UL) /*!< EMI EC_SWI: NOTIFICATION (Bit 1) */ +#define EMI_EC_SWI_NOTIFICATION_Msk (0xfffeUL) /*!< EMI EC_SWI: NOTIFICATION (Bitfield-Mask: 0x7fff) */ + + +/* ================================================================================ */ +/* ================ struct 'ACPI_EC0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- ACPI_EC0_OS_STATUS ----------------------------- */ +#define ACPI_EC0_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bit 0) */ +#define ACPI_EC0_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 OS_STATUS: OBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bit 1) */ +#define ACPI_EC0_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 OS_STATUS: IBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bit 2) */ +#define ACPI_EC0_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC0 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bit 3) */ +#define ACPI_EC0_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 OS_STATUS: CMD (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bit 4) */ +#define ACPI_EC0_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 OS_STATUS: BURST (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bit 5) */ +#define ACPI_EC0_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bit 6) */ +#define ACPI_EC0_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bit 7) */ +#define ACPI_EC0_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC0 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */ + +/* ----------------------------- ACPI_EC0_EC_STATUS ----------------------------- */ +#define ACPI_EC0_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bit 0) */ +#define ACPI_EC0_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC0 EC_STATUS: OBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bit 1) */ +#define ACPI_EC0_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC0 EC_STATUS: IBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bit 2) */ +#define ACPI_EC0_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC0 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bit 3) */ +#define ACPI_EC0_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC0 EC_STATUS: CMD (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bit 4) */ +#define ACPI_EC0_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC0 EC_STATUS: BURST (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bit 5) */ +#define ACPI_EC0_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC0 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bit 6) */ +#define ACPI_EC0_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC0 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC0_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bit 7) */ +#define ACPI_EC0_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC0 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'ACPI_EC1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- ACPI_EC1_OS_STATUS ----------------------------- */ +#define ACPI_EC1_OS_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bit 0) */ +#define ACPI_EC1_OS_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 OS_STATUS: OBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bit 1) */ +#define ACPI_EC1_OS_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 OS_STATUS: IBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_UD1B_Pos (2UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bit 2) */ +#define ACPI_EC1_OS_STATUS_UD1B_Msk (0x4UL) /*!< ACPI_EC1 OS_STATUS: UD1B (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bit 3) */ +#define ACPI_EC1_OS_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 OS_STATUS: CMD (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bit 4) */ +#define ACPI_EC1_OS_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 OS_STATUS: BURST (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bit 5) */ +#define ACPI_EC1_OS_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 OS_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bit 6) */ +#define ACPI_EC1_OS_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 OS_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_OS_STATUS_UD0B_Pos (7UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bit 7) */ +#define ACPI_EC1_OS_STATUS_UD0B_Msk (0x80UL) /*!< ACPI_EC1 OS_STATUS: UD0B (Bitfield-Mask: 0x01) */ + +/* ----------------------------- ACPI_EC1_EC_STATUS ----------------------------- */ +#define ACPI_EC1_EC_STATUS_OBF_Pos (0UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bit 0) */ +#define ACPI_EC1_EC_STATUS_OBF_Msk (0x1UL) /*!< ACPI_EC1 EC_STATUS: OBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_IBF_Pos (1UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bit 1) */ +#define ACPI_EC1_EC_STATUS_IBF_Msk (0x2UL) /*!< ACPI_EC1 EC_STATUS: IBF (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_UD1A_Pos (2UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bit 2) */ +#define ACPI_EC1_EC_STATUS_UD1A_Msk (0x4UL) /*!< ACPI_EC1 EC_STATUS: UD1A (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_CMD_Pos (3UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bit 3) */ +#define ACPI_EC1_EC_STATUS_CMD_Msk (0x8UL) /*!< ACPI_EC1 EC_STATUS: CMD (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_BURST_Pos (4UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bit 4) */ +#define ACPI_EC1_EC_STATUS_BURST_Msk (0x10UL) /*!< ACPI_EC1 EC_STATUS: BURST (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_SCI_EVT_Pos (5UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bit 5) */ +#define ACPI_EC1_EC_STATUS_SCI_EVT_Msk (0x20UL) /*!< ACPI_EC1 EC_STATUS: SCI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_SMI_EVT_Pos (6UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bit 6) */ +#define ACPI_EC1_EC_STATUS_SMI_EVT_Msk (0x40UL) /*!< ACPI_EC1 EC_STATUS: SMI_EVT (Bitfield-Mask: 0x01) */ +#define ACPI_EC1_EC_STATUS_UD0A_Pos (7UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bit 7) */ +#define ACPI_EC1_EC_STATUS_UD0A_Msk (0x80UL) /*!< ACPI_EC1 EC_STATUS: UD0A (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'KBC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- KBC_RD_PORT64_STATUS ---------------------------- */ +#define KBC_RD_PORT64_STATUS_OBF_Pos (0UL) /*!< KBC RD_PORT64_STATUS: OBF (Bit 0) */ +#define KBC_RD_PORT64_STATUS_OBF_Msk (0x1UL) /*!< KBC RD_PORT64_STATUS: OBF (Bitfield-Mask: 0x01) */ +#define KBC_RD_PORT64_STATUS_IBF_Pos (1UL) /*!< KBC RD_PORT64_STATUS: IBF (Bit 1) */ +#define KBC_RD_PORT64_STATUS_IBF_Msk (0x2UL) /*!< KBC RD_PORT64_STATUS: IBF (Bitfield-Mask: 0x01) */ +#define KBC_RD_PORT64_STATUS_UD0_Pos (2UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bit 2) */ +#define KBC_RD_PORT64_STATUS_UD0_Msk (0x4UL) /*!< KBC RD_PORT64_STATUS: UD0 (Bitfield-Mask: 0x01) */ +#define KBC_RD_PORT64_STATUS_CMDnDATA_Pos (3UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bit 3) */ +#define KBC_RD_PORT64_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC RD_PORT64_STATUS: CMDnDATA (Bitfield-Mask: 0x01) */ +#define KBC_RD_PORT64_STATUS_UD1_Pos (4UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bit 4) */ +#define KBC_RD_PORT64_STATUS_UD1_Msk (0x10UL) /*!< KBC RD_PORT64_STATUS: UD1 (Bitfield-Mask: 0x01) */ +#define KBC_RD_PORT64_STATUS_AUXOBF_Pos (5UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bit 5) */ +#define KBC_RD_PORT64_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC RD_PORT64_STATUS: AUXOBF (Bitfield-Mask: 0x01) */ +#define KBC_RD_PORT64_STATUS_UD2_Pos (6UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bit 6) */ +#define KBC_RD_PORT64_STATUS_UD2_Msk (0xc0UL) /*!< KBC RD_PORT64_STATUS: UD2 (Bitfield-Mask: 0x03) */ + +/* --------------------------------- KBC_STATUS --------------------------------- */ +#define KBC_STATUS_OBF_Pos (0UL) /*!< KBC STATUS: OBF (Bit 0) */ +#define KBC_STATUS_OBF_Msk (0x1UL) /*!< KBC STATUS: OBF (Bitfield-Mask: 0x01) */ +#define KBC_STATUS_IBF_Pos (1UL) /*!< KBC STATUS: IBF (Bit 1) */ +#define KBC_STATUS_IBF_Msk (0x2UL) /*!< KBC STATUS: IBF (Bitfield-Mask: 0x01) */ +#define KBC_STATUS_UD0_Pos (2UL) /*!< KBC STATUS: UD0 (Bit 2) */ +#define KBC_STATUS_UD0_Msk (0x4UL) /*!< KBC STATUS: UD0 (Bitfield-Mask: 0x01) */ +#define KBC_STATUS_CMDnDATA_Pos (3UL) /*!< KBC STATUS: CMDnDATA (Bit 3) */ +#define KBC_STATUS_CMDnDATA_Msk (0x8UL) /*!< KBC STATUS: CMDnDATA (Bitfield-Mask: 0x01) */ +#define KBC_STATUS_UD1_Pos (4UL) /*!< KBC STATUS: UD1 (Bit 4) */ +#define KBC_STATUS_UD1_Msk (0x10UL) /*!< KBC STATUS: UD1 (Bitfield-Mask: 0x01) */ +#define KBC_STATUS_AUXOBF_Pos (5UL) /*!< KBC STATUS: AUXOBF (Bit 5) */ +#define KBC_STATUS_AUXOBF_Msk (0x20UL) /*!< KBC STATUS: AUXOBF (Bitfield-Mask: 0x01) */ +#define KBC_STATUS_UD2_Pos (6UL) /*!< KBC STATUS: UD2 (Bit 6) */ +#define KBC_STATUS_UD2_Msk (0xc0UL) /*!< KBC STATUS: UD2 (Bitfield-Mask: 0x03) */ + +/* --------------------------------- KBC_CONTROL -------------------------------- */ +#define KBC_CONTROL_UD3_Pos (0UL) /*!< KBC CONTROL: UD3 (Bit 0) */ +#define KBC_CONTROL_UD3_Msk (0x1UL) /*!< KBC CONTROL: UD3 (Bitfield-Mask: 0x01) */ +#define KBC_CONTROL_SAEN_Pos (1UL) /*!< KBC CONTROL: SAEN (Bit 1) */ +#define KBC_CONTROL_SAEN_Msk (0x2UL) /*!< KBC CONTROL: SAEN (Bitfield-Mask: 0x01) */ +#define KBC_CONTROL_PCOBFEN_Pos (2UL) /*!< KBC CONTROL: PCOBFEN (Bit 2) */ +#define KBC_CONTROL_PCOBFEN_Msk (0x4UL) /*!< KBC CONTROL: PCOBFEN (Bitfield-Mask: 0x01) */ +#define KBC_CONTROL_UD4_Pos (3UL) /*!< KBC CONTROL: UD4 (Bit 3) */ +#define KBC_CONTROL_UD4_Msk (0x18UL) /*!< KBC CONTROL: UD4 (Bitfield-Mask: 0x03) */ +#define KBC_CONTROL_OBFEN_Pos (5UL) /*!< KBC CONTROL: OBFEN (Bit 5) */ +#define KBC_CONTROL_OBFEN_Msk (0x20UL) /*!< KBC CONTROL: OBFEN (Bitfield-Mask: 0x01) */ +#define KBC_CONTROL_UD5_Pos (6UL) /*!< KBC CONTROL: UD5 (Bit 6) */ +#define KBC_CONTROL_UD5_Msk (0x40UL) /*!< KBC CONTROL: UD5 (Bitfield-Mask: 0x01) */ +#define KBC_CONTROL_AUXH_Pos (7UL) /*!< KBC CONTROL: AUXH (Bit 7) */ +#define KBC_CONTROL_AUXH_Msk (0x80UL) /*!< KBC CONTROL: AUXH (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'PORT92' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PORT92_PORT92 ------------------------------- */ +#define PORT92_PORT92_ALT_CPU_RESET_Pos (0UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bit 0) */ +#define PORT92_PORT92_ALT_CPU_RESET_Msk (0x1UL) /*!< PORT92 PORT92: ALT_CPU_RESET (Bitfield-Mask: 0x01) */ +#define PORT92_PORT92_ALT_GATE_A20_Pos (1UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bit 1) */ +#define PORT92_PORT92_ALT_GATE_A20_Msk (0x2UL) /*!< PORT92 PORT92: ALT_GATE_A20 (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'MBX' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- MBX_SMI_SOURCE ------------------------------- */ +#define MBX_SMI_SOURCE_EC_WR_Pos (0UL) /*!< MBX SMI_SOURCE: EC_WR (Bit 0) */ +#define MBX_SMI_SOURCE_EC_WR_Msk (0x1UL) /*!< MBX SMI_SOURCE: EC_WR (Bitfield-Mask: 0x01) */ +#define MBX_SMI_SOURCE_EC_SMI_Pos (1UL) /*!< MBX SMI_SOURCE: EC_SMI (Bit 1) */ +#define MBX_SMI_SOURCE_EC_SMI_Msk (0xfeUL) /*!< MBX SMI_SOURCE: EC_SMI (Bitfield-Mask: 0x7f) */ + +/* -------------------------------- MBX_SMI_MASK -------------------------------- */ +#define MBX_SMI_MASK_EC_WR_EN_Pos (0UL) /*!< MBX SMI_MASK: EC_WR_EN (Bit 0) */ +#define MBX_SMI_MASK_EC_WR_EN_Msk (0x1UL) /*!< MBX SMI_MASK: EC_WR_EN (Bitfield-Mask: 0x01) */ +#define MBX_SMI_MASK_EC_SMI_EN_Pos (1UL) /*!< MBX SMI_MASK: EC_SMI_EN (Bit 1) */ +#define MBX_SMI_MASK_EC_SMI_EN_Msk (0xfeUL) /*!< MBX SMI_MASK: EC_SMI_EN (Bitfield-Mask: 0x7f) */ + + +/* ================================================================================ */ +/* ================ struct 'PM1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PM1_STS2 ---------------------------------- */ +#define PM1_STS2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS2: PWRBTN_STS (Bit 0) */ +#define PM1_STS2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS2: PWRBTN_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS2: SLPBTN_STS (Bit 1) */ +#define PM1_STS2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS2: SLPBTN_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS2_RTC_STS_Pos (2UL) /*!< PM1 STS2: RTC_STS (Bit 2) */ +#define PM1_STS2_RTC_STS_Msk (0x4UL) /*!< PM1 STS2: RTC_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS2: PWRBTNOR_STS (Bit 3) */ +#define PM1_STS2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS2_WAK_STS_Pos (7UL) /*!< PM1 STS2: WAK_STS (Bit 7) */ +#define PM1_STS2_WAK_STS_Msk (0x80UL) /*!< PM1 STS2: WAK_STS (Bitfield-Mask: 0x01) */ + +/* ----------------------------------- PM1_EN2 ---------------------------------- */ +#define PM1_EN2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN2: PWRBTN_EN (Bit 0) */ +#define PM1_EN2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN2: PWRBTN_EN (Bitfield-Mask: 0x01) */ +#define PM1_EN2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN2: SLPBTN_EN (Bit 1) */ +#define PM1_EN2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN2: SLPBTN_EN (Bitfield-Mask: 0x01) */ +#define PM1_EN2_RTC_EN_Pos (2UL) /*!< PM1 EN2: RTC_EN (Bit 2) */ +#define PM1_EN2_RTC_EN_Msk (0x4UL) /*!< PM1 EN2: RTC_EN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PM1_CTRL2 --------------------------------- */ +#define PM1_CTRL2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bit 1) */ +#define PM1_CTRL2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */ +#define PM1_CTRL2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL2: SLP_TYP (Bit 2) */ +#define PM1_CTRL2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL2: SLP_TYP (Bitfield-Mask: 0x07) */ +#define PM1_CTRL2_SLP_EN_Pos (5UL) /*!< PM1 CTRL2: SLP_EN (Bit 5) */ +#define PM1_CTRL2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL2: SLP_EN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PM1_STS_2 --------------------------------- */ +#define PM1_STS_2_PWRBTN_STS_Pos (0UL) /*!< PM1 STS_2: PWRBTN_STS (Bit 0) */ +#define PM1_STS_2_PWRBTN_STS_Msk (0x1UL) /*!< PM1 STS_2: PWRBTN_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS_2_SLPBTN_STS_Pos (1UL) /*!< PM1 STS_2: SLPBTN_STS (Bit 1) */ +#define PM1_STS_2_SLPBTN_STS_Msk (0x2UL) /*!< PM1 STS_2: SLPBTN_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS_2_RTC_STS_Pos (2UL) /*!< PM1 STS_2: RTC_STS (Bit 2) */ +#define PM1_STS_2_RTC_STS_Msk (0x4UL) /*!< PM1 STS_2: RTC_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS_2_PWRBTNOR_STS_Pos (3UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bit 3) */ +#define PM1_STS_2_PWRBTNOR_STS_Msk (0x8UL) /*!< PM1 STS_2: PWRBTNOR_STS (Bitfield-Mask: 0x01) */ +#define PM1_STS_2_WAK_STS_Pos (7UL) /*!< PM1 STS_2: WAK_STS (Bit 7) */ +#define PM1_STS_2_WAK_STS_Msk (0x80UL) /*!< PM1 STS_2: WAK_STS (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PM1_EN_2 ---------------------------------- */ +#define PM1_EN_2_PWRBTN_EN_Pos (0UL) /*!< PM1 EN_2: PWRBTN_EN (Bit 0) */ +#define PM1_EN_2_PWRBTN_EN_Msk (0x1UL) /*!< PM1 EN_2: PWRBTN_EN (Bitfield-Mask: 0x01) */ +#define PM1_EN_2_SLPBTN_EN_Pos (1UL) /*!< PM1 EN_2: SLPBTN_EN (Bit 1) */ +#define PM1_EN_2_SLPBTN_EN_Msk (0x2UL) /*!< PM1 EN_2: SLPBTN_EN (Bitfield-Mask: 0x01) */ +#define PM1_EN_2_RTC_EN_Pos (2UL) /*!< PM1 EN_2: RTC_EN (Bit 2) */ +#define PM1_EN_2_RTC_EN_Msk (0x4UL) /*!< PM1 EN_2: RTC_EN (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PM1_CTRL_2 --------------------------------- */ +#define PM1_CTRL_2_PWRBTNOR_EN_Pos (1UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bit 1) */ +#define PM1_CTRL_2_PWRBTNOR_EN_Msk (0x2UL) /*!< PM1 CTRL_2: PWRBTNOR_EN (Bitfield-Mask: 0x01) */ +#define PM1_CTRL_2_SLP_TYP_Pos (2UL) /*!< PM1 CTRL_2: SLP_TYP (Bit 2) */ +#define PM1_CTRL_2_SLP_TYP_Msk (0x1cUL) /*!< PM1 CTRL_2: SLP_TYP (Bitfield-Mask: 0x07) */ +#define PM1_CTRL_2_SLP_EN_Pos (5UL) /*!< PM1 CTRL_2: SLP_EN (Bit 5) */ +#define PM1_CTRL_2_SLP_EN_Msk (0x20UL) /*!< PM1 CTRL_2: SLP_EN (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'UART' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- UART_INT_EN -------------------------------- */ +#define UART_INT_EN_ERDAI_Pos (0UL) /*!< UART INT_EN: ERDAI (Bit 0) */ +#define UART_INT_EN_ERDAI_Msk (0x1UL) /*!< UART INT_EN: ERDAI (Bitfield-Mask: 0x01) */ +#define UART_INT_EN_ETHREI_Pos (1UL) /*!< UART INT_EN: ETHREI (Bit 1) */ +#define UART_INT_EN_ETHREI_Msk (0x2UL) /*!< UART INT_EN: ETHREI (Bitfield-Mask: 0x01) */ +#define UART_INT_EN_ELSI_Pos (2UL) /*!< UART INT_EN: ELSI (Bit 2) */ +#define UART_INT_EN_ELSI_Msk (0x4UL) /*!< UART INT_EN: ELSI (Bitfield-Mask: 0x01) */ +#define UART_INT_EN_EMSI_Pos (3UL) /*!< UART INT_EN: EMSI (Bit 3) */ +#define UART_INT_EN_EMSI_Msk (0x8UL) /*!< UART INT_EN: EMSI (Bitfield-Mask: 0x01) */ + +/* -------------------------------- UART_FIFO_CR -------------------------------- */ +#define UART_FIFO_CR_EXRF_Pos (0UL) /*!< UART FIFO_CR: EXRF (Bit 0) */ +#define UART_FIFO_CR_EXRF_Msk (0x1UL) /*!< UART FIFO_CR: EXRF (Bitfield-Mask: 0x01) */ +#define UART_FIFO_CR_CLEAR_RECV_FIFO_Pos (1UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bit 1) */ +#define UART_FIFO_CR_CLEAR_RECV_FIFO_Msk (0x2UL) /*!< UART FIFO_CR: CLEAR_RECV_FIFO (Bitfield-Mask: 0x01) */ +#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Pos (2UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bit 2) */ +#define UART_FIFO_CR_CLEAR_XMIT_FIFO_Msk (0x4UL) /*!< UART FIFO_CR: CLEAR_XMIT_FIFO (Bitfield-Mask: 0x01) */ +#define UART_FIFO_CR_DMA_MODE_SELECT_Pos (3UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bit 3) */ +#define UART_FIFO_CR_DMA_MODE_SELECT_Msk (0x8UL) /*!< UART FIFO_CR: DMA_MODE_SELECT (Bitfield-Mask: 0x01) */ +#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Pos (6UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bit 6) */ +#define UART_FIFO_CR_RECV_FIFO_TRIGGER_LEVEL_Msk (0xc0UL) /*!< UART FIFO_CR: RECV_FIFO_TRIGGER_LEVEL (Bitfield-Mask: 0x03) */ + +/* --------------------------------- UART_INT_ID -------------------------------- */ +#define UART_INT_ID_IPEND_Pos (0UL) /*!< UART INT_ID: IPEND (Bit 0) */ +#define UART_INT_ID_IPEND_Msk (0x1UL) /*!< UART INT_ID: IPEND (Bitfield-Mask: 0x01) */ +#define UART_INT_ID_INTID_Pos (1UL) /*!< UART INT_ID: INTID (Bit 1) */ +#define UART_INT_ID_INTID_Msk (0xeUL) /*!< UART INT_ID: INTID (Bitfield-Mask: 0x07) */ +#define UART_INT_ID_FIFO_EN_Pos (6UL) /*!< UART INT_ID: FIFO_EN (Bit 6) */ +#define UART_INT_ID_FIFO_EN_Msk (0xc0UL) /*!< UART INT_ID: FIFO_EN (Bitfield-Mask: 0x03) */ + +/* -------------------------------- UART_LINE_CR -------------------------------- */ +#define UART_LINE_CR_WORD_LENGTH_Pos (0UL) /*!< UART LINE_CR: WORD_LENGTH (Bit 0) */ +#define UART_LINE_CR_WORD_LENGTH_Msk (0x3UL) /*!< UART LINE_CR: WORD_LENGTH (Bitfield-Mask: 0x03) */ +#define UART_LINE_CR_STOP_BITS_Pos (2UL) /*!< UART LINE_CR: STOP_BITS (Bit 2) */ +#define UART_LINE_CR_STOP_BITS_Msk (0x4UL) /*!< UART LINE_CR: STOP_BITS (Bitfield-Mask: 0x01) */ +#define UART_LINE_CR_ENABLE_PARITY_Pos (3UL) /*!< UART LINE_CR: ENABLE_PARITY (Bit 3) */ +#define UART_LINE_CR_ENABLE_PARITY_Msk (0x8UL) /*!< UART LINE_CR: ENABLE_PARITY (Bitfield-Mask: 0x01) */ +#define UART_LINE_CR_PARITY_SELECT_Pos (4UL) /*!< UART LINE_CR: PARITY_SELECT (Bit 4) */ +#define UART_LINE_CR_PARITY_SELECT_Msk (0x10UL) /*!< UART LINE_CR: PARITY_SELECT (Bitfield-Mask: 0x01) */ +#define UART_LINE_CR_STICK_PARITY_Pos (5UL) /*!< UART LINE_CR: STICK_PARITY (Bit 5) */ +#define UART_LINE_CR_STICK_PARITY_Msk (0x20UL) /*!< UART LINE_CR: STICK_PARITY (Bitfield-Mask: 0x01) */ +#define UART_LINE_CR_BREAK_CONTROL_Pos (6UL) /*!< UART LINE_CR: BREAK_CONTROL (Bit 6) */ +#define UART_LINE_CR_BREAK_CONTROL_Msk (0x40UL) /*!< UART LINE_CR: BREAK_CONTROL (Bitfield-Mask: 0x01) */ +#define UART_LINE_CR_DLAB_Pos (7UL) /*!< UART LINE_CR: DLAB (Bit 7) */ +#define UART_LINE_CR_DLAB_Msk (0x80UL) /*!< UART LINE_CR: DLAB (Bitfield-Mask: 0x01) */ + +/* -------------------------------- UART_MODEM_CR ------------------------------- */ +#define UART_MODEM_CR_DTR_Pos (0UL) /*!< UART MODEM_CR: DTR (Bit 0) */ +#define UART_MODEM_CR_DTR_Msk (0x1UL) /*!< UART MODEM_CR: DTR (Bitfield-Mask: 0x01) */ +#define UART_MODEM_CR_RTS_Pos (1UL) /*!< UART MODEM_CR: RTS (Bit 1) */ +#define UART_MODEM_CR_RTS_Msk (0x2UL) /*!< UART MODEM_CR: RTS (Bitfield-Mask: 0x01) */ +#define UART_MODEM_CR_OUT1_Pos (2UL) /*!< UART MODEM_CR: OUT1 (Bit 2) */ +#define UART_MODEM_CR_OUT1_Msk (0x4UL) /*!< UART MODEM_CR: OUT1 (Bitfield-Mask: 0x01) */ +#define UART_MODEM_CR_OUT2_Pos (3UL) /*!< UART MODEM_CR: OUT2 (Bit 3) */ +#define UART_MODEM_CR_OUT2_Msk (0x8UL) /*!< UART MODEM_CR: OUT2 (Bitfield-Mask: 0x01) */ +#define UART_MODEM_CR_LOOPBACK_Pos (4UL) /*!< UART MODEM_CR: LOOPBACK (Bit 4) */ +#define UART_MODEM_CR_LOOPBACK_Msk (0x10UL) /*!< UART MODEM_CR: LOOPBACK (Bitfield-Mask: 0x01) */ + +/* -------------------------------- UART_LINE_STS ------------------------------- */ +#define UART_LINE_STS_DATA_READY_Pos (0UL) /*!< UART LINE_STS: DATA_READY (Bit 0) */ +#define UART_LINE_STS_DATA_READY_Msk (0x1UL) /*!< UART LINE_STS: DATA_READY (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_OVERRUN_Pos (1UL) /*!< UART LINE_STS: OVERRUN (Bit 1) */ +#define UART_LINE_STS_OVERRUN_Msk (0x2UL) /*!< UART LINE_STS: OVERRUN (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_PE_Pos (2UL) /*!< UART LINE_STS: PE (Bit 2) */ +#define UART_LINE_STS_PE_Msk (0x4UL) /*!< UART LINE_STS: PE (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_FRAME_ERROR_Pos (3UL) /*!< UART LINE_STS: FRAME_ERROR (Bit 3) */ +#define UART_LINE_STS_FRAME_ERROR_Msk (0x8UL) /*!< UART LINE_STS: FRAME_ERROR (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_BREAK_INTERRUPT_Pos (4UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bit 4) */ +#define UART_LINE_STS_BREAK_INTERRUPT_Msk (0x10UL) /*!< UART LINE_STS: BREAK_INTERRUPT (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_TRANSMIT_EMPTY_Pos (5UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bit 5) */ +#define UART_LINE_STS_TRANSMIT_EMPTY_Msk (0x20UL) /*!< UART LINE_STS: TRANSMIT_EMPTY (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_TRANSMIT_ERROR_Pos (6UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bit 6) */ +#define UART_LINE_STS_TRANSMIT_ERROR_Msk (0x40UL) /*!< UART LINE_STS: TRANSMIT_ERROR (Bitfield-Mask: 0x01) */ +#define UART_LINE_STS_FIFO_ERROR_Pos (7UL) /*!< UART LINE_STS: FIFO_ERROR (Bit 7) */ +#define UART_LINE_STS_FIFO_ERROR_Msk (0x80UL) /*!< UART LINE_STS: FIFO_ERROR (Bitfield-Mask: 0x01) */ + +/* ------------------------------- UART_MODEM_STS ------------------------------- */ +#define UART_MODEM_STS_CTS_Pos (0UL) /*!< UART MODEM_STS: CTS (Bit 0) */ +#define UART_MODEM_STS_CTS_Msk (0x1UL) /*!< UART MODEM_STS: CTS (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_DSR_Pos (1UL) /*!< UART MODEM_STS: DSR (Bit 1) */ +#define UART_MODEM_STS_DSR_Msk (0x2UL) /*!< UART MODEM_STS: DSR (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_RI_Pos (2UL) /*!< UART MODEM_STS: RI (Bit 2) */ +#define UART_MODEM_STS_RI_Msk (0x4UL) /*!< UART MODEM_STS: RI (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_DCD_Pos (3UL) /*!< UART MODEM_STS: DCD (Bit 3) */ +#define UART_MODEM_STS_DCD_Msk (0x8UL) /*!< UART MODEM_STS: DCD (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_nCTS_Pos (4UL) /*!< UART MODEM_STS: nCTS (Bit 4) */ +#define UART_MODEM_STS_nCTS_Msk (0x10UL) /*!< UART MODEM_STS: nCTS (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_nDSR_Pos (5UL) /*!< UART MODEM_STS: nDSR (Bit 5) */ +#define UART_MODEM_STS_nDSR_Msk (0x20UL) /*!< UART MODEM_STS: nDSR (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_nRI_Pos (6UL) /*!< UART MODEM_STS: nRI (Bit 6) */ +#define UART_MODEM_STS_nRI_Msk (0x40UL) /*!< UART MODEM_STS: nRI (Bitfield-Mask: 0x01) */ +#define UART_MODEM_STS_nDCD_Pos (7UL) /*!< UART MODEM_STS: nDCD (Bit 7) */ +#define UART_MODEM_STS_nDCD_Msk (0x80UL) /*!< UART MODEM_STS: nDCD (Bitfield-Mask: 0x01) */ + +/* --------------------------------- UART_CONFIG -------------------------------- */ +#define UART_CONFIG_CLK_SRC_Pos (0UL) /*!< UART CONFIG: CLK_SRC (Bit 0) */ +#define UART_CONFIG_CLK_SRC_Msk (0x1UL) /*!< UART CONFIG: CLK_SRC (Bitfield-Mask: 0x01) */ +#define UART_CONFIG_POWER_Pos (1UL) /*!< UART CONFIG: POWER (Bit 1) */ +#define UART_CONFIG_POWER_Msk (0x2UL) /*!< UART CONFIG: POWER (Bitfield-Mask: 0x01) */ +#define UART_CONFIG_POLARITY_Pos (2UL) /*!< UART CONFIG: POLARITY (Bit 2) */ +#define UART_CONFIG_POLARITY_Msk (0x4UL) /*!< UART CONFIG: POLARITY (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'WDT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- WDT_CONTROL -------------------------------- */ +#define WDT_CONTROL_ENABLE_Pos (0UL) /*!< WDT CONTROL: ENABLE (Bit 0) */ +#define WDT_CONTROL_ENABLE_Msk (0x1UL) /*!< WDT CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define WDT_CONTROL_STATUS_Pos (1UL) /*!< WDT CONTROL: STATUS (Bit 1) */ +#define WDT_CONTROL_STATUS_Msk (0x2UL) /*!< WDT CONTROL: STATUS (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER_16_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- TIMER_16_0_CONTROL ----------------------------- */ +#define TIMER_16_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bit 0) */ +#define TIMER_16_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER_16_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER_16_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER_16_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_START_Pos (5UL) /*!< TIMER_16_0 CONTROL: START (Bit 5) */ +#define TIMER_16_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_0 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bit 6) */ +#define TIMER_16_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_0 CONTROL: HALT (Bit 7) */ +#define TIMER_16_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_0 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER_16_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER_16_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER_16_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- TIMER_16_1_CONTROL ----------------------------- */ +#define TIMER_16_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bit 0) */ +#define TIMER_16_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER_16_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER_16_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER_16_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_START_Pos (5UL) /*!< TIMER_16_1 CONTROL: START (Bit 5) */ +#define TIMER_16_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_1 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bit 6) */ +#define TIMER_16_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_1 CONTROL: HALT (Bit 7) */ +#define TIMER_16_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_1 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER_16_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER_16_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER_16_2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- TIMER_16_2_CONTROL ----------------------------- */ +#define TIMER_16_2_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bit 0) */ +#define TIMER_16_2_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_2 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER_16_2_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_2 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER_16_2_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_2 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER_16_2_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_2 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_START_Pos (5UL) /*!< TIMER_16_2 CONTROL: START (Bit 5) */ +#define TIMER_16_2_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_2 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bit 6) */ +#define TIMER_16_2_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_2 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_2 CONTROL: HALT (Bit 7) */ +#define TIMER_16_2_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_2 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER_16_2_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER_16_2_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_2 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER_16_3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- TIMER_16_3_CONTROL ----------------------------- */ +#define TIMER_16_3_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bit 0) */ +#define TIMER_16_3_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_16_3 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER_16_3_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_16_3 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER_16_3_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_16_3 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER_16_3_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_16_3 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_START_Pos (5UL) /*!< TIMER_16_3 CONTROL: START (Bit 5) */ +#define TIMER_16_3_CONTROL_START_Msk (0x20UL) /*!< TIMER_16_3 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bit 6) */ +#define TIMER_16_3_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_16_3 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_HALT_Pos (7UL) /*!< TIMER_16_3 CONTROL: HALT (Bit 7) */ +#define TIMER_16_3_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_16_3 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER_16_3_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER_16_3_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_16_3 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER_32_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- TIMER_32_0_CONTROL ----------------------------- */ +#define TIMER_32_0_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bit 0) */ +#define TIMER_32_0_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_0 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER_32_0_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_0 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER_32_0_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_0 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER_32_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_START_Pos (5UL) /*!< TIMER_32_0 CONTROL: START (Bit 5) */ +#define TIMER_32_0_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_0 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bit 6) */ +#define TIMER_32_0_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_0 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_0 CONTROL: HALT (Bit 7) */ +#define TIMER_32_0_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_0 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER_32_0_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER_32_0_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_0 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'TIMER_32_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------- TIMER_32_1_CONTROL ----------------------------- */ +#define TIMER_32_1_CONTROL_ENABLE_Pos (0UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bit 0) */ +#define TIMER_32_1_CONTROL_ENABLE_Msk (0x1UL) /*!< TIMER_32_1 CONTROL: ENABLE (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_COUNT_UP_Pos (2UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bit 2) */ +#define TIMER_32_1_CONTROL_COUNT_UP_Msk (0x4UL) /*!< TIMER_32_1 CONTROL: COUNT_UP (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_AUTO_RESTART_Pos (3UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bit 3) */ +#define TIMER_32_1_CONTROL_AUTO_RESTART_Msk (0x8UL) /*!< TIMER_32_1 CONTROL: AUTO_RESTART (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bit 4) */ +#define TIMER_32_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< TIMER_32_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_START_Pos (5UL) /*!< TIMER_32_1 CONTROL: START (Bit 5) */ +#define TIMER_32_1_CONTROL_START_Msk (0x20UL) /*!< TIMER_32_1 CONTROL: START (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_RELOAD_Pos (6UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bit 6) */ +#define TIMER_32_1_CONTROL_RELOAD_Msk (0x40UL) /*!< TIMER_32_1 CONTROL: RELOAD (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_HALT_Pos (7UL) /*!< TIMER_32_1 CONTROL: HALT (Bit 7) */ +#define TIMER_32_1_CONTROL_HALT_Msk (0x80UL) /*!< TIMER_32_1 CONTROL: HALT (Bitfield-Mask: 0x01) */ +#define TIMER_32_1_CONTROL_PRE_SCALE_Pos (16UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bit 16) */ +#define TIMER_32_1_CONTROL_PRE_SCALE_Msk (0xffff0000UL) /*!< TIMER_32_1 CONTROL: PRE_SCALE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'RTC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- RTC_CONTROL -------------------------------- */ +#define RTC_CONTROL_BLOCK_ENABLE_Pos (0UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bit 0) */ +#define RTC_CONTROL_BLOCK_ENABLE_Msk (0x1UL) /*!< RTC CONTROL: BLOCK_ENABLE (Bitfield-Mask: 0x01) */ +#define RTC_CONTROL_SOFT_RESET_Pos (1UL) /*!< RTC CONTROL: SOFT_RESET (Bit 1) */ +#define RTC_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< RTC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define RTC_CONTROL_ALARM_ENABLE_Pos (3UL) /*!< RTC CONTROL: ALARM_ENABLE (Bit 3) */ +#define RTC_CONTROL_ALARM_ENABLE_Msk (0x8UL) /*!< RTC CONTROL: ALARM_ENABLE (Bitfield-Mask: 0x01) */ + +/* ------------------------ RTC_DAYLIGHT_SAVINGS_FORWARD ------------------------ */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bit 0) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_MONTH (Bitfield-Mask: 0xff) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bit 8) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bit 16) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bit 24) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_HOUR (Bitfield-Mask: 0x7f) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bit 31) */ +#define RTC_DAYLIGHT_SAVINGS_FORWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_FORWARD: DST_AM_PM (Bitfield-Mask: 0x01) */ + +/* ------------------------ RTC_DAYLIGHT_SAVINGS_BACKWARD ----------------------- */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Pos (0UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bit 0) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_MONTH_Msk (0xffUL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_MONTH (Bitfield-Mask: 0xff) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Pos (8UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bit 8) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_DAY_OF_WEEK_Msk (0x700UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_DAY_OF_WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Pos (16UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bit 16) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_WEEK_Msk (0x70000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_WEEK (Bitfield-Mask: 0x07) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Pos (24UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bit 24) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_HOUR_Msk (0x7f000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_HOUR (Bitfield-Mask: 0x7f) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Pos (31UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bit 31) */ +#define RTC_DAYLIGHT_SAVINGS_BACKWARD_DST_AM_PM_Msk (0x80000000UL) /*!< RTC DAYLIGHT_SAVINGS_BACKWARD: DST_AM_PM (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'GPIO' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ GPIO_PIN_CONTROL ------------------------------ */ +#define GPIO_PIN_CONTROL_PU_PD_Pos (0UL) /*!< GPIO PIN_CONTROL: PU_PD (Bit 0) */ +#define GPIO_PIN_CONTROL_PU_PD_Msk (0x3UL) /*!< GPIO PIN_CONTROL: PU_PD (Bitfield-Mask: 0x03) */ +#define GPIO_PIN_CONTROL_PWR_Pos (2UL) /*!< GPIO PIN_CONTROL: PWR (Bit 2) */ +#define GPIO_PIN_CONTROL_PWR_Msk (0xcUL) /*!< GPIO PIN_CONTROL: PWR (Bitfield-Mask: 0x03) */ +#define GPIO_PIN_CONTROL_INT_DET_Pos (4UL) /*!< GPIO PIN_CONTROL: INT_DET (Bit 4) */ +#define GPIO_PIN_CONTROL_INT_DET_Msk (0x70UL) /*!< GPIO PIN_CONTROL: INT_DET (Bitfield-Mask: 0x07) */ +#define GPIO_PIN_CONTROL_EDGE_EN_Pos (7UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bit 7) */ +#define GPIO_PIN_CONTROL_EDGE_EN_Msk (0x80UL) /*!< GPIO PIN_CONTROL: EDGE_EN (Bitfield-Mask: 0x01) */ +#define GPIO_PIN_CONTROL_BUFFER_Pos (8UL) /*!< GPIO PIN_CONTROL: BUFFER (Bit 8) */ +#define GPIO_PIN_CONTROL_BUFFER_Msk (0x100UL) /*!< GPIO PIN_CONTROL: BUFFER (Bitfield-Mask: 0x01) */ +#define GPIO_PIN_CONTROL_DIR_Pos (9UL) /*!< GPIO PIN_CONTROL: DIR (Bit 9) */ +#define GPIO_PIN_CONTROL_DIR_Msk (0x200UL) /*!< GPIO PIN_CONTROL: DIR (Bitfield-Mask: 0x01) */ +#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Pos (10UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bit 10) */ +#define GPIO_PIN_CONTROL_OUTPUT_WRITE_EN_Msk (0x400UL) /*!< GPIO PIN_CONTROL: OUTPUT_WRITE_EN (Bitfield-Mask: 0x01) */ +#define GPIO_PIN_CONTROL_POLARITY_Pos (11UL) /*!< GPIO PIN_CONTROL: POLARITY (Bit 11) */ +#define GPIO_PIN_CONTROL_POLARITY_Msk (0x800UL) /*!< GPIO PIN_CONTROL: POLARITY (Bitfield-Mask: 0x01) */ +#define GPIO_PIN_CONTROL_MUX_Pos (12UL) /*!< GPIO PIN_CONTROL: MUX (Bit 12) */ +#define GPIO_PIN_CONTROL_MUX_Msk (0x3000UL) /*!< GPIO PIN_CONTROL: MUX (Bitfield-Mask: 0x03) */ +#define GPIO_PIN_CONTROL_OUTPUT_Pos (16UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bit 16) */ +#define GPIO_PIN_CONTROL_OUTPUT_Msk (0x10000UL) /*!< GPIO PIN_CONTROL: OUTPUT (Bitfield-Mask: 0x01) */ +#define GPIO_PIN_CONTROL_INPUT_Pos (24UL) /*!< GPIO PIN_CONTROL: INPUT (Bit 24) */ +#define GPIO_PIN_CONTROL_INPUT_Msk (0x1000000UL) /*!< GPIO PIN_CONTROL: INPUT (Bitfield-Mask: 0x01) */ + +/* ---------------------------- GPIO_CONTROL2_000_067 --------------------------- */ +#define GPIO_CONTROL2_000_067_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bit 0) */ +#define GPIO_CONTROL2_000_067_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_000_067: SLEW_RATE (Bitfield-Mask: 0x01) */ +#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bit 4) */ +#define GPIO_CONTROL2_000_067_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_000_067: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */ + +/* ---------------------------- GPIO_CONTROL2_100_167 --------------------------- */ +#define GPIO_CONTROL2_100_167_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bit 0) */ +#define GPIO_CONTROL2_100_167_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_100_167: SLEW_RATE (Bitfield-Mask: 0x01) */ +#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bit 4) */ +#define GPIO_CONTROL2_100_167_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_100_167: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */ + +/* ---------------------------- GPIO_CONTROL2_200_267 --------------------------- */ +#define GPIO_CONTROL2_200_267_SLEW_RATE_Pos (0UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bit 0) */ +#define GPIO_CONTROL2_200_267_SLEW_RATE_Msk (0x1UL) /*!< GPIO CONTROL2_200_267: SLEW_RATE (Bitfield-Mask: 0x01) */ +#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Pos (4UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bit 4) */ +#define GPIO_CONTROL2_200_267_DRIVE_STRENGTH_Msk (0x30UL) /*!< GPIO CONTROL2_200_267: DRIVE_STRENGTH (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'DMA' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- DMA_CONTROL -------------------------------- */ +#define DMA_CONTROL_ACTIVATE_Pos (0UL) /*!< DMA CONTROL: ACTIVATE (Bit 0) */ +#define DMA_CONTROL_ACTIVATE_Msk (0x1UL) /*!< DMA CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */ +#define DMA_CONTROL_SOFT_RESET_Pos (1UL) /*!< DMA CONTROL: SOFT_RESET (Bit 1) */ +#define DMA_CONTROL_SOFT_RESET_Msk (0x2UL) /*!< DMA CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'CH' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- CH_ACTIVATE -------------------------------- */ +#define CH_ACTIVATE_EN_Pos (0UL) /*!< CH ACTIVATE: EN (Bit 0) */ +#define CH_ACTIVATE_EN_Msk (0x1UL) /*!< CH ACTIVATE: EN (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CH_CONTROL --------------------------------- */ +#define CH_CONTROL_RUN_Pos (0UL) /*!< CH CONTROL: RUN (Bit 0) */ +#define CH_CONTROL_RUN_Msk (0x1UL) /*!< CH CONTROL: RUN (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_REQUEST_Pos (1UL) /*!< CH CONTROL: REQUEST (Bit 1) */ +#define CH_CONTROL_REQUEST_Msk (0x2UL) /*!< CH CONTROL: REQUEST (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_DONE_Pos (2UL) /*!< CH CONTROL: DONE (Bit 2) */ +#define CH_CONTROL_DONE_Msk (0x4UL) /*!< CH CONTROL: DONE (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_STATUS_Pos (3UL) /*!< CH CONTROL: STATUS (Bit 3) */ +#define CH_CONTROL_STATUS_Msk (0x18UL) /*!< CH CONTROL: STATUS (Bitfield-Mask: 0x03) */ +#define CH_CONTROL_BUSY_Pos (5UL) /*!< CH CONTROL: BUSY (Bit 5) */ +#define CH_CONTROL_BUSY_Msk (0x20UL) /*!< CH CONTROL: BUSY (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_TX_DIRECTION_Pos (8UL) /*!< CH CONTROL: TX_DIRECTION (Bit 8) */ +#define CH_CONTROL_TX_DIRECTION_Msk (0x100UL) /*!< CH CONTROL: TX_DIRECTION (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Pos (9UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bit 9) */ +#define CH_CONTROL_HARDWARE_FLOW_CONTROL_DEVICE_Msk (0xfe00UL) /*!< CH CONTROL: HARDWARE_FLOW_CONTROL_DEVICE (Bitfield-Mask: 0x7f) */ +#define CH_CONTROL_INCREMENT_MEM_ADDR_Pos (16UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bit 16) */ +#define CH_CONTROL_INCREMENT_MEM_ADDR_Msk (0x10000UL) /*!< CH CONTROL: INCREMENT_MEM_ADDR (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Pos (17UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bit 17) */ +#define CH_CONTROL_INCREMENT_DEVICE_ADDR_Msk (0x20000UL) /*!< CH CONTROL: INCREMENT_DEVICE_ADDR (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_LOCK_Pos (18UL) /*!< CH CONTROL: LOCK (Bit 18) */ +#define CH_CONTROL_LOCK_Msk (0x40000UL) /*!< CH CONTROL: LOCK (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Pos (19UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bit 19) */ +#define CH_CONTROL_DISABLE_HW_FLOW_CONTROL_Msk (0x80000UL) /*!< CH CONTROL: DISABLE_HW_FLOW_CONTROL (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_TRANSFER_SIZE_Pos (20UL) /*!< CH CONTROL: TRANSFER_SIZE (Bit 20) */ +#define CH_CONTROL_TRANSFER_SIZE_Msk (0x700000UL) /*!< CH CONTROL: TRANSFER_SIZE (Bitfield-Mask: 0x07) */ +#define CH_CONTROL_TRANSFER_GO_Pos (24UL) /*!< CH CONTROL: TRANSFER_GO (Bit 24) */ +#define CH_CONTROL_TRANSFER_GO_Msk (0x1000000UL) /*!< CH CONTROL: TRANSFER_GO (Bitfield-Mask: 0x01) */ +#define CH_CONTROL_TRANSFER_ABORT_Pos (25UL) /*!< CH CONTROL: TRANSFER_ABORT (Bit 25) */ +#define CH_CONTROL_TRANSFER_ABORT_Msk (0x2000000UL) /*!< CH CONTROL: TRANSFER_ABORT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CH_INT_STATUS ------------------------------- */ +#define CH_INT_STATUS_BUS_ERROR_Pos (0UL) /*!< CH INT_STATUS: BUS_ERROR (Bit 0) */ +#define CH_INT_STATUS_BUS_ERROR_Msk (0x1UL) /*!< CH INT_STATUS: BUS_ERROR (Bitfield-Mask: 0x01) */ +#define CH_INT_STATUS_FLOW_CONTROL_Pos (1UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bit 1) */ +#define CH_INT_STATUS_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_STATUS: FLOW_CONTROL (Bitfield-Mask: 0x01) */ +#define CH_INT_STATUS_DONE_Pos (2UL) /*!< CH INT_STATUS: DONE (Bit 2) */ +#define CH_INT_STATUS_DONE_Msk (0x4UL) /*!< CH INT_STATUS: DONE (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CH_INT_EN --------------------------------- */ +#define CH_INT_EN_BUS_ERROR_Pos (0UL) /*!< CH INT_EN: BUS_ERROR (Bit 0) */ +#define CH_INT_EN_BUS_ERROR_Msk (0x1UL) /*!< CH INT_EN: BUS_ERROR (Bitfield-Mask: 0x01) */ +#define CH_INT_EN_FLOW_CONTROL_Pos (1UL) /*!< CH INT_EN: FLOW_CONTROL (Bit 1) */ +#define CH_INT_EN_FLOW_CONTROL_Msk (0x2UL) /*!< CH INT_EN: FLOW_CONTROL (Bitfield-Mask: 0x01) */ +#define CH_INT_EN_DONE_Pos (2UL) /*!< CH INT_EN: DONE (Bit 2) */ +#define CH_INT_EN_DONE_Msk (0x4UL) /*!< CH INT_EN: DONE (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SMB0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- SMB0_CONTROL -------------------------------- */ +#define SMB0_CONTROL_ACK_Pos (0UL) /*!< SMB0 CONTROL: ACK (Bit 0) */ +#define SMB0_CONTROL_ACK_Msk (0x1UL) /*!< SMB0 CONTROL: ACK (Bitfield-Mask: 0x01) */ +#define SMB0_CONTROL_STO_Pos (1UL) /*!< SMB0 CONTROL: STO (Bit 1) */ +#define SMB0_CONTROL_STO_Msk (0x2UL) /*!< SMB0 CONTROL: STO (Bitfield-Mask: 0x01) */ +#define SMB0_CONTROL_STA_Pos (2UL) /*!< SMB0 CONTROL: STA (Bit 2) */ +#define SMB0_CONTROL_STA_Msk (0x4UL) /*!< SMB0 CONTROL: STA (Bitfield-Mask: 0x01) */ +#define SMB0_CONTROL_ENI_Pos (3UL) /*!< SMB0 CONTROL: ENI (Bit 3) */ +#define SMB0_CONTROL_ENI_Msk (0x8UL) /*!< SMB0 CONTROL: ENI (Bitfield-Mask: 0x01) */ +#define SMB0_CONTROL_ESO_Pos (6UL) /*!< SMB0 CONTROL: ESO (Bit 6) */ +#define SMB0_CONTROL_ESO_Msk (0x40UL) /*!< SMB0 CONTROL: ESO (Bitfield-Mask: 0x01) */ +#define SMB0_CONTROL_PIN_Pos (7UL) /*!< SMB0 CONTROL: PIN (Bit 7) */ +#define SMB0_CONTROL_PIN_Msk (0x80UL) /*!< SMB0 CONTROL: PIN (Bitfield-Mask: 0x01) */ + +/* --------------------------------- SMB0_STATUS -------------------------------- */ +#define SMB0_STATUS_nBB_Pos (0UL) /*!< SMB0 STATUS: nBB (Bit 0) */ +#define SMB0_STATUS_nBB_Msk (0x1UL) /*!< SMB0 STATUS: nBB (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_LAB_Pos (1UL) /*!< SMB0 STATUS: LAB (Bit 1) */ +#define SMB0_STATUS_LAB_Msk (0x2UL) /*!< SMB0 STATUS: LAB (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_AAS_Pos (2UL) /*!< SMB0 STATUS: AAS (Bit 2) */ +#define SMB0_STATUS_AAS_Msk (0x4UL) /*!< SMB0 STATUS: AAS (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_LRB_AD0_Pos (3UL) /*!< SMB0 STATUS: LRB_AD0 (Bit 3) */ +#define SMB0_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB0 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_BER_Pos (4UL) /*!< SMB0 STATUS: BER (Bit 4) */ +#define SMB0_STATUS_BER_Msk (0x10UL) /*!< SMB0 STATUS: BER (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_STS_Pos (5UL) /*!< SMB0 STATUS: STS (Bit 5) */ +#define SMB0_STATUS_STS_Msk (0x20UL) /*!< SMB0 STATUS: STS (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_SAD_Pos (6UL) /*!< SMB0 STATUS: SAD (Bit 6) */ +#define SMB0_STATUS_SAD_Msk (0x40UL) /*!< SMB0 STATUS: SAD (Bitfield-Mask: 0x01) */ +#define SMB0_STATUS_PIN_Pos (7UL) /*!< SMB0 STATUS: PIN (Bit 7) */ +#define SMB0_STATUS_PIN_Msk (0x80UL) /*!< SMB0 STATUS: PIN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- SMB0_OWN ---------------------------------- */ +#define SMB0_OWN_ADDRESS_1_Pos (0UL) /*!< SMB0 OWN: ADDRESS_1 (Bit 0) */ +#define SMB0_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB0 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ +#define SMB0_OWN_ADDRESS_2_Pos (8UL) /*!< SMB0 OWN: ADDRESS_2 (Bit 8) */ +#define SMB0_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB0 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ + +/* ----------------------------- SMB0_MASTER_COMMAND ---------------------------- */ +#define SMB0_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bit 0) */ +#define SMB0_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB0 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bit 1) */ +#define SMB0_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB0 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB0 MASTER_COMMAND: START0 (Bit 8) */ +#define SMB0_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB0 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bit 9) */ +#define SMB0_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB0 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB0 MASTER_COMMAND: STOP (Bit 10) */ +#define SMB0_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB0 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bit 11) */ +#define SMB0_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB0 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB0 MASTER_COMMAND: READM (Bit 12) */ +#define SMB0_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB0 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bit 13) */ +#define SMB0_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB0 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ +#define SMB0_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bit 16) */ +#define SMB0_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB0 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB0_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bit 24) */ +#define SMB0_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB0 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ + +/* ----------------------------- SMB0_SLAVE_COMMAND ----------------------------- */ +#define SMB0_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bit 0) */ +#define SMB0_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB0 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ +#define SMB0_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bit 1) */ +#define SMB0_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB0 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ +#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ +#define SMB0_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ +#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ +#define SMB0_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ +#define SMB0_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB0 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ + +/* ------------------------------- SMB0_COMPLETION ------------------------------ */ +#define SMB0_COMPLETION_DTEN_Pos (2UL) /*!< SMB0 COMPLETION: DTEN (Bit 2) */ +#define SMB0_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB0 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_MCEN_Pos (3UL) /*!< SMB0 COMPLETION: MCEN (Bit 3) */ +#define SMB0_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB0 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_SCEN_Pos (4UL) /*!< SMB0 COMPLETION: SCEN (Bit 4) */ +#define SMB0_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB0 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_BIDEN_Pos (5UL) /*!< SMB0 COMPLETION: BIDEN (Bit 5) */ +#define SMB0_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB0 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_TIMERR_Pos (6UL) /*!< SMB0 COMPLETION: TIMERR (Bit 6) */ +#define SMB0_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB0 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_DTO_Pos (8UL) /*!< SMB0 COMPLETION: DTO (Bit 8) */ +#define SMB0_COMPLETION_DTO_Msk (0x100UL) /*!< SMB0 COMPLETION: DTO (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_MCTO_Pos (9UL) /*!< SMB0 COMPLETION: MCTO (Bit 9) */ +#define SMB0_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB0 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_SCTO_Pos (10UL) /*!< SMB0 COMPLETION: SCTO (Bit 10) */ +#define SMB0_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB0 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_CHDL_Pos (11UL) /*!< SMB0 COMPLETION: CHDL (Bit 11) */ +#define SMB0_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB0 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_CHDH_Pos (12UL) /*!< SMB0 COMPLETION: CHDH (Bit 12) */ +#define SMB0_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB0 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_BER_Pos (13UL) /*!< SMB0 COMPLETION: BER (Bit 13) */ +#define SMB0_COMPLETION_BER_Msk (0x2000UL) /*!< SMB0 COMPLETION: BER (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_LAB_Pos (14UL) /*!< SMB0 COMPLETION: LAB (Bit 14) */ +#define SMB0_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB0 COMPLETION: LAB (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_SNAKR_Pos (16UL) /*!< SMB0 COMPLETION: SNAKR (Bit 16) */ +#define SMB0_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB0 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_STR_Pos (17UL) /*!< SMB0 COMPLETION: STR (Bit 17) */ +#define SMB0_COMPLETION_STR_Msk (0x20000UL) /*!< SMB0 COMPLETION: STR (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_SPROT_Pos (19UL) /*!< SMB0 COMPLETION: SPROT (Bit 19) */ +#define SMB0_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB0 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bit 20) */ +#define SMB0_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB0 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bit 21) */ +#define SMB0_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB0 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_MNAKX_Pos (24UL) /*!< SMB0 COMPLETION: MNAKX (Bit 24) */ +#define SMB0_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB0 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_MTR_Pos (25UL) /*!< SMB0 COMPLETION: MTR (Bit 25) */ +#define SMB0_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB0 COMPLETION: MTR (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_IDLE_Pos (29UL) /*!< SMB0 COMPLETION: IDLE (Bit 29) */ +#define SMB0_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB0 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_MDONE_Pos (30UL) /*!< SMB0 COMPLETION: MDONE (Bit 30) */ +#define SMB0_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB0 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ +#define SMB0_COMPLETION_SDONE_Pos (31UL) /*!< SMB0 COMPLETION: SDONE (Bit 31) */ +#define SMB0_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB0 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB0_IDLE_SCALING ----------------------------- */ +#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ +#define SMB0_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB0 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ +#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ +#define SMB0_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB0 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ + +/* ----------------------------- SMB0_CONFIGURATION ----------------------------- */ +#define SMB0_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bit 0) */ +#define SMB0_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB0 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ +#define SMB0_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB0 CONFIGURATION: TCEN (Bit 4) */ +#define SMB0_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB0 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bit 5) */ +#define SMB0_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB0 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB0 CONFIGURATION: PECEN (Bit 7) */ +#define SMB0_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB0 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB0 CONFIGURATION: DFEN (Bit 8) */ +#define SMB0_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB0 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_RESET_Pos (9UL) /*!< SMB0 CONFIGURATION: RESET (Bit 9) */ +#define SMB0_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB0 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB0 CONFIGURATION: ENAB (Bit 10) */ +#define SMB0_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB0 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_DSA_Pos (11UL) /*!< SMB0 CONFIGURATION: DSA (Bit 11) */ +#define SMB0_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB0 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB0 CONFIGURATION: FAIR (Bit 12) */ +#define SMB0_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB0 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bit 14) */ +#define SMB0_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB0 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ +#define SMB0_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB0 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ +#define SMB0_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB0 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ +#define SMB0_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB0 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ +#define SMB0_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB0 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bit 28) */ +#define SMB0_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB0 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB0 CONFIGURATION: ENIDI (Bit 29) */ +#define SMB0_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB0 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB0 CONFIGURATION: ENMI (Bit 30) */ +#define SMB0_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB0 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ +#define SMB0_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB0 CONFIGURATION: ENSI (Bit 31) */ +#define SMB0_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB0 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SMB0_BUS_CLOCK ------------------------------- */ +#define SMB0_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bit 0) */ +#define SMB0_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB0 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ +#define SMB0_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ +#define SMB0_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB0 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB0_BIT_BANG_CONTROL --------------------------- */ +#define SMB0_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bit 0) */ +#define SMB0_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB0 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ +#define SMB0_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bit 1) */ +#define SMB0_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB0 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ +#define SMB0_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bit 2) */ +#define SMB0_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB0 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ +#define SMB0_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bit 3) */ +#define SMB0_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ +#define SMB0_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bit 4) */ +#define SMB0_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB0 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ +#define SMB0_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ +#define SMB0_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB0 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ +#define SMB0_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bit 6) */ +#define SMB0_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB0 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB0_DATA_TIMING ------------------------------ */ +#define SMB0_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bit 0) */ +#define SMB0_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB0 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ +#define SMB0_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bit 8) */ +#define SMB0_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB0 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ +#define SMB0_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bit 16) */ +#define SMB0_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB0 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ +#define SMB0_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bit 24) */ +#define SMB0_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB0 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB0_TIME_OUT_SCALING --------------------------- */ +#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ +#define SMB0_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB0 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ +#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ +#define SMB0_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB0 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ +#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ +#define SMB0_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB0 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ +#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ +#define SMB0_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB0 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'SMB1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SMB1_STATUS -------------------------------- */ +#define SMB1_STATUS_nBB_Pos (0UL) /*!< SMB1 STATUS: nBB (Bit 0) */ +#define SMB1_STATUS_nBB_Msk (0x1UL) /*!< SMB1 STATUS: nBB (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_LAB_Pos (1UL) /*!< SMB1 STATUS: LAB (Bit 1) */ +#define SMB1_STATUS_LAB_Msk (0x2UL) /*!< SMB1 STATUS: LAB (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_AAS_Pos (2UL) /*!< SMB1 STATUS: AAS (Bit 2) */ +#define SMB1_STATUS_AAS_Msk (0x4UL) /*!< SMB1 STATUS: AAS (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_LRB_AD0_Pos (3UL) /*!< SMB1 STATUS: LRB_AD0 (Bit 3) */ +#define SMB1_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB1 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_BER_Pos (4UL) /*!< SMB1 STATUS: BER (Bit 4) */ +#define SMB1_STATUS_BER_Msk (0x10UL) /*!< SMB1 STATUS: BER (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_STS_Pos (5UL) /*!< SMB1 STATUS: STS (Bit 5) */ +#define SMB1_STATUS_STS_Msk (0x20UL) /*!< SMB1 STATUS: STS (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_SAD_Pos (6UL) /*!< SMB1 STATUS: SAD (Bit 6) */ +#define SMB1_STATUS_SAD_Msk (0x40UL) /*!< SMB1 STATUS: SAD (Bitfield-Mask: 0x01) */ +#define SMB1_STATUS_PIN_Pos (7UL) /*!< SMB1 STATUS: PIN (Bit 7) */ +#define SMB1_STATUS_PIN_Msk (0x80UL) /*!< SMB1 STATUS: PIN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- SMB1_CONTROL -------------------------------- */ +#define SMB1_CONTROL_ACK_Pos (0UL) /*!< SMB1 CONTROL: ACK (Bit 0) */ +#define SMB1_CONTROL_ACK_Msk (0x1UL) /*!< SMB1 CONTROL: ACK (Bitfield-Mask: 0x01) */ +#define SMB1_CONTROL_STO_Pos (1UL) /*!< SMB1 CONTROL: STO (Bit 1) */ +#define SMB1_CONTROL_STO_Msk (0x2UL) /*!< SMB1 CONTROL: STO (Bitfield-Mask: 0x01) */ +#define SMB1_CONTROL_STA_Pos (2UL) /*!< SMB1 CONTROL: STA (Bit 2) */ +#define SMB1_CONTROL_STA_Msk (0x4UL) /*!< SMB1 CONTROL: STA (Bitfield-Mask: 0x01) */ +#define SMB1_CONTROL_ENI_Pos (3UL) /*!< SMB1 CONTROL: ENI (Bit 3) */ +#define SMB1_CONTROL_ENI_Msk (0x8UL) /*!< SMB1 CONTROL: ENI (Bitfield-Mask: 0x01) */ +#define SMB1_CONTROL_ESO_Pos (6UL) /*!< SMB1 CONTROL: ESO (Bit 6) */ +#define SMB1_CONTROL_ESO_Msk (0x40UL) /*!< SMB1 CONTROL: ESO (Bitfield-Mask: 0x01) */ +#define SMB1_CONTROL_PIN_Pos (7UL) /*!< SMB1 CONTROL: PIN (Bit 7) */ +#define SMB1_CONTROL_PIN_Msk (0x80UL) /*!< SMB1 CONTROL: PIN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- SMB1_OWN ---------------------------------- */ +#define SMB1_OWN_ADDRESS_1_Pos (0UL) /*!< SMB1 OWN: ADDRESS_1 (Bit 0) */ +#define SMB1_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB1 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ +#define SMB1_OWN_ADDRESS_2_Pos (8UL) /*!< SMB1 OWN: ADDRESS_2 (Bit 8) */ +#define SMB1_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB1 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ + +/* ----------------------------- SMB1_MASTER_COMMAND ---------------------------- */ +#define SMB1_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bit 0) */ +#define SMB1_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB1 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bit 1) */ +#define SMB1_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB1 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB1 MASTER_COMMAND: START0 (Bit 8) */ +#define SMB1_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB1 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bit 9) */ +#define SMB1_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB1 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB1 MASTER_COMMAND: STOP (Bit 10) */ +#define SMB1_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB1 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bit 11) */ +#define SMB1_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB1 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB1 MASTER_COMMAND: READM (Bit 12) */ +#define SMB1_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB1 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bit 13) */ +#define SMB1_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB1 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ +#define SMB1_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bit 16) */ +#define SMB1_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB1 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB1_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bit 24) */ +#define SMB1_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB1 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ + +/* ----------------------------- SMB1_SLAVE_COMMAND ----------------------------- */ +#define SMB1_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bit 0) */ +#define SMB1_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB1 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ +#define SMB1_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bit 1) */ +#define SMB1_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB1 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ +#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ +#define SMB1_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ +#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ +#define SMB1_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ +#define SMB1_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB1 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ + +/* ------------------------------- SMB1_COMPLETION ------------------------------ */ +#define SMB1_COMPLETION_DTEN_Pos (2UL) /*!< SMB1 COMPLETION: DTEN (Bit 2) */ +#define SMB1_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB1 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_MCEN_Pos (3UL) /*!< SMB1 COMPLETION: MCEN (Bit 3) */ +#define SMB1_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB1 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_SCEN_Pos (4UL) /*!< SMB1 COMPLETION: SCEN (Bit 4) */ +#define SMB1_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB1 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_BIDEN_Pos (5UL) /*!< SMB1 COMPLETION: BIDEN (Bit 5) */ +#define SMB1_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB1 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_TIMERR_Pos (6UL) /*!< SMB1 COMPLETION: TIMERR (Bit 6) */ +#define SMB1_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB1 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_DTO_Pos (8UL) /*!< SMB1 COMPLETION: DTO (Bit 8) */ +#define SMB1_COMPLETION_DTO_Msk (0x100UL) /*!< SMB1 COMPLETION: DTO (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_MCTO_Pos (9UL) /*!< SMB1 COMPLETION: MCTO (Bit 9) */ +#define SMB1_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB1 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_SCTO_Pos (10UL) /*!< SMB1 COMPLETION: SCTO (Bit 10) */ +#define SMB1_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB1 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_CHDL_Pos (11UL) /*!< SMB1 COMPLETION: CHDL (Bit 11) */ +#define SMB1_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB1 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_CHDH_Pos (12UL) /*!< SMB1 COMPLETION: CHDH (Bit 12) */ +#define SMB1_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB1 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_BER_Pos (13UL) /*!< SMB1 COMPLETION: BER (Bit 13) */ +#define SMB1_COMPLETION_BER_Msk (0x2000UL) /*!< SMB1 COMPLETION: BER (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_LAB_Pos (14UL) /*!< SMB1 COMPLETION: LAB (Bit 14) */ +#define SMB1_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB1 COMPLETION: LAB (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_SNAKR_Pos (16UL) /*!< SMB1 COMPLETION: SNAKR (Bit 16) */ +#define SMB1_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB1 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_STR_Pos (17UL) /*!< SMB1 COMPLETION: STR (Bit 17) */ +#define SMB1_COMPLETION_STR_Msk (0x20000UL) /*!< SMB1 COMPLETION: STR (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_SPROT_Pos (19UL) /*!< SMB1 COMPLETION: SPROT (Bit 19) */ +#define SMB1_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB1 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bit 20) */ +#define SMB1_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB1 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bit 21) */ +#define SMB1_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB1 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_MNAKX_Pos (24UL) /*!< SMB1 COMPLETION: MNAKX (Bit 24) */ +#define SMB1_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB1 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_MTR_Pos (25UL) /*!< SMB1 COMPLETION: MTR (Bit 25) */ +#define SMB1_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB1 COMPLETION: MTR (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_IDLE_Pos (29UL) /*!< SMB1 COMPLETION: IDLE (Bit 29) */ +#define SMB1_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB1 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_MDONE_Pos (30UL) /*!< SMB1 COMPLETION: MDONE (Bit 30) */ +#define SMB1_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB1 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ +#define SMB1_COMPLETION_SDONE_Pos (31UL) /*!< SMB1 COMPLETION: SDONE (Bit 31) */ +#define SMB1_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB1 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB1_IDLE_SCALING ----------------------------- */ +#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ +#define SMB1_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB1 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ +#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ +#define SMB1_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB1 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ + +/* ----------------------------- SMB1_CONFIGURATION ----------------------------- */ +#define SMB1_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bit 0) */ +#define SMB1_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB1 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ +#define SMB1_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB1 CONFIGURATION: TCEN (Bit 4) */ +#define SMB1_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB1 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bit 5) */ +#define SMB1_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB1 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB1 CONFIGURATION: PECEN (Bit 7) */ +#define SMB1_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB1 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB1 CONFIGURATION: DFEN (Bit 8) */ +#define SMB1_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB1 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_RESET_Pos (9UL) /*!< SMB1 CONFIGURATION: RESET (Bit 9) */ +#define SMB1_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB1 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB1 CONFIGURATION: ENAB (Bit 10) */ +#define SMB1_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB1 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_DSA_Pos (11UL) /*!< SMB1 CONFIGURATION: DSA (Bit 11) */ +#define SMB1_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB1 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB1 CONFIGURATION: FAIR (Bit 12) */ +#define SMB1_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB1 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bit 14) */ +#define SMB1_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB1 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ +#define SMB1_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB1 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ +#define SMB1_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB1 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ +#define SMB1_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB1 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ +#define SMB1_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB1 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bit 28) */ +#define SMB1_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB1 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB1 CONFIGURATION: ENIDI (Bit 29) */ +#define SMB1_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB1 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB1 CONFIGURATION: ENMI (Bit 30) */ +#define SMB1_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB1 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ +#define SMB1_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB1 CONFIGURATION: ENSI (Bit 31) */ +#define SMB1_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB1 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SMB1_BUS_CLOCK ------------------------------- */ +#define SMB1_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bit 0) */ +#define SMB1_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB1 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ +#define SMB1_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ +#define SMB1_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB1 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB1_BIT_BANG_CONTROL --------------------------- */ +#define SMB1_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bit 0) */ +#define SMB1_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB1 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ +#define SMB1_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bit 1) */ +#define SMB1_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB1 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ +#define SMB1_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bit 2) */ +#define SMB1_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB1 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ +#define SMB1_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bit 3) */ +#define SMB1_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ +#define SMB1_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bit 4) */ +#define SMB1_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB1 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ +#define SMB1_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ +#define SMB1_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB1 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ +#define SMB1_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bit 6) */ +#define SMB1_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB1 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB1_DATA_TIMING ------------------------------ */ +#define SMB1_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bit 0) */ +#define SMB1_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB1 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ +#define SMB1_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bit 8) */ +#define SMB1_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB1 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ +#define SMB1_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bit 16) */ +#define SMB1_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB1 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ +#define SMB1_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bit 24) */ +#define SMB1_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB1 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB1_TIME_OUT_SCALING --------------------------- */ +#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ +#define SMB1_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB1 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ +#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ +#define SMB1_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB1 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ +#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ +#define SMB1_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB1 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ +#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ +#define SMB1_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB1 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'SMB2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SMB2_STATUS -------------------------------- */ +#define SMB2_STATUS_nBB_Pos (0UL) /*!< SMB2 STATUS: nBB (Bit 0) */ +#define SMB2_STATUS_nBB_Msk (0x1UL) /*!< SMB2 STATUS: nBB (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_LAB_Pos (1UL) /*!< SMB2 STATUS: LAB (Bit 1) */ +#define SMB2_STATUS_LAB_Msk (0x2UL) /*!< SMB2 STATUS: LAB (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_AAS_Pos (2UL) /*!< SMB2 STATUS: AAS (Bit 2) */ +#define SMB2_STATUS_AAS_Msk (0x4UL) /*!< SMB2 STATUS: AAS (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_LRB_AD0_Pos (3UL) /*!< SMB2 STATUS: LRB_AD0 (Bit 3) */ +#define SMB2_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB2 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_BER_Pos (4UL) /*!< SMB2 STATUS: BER (Bit 4) */ +#define SMB2_STATUS_BER_Msk (0x10UL) /*!< SMB2 STATUS: BER (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_STS_Pos (5UL) /*!< SMB2 STATUS: STS (Bit 5) */ +#define SMB2_STATUS_STS_Msk (0x20UL) /*!< SMB2 STATUS: STS (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_SAD_Pos (6UL) /*!< SMB2 STATUS: SAD (Bit 6) */ +#define SMB2_STATUS_SAD_Msk (0x40UL) /*!< SMB2 STATUS: SAD (Bitfield-Mask: 0x01) */ +#define SMB2_STATUS_PIN_Pos (7UL) /*!< SMB2 STATUS: PIN (Bit 7) */ +#define SMB2_STATUS_PIN_Msk (0x80UL) /*!< SMB2 STATUS: PIN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- SMB2_CONTROL -------------------------------- */ +#define SMB2_CONTROL_ACK_Pos (0UL) /*!< SMB2 CONTROL: ACK (Bit 0) */ +#define SMB2_CONTROL_ACK_Msk (0x1UL) /*!< SMB2 CONTROL: ACK (Bitfield-Mask: 0x01) */ +#define SMB2_CONTROL_STO_Pos (1UL) /*!< SMB2 CONTROL: STO (Bit 1) */ +#define SMB2_CONTROL_STO_Msk (0x2UL) /*!< SMB2 CONTROL: STO (Bitfield-Mask: 0x01) */ +#define SMB2_CONTROL_STA_Pos (2UL) /*!< SMB2 CONTROL: STA (Bit 2) */ +#define SMB2_CONTROL_STA_Msk (0x4UL) /*!< SMB2 CONTROL: STA (Bitfield-Mask: 0x01) */ +#define SMB2_CONTROL_ENI_Pos (3UL) /*!< SMB2 CONTROL: ENI (Bit 3) */ +#define SMB2_CONTROL_ENI_Msk (0x8UL) /*!< SMB2 CONTROL: ENI (Bitfield-Mask: 0x01) */ +#define SMB2_CONTROL_ESO_Pos (6UL) /*!< SMB2 CONTROL: ESO (Bit 6) */ +#define SMB2_CONTROL_ESO_Msk (0x40UL) /*!< SMB2 CONTROL: ESO (Bitfield-Mask: 0x01) */ +#define SMB2_CONTROL_PIN_Pos (7UL) /*!< SMB2 CONTROL: PIN (Bit 7) */ +#define SMB2_CONTROL_PIN_Msk (0x80UL) /*!< SMB2 CONTROL: PIN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- SMB2_OWN ---------------------------------- */ +#define SMB2_OWN_ADDRESS_1_Pos (0UL) /*!< SMB2 OWN: ADDRESS_1 (Bit 0) */ +#define SMB2_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB2 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ +#define SMB2_OWN_ADDRESS_2_Pos (8UL) /*!< SMB2 OWN: ADDRESS_2 (Bit 8) */ +#define SMB2_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB2 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ + +/* ----------------------------- SMB2_MASTER_COMMAND ---------------------------- */ +#define SMB2_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bit 0) */ +#define SMB2_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB2 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bit 1) */ +#define SMB2_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB2 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB2 MASTER_COMMAND: START0 (Bit 8) */ +#define SMB2_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB2 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bit 9) */ +#define SMB2_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB2 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB2 MASTER_COMMAND: STOP (Bit 10) */ +#define SMB2_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB2 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bit 11) */ +#define SMB2_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB2 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB2 MASTER_COMMAND: READM (Bit 12) */ +#define SMB2_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB2 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bit 13) */ +#define SMB2_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB2 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ +#define SMB2_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bit 16) */ +#define SMB2_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB2 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB2_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bit 24) */ +#define SMB2_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB2 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ + +/* ----------------------------- SMB2_SLAVE_COMMAND ----------------------------- */ +#define SMB2_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bit 0) */ +#define SMB2_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB2 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ +#define SMB2_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bit 1) */ +#define SMB2_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB2 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ +#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ +#define SMB2_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ +#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ +#define SMB2_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ +#define SMB2_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB2 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ + +/* ------------------------------- SMB2_COMPLETION ------------------------------ */ +#define SMB2_COMPLETION_DTEN_Pos (2UL) /*!< SMB2 COMPLETION: DTEN (Bit 2) */ +#define SMB2_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB2 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_MCEN_Pos (3UL) /*!< SMB2 COMPLETION: MCEN (Bit 3) */ +#define SMB2_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB2 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_SCEN_Pos (4UL) /*!< SMB2 COMPLETION: SCEN (Bit 4) */ +#define SMB2_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB2 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_BIDEN_Pos (5UL) /*!< SMB2 COMPLETION: BIDEN (Bit 5) */ +#define SMB2_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB2 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_TIMERR_Pos (6UL) /*!< SMB2 COMPLETION: TIMERR (Bit 6) */ +#define SMB2_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB2 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_DTO_Pos (8UL) /*!< SMB2 COMPLETION: DTO (Bit 8) */ +#define SMB2_COMPLETION_DTO_Msk (0x100UL) /*!< SMB2 COMPLETION: DTO (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_MCTO_Pos (9UL) /*!< SMB2 COMPLETION: MCTO (Bit 9) */ +#define SMB2_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB2 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_SCTO_Pos (10UL) /*!< SMB2 COMPLETION: SCTO (Bit 10) */ +#define SMB2_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB2 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_CHDL_Pos (11UL) /*!< SMB2 COMPLETION: CHDL (Bit 11) */ +#define SMB2_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB2 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_CHDH_Pos (12UL) /*!< SMB2 COMPLETION: CHDH (Bit 12) */ +#define SMB2_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB2 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_BER_Pos (13UL) /*!< SMB2 COMPLETION: BER (Bit 13) */ +#define SMB2_COMPLETION_BER_Msk (0x2000UL) /*!< SMB2 COMPLETION: BER (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_LAB_Pos (14UL) /*!< SMB2 COMPLETION: LAB (Bit 14) */ +#define SMB2_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB2 COMPLETION: LAB (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_SNAKR_Pos (16UL) /*!< SMB2 COMPLETION: SNAKR (Bit 16) */ +#define SMB2_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB2 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_STR_Pos (17UL) /*!< SMB2 COMPLETION: STR (Bit 17) */ +#define SMB2_COMPLETION_STR_Msk (0x20000UL) /*!< SMB2 COMPLETION: STR (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_SPROT_Pos (19UL) /*!< SMB2 COMPLETION: SPROT (Bit 19) */ +#define SMB2_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB2 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bit 20) */ +#define SMB2_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB2 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bit 21) */ +#define SMB2_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB2 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_MNAKX_Pos (24UL) /*!< SMB2 COMPLETION: MNAKX (Bit 24) */ +#define SMB2_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB2 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_MTR_Pos (25UL) /*!< SMB2 COMPLETION: MTR (Bit 25) */ +#define SMB2_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB2 COMPLETION: MTR (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_IDLE_Pos (29UL) /*!< SMB2 COMPLETION: IDLE (Bit 29) */ +#define SMB2_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB2 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_MDONE_Pos (30UL) /*!< SMB2 COMPLETION: MDONE (Bit 30) */ +#define SMB2_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB2 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ +#define SMB2_COMPLETION_SDONE_Pos (31UL) /*!< SMB2 COMPLETION: SDONE (Bit 31) */ +#define SMB2_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB2 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB2_IDLE_SCALING ----------------------------- */ +#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ +#define SMB2_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB2 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ +#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ +#define SMB2_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB2 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ + +/* ----------------------------- SMB2_CONFIGURATION ----------------------------- */ +#define SMB2_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bit 0) */ +#define SMB2_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB2 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ +#define SMB2_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB2 CONFIGURATION: TCEN (Bit 4) */ +#define SMB2_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB2 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bit 5) */ +#define SMB2_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB2 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB2 CONFIGURATION: PECEN (Bit 7) */ +#define SMB2_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB2 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB2 CONFIGURATION: DFEN (Bit 8) */ +#define SMB2_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB2 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_RESET_Pos (9UL) /*!< SMB2 CONFIGURATION: RESET (Bit 9) */ +#define SMB2_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB2 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB2 CONFIGURATION: ENAB (Bit 10) */ +#define SMB2_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB2 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_DSA_Pos (11UL) /*!< SMB2 CONFIGURATION: DSA (Bit 11) */ +#define SMB2_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB2 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB2 CONFIGURATION: FAIR (Bit 12) */ +#define SMB2_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB2 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bit 14) */ +#define SMB2_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB2 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ +#define SMB2_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB2 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ +#define SMB2_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB2 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ +#define SMB2_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB2 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ +#define SMB2_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB2 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bit 28) */ +#define SMB2_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB2 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB2 CONFIGURATION: ENIDI (Bit 29) */ +#define SMB2_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB2 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB2 CONFIGURATION: ENMI (Bit 30) */ +#define SMB2_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB2 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ +#define SMB2_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB2 CONFIGURATION: ENSI (Bit 31) */ +#define SMB2_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB2 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SMB2_BUS_CLOCK ------------------------------- */ +#define SMB2_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bit 0) */ +#define SMB2_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB2 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ +#define SMB2_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ +#define SMB2_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB2 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB2_BIT_BANG_CONTROL --------------------------- */ +#define SMB2_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bit 0) */ +#define SMB2_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB2 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ +#define SMB2_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bit 1) */ +#define SMB2_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB2 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ +#define SMB2_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bit 2) */ +#define SMB2_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB2 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ +#define SMB2_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bit 3) */ +#define SMB2_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ +#define SMB2_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bit 4) */ +#define SMB2_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB2 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ +#define SMB2_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ +#define SMB2_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB2 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ +#define SMB2_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bit 6) */ +#define SMB2_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB2 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB2_DATA_TIMING ------------------------------ */ +#define SMB2_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bit 0) */ +#define SMB2_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB2 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ +#define SMB2_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bit 8) */ +#define SMB2_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB2 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ +#define SMB2_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bit 16) */ +#define SMB2_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB2 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ +#define SMB2_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bit 24) */ +#define SMB2_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB2 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB2_TIME_OUT_SCALING --------------------------- */ +#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ +#define SMB2_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB2 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ +#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ +#define SMB2_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB2 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ +#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ +#define SMB2_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB2 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ +#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ +#define SMB2_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB2 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'SMB3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- SMB3_STATUS -------------------------------- */ +#define SMB3_STATUS_nBB_Pos (0UL) /*!< SMB3 STATUS: nBB (Bit 0) */ +#define SMB3_STATUS_nBB_Msk (0x1UL) /*!< SMB3 STATUS: nBB (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_LAB_Pos (1UL) /*!< SMB3 STATUS: LAB (Bit 1) */ +#define SMB3_STATUS_LAB_Msk (0x2UL) /*!< SMB3 STATUS: LAB (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_AAS_Pos (2UL) /*!< SMB3 STATUS: AAS (Bit 2) */ +#define SMB3_STATUS_AAS_Msk (0x4UL) /*!< SMB3 STATUS: AAS (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_LRB_AD0_Pos (3UL) /*!< SMB3 STATUS: LRB_AD0 (Bit 3) */ +#define SMB3_STATUS_LRB_AD0_Msk (0x8UL) /*!< SMB3 STATUS: LRB_AD0 (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_BER_Pos (4UL) /*!< SMB3 STATUS: BER (Bit 4) */ +#define SMB3_STATUS_BER_Msk (0x10UL) /*!< SMB3 STATUS: BER (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_STS_Pos (5UL) /*!< SMB3 STATUS: STS (Bit 5) */ +#define SMB3_STATUS_STS_Msk (0x20UL) /*!< SMB3 STATUS: STS (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_SAD_Pos (6UL) /*!< SMB3 STATUS: SAD (Bit 6) */ +#define SMB3_STATUS_SAD_Msk (0x40UL) /*!< SMB3 STATUS: SAD (Bitfield-Mask: 0x01) */ +#define SMB3_STATUS_PIN_Pos (7UL) /*!< SMB3 STATUS: PIN (Bit 7) */ +#define SMB3_STATUS_PIN_Msk (0x80UL) /*!< SMB3 STATUS: PIN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- SMB3_CONTROL -------------------------------- */ +#define SMB3_CONTROL_ACK_Pos (0UL) /*!< SMB3 CONTROL: ACK (Bit 0) */ +#define SMB3_CONTROL_ACK_Msk (0x1UL) /*!< SMB3 CONTROL: ACK (Bitfield-Mask: 0x01) */ +#define SMB3_CONTROL_STO_Pos (1UL) /*!< SMB3 CONTROL: STO (Bit 1) */ +#define SMB3_CONTROL_STO_Msk (0x2UL) /*!< SMB3 CONTROL: STO (Bitfield-Mask: 0x01) */ +#define SMB3_CONTROL_STA_Pos (2UL) /*!< SMB3 CONTROL: STA (Bit 2) */ +#define SMB3_CONTROL_STA_Msk (0x4UL) /*!< SMB3 CONTROL: STA (Bitfield-Mask: 0x01) */ +#define SMB3_CONTROL_ENI_Pos (3UL) /*!< SMB3 CONTROL: ENI (Bit 3) */ +#define SMB3_CONTROL_ENI_Msk (0x8UL) /*!< SMB3 CONTROL: ENI (Bitfield-Mask: 0x01) */ +#define SMB3_CONTROL_ESO_Pos (6UL) /*!< SMB3 CONTROL: ESO (Bit 6) */ +#define SMB3_CONTROL_ESO_Msk (0x40UL) /*!< SMB3 CONTROL: ESO (Bitfield-Mask: 0x01) */ +#define SMB3_CONTROL_PIN_Pos (7UL) /*!< SMB3 CONTROL: PIN (Bit 7) */ +#define SMB3_CONTROL_PIN_Msk (0x80UL) /*!< SMB3 CONTROL: PIN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- SMB3_OWN ---------------------------------- */ +#define SMB3_OWN_ADDRESS_1_Pos (0UL) /*!< SMB3 OWN: ADDRESS_1 (Bit 0) */ +#define SMB3_OWN_ADDRESS_1_Msk (0x7fUL) /*!< SMB3 OWN: ADDRESS_1 (Bitfield-Mask: 0x7f) */ +#define SMB3_OWN_ADDRESS_2_Pos (8UL) /*!< SMB3 OWN: ADDRESS_2 (Bit 8) */ +#define SMB3_OWN_ADDRESS_2_Msk (0x7f00UL) /*!< SMB3 OWN: ADDRESS_2 (Bitfield-Mask: 0x7f) */ + +/* ----------------------------- SMB3_MASTER_COMMAND ---------------------------- */ +#define SMB3_MASTER_COMMAND_MRUN_Pos (0UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bit 0) */ +#define SMB3_MASTER_COMMAND_MRUN_Msk (0x1UL) /*!< SMB3 MASTER_COMMAND: MRUN (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_MPROCEED_Pos (1UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bit 1) */ +#define SMB3_MASTER_COMMAND_MPROCEED_Msk (0x2UL) /*!< SMB3 MASTER_COMMAND: MPROCEED (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_START0_Pos (8UL) /*!< SMB3 MASTER_COMMAND: START0 (Bit 8) */ +#define SMB3_MASTER_COMMAND_START0_Msk (0x100UL) /*!< SMB3 MASTER_COMMAND: START0 (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_STARTN_Pos (9UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bit 9) */ +#define SMB3_MASTER_COMMAND_STARTN_Msk (0x200UL) /*!< SMB3 MASTER_COMMAND: STARTN (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_STOP_Pos (10UL) /*!< SMB3 MASTER_COMMAND: STOP (Bit 10) */ +#define SMB3_MASTER_COMMAND_STOP_Msk (0x400UL) /*!< SMB3 MASTER_COMMAND: STOP (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_PEC_TERM_Pos (11UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bit 11) */ +#define SMB3_MASTER_COMMAND_PEC_TERM_Msk (0x800UL) /*!< SMB3 MASTER_COMMAND: PEC_TERM (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_READM_Pos (12UL) /*!< SMB3 MASTER_COMMAND: READM (Bit 12) */ +#define SMB3_MASTER_COMMAND_READM_Msk (0x1000UL) /*!< SMB3 MASTER_COMMAND: READM (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_READ_PEC_Pos (13UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bit 13) */ +#define SMB3_MASTER_COMMAND_READ_PEC_Msk (0x2000UL) /*!< SMB3 MASTER_COMMAND: READ_PEC (Bitfield-Mask: 0x01) */ +#define SMB3_MASTER_COMMAND_WRITECOUNT_Pos (16UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bit 16) */ +#define SMB3_MASTER_COMMAND_WRITECOUNT_Msk (0xff0000UL) /*!< SMB3 MASTER_COMMAND: WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB3_MASTER_COMMAND_READCOUNT_Pos (24UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bit 24) */ +#define SMB3_MASTER_COMMAND_READCOUNT_Msk (0xff000000UL) /*!< SMB3 MASTER_COMMAND: READCOUNT (Bitfield-Mask: 0xff) */ + +/* ----------------------------- SMB3_SLAVE_COMMAND ----------------------------- */ +#define SMB3_SLAVE_COMMAND_SRUN_Pos (0UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bit 0) */ +#define SMB3_SLAVE_COMMAND_SRUN_Msk (0x1UL) /*!< SMB3 SLAVE_COMMAND: SRUN (Bitfield-Mask: 0x01) */ +#define SMB3_SLAVE_COMMAND_SPROCEED_Pos (1UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bit 1) */ +#define SMB3_SLAVE_COMMAND_SPROCEED_Msk (0x2UL) /*!< SMB3 SLAVE_COMMAND: SPROCEED (Bitfield-Mask: 0x01) */ +#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Pos (2UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bit 2) */ +#define SMB3_SLAVE_COMMAND_SLAVE_PEC_Msk (0x4UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_PEC (Bitfield-Mask: 0x01) */ +#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Pos (8UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bit 8) */ +#define SMB3_SLAVE_COMMAND_SLAVE_WRITECOUNT_Msk (0xff00UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_WRITECOUNT (Bitfield-Mask: 0xff) */ +#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Pos (16UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bit 16) */ +#define SMB3_SLAVE_COMMAND_SLAVE_READCOUNT_Msk (0xff0000UL) /*!< SMB3 SLAVE_COMMAND: SLAVE_READCOUNT (Bitfield-Mask: 0xff) */ + +/* ------------------------------- SMB3_COMPLETION ------------------------------ */ +#define SMB3_COMPLETION_DTEN_Pos (2UL) /*!< SMB3 COMPLETION: DTEN (Bit 2) */ +#define SMB3_COMPLETION_DTEN_Msk (0x4UL) /*!< SMB3 COMPLETION: DTEN (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_MCEN_Pos (3UL) /*!< SMB3 COMPLETION: MCEN (Bit 3) */ +#define SMB3_COMPLETION_MCEN_Msk (0x8UL) /*!< SMB3 COMPLETION: MCEN (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_SCEN_Pos (4UL) /*!< SMB3 COMPLETION: SCEN (Bit 4) */ +#define SMB3_COMPLETION_SCEN_Msk (0x10UL) /*!< SMB3 COMPLETION: SCEN (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_BIDEN_Pos (5UL) /*!< SMB3 COMPLETION: BIDEN (Bit 5) */ +#define SMB3_COMPLETION_BIDEN_Msk (0x20UL) /*!< SMB3 COMPLETION: BIDEN (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_TIMERR_Pos (6UL) /*!< SMB3 COMPLETION: TIMERR (Bit 6) */ +#define SMB3_COMPLETION_TIMERR_Msk (0x40UL) /*!< SMB3 COMPLETION: TIMERR (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_DTO_Pos (8UL) /*!< SMB3 COMPLETION: DTO (Bit 8) */ +#define SMB3_COMPLETION_DTO_Msk (0x100UL) /*!< SMB3 COMPLETION: DTO (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_MCTO_Pos (9UL) /*!< SMB3 COMPLETION: MCTO (Bit 9) */ +#define SMB3_COMPLETION_MCTO_Msk (0x200UL) /*!< SMB3 COMPLETION: MCTO (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_SCTO_Pos (10UL) /*!< SMB3 COMPLETION: SCTO (Bit 10) */ +#define SMB3_COMPLETION_SCTO_Msk (0x400UL) /*!< SMB3 COMPLETION: SCTO (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_CHDL_Pos (11UL) /*!< SMB3 COMPLETION: CHDL (Bit 11) */ +#define SMB3_COMPLETION_CHDL_Msk (0x800UL) /*!< SMB3 COMPLETION: CHDL (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_CHDH_Pos (12UL) /*!< SMB3 COMPLETION: CHDH (Bit 12) */ +#define SMB3_COMPLETION_CHDH_Msk (0x1000UL) /*!< SMB3 COMPLETION: CHDH (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_BER_Pos (13UL) /*!< SMB3 COMPLETION: BER (Bit 13) */ +#define SMB3_COMPLETION_BER_Msk (0x2000UL) /*!< SMB3 COMPLETION: BER (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_LAB_Pos (14UL) /*!< SMB3 COMPLETION: LAB (Bit 14) */ +#define SMB3_COMPLETION_LAB_Msk (0x4000UL) /*!< SMB3 COMPLETION: LAB (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_SNAKR_Pos (16UL) /*!< SMB3 COMPLETION: SNAKR (Bit 16) */ +#define SMB3_COMPLETION_SNAKR_Msk (0x10000UL) /*!< SMB3 COMPLETION: SNAKR (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_STR_Pos (17UL) /*!< SMB3 COMPLETION: STR (Bit 17) */ +#define SMB3_COMPLETION_STR_Msk (0x20000UL) /*!< SMB3 COMPLETION: STR (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_SPROT_Pos (19UL) /*!< SMB3 COMPLETION: SPROT (Bit 19) */ +#define SMB3_COMPLETION_SPROT_Msk (0x80000UL) /*!< SMB3 COMPLETION: SPROT (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_REPEAT_READ_Pos (20UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bit 20) */ +#define SMB3_COMPLETION_REPEAT_READ_Msk (0x100000UL) /*!< SMB3 COMPLETION: REPEAT_READ (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_REPEAT_WRITE_Pos (21UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bit 21) */ +#define SMB3_COMPLETION_REPEAT_WRITE_Msk (0x200000UL) /*!< SMB3 COMPLETION: REPEAT_WRITE (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_MNAKX_Pos (24UL) /*!< SMB3 COMPLETION: MNAKX (Bit 24) */ +#define SMB3_COMPLETION_MNAKX_Msk (0x1000000UL) /*!< SMB3 COMPLETION: MNAKX (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_MTR_Pos (25UL) /*!< SMB3 COMPLETION: MTR (Bit 25) */ +#define SMB3_COMPLETION_MTR_Msk (0x2000000UL) /*!< SMB3 COMPLETION: MTR (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_IDLE_Pos (29UL) /*!< SMB3 COMPLETION: IDLE (Bit 29) */ +#define SMB3_COMPLETION_IDLE_Msk (0x20000000UL) /*!< SMB3 COMPLETION: IDLE (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_MDONE_Pos (30UL) /*!< SMB3 COMPLETION: MDONE (Bit 30) */ +#define SMB3_COMPLETION_MDONE_Msk (0x40000000UL) /*!< SMB3 COMPLETION: MDONE (Bitfield-Mask: 0x01) */ +#define SMB3_COMPLETION_SDONE_Pos (31UL) /*!< SMB3 COMPLETION: SDONE (Bit 31) */ +#define SMB3_COMPLETION_SDONE_Msk (0x80000000UL) /*!< SMB3 COMPLETION: SDONE (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB3_IDLE_SCALING ----------------------------- */ +#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Pos (0UL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bit 0) */ +#define SMB3_IDLE_SCALING_FAIR_BUS_IDLE_MIN_Msk (0xfffUL) /*!< SMB3 IDLE_SCALING: FAIR_BUS_IDLE_MIN (Bitfield-Mask: 0xfff) */ +#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Pos (16UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bit 16) */ +#define SMB3_IDLE_SCALING_FAIR_IDLE_DELAY_Msk (0xfff0000UL) /*!< SMB3 IDLE_SCALING: FAIR_IDLE_DELAY (Bitfield-Mask: 0xfff) */ + +/* ----------------------------- SMB3_CONFIGURATION ----------------------------- */ +#define SMB3_CONFIGURATION_PORT_SEL_Pos (0UL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bit 0) */ +#define SMB3_CONFIGURATION_PORT_SEL_Msk (0xfUL) /*!< SMB3 CONFIGURATION: PORT_SEL (Bitfield-Mask: 0x0f) */ +#define SMB3_CONFIGURATION_TCEN_Pos (4UL) /*!< SMB3 CONFIGURATION: TCEN (Bit 4) */ +#define SMB3_CONFIGURATION_TCEN_Msk (0x10UL) /*!< SMB3 CONFIGURATION: TCEN (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_SLOW_CLOCK_Pos (5UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bit 5) */ +#define SMB3_CONFIGURATION_SLOW_CLOCK_Msk (0x20UL) /*!< SMB3 CONFIGURATION: SLOW_CLOCK (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_PECEN_Pos (7UL) /*!< SMB3 CONFIGURATION: PECEN (Bit 7) */ +#define SMB3_CONFIGURATION_PECEN_Msk (0x80UL) /*!< SMB3 CONFIGURATION: PECEN (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_DFEN_Pos (8UL) /*!< SMB3 CONFIGURATION: DFEN (Bit 8) */ +#define SMB3_CONFIGURATION_DFEN_Msk (0x100UL) /*!< SMB3 CONFIGURATION: DFEN (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_RESET_Pos (9UL) /*!< SMB3 CONFIGURATION: RESET (Bit 9) */ +#define SMB3_CONFIGURATION_RESET_Msk (0x200UL) /*!< SMB3 CONFIGURATION: RESET (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_ENAB_Pos (10UL) /*!< SMB3 CONFIGURATION: ENAB (Bit 10) */ +#define SMB3_CONFIGURATION_ENAB_Msk (0x400UL) /*!< SMB3 CONFIGURATION: ENAB (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_DSA_Pos (11UL) /*!< SMB3 CONFIGURATION: DSA (Bit 11) */ +#define SMB3_CONFIGURATION_DSA_Msk (0x800UL) /*!< SMB3 CONFIGURATION: DSA (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_FAIR_Pos (12UL) /*!< SMB3 CONFIGURATION: FAIR (Bit 12) */ +#define SMB3_CONFIGURATION_FAIR_Msk (0x1000UL) /*!< SMB3 CONFIGURATION: FAIR (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_GC_DIS_Pos (14UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bit 14) */ +#define SMB3_CONFIGURATION_GC_DIS_Msk (0x4000UL) /*!< SMB3 CONFIGURATION: GC_DIS (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_FLUSH_SXBUF_Pos (16UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bit 16) */ +#define SMB3_CONFIGURATION_FLUSH_SXBUF_Msk (0x10000UL) /*!< SMB3 CONFIGURATION: FLUSH_SXBUF (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_FLUSH_SRBUF_Pos (17UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bit 17) */ +#define SMB3_CONFIGURATION_FLUSH_SRBUF_Msk (0x20000UL) /*!< SMB3 CONFIGURATION: FLUSH_SRBUF (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_FLUSH_MXBUF_Pos (18UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bit 18) */ +#define SMB3_CONFIGURATION_FLUSH_MXBUF_Msk (0x40000UL) /*!< SMB3 CONFIGURATION: FLUSH_MXBUF (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_FLUSH_MRBUF_Pos (19UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bit 19) */ +#define SMB3_CONFIGURATION_FLUSH_MRBUF_Msk (0x80000UL) /*!< SMB3 CONFIGURATION: FLUSH_MRBUF (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_EN_AAS_Pos (28UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bit 28) */ +#define SMB3_CONFIGURATION_EN_AAS_Msk (0x10000000UL) /*!< SMB3 CONFIGURATION: EN_AAS (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_ENIDI_Pos (29UL) /*!< SMB3 CONFIGURATION: ENIDI (Bit 29) */ +#define SMB3_CONFIGURATION_ENIDI_Msk (0x20000000UL) /*!< SMB3 CONFIGURATION: ENIDI (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_ENMI_Pos (30UL) /*!< SMB3 CONFIGURATION: ENMI (Bit 30) */ +#define SMB3_CONFIGURATION_ENMI_Msk (0x40000000UL) /*!< SMB3 CONFIGURATION: ENMI (Bitfield-Mask: 0x01) */ +#define SMB3_CONFIGURATION_ENSI_Pos (31UL) /*!< SMB3 CONFIGURATION: ENSI (Bit 31) */ +#define SMB3_CONFIGURATION_ENSI_Msk (0x80000000UL) /*!< SMB3 CONFIGURATION: ENSI (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SMB3_BUS_CLOCK ------------------------------- */ +#define SMB3_BUS_CLOCK_LOW_PERIOD_Pos (0UL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bit 0) */ +#define SMB3_BUS_CLOCK_LOW_PERIOD_Msk (0xffUL) /*!< SMB3 BUS_CLOCK: LOW_PERIOD (Bitfield-Mask: 0xff) */ +#define SMB3_BUS_CLOCK_HIGH_PERIOD_Pos (8UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bit 8) */ +#define SMB3_BUS_CLOCK_HIGH_PERIOD_Msk (0xff00UL) /*!< SMB3 BUS_CLOCK: HIGH_PERIOD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB3_BIT_BANG_CONTROL --------------------------- */ +#define SMB3_BIT_BANG_CONTROL_BBEN_Pos (0UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bit 0) */ +#define SMB3_BIT_BANG_CONTROL_BBEN_Msk (0x1UL) /*!< SMB3 BIT_BANG_CONTROL: BBEN (Bitfield-Mask: 0x01) */ +#define SMB3_BIT_BANG_CONTROL_CLDIR_Pos (1UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bit 1) */ +#define SMB3_BIT_BANG_CONTROL_CLDIR_Msk (0x2UL) /*!< SMB3 BIT_BANG_CONTROL: CLDIR (Bitfield-Mask: 0x01) */ +#define SMB3_BIT_BANG_CONTROL_DADIR_Pos (2UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bit 2) */ +#define SMB3_BIT_BANG_CONTROL_DADIR_Msk (0x4UL) /*!< SMB3 BIT_BANG_CONTROL: DADIR (Bitfield-Mask: 0x01) */ +#define SMB3_BIT_BANG_CONTROL_BBCLK_Pos (3UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bit 3) */ +#define SMB3_BIT_BANG_CONTROL_BBCLK_Msk (0x8UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLK (Bitfield-Mask: 0x01) */ +#define SMB3_BIT_BANG_CONTROL_BBDAT_Pos (4UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bit 4) */ +#define SMB3_BIT_BANG_CONTROL_BBDAT_Msk (0x10UL) /*!< SMB3 BIT_BANG_CONTROL: BBDAT (Bitfield-Mask: 0x01) */ +#define SMB3_BIT_BANG_CONTROL_BBCLKI_Pos (5UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bit 5) */ +#define SMB3_BIT_BANG_CONTROL_BBCLKI_Msk (0x20UL) /*!< SMB3 BIT_BANG_CONTROL: BBCLKI (Bitfield-Mask: 0x01) */ +#define SMB3_BIT_BANG_CONTROL_BBDATI_Pos (6UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bit 6) */ +#define SMB3_BIT_BANG_CONTROL_BBDATI_Msk (0x40UL) /*!< SMB3 BIT_BANG_CONTROL: BBDATI (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SMB3_DATA_TIMING ------------------------------ */ +#define SMB3_DATA_TIMING_DATA_HOLD_Pos (0UL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bit 0) */ +#define SMB3_DATA_TIMING_DATA_HOLD_Msk (0xffUL) /*!< SMB3 DATA_TIMING: DATA_HOLD (Bitfield-Mask: 0xff) */ +#define SMB3_DATA_TIMING_RESTART_SETUP_Pos (8UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bit 8) */ +#define SMB3_DATA_TIMING_RESTART_SETUP_Msk (0xff00UL) /*!< SMB3 DATA_TIMING: RESTART_SETUP (Bitfield-Mask: 0xff) */ +#define SMB3_DATA_TIMING_STOP_SETUP_Pos (16UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bit 16) */ +#define SMB3_DATA_TIMING_STOP_SETUP_Msk (0xff0000UL) /*!< SMB3 DATA_TIMING: STOP_SETUP (Bitfield-Mask: 0xff) */ +#define SMB3_DATA_TIMING_START_HOLD_Pos (24UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bit 24) */ +#define SMB3_DATA_TIMING_START_HOLD_Msk (0xff000000UL) /*!< SMB3 DATA_TIMING: START_HOLD (Bitfield-Mask: 0xff) */ + +/* ---------------------------- SMB3_TIME_OUT_SCALING --------------------------- */ +#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Pos (0UL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bit 0) */ +#define SMB3_TIME_OUT_SCALING_CLOCK_HIGH_Msk (0xffUL) /*!< SMB3 TIME_OUT_SCALING: CLOCK_HIGH (Bitfield-Mask: 0xff) */ +#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Pos (8UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bit 8) */ +#define SMB3_TIME_OUT_SCALING_SLAVE_CUM_Msk (0xff00UL) /*!< SMB3 TIME_OUT_SCALING: SLAVE_CUM (Bitfield-Mask: 0xff) */ +#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Pos (16UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bit 16) */ +#define SMB3_TIME_OUT_SCALING_MASTER_CUM_Msk (0xff0000UL) /*!< SMB3 TIME_OUT_SCALING: MASTER_CUM (Bitfield-Mask: 0xff) */ +#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Pos (24UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bit 24) */ +#define SMB3_TIME_OUT_SCALING_BUS_IDLE_MIN_Msk (0xff000000UL) /*!< SMB3 TIME_OUT_SCALING: BUS_IDLE_MIN (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'PECI' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PECI_CONTROL -------------------------------- */ +#define PECI_CONTROL_PD_Pos (0UL) /*!< PECI CONTROL: PD (Bit 0) */ +#define PECI_CONTROL_PD_Msk (0x1UL) /*!< PECI CONTROL: PD (Bitfield-Mask: 0x01) */ +#define PECI_CONTROL_RST_Pos (3UL) /*!< PECI CONTROL: RST (Bit 3) */ +#define PECI_CONTROL_RST_Msk (0x8UL) /*!< PECI CONTROL: RST (Bitfield-Mask: 0x01) */ +#define PECI_CONTROL_FRST_Pos (5UL) /*!< PECI CONTROL: FRST (Bit 5) */ +#define PECI_CONTROL_FRST_Msk (0x20UL) /*!< PECI CONTROL: FRST (Bitfield-Mask: 0x01) */ +#define PECI_CONTROL_TXEN_Pos (6UL) /*!< PECI CONTROL: TXEN (Bit 6) */ +#define PECI_CONTROL_TXEN_Msk (0x40UL) /*!< PECI CONTROL: TXEN (Bitfield-Mask: 0x01) */ +#define PECI_CONTROL_MIEN_Pos (7UL) /*!< PECI CONTROL: MIEN (Bit 7) */ +#define PECI_CONTROL_MIEN_Msk (0x80UL) /*!< PECI CONTROL: MIEN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PECI_STATUS1 -------------------------------- */ +#define PECI_STATUS1_BOF_Pos (0UL) /*!< PECI STATUS1: BOF (Bit 0) */ +#define PECI_STATUS1_BOF_Msk (0x1UL) /*!< PECI STATUS1: BOF (Bitfield-Mask: 0x01) */ +#define PECI_STATUS1_EOF_Pos (1UL) /*!< PECI STATUS1: EOF (Bit 1) */ +#define PECI_STATUS1_EOF_Msk (0x2UL) /*!< PECI STATUS1: EOF (Bitfield-Mask: 0x01) */ +#define PECI_STATUS1_ERR_Pos (2UL) /*!< PECI STATUS1: ERR (Bit 2) */ +#define PECI_STATUS1_ERR_Msk (0x4UL) /*!< PECI STATUS1: ERR (Bitfield-Mask: 0x01) */ +#define PECI_STATUS1_RDY_Pos (3UL) /*!< PECI STATUS1: RDY (Bit 3) */ +#define PECI_STATUS1_RDY_Msk (0x8UL) /*!< PECI STATUS1: RDY (Bitfield-Mask: 0x01) */ +#define PECI_STATUS1_RDYLO_Pos (4UL) /*!< PECI STATUS1: RDYLO (Bit 4) */ +#define PECI_STATUS1_RDYLO_Msk (0x10UL) /*!< PECI STATUS1: RDYLO (Bitfield-Mask: 0x01) */ +#define PECI_STATUS1_RDYHI_Pos (5UL) /*!< PECI STATUS1: RDYHI (Bit 5) */ +#define PECI_STATUS1_RDYHI_Msk (0x20UL) /*!< PECI STATUS1: RDYHI (Bitfield-Mask: 0x01) */ +#define PECI_STATUS1_MINT_Pos (7UL) /*!< PECI STATUS1: MINT (Bit 7) */ +#define PECI_STATUS1_MINT_Msk (0x80UL) /*!< PECI STATUS1: MINT (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PECI_STATUS2 -------------------------------- */ +#define PECI_STATUS2_WFF_Pos (0UL) /*!< PECI STATUS2: WFF (Bit 0) */ +#define PECI_STATUS2_WFF_Msk (0x1UL) /*!< PECI STATUS2: WFF (Bitfield-Mask: 0x01) */ +#define PECI_STATUS2_WFE_Pos (1UL) /*!< PECI STATUS2: WFE (Bit 1) */ +#define PECI_STATUS2_WFE_Msk (0x2UL) /*!< PECI STATUS2: WFE (Bitfield-Mask: 0x01) */ +#define PECI_STATUS2_RFF_Pos (2UL) /*!< PECI STATUS2: RFF (Bit 2) */ +#define PECI_STATUS2_RFF_Msk (0x4UL) /*!< PECI STATUS2: RFF (Bitfield-Mask: 0x01) */ +#define PECI_STATUS2_RFE_Pos (3UL) /*!< PECI STATUS2: RFE (Bit 3) */ +#define PECI_STATUS2_RFE_Msk (0x8UL) /*!< PECI STATUS2: RFE (Bitfield-Mask: 0x01) */ +#define PECI_STATUS2_IDLE_Pos (7UL) /*!< PECI STATUS2: IDLE (Bit 7) */ +#define PECI_STATUS2_IDLE_Msk (0x80UL) /*!< PECI STATUS2: IDLE (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PECI_ERROR --------------------------------- */ +#define PECI_ERROR_FERR_Pos (0UL) /*!< PECI ERROR: FERR (Bit 0) */ +#define PECI_ERROR_FERR_Msk (0x1UL) /*!< PECI ERROR: FERR (Bitfield-Mask: 0x01) */ +#define PECI_ERROR_BERR_Pos (1UL) /*!< PECI ERROR: BERR (Bit 1) */ +#define PECI_ERROR_BERR_Msk (0x2UL) /*!< PECI ERROR: BERR (Bitfield-Mask: 0x01) */ +#define PECI_ERROR_REQERR_Pos (3UL) /*!< PECI ERROR: REQERR (Bit 3) */ +#define PECI_ERROR_REQERR_Msk (0x8UL) /*!< PECI ERROR: REQERR (Bitfield-Mask: 0x01) */ +#define PECI_ERROR_WROV_Pos (4UL) /*!< PECI ERROR: WROV (Bit 4) */ +#define PECI_ERROR_WROV_Msk (0x10UL) /*!< PECI ERROR: WROV (Bitfield-Mask: 0x01) */ +#define PECI_ERROR_WRUN_Pos (5UL) /*!< PECI ERROR: WRUN (Bit 5) */ +#define PECI_ERROR_WRUN_Msk (0x20UL) /*!< PECI ERROR: WRUN (Bitfield-Mask: 0x01) */ +#define PECI_ERROR_RDOV_Pos (6UL) /*!< PECI ERROR: RDOV (Bit 6) */ +#define PECI_ERROR_RDOV_Msk (0x40UL) /*!< PECI ERROR: RDOV (Bitfield-Mask: 0x01) */ +#define PECI_ERROR_CLKERR_Pos (7UL) /*!< PECI ERROR: CLKERR (Bit 7) */ +#define PECI_ERROR_CLKERR_Msk (0x80UL) /*!< PECI ERROR: CLKERR (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PECI_INT_EN1 -------------------------------- */ +#define PECI_INT_EN1_BIEN_Pos (0UL) /*!< PECI INT_EN1: BIEN (Bit 0) */ +#define PECI_INT_EN1_BIEN_Msk (0x1UL) /*!< PECI INT_EN1: BIEN (Bitfield-Mask: 0x01) */ +#define PECI_INT_EN1_EIEN_Pos (1UL) /*!< PECI INT_EN1: EIEN (Bit 1) */ +#define PECI_INT_EN1_EIEN_Msk (0x2UL) /*!< PECI INT_EN1: EIEN (Bitfield-Mask: 0x01) */ +#define PECI_INT_EN1_EREN_Pos (2UL) /*!< PECI INT_EN1: EREN (Bit 2) */ +#define PECI_INT_EN1_EREN_Msk (0x4UL) /*!< PECI INT_EN1: EREN (Bitfield-Mask: 0x01) */ +#define PECI_INT_EN1_RLEN_Pos (4UL) /*!< PECI INT_EN1: RLEN (Bit 4) */ +#define PECI_INT_EN1_RLEN_Msk (0x10UL) /*!< PECI INT_EN1: RLEN (Bitfield-Mask: 0x01) */ +#define PECI_INT_EN1_RHEN_Pos (5UL) /*!< PECI INT_EN1: RHEN (Bit 5) */ +#define PECI_INT_EN1_RHEN_Msk (0x20UL) /*!< PECI INT_EN1: RHEN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PECI_INT_EN2 -------------------------------- */ +#define PECI_INT_EN2_ENWFE_Pos (1UL) /*!< PECI INT_EN2: ENWFE (Bit 1) */ +#define PECI_INT_EN2_ENWFE_Msk (0x2UL) /*!< PECI INT_EN2: ENWFE (Bitfield-Mask: 0x01) */ +#define PECI_INT_EN2_ENRFF_Pos (2UL) /*!< PECI INT_EN2: ENRFF (Bit 2) */ +#define PECI_INT_EN2_ENRFF_Msk (0x4UL) /*!< PECI INT_EN2: ENRFF (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'TACH_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- TACH_0_CONTROL ------------------------------- */ +#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */ +#define TACH_0_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_0 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */ +#define TACH_0_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_0 CONTROL: TACH_EN (Bit 1) */ +#define TACH_0_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_0 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */ +#define TACH_0_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_0 CONTROL: FILTER_EN (Bit 8) */ +#define TACH_0_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_0 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */ +#define TACH_0_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bit 10) */ +#define TACH_0_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_0 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */ +#define TACH_0_CONTROL_EDGES_Pos (11UL) /*!< TACH_0 CONTROL: EDGES (Bit 11) */ +#define TACH_0_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_0 CONTROL: EDGES (Bitfield-Mask: 0x03) */ +#define TACH_0_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bit 14) */ +#define TACH_0_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_0 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */ +#define TACH_0_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bit 15) */ +#define TACH_0_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_0 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */ +#define TACH_0_CONTROL_COUNTER_Pos (16UL) /*!< TACH_0 CONTROL: COUNTER (Bit 16) */ +#define TACH_0_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_0 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- TACH_0_STATUS ------------------------------- */ +#define TACH_0_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bit 0) */ +#define TACH_0_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_0 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */ +#define TACH_0_STATUS_PIN_Pos (1UL) /*!< TACH_0 STATUS: PIN (Bit 1) */ +#define TACH_0_STATUS_PIN_Msk (0x2UL) /*!< TACH_0 STATUS: PIN (Bitfield-Mask: 0x01) */ +#define TACH_0_STATUS_TOGGLE_Pos (2UL) /*!< TACH_0 STATUS: TOGGLE (Bit 2) */ +#define TACH_0_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_0 STATUS: TOGGLE (Bitfield-Mask: 0x01) */ +#define TACH_0_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_0 STATUS: COUNT_READY (Bit 3) */ +#define TACH_0_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_0 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'TACH_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- TACH_1_CONTROL ------------------------------- */ +#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Pos (0UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bit 0) */ +#define TACH_1_CONTROL_OUT_LIMIT_ENABLE_Msk (0x1UL) /*!< TACH_1 CONTROL: OUT_LIMIT_ENABLE (Bitfield-Mask: 0x01) */ +#define TACH_1_CONTROL_TACH_EN_Pos (1UL) /*!< TACH_1 CONTROL: TACH_EN (Bit 1) */ +#define TACH_1_CONTROL_TACH_EN_Msk (0x2UL) /*!< TACH_1 CONTROL: TACH_EN (Bitfield-Mask: 0x01) */ +#define TACH_1_CONTROL_FILTER_EN_Pos (8UL) /*!< TACH_1 CONTROL: FILTER_EN (Bit 8) */ +#define TACH_1_CONTROL_FILTER_EN_Msk (0x100UL) /*!< TACH_1 CONTROL: FILTER_EN (Bitfield-Mask: 0x01) */ +#define TACH_1_CONTROL_MODE_SELECT_Pos (10UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bit 10) */ +#define TACH_1_CONTROL_MODE_SELECT_Msk (0x400UL) /*!< TACH_1 CONTROL: MODE_SELECT (Bitfield-Mask: 0x01) */ +#define TACH_1_CONTROL_EDGES_Pos (11UL) /*!< TACH_1 CONTROL: EDGES (Bit 11) */ +#define TACH_1_CONTROL_EDGES_Msk (0x1800UL) /*!< TACH_1 CONTROL: EDGES (Bitfield-Mask: 0x03) */ +#define TACH_1_CONTROL_READY_INT_EN_Pos (14UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bit 14) */ +#define TACH_1_CONTROL_READY_INT_EN_Msk (0x4000UL) /*!< TACH_1 CONTROL: READY_INT_EN (Bitfield-Mask: 0x01) */ +#define TACH_1_CONTROL_INPUT_INT_EN_Pos (15UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bit 15) */ +#define TACH_1_CONTROL_INPUT_INT_EN_Msk (0x8000UL) /*!< TACH_1 CONTROL: INPUT_INT_EN (Bitfield-Mask: 0x01) */ +#define TACH_1_CONTROL_COUNTER_Pos (16UL) /*!< TACH_1 CONTROL: COUNTER (Bit 16) */ +#define TACH_1_CONTROL_COUNTER_Msk (0xffff0000UL) /*!< TACH_1 CONTROL: COUNTER (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- TACH_1_STATUS ------------------------------- */ +#define TACH_1_STATUS_OUT_LIMIT_Pos (0UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bit 0) */ +#define TACH_1_STATUS_OUT_LIMIT_Msk (0x1UL) /*!< TACH_1 STATUS: OUT_LIMIT (Bitfield-Mask: 0x01) */ +#define TACH_1_STATUS_PIN_Pos (1UL) /*!< TACH_1 STATUS: PIN (Bit 1) */ +#define TACH_1_STATUS_PIN_Msk (0x2UL) /*!< TACH_1 STATUS: PIN (Bitfield-Mask: 0x01) */ +#define TACH_1_STATUS_TOGGLE_Pos (2UL) /*!< TACH_1 STATUS: TOGGLE (Bit 2) */ +#define TACH_1_STATUS_TOGGLE_Msk (0x4UL) /*!< TACH_1 STATUS: TOGGLE (Bitfield-Mask: 0x01) */ +#define TACH_1_STATUS_COUNT_READY_Pos (3UL) /*!< TACH_1 STATUS: COUNT_READY (Bit 3) */ +#define TACH_1_STATUS_COUNT_READY_Msk (0x8UL) /*!< TACH_1 STATUS: COUNT_READY (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'PWM_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PWM_0_CONFIG -------------------------------- */ +#define PWM_0_CONFIG_EN_Pos (0UL) /*!< PWM_0 CONFIG: EN (Bit 0) */ +#define PWM_0_CONFIG_EN_Msk (0x1UL) /*!< PWM_0 CONFIG: EN (Bitfield-Mask: 0x01) */ +#define PWM_0_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bit 1) */ +#define PWM_0_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_0 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ +#define PWM_0_CONFIG_INVERT_Pos (2UL) /*!< PWM_0 CONFIG: INVERT (Bit 2) */ +#define PWM_0_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_0 CONFIG: INVERT (Bitfield-Mask: 0x01) */ +#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ +#define PWM_0_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_0 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'PWM_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PWM_1_CONFIG -------------------------------- */ +#define PWM_1_CONFIG_EN_Pos (0UL) /*!< PWM_1 CONFIG: EN (Bit 0) */ +#define PWM_1_CONFIG_EN_Msk (0x1UL) /*!< PWM_1 CONFIG: EN (Bitfield-Mask: 0x01) */ +#define PWM_1_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bit 1) */ +#define PWM_1_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_1 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ +#define PWM_1_CONFIG_INVERT_Pos (2UL) /*!< PWM_1 CONFIG: INVERT (Bit 2) */ +#define PWM_1_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_1 CONFIG: INVERT (Bitfield-Mask: 0x01) */ +#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ +#define PWM_1_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_1 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'PWM_2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PWM_2_CONFIG -------------------------------- */ +#define PWM_2_CONFIG_EN_Pos (0UL) /*!< PWM_2 CONFIG: EN (Bit 0) */ +#define PWM_2_CONFIG_EN_Msk (0x1UL) /*!< PWM_2 CONFIG: EN (Bitfield-Mask: 0x01) */ +#define PWM_2_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bit 1) */ +#define PWM_2_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_2 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ +#define PWM_2_CONFIG_INVERT_Pos (2UL) /*!< PWM_2 CONFIG: INVERT (Bit 2) */ +#define PWM_2_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_2 CONFIG: INVERT (Bitfield-Mask: 0x01) */ +#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ +#define PWM_2_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_2 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'PWM_3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PWM_3_CONFIG -------------------------------- */ +#define PWM_3_CONFIG_EN_Pos (0UL) /*!< PWM_3 CONFIG: EN (Bit 0) */ +#define PWM_3_CONFIG_EN_Msk (0x1UL) /*!< PWM_3 CONFIG: EN (Bitfield-Mask: 0x01) */ +#define PWM_3_CONFIG_CLK_SELECT_Pos (1UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bit 1) */ +#define PWM_3_CONFIG_CLK_SELECT_Msk (0x2UL) /*!< PWM_3 CONFIG: CLK_SELECT (Bitfield-Mask: 0x01) */ +#define PWM_3_CONFIG_INVERT_Pos (2UL) /*!< PWM_3 CONFIG: INVERT (Bit 2) */ +#define PWM_3_CONFIG_INVERT_Msk (0x4UL) /*!< PWM_3 CONFIG: INVERT (Bitfield-Mask: 0x01) */ +#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Pos (3UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bit 3) */ +#define PWM_3_CONFIG_CLK_PRE_DIVIDER_Msk (0x78UL) /*!< PWM_3 CONFIG: CLK_PRE_DIVIDER (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'RPM_FAN' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- RPM_FAN_CONFIGURATION --------------------------- */ +#define RPM_FAN_CONFIGURATION_UPDATE_Pos (0UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bit 0) */ +#define RPM_FAN_CONFIGURATION_UPDATE_Msk (0x7UL) /*!< RPM_FAN CONFIGURATION: UPDATE (Bitfield-Mask: 0x07) */ +#define RPM_FAN_CONFIGURATION_EDGES_Pos (3UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bit 3) */ +#define RPM_FAN_CONFIGURATION_EDGES_Msk (0x18UL) /*!< RPM_FAN CONFIGURATION: EDGES (Bitfield-Mask: 0x03) */ +#define RPM_FAN_CONFIGURATION_RANGE_Pos (5UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bit 5) */ +#define RPM_FAN_CONFIGURATION_RANGE_Msk (0x60UL) /*!< RPM_FAN CONFIGURATION: RANGE (Bitfield-Mask: 0x03) */ +#define RPM_FAN_CONFIGURATION_EN_ALGO_Pos (7UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bit 7) */ +#define RPM_FAN_CONFIGURATION_EN_ALGO_Msk (0x80UL) /*!< RPM_FAN CONFIGURATION: EN_ALGO (Bitfield-Mask: 0x01) */ +#define RPM_FAN_CONFIGURATION_POLARITY_Pos (8UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bit 8) */ +#define RPM_FAN_CONFIGURATION_POLARITY_Msk (0x100UL) /*!< RPM_FAN CONFIGURATION: POLARITY (Bitfield-Mask: 0x01) */ +#define RPM_FAN_CONFIGURATION_ERR_RNG_Pos (9UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bit 9) */ +#define RPM_FAN_CONFIGURATION_ERR_RNG_Msk (0x600UL) /*!< RPM_FAN CONFIGURATION: ERR_RNG (Bitfield-Mask: 0x03) */ +#define RPM_FAN_CONFIGURATION_DER_OPT_Pos (11UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bit 11) */ +#define RPM_FAN_CONFIGURATION_DER_OPT_Msk (0x1800UL) /*!< RPM_FAN CONFIGURATION: DER_OPT (Bitfield-Mask: 0x03) */ +#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Pos (13UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bit 13) */ +#define RPM_FAN_CONFIGURATION_DIS_GLITCH_Msk (0x2000UL) /*!< RPM_FAN CONFIGURATION: DIS_GLITCH (Bitfield-Mask: 0x01) */ +#define RPM_FAN_CONFIGURATION_EN_RRC_Pos (14UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bit 14) */ +#define RPM_FAN_CONFIGURATION_EN_RRC_Msk (0x4000UL) /*!< RPM_FAN CONFIGURATION: EN_RRC (Bitfield-Mask: 0x01) */ + +/* -------------------------------- RPM_FAN_GAIN -------------------------------- */ +#define RPM_FAN_GAIN_GAINP_Pos (0UL) /*!< RPM_FAN GAIN: GAINP (Bit 0) */ +#define RPM_FAN_GAIN_GAINP_Msk (0x3UL) /*!< RPM_FAN GAIN: GAINP (Bitfield-Mask: 0x03) */ +#define RPM_FAN_GAIN_GAINI_Pos (2UL) /*!< RPM_FAN GAIN: GAINI (Bit 2) */ +#define RPM_FAN_GAIN_GAINI_Msk (0xcUL) /*!< RPM_FAN GAIN: GAINI (Bitfield-Mask: 0x03) */ +#define RPM_FAN_GAIN_GAIND_Pos (4UL) /*!< RPM_FAN GAIN: GAIND (Bit 4) */ +#define RPM_FAN_GAIN_GAIND_Msk (0x30UL) /*!< RPM_FAN GAIN: GAIND (Bitfield-Mask: 0x03) */ + +/* ------------------------ RPM_FAN_SPIN_UP_CONFIGURATION ----------------------- */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Pos (0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bit 0) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_SPINUP_TIME_Msk (0x3UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPINUP_TIME (Bitfield-Mask: 0x03) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Pos (2UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bit 2) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_SPIN_LVL_Msk (0x1cUL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: SPIN_LVL (Bitfield-Mask: 0x07) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Pos (5UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bit 5) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_NOKICK_Msk (0x20UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: NOKICK (Bitfield-Mask: 0x01) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Pos (6UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bit 6) */ +#define RPM_FAN_SPIN_UP_CONFIGURATION_DRIVE_FAIL_CNT_Msk (0xc0UL) /*!< RPM_FAN SPIN_UP_CONFIGURATION: DRIVE_FAIL_CNT (Bitfield-Mask: 0x03) */ + +/* ------------------------------- RPM_FAN_STATUS ------------------------------- */ +#define RPM_FAN_STATUS_FAN_STALL_Pos (0UL) /*!< RPM_FAN STATUS: FAN_STALL (Bit 0) */ +#define RPM_FAN_STATUS_FAN_STALL_Msk (0x1UL) /*!< RPM_FAN STATUS: FAN_STALL (Bitfield-Mask: 0x01) */ +#define RPM_FAN_STATUS_FAN_SPIN_Pos (1UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bit 1) */ +#define RPM_FAN_STATUS_FAN_SPIN_Msk (0x2UL) /*!< RPM_FAN STATUS: FAN_SPIN (Bitfield-Mask: 0x01) */ +#define RPM_FAN_STATUS_DRIVE_FAIL_Pos (5UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bit 5) */ +#define RPM_FAN_STATUS_DRIVE_FAIL_Msk (0x20UL) /*!< RPM_FAN STATUS: DRIVE_FAIL (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SPI_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- SPI_0_CONTROL ------------------------------- */ +#define SPI_0_CONTROL_LSBF_Pos (0UL) /*!< SPI_0 CONTROL: LSBF (Bit 0) */ +#define SPI_0_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_0 CONTROL: LSBF (Bitfield-Mask: 0x01) */ +#define SPI_0_CONTROL_BIOEN_Pos (1UL) /*!< SPI_0 CONTROL: BIOEN (Bit 1) */ +#define SPI_0_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_0 CONTROL: BIOEN (Bitfield-Mask: 0x01) */ +#define SPI_0_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bit 2) */ +#define SPI_0_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_0 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */ +#define SPI_0_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bit 4) */ +#define SPI_0_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_0 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define SPI_0_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_0 CONTROL: AUTO_READ (Bit 5) */ +#define SPI_0_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_0 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */ +#define SPI_0_CONTROL_CE_Pos (6UL) /*!< SPI_0 CONTROL: CE (Bit 6) */ +#define SPI_0_CONTROL_CE_Msk (0x40UL) /*!< SPI_0 CONTROL: CE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- SPI_0_STATUS -------------------------------- */ +#define SPI_0_STATUS_TXBE_Pos (0UL) /*!< SPI_0 STATUS: TXBE (Bit 0) */ +#define SPI_0_STATUS_TXBE_Msk (0x1UL) /*!< SPI_0 STATUS: TXBE (Bitfield-Mask: 0x01) */ +#define SPI_0_STATUS_RXBF_Pos (1UL) /*!< SPI_0 STATUS: RXBF (Bit 1) */ +#define SPI_0_STATUS_RXBF_Msk (0x2UL) /*!< SPI_0 STATUS: RXBF (Bitfield-Mask: 0x01) */ +#define SPI_0_STATUS_ACTIVE_Pos (2UL) /*!< SPI_0 STATUS: ACTIVE (Bit 2) */ +#define SPI_0_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_0 STATUS: ACTIVE (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SPI_0_CLOCK_Control ---------------------------- */ +#define SPI_0_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bit 0) */ +#define SPI_0_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_0 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */ +#define SPI_0_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bit 1) */ +#define SPI_0_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_0 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */ +#define SPI_0_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bit 2) */ +#define SPI_0_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_0 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */ +#define SPI_0_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bit 4) */ +#define SPI_0_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_0 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SPI_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- SPI_1_CONTROL ------------------------------- */ +#define SPI_1_CONTROL_LSBF_Pos (0UL) /*!< SPI_1 CONTROL: LSBF (Bit 0) */ +#define SPI_1_CONTROL_LSBF_Msk (0x1UL) /*!< SPI_1 CONTROL: LSBF (Bitfield-Mask: 0x01) */ +#define SPI_1_CONTROL_BIOEN_Pos (1UL) /*!< SPI_1 CONTROL: BIOEN (Bit 1) */ +#define SPI_1_CONTROL_BIOEN_Msk (0x2UL) /*!< SPI_1 CONTROL: BIOEN (Bitfield-Mask: 0x01) */ +#define SPI_1_CONTROL_SPDIN_SELECT_Pos (2UL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bit 2) */ +#define SPI_1_CONTROL_SPDIN_SELECT_Msk (0xcUL) /*!< SPI_1 CONTROL: SPDIN_SELECT (Bitfield-Mask: 0x03) */ +#define SPI_1_CONTROL_SOFT_RESET_Pos (4UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bit 4) */ +#define SPI_1_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< SPI_1 CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define SPI_1_CONTROL_AUTO_READ_Pos (5UL) /*!< SPI_1 CONTROL: AUTO_READ (Bit 5) */ +#define SPI_1_CONTROL_AUTO_READ_Msk (0x20UL) /*!< SPI_1 CONTROL: AUTO_READ (Bitfield-Mask: 0x01) */ +#define SPI_1_CONTROL_CE_Pos (6UL) /*!< SPI_1 CONTROL: CE (Bit 6) */ +#define SPI_1_CONTROL_CE_Msk (0x40UL) /*!< SPI_1 CONTROL: CE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- SPI_1_STATUS -------------------------------- */ +#define SPI_1_STATUS_TXBE_Pos (0UL) /*!< SPI_1 STATUS: TXBE (Bit 0) */ +#define SPI_1_STATUS_TXBE_Msk (0x1UL) /*!< SPI_1 STATUS: TXBE (Bitfield-Mask: 0x01) */ +#define SPI_1_STATUS_RXBF_Pos (1UL) /*!< SPI_1 STATUS: RXBF (Bit 1) */ +#define SPI_1_STATUS_RXBF_Msk (0x2UL) /*!< SPI_1 STATUS: RXBF (Bitfield-Mask: 0x01) */ +#define SPI_1_STATUS_ACTIVE_Pos (2UL) /*!< SPI_1 STATUS: ACTIVE (Bit 2) */ +#define SPI_1_STATUS_ACTIVE_Msk (0x4UL) /*!< SPI_1 STATUS: ACTIVE (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SPI_1_CLOCK_Control ---------------------------- */ +#define SPI_1_CLOCK_Control_TCLKPH_Pos (0UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bit 0) */ +#define SPI_1_CLOCK_Control_TCLKPH_Msk (0x1UL) /*!< SPI_1 CLOCK_Control: TCLKPH (Bitfield-Mask: 0x01) */ +#define SPI_1_CLOCK_Control_RCLKPH_Pos (1UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bit 1) */ +#define SPI_1_CLOCK_Control_RCLKPH_Msk (0x2UL) /*!< SPI_1 CLOCK_Control: RCLKPH (Bitfield-Mask: 0x01) */ +#define SPI_1_CLOCK_Control_CLKPOL_Pos (2UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bit 2) */ +#define SPI_1_CLOCK_Control_CLKPOL_Msk (0x4UL) /*!< SPI_1 CLOCK_Control: CLKPOL (Bitfield-Mask: 0x01) */ +#define SPI_1_CLOCK_Control_CLKSRC_Pos (4UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bit 4) */ +#define SPI_1_CLOCK_Control_CLKSRC_Msk (0x10UL) /*!< SPI_1 CLOCK_Control: CLKSRC (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'LED_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- LED_0_CONFIG -------------------------------- */ +#define LED_0_CONFIG_CONTROL_Pos (0UL) /*!< LED_0 CONFIG: CONTROL (Bit 0) */ +#define LED_0_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_0 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ +#define LED_0_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bit 2) */ +#define LED_0_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_0 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ +#define LED_0_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bit 3) */ +#define LED_0_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_0 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ +#define LED_0_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_0 CONFIG: PWM_SIZE (Bit 4) */ +#define LED_0_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_0 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ +#define LED_0_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bit 6) */ +#define LED_0_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_0 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ +#define LED_0_CONFIG_RESET_Pos (7UL) /*!< LED_0 CONFIG: RESET (Bit 7) */ +#define LED_0_CONFIG_RESET_Msk (0x80UL) /*!< LED_0 CONFIG: RESET (Bitfield-Mask: 0x01) */ +#define LED_0_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bit 8) */ +#define LED_0_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_0 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ +#define LED_0_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_0 CONFIG: SYMMETRY (Bit 16) */ +#define LED_0_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_0 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ + +/* -------------------------------- LED_0_LIMITS -------------------------------- */ +#define LED_0_LIMITS_MINIMUM_Pos (0UL) /*!< LED_0 LIMITS: MINIMUM (Bit 0) */ +#define LED_0_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_0 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ +#define LED_0_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_0 LIMITS: MAXIMUM (Bit 8) */ +#define LED_0_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_0 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ + +/* --------------------------------- LED_0_DELAY -------------------------------- */ +#define LED_0_DELAY_LOW_Pos (0UL) /*!< LED_0 DELAY: LOW (Bit 0) */ +#define LED_0_DELAY_LOW_Msk (0xfffUL) /*!< LED_0 DELAY: LOW (Bitfield-Mask: 0xfff) */ +#define LED_0_DELAY_HIGH_Pos (12UL) /*!< LED_0 DELAY: HIGH (Bit 12) */ +#define LED_0_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_0 DELAY: HIGH (Bitfield-Mask: 0xfff) */ + +/* ---------------------------- LED_0_UPDATE_STEPSIZE --------------------------- */ +#define LED_0_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bit 0) */ +#define LED_0_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_0 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bit 4) */ +#define LED_0_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_0 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bit 8) */ +#define LED_0_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_0 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bit 12) */ +#define LED_0_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bit 16) */ +#define LED_0_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bit 20) */ +#define LED_0_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bit 24) */ +#define LED_0_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bit 28) */ +#define LED_0_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ + +/* ---------------------------- LED_0_UPDATE_INTERVAL --------------------------- */ +#define LED_0_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ +#define LED_0_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_0 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'LED_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- LED_1_CONFIG -------------------------------- */ +#define LED_1_CONFIG_CONTROL_Pos (0UL) /*!< LED_1 CONFIG: CONTROL (Bit 0) */ +#define LED_1_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_1 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ +#define LED_1_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bit 2) */ +#define LED_1_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_1 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ +#define LED_1_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bit 3) */ +#define LED_1_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_1 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ +#define LED_1_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_1 CONFIG: PWM_SIZE (Bit 4) */ +#define LED_1_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_1 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ +#define LED_1_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bit 6) */ +#define LED_1_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_1 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ +#define LED_1_CONFIG_RESET_Pos (7UL) /*!< LED_1 CONFIG: RESET (Bit 7) */ +#define LED_1_CONFIG_RESET_Msk (0x80UL) /*!< LED_1 CONFIG: RESET (Bitfield-Mask: 0x01) */ +#define LED_1_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bit 8) */ +#define LED_1_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_1 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ +#define LED_1_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_1 CONFIG: SYMMETRY (Bit 16) */ +#define LED_1_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_1 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ + +/* -------------------------------- LED_1_LIMITS -------------------------------- */ +#define LED_1_LIMITS_MINIMUM_Pos (0UL) /*!< LED_1 LIMITS: MINIMUM (Bit 0) */ +#define LED_1_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_1 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ +#define LED_1_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_1 LIMITS: MAXIMUM (Bit 8) */ +#define LED_1_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_1 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ + +/* --------------------------------- LED_1_DELAY -------------------------------- */ +#define LED_1_DELAY_LOW_Pos (0UL) /*!< LED_1 DELAY: LOW (Bit 0) */ +#define LED_1_DELAY_LOW_Msk (0xfffUL) /*!< LED_1 DELAY: LOW (Bitfield-Mask: 0xfff) */ +#define LED_1_DELAY_HIGH_Pos (12UL) /*!< LED_1 DELAY: HIGH (Bit 12) */ +#define LED_1_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_1 DELAY: HIGH (Bitfield-Mask: 0xfff) */ + +/* ---------------------------- LED_1_UPDATE_STEPSIZE --------------------------- */ +#define LED_1_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bit 0) */ +#define LED_1_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_1 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bit 4) */ +#define LED_1_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_1 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bit 8) */ +#define LED_1_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_1 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bit 12) */ +#define LED_1_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bit 16) */ +#define LED_1_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bit 20) */ +#define LED_1_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bit 24) */ +#define LED_1_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bit 28) */ +#define LED_1_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ + +/* ---------------------------- LED_1_UPDATE_INTERVAL --------------------------- */ +#define LED_1_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ +#define LED_1_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_1 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'LED_2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- LED_2_CONFIG -------------------------------- */ +#define LED_2_CONFIG_CONTROL_Pos (0UL) /*!< LED_2 CONFIG: CONTROL (Bit 0) */ +#define LED_2_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_2 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ +#define LED_2_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bit 2) */ +#define LED_2_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_2 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ +#define LED_2_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bit 3) */ +#define LED_2_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_2 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ +#define LED_2_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_2 CONFIG: PWM_SIZE (Bit 4) */ +#define LED_2_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_2 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ +#define LED_2_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bit 6) */ +#define LED_2_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_2 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ +#define LED_2_CONFIG_RESET_Pos (7UL) /*!< LED_2 CONFIG: RESET (Bit 7) */ +#define LED_2_CONFIG_RESET_Msk (0x80UL) /*!< LED_2 CONFIG: RESET (Bitfield-Mask: 0x01) */ +#define LED_2_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bit 8) */ +#define LED_2_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_2 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ +#define LED_2_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_2 CONFIG: SYMMETRY (Bit 16) */ +#define LED_2_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_2 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ + +/* -------------------------------- LED_2_LIMITS -------------------------------- */ +#define LED_2_LIMITS_MINIMUM_Pos (0UL) /*!< LED_2 LIMITS: MINIMUM (Bit 0) */ +#define LED_2_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_2 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ +#define LED_2_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_2 LIMITS: MAXIMUM (Bit 8) */ +#define LED_2_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_2 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ + +/* --------------------------------- LED_2_DELAY -------------------------------- */ +#define LED_2_DELAY_LOW_Pos (0UL) /*!< LED_2 DELAY: LOW (Bit 0) */ +#define LED_2_DELAY_LOW_Msk (0xfffUL) /*!< LED_2 DELAY: LOW (Bitfield-Mask: 0xfff) */ +#define LED_2_DELAY_HIGH_Pos (12UL) /*!< LED_2 DELAY: HIGH (Bit 12) */ +#define LED_2_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_2 DELAY: HIGH (Bitfield-Mask: 0xfff) */ + +/* ---------------------------- LED_2_UPDATE_STEPSIZE --------------------------- */ +#define LED_2_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bit 0) */ +#define LED_2_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_2 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bit 4) */ +#define LED_2_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_2 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bit 8) */ +#define LED_2_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_2 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bit 12) */ +#define LED_2_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bit 16) */ +#define LED_2_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bit 20) */ +#define LED_2_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bit 24) */ +#define LED_2_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bit 28) */ +#define LED_2_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ + +/* ---------------------------- LED_2_UPDATE_INTERVAL --------------------------- */ +#define LED_2_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ +#define LED_2_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_2 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'LED_3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- LED_3_CONFIG -------------------------------- */ +#define LED_3_CONFIG_CONTROL_Pos (0UL) /*!< LED_3 CONFIG: CONTROL (Bit 0) */ +#define LED_3_CONFIG_CONTROL_Msk (0x3UL) /*!< LED_3 CONFIG: CONTROL (Bitfield-Mask: 0x03) */ +#define LED_3_CONFIG_CLOCK_SOURCE_Pos (2UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bit 2) */ +#define LED_3_CONFIG_CLOCK_SOURCE_Msk (0x4UL) /*!< LED_3 CONFIG: CLOCK_SOURCE (Bitfield-Mask: 0x01) */ +#define LED_3_CONFIG_SYNCHRONIZE_Pos (3UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bit 3) */ +#define LED_3_CONFIG_SYNCHRONIZE_Msk (0x8UL) /*!< LED_3 CONFIG: SYNCHRONIZE (Bitfield-Mask: 0x01) */ +#define LED_3_CONFIG_PWM_SIZE_Pos (4UL) /*!< LED_3 CONFIG: PWM_SIZE (Bit 4) */ +#define LED_3_CONFIG_PWM_SIZE_Msk (0x30UL) /*!< LED_3 CONFIG: PWM_SIZE (Bitfield-Mask: 0x03) */ +#define LED_3_CONFIG_ENABLE_UPDATE_Pos (6UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bit 6) */ +#define LED_3_CONFIG_ENABLE_UPDATE_Msk (0x40UL) /*!< LED_3 CONFIG: ENABLE_UPDATE (Bitfield-Mask: 0x01) */ +#define LED_3_CONFIG_RESET_Pos (7UL) /*!< LED_3 CONFIG: RESET (Bit 7) */ +#define LED_3_CONFIG_RESET_Msk (0x80UL) /*!< LED_3 CONFIG: RESET (Bitfield-Mask: 0x01) */ +#define LED_3_CONFIG_WDT_RELOAD_Pos (8UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bit 8) */ +#define LED_3_CONFIG_WDT_RELOAD_Msk (0xff00UL) /*!< LED_3 CONFIG: WDT_RELOAD (Bitfield-Mask: 0xff) */ +#define LED_3_CONFIG_SYMMETRY_Pos (16UL) /*!< LED_3 CONFIG: SYMMETRY (Bit 16) */ +#define LED_3_CONFIG_SYMMETRY_Msk (0x10000UL) /*!< LED_3 CONFIG: SYMMETRY (Bitfield-Mask: 0x01) */ + +/* -------------------------------- LED_3_LIMITS -------------------------------- */ +#define LED_3_LIMITS_MINIMUM_Pos (0UL) /*!< LED_3 LIMITS: MINIMUM (Bit 0) */ +#define LED_3_LIMITS_MINIMUM_Msk (0xffUL) /*!< LED_3 LIMITS: MINIMUM (Bitfield-Mask: 0xff) */ +#define LED_3_LIMITS_MAXIMUM_Pos (8UL) /*!< LED_3 LIMITS: MAXIMUM (Bit 8) */ +#define LED_3_LIMITS_MAXIMUM_Msk (0xff00UL) /*!< LED_3 LIMITS: MAXIMUM (Bitfield-Mask: 0xff) */ + +/* --------------------------------- LED_3_DELAY -------------------------------- */ +#define LED_3_DELAY_LOW_Pos (0UL) /*!< LED_3 DELAY: LOW (Bit 0) */ +#define LED_3_DELAY_LOW_Msk (0xfffUL) /*!< LED_3 DELAY: LOW (Bitfield-Mask: 0xfff) */ +#define LED_3_DELAY_HIGH_Pos (12UL) /*!< LED_3 DELAY: HIGH (Bit 12) */ +#define LED_3_DELAY_HIGH_Msk (0xfff000UL) /*!< LED_3 DELAY: HIGH (Bitfield-Mask: 0xfff) */ + +/* ---------------------------- LED_3_UPDATE_STEPSIZE --------------------------- */ +#define LED_3_UPDATE_STEPSIZE_STEP0_Pos (0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bit 0) */ +#define LED_3_UPDATE_STEPSIZE_STEP0_Msk (0xfUL) /*!< LED_3 UPDATE_STEPSIZE: STEP0 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP1_Pos (4UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bit 4) */ +#define LED_3_UPDATE_STEPSIZE_STEP1_Msk (0xf0UL) /*!< LED_3 UPDATE_STEPSIZE: STEP1 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP2_Pos (8UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bit 8) */ +#define LED_3_UPDATE_STEPSIZE_STEP2_Msk (0xf00UL) /*!< LED_3 UPDATE_STEPSIZE: STEP2 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP3_Pos (12UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bit 12) */ +#define LED_3_UPDATE_STEPSIZE_STEP3_Msk (0xf000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP3 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP4_Pos (16UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bit 16) */ +#define LED_3_UPDATE_STEPSIZE_STEP4_Msk (0xf0000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP4 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP5_Pos (20UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bit 20) */ +#define LED_3_UPDATE_STEPSIZE_STEP5_Msk (0xf00000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP5 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP6_Pos (24UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bit 24) */ +#define LED_3_UPDATE_STEPSIZE_STEP6_Msk (0xf000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP6 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_STEPSIZE_STEP7_Pos (28UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bit 28) */ +#define LED_3_UPDATE_STEPSIZE_STEP7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_STEPSIZE: STEP7 (Bitfield-Mask: 0x0f) */ + +/* ---------------------------- LED_3_UPDATE_INTERVAL --------------------------- */ +#define LED_3_UPDATE_INTERVAL_INTERVAL0_Pos (0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bit 0) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL0_Msk (0xfUL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL0 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL1_Pos (4UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bit 4) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL1_Msk (0xf0UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL1 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL2_Pos (8UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bit 8) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL2_Msk (0xf00UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL2 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL3_Pos (12UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bit 12) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL3_Msk (0xf000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL3 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL4_Pos (16UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bit 16) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL4_Msk (0xf0000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL4 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL5_Pos (20UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bit 20) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL5_Msk (0xf00000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL5 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL6_Pos (24UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bit 24) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL6_Msk (0xf000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL6 (Bitfield-Mask: 0x0f) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL7_Pos (28UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bit 28) */ +#define LED_3_UPDATE_INTERVAL_INTERVAL7_Msk (0xf0000000UL) /*!< LED_3 UPDATE_INTERVAL: INTERVAL7 (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'PS2_0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PS2_0_CONTROL ------------------------------- */ +#define PS2_0_CONTROL_TR_Pos (0UL) /*!< PS2_0 CONTROL: TR (Bit 0) */ +#define PS2_0_CONTROL_TR_Msk (0x1UL) /*!< PS2_0 CONTROL: TR (Bitfield-Mask: 0x01) */ +#define PS2_0_CONTROL_EN_Pos (1UL) /*!< PS2_0 CONTROL: EN (Bit 1) */ +#define PS2_0_CONTROL_EN_Msk (0x2UL) /*!< PS2_0 CONTROL: EN (Bitfield-Mask: 0x01) */ +#define PS2_0_CONTROL_PARITY_Pos (2UL) /*!< PS2_0 CONTROL: PARITY (Bit 2) */ +#define PS2_0_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_0 CONTROL: PARITY (Bitfield-Mask: 0x03) */ +#define PS2_0_CONTROL_STOP_Pos (4UL) /*!< PS2_0 CONTROL: STOP (Bit 4) */ +#define PS2_0_CONTROL_STOP_Msk (0x30UL) /*!< PS2_0 CONTROL: STOP (Bitfield-Mask: 0x03) */ + +/* -------------------------------- PS2_0_STATUS -------------------------------- */ +#define PS2_0_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_0 STATUS: RDATA_RDY (Bit 0) */ +#define PS2_0_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_0 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bit 1) */ +#define PS2_0_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_0 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_PE_Pos (2UL) /*!< PS2_0 STATUS: PE (Bit 2) */ +#define PS2_0_STATUS_PE_Msk (0x4UL) /*!< PS2_0 STATUS: PE (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_FE_Pos (3UL) /*!< PS2_0 STATUS: FE (Bit 3) */ +#define PS2_0_STATUS_FE_Msk (0x8UL) /*!< PS2_0 STATUS: FE (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bit 4) */ +#define PS2_0_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_0 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bit 5) */ +#define PS2_0_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_0 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_0 STATUS: RX_BUSY (Bit 6) */ +#define PS2_0_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_0 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ +#define PS2_0_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bit 7) */ +#define PS2_0_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_0 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'PS2_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PS2_1_CONTROL ------------------------------- */ +#define PS2_1_CONTROL_TR_Pos (0UL) /*!< PS2_1 CONTROL: TR (Bit 0) */ +#define PS2_1_CONTROL_TR_Msk (0x1UL) /*!< PS2_1 CONTROL: TR (Bitfield-Mask: 0x01) */ +#define PS2_1_CONTROL_EN_Pos (1UL) /*!< PS2_1 CONTROL: EN (Bit 1) */ +#define PS2_1_CONTROL_EN_Msk (0x2UL) /*!< PS2_1 CONTROL: EN (Bitfield-Mask: 0x01) */ +#define PS2_1_CONTROL_PARITY_Pos (2UL) /*!< PS2_1 CONTROL: PARITY (Bit 2) */ +#define PS2_1_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_1 CONTROL: PARITY (Bitfield-Mask: 0x03) */ +#define PS2_1_CONTROL_STOP_Pos (4UL) /*!< PS2_1 CONTROL: STOP (Bit 4) */ +#define PS2_1_CONTROL_STOP_Msk (0x30UL) /*!< PS2_1 CONTROL: STOP (Bitfield-Mask: 0x03) */ + +/* -------------------------------- PS2_1_STATUS -------------------------------- */ +#define PS2_1_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_1 STATUS: RDATA_RDY (Bit 0) */ +#define PS2_1_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_1 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bit 1) */ +#define PS2_1_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_1 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_PE_Pos (2UL) /*!< PS2_1 STATUS: PE (Bit 2) */ +#define PS2_1_STATUS_PE_Msk (0x4UL) /*!< PS2_1 STATUS: PE (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_FE_Pos (3UL) /*!< PS2_1 STATUS: FE (Bit 3) */ +#define PS2_1_STATUS_FE_Msk (0x8UL) /*!< PS2_1 STATUS: FE (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bit 4) */ +#define PS2_1_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_1 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bit 5) */ +#define PS2_1_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_1 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_1 STATUS: RX_BUSY (Bit 6) */ +#define PS2_1_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_1 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ +#define PS2_1_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bit 7) */ +#define PS2_1_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_1 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'PS2_2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PS2_2_CONTROL ------------------------------- */ +#define PS2_2_CONTROL_TR_Pos (0UL) /*!< PS2_2 CONTROL: TR (Bit 0) */ +#define PS2_2_CONTROL_TR_Msk (0x1UL) /*!< PS2_2 CONTROL: TR (Bitfield-Mask: 0x01) */ +#define PS2_2_CONTROL_EN_Pos (1UL) /*!< PS2_2 CONTROL: EN (Bit 1) */ +#define PS2_2_CONTROL_EN_Msk (0x2UL) /*!< PS2_2 CONTROL: EN (Bitfield-Mask: 0x01) */ +#define PS2_2_CONTROL_PARITY_Pos (2UL) /*!< PS2_2 CONTROL: PARITY (Bit 2) */ +#define PS2_2_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_2 CONTROL: PARITY (Bitfield-Mask: 0x03) */ +#define PS2_2_CONTROL_STOP_Pos (4UL) /*!< PS2_2 CONTROL: STOP (Bit 4) */ +#define PS2_2_CONTROL_STOP_Msk (0x30UL) /*!< PS2_2 CONTROL: STOP (Bitfield-Mask: 0x03) */ + +/* -------------------------------- PS2_2_STATUS -------------------------------- */ +#define PS2_2_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_2 STATUS: RDATA_RDY (Bit 0) */ +#define PS2_2_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_2 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bit 1) */ +#define PS2_2_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_2 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_PE_Pos (2UL) /*!< PS2_2 STATUS: PE (Bit 2) */ +#define PS2_2_STATUS_PE_Msk (0x4UL) /*!< PS2_2 STATUS: PE (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_FE_Pos (3UL) /*!< PS2_2 STATUS: FE (Bit 3) */ +#define PS2_2_STATUS_FE_Msk (0x8UL) /*!< PS2_2 STATUS: FE (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bit 4) */ +#define PS2_2_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_2 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bit 5) */ +#define PS2_2_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_2 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_2 STATUS: RX_BUSY (Bit 6) */ +#define PS2_2_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_2 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ +#define PS2_2_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bit 7) */ +#define PS2_2_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_2 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'PS2_3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- PS2_3_CONTROL ------------------------------- */ +#define PS2_3_CONTROL_TR_Pos (0UL) /*!< PS2_3 CONTROL: TR (Bit 0) */ +#define PS2_3_CONTROL_TR_Msk (0x1UL) /*!< PS2_3 CONTROL: TR (Bitfield-Mask: 0x01) */ +#define PS2_3_CONTROL_EN_Pos (1UL) /*!< PS2_3 CONTROL: EN (Bit 1) */ +#define PS2_3_CONTROL_EN_Msk (0x2UL) /*!< PS2_3 CONTROL: EN (Bitfield-Mask: 0x01) */ +#define PS2_3_CONTROL_PARITY_Pos (2UL) /*!< PS2_3 CONTROL: PARITY (Bit 2) */ +#define PS2_3_CONTROL_PARITY_Msk (0xcUL) /*!< PS2_3 CONTROL: PARITY (Bitfield-Mask: 0x03) */ +#define PS2_3_CONTROL_STOP_Pos (4UL) /*!< PS2_3 CONTROL: STOP (Bit 4) */ +#define PS2_3_CONTROL_STOP_Msk (0x30UL) /*!< PS2_3 CONTROL: STOP (Bitfield-Mask: 0x03) */ + +/* -------------------------------- PS2_3_STATUS -------------------------------- */ +#define PS2_3_STATUS_RDATA_RDY_Pos (0UL) /*!< PS2_3 STATUS: RDATA_RDY (Bit 0) */ +#define PS2_3_STATUS_RDATA_RDY_Msk (0x1UL) /*!< PS2_3 STATUS: RDATA_RDY (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_REC_TIMEOUT_Pos (1UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bit 1) */ +#define PS2_3_STATUS_REC_TIMEOUT_Msk (0x2UL) /*!< PS2_3 STATUS: REC_TIMEOUT (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_PE_Pos (2UL) /*!< PS2_3 STATUS: PE (Bit 2) */ +#define PS2_3_STATUS_PE_Msk (0x4UL) /*!< PS2_3 STATUS: PE (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_FE_Pos (3UL) /*!< PS2_3 STATUS: FE (Bit 3) */ +#define PS2_3_STATUS_FE_Msk (0x8UL) /*!< PS2_3 STATUS: FE (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_XMIT_IDLE_Pos (4UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bit 4) */ +#define PS2_3_STATUS_XMIT_IDLE_Msk (0x10UL) /*!< PS2_3 STATUS: XMIT_IDLE (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_XMIT_TIME_OUT_Pos (5UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bit 5) */ +#define PS2_3_STATUS_XMIT_TIME_OUT_Msk (0x20UL) /*!< PS2_3 STATUS: XMIT_TIME_OUT (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_RX_BUSY_Pos (6UL) /*!< PS2_3 STATUS: RX_BUSY (Bit 6) */ +#define PS2_3_STATUS_RX_BUSY_Msk (0x40UL) /*!< PS2_3 STATUS: RX_BUSY (Bitfield-Mask: 0x01) */ +#define PS2_3_STATUS_XMIT_START_TIMEOUT_Pos (7UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bit 7) */ +#define PS2_3_STATUS_XMIT_START_TIMEOUT_Msk (0x80UL) /*!< PS2_3 STATUS: XMIT_START_TIMEOUT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'KEYSCAN' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- KEYSCAN_CONTROL ------------------------------ */ +#define KEYSCAN_CONTROL_SELECT_Pos (0UL) /*!< KEYSCAN CONTROL: SELECT (Bit 0) */ +#define KEYSCAN_CONTROL_SELECT_Msk (0x1fUL) /*!< KEYSCAN CONTROL: SELECT (Bitfield-Mask: 0x1f) */ +#define KEYSCAN_CONTROL_ALL_Pos (5UL) /*!< KEYSCAN CONTROL: ALL (Bit 5) */ +#define KEYSCAN_CONTROL_ALL_Msk (0x20UL) /*!< KEYSCAN CONTROL: ALL (Bitfield-Mask: 0x01) */ +#define KEYSCAN_CONTROL_KSEN_Pos (6UL) /*!< KEYSCAN CONTROL: KSEN (Bit 6) */ +#define KEYSCAN_CONTROL_KSEN_Msk (0x40UL) /*!< KEYSCAN CONTROL: KSEN (Bitfield-Mask: 0x01) */ +#define KEYSCAN_CONTROL_INVERT_Pos (7UL) /*!< KEYSCAN CONTROL: INVERT (Bit 7) */ +#define KEYSCAN_CONTROL_INVERT_Msk (0x80UL) /*!< KEYSCAN CONTROL: INVERT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'BC_LINK' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- BC_LINK_STATUS ------------------------------- */ +#define BC_LINK_STATUS_BUSY_Pos (0UL) /*!< BC_LINK STATUS: BUSY (Bit 0) */ +#define BC_LINK_STATUS_BUSY_Msk (0x1UL) /*!< BC_LINK STATUS: BUSY (Bitfield-Mask: 0x01) */ +#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Pos (4UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bit 4) */ +#define BC_LINK_STATUS_BUSY_CLR_INT_EN_Msk (0x10UL) /*!< BC_LINK STATUS: BUSY_CLR_INT_EN (Bitfield-Mask: 0x01) */ +#define BC_LINK_STATUS_ERR_INT_EN_Pos (5UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bit 5) */ +#define BC_LINK_STATUS_ERR_INT_EN_Msk (0x20UL) /*!< BC_LINK STATUS: ERR_INT_EN (Bitfield-Mask: 0x01) */ +#define BC_LINK_STATUS_ERROR_Pos (6UL) /*!< BC_LINK STATUS: ERROR (Bit 6) */ +#define BC_LINK_STATUS_ERROR_Msk (0x40UL) /*!< BC_LINK STATUS: ERROR (Bitfield-Mask: 0x01) */ +#define BC_LINK_STATUS_RESET_Pos (7UL) /*!< BC_LINK STATUS: RESET (Bit 7) */ +#define BC_LINK_STATUS_RESET_Msk (0x80UL) /*!< BC_LINK STATUS: RESET (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'TFDP' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- TFDP_CONTROL -------------------------------- */ +#define TFDP_CONTROL_EN_Pos (0UL) /*!< TFDP CONTROL: EN (Bit 0) */ +#define TFDP_CONTROL_EN_Msk (0x1UL) /*!< TFDP CONTROL: EN (Bitfield-Mask: 0x01) */ +#define TFDP_CONTROL_EDGE_SEL_Pos (1UL) /*!< TFDP CONTROL: EDGE_SEL (Bit 1) */ +#define TFDP_CONTROL_EDGE_SEL_Msk (0x2UL) /*!< TFDP CONTROL: EDGE_SEL (Bitfield-Mask: 0x01) */ +#define TFDP_CONTROL_DIVSEL_Pos (2UL) /*!< TFDP CONTROL: DIVSEL (Bit 2) */ +#define TFDP_CONTROL_DIVSEL_Msk (0xcUL) /*!< TFDP CONTROL: DIVSEL (Bitfield-Mask: 0x03) */ +#define TFDP_CONTROL_IP_DELAY_Pos (4UL) /*!< TFDP CONTROL: IP_DELAY (Bit 4) */ +#define TFDP_CONTROL_IP_DELAY_Msk (0x70UL) /*!< TFDP CONTROL: IP_DELAY (Bitfield-Mask: 0x07) */ + + +/* ================================================================================ */ +/* ================ struct 'ADC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- ADC_CONTROL -------------------------------- */ +#define ADC_CONTROL_ACTIVATE_Pos (0UL) /*!< ADC CONTROL: ACTIVATE (Bit 0) */ +#define ADC_CONTROL_ACTIVATE_Msk (0x1UL) /*!< ADC CONTROL: ACTIVATE (Bitfield-Mask: 0x01) */ +#define ADC_CONTROL_START_SINGLE_Pos (1UL) /*!< ADC CONTROL: START_SINGLE (Bit 1) */ +#define ADC_CONTROL_START_SINGLE_Msk (0x2UL) /*!< ADC CONTROL: START_SINGLE (Bitfield-Mask: 0x01) */ +#define ADC_CONTROL_START_REPEAT_Pos (2UL) /*!< ADC CONTROL: START_REPEAT (Bit 2) */ +#define ADC_CONTROL_START_REPEAT_Msk (0x4UL) /*!< ADC CONTROL: START_REPEAT (Bitfield-Mask: 0x01) */ +#define ADC_CONTROL_POWER_SAVER_DIS_Pos (3UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bit 3) */ +#define ADC_CONTROL_POWER_SAVER_DIS_Msk (0x8UL) /*!< ADC CONTROL: POWER_SAVER_DIS (Bitfield-Mask: 0x01) */ +#define ADC_CONTROL_SOFT_RESET_Pos (4UL) /*!< ADC CONTROL: SOFT_RESET (Bit 4) */ +#define ADC_CONTROL_SOFT_RESET_Msk (0x10UL) /*!< ADC CONTROL: SOFT_RESET (Bitfield-Mask: 0x01) */ +#define ADC_CONTROL_REPEAT_DONE_STAT_Pos (6UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bit 6) */ +#define ADC_CONTROL_REPEAT_DONE_STAT_Msk (0x40UL) /*!< ADC CONTROL: REPEAT_DONE_STAT (Bitfield-Mask: 0x01) */ +#define ADC_CONTROL_SINGLE_DONE_STAT_Pos (7UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bit 7) */ +#define ADC_CONTROL_SINGLE_DONE_STAT_Msk (0x80UL) /*!< ADC CONTROL: SINGLE_DONE_STAT (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- ADC_DELAY --------------------------------- */ +#define ADC_DELAY_START_Pos (0UL) /*!< ADC DELAY: START (Bit 0) */ +#define ADC_DELAY_START_Msk (0xffffUL) /*!< ADC DELAY: START (Bitfield-Mask: 0xffff) */ +#define ADC_DELAY_REPEAT_Pos (16UL) /*!< ADC DELAY: REPEAT (Bit 16) */ +#define ADC_DELAY_REPEAT_Msk (0xffff0000UL) /*!< ADC DELAY: REPEAT (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- ADC_STATUS --------------------------------- */ +#define ADC_STATUS_CH0_Pos (0UL) /*!< ADC STATUS: CH0 (Bit 0) */ +#define ADC_STATUS_CH0_Msk (0x1UL) /*!< ADC STATUS: CH0 (Bitfield-Mask: 0x01) */ +#define ADC_STATUS_CH1_Pos (1UL) /*!< ADC STATUS: CH1 (Bit 1) */ +#define ADC_STATUS_CH1_Msk (0x2UL) /*!< ADC STATUS: CH1 (Bitfield-Mask: 0x01) */ +#define ADC_STATUS_CH2_Pos (2UL) /*!< ADC STATUS: CH2 (Bit 2) */ +#define ADC_STATUS_CH2_Msk (0x4UL) /*!< ADC STATUS: CH2 (Bitfield-Mask: 0x01) */ +#define ADC_STATUS_CH3_Pos (3UL) /*!< ADC STATUS: CH3 (Bit 3) */ +#define ADC_STATUS_CH3_Msk (0x8UL) /*!< ADC STATUS: CH3 (Bitfield-Mask: 0x01) */ +#define ADC_STATUS_CH4_Pos (4UL) /*!< ADC STATUS: CH4 (Bit 4) */ +#define ADC_STATUS_CH4_Msk (0x10UL) /*!< ADC STATUS: CH4 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- ADC_SINGLE_EN ------------------------------- */ +#define ADC_SINGLE_EN_CH0_Pos (0UL) /*!< ADC SINGLE_EN: CH0 (Bit 0) */ +#define ADC_SINGLE_EN_CH0_Msk (0x1UL) /*!< ADC SINGLE_EN: CH0 (Bitfield-Mask: 0x01) */ +#define ADC_SINGLE_EN_CH1_Pos (1UL) /*!< ADC SINGLE_EN: CH1 (Bit 1) */ +#define ADC_SINGLE_EN_CH1_Msk (0x2UL) /*!< ADC SINGLE_EN: CH1 (Bitfield-Mask: 0x01) */ +#define ADC_SINGLE_EN_CH2_Pos (2UL) /*!< ADC SINGLE_EN: CH2 (Bit 2) */ +#define ADC_SINGLE_EN_CH2_Msk (0x4UL) /*!< ADC SINGLE_EN: CH2 (Bitfield-Mask: 0x01) */ +#define ADC_SINGLE_EN_CH3_Pos (3UL) /*!< ADC SINGLE_EN: CH3 (Bit 3) */ +#define ADC_SINGLE_EN_CH3_Msk (0x8UL) /*!< ADC SINGLE_EN: CH3 (Bitfield-Mask: 0x01) */ +#define ADC_SINGLE_EN_CH4_Pos (4UL) /*!< ADC SINGLE_EN: CH4 (Bit 4) */ +#define ADC_SINGLE_EN_CH4_Msk (0x10UL) /*!< ADC SINGLE_EN: CH4 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- ADC_REPEAT --------------------------------- */ +#define ADC_REPEAT_CH0_Pos (0UL) /*!< ADC REPEAT: CH0 (Bit 0) */ +#define ADC_REPEAT_CH0_Msk (0x1UL) /*!< ADC REPEAT: CH0 (Bitfield-Mask: 0x01) */ +#define ADC_REPEAT_CH1_Pos (1UL) /*!< ADC REPEAT: CH1 (Bit 1) */ +#define ADC_REPEAT_CH1_Msk (0x2UL) /*!< ADC REPEAT: CH1 (Bitfield-Mask: 0x01) */ +#define ADC_REPEAT_CH2_Pos (2UL) /*!< ADC REPEAT: CH2 (Bit 2) */ +#define ADC_REPEAT_CH2_Msk (0x4UL) /*!< ADC REPEAT: CH2 (Bitfield-Mask: 0x01) */ +#define ADC_REPEAT_CH3_Pos (3UL) /*!< ADC REPEAT: CH3 (Bit 3) */ +#define ADC_REPEAT_CH3_Msk (0x8UL) /*!< ADC REPEAT: CH3 (Bitfield-Mask: 0x01) */ +#define ADC_REPEAT_CH4_Pos (4UL) /*!< ADC REPEAT: CH4 (Bit 4) */ +#define ADC_REPEAT_CH4_Msk (0x10UL) /*!< ADC REPEAT: CH4 (Bitfield-Mask: 0x01) */ + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define PCR_BASE 0x40080100UL +#define VBAT_BASE 0x4000A400UL +#define LPC_BASE 0x400F3000UL +#define LPC_CONFIG_BASE 0x400F3300UL +#define GCR_BASE 0x400FFF00UL +#define EMI_BASE 0x400F0000UL +#define ACPI_EC0_BASE 0x400F0C00UL +#define ACPI_EC1_BASE 0x400F1000UL +#define KBC_BASE 0x400F0400UL +#define PORT92_BASE 0x400F1800UL +#define MBX_BASE 0x400F2400UL +#define PM1_BASE 0x400F1400UL +#define UART_BASE 0x400F1C00UL +#define INTR_BASE 0x4000C000UL +#define WDT_BASE 0x40000400UL +#define TIMER_16_0_BASE 0x40000C00UL +#define TIMER_16_1_BASE 0x40000C20UL +#define TIMER_16_2_BASE 0x40000C40UL +#define TIMER_16_3_BASE 0x40000C60UL +#define TIMER_32_0_BASE 0x40000C80UL +#define TIMER_32_1_BASE 0x40000CA0UL +#define HTM_BASE 0x40009800UL +#define RTC_BASE 0x400F2C00UL +#define GPIO_BASE 0x40081000UL +#define DMA_BASE 0x40002400UL +#define SMB0_BASE 0x40001800UL +#define SMB1_BASE 0x4000AC00UL +#define SMB2_BASE 0x4000B000UL +#define SMB3_BASE 0x4000B400UL +#define PECI_BASE 0x40006400UL +#define TACH_0_BASE 0x40006000UL +#define TACH_1_BASE 0x40006100UL +#define PWM_0_BASE 0x40005800UL +#define PWM_1_BASE 0x40005810UL +#define PWM_2_BASE 0x40005820UL +#define PWM_3_BASE 0x40005830UL +#define RPM_FAN_BASE 0x4000A000UL +#define SPI_0_BASE 0x40009400UL +#define SPI_1_BASE 0x40009480UL +#define LED_0_BASE 0x4000B800UL +#define LED_1_BASE 0x4000B900UL +#define LED_2_BASE 0x4000BA00UL +#define LED_3_BASE 0x4000BB00UL +#define PS2_0_BASE 0x40009000UL +#define PS2_1_BASE 0x40009040UL +#define PS2_2_BASE 0x40009080UL +#define PS2_3_BASE 0x400090C0UL +#define KEYSCAN_BASE 0x40009C00UL +#define BC_LINK_BASE 0x4000BC00UL +#define TFDP_BASE 0x40008C00UL +#define ADC_BASE 0x40007C00UL +#define EC_REG_BANK_BASE 0x4000FC00UL +#define JTAG_BASE 0x40080000UL +#define PKE_BASE 0x4000BD00UL +#define TRNG_BASE 0x4000BE00UL +#define HASH_BASE 0x4000D000UL +#define AES_BASE 0x4000D200UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define CEC1302_PCR ((PCR_Type *) PCR_BASE) +#define CEC1302_VBAT ((VBAT_Type *) VBAT_BASE) +#define CEC1302_LPC ((LPC_Type *) LPC_BASE) +#define CEC1302_LPC_CONFIG ((LPC_CONFIG_Type *) LPC_CONFIG_BASE) +#define CEC1302_GCR ((GCR_Type *) GCR_BASE) +#define CEC1302_EMI ((EMI_Type *) EMI_BASE) +#define CEC1302_ACPI_EC0 ((ACPI_EC0_Type *) ACPI_EC0_BASE) +#define CEC1302_ACPI_EC1 ((ACPI_EC0_Type *) ACPI_EC1_BASE) +#define CEC1302_KBC ((KBC_Type *) KBC_BASE) +#define CEC1302_PORT92 ((PORT92_Type *) PORT92_BASE) +#define CEC1302_MBX ((MBX_Type *) MBX_BASE) +#define CEC1302_PM1 ((PM1_Type *) PM1_BASE) +#define CEC1302_UART ((UART_Type *) UART_BASE) +#define CEC1302_INTR ((INTR_Type *) INTR_BASE) +#define CEC1302_WDT ((WDT_Type *) WDT_BASE) +#define CEC1302_TIMER_16_0 ((TIMER_16_0_Type *) TIMER_16_0_BASE) +#define CEC1302_TIMER_16_1 ((TIMER_16_0_Type *) TIMER_16_1_BASE) +#define CEC1302_TIMER_16_2 ((TIMER_16_0_Type *) TIMER_16_2_BASE) +#define CEC1302_TIMER_16_3 ((TIMER_16_0_Type *) TIMER_16_3_BASE) +#define CEC1302_TIMER_32_0 ((TIMER_16_0_Type *) TIMER_32_0_BASE) +#define CEC1302_TIMER_32_1 ((TIMER_16_0_Type *) TIMER_32_1_BASE) +#define CEC1302_HTM ((HTM_Type *) HTM_BASE) +#define CEC1302_RTC ((RTC_Type *) RTC_BASE) +#define CEC1302_GPIO ((GPIO_Type *) GPIO_BASE) +#define CEC1302_DMA ((DMA_Type *) DMA_BASE) +#define CEC1302_SMB0 ((SMB0_Type *) SMB0_BASE) +#define CEC1302_SMB1 ((SMB0_Type *) SMB1_BASE) +#define CEC1302_SMB2 ((SMB0_Type *) SMB2_BASE) +#define CEC1302_SMB3 ((SMB0_Type *) SMB3_BASE) +#define CEC1302_PECI ((PECI_Type *) PECI_BASE) +#define CEC1302_TACH_0 ((TACH_0_Type *) TACH_0_BASE) +#define CEC1302_TACH_1 ((TACH_0_Type *) TACH_1_BASE) +#define CEC1302_PWM_0 ((PWM_0_Type *) PWM_0_BASE) +#define CEC1302_PWM_1 ((PWM_0_Type *) PWM_1_BASE) +#define CEC1302_PWM_2 ((PWM_0_Type *) PWM_2_BASE) +#define CEC1302_PWM_3 ((PWM_0_Type *) PWM_3_BASE) +#define CEC1302_RPM_FAN ((RPM_FAN_Type *) RPM_FAN_BASE) +#define CEC1302_SPI_0 ((SPI_0_Type *) SPI_0_BASE) +#define CEC1302_SPI_1 ((SPI_0_Type *) SPI_1_BASE) +#define CEC1302_LED_0 ((LED_0_Type *) LED_0_BASE) +#define CEC1302_LED_1 ((LED_0_Type *) LED_1_BASE) +#define CEC1302_LED_2 ((LED_0_Type *) LED_2_BASE) +#define CEC1302_LED_3 ((LED_0_Type *) LED_3_BASE) +#define CEC1302_PS2_0 ((PS2_0_Type *) PS2_0_BASE) +#define CEC1302_PS2_1 ((PS2_0_Type *) PS2_1_BASE) +#define CEC1302_PS2_2 ((PS2_0_Type *) PS2_2_BASE) +#define CEC1302_PS2_3 ((PS2_0_Type *) PS2_3_BASE) +#define CEC1302_KEYSCAN ((KEYSCAN_Type *) KEYSCAN_BASE) +#define CEC1302_BC_LINK ((BC_LINK_Type *) BC_LINK_BASE) +#define CEC1302_TFDP ((TFDP_Type *) TFDP_BASE) +#define CEC1302_ADC ((ADC_Type *) ADC_BASE) +#define CEC1302_EC_REG_BANK ((EC_REG_BANK_Type *) EC_REG_BANK_BASE) +#define CEC1302_JTAG ((JTAG_Type *) JTAG_BASE) +#define CEC1302_PKE ((PKE_TypeDef *) PKE_BASE) +#define CEC1302_TRNG ((TRNG_TypeDef *) TRNG_BASE) +#define CEC1302_HASH ((HASH_TypeDef *) HASH_BASE) +#define CEC1302_AES ((AES_TypeDef *) AES_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group MCHP_CEC1302 */ +/** @} */ /* End of group Microchip Technology Inc. */ + +#ifdef __cplusplus +} +#endif + + +#endif /* MCHP_CEC1302_H */ + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MEC1322.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MEC1322.h new file mode 100644 index 000000000..91f3c8ead --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/MEC1322.h @@ -0,0 +1,2862 @@ +/******************************************************************************* +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +******************************************************************************** + +Version Control Information (Perforce) +$File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $ +******************************************************************************** +$Revision: #1 $ +$DateTime: 2015/12/23 15:37:58 $ +$Author: akrishnan $ + Change Description: Initial revision for MEC1322 +******************************************************************************/ +/** @file smscmmcr.h +* brief the mmcr definitions +* +******************************************************************************/ +#ifndef SMSCMMCR_H_ +#define SMSCMMCR_H_ + +//NOTE: Please Don't edit this File, this is extrated from the Spread sheet +// : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv +typedef volatile unsigned char VUINT8; +typedef volatile unsigned short int VUINT16; +typedef volatile unsigned long int VUINT32; + +/*************************************************************** +* PWM +***************************************************************/ +#define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800 +#define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME)) + +#define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804 +#define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME)) + +#define ADDR_PWM_0_CONFIGURATION 0x40005808 +#define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION)) + +#define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810 +#define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME)) + +#define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814 +#define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME)) + +#define ADDR_PWM_1_CONFIGURATION 0x40005818 +#define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION)) + +#define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820 +#define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME)) + +#define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824 +#define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME)) + +#define ADDR_PWM_2_CONFIGURATION 0x40005828 +#define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION)) + +#define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830 +#define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME)) + +#define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834 +#define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME)) + +#define ADDR_PWM_3_CONFIGURATION 0x40005838 +#define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION)) + +/*************************************************************** +* PECI +***************************************************************/ +#define ADDR_PECI_WRITE_DATA 0x40006400 +#define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA)) + +#define ADDR_PECI_READ_DATA 0x40006404 +#define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA)) + +#define ADDR_PECI_CONTROL 0x40006408 +#define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL)) + +#define ADDR_PECI_STATUS_1 0x4000640C +#define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1)) + +#define ADDR_PECI_STATUS_2 0x40006410 +#define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2)) + +#define ADDR_PECI_ERROR 0x40006414 +#define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR)) + +#define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418 +#define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1)) + +#define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C +#define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2)) + +#define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420 +#define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE)) + +#define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424 +#define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE)) + +#define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428 +#define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE)) + +#define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C +#define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE)) + +#define ADDR_PECI_BLOCK_ID 0x40006440 +#define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID)) + +#define ADDR_PECI_BLOCK_REVISION 0x40006444 +#define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION)) + +/*************************************************************** +* ACPI EC Interface +***************************************************************/ +#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00 +#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0)) + +#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01 +#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1)) + +#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02 +#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2)) + +#define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03 +#define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3)) + +#define ADDR_ACPI_0_STATUS_EC 0x400F0D04 +#define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC)) + +#define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05 +#define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC)) + +#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08 +#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0)) + +#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08 +#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0)) + +#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09 +#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1)) + +#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A +#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2)) + +#define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B +#define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3)) + +#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100 +#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0)) + +#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101 +#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1)) + +#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102 +#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2)) + +#define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103 +#define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3)) + +#define ADDR_ACPI_1_STATUS_EC 0x400F1104 +#define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC)) + +#define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105 +#define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC)) + +#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108 +#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0)) + +#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108 +#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0)) + +#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109 +#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1)) + +#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A +#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2)) + +#define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B +#define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3)) + +/*************************************************************** +* Keyboard Matrix Scan Support +***************************************************************/ +#define ADDR_KEYBOARD_KSO_SELECT 0x40009C04 +#define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT)) + +#define ADDR_KEYBOARD_KSI_INPUT 0x40009C08 +#define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT)) + +#define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C +#define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS)) + +#define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10 +#define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE)) + +#define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14 +#define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL)) + +/*************************************************************** +* PS/2 Device Interface +***************************************************************/ +#define ADDR_PS2_3_STATUS 0x400090C8 +#define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS)) + +#define ADDR_PS2_3_CONTROL 0x400090C4 +#define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL)) + +#define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0 +#define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER)) + +#define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0 +#define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER)) + +#define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000 +#define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER)) + +#define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000 +#define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER)) + +#define ADDR_PS2_0_CONTROL 0x40009004 +#define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL)) + +#define ADDR_PS2_0_STATUS 0x40009008 +#define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS)) + +#define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040 +#define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER)) + +#define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040 +#define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER)) + +#define ADDR_PS2_1_CONTROL 0x40009044 +#define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL)) + +#define ADDR_PS2_1_STATUS 0x40009048 +#define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS)) + +#define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080 +#define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER)) + +#define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080 +#define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER)) + +#define ADDR_PS2_2_CONTROL 0x40009084 +#define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL)) + +#define ADDR_PS2_2_STATUS 0x40009088 +#define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS)) + +/*************************************************************** +* 8042 Host Interface +***************************************************************/ +#define ADDR_8042_ACTIVATE 0x400F0730 +#define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE)) + +#define ADDR_8042_HOST_EC_DATACMD 0x400F0500 +#define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD)) + +#define ADDR_8042_EC_HOST_DATA 0x400F0500 +#define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA)) + +#define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504 +#define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ)) + +#define ADDR_8042_KEYBOARD_CONTROL 0x400F0508 +#define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL)) + +#define ADDR_8042_EC_HOST_AUX 0x400F050C +#define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX)) + +#define ADDR_8042_PCOBF 0x400F0514 +#define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF)) + +#define ADDR_8042_PORT92_ENABLE 0x400F1B30 +#define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE)) + +#define ADDR_8042_GATEA20_CONTROL 0x400F1900 +#define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL)) + +#define ADDR_8042_SETGA20L 0x400F1908 +#define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L)) + +#define ADDR_8042_RSTGA20L 0x400F190C +#define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L)) + +/*************************************************************** +* SMBus +***************************************************************/ +#define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C +#define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB)) + +#define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458 +#define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C)) + +#define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454 +#define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER)) + +#define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450 +#define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER)) + +#define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C +#define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER)) + +#define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448 +#define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER)) + +#define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444 +#define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING)) + +#define ADDR_SMB_3_DATA_TIMING 0x4000B440 +#define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING)) + +#define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C +#define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC)) + +#define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438 +#define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL)) + +#define ADDR_SMB_3_REVISION 0x4000B434 +#define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION)) + +#define ADDR_SMB_3_BLOCK_ID 0x4000B430 +#define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID)) + +#define ADDR_SMB_3_BUS_CLOCK 0x4000B42C +#define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK)) + +#define ADDR_SMB_3_CONFIGURATION 0x4000B428 +#define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION)) + +#define ADDR_SMB_3_IDLE_SCALING 0x4000B424 +#define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING)) + +#define ADDR_SMB_3_COMPLETION 0x4000B420 +#define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION)) + +#define ADDR_SMB_3_DATA_TIMING2 0x4000B418 +#define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2)) + +#define ADDR_SMB_3_PEC 0x4000B414 +#define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC)) + +#define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410 +#define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND)) + +#define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C +#define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND)) + +#define ADDR_SMB_3_DATA 0x4000B408 +#define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA)) + +#define ADDR_SMB_3_OWN_ADDRESS 0x4000B404 +#define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS)) + +#define ADDR_SMB_3_STATUS 0x4000B400 +#define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS)) + +#define ADDR_SMB_3_CONTROL 0x4000B400 +#define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL)) + +#define ADDR_SMB_2_CONTROL 0x4000B000 +#define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL)) + +#define ADDR_SMB_2_STATUS 0x4000B000 +#define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS)) + +#define ADDR_SMB_2_OWN_ADDRESS 0x4000B004 +#define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS)) + +#define ADDR_SMB_2_DATA 0x4000B008 +#define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA)) + +#define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C +#define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND)) + +#define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010 +#define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND)) + +#define ADDR_SMB_2_PEC 0x4000B014 +#define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC)) + +#define ADDR_SMB_2_DATA_TIMING2 0x4000B018 +#define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2)) + +#define ADDR_SMB_2_COMPLETION 0x4000B020 +#define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION)) + +#define ADDR_SMB_2_IDLE_SCALING 0x4000B024 +#define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING)) + +#define ADDR_SMB_2_CONFIGURATION 0x4000B028 +#define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION)) + +#define ADDR_SMB_2_BUS_CLOCK 0x4000B02C +#define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK)) + +#define ADDR_SMB_2_BLOCK_ID 0x4000B030 +#define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID)) + +#define ADDR_SMB_2_REVISION 0x4000B034 +#define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION)) + +#define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038 +#define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL)) + +#define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C +#define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC)) + +#define ADDR_SMB_2_DATA_TIMING 0x4000B040 +#define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING)) + +#define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044 +#define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING)) + +#define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048 +#define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER)) + +#define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C +#define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER)) + +#define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050 +#define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER)) + +#define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054 +#define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER)) + +#define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058 +#define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C)) + +#define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C +#define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB)) + +#define ADDR_SMB_1_CONTROL 0x4000AC00 +#define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL)) + +#define ADDR_SMB_1_STATUS 0x4000AC00 +#define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS)) + +#define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04 +#define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS)) + +#define ADDR_SMB_1_DATA 0x4000AC08 +#define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA)) + +#define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C +#define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND)) + +#define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10 +#define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND)) + +#define ADDR_SMB_1_PEC 0x4000AC14 +#define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC)) + +#define ADDR_SMB_1_DATA_TIMING2 0x4000AC18 +#define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2)) + +#define ADDR_SMB_1_COMPLETION 0x4000AC20 +#define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION)) + +#define ADDR_SMB_1_IDLE_SCALING 0x4000AC24 +#define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING)) + +#define ADDR_SMB_1_CONFIGURATION 0x4000AC28 +#define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION)) + +#define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C +#define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK)) + +#define ADDR_SMB_1_BLOCK_ID 0x4000AC30 +#define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID)) + +#define ADDR_SMB_1_REVISION 0x4000AC34 +#define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION)) + +#define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38 +#define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL)) + +#define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C +#define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC)) + +#define ADDR_SMB_1_DATA_TIMING 0x4000AC40 +#define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING)) + +#define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44 +#define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING)) + +#define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48 +#define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER)) + +#define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C +#define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER)) + +#define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50 +#define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER)) + +#define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54 +#define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER)) + +#define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58 +#define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C)) + +#define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C +#define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB)) + +#define ADDR_SMB_0_STATUS 0x40001800 +#define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS)) + +#define ADDR_SMB_0_CONTROL 0x40001800 +#define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL)) + +#define ADDR_SMB_0_OWN_ADDRESS 0x40001804 +#define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS)) + +#define ADDR_SMB_0_DATA 0x40001808 +#define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA)) + +#define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C +#define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND)) + +#define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810 +#define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND)) + +#define ADDR_SMB_0_PEC 0x40001814 +#define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC)) + +#define ADDR_SMB_0_DATA_TIMING2 0x40001818 +#define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2)) + +#define ADDR_SMB_0_COMPLETION 0x40001820 +#define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION)) + +#define ADDR_SMB_0_IDLE_SCALING 0x40001824 +#define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING)) + +#define ADDR_SMB_0_CONFIGURATION 0x40001828 +#define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION)) + +#define ADDR_SMB_0_BUS_CLOCK 0x4000182C +#define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK)) + +#define ADDR_SMB_0_BLOCK_ID 0x40001830 +#define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID)) + +#define ADDR_SMB_0_REVISION 0x40001834 +#define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION)) + +#define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838 +#define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL)) + +#define ADDR_SMB_0_CLOCK_SYNC 0x4000183C +#define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC)) + +#define ADDR_SMB_0_DATA_TIMING 0x40001840 +#define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING)) + +#define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844 +#define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING)) + +#define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848 +#define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER)) + +#define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C +#define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER)) + +#define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850 +#define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER)) + +#define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854 +#define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER)) + +#define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858 +#define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C)) + +#define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C +#define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB)) + +/*************************************************************** +* Watchdog Timer Interface +***************************************************************/ +#define ADDR_WATCHDOG_WDT_LOAD 0x40000400 +#define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD)) + +#define ADDR_WATCHDOG_WDT_CONTROL 0x40000404 +#define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL)) + +#define ADDR_WATCHDOG_WDT_KICK 0x40000408 +#define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK)) + +#define ADDR_WATCHDOG_WDT_COUNT 0x4000040C +#define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT)) + +/*************************************************************** +* ACPI PM1 +***************************************************************/ +#define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500 +#define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1)) + +#define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501 +#define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2)) + +#define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502 +#define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1)) + +#define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503 +#define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2)) + +#define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504 +#define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1)) + +#define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505 +#define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2)) + +#define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506 +#define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1)) + +#define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507 +#define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2)) + +#define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510 +#define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS)) + +/*************************************************************** +* EC GP-SPI +***************************************************************/ +#define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498 +#define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR)) + +#define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494 +#define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL)) + +#define ADDR_EC_1_SPI_RX_DATA 0x40009490 +#define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA)) + +#define ADDR_EC_1_SPI_TX_DATA 0x4000948C +#define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA)) + +#define ADDR_EC_1_SPI_STATUS 0x40009488 +#define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS)) + +#define ADDR_EC_1_SPI_CONTROL 0x40009484 +#define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL)) + +#define ADDR_EC_1_SPI_ENABLE 0x40009480 +#define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE)) + +#define ADDR_EC_0_SPI_ENABLE 0x40009400 +#define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE)) + +#define ADDR_EC_0_SPI_CONTROL 0x40009404 +#define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL)) + +#define ADDR_EC_0_SPI_STATUS 0x40009408 +#define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS)) + +#define ADDR_EC_0_SPI_TX_DATA 0x4000940C +#define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA)) + +#define ADDR_EC_0_SPI_RX_DATA 0x40009410 +#define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA)) + +#define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414 +#define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL)) + +#define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418 +#define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR)) + +/*************************************************************** +* Mailbox Registers Interface +***************************************************************/ +#define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500 +#define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX)) + +#define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504 +#define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX)) + +#define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508 +#define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE)) + +#define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C +#define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK)) + +#define ADDR_MAILBOX_3_0 0x400F2510 +#define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0)) + +#define ADDR_MAILBOX_7_4 0x400F2514 +#define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4)) + +#define ADDR_MAILBOX_BH_8 0x400F2518 +#define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8)) + +#define ADDR_MAILBOX_FH_CH 0x400F251C +#define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH)) + +#define ADDR_MAILBOX_13H_10H 0x400F2520 +#define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H)) + +#define ADDR_MAILBOX_17H_14H 0x400F2524 +#define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H)) + +#define ADDR_MAILBOX_1BH_18H 0x400F2528 +#define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H)) + +#define ADDR_MAILBOX_1FH_1CH 0x400F252C +#define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH)) + +/*************************************************************** +* Hibernation Timer +***************************************************************/ +#define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800 +#define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD)) + +#define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804 +#define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL)) + +#define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808 +#define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT)) + +/*************************************************************** +* UART +***************************************************************/ +#define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30 +#define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE)) + +#define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0 +#define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT)) + +#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00 +#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB)) + +#define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00 +#define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER)) + +#define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00 +#define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER)) + +#define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01 +#define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB)) + +#define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01 +#define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE)) + +#define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02 +#define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL)) + +#define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02 +#define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION)) + +#define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03 +#define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL)) + +#define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04 +#define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL)) + +#define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05 +#define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS)) + +#define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06 +#define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS)) + +#define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07 +#define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD)) + +/*************************************************************** +* TACH +***************************************************************/ +#define ADDR_TACH_0_CONTROL 0x40006000 +#define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL)) + +#define ADDR_TACH_0_STATUS 0x40006004 +#define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS)) + +#define ADDR_TACH_0_HIGH_LIMIT 0x40006008 +#define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT)) + +#define ADDR_TACH_0_LOW_LIMIT 0x4000600C +#define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT)) + +#define ADDR_TACH_1_CONTROL 0x40006010 +#define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL)) + +#define ADDR_TACH_1_STATUS 0x40006014 +#define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS)) + +#define ADDR_TACH_1_HIGH_LIMIT 0x40006018 +#define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT)) + +#define ADDR_TACH_1_LOW_LIMIT 0x4000601C +#define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT)) + +/*************************************************************** +* Global Config Regs Basic +***************************************************************/ +#define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07 +#define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER)) + +#define ADDR_GLOBAL_DEVICE_ID 0x400FFF20 +#define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID)) + +#define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21 +#define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED)) + +#define ADDR_GLOBAL_GCR_BUILD 0x400FFF28 +#define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD)) + +#define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C +#define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH)) + +/*************************************************************** +* Trace FIFO Debug Port +***************************************************************/ +#define ADDR_TRACE_DATA 0x40008C00 +#define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA)) + +#define ADDR_TRACE_CONTROL 0x40008C04 +#define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL)) + +/*************************************************************** +* STAP +***************************************************************/ +#define ADDR_STAP_MESSAGE_OBF 0x40080000 +#define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF)) + +#define ADDR_STAP_MESSAGE_IBF 0x40080004 +#define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF)) + +#define ADDR_STAP_OBF_STATUS 0x40080008 +#define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS)) + +#define ADDR_STAP_IBF_STATUS 0x40080009 +#define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS)) + +#define ADDR_STAP_DBG_CTRL 0x4008000C +#define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL)) + +/*************************************************************** +* EMI +***************************************************************/ +#define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100 +#define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX)) + +#define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101 +#define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX)) + +#define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104 +#define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0)) + +#define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108 +#define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0)) + +#define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A +#define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0)) + +#define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C +#define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1)) + +#define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110 +#define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1)) + +#define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112 +#define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1)) + +#define ADDR_IMAP_INTERRUPT_SET 0x400F0114 +#define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET)) + +#define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116 +#define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE)) + +/*************************************************************** +* Blinking/Breathing PWM +***************************************************************/ +#define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10 +#define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL)) + +#define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C +#define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE)) + +#define ADDR_LED_3_DELAY 0x4000BB08 +#define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY)) + +#define ADDR_LED_3_LIMITS 0x4000BB04 +#define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS)) + +#define ADDR_LED_3_CONFIGURATION 0x4000BB00 +#define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION)) + +#define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10 +#define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL)) + +#define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C +#define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE)) + +#define ADDR_LED_2_DELAY 0x4000BA08 +#define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY)) + +#define ADDR_LED_2_LIMITS 0x4000BA04 +#define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS)) + +#define ADDR_LED_2_CONFIGURATION 0x4000BA00 +#define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION)) + +#define ADDR_LED_1_CONFIGURATION 0x4000B900 +#define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION)) + +#define ADDR_LED_1_LIMITS 0x4000B904 +#define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS)) + +#define ADDR_LED_1_DELAY 0x4000B908 +#define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY)) + +#define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C +#define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE)) + +#define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910 +#define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL)) + +#define ADDR_LED_0_CONFIGURATION 0x4000B800 +#define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION)) + +#define ADDR_LED_0_LIMITS 0x4000B804 +#define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS)) + +#define ADDR_LED_0_DELAY 0x4000B808 +#define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY)) + +#define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C +#define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE)) + +#define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810 +#define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL)) + +/*************************************************************** +* SMSC BC-Link Master +***************************************************************/ +#define ADDR_BC_LINK_STATUS 0x4000BC00 +#define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS)) + +#define ADDR_BC_LINK_ADDRESS 0x4000BC04 +#define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS)) + +#define ADDR_BC_LINK_DATA 0x4000BC08 +#define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA)) + +#define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C +#define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT)) + +/*************************************************************** +* Basic Timer +***************************************************************/ +#define ADDR_BASIC_0_TIMER_COUNT 0x40000C00 +#define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT)) + +#define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04 +#define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD)) + +#define ADDR_BASIC_0_TIMER_STATUS 0x40000C08 +#define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS)) + +#define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C +#define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE)) + +#define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10 +#define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL)) + +#define ADDR_BASIC_1_TIMER_COUNT 0x40000C20 +#define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT)) + +#define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24 +#define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD)) + +#define ADDR_BASIC_1_TIMER_STATUS 0x40000C28 +#define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS)) + +#define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C +#define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE)) + +#define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30 +#define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL)) + +#define ADDR_BASIC_2_TIMER_COUNT 0x40000C40 +#define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT)) + +#define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44 +#define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD)) + +#define ADDR_BASIC_2_TIMER_STATUS 0x40000C48 +#define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS)) + +#define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C +#define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE)) + +#define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50 +#define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL)) + +#define ADDR_BASIC_3_TIMER_COUNT 0x40000C60 +#define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT)) + +#define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64 +#define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD)) + +#define ADDR_BASIC_3_TIMER_STATUS 0x40000C68 +#define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS)) + +#define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C +#define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE)) + +#define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70 +#define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL)) + +#define ADDR_BASIC_4_TIMER_COUNT 0x40000C80 +#define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT)) + +#define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84 +#define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD)) + +#define ADDR_BASIC_4_TIMER_STATUS 0x40000C88 +#define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS)) + +#define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C +#define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE)) + +#define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90 +#define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL)) + +#define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0 +#define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT)) + +#define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4 +#define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD)) + +#define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8 +#define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS)) + +#define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC +#define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE)) + +#define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0 +#define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL)) + +/*************************************************************** +* INTS +***************************************************************/ +#define ADDR_EC_GIRQ8_SOURCE 0x4000C000 +#define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE)) + +#define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004 +#define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET)) + +#define ADDR_EC_GIRQ8_RESULT 0x4000C008 +#define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT)) + +#define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C +#define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ9_SOURCE 0x4000C014 +#define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE)) + +#define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018 +#define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET)) + +#define ADDR_EC_GIRQ9_RESULT 0x4000C01C +#define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT)) + +#define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020 +#define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ10_SOURCE 0x4000C028 +#define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE)) + +#define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C +#define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET)) + +#define ADDR_EC_GIRQ10_RESULT 0x4000C030 +#define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT)) + +#define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034 +#define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ11_SOURCE 0x4000C03C +#define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE)) + +#define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040 +#define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET)) + +#define ADDR_EC_GIRQ11_RESULT 0x4000C044 +#define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT)) + +#define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048 +#define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ12_SOURCE 0x4000C050 +#define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE)) + +#define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054 +#define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET)) + +#define ADDR_EC_GIRQ12_RESULT 0x4000C058 +#define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT)) + +#define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C +#define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ13_SOURCE 0x4000C064 +#define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE)) + +#define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068 +#define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET)) + +#define ADDR_EC_GIRQ13_RESULT 0x4000C06C +#define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT)) + +#define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070 +#define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ14_SOURCE 0x4000C078 +#define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE)) + +#define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C +#define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET)) + +#define ADDR_EC_GIRQ14_RESULT 0x4000C080 +#define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT)) + +#define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084 +#define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ15_SOURCE 0x4000C08C +#define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE)) + +#define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090 +#define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET)) + +#define ADDR_EC_GIRQ15_RESULT 0x4000C094 +#define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT)) + +#define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098 +#define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0 +#define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE)) + +#define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4 +#define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET)) + +#define ADDR_EC_GIRQ16_RESULT 0x4000C0A8 +#define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT)) + +#define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC +#define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4 +#define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE)) + +#define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8 +#define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET)) + +#define ADDR_EC_GIRQ17_RESULT 0x4000C0BC +#define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT)) + +#define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0 +#define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8 +#define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE)) + +#define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC +#define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET)) + +#define ADDR_EC_GIRQ18_RESULT 0x4000C0D0 +#define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT)) + +#define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4 +#define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC +#define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE)) + +#define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0 +#define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET)) + +#define ADDR_EC_GIRQ19_RESULT 0x4000C0E4 +#define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT)) + +#define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8 +#define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0 +#define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE)) + +#define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4 +#define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET)) + +#define ADDR_EC_GIRQ20_RESULT 0x4000C0F8 +#define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT)) + +#define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC +#define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ21_SOURCE 0x4000C104 +#define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE)) + +#define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108 +#define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET)) + +#define ADDR_EC_GIRQ21_RESULT 0x4000C10C +#define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT)) + +#define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110 +#define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ22_SOURCE 0x4000C118 +#define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE)) + +#define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C +#define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET)) + +#define ADDR_EC_GIRQ22_RESULT 0x4000C120 +#define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT)) + +#define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124 +#define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR)) + +#define ADDR_EC_GIRQ23_SOURCE 0x4000C12C +#define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE)) + +#define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130 +#define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET)) + +#define ADDR_EC_GIRQ23_RESULT 0x4000C134 +#define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT)) + +#define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138 +#define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR)) + +#define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200 +#define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET)) + +#define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204 +#define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR)) + +#define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208 +#define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR)) + +/*************************************************************** +* RPM Fan Control +***************************************************************/ +#define ADDR_RPM_FAN_SETTING 0x4000A000 +#define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING)) + +#define ADDR_RPM_PWM_DIVIDE 0x4000A001 +#define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE)) + +#define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002 +#define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1)) + +#define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003 +#define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2)) + +#define ADDR_RPM_GAIN 0x4000A005 +#define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN)) + +#define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006 +#define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION)) + +#define ADDR_RPM_FAN_STEP 0x4000A007 +#define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP)) + +#define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008 +#define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE)) + +#define ADDR_RPM_VALID_TACH_COUNT 0x4000A009 +#define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT)) + +#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A +#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE)) + +#define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B +#define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE)) + +#define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C +#define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE)) + +#define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D +#define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE)) + +#define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E +#define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE)) + +#define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F +#define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE)) + +#define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010 +#define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY)) + +#define ADDR_RPM_FAN_STATUS 0x4000A011 +#define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS)) + +#define ADDR_RPM_FAN_TEST 0x4000A014 +#define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST)) + +#define ADDR_RPM_FAN_TEST1 0x4000A015 +#define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1)) + +#define ADDR_RPM_FAN_TEST2 0x4000A016 +#define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2)) + +#define ADDR_RPM_FAN_TEST3 0x4000A017 +#define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3)) + +/*************************************************************** +* V2P (HP ckt#1) 32bit_aligned +***************************************************************/ +#define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80 +#define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY)) + +#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84 +#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW)) + +#define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88 +#define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH)) + +#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C +#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA)) + +#define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90 +#define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS)) + +#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94 +#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1)) + +#define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98 +#define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2)) + +#define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C +#define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL)) + +#define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0 +#define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY)) + +#define ADDR_V2P_TEST 0x40007CA4 +#define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST)) + +#define ADDR_V2P_NOTICE_DATA 0x40007CA8 +#define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA)) + +#define ADDR_V2P_TEST_DATA 0x40007CAC +#define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA)) + +#define ADDR_V2P_COUNTER_START 0x40007CB0 +#define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START)) + +#define ADDR_V2P_HYSTERESIS 0x40007CB4 +#define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS)) + +#define ADDR_V2P_BIAS 0x40007CB8 +#define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS)) + +#define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC +#define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL)) + +/*************************************************************** +* VBAT_REGS (1322) +***************************************************************/ +#define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400 +#define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS)) + +#define ADDR_VBAT_CONTROL 0x4000A404 +#define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL)) + +#define ADDR_VBAT_CLOCK_ENABLE 0x4000A408 +#define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE)) + +/*************************************************************** +* EC_REG_BANK (1322) +***************************************************************/ +#define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04 +#define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS)) + +#define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08 +#define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0)) + +#define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C +#define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1)) + +#define ADDR_EC_REG_BANK_ID 0x4000FC10 +#define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID)) + +#define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14 +#define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL)) + +#define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18 +#define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL)) + +#define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C +#define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE)) + +#define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20 +#define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE)) + +#define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24 +#define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK)) + +#define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28 +#define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT)) + +#define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C +#define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL)) + +#define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30 +#define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM)) + +#define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34 +#define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM)) + +#define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38 +#define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD)) + +#define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C +#define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST)) + +#define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40 +#define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM)) + +/*************************************************************** +* PCR +***************************************************************/ +#define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100 +#define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE)) + +#define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104 +#define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED)) + +#define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108 +#define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES)) + +#define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C +#define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS)) + +#define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110 +#define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES)) + +#define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114 +#define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS)) + +#define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118 +#define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0)) + +#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120 +#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL)) + +#define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124 +#define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2)) + +#define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128 +#define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS)) + +#define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C +#define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL)) + +#define ADDR_PCR_OSCILLATOR_ID 0x40080130 +#define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID)) + +#define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138 +#define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE)) + +#define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C +#define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE)) + +#define ADDR_PCR_EC_RESET_ENABLE 0x40080140 +#define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE)) + +#define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144 +#define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2)) + +#define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148 +#define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL)) + +/*************************************************************** +* Public Key Crypto Engine +***************************************************************/ +#define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00 +#define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG)) + +#define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04 +#define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG)) + +#define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08 +#define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG)) + +#define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C +#define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG)) + +#define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10 +#define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG)) + +#define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14 +#define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG)) + +/*************************************************************** +* Non Deterministic Random Number Generator +***************************************************************/ +#define ADDR_NON_CONTROLREG 0x4000BE00 +#define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG)) + +#define ADDR_NON_FIFOLEVELREG 0x4000BE04 +#define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG)) + +#define ADDR_NON_VERSIONREG 0x4000BE08 +#define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG)) + +/*************************************************************** +* RTC +***************************************************************/ +#define ADDR_RTC_SECONDS 0x400F2800 +#define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS)) + +#define ADDR_RTC_SECONDS_ALARM 0x400F2801 +#define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM)) + +#define ADDR_RTC_MINUTES 0x400F2802 +#define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES)) + +#define ADDR_RTC_MINUTES_ALARM 0x400F2803 +#define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM)) + +#define ADDR_RTC_HOURS 0x400F2804 +#define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS)) + +#define ADDR_RTC_HOURS_ALARM 0x400F2805 +#define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM)) + +#define ADDR_RTC_DAY_OF_WEEK 0x400F2806 +#define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK)) + +#define ADDR_RTC_DAY_OF_MONTH 0x400F2807 +#define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH)) + +#define ADDR_RTC_MONTH 0x400F2808 +#define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH)) + +#define ADDR_RTC_YEAR 0x400F2809 +#define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR)) + +#define ADDR_RTC_A 0x400F280A +#define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A)) + +#define ADDR_RTC_B 0x400F280B +#define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B)) + +#define ADDR_RTC_C 0x400F280C +#define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C)) + +#define ADDR_RTC_D 0x400F280D +#define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D)) + +#define ADDR_RTC_CONTROL 0x400F2810 +#define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL)) + +#define ADDR_RTC_WEEK_ALARM 0x400F2814 +#define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM)) + +#define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818 +#define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD)) + +#define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C +#define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD)) + +#define ADDR_RTC_TEST_MODE 0x400F2820 +#define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE)) + +/*************************************************************** +* Analog to Digital Converter (ADC) +***************************************************************/ +#define ADDR_ADC_CONTROL 0x40007C00 +#define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL)) + +#define ADDR_ADC_DELAY 0x40007C04 +#define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY)) + +#define ADDR_ADC_STATUS 0x40007C08 +#define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS)) + +#define ADDR_ADC_SINGLE 0x40007C0C +#define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE)) + +#define ADDR_ADC_REPEAT 0x40007C10 +#define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT)) + +#define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14 +#define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS)) + +#define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18 +#define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS)) + +#define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C +#define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS)) + +#define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20 +#define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS)) + +#define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24 +#define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS)) + +#define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54 +#define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE)) + +#define ADDR_ADC_TEST 0x40007C78 +#define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST)) + +#define ADDR_ADC_CONFIGURATION 0x40007C7C +#define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION)) + +/*************************************************************** +* eFUSE +***************************************************************/ +#define ADDR_EFUSE_CONTROL 0x40082000 +#define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL)) + +#define ADDR_EFUSE_MANUAL_CONTROL 0x40082004 +#define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL)) + +#define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006 +#define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS)) + +#define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C +#define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA)) + +/*************************************************************** +* AES Crypto Engine & Hash Function +***************************************************************/ +#define ADDR_AES_CONFIGREG 0x4000D200 +#define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG)) + +#define ADDR_AES_COMMANDREG 0x4000D204 +#define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG)) + +#define ADDR_AES_CONTROLREG 0x4000D208 +#define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG)) + +#define ADDR_AES_STATUSREG 0x4000D20C +#define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG)) + +#define ADDR_AES_VERSIONREG 0x4000D210 +#define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG)) + +#define ADDR_AES_NBHEADERREG 0x4000D214 +#define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG)) + +#define ADDR_AES_LASTHEADERREG 0x4000D218 +#define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG)) + +#define ADDR_AES_NBBLOCKREG 0x4000D21C +#define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG)) + +#define ADDR_AES_LASTBLOCKREG 0x4000D220 +#define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG)) + +#define ADDR_AES_DMAINREG 0x4000D224 +#define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG)) + +#define ADDR_AES_DMAOUTREG 0x4000D228 +#define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG)) + +#define ADDR_AES_SHAMODE_REGISTER 0x4000D000 +#define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER)) + +#define ADDR_AES_NBBLOCK_REGISTER 0x4000D004 +#define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER)) + +#define ADDR_AES_CONTROL 0x4000D008 +#define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL)) + +#define ADDR_AES_STATUS 0x4000D00C +#define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS)) + +#define ADDR_AES_VERSION 0x4000D010 +#define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION)) + +#define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014 +#define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER)) + +#define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018 +#define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS)) + +#define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C +#define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS)) + +#define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020 +#define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS)) + +/*************************************************************** +* LPC +***************************************************************/ +#define ADDR_LPC_ACTIVATE 0x400F3330 +#define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE)) + +#define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340 +#define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341 +#define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342 +#define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343 +#define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344 +#define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345 +#define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346 +#define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347 +#define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348 +#define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349 +#define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A +#define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B +#define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C +#define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D +#define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E +#define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F +#define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION)) + +#define ADDR_LPC_INTERFACE_BAR 0x400F3360 +#define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR)) + +#define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364 +#define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR)) + +#define ADDR_LPC_UART_0_BAR 0x400F3368 +#define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR)) + +#define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378 +#define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR)) + +#define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388 +#define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR)) + +#define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C +#define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR)) + +#define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390 +#define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR)) + +#define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394 +#define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR)) + +#define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398 +#define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR)) + +#define ADDR_LPC_BUS_MONITOR 0x400F3104 +#define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR)) + +#define ADDR_LPC_HOST_BUS_ERROR 0x400F3108 +#define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR)) + +#define ADDR_LPC_EC_SERIRQ 0x400F310C +#define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ)) + +#define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110 +#define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL)) + +#define ADDR_LPC_BAR_INHIBIT 0x400F3120 +#define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT)) + +#define ADDR_LPC_BAR_INIT 0x400F3130 +#define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT)) + +#define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC +#define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION)) + +/*************************************************************** +* GPIO +***************************************************************/ +#define ADDR_GPIO000_PIN_CONTROL 0x40081000 +#define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL)) + +#define ADDR_GPIO001_PIN_CONTROL 0x40081004 +#define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL)) + +#define ADDR_GPIO002_PIN_CONTROL 0x40081008 +#define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL)) + +#define ADDR_GPIO003_PIN_CONTROL 0x4008100C +#define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL)) + +#define ADDR_GPIO004_PIN_CONTROL 0x40081010 +#define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL)) + +#define ADDR_GPIO005_PIN_CONTROL 0x40081014 +#define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL)) + +#define ADDR_GPIO006_PIN_CONTROL 0x40081018 +#define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL)) + +#define ADDR_GPIO007_PIN_CONTROL 0x4008101C +#define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL)) + +#define ADDR_GPIO010_PIN_CONTROL 0x40081020 +#define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL)) + +#define ADDR_GPIO011_PIN_CONTROL 0x40081024 +#define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL)) + +#define ADDR_GPIO012_PIN_CONTROL 0x40081028 +#define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL)) + +#define ADDR_GPIO013_PIN_CONTROL 0x4008102C +#define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL)) + +#define ADDR_GPIO014_PIN_CONTROL 0x40081030 +#define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL)) + +#define ADDR_GPIO015_PIN_CONTROL 0x40081034 +#define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL)) + +#define ADDR_GPIO016_PIN_CONTROL 0x40081038 +#define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL)) + +#define ADDR_GPIO017_PIN_CONTROL 0x4008103C +#define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL)) + +#define ADDR_GPIO020_PIN_CONTROL 0x40081040 +#define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL)) + +#define ADDR_GPIO021_PIN_CONTROL 0x40081044 +#define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL)) + +#define ADDR_GPIO022_PIN_CONTROL 0x40081048 +#define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL)) + +#define ADDR_GPIO023_PIN_CONTROL 0x4008104C +#define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL)) + +#define ADDR_GPIO024_PIN_CONTROL 0x40081050 +#define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL)) + +#define ADDR_GPIO025_PIN_CONTROL 0x40081054 +#define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL)) + +#define ADDR_GPIO026_PIN_CONTROL 0x40081058 +#define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL)) + +#define ADDR_GPIO027_PIN_CONTROL 0x4008105C +#define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL)) + +#define ADDR_GPIO030_PIN_CONTROL 0x40081060 +#define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL)) + +#define ADDR_GPIO031_PIN_CONTROL 0x40081064 +#define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL)) + +#define ADDR_GPIO032_PIN_CONTROL 0x40081068 +#define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL)) + +#define ADDR_GPIO033_PIN_CONTROL 0x4008106C +#define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL)) + +#define ADDR_GPIO034_PIN_CONTROL 0x40081070 +#define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL)) + +#define ADDR_GPIO035_PIN_CONTROL 0x40081074 +#define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL)) + +#define ADDR_GPIO036_PIN_CONTROL 0x40081078 +#define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL)) + +#define ADDR_GPIO040_PIN_CONTROL 0x40081080 +#define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL)) + +#define ADDR_GPIO041_PIN_CONTROL 0x40081084 +#define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL)) + +#define ADDR_GPIO042_PIN_CONTROL 0x40081088 +#define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL)) + +#define ADDR_GPIO043_PIN_CONTROL 0x4008108C +#define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL)) + +#define ADDR_GPIO044_PIN_CONTROL 0x40081090 +#define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL)) + +#define ADDR_GPIO045_PIN_CONTROL 0x40081094 +#define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL)) + +#define ADDR_GPIO046_PIN_CONTROL 0x40081098 +#define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL)) + +#define ADDR_GPIO047_PIN_CONTROL 0x4008109C +#define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL)) + +#define ADDR_GPIO050_PIN_CONTROL 0x400810A0 +#define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL)) + +#define ADDR_GPIO051_PIN_CONTROL 0x400810A4 +#define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL)) + +#define ADDR_GPIO052_PIN_CONTROL 0x400810A8 +#define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL)) + +#define ADDR_GPIO053_PIN_CONTROL 0x400810AC +#define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL)) + +#define ADDR_GPIO054_PIN_CONTROL 0x400810B0 +#define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL)) + +#define ADDR_GPIO055_PIN_CONTROL 0x400810B4 +#define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL)) + +#define ADDR_GPIO056_PIN_CONTROL 0x400810B8 +#define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL)) + +#define ADDR_GPIO057_PIN_CONTROL 0x400810BC +#define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL)) + +#define ADDR_GPIO060_PIN_CONTROL 0x400810C0 +#define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL)) + +#define ADDR_GPIO061_PIN_CONTROL 0x400810C4 +#define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL)) + +#define ADDR_GPIO062_PIN_CONTROL 0x400810C8 +#define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL)) + +#define ADDR_GPIO063_PIN_CONTROL 0x400810CC +#define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL)) + +#define ADDR_GPIO064_PIN_CONTROL 0x400810D0 +#define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL)) + +#define ADDR_GPIO065_PIN_CONTROL 0x400810D4 +#define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL)) + +#define ADDR_GPIO066_PIN_CONTROL 0x400810D8 +#define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL)) + +#define ADDR_GPIO067_PIN_CONTROL 0x400810DC +#define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL)) + +#define ADDR_GPIO100_PIN_CONTROL 0x40081100 +#define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL)) + +#define ADDR_GPIO101_PIN_CONTROL 0x40081104 +#define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL)) + +#define ADDR_GPIO102_PIN_CONTROL 0x40081108 +#define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL)) + +#define ADDR_GPIO103_PIN_CONTROL 0x4008110C +#define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL)) + +#define ADDR_GPIO104_PIN_CONTROL 0x40081110 +#define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL)) + +#define ADDR_GPIO105_PIN_CONTROL 0x40081114 +#define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL)) + +#define ADDR_GPIO106_PIN_CONTROL 0x40081118 +#define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL)) + +#define ADDR_GPIO107_PIN_CONTROL 0x4008111C +#define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL)) + +#define ADDR_GPIO110_PIN_CONTROL 0x40081120 +#define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL)) + +#define ADDR_GPIO111_PIN_CONTROL 0x40081124 +#define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL)) + +#define ADDR_GPIO112_PIN_CONTROL 0x40081128 +#define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL)) + +#define ADDR_GPIO113_PIN_CONTROL 0x4008112C +#define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL)) + +#define ADDR_GPIO114_PIN_CONTROL 0x40081130 +#define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL)) + +#define ADDR_GPIO115_PIN_CONTROL 0x40081134 +#define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL)) + +#define ADDR_GPIO116_PIN_CONTROL 0x40081138 +#define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL)) + +#define ADDR_GPIO117_PIN_CONTROL 0x4008113C +#define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL)) + +#define ADDR_GPIO120_PIN_CONTROL 0x40081140 +#define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL)) + +#define ADDR_GPIO121_PIN_CONTROL 0x40081144 +#define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL)) + +#define ADDR_GPIO122_PIN_CONTROL 0x40081148 +#define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL)) + +#define ADDR_GPIO123_PIN_CONTROL 0x4008114C +#define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL)) + +#define ADDR_GPIO124_PIN_CONTROL 0x40081150 +#define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL)) + +#define ADDR_GPIO125_PIN_CONTROL 0x40081154 +#define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL)) + +#define ADDR_GPIO126_PIN_CONTROL 0x40081158 +#define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL)) + +#define ADDR_GPIO127_PIN_CONTROL 0x4008115C +#define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL)) + +#define ADDR_GPIO130_PIN_CONTROL 0x40081160 +#define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL)) + +#define ADDR_GPIO131_PIN_CONTROL 0x40081164 +#define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL)) + +#define ADDR_GPIO132_PIN_CONTROL 0x40081168 +#define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL)) + +#define ADDR_GPIO133_PIN_CONTROL 0x4008116C +#define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL)) + +#define ADDR_GPIO134_PIN_CONTROL 0x40081170 +#define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL)) + +#define ADDR_GPIO135_PIN_CONTROL 0x40081174 +#define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL)) + +#define ADDR_GPIO136_PIN_CONTROL 0x40081178 +#define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL)) + +#define ADDR_GPIO140_PIN_CONTROL 0x40081180 +#define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL)) + +#define ADDR_GPIO141_PIN_CONTROL 0x40081184 +#define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL)) + +#define ADDR_GPIO142_PIN_CONTROL 0x40081188 +#define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL)) + +#define ADDR_GPIO143_PIN_CONTROL 0x4008118C +#define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL)) + +#define ADDR_GPIO144_PIN_CONTROL 0x40081190 +#define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL)) + +#define ADDR_GPIO145_PIN_CONTROL 0x40081194 +#define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL)) + +#define ADDR_GPIO146_PIN_CONTROL 0x40081198 +#define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL)) + +#define ADDR_GPIO147_PIN_CONTROL 0x4008119C +#define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL)) + +#define ADDR_GPIO150_PIN_CONTROL 0x400811A0 +#define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL)) + +#define ADDR_GPIO151_PIN_CONTROL 0x400811A4 +#define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL)) + +#define ADDR_GPIO152_PIN_CONTROL 0x400811A8 +#define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL)) + +#define ADDR_GPIO153_PIN_CONTROL 0x400811AC +#define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL)) + +#define ADDR_GPIO154_PIN_CONTROL 0x400811B0 +#define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL)) + +#define ADDR_GPIO155_PIN_CONTROL 0x400811B4 +#define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL)) + +#define ADDR_GPIO156_PIN_CONTROL 0x400811B8 +#define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL)) + +#define ADDR_GPIO157_PIN_CONTROL 0x400811BC +#define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL)) + +#define ADDR_GPIO160_PIN_CONTROL 0x400811C0 +#define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL)) + +#define ADDR_GPIO161_PIN_CONTROL 0x400811C4 +#define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL)) + +#define ADDR_GPIO162_PIN_CONTROL 0x400811C8 +#define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL)) + +#define ADDR_GPIO163_PIN_CONTROL 0x400811CC +#define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL)) + +#define ADDR_GPIO164_PIN_CONTROL 0x400811D0 +#define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL)) + +#define ADDR_GPIO165_PIN_CONTROL 0x400811D4 +#define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL)) + +#define ADDR_GPIO200_PIN_CONTROL 0x40081200 +#define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL)) + +#define ADDR_GPIO201_PIN_CONTROL 0x40081204 +#define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL)) + +#define ADDR_GPIO202_PIN_CONTROL 0x40081208 +#define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL)) + +#define ADDR_GPIO203_PIN_CONTROL 0x4008120C +#define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL)) + +#define ADDR_GPIO204_PIN_CONTROL 0x40081210 +#define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL)) + +#define ADDR_GPIO206_PIN_CONTROL 0x40081218 +#define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL)) + +#define ADDR_GPIO210_PIN_CONTROL 0x40081220 +#define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL)) + +#define ADDR_GPIO211_PIN_CONTROL 0x40081224 +#define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL)) + +#define ADDR_GPIO212_PIN_CONTROL 0x40081228 +#define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL)) + +#define ADDR_GPIO213_PIN_CONTROL 0x4008122C +#define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL)) + +#define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280 +#define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036)) + +#define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284 +#define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076)) + +#define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288 +#define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136)) + +#define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C +#define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176)) + +#define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290 +#define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236)) + +#define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300 +#define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036)) + +#define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304 +#define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076)) + +#define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308 +#define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136)) + +#define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C +#define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176)) + +#define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310 +#define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236)) + +#define ADDR_GPIO_LOCK_4 0x400813EC +#define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4)) + +#define ADDR_GPIO_LOCK_3 0x400813F0 +#define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3)) + +#define ADDR_GPIO_LOCK_2 0x400813F4 +#define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2)) + +#define ADDR_GPIO_LOCK_1 0x400813F8 +#define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1)) + +#define ADDR_GPIO_LOCK_0 0x400813FC +#define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0)) + +#define ADDR_GPIO000_PIN_CONTROL_2 0x40081500 +#define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2)) + +#define ADDR_GPIO001_PIN_CONTROL_2 0x40081504 +#define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2)) + +#define ADDR_GPIO002_PIN_CONTROL_2 0x40081508 +#define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2)) + +#define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C +#define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2)) + +#define ADDR_GPIO004_PIN_CONTROL_2 0x40081510 +#define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2)) + +#define ADDR_GPIO005_PIN_CONTROL_2 0x40081514 +#define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2)) + +#define ADDR_GPIO006_PIN_CONTROL_2 0x40081518 +#define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2)) + +#define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C +#define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2)) + +#define ADDR_GPIO010_PIN_CONTROL_2 0x40081520 +#define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2)) + +#define ADDR_GPIO011_PIN_CONTROL_2 0x40081524 +#define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2)) + +#define ADDR_GPIO012_PIN_CONTROL_2 0x40081528 +#define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2)) + +#define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C +#define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2)) + +#define ADDR_GPIO014_PIN_CONTROL_2 0x40081530 +#define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2)) + +#define ADDR_GPIO015_PIN_CONTROL_2 0x40081534 +#define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2)) + +#define ADDR_GPIO016_PIN_CONTROL_2 0x40081538 +#define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2)) + +#define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C +#define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2)) + +#define ADDR_GPIO020_PIN_CONTROL_2 0x40081540 +#define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2)) + +#define ADDR_GPIO021_PIN_CONTROL_2 0x40081544 +#define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2)) + +#define ADDR_GPIO022_PIN_CONTROL_2 0x40081548 +#define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2)) + +#define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C +#define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2)) + +#define ADDR_GPIO024_PIN_CONTROL_2 0x40081550 +#define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2)) + +#define ADDR_GPIO025_PIN_CONTROL_2 0x40081554 +#define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2)) + +#define ADDR_GPIO026_PIN_CONTROL_2 0x40081558 +#define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2)) + +#define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C +#define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2)) + +#define ADDR_GPIO030_PIN_CONTROL_2 0x40081560 +#define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2)) + +#define ADDR_GPIO031_PIN_CONTROL_2 0x40081564 +#define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2)) + +#define ADDR_GPIO032_PIN_CONTROL_2 0x40081568 +#define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2)) + +#define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C +#define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2)) + +#define ADDR_GPIO034_PIN_CONTROL_2 0x40081570 +#define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2)) + +#define ADDR_GPIO035_PIN_CONTROL_2 0x40081574 +#define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2)) + +#define ADDR_GPIO036_PIN_CONTROL_2 0x40081578 +#define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2)) + +#define ADDR_GPIO040_PIN_CONTROL_2 0x40081580 +#define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2)) + +#define ADDR_GPIO041_PIN_CONTROL_2 0x40081584 +#define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2)) + +#define ADDR_GPIO042_PIN_CONTROL_2 0x40081588 +#define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2)) + +#define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C +#define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2)) + +#define ADDR_GPIO044_PIN_CONTROL_2 0x40081590 +#define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2)) + +#define ADDR_GPIO045_PIN_CONTROL_2 0x40081594 +#define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2)) + +#define ADDR_GPIO046_PIN_CONTROL_2 0x40081598 +#define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2)) + +#define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C +#define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2)) + +#define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0 +#define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2)) + +#define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4 +#define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2)) + +#define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8 +#define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2)) + +#define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC +#define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2)) + +#define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0 +#define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2)) + +#define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4 +#define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2)) + +#define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8 +#define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2)) + +#define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC +#define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2)) + +#define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0 +#define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2)) + +#define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4 +#define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2)) + +#define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8 +#define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2)) + +#define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC +#define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2)) + +#define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0 +#define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2)) + +#define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4 +#define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2)) + +#define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8 +#define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2)) + +#define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC +#define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2)) + +#define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0 +#define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2)) + +#define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4 +#define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2)) + +#define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8 +#define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2)) + +#define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC +#define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2)) + +#define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0 +#define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2)) + +#define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4 +#define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2)) + +#define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8 +#define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2)) + +#define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC +#define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2)) + +#define ADDR_GPIO110_PIN_CONTROL_2 0x40081600 +#define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2)) + +#define ADDR_GPIO111_PIN_CONTROL_2 0x40081604 +#define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2)) + +#define ADDR_GPIO112_PIN_CONTROL_2 0x40081608 +#define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2)) + +#define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C +#define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2)) + +#define ADDR_GPIO114_PIN_CONTROL_2 0x40081610 +#define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2)) + +#define ADDR_GPIO115_PIN_CONTROL_2 0x40081614 +#define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2)) + +#define ADDR_GPIO116_PIN_CONTROL_2 0x40081618 +#define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2)) + +#define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C +#define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2)) + +#define ADDR_GPIO120_PIN_CONTROL_2 0x40081620 +#define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2)) + +#define ADDR_GPIO121_PIN_CONTROL_2 0x40081624 +#define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2)) + +#define ADDR_GPIO122_PIN_CONTROL_2 0x40081628 +#define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2)) + +#define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C +#define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2)) + +#define ADDR_GPIO124_PIN_CONTROL_2 0x40081630 +#define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2)) + +#define ADDR_GPIO125_PIN_CONTROL_2 0x40081634 +#define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2)) + +#define ADDR_GPIO126_PIN_CONTROL_2 0x40081638 +#define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2)) + +#define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C +#define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2)) + +#define ADDR_GPIO130_PIN_CONTROL_2 0x40081640 +#define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2)) + +#define ADDR_GPIO131_PIN_CONTROL_2 0x40081644 +#define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2)) + +#define ADDR_GPIO132_PIN_CONTROL_2 0x40081648 +#define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2)) + +#define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C +#define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2)) + +#define ADDR_GPIO134_PIN_CONTROL_2 0x40081650 +#define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2)) + +#define ADDR_GPIO135_PIN_CONTROL_2 0x40081654 +#define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2)) + +#define ADDR_GPIO136_PIN_CONTROL_2 0x40081658 +#define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2)) + +#define ADDR_GPIO140_PIN_CONTROL_2 0x40081660 +#define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2)) + +#define ADDR_GPIO141_PIN_CONTROL_2 0x40081664 +#define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2)) + +#define ADDR_GPIO142_PIN_CONTROL_2 0x40081668 +#define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2)) + +#define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C +#define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2)) + +#define ADDR_GPIO144_PIN_CONTROL_2 0x40081670 +#define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2)) + +#define ADDR_GPIO145_PIN_CONTROL_2 0x40081674 +#define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2)) + +#define ADDR_GPIO146_PIN_CONTROL_2 0x40081678 +#define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2)) + +#define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C +#define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2)) + +#define ADDR_GPIO150_PIN_CONTROL_2 0x40081680 +#define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2)) + +#define ADDR_GPIO151_PIN_CONTROL_2 0x40081684 +#define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2)) + +#define ADDR_GPIO152_PIN_CONTROL_2 0x40081688 +#define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2)) + +#define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C +#define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2)) + +#define ADDR_GPIO154_PIN_CONTROL_2 0x40081690 +#define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2)) + +#define ADDR_GPIO155_PIN_CONTROL_2 0x40081694 +#define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2)) + +#define ADDR_GPIO156_PIN_CONTROL_2 0x40081698 +#define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2)) + +#define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C +#define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2)) + +#define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0 +#define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2)) + +#define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4 +#define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2)) + +#define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8 +#define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2)) + +#define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC +#define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2)) + +#define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0 +#define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2)) + +#define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4 +#define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2)) + +#define ADDR_GPIO200_PIN_CONTROL_2 0x40081720 +#define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2)) + +#define ADDR_GPIO201_PIN_CONTROL_2 0x40081724 +#define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2)) + +#define ADDR_GPIO202_PIN_CONTROL_2 0x40081728 +#define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2)) + +#define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C +#define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2)) + +#define ADDR_GPIO204_PIN_CONTROL_2 0x40081730 +#define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2)) + +#define ADDR_GPIO206_PIN_CONTROL_2 0x40081738 +#define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2)) + +#define ADDR_GPIO210_PIN_CONTROL_2 0x40081740 +#define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2)) + +#define ADDR_GPIO211_PIN_CONTROL_2 0x40081744 +#define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2)) + +#define ADDR_GPIO212_PIN_CONTROL_2 0x40081748 +#define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2)) + +#define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C +#define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2)) + +/*************************************************************** +* DMA +***************************************************************/ +#define ADDR_DMA_MAIN_CONTROL 0x40002400 +#define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL)) + +#define ADDR_DMA_AFIFO_DATA 0x40002404 +#define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA)) + +#define ADDR_DMA_MAIN_DEBUG 0x40002408 +#define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG)) + +#define ADDR_DMA_CH0_ACTIVATE 0x40002410 +#define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE)) + +#define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414 +#define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418 +#define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C +#define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS)) + +#define ADDR_DMA_CH0_CONTROL 0x40002420 +#define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL)) + +#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424 +#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428 +#define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH0_TEST 0x4000242C +#define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST)) + +#define ADDR_DMA_CH1_ACTIVATE 0x40002430 +#define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE)) + +#define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434 +#define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438 +#define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C +#define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS)) + +#define ADDR_DMA_CH1_CONTROL 0x40002440 +#define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL)) + +#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444 +#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448 +#define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH1_TEST 0x4000244C +#define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST)) + +#define ADDR_DMA_CH10_ACTIVATE 0x40002550 +#define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE)) + +#define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554 +#define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558 +#define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C +#define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS)) + +#define ADDR_DMA_CH10_CONTROL 0x40002560 +#define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL)) + +#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564 +#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568 +#define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH10_TEST 0x4000256C +#define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST)) + +#define ADDR_DMA_CH11_ACTIVATE 0x40002570 +#define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE)) + +#define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574 +#define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578 +#define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C +#define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS)) + +#define ADDR_DMA_CH11_CONTROL 0x40002580 +#define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL)) + +#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584 +#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588 +#define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH11_TEST 0x4000258C +#define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST)) + +#define ADDR_DMA_CH2_ACTIVATE 0x40002450 +#define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE)) + +#define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454 +#define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458 +#define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C +#define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS)) + +#define ADDR_DMA_CH2_CONTROL 0x40002460 +#define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL)) + +#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464 +#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468 +#define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH2_TEST 0x4000246C +#define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST)) + +#define ADDR_DMA_CH3_ACTIVATE 0x40002470 +#define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE)) + +#define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474 +#define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478 +#define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C +#define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS)) + +#define ADDR_DMA_CH3_CONTROL 0x40002480 +#define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL)) + +#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484 +#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488 +#define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH3_TEST 0x4000248C +#define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST)) + +#define ADDR_DMA_CH4_ACTIVATE 0x40002490 +#define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE)) + +#define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494 +#define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498 +#define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C +#define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS)) + +#define ADDR_DMA_CH4_CONTROL 0x400024A0 +#define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL)) + +#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4 +#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8 +#define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH4_TEST 0x400024AC +#define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST)) + +#define ADDR_DMA_CH5_ACTIVATE 0x400024B0 +#define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE)) + +#define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4 +#define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8 +#define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC +#define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS)) + +#define ADDR_DMA_CH5_CONTROL 0x400024C0 +#define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL)) + +#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4 +#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8 +#define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH5_TEST 0x400024CC +#define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST)) + +#define ADDR_DMA_CH6_ACTIVATE 0x400024D0 +#define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE)) + +#define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4 +#define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8 +#define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC +#define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS)) + +#define ADDR_DMA_CH6_CONTROL 0x4.00E+05 +#define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL)) + +#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09 +#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13 +#define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH6_TEST 0x400024EC +#define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST)) + +#define ADDR_DMA_CH7_ACTIVATE 0x400024F0 +#define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE)) + +#define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4 +#define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8 +#define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC +#define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS)) + +#define ADDR_DMA_CH7_CONTROL 0x40002500 +#define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL)) + +#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504 +#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508 +#define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH7_TEST 0x4000250C +#define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST)) + +#define ADDR_DMA_CH8_ACTIVATE 0x40002510 +#define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE)) + +#define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514 +#define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518 +#define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C +#define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS)) + +#define ADDR_DMA_CH8_CONTROL 0x40002520 +#define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL)) + +#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524 +#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528 +#define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH8_TEST 0x4000252C +#define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST)) + +#define ADDR_DMA_CH9_ACTIVATE 0x40002530 +#define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE)) + +#define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534 +#define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS)) + +#define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538 +#define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS)) + +#define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C +#define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS)) + +#define ADDR_DMA_CH9_CONTROL 0x40002540 +#define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL)) + +#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544 +#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS)) + +#define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548 +#define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE)) + +#define ADDR_DMA_CH9_TEST 0x4000254C +#define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST)) + +#endif /*SMSCMMCR_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h new file mode 100644 index 000000000..129f5f2f5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer.h @@ -0,0 +1,409 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/11/22 06:01:28 $ +$Author: amohandas $ +Last Change: Updated with unit testing feedbacks +******************************************************************************/ +/** @file btimer.h +* \brief Basic Timer Peripheral Header file +* \author jvasanth +* +* This file is the header file for Basic Timer Peripheral +******************************************************************************/ + +/** @defgroup Basic_Timer + * @{ + */ + +#ifndef _BTIMER_H +#define _BTIMER_H + +/******************************************************************************/ +/** Logical Timer ID for APIs. + * This is the timer IDs passed to Basic Timer API function calls + *******************************************************************************/ +enum _PID_BTIMER_ +{ + PID_BTIMER_0, + PID_BTIMER_1, + PID_BTIMER_2, + PID_BTIMER_3, + PID_BTIMER_4, + PID_BTIMER_5, + PID_BTIMER_MAX +}; + +/* ---------------------------------------------------------------------- */ +/* Logical flags for Timer Control */ +/* ---------------------------------------------------------------------- */ +//This is for tmr_cntl parameter in btimer_init function +#define BTIMER_AUTO_RESTART (0x08u) +#define BTIMER_ONE_SHOT (0u) +#define BTIMER_COUNT_UP (0x04u) +#define BTIMER_COUNT_DOWN (0u) +#define BTIMER_INT_EN (0x01u) +#define BTIMER_NO_INT (0u) +/* ---------------------------------------------------------------------- */ + + +//Timer Block Hardware Bits and Masks +#define BTIMER_CNTL_HALT (0x80UL) +#define BTIMER_CNTL_RELOAD (0x40UL) +#define BTIMER_CNTL_START (0x20UL) +#define BTIMER_CNTL_SOFT_RESET (0x10UL) +#define BTIMER_CNTL_AUTO_RESTART (0x08UL) +#define BTIMER_CNTL_COUNT_UP (0x04UL) +#define BTIMER_CNTL_ENABLE (0x01UL) + +#define BTIMER_CNTL_HALT_BIT (7U) +#define BTIMER_CNTL_RELOAD_BIT (6U) +#define BTIMER_CNTL_START_BIT (5U) +#define BTIMER_CNTRL_SOFT_RESET_BIT (4U) +#define BTIMER_CNTL_AUTO_RESTART_BIT (3U) +#define BTIMER_CNTL_COUNT_DIR_BIT (2U) +#define BTIMER_CNTL_ENABLE_BIT (0U) + +#define BTIMER_GIRQ MEC_GIRQ23_ID +#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX + + +/* ---------------------------------------------------------------------- */ +/* API - Basic Timer Intitialization function */ +/* ---------------------------------------------------------------------- */ + +/** Initialize specified timer + * @param btimer_id Basic Timer ID + * @param tmr_cntl Logical flags for Timer Control + * @param initial_count Initial Count + * @param preload_count Preload Count + * @note Performs a soft reset of the timer before configuration + */ +void btimer_init(uint8_t btimer_id, + uint16_t tmr_cntl, + uint16_t prescaler, + uint32_t initial_count, + uint32_t preload_count); + +/* ---------------------------------------------------------------------- */ +/* API - Functions to program and read the Basic Timer Counter */ +/* ---------------------------------------------------------------------- */ +/** Program timer's counter register. + * @param btimer_id Basic Timer ID + * @param count new counter value + * @note Timer hardware may implement a 16-bit or 32-bit + * hardware counter. If the timer is 16-bit only the lower + * 16-bits of the count paramter are used. + */ +void btimer_count_set(uint8_t btimer_id, uint32_t count); + +/** Return current value of timer's count register. + * @param btimer_id Basic Timer ID. + * @return uint32_t timer count may be 32 or 16 bits depending + * upon the hardware. Timers 0-3 are 16-bit + * and Timers 4-5 are 32-bit. + */ +uint32_t btimer_count_get(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Function to reload counter from Preload Register */ +/* ---------------------------------------------------------------------- */ +/** Force timer to reload counter from preload + * register. + * @param btimer_id Basic Timer ID. + * @note Hardware will only reload counter if timer is running. + */ +void btimer_reload(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for stopping and starting the basic Timer */ +/* ---------------------------------------------------------------------- */ +/** Start timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_start(uint8_t btimer_id); + +/** Stop timer. + * @param btimer_id Basic Timer ID. + * @note When a stopped timer is started again it will reload + * the count register from preload value. + */ +void btimer_stop(uint8_t btimer_id); + +/** Return state of timer's START bit. + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(timer not started), 1 (timer started) + */ +uint8_t btimer_is_started(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Function to perform basic timer soft reset */ +/* ---------------------------------------------------------------------- */ +/** Peform soft reset of specified timer. + * @param btimer_id Basic Timer ID + * @note Soft reset set all registers to POR values. + * Spins 256 times waiting on hardware to clear reset bit. + */ +void btimer_reset(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions to halt/unhalt the timer counting */ +/* ---------------------------------------------------------------------- */ +/** Halt timer counting with no reload on unhalt. + * @param btimer_id Basic Timer ID. + * @note A halted timer will not reload the count register when + * unhalted, it will continue counting from the current + * count value. + */ +void btimer_halt(uint8_t btimer_id); + +/** Unhalt timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_unhalt(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for Basic Timer interrupt */ +/* ---------------------------------------------------------------------- */ +/** Enable specified timer's interrupt from the block. + * @param btimer_id Basic Timer ID. + * @param ien Non-zero enable interrupt in timer block, 0 + * disable. + */ +void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien); + +/** Read Timer interrupt status and clear if set + * @param btimer_id Basic Timer ID. + * @return uint8_t 1 (Timer interrupt status set) else 0. + * @note If timer interrupt status is set then clear it before + * returning. + */ +uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for Basic Timer GIRQ */ +/* ---------------------------------------------------------------------- */ +/** Enables GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_set(uint8_t btimer_id); + +/** Clears GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_clr(uint8_t btimer_id); + +/** Returns GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(src bit not set), Non-zero (src bit set) + */ +uint8_t btimer_girq_src_get(uint8_t btimer_id); + +/** Clears GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_src_clr(uint8_t btimer_id); + +/** Returns GIRQ result bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(result bit not set), Non-zero (result bit set) + */ +uint8_t btimer_girq_result_get(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for Basic Timer Sleep */ +/* ---------------------------------------------------------------------- */ +/** Enable/Disable clock gating on idle of a timer + * @param btimer_id Basic Timer ID. + * @param sleep_en 1 = Sleep enable, 0 = Sleep disable + */ +void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en); + +/** Returns clk required status for the timer block + * @param btimer_id Basic Timer ID. + * @return Non-zero if clk required, else 0 + */ +uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id); + +/** Enable/Disable reset on sleep for the timer block + * @param btimer_id Basic Timer ID. + * @param reset_en 1 to enable, 0 to disable + */ +void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to set and read Timer Counter Register */ +/* ---------------------------------------------------------------------- */ +/** Sets timer counter + * @param btimer_id Basic Timer ID + * @param count - 32-bit counter + */ +void p_btimer_count_set(uint8_t btimer_id, uint32_t count); + +/** Read the timer counter + * @param btimer_id Basic Timer ID + * @return count - 32-bit counter + */ +uint32_t p_btimer_count_get(uint8_t btimer_id); + + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to program the Preload */ +/* ---------------------------------------------------------------------- */ +/** Sets preload for the counter + * @param btimer_id Basic Timer ID + * @param preload_count - 32-bit pre-load value + */ +void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Functions - Functions for basic timer interrupts */ +/* ---------------------------------------------------------------------- */ +/** Reads the interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + * @return status - 1 if interrupt status set, else 0 + */ +uint8_t p_btimer_int_status_get(uint8_t btimer_id); + +/** Clears interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_status_clr(uint8_t btimer_id); + +/** Sets interrupt enable bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_set(uint8_t btimer_id); + +/** Clears interrupt enable bit for the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_clr(uint8_t btimer_id); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Functions - Functions for Control Register */ +/* ---------------------------------------------------------------------- */ +/** Writes the control register 32-bits + * @param btimer_id Basic Timer ID + * @param value - 32-bit value to program + */ +void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value); + +/** Reads the control register + * @param btimer_id Basic Timer ID + * @return uint32_t - 32-bit value + */ +uint32_t p_btimer_ctrl_read(uint8_t btimer_id); + +/** Clears enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_set(uint8_t btimer_id); + +/** Clears enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_clr(uint8_t btimer_id); + +/** Sets counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id); + +/** Clears counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id); + +/** Sets auto restart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id); + +/** Clears auto resetart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id); + +/** Sets soft reset bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id); + +/** Read Soft Reset bit + * @param btimer_id Basic Timer ID + * @return 0 if soft reset status bit cleared; else non-zero value + */ +uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id); + +/** Sets start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_set(uint8_t btimer_id); + +/** Read start bit in the control register + * @param btimer_id Basic Timer ID + * @return 0 if start bit not set; else non-zero value + */ +uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id); + +/** Clears start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_clr(uint8_t btimer_id); + +/** Sets reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_set(uint8_t btimer_id); + +/** Clears reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_clr(uint8_t btimer_id); + +/** Sets halt bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_halt_set(uint8_t btimer_id); + +/** Clears halt bit in the control register + * @param btimer_id Basic Timer ID + */ + +void p_btimer_ctrl_halt_clr(uint8_t btimer_id); + +/** Sets prescale value + * @param btimer_id Basic Timer ID + * @param prescaler - 16-bit pre-scale value + */ +void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler); + + +#endif // #ifndef _BTIMER_H + +/* end btimer_perphl.c */ + +/** @} //Peripherals Basic_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c new file mode 100644 index 000000000..d4cfea3e2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_api.c @@ -0,0 +1,473 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #2 $ +$DateTime: 2015/11/24 06:27:00 $ +$Author: amohandas $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file btimer_api.c +* \brief Basic Timer APIs Source file +* \author jvasanth +* +* This file implements the Basic Timer API functions +******************************************************************************/ + +/** @defgroup Basic_Timer + * @{ + */ + +#include "common_lib.h" +#include "btimer.h" +#include "..\pcr\pcr.h" + +/** Basic Timer Sleep Registers & Bit Positions */ +static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = { + PCR_BTIMER0, + PCR_BTIMER1, + PCR_BTIMER2, + PCR_BTIMER3, + PCR_BTIMER4, + PCR_BTIMER5 +}; + +#ifdef PLIB_BTIMER_CHECK_ID + +/** Local helper that checks if logical Timer ID is valid. + * @param btimer_id Basic Timer ID + * @return uint8_t Non-zero(VALID), 0(Invalid) + */ +static uint8_t btmr_valid(uint8_t btimer_id) +{ + if ( btimer_id < (PID_BTIMER_MAX ) ) { + return true; + } + return false; +} + +#else + + +/** This version of tmr_valid skips checking always returning 1. + * Compiler may optimize it out. + * @param btimer_id Basic Timer ID + * @return uint8_t 1(VALID) + */ +static uint8_t btmr_valid(uint8_t btimer_id) { return 1; } + +#endif + + +/* ---------------------------------------------------------------------- */ +/* Basic Timer Intitialization function */ +/* ---------------------------------------------------------------------- */ + +/** Initialize specified timer + * @param btimer_id Basic Timer ID + * @param tmr_cntl Logical flags for Timer Control + * @param initial_count Initial Count + * @param preload_count Preload Count + * @note Performs a soft reset of the timer before configuration + */ +void btimer_init(uint8_t btimer_id, + uint16_t tmr_cntl, + uint16_t prescaler, + uint32_t initial_count, + uint32_t preload_count) +{ + uint32_t value; + + if (btmr_valid(btimer_id)) { + + btimer_reset(btimer_id); + + // Ungate timer clocks and program prescale + value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE); + p_btimer_ctrl_write(btimer_id, value); + + // Program Preload & initial counter value + p_btimer_preload_set(btimer_id, preload_count); + p_btimer_count_set(btimer_id, initial_count); + + // Program control register, interrupt enable, and clear status + if (tmr_cntl & BTIMER_COUNT_UP) { + p_btimer_ctrl_counter_dir_set(btimer_id); + } + if (tmr_cntl & BTIMER_AUTO_RESTART) { + p_btimer_ctrl_auto_restart_set(btimer_id); + } + if (tmr_cntl & BTIMER_INT_EN) { + p_btimer_int_enable_set(btimer_id); // enable first + p_btimer_int_status_clr(btimer_id); // clear status + } + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions to program and read the Basic Timer Counter */ +/* ---------------------------------------------------------------------- */ + +/** Program timer's counter register. + * @param btimer_id Basic Timer ID + * @param count new counter value + * @note Timer hardware may implement a 16-bit or 32-bit + * hardware counter. If the timer is 16-bit only the lower + * 16-bits of the count paramter are used. + */ +void btimer_count_set(uint8_t btimer_id, uint32_t count) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_count_set(btimer_id, count); + } +} + +/** Return current value of timer's count register. + * @param btimer_id Basic Timer ID. + * @return uint32_t timer count may be 32 or 16 bits depending + * upon the hardware. Timers 0-3 are 16-bit + * and Timers 4-5 are 32-bit. + */ +uint32_t btimer_count_get(uint8_t btimer_id) +{ + uint32_t cnt; + + cnt = 0ul; + if ( btmr_valid(btimer_id) ) { + + cnt = p_btimer_count_get(btimer_id); + } + + return cnt; +} + +/* ---------------------------------------------------------------------- */ +/* Function to reload counter from Preload Register */ +/* ---------------------------------------------------------------------- */ + +/** Force timer to reload counter from preload + * register. + * @param btimer_id Basic Timer ID. + * @note Hardware will only reload counter if timer is running. + */ +void btimer_reload(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running + { + p_btimer_ctrl_reload_set(btimer_id); + } + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions for stopping and starting the basic Timer */ +/* ---------------------------------------------------------------------- */ + +/** Start timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_start(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_start_set(btimer_id); + } +} + +/** Stop timer. + * @param btimer_id Basic Timer ID. + * @note When a stopped timer is started again it will reload + * the count register from preload value. + */ +void btimer_stop(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_start_clr(btimer_id); + + } +} + +/** Return state of timer's START bit. + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(timer not started), 1 (timer started) + */ +uint8_t btimer_is_started(uint8_t btimer_id) +{ + uint8_t sts; + + sts = 0; + if ( btmr_valid(btimer_id) ) { + + if (p_btimer_ctrl_start_get(btimer_id)) + { + sts = 1; + } + } + return sts; +} + +/* ---------------------------------------------------------------------- */ +/* Function to perform basic timer soft reset */ +/* ---------------------------------------------------------------------- */ + +/** Peform soft reset of specified timer. + * @param btimer_id Basic Timer ID + * @note Soft reset set all registers to POR values. + * Spins 256 times waiting on hardware to clear reset bit. + */ +void btimer_reset(uint8_t btimer_id) +{ + uint32_t wait_cnt; + uint8_t soft_reset_sts; + + if (btmr_valid(btimer_id)) { + + p_btimer_ctrl_soft_reset_set(btimer_id); + + wait_cnt = 256ul; + do { + soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id); + + if (0 == soft_reset_sts){ + break; + } + } + while ( wait_cnt-- ); + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions to halt/unhalt the timer counting */ +/* ---------------------------------------------------------------------- */ + +/** Halt timer counting with no reload on unhalt. + * @param btimer_id Basic Timer ID. + * @note A halted timer will not reload the count register when + * unhalted, it will continue counting from the current + * count value. + */ +void btimer_halt(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_halt_set(btimer_id); + } +} + +/** Unhalt timer counting. + * @param btimer_id Basic Timer ID. + */ +void btimer_unhalt(uint8_t btimer_id) +{ + if ( btmr_valid(btimer_id) ) { + + p_btimer_ctrl_halt_clr(btimer_id); + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Basic Timer interrupt */ +/* ---------------------------------------------------------------------- */ + +/** Enable specified timer's interrupt from the block. + * @param btimer_id Basic Timer ID. + * @param ien Non-zero enable interrupt in timer block, 0 + * disable. + */ +void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien) +{ + if (btmr_valid(btimer_id)) { + + p_btimer_int_enable_set(btimer_id); + + if (ien) { + p_btimer_int_enable_set(btimer_id); + } else { + p_btimer_int_enable_clr(btimer_id); + } + } +} + +/** Read Timer interrupt status and clear if set + * @param btimer_id Basic Timer ID. + * @return uint8_t 1 (Timer interrupt status set) else 0. + * @note If timer interrupt status is set then clear it before + * returning. + */ +uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id) +{ + uint8_t sts; + + sts = 0; + if (btmr_valid(btimer_id)) { + + sts = p_btimer_int_status_get(btimer_id); + if (sts) { + p_btimer_int_status_clr(btimer_id); + } + } + return sts; +} + +#if 0 //Temporary disable until interrupt module + +/* ---------------------------------------------------------------------- */ +/* Functions for Basic Timer GIRQ */ +/* ---------------------------------------------------------------------- */ + +/** Enables GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_set(uint8_t btimer_id) +{ + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id); + } +} + +/** Clears GIRQ enable bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_enable_clr(uint8_t btimer_id) +{ + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id); + } + +} + +/** Returns GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(src bit not set), Non-zero (src bit set) + */ +uint8_t btimer_girq_src_get(uint8_t btimer_id) +{ + uint8_t retVal; + + retVal = 0; + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id); + } + + return retVal; +} + +/** Clears GIRQ source bit for the timer + * @param btimer_id Basic Timer ID. + */ +void btimer_girq_src_clr(uint8_t btimer_id) +{ + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id); + } +} + +/** Returns GIRQ result bit for the timer + * @param btimer_id Basic Timer ID. + * @return uint8_t 0(result bit not set), Non-zero (result bit set) + */ +uint8_t btimer_girq_result_get(uint8_t btimer_id) +{ + uint8_t retVal; + + retVal = 0; + if (btmr_valid(btimer_id)) + { + //Note: Bit Position is same as Timer ID + retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id); + } + + return retVal; +} +#endif + +/* ---------------------------------------------------------------------- */ +/* Functions for Basic Timer Sleep */ +/* ---------------------------------------------------------------------- */ + +/** Enable/Disable clock gating on idle of a timer + * @param btimer_id Basic Timer ID. + * @param sleep_en 1 = Sleep enable, 0 = Sleep disable + */ +void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en) +{ + uint32_t pcr_blk_id; + + if ( btmr_valid(btimer_id) ) + { + pcr_blk_id = btmr_pcr_id[btimer_id]; + + pcr_sleep_enable(pcr_blk_id, sleep_en); + } +} + +/** Returns clk required status for the timer block + * @param btimer_id Basic Timer ID. + * @return Non-zero if clk required, else 0 + */ +uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id) +{ + uint32_t retVal; + uint32_t pcr_blk_id; + + retVal = 0ul; + if ( btmr_valid(btimer_id) ) + { + pcr_blk_id = btmr_pcr_id[btimer_id]; + + retVal = pcr_clock_reqd_status_get(pcr_blk_id); + } + + return retVal; +} + +/** Enable/Disable reset on sleep for the timer block + * @param btimer_id Basic Timer ID. + * @param reset_en 1 to enable, 0 to disable + */ +void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en) +{ + uint32_t pcr_blk_id; + + if ( btmr_valid(btimer_id) ) + { + pcr_blk_id = btmr_pcr_id[btimer_id]; + + pcr_reset_enable(pcr_blk_id, reset_en); + } +} + +/* end btimer_api.c */ + +/** @} //Peripheral Basic_Timer + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c new file mode 100644 index 000000000..b2c9b97bc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/basic_timer/btimer_perphl.c @@ -0,0 +1,287 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #2 $ +$DateTime: 2015/11/24 06:27:00 $ +$Author: amohandas $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file btimer_perphl.c +* \brief Basic Timer Peripheral Source file +* \author jvasanth +* +* This file implements the Basic Timer Peripheral functions +******************************************************************************/ + +/** @defgroup Basic_Timer + * @{ + */ + +#include "common_lib.h" +#include "btimer.h" + +/** Basic Timer Instance base addresses */ +static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = { + CEC1302_TIMER_16_0, + CEC1302_TIMER_16_1, + CEC1302_TIMER_16_2, + CEC1302_TIMER_16_3, + CEC1302_TIMER_32_0, + CEC1302_TIMER_32_1 +}; + +/* ---------------------------------------------------------------------- */ +/* Functions to set and read Timer Counter Register */ +/* ---------------------------------------------------------------------- */ + +/** Sets timer counter + * @param btimer_id Basic Timer ID + * @param count - 32-bit counter + */ +void p_btimer_count_set(uint8_t btimer_id, uint32_t count) +{ + btmr_inst[btimer_id]->COUNT = count; +} + +/** Read the timer counter + * @param btimer_id Basic Timer ID + * @return count - 32-bit counter + */ +uint32_t p_btimer_count_get(uint8_t btimer_id) +{ + return btmr_inst[btimer_id]->COUNT; +} + +/* ---------------------------------------------------------------------- */ +/* Function to program the Preload */ +/* ---------------------------------------------------------------------- */ + +/** Sets preload for the counter + * @param btimer_id Basic Timer ID + * @param preload_count - 32-bit pre-load value + */ +void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count) +{ + btmr_inst[btimer_id]->PRE_LOAD = preload_count; +} + +/* ---------------------------------------------------------------------- */ +/* Functions for basic timer interrupts */ +/* ---------------------------------------------------------------------- */ + +/** Reads the interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + * @return status - 1 if interrupt status set, else 0 + */ +uint8_t p_btimer_int_status_get(uint8_t btimer_id) +{ + return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS); +} + +/** Clears interrupt status bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_status_clr(uint8_t btimer_id) +{ + // Write 1 to clear + btmr_inst[btimer_id]->INTERRUPT_STATUS = 1; +} + +/** Sets interrupt enable bit in the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1; +} + +/** Clears interrupt enable bit for the timer block + * @param btimer_id Basic Timer ID + */ +void p_btimer_int_enable_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0; +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Control Register */ +/* ---------------------------------------------------------------------- */ + +/** Writes the control register 32-bits + * @param btimer_id Basic Timer ID + * @param value - 32-bit value to program + */ +void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value) +{ + btmr_inst[btimer_id]->CONTROL.w = value; +} + +/** Reads the control register + * @param btimer_id Basic Timer ID + * @return uint32_t - 32-bit value + */ +uint32_t p_btimer_ctrl_read(uint8_t btimer_id) +{ + uint32_t retVal; + + retVal = btmr_inst[btimer_id]->CONTROL.w; + + return retVal; +} + +/** Sets enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE; +} + +/** Clears enable bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_enable_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE; +} + +/** Sets counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP; +} + +/** Clears counter direction bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP; +} + +/** Sets auto restart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART; +} + +/** Clears auto resetart bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART; +} + +/** Sets soft reset bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET; +} + +/** Read Soft Reset bit + * @param btimer_id Basic Timer ID + * @return 0 if soft reset status bit cleared; else non-zero value + */ +uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id) +{ + return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET); +} + +/** Sets start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START; +} + +/** Read start bit in the control register + * @param btimer_id Basic Timer ID + * @return 0 if start bit not set; else non-zero value + */ +uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id) +{ + return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START); +} + +/** Clears start bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_start_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START; +} + +/** Sets reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD; +} + +/** Clears reload bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_reload_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD; +} + +/** Sets halt bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_halt_set(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT; +} + +/** Clears halt bit in the control register + * @param btimer_id Basic Timer ID + */ +void p_btimer_ctrl_halt_clr(uint8_t btimer_id) +{ + btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT; +} + +/** Sets prescale value + * @param btimer_id Basic Timer ID + * @param prescaler - 16-bit pre-scale value + */ +void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler) +{ + btmr_inst[btimer_id]->CONTROL.h[1] = prescaler; +} + + +/* end btimer_perphl.c */ + +/** @} //Peripheral Basic_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h new file mode 100644 index 000000000..f8fc613b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common.h @@ -0,0 +1,71 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * common.h + * This is the header file including common headers from various modules + ********************************************************************************** + * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $ + * Description: added ict module + ********************************************************************************** + * #xx + ********************************************************************************** + * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $ + */ + +/*********************************************************************************/ +/** @defgroup common common + * @{ + */ + +/** @file common.h +* \brief header file including common headers from various modules +* \author App Firmware Team +* +**********************************************************************************/ +#ifndef _COMMON_H_ +#define _COMMON_H_ + +// Include common headers from various modules +// !!! The include order is important !!! +#include "cfg.h" +#include "platform.h" +#include "MCHP_CEC1302.h" +#include "ARM_REG.h" +/* Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" +#include "MEC1322.h" + +#include "defs.h" +#include "string.h" + +#include "kernel.h" +#include "..\system\system.h" +#include "..\debug\trace.h" +#include "..\interrupt\interrupt.h" +#include "..\timer\timer_app.h" + +#include "cec1302_crypto_api.h" + +#endif /*_COMMON_H_*/ + +/** @} + */ + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h new file mode 100644 index 000000000..b97c5015e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/common_lib.h @@ -0,0 +1,64 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * common.h + * This is the header file including common headers from various modules + ********************************************************************************** + * $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $ + * Description: added ict module + ********************************************************************************** + * #xx + ********************************************************************************** + * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $ + */ + +/*********************************************************************************/ +/** @defgroup common common + * @{ + */ + +/** @file common.h +* \brief header file including common headers from various modules +* \author App Firmware Team +* +**********************************************************************************/ +#ifndef _COMMON_LIB_H_ +#define _COMMON_LIB_H_ + +// Include common headers from various modules +// !!! The include order is important !!! +#include "platform.h" +#include "ARM_REG.h" +#include "MCHP_CEC1302.h" +/* Cortex-M4 processor and core peripherals */ +#include "core_cm4.h" +#include "MEC1322.h" +#include "defs.h" +#include "string.h" +//_RB_#include "build.h" +//_RB_#include "..\system\system.h" +//_RB_#include "..\debug\trace.h" +#include +#endif /*_COMMON_LIB_H_*/ + +/** @} + */ + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h new file mode 100644 index 000000000..d900fab29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/defs.h @@ -0,0 +1,54 @@ +/* + ********************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. + ********************************************************************************** + * defs.h + * This is the definition header file for generic usages + ********************************************************************************** + * #xx + ********************************************************************************** + * $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $ + */ + + +/*********************************************************************************/ +/** @defgroup defs defs + * @{ + */ + +/** @file defs.h +* \brief definition header file for generic usages +* \author App Firmware Team +* +**********************************************************************************/ +#ifndef _DEFS_H_ +#define _DEFS_H_ + +/* bit operation MACRO, xvar could be byte, word or dword */ +#define mSET_BIT(x, xvar) ( xvar |= x ) +#define mCLR_BIT(x, xvar) ( xvar &= ~x ) +#define mGET_BIT(x, xvar) ( xvar & x ) +#define mCLR_SRC_BIT(x, xvar) ( xvar = x ) +#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}} + +#endif /*_DEFS_H_*/ + +/** @} + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h new file mode 100644 index 000000000..cf94dd5eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer.h @@ -0,0 +1,111 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/12/17 01:09:00 $ +$Author: snakka $ +Last Change: Updated for peripheral functions prefix p_ +******************************************************************************/ +/** @file btimer.h +* \brief Hibernation Timer Peripheral Header file +* \author jvasanth +* +* This file is the header file for Hibernation Timer Peripheral +******************************************************************************/ + +/** @defgroup Hibernation_Timer + * @{ + */ + +#ifndef _HTIMER_H +#define _HTIMER_H + +/******************************************************************************/ +/** Logical Timer ID for APIs. + * This is the timer IDs passed to Hibernation Timer function calls + *******************************************************************************/ +enum _PID_HTIMER_ +{ + PID_HTIMER_0, + PID_HTIMER_MAX +}; + +#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX + +/* -------------------------------------------------------------------- */ +/* Hibernation Timer APIs */ +/* -------------------------------------------------------------------- */ +/** Enables hibernation timer + * @param htimer_id Hibernation Timer ID + * @param preload_value - 16-bit preload value + * @param resolution_mode 0 - resolution of 30.5us per LSB, + * 1 - resolution of 0.125s per LSB + */ +void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode); + +/** Disables the hibernation timer by programming the prelaod value as 0 + * @param htimer_id Hibernation Timer ID + */ +void htimer_disable(uint8_t htimer_id); + + +/** Reloads new preload value for the hibernation timer + * @param htimer_id Hibernation Timer ID + * @param reload_value - 16-bit preload value + */ +void htimer_reload(uint8_t htimer_id, uint16_t reload_value); + + +/* -------------------------------------------------------------------- */ +/* Hibernation Timer Peripheral Functions */ +/* -------------------------------------------------------------------- */ +/** Sets hibernation timer preload value + * @param htimer_id Hibernation Timer ID + * @param preload_value - 16-bit preload value + */ +void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value); + +/*_RB_ Added by RB. */ +uint16_t p_htimer_preload_get(uint8_t htimer_id); + +/** Sets hibernation timer resolution + * @param htimer_id Hibernation Timer ID + * @param resolution_mode 0 - resolution of 30.5us per LSB, + * 1 - resolution of 0.125s per LSB + */ +void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode); + + +/** Returns the Hibernation Timer current count value + * @param htimer_id Hibernation Timer ID + * @return 16-bit count value + */ +uint16_t p_htimer_count_get(uint8_t htimer_id); + + +#endif // #ifndef _HTIMER_H + +/* end htimer.h */ + +/** @} //Peripherals Hibernation_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c new file mode 100644 index 000000000..1441bcf36 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_api.c @@ -0,0 +1,112 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/12/17 01:09:00 $ +$Author: snakka $ +Last Change: Updated for peripheral functions prefix p_ +******************************************************************************/ +/** @file btimer_perphl.c +* \brief Hibernation Timer API Source file +* \author jvasanth +* +* This file implements Hibernation Timer APIs +******************************************************************************/ + +/** @defgroup Hibernation_Timer + * @{ + */ + +#include "common_lib.h" +#include "htimer.h" + +#ifdef PLIB_HTIMER_CHECK_ID + +/** Local helper that checks if logical Timer ID is valid. + * @param htimer_id Hibernation Timer ID + * @return uint8_t Non-zero(VALID), 0(Invalid) + */ +static uint8_t htmr_valid(uint8_t htimer_id) +{ + if ( htimer_id < (PID_HTIMER_MAX ) ) { + return 1; + } + return 0; +} + +#else + + +/** This version of tmr_valid skips checking always returning 1. + * Compiler may optimize it out. + * @param htimer_id Hibernation Timer ID + * @return uint8_t 1(VALID) + */ +static uint8_t htmr_valid(uint8_t htimer_id) { return 1; } + +#endif + + +/** Enables hibernation timer + * @param htimer_id Hibernation Timer ID + * @param preload_value - 16-bit preload value + * @param resolution_mode 0 - resolution of 30.5us per LSB, + * 1 - resolution of 0.125s per LSB + */ +void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode) +{ + if (htmr_valid(htimer_id)) + { + p_htimer_preload_set(htimer_id, preload_value); + + p_htimer_resolution_set(htimer_id, resolution_mode); + } +} + +/** Disables the hibernation timer by programming the prelaod value as 0 + * @param htimer_id Hibernation Timer ID + */ +void htimer_disable(uint8_t htimer_id) +{ + if (htmr_valid(htimer_id)) + { + p_htimer_preload_set(htimer_id, 0); + } +} + +/** Reloads new preload value for the hibernation timer + * @param htimer_id Hibernation Timer ID + * @param reload_value - 16-bit preload value + */ +void htimer_reload(uint8_t htimer_id, uint16_t reload_value) +{ + if ( htmr_valid(htimer_id)) + { + p_htimer_preload_set(htimer_id, reload_value); + } +} + +/* end htimer_api.c */ + +/** @} //APIs Hibernation_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c new file mode 100644 index 000000000..64d632649 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/htimer/htimer_perphl.c @@ -0,0 +1,93 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/12/17 01:09:00 $ +$Author: snakka $ +Last Change: Updated for peripheral functions prefix p_ +******************************************************************************/ +/** @file btimer_perphl.c +* \brief Hibernation Timer Peripheral Source file +* \author jvasanth +* +* This file implements Hibernation Timer Peripheral functions +******************************************************************************/ + +/** @defgroup Hibernation_Timer + * @{ + */ + +#include "common_lib.h" +#include "htimer.h" + +/** Hibernation Timer Instance base addresses */ +static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = { + CEC1302_HTM +}; + +/** Sets hibernation timer preload value + * @param htimer_id Hibernation Timer ID + * @param preload_value - 16-bit preload value + * @note Setting the preload with a non-zero value starts + * the hibernation timer to down count. Setting the preload + * to 0 disables the hibernation counter + */ +void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value) +{ + htmr_inst[htimer_id]->PRELOAD = preload_value; +} + +/** Sets hibernation timer resolution + * @param htimer_id Hibernation Timer ID + * @param resolution_mode 0 - resolution of 30.5us per LSB, + * 1 - resolution of 0.125s per LSB + */ +void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode) +{ + htmr_inst[htimer_id]->CONTROL = resolution_mode; +} + +/** Returns the Hibernation Timer current count value + * @param htimer_id Hibernation Timer ID + * @return 16-bit count value + */ +uint16_t p_htimer_count_get(uint8_t htimer_id) +{ + uint16_t htimer_count; + + htimer_count = htmr_inst[htimer_id]->COUNT; + + return htimer_count; +} + +/*_RB_ Added by RB. */ +uint16_t p_htimer_preload_get(uint8_t htimer_id) +{ + return htmr_inst[htimer_id]->PRELOAD; +} + + +/* end htimer_perphl.c */ + +/** @} //Peripheral Hibernation_Timer + */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h new file mode 100644 index 000000000..2b30af9eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/interrupt/interrupt.h @@ -0,0 +1,1176 @@ +/**************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*/ + +/** @defgroup interrupt interrupt + * @{ + */ +/** @file interrupt.h + \brief This is the header file for interrupt.c + This program is designed to allow the other C programs to be able to use this component + + There are entry points for all C wrapper API implementation + +Platform: This is ARC-based component + +Toolset: Metaware IDE(8.5.1) +Reference: smsc_reusable_fw_requirement.doc */ + +/******************************************************************************* + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/kernel/skern/source/interrupt/interrupt.h $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2015/12/23 15:37:58 $ + * AUTHOR: $Author: akrishnan $ + * + * Revision history (latest first): + * #xx + *********************************************************************************** + */ + +#ifndef _INTERRUPT_H_ +#define _INTERRUPT_H_ + + +/* public function prototypes */ +void interrupt_block_init(void); +void null_handler(void); + +/* macro for interrupt control */ +/* 16-bit timers interrupt control */ +#define sbit_TIMER0 ( 1UL << 0UL ) +#define sbit_TIMER1 ( 1UL << 1UL ) +#define sbit_TIMER2 ( 1UL << 2UL ) +#define sbit_TIMER3 ( 1UL << 3Ul ) + +#define disable_timer0_irq() mCLR_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_timer0_irq() mSET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_timer0_source() mCLR_SRC_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE) +#define get_timer0_source() mGET_BIT(sbit_TIMER0, MMCR_EC_GIRQ23_SOURCE) + +#define disable_timer1_irq() mCLR_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_timer1_irq() mSET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_timer1_source() mCLR_SRC_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE) +#define get_timer1_source() mGET_BIT(sbit_TIMER1, MMCR_EC_GIRQ23_SOURCE) + +#define disable_timer2_irq() mCLR_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_timer2_irq() mSET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_timer2_source() mCLR_SRC_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE) +#define get_timer2_source() mGET_BIT(sbit_TIMER2, MMCR_EC_GIRQ23_SOURCE) + +#define disable_timer3_irq() mCLR_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_timer3_irq() mSET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_timer3_source() mCLR_SRC_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE) +#define get_timer3_source() mGET_BIT(sbit_TIMER3, MMCR_EC_GIRQ23_SOURCE) + + +/* hibernation timers interrupt control */ +#define sbit_HTIMER0 ( 1UL << 20 ) +#define sbit_HTIMER1 b_bit14 + +#define disable_htimer0_irq() mCLR_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET) +#define enable_htimer0_irq() mSET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_ENABLE_SET) +#define clear_htimer0_source() mCLR_SRC_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE) +#define get_htimer0_source() mGET_BIT(sbit_HTIMER0, MMCR_EC_GIRQ17_SOURCE) + +#define disable_htimer1_irq() mCLR_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_htimer1_irq() mSET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_htimer1_source() mCLR_SRC_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE) +#define get_htimer1_source() mGET_BIT(sbit_HTIMER1, MMCR_EC_GIRQ23_SOURCE) + +/* RTC interrupt control */ +#define b_bit18 (1 << 18) +#define b_bit19 (1 << 19) +#define sbit_RTC_INT b_bit18 +#define disable_rtc_irq() mCLR_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) +#define enable_rtc_irq() mSET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) +#define clear_rtc_irq_source() mCLR_SRC_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) +#define get_rtc_irq_source() mGET_BIT(sbit_RTC_INT, MMCR_EC_GIRQ17_ENABLE_SET) +/* RTC alarm interrupt control */ +#define sbit_RTC_ALM_INT b_bit19 +#define disable_rtc_alm_irq() mCLR_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) +#define enable_rtc_alm_irq() mSET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) +#define clear_rtc_irq_alm_source() mCLR_SRC_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) +#define get_rtc_irq_alm_source() mGET_BIT(sbit_RTC_ALM_INT, MMCR_EC_GIRQ17_ENABLE_SET) + +/* week timer interrupt control */ +#define sbit_WKTIMER b_bit7 + +#define disable_wktimer_irq() mCLR_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_wktimer_irq() mSET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_wktimer_source() mCLR_SRC_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE) +#define get_wktimer_source() mGET_BIT(sbit_WKTIMER, MMCR_EC_GIRQ23_SOURCE) + + +/* scan matrix interrupt control */ +#define sbit_SCANNER b_bit16 +#define disable_scanner_irq() mCLR_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET) +#define enable_scanner_irq() mSET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_ENABLE_SET) +#define clear_scanner_source() mCLR_SRC_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE) +#define get_scanner_source() mGET_BIT(sbit_SCANNER, MMCR_EC_GIRQ18_SOURCE) + + +/* PS2 interrupt control */ +/* PS2 activity interrupt */ +#define sbit_PS2_ACT_0 b_bit13 +#define sbit_PS2_ACT_1 b_bit14 +#define sbit_PS2_ACT_2 b_bit15 +/* PS2 wakeup interrupt: detect start bit */ +#define sbit_PS2_WK_0A b_bit17 +#define sbit_PS2_WK_1B b_bit20 +#define sbit_PS2_WK_2 b_bit21 + +/* PS2 activity interrupt control */ +#define disable_ps2_act_0_irq() mCLR_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET) +#define enable_ps2_act_0_irq() mSET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_ENABLE_SET) +#define clear_ps2_act_0_source() mCLR_SRC_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE) +#define get_ps2_act_0_source() mGET_BIT(sbit_PS2_ACT_0, MMCR_EC_GIRQ19_SOURCE) + +#define disable_ps2_act_1_irq() mCLR_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET) +#define enable_ps2_act_1_irq() mSET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_ENABLE_SET) +#define clear_ps2_act_1_source() mCLR_SRC_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE) +#define get_ps2_act_1_source() mGET_BIT(sbit_PS2_ACT_1, MMCR_EC_GIRQ19_SOURCE) + +#define disable_ps2_act_2_irq() mCLR_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET) +#define enable_ps2_act_2_irq() mSET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_ENABLE_SET) +#define clear_ps2_act_2_source() mCLR_SRC_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE) +#define get_ps2_act_2_source() mGET_BIT(sbit_PS2_ACT_2, MMCR_EC_GIRQ19_SOURCE) + +/* PS2 wakeup interrupt control */ +#define disable_ps2_wk_0_irq() mCLR_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET) +#define enable_ps2_wk_0_irq() mSET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_ENABLE_SET) +#define clear_ps2_wk_0_source() mCLR_SRC_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE) +#define get_ps2_wk_0_source() mGET_BIT(sbit_PS2_WK_0A, MMCR_EC_GIRQ19_SOURCE) + +#define disable_ps2_wk_1_irq() mCLR_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET) +#define enable_ps2_wk_1_irq() mSET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_ENABLE_SET) +#define clear_ps2_wk_1_source() mCLR_SRC_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE) +#define get_ps2_wk_1_source() mGET_BIT(sbit_PS2_WK_1B, MMCR_EC_GIRQ19_SOURCE) + +#define disable_ps2_wk_2_irq() mCLR_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET) +#define enable_ps2_wk_2_irq() mSET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_ENABLE_SET) +#define clear_ps2_wk_2_source() mCLR_SRC_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE) +#define get_ps2_wk_2_source() mGET_BIT(sbit_PS2_WK_2, MMCR_EC_GIRQ19_SOURCE) + + +/* ICT interrupt control */ +/* capture 0~5 interrupt */ +#define sbit_ICT_CAPTURE0 b_bit17 +#define sbit_ICT_CAPTURE1 b_bit18 +#define sbit_ICT_CAPTURE2 b_bit19 +#define sbit_ICT_CAPTURE3 b_bit20 +#define sbit_ICT_CAPTURE4 b_bit21 +#define sbit_ICT_CAPTURE5 b_bit22 + +/* capture 0 interrupt control */ +#define disable_capture0_irq() mCLR_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET) +#define enable_capture0_irq() mSET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_ENABLE_SET) +#define clear_capture0_source() mCLR_SRC_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE) +#define get_capture0_source() mGET_BIT(sbit_ICT_CAPTURE0, MMCR_EC_GIRQ23_SOURCE) + + +/* SMBus interrupt control */ + + +/* GPIO interrupt control */ + + +/* BC link interrupt control */ +/* bclink A~D interrupt */ +#define sbit_BCLINK_A_BUSY b_bit0 +#define sbit_BCLINK_A_ERR b_bit1 +#define sbit_BCLINK_A_INT b_bit2 +#define sbit_BCLINK_B_BUSY b_bit3 +#define sbit_BCLINK_B_ERR b_bit4 +#define sbit_BCLINK_B_INT b_bit5 +#define sbit_BCLINK_C_BUSY b_bit6 +#define sbit_BCLINK_C_ERR b_bit7 +#define sbit_BCLINK_C_INT b_bit8 +#define sbit_BCLINK_D_BUSY b_bit9 +#define sbit_BCLINK_D_ERR b_bit10 +#define sbit_BCLINK_D_INT b_bit11 + +/* bclink B interrupt control */ +#define disable_bclink_b_busy_irq() mCLR_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET) +#define enable_bclink_b_busy_irq() mSET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_ENABLE_SET) +#define clear_bclink_b_busy_source() mCLR_SRC_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE) +#define get_bclink_b_busy_source() mGET_BIT(sbit_BCLINK_B_BUSY, MMCR_EC_GIRQ18_SOURCE) + +#define disable_bclink_b_err_irq() mCLR_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET) +#define enable_bclink_b_err_irq() mSET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_ENABLE_SET) +#define clear_bclink_b_err_source() mCLR_SRC_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE) +#define get_bclink_b_err_source() mGET_BIT(sbit_BCLINK_B_ERR, MMCR_EC_GIRQ18_SOURCE) + +#define disable_bclink_b_int_irq() mCLR_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET) +#define enable_bclink_b_int_irq() mSET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_ENABLE_SET) +#define clear_bclink_b_int_source() mCLR_SRC_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE) +#define get_bclink_b_int_source() mGET_BIT(sbit_BCLINK_B_INT, MMCR_EC_GIRQ18_SOURCE) + +/* UART interrupt control */ +#define sbit_UART_INT b_bit0 + +#define disable_uart_irq() mCLR_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET) +#define enable_uart_irq() mSET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_ENABLE_SET) +#define clear_uart_irq_source() mCLR_SRC_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE) +#define get_uart_irq_source() mGET_BIT(sbit_UART_INT, MMCR_EC_GIRQ15_SOURCE) + +// GIRQ IDs for EC Interrupt Aggregator +enum MEC_GIRQ_IDS +{ + MEC_GIRQ08_ID = 0, + MEC_GIRQ09_ID, + MEC_GIRQ10_ID, + MEC_GIRQ11_ID, + MEC_GIRQ12_ID, + MEC_GIRQ13_ID, + MEC_GIRQ14_ID, + MEC_GIRQ15_ID, + MEC_GIRQ16_ID, + MEC_GIRQ17_ID, + MEC_GIRQ18_ID, + MEC_GIRQ19_ID, + MEC_GIRQ20_ID, + MEC_GIRQ21_ID, + MEC_GIRQ22_ID, + MEC_GIRQ23_ID, + MEC_GIRQ_ID_MAX +}; + +//Bitmask of GIRQ in ECIA Block Registers +#define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8)) +#define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8)) +#define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8)) +#define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8)) +#define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8)) +#define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8)) +#define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8)) +#define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8)) +#define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8)) +#define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8)) +#define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8)) +#define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8)) +#define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8)) +#define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8)) +#define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8)) +#define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8)) + +#define INTERRUPT_MODE_ALL_AGGREGATED (0u) +#define INTERRUPT_MODE_DIRECT (1u) + +// Bit map of GIRQs whose sources can be directly connected to the NVIC +// GIRQs 12 - 18, 23 +#define ECIA_GIRQ_DIRECT_BITMAP (0x0087F000ul) + +/* + * n = b[7:0] = zero-based direct mapped NVIC ID + * m = b[15:8] = zero-based aggregated NVIC ID + * a = b[23:16] = block Aggregator register block ID + * b = b[31:24] = block bit position in Aggregator registers +*/ +#define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \ + (((uint32_t)(m)&0xFFul)<<8u) + \ + ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \ + (((uint32_t)(b)&0x1Ful)<<24)) + +#define ECIA_NVIC_ID_BITPOS (0u) +#define ECIA_IA_NVIC_ID_BITPOS (8u) +#define ECIA_GIRQ_ID_BITPOS (16u) +#define ECIA_GIRQ_BIT_BITPOS (24u) + +// +// GIRQ08 +// +#define GPIO_0140_IROUTE IROUTE(0,8,57,57) +#define GPIO_0141_IROUTE IROUTE(1,8,57,57) +#define GPIO_0142_IROUTE IROUTE(2,8,57,57) +#define GPIO_0143_IROUTE IROUTE(3,8,57,57) +#define GPIO_0144_IROUTE IROUTE(4,8,57,57) +#define GPIO_0145_IROUTE IROUTE(5,8,57,57) +#define GPIO_0147_IROUTE IROUTE(7,8,57,57) +// +#define GPIO_0150_IROUTE IROUTE(8,8,57,57) +#define GPIO_0151_IROUTE IROUTE(9,8,57,57) +#define GPIO_0152_IROUTE IROUTE(10,8,57,57) +#define GPIO_0153_IROUTE IROUTE(11,8,57,57) +#define GPIO_0154_IROUTE IROUTE(12,8,57,57) +#define GPIO_0155_IROUTE IROUTE(13,8,57,57) +#define GPIO_0156_IROUTE IROUTE(14,8,57,57) +#define GPIO_0157_IROUTE IROUTE(15,8,57,57) +// +#define GPIO_0160_IROUTE IROUTE(16,8,57,57) +#define GPIO_0161_IROUTE IROUTE(17,8,57,57) +#define GPIO_0162_IROUTE IROUTE(18,8,57,57) +#define GPIO_0163_IROUTE IROUTE(19,8,57,57) +#define GPIO_0164_IROUTE IROUTE(20,8,57,57) +#define GPIO_0165_IROUTE IROUTE(21,8,57,57) +#define GPIO_0166_IROUTE IROUTE(22,8,57,57) +#define GPIO_0167_IROUTE IROUTE(23,8,57,57) + +// +// GIRQ09 +// +#define GPIO_0100_IROUTE IROUTE(0,9,58,58) +#define GPIO_0101_IROUTE IROUTE(1,9,58,58) +#define GPIO_0102_IROUTE IROUTE(2,9,58,58) +#define GPIO_0103_IROUTE IROUTE(3,9,58,58) +#define GPIO_0104_IROUTE IROUTE(4,9,58,58) +#define GPIO_0105_IROUTE IROUTE(5,9,58,58) +#define GPIO_0105_IROUTE IROUTE(5,9,58,58) +#define GPIO_0107_IROUTE IROUTE(7,9,58,58) +// +#define GPIO_0110_IROUTE IROUTE(8,9,58,58) +#define GPIO_0111_IROUTE IROUTE(9,9,58,58) +#define GPIO_0112_IROUTE IROUTE(10,9,58,58) +#define GPIO_0113_IROUTE IROUTE(11,9,58,58) +#define GPIO_0114_IROUTE IROUTE(12,9,58,58) +#define GPIO_0115_IROUTE IROUTE(13,9,58,58) +#define GPIO_0116_IROUTE IROUTE(14,9,58,58) +#define GPIO_0117_IROUTE IROUTE(15,9,58,58) +// +#define GPIO_0120_IROUTE IROUTE(16,9,58,58) +#define GPIO_0121_IROUTE IROUTE(17,9,58,58) +#define GPIO_0122_IROUTE IROUTE(18,9,58,58) +#define GPIO_0124_IROUTE IROUTE(20,9,58,58) +#define GPIO_0125_IROUTE IROUTE(21,9,58,58) +#define GPIO_0126_IROUTE IROUTE(22,9,58,58) +#define GPIO_0127_IROUTE IROUTE(23,9,58,58) +// +#define GPIO_0130_IROUTE IROUTE(24,9,58,58) +#define GPIO_0131_IROUTE IROUTE(25,9,58,58) +#define GPIO_0132_IROUTE IROUTE(26,9,58,58) +#define GPIO_0133_IROUTE IROUTE(27,9,58,58) +#define GPIO_0134_IROUTE IROUTE(28,9,58,58) +#define GPIO_0135_IROUTE IROUTE(29,9,58,58) +#define GPIO_0136_IROUTE IROUTE(30,9,58,58) + +// +// GIRQ10 +// +#define GPIO_0040_IROUTE IROUTE(0,10,59,59) +#define GPIO_0041_IROUTE IROUTE(1,10,59,59) +#define GPIO_0042_IROUTE IROUTE(2,10,59,59) +#define GPIO_0043_IROUTE IROUTE(3,10,59,59) +#define GPIO_0044_IROUTE IROUTE(4,10,59,59) +#define GPIO_0045_IROUTE IROUTE(5,10,59,59) +#define GPIO_0045_IROUTE IROUTE(5,10,59,59) +#define GPIO_0047_IROUTE IROUTE(7,10,59,59) +// +#define GPIO_0050_IROUTE IROUTE(8,10,59,59) +#define GPIO_0051_IROUTE IROUTE(9,10,59,59) +#define GPIO_0052_IROUTE IROUTE(10,10,59,59) +#define GPIO_0053_IROUTE IROUTE(11,10,59,59) +#define GPIO_0054_IROUTE IROUTE(12,10,59,59) +#define GPIO_0055_IROUTE IROUTE(13,10,59,59) +#define GPIO_0056_IROUTE IROUTE(14,10,59,59) +#define GPIO_0057_IROUTE IROUTE(15,10,59,59) +// +#define GPIO_0060_IROUTE IROUTE(16,10,59,59) +#define GPIO_0061_IROUTE IROUTE(17,10,59,59) +#define GPIO_0062_IROUTE IROUTE(18,10,59,59) +#define GPIO_0063_IROUTE IROUTE(19,10,59,59) +#define GPIO_0064_IROUTE IROUTE(20,10,59,59) +#define GPIO_0065_IROUTE IROUTE(21,10,59,59) +#define GPIO_0066_IROUTE IROUTE(22,10,59,59) +#define GPIO_0067_IROUTE IROUTE(23,10,59,59) +// +#define GPIO_0070_IROUTE IROUTE(24,10,59,59) +#define GPIO_0071_IROUTE IROUTE(25,10,59,59) +#define GPIO_0072_IROUTE IROUTE(26,10,59,59) +#define GPIO_0073_IROUTE IROUTE(27,10,59,59) +#define GPIO_0074_IROUTE IROUTE(28,10,59,59) +#define GPIO_0075_IROUTE IROUTE(29,10,59,59) +#define GPIO_0076_IROUTE IROUTE(30,10,59,59) + +// +// GIRQ11 +// +#define GPIO_0000_IROUTE IROUTE(0,11,60,60) +#define GPIO_0001_IROUTE IROUTE(1,11,60,60) +#define GPIO_0002_IROUTE IROUTE(2,11,60,60) +#define GPIO_0003_IROUTE IROUTE(3,11,60,60) +#define GPIO_0004_IROUTE IROUTE(4,11,60,60) +#define GPIO_0005_IROUTE IROUTE(5,11,60,60) +#define GPIO_0006_IROUTE IROUTE(6,11,60,60) +#define GPIO_0007_IROUTE IROUTE(7,11,60,60) +// +#define GPIO_0010_IROUTE IROUTE(8,11,60,60) +#define GPIO_0011_IROUTE IROUTE(9,11,60,60) +#define GPIO_0012_IROUTE IROUTE(10,11,60,60) +#define GPIO_0013_IROUTE IROUTE(11,11,60,60) +#define GPIO_0014_IROUTE IROUTE(12,11,60,60) +#define GPIO_0015_IROUTE IROUTE(13,11,60,60) +#define GPIO_0016_IROUTE IROUTE(14,11,60,60) +#define GPIO_0017_IROUTE IROUTE(15,11,60,60) +// +#define GPIO_0020_IROUTE IROUTE(16,11,60,60) +#define GPIO_0021_IROUTE IROUTE(17,11,60,60) +#define GPIO_0022_IROUTE IROUTE(18,11,60,60) +#define GPIO_0023_IROUTE IROUTE(19,11,60,60) +#define GPIO_0024_IROUTE IROUTE(20,11,60,60) +#define GPIO_0025_IROUTE IROUTE(21,11,60,60) +#define GPIO_0026_IROUTE IROUTE(22,11,60,60) +#define GPIO_0027_IROUTE IROUTE(23,11,60,60) +// +#define GPIO_0030_IROUTE IROUTE(24,11,60,60) +#define GPIO_0031_IROUTE IROUTE(25,11,60,60) +#define GPIO_0032_IROUTE IROUTE(26,11,60,60) +#define GPIO_0033_IROUTE IROUTE(27,11,60,60) +#define GPIO_0034_IROUTE IROUTE(28,11,60,60) +#define GPIO_0035_IROUTE IROUTE(29,11,60,60) +#define GPIO_0036_IROUTE IROUTE(30,11,60,60) + +// +// GIRQ12 +// +#define SMB0_IROUTE IROUTE(0,12,61,0) +#define SMB1_IROUTE IROUTE(1,12,61,1) +#define SMB2_IROUTE IROUTE(2,12,61,2) +#define SMB3_IROUTE IROUTE(3,12,61,3) +// SMB wakes have no direct connection to NVIC, always aggregated +#define SMB0_WAKE_IROUTE IROUTE(4,12,61,61) +#define SMB1_WAKE_IROUTE IROUTE(5,12,61,61) +#define SMB2_WAKE_IROUTE IROUTE(6,12,61,61) +#define SMB3_WAKE_IROUTE IROUTE(7,12,61,61) +#define SMB4_WAKE_IROUTE IROUTE(8,12,61,61) + +// +// GIRQ13 +// +#define DMA0_IROUTE IROUTE(16,13,62,4) +#define DMA1_IROUTE IROUTE(17,13,62,5) +#define DMA2_IROUTE IROUTE(18,13,62,6) +#define DMA3_IROUTE IROUTE(19,13,62,7) +#define DMA4_IROUTE IROUTE(20,13,62,8) +#define DMA5_IROUTE IROUTE(21,13,62,9) +#define DMA6_IROUTE IROUTE(22,13,62,10) +#define DMA7_IROUTE IROUTE(23,13,62,11) +#define DMA8_IROUTE IROUTE(24,13,62,81) +#define DMA9_IROUTE IROUTE(25,13,62,82) +#define DMA10_IROUTE IROUTE(26,13,62,83) +#define DMA11_IROUTE IROUTE(27,13,62,84) + +// +// GIRQ14 +// +#define LPC_BERR_IROUTE IROUTE(2,14,63,12) + +// +// GIRQ15 +// +#define UART0_IROUTE IROUTE(0,15,64,13) +#define EMI0_IROUTE IROUTE(2,15,64,14) +#define ACPI_EC0_IBF_IROUTE IROUTE(6,15,64,15) +#define ACPI_EC0_OBF_IROUTE IROUTE(7,15,64,16) +#define ACPI_EC1_IBF_IROUTE IROUTE(8,15,64,17) +#define ACPI_EC1_OBF_IROUTE IROUTE(9,15,64,18) +#define ACPI_PM1_CTL_IROUTE IROUTE(10,15,64,19) +#define ACPI_PM1_EN_IROUTE IROUTE(11,15,64,20) +#define ACPI_PM1_STS_IROUTE IROUTE(12,15,64,21) +#define EM8042_OBF_IROUTE IROUTE(13,15,64,22) +#define EM8042_IBF_IROUTE IROUTE(14,15,64,23) +#define MBOX_IROUTE IROUTE(15,15,64,24) +#define MBOX_DATA_IROUTE IROUTE(16,15,64,40) + +// +// GIRQ16 +// +#define PECI_IROUTE IROUTE(3,16,65,25) + +// +// GIRQ17 +// +#define TACH0_IROUTE IROUTE(0,17,66,26) +#define TACH1_IROUTE IROUTE(1,17,66,27) +#define PS2_0_WAKE_IROUTE IROUTE(2,17,66,66) +#define PS2_1_WAKE_IROUTE IROUTE(3,17,66,66) +#define PS2_2_WAKE_IROUTE IROUTE(4,17,66,66) +#define PS2_3_WAKE_IROUTE IROUTE(5,17,66,66) +#define BC_WAKE_IROUTE IROUTE(6,17,66,66) +#define ADC_SNGL_IROUTE IROUTE(10,17,66,28) +#define ADC_RPT_IROUTE IROUTE(11,17,66,29) +#define ADC2PWM1_IROUTE IROUTE(12,17,66,30) +#define ADC2PWM2_IROUTE IROUTE(13,17,66,31) +#define PS2_0_IROUTE IROUTE(14,17,66,32) +#define PS2_1_IROUTE IROUTE(15,17,66,33) +#define PS2_2_IROUTE IROUTE(16,17,66,34) +#define PS2_3_IROUTE IROUTE(17,17,66,35) +#define RTC_IROUTE IROUTE(18,17,66,91) +#define RTC_ALARM_IROUTE IROUTE(19,17,66,92) +#define HTIMER_IROUTE IROUTE(20,17,66,38) +#define KSC_IROUTE IROUTE(21,17,66,39) +#define KSC_WAKE_IROUTE IROUTE(22,17,66,66) +#define RPM_STALL_IROUTE IROUTE(23,17,66,41) +#define RPM_SPIN_IROUTE IROUTE(24,17,66,42) +#define PFR_IROUTE IROUTE(25,17,66,43) +#define LED0_IROUTE IROUTE(26,17,66,44) +#define LED1_IROUTE IROUTE(27,17,66,45) +#define LED2_IROUTE IROUTE(28,17,66,46) +#define BCM_ERR_IROUTE IROUTE(29,17,66,47) +#define BCM_BUSY_IROUTE IROUTE(30,17,66,48) + +// +// GIRQ18 +// +#define SPI0_TX_IROUTE IROUTE(0,18,67,36) +#define SPI0_RX_IROUTE IROUTE(1,18,67,37) +#define SPI1_TX_IROUTE IROUTE(2,18,67,55) +#define SPI1_RX_IROUTE IROUTE(3,18,67,56) +#define LED3_IROUTE IROUTE(4,18,67,85) +#define PKE_ERR_IROUTE IROUTE(5,18,67,86) +#define PKE_END_IROUTE IROUTE(6,18,67,87) +#define NDRNG_IROUTE IROUTE(7,18,67,88) +#define AES_IROUTE IROUTE(8,18,67,89) +#define HASH_IROUTE IROUTE(9,18,67,90) + +// +// GIRQ19, Aggregated only +// +#define LRESET_IROUTE IROUTE(0,19,68,68) +#define VCC_PWRGD_IROUTE IROUTE(1,19,68,68) + +// +// GIRQ20, Aggregated only +// +#define GPIO_0200_IROUTE IROUTE(0,20,69,69) +#define GPIO_0201_IROUTE IROUTE(1,20,69,69) +#define GPIO_0202_IROUTE IROUTE(2,20,69,69) +#define GPIO_0203_IROUTE IROUTE(3,20,69,69) +#define GPIO_0204_IROUTE IROUTE(4,20,69,69) +#define GPIO_0206_IROUTE IROUTE(6,20,69,69) +// +#define GPIO_0210_IROUTE IROUTE(8,20,69,69) +#define GPIO_0211_IROUTE IROUTE(9,20,69,69) +#define GPIO_0212_IROUTE IROUTE(10,20,69,69) +#define GPIO_0213_IROUTE IROUTE(11,20,69,69) + +// +// GIRQ21 +// +// No sources + +// +// GIRQ22 +// +// No sources + +// +// GIRQ23 +// +#define BTMR0_IROUTE IROUTE(0,23,72,49) +#define BTMR1_IROUTE IROUTE(1,23,72,50) +#define BTMR2_IROUTE IROUTE(2,23,72,51) +#define BTMR3_IROUTE IROUTE(3,23,72,52) +#define BTMR4_IROUTE IROUTE(4,23,72,53) +#define BTMR5_IROUTE IROUTE(5,23,72,54) + +// GIRQ08 Bit Positions +#define GIRQ08_GPIO_0140_BITPOS (0) +#define GIRQ08_GPIO_0141_BITPOS (1) +#define GIRQ08_GPIO_0142_BITPOS (2) +#define GIRQ08_GPIO_0143_BITPOS (3) +#define GIRQ08_GPIO_0144_BITPOS (4) +#define GIRQ08_GPIO_0145_BITPOS (5) +//#define GIRQ08_GPIO_0146_BITPOS (6) RESERVED +#define GIRQ08_GPIO_0147_BITPOS (7) +// +#define GIRQ08_GPIO_0150_BITPOS (8) +#define GIRQ08_GPIO_0151_BITPOS (9) +#define GIRQ08_GPIO_0152_BITPOS (10) +#define GIRQ08_GPIO_0153_BITPOS (11) +#define GIRQ08_GPIO_0154_BITPOS (12) +#define GIRQ08_GPIO_0155_BITPOS (13) +#define GIRQ08_GPIO_0156_BITPOS (14) +#define GIRQ08_GPIO_0157_BITPOS (15) +// +#define GIRQ08_GPIO_0160_BITPOS (16) +#define GIRQ08_GPIO_0161_BITPOS (17) +#define GIRQ08_GPIO_0162_BITPOS (18) +#define GIRQ08_GPIO_0163_BITPOS (19) +#define GIRQ08_GPIO_0164_BITPOS (20) +#define GIRQ08_GPIO_0165_BITPOS (21) +#define GIRQ08_GPIO_0166_BITPOS (22) +#define GIRQ08_GPIO_0167_BITPOS (23) +// +#define GIRQ08_MASK (0x00FFFFBFul) +#define GIRQ08_WAKE_CAPABLE_MASK (0x00FFFFBFul) +// + +// GIRQ09 Bit Positions +#define GIRQ09_GPIO_0100_BITPOS (0) +#define GIRQ09_GPIO_0101_BITPOS (1) +#define GIRQ09_GPIO_0102_BITPOS (2) +#define GIRQ09_GPIO_0103_BITPOS (3) +#define GIRQ09_GPIO_0104_BITPOS (4) +#define GIRQ09_GPIO_0105_BITPOS (5) +#define GIRQ09_GPIO_0106_BITPOS (6) +#define GIRQ09_GPIO_0107_BITPOS (7) +// +#define GIRQ09_GPIO_0110_BITPOS (8) +#define GIRQ09_GPIO_0111_BITPOS (9) +#define GIRQ09_GPIO_0112_BITPOS (10) +#define GIRQ09_GPIO_0113_BITPOS (11) +#define GIRQ09_GPIO_0114_BITPOS (12) +#define GIRQ09_GPIO_0115_BITPOS (13) +#define GIRQ09_GPIO_0116_BITPOS (14) +#define GIRQ09_GPIO_0117_BITPOS (15) +// +#define GIRQ09_GPIO_0120_BITPOS (16) +#define GIRQ09_GPIO_0121_BITPOS (17) +#define GIRQ09_GPIO_0122_BITPOS (18) +//#define GIRQ09_GPIO_0123_BITPOS (19) RESERVED +#define GIRQ09_GPIO_0124_BITPOS (20) +#define GIRQ09_GPIO_0125_BITPOS (21) +#define GIRQ09_GPIO_0126_BITPOS (22) +#define GIRQ09_GPIO_0127_BITPOS (23) +// +#define GIRQ09_GPIO_0130_BITPOS (24) +#define GIRQ09_GPIO_0131_BITPOS (25) +#define GIRQ09_GPIO_0132_BITPOS (26) +#define GIRQ09_GPIO_0133_BITPOS (27) +#define GIRQ09_GPIO_0134_BITPOS (28) +#define GIRQ09_GPIO_0135_BITPOS (29) +#define GIRQ09_GPIO_0136_BITPOS (30) +//#define GIRQ09_GPIO_0137_BITPOS (31) RESERVED +// +#define GIRQ09_MASK (0x7FF7FFFFul) +#define GIRQ09_WAKE_CAPABLE_MASK (0x7FF7FFFFul) +// + +// GIRQ10 Bit Positions +#define GIRQ10_GPIO_0040_BITPOS (0) +#define GIRQ10_GPIO_0041_BITPOS (1) +#define GIRQ10_GPIO_0042_BITPOS (2) +#define GIRQ10_GPIO_0043_BITPOS (3) +#define GIRQ10_GPIO_0044_BITPOS (4) +#define GIRQ10_GPIO_0045_BITPOS (5) +#define GIRQ10_GPIO_0046_BITPOS (6) +#define GIRQ10_GPIO_0047_BITPOS (7) +// +#define GIRQ10_GPIO_0050_BITPOS (8) +#define GIRQ10_GPIO_0051_BITPOS (9) +#define GIRQ10_GPIO_0052_BITPOS (10) +#define GIRQ10_GPIO_0053_BITPOS (11) +#define GIRQ10_GPIO_0054_BITPOS (12) +#define GIRQ10_GPIO_0055_BITPOS (13) +#define GIRQ10_GPIO_0056_BITPOS (14) +#define GIRQ10_GPIO_0057_BITPOS (15) +// +#define GIRQ10_GPIO_0060_BITPOS (16) +#define GIRQ10_GPIO_0061_BITPOS (17) +#define GIRQ10_GPIO_0062_BITPOS (18) +#define GIRQ10_GPIO_0063_BITPOS (19) +#define GIRQ10_GPIO_0064_BITPOS (20) +#define GIRQ10_GPIO_0065_BITPOS (21) +#define GIRQ10_GPIO_0066_BITPOS (22) +#define GIRQ10_GPIO_0067_BITPOS (23) +// +#define GIRQ10_GPIO_0070_BITPOS (24) +#define GIRQ10_GPIO_0071_BITPOS (25) +#define GIRQ10_GPIO_0072_BITPOS (26) +#define GIRQ10_GPIO_0073_BITPOS (27) +#define GIRQ10_GPIO_0074_BITPOS (28) +#define GIRQ10_GPIO_0075_BITPOS (29) +#define GIRQ10_GPIO_0076_BITPOS (30) +//#define GIRQ10_GPIO_0077_BITPOS (31) RESERVED +// +#define GIRQ10_MASK (0x7FFFFFFFul) +#define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul) +// + +// GIRQ11 Bit Positions +#define GIRQ11_GPIO_0000_BITPOS (0) +#define GIRQ11_GPIO_0001_BITPOS (1) +#define GIRQ11_GPIO_0002_BITPOS (2) +#define GIRQ11_GPIO_0003_BITPOS (3) +#define GIRQ11_GPIO_0004_BITPOS (4) +#define GIRQ11_GPIO_0005_BITPOS (5) +#define GIRQ11_GPIO_0006_BITPOS (6) +#define GIRQ11_GPIO_0007_BITPOS (7) +// +#define GIRQ11_GPIO_0010_BITPOS (8) +#define GIRQ11_GPIO_0011_BITPOS (9) +#define GIRQ11_GPIO_0012_BITPOS (10) +#define GIRQ11_GPIO_0013_BITPOS (11) +#define GIRQ11_GPIO_0014_BITPOS (12) +#define GIRQ11_GPIO_0015_BITPOS (13) +#define GIRQ11_GPIO_0016_BITPOS (14) +#define GIRQ11_GPIO_0017_BITPOS (15) +// +#define GIRQ11_GPIO_0020_BITPOS (16) +#define GIRQ11_GPIO_0021_BITPOS (17) +#define GIRQ11_GPIO_0022_BITPOS (18) +#define GIRQ11_GPIO_0023_BITPOS (19) +#define GIRQ11_GPIO_0024_BITPOS (20) +#define GIRQ11_GPIO_0025_BITPOS (21) +#define GIRQ11_GPIO_0026_BITPOS (22) +#define GIRQ11_GPIO_0027_BITPOS (23) +// +#define GIRQ11_GPIO_0030_BITPOS (24) +#define GIRQ11_GPIO_0031_BITPOS (25) +#define GIRQ11_GPIO_0032_BITPOS (26) +#define GIRQ11_GPIO_0033_BITPOS (27) +#define GIRQ11_GPIO_0034_BITPOS (28) +#define GIRQ11_GPIO_0035_BITPOS (29) +#define GIRQ11_GPIO_0036_BITPOS (30) +//#define GIRQ11_GPIO_0037_BITPOS (31) RESERVED +// +#define GIRQ11_MASK (0x7FFFFFFFul) +#define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul) +// + +// GIRQ12 Bit Positions +#define GIRQ12_SMBUS0_BITPOS (0) +#define GIRQ12_SMBUS1_BITPOS (1) +#define GIRQ12_SMBUS2_BITPOS (2) +#define GIRQ12_SMBUS3_BITPOS (3) +#define GIRQ12_SMBUS0_WAKE_BITPOS (4) +#define GIRQ12_SMBUS1_WAKE_BITPOS (5) +#define GIRQ12_SMBUS2_WAKE_BITPOS (6) +#define GIRQ12_SMBUS3_WAKE_BITPOS (7) +#define GIRQ12_SMBUS4_WAKE_BITPOS (8) +// RESERVED bits[31:9] +#define GIRQ12_MASK (0x01FFul) +#define GIRQ12_WAKE_CAPABLE_MASK (0x01F0ul) +// + +// GIRQ13 Bit Positions +#define GIRQ13_DMA0_BITPOS (16) +#define GIRQ13_DMA1_BITPOS (17) +#define GIRQ13_DMA2_BITPOS (18) +#define GIRQ13_DMA3_BITPOS (19) +#define GIRQ13_DMA4_BITPOS (20) +#define GIRQ13_DMA5_BITPOS (21) +#define GIRQ13_DMA6_BITPOS (22) +#define GIRQ13_DMA7_BITPOS (23) +#define GIRQ13_DMA8_BITPOS (24) +#define GIRQ13_DMA9_BITPOS (25) +#define GIRQ13_DMA10_BITPOS (26) +#define GIRQ13_DMA11_BITPOS (27) +// +#define GIRQ13_MASK (0x0FFF0000ul) +#define GIRQ13_WAKE_CAPABLE_MASK (0x00000000ul) +// + +// GIRQ14 Bit Positions +#define GIRQ14_LPC_BITPOS (2) +// +#define GIRQ14_MASK (0x04ul) +#define GIRQ14_WAKE_CAPABLE_MASK (0x00ul) +// + +// GIRQ15 Bit Positions +#define GIRQ15_UART0_BITPOS (0) +#define GIRQ15_IMAP_BITPOS (2) +#define GIRQ15_KBD_K_BITPOS (3) +#define GIRQ15_KBD_M_BITPOS (4) +#define GIRQ15_ACPI0_IBF_BITPOS (6) +#define GIRQ15_ACPI0_OBF_BITPOS (7) +#define GIRQ15_ACPI1_IBF_BITPOS (8) +#define GIRQ15_ACPI1_OBF_BITPOS (9) +#define GIRQ15_ACPI_PM1CTL_BITPOS (10) +#define GIRQ15_ACPI_PM1EN_BITPOS (11) +#define GIRQ15_ACPI_PM1STS_BITPOS (12) +#define GIRQ15_MF8042_OBF_BITPOS (13) +#define GIRQ15_MF8042_IBF_BITPOS (14) +#define GIRQ15_MAILBOX_BITPOS (15) +#define GIRQ15_MAILBOX_DATA_BITPOS (16) +// +#define GIRQ15_MASK (0x01FFDDul) +#define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul) +// + +// GIRQ16 Bit Positions +#define GIRQ16_PECI_BITPOS (3) +// +#define GIRQ16_MASK (0x08ul) +#define GIRQ16_WAKE_CAPABLE_MASK (0x00ul) +// + +// GIRQ17 Bit Positions +#define GIRQ17_TACH0_BITPOS (0) +#define GIRQ17_TACH1_BITPOS (1) +#define GIRQ17_PS2_0_WAKE_BITPOS (2) +#define GIRQ17_PS2_1_WAKE_BITPOS (3) +#define GIRQ17_PS2_2_WAKE_BITPOS (4) +#define GIRQ17_PS2_3_WAKE_BITPOS (5) +#define GIRQ17_BC_WAKE_BITPOS (6) +// RESERVED b[9:7] +#define GIRQ17_ADC_INT0_BITPOS (10) +#define GIRQ17_ADC_INT1_BITPOS (11) +#define GIRQ17_V2P_INT0_BITPOS (12) +#define GIRQ17_V2P_INT1_BITPOS (13) +#define GIRQ17_PS2_0_BITPOS (14) +#define GIRQ17_PS2_1_BITPOS (15) +#define GIRQ17_PS2_2_BITPOS (16) +#define GIRQ17_PS2_3_BITPOS (17) +// RESERVED b[19:18] +#define GIRQ17_HIBTMR_BITPOS (20) +#define GIRQ17_KEY_INT_BITPOS (21) +#define GIRQ17_KEY_INT_WAKE_BITPOS (22) +#define GIRQ17_RPM_STALL_BITPOS (23) +#define GIRQ17_RPM_SPIN_BITPOS (24) +#define GIRQ17_VBAT_BITPOS (25) +#define GIRQ17_LED0_BITPOS (26) +#define GIRQ17_LED1_BITPOS (27) +#define GIRQ17_LED2_BITPOS (28) +#define GIRQ17_MBC_ERR_BITPOS (29) +#define GIRQ17_MBC_BUSY_BITPOS (30) +// +#define GIRQ17_MASK (0x7FF3FC7Ful) +#define GIRQ17_WAKE_CAPABLE_MASK (0x0230007Cul) +// + +// GIRQ18 Bit Positions +#define GIRQ18_SPI0_TX_BITPOS (0) +#define GIRQ18_SPI0_RX_BITPOS (1) +#define GIRQ18_SPI1_TX_BITPOS (2) +#define GIRQ18_SPI1_RX_BITPOS (3) +#define GIRQ18_LED3_BITPOS (4) // NVIC 85 +#define GIRQ18_PKE_ERR_BITPOS (5) // NVIC 86 +#define GIRQ18_PKE_END_BITPOS (6) // NVIC 87 +#define GIRQ18_TRNG_BITPOS (7) // NVIC 88 +#define GIRQ18_AES_BITPOS (8) // NVIC 89 +#define GIRQ18_HASH_BITPOS (9) // NVIC 90 +// +#define GIRQ18_MASK (0x0FFul) +#define GIRQ18_WAKE_CAPABLE_MASK (0x000ul) +// + +// GIRQ19 Bit Positions +#define GIRQ19_LRESET_BITPOS (0) +#define GIRQ19_VCC_PWRGD_BITPOS (1) +// +#define GIRQ19_MASK (0x03ul) +#define GIRQ19_WAKE_CAPABLE_MASK (0x03ul) +// + +// GIRQ20 Bit Positions +#define GIRQ20_GPIO_0200_BITPOS (0) +#define GIRQ20_GPIO_0201_BITPOS (1) +#define GIRQ20_GPIO_0202_BITPOS (2) +#define GIRQ20_GPIO_0203_BITPOS (3) +#define GIRQ20_GPIO_0204_BITPOS (4) +//#define GIRQ20_GPIO_0205_BITPOS (5) +#define GIRQ20_GPIO_0206_BITPOS (6) +//#define GIRQ20_GPIO_0207_BITPOS (7) +// +#define GIRQ20_GPIO_0210_BITPOS (8) +#define GIRQ20_GPIO_0211_BITPOS (9) +#define GIRQ20_GPIO_0212_BITPOS (10) +#define GIRQ20_GPIO_0213_BITPOS (11) +// +#define GIRQ20_MASK (0x0F5Ful) +#define GIRQ20_WAKE_CAPABLE_MASK (0x0F5Ful) +// + +// GIRQ21 Bit Positions +#define GIRQ21_MASK (0x00ul) +#define GIRQ21_WAKE_CAPABLE_MASK (0x00ul) + +// GIRQ22 Bit Positions +#define GIRQ22_MASK (0x00ul) +#define GIRQ22_WAKE_CAPABLE_MASK (0x00ul) + +// GIRQ23 Bit Positions +#define GIRQ23_TMR0_BITPOS (0) +#define GIRQ23_TMR1_BITPOS (1) +#define GIRQ23_TMR2_BITPOS (2) +#define GIRQ23_TMR3_BITPOS (3) +#define GIRQ23_TMR4_BITPOS (4) +#define GIRQ23_TMR5_BITPOS (5) +// +#define GIRQ23_MASK (0x03Ful) +#define GIRQ23_WAKE_CAPABLE_MASK (0x000ul) +// + +/* ------------------------------------------------------------------------------- */ +/* NVIC,ECIA Routing Policy for Direct Mode */ +/* ------------------------------------------------------------------------------- */ +/* In Direct Mode, some interrupts could be configured to be used as aggregated. + * Configuration: + * 1. Always set ECS Interrupt Direct enable bit. + * 2. If GIRQn aggregated set Block Enable bit. + * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs. + * Switching issues: + * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers. + * Also requires set/clear of individual NVIC Enables. + * + * Note: interrupt_is_girq_direct() internal function uses this policy to detect + * if any interrupt is configured as direct or aggregated +*/ + +/** Initialize EC Interrupt Aggregator + * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode + * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated + * This parameter is only applicable in direct mode. + * @note All GPIO's and wake capable sources are always + * aggregated! GPIO's interrupts will still work in direct mode. + * Block wakes are not be routed to the processor in direct + * mode. + * Note2: This function disables and enables global interrupt + */ +void interrupt_init(uint8_t mode, uint32_t girq_bitmask); + +/** Set interrupt routing mode to aggregated or direct. + * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated + * @note In direct mode, one could enable certain GIRQs as aggregated using + * p_interrupt_ecia_block_enable_set function + */ +void interrupt_mode_set(uint8_t mode); + +/** Clears all individual interrupts Enables and Source in ECIA, + * and Clears all NVIC external enables and pending bits + */ +void interrupt_reset(void); + +/** Enables interrupt for a device + * @param dev_iroute - source IROUTING information + * @note This function disables and enables global interrupt + */ +void interrupt_device_enable(uint32_t dev_iroute); + +/** Disables interrupt for a device + * @param dev_iroute - source IROUTING information + * @note This function disables and enables global interrupt + */ +void interrupt_device_disable(uint32_t dev_iroute); + +/* ------------------------------------------------------------------------------- */ +/* ECIA APIs using device IROUTE() as input */ +/* ------------------------------------------------------------------------------- */ + +/** Clear Source in the ECIA for the device + * @param devi - device IROUTING value + */ +void interrupt_device_ecia_source_clear(const uint32_t dev_iroute); + +/** Get the Source bit in the ECIA for the device + * @param devi - device IROUTING value + * @return 0 if source bit not set; else non-zero value + */ +uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute); + +/** Get the Result bit in the ECIA for the device + * @param devi - device IROUTING value + * @return 0 if result bit not set; else non-zero value + */ +uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute); + +/* ------------------------------------------------------------------------------- */ +/* NVIC APIs using device IROUTE() as input */ +/* ------------------------------------------------------------------------------- */ +/* Note that if the device interrupt is aggregated, then these APIs would affect the + * NVIC corresponding to the aggregated GIRQ + */ + +/** Enable/Disable the NVIC (in the NVIC controller) for the device + * @param dev_iroute : source IROUTING information (encoded in a uint32_t) + * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ + * @note Recommended to use interrupt_device_enable, interrupt_device_disable + * to enable/disable interrupts for the device, since those APIs configure ECIA as well + */ +void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag); + +/** Set NVIC priority for specified peripheral interrupt source + * @param dev_iroute - source IROUTING information (encoded in a uint32_t) + * @param nvic_pri - NVIC Priority + * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt + * sources in the GIRQ. + * 2. This function disables and enables global interrupt + */ +void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri); + +/** Return NVIC priority for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint32_t NVIC priority + */ +uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute); + +/** Return NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint8_t 0(not pending), 1 (pending in NVIC) + * + */ +uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute); + +/** Set NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + */ +void interrupt_device_nvic_pending_set(const uint32_t dev_iroute); + +/** Clears NVIC pending for interrupt source + * @param dev_iroute - source IROUTING information + * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear + * @note This function disables and enables global interrupt + */ +uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear * + * and Status Register */ +/* ------------------------------------------------------------------------------- */ + +/** Enable specified GIRQ in ECIA block + * @param girq_id - enum MEC_GIRQ_IDS + */ + void p_interrupt_ecia_block_enable_set(uint8_t girq_id); + + /** Enable GIRQs in ECIA Block + * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block + */ +void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask); + +/** Check if specified GIRQ block enabled or not + * @param girq_id - enum MEC_GIRQ_IDS + * @return retVal - 1 if the particular GIRQ block enabled, else 0 + */ +uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id); + +/** Set all GIRQ block enables */ +void p_interrupt_ecia_block_enable_all_set(void); + +/** Clear specified GIRQ in ECIA Block + * @param girq_id - enum MEC_GIRQ_IDS + */ +void p_interrupt_ecia_block_enable_clr(uint8_t girq_id); + +/** Clear GIRQs in ECIA Block + * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block + */ +void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask); + +/** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */ +void p_interrupt_ecia_block_enable_all_clr(void); + + /** Get status of GIRQ in ECIA Block + * @param girq_id - enum MEC_GIRQ_IDS + * @return 0 if status bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id); + +/** Reads the Block IRQ Vector Register + * @return 32-bit value + */ +uint32_t p_interrupt_ecia_block_irq_all_status_get(void); + +/* ---------------------------------------------------------------------------- */ +/* Peripheral Functions - Operations on GIRQx Source, Enable, Result * + * and Enable Registers */ +/* ---------------------------------------------------------------------------- */ + +/** Clear specified interrupt source bit in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + */ +void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum); + +/** Read the specified interrupt source bit in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + * @return 0 if source bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum); + +/** Enable the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + */ +void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum); + +/** Disable the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + */ +void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum); + +/** Read the status of the specified interrupt in GIRQx + * girq_id - enum MEC_GIRQ_IDS + * bitnum = [0, 31] + * @return 0 if enable bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum); + +/** Read the result bit of the interrupt in GIRQx + * @param girq_id - enum MEC_GIRQ_IDS + * @param bitnum -[0, 31] + * @return 0 if enable bit not set; else non-zero value + */ +uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Function - Operations on all GIRQs */ +/* ------------------------------------------------------------------------------- */ + +/** Clear all aggregator GIRQn status registers */ +void p_interrupt_ecia_girqs_source_reset(void); + +/** Clear all aggregator GIRQn enables */ + void p_interrupt_ecia_girqs_enable_reset(void); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Function - Function to set interrupt control */ +/* ------------------------------------------------------------------------------- */ + +/** Set interrupt control + * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled + */ + void p_interrupt_control_set(uint8_t nvic_en_flag); + + /** Read interrupt control + * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled + */ +uint8_t p_interrupt_control_get(void); + +/* ------------------------------------------------------------------------------- */ +/* Peripheral Functions - NVIC */ +/* ------------------------------------------------------------------------------- */ + +/** Enable/Disable the NVIC IRQ in the NVIC interrupt controller + * @param nvic_num : NVIC number (see enum IRQn_Type) + * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ + * @note Application should perform this operation + */ + void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag); + + /** ecia_nvic_clr_en - Clear all NVIC external enables */ +void p_interrupt_nvic_extEnables_clr(void); + +/** Clear all NVIC external enables and pending bits */ +void p_interrupt_nvic_enpend_clr(void); + +/** Set NVIC external priorities to POR value */ +void p_interrupt_nvic_priorities_default_set(void); + +/** Set NVIC external priorities to specified priority (0 - 7) + * @param zero-based 3-bit priority value: 0=highest, 7=lowest. + * @note NVIC highest priority is the value 0, lowest is all 1's. + * Each external interrupt has an 8-bit register and the priority + * is left justified in the registers. MECxxx implements 8 priority + * levels or bits [7:5] in the register. Lowest priority = 0xE0 + */ +void p_interrupt_nvic_priorities_set(uint8_t new_pri); + +#endif /*_INTERRUPT_H_*/ + +/** @} + */ + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h new file mode 100644 index 000000000..10710ead3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr.h @@ -0,0 +1,462 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/11/24 06:28:28 $ +$Author: amohandas $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file pcr.h +* \brief Power, Clocks, and Resets Header file +* \author jvasanth +* +* This file is the PCR header file +******************************************************************************/ + +/** @defgroup PCR + * @{ + */ + +#ifndef _PCR_H +#define _PCR_H + + +/******************************************************************************/ +/** PCR Register IDS + *******************************************************************************/ +enum _PCR_REGSET_ID_ +{ + PCR_REG_CHIP_SLEEP_ENABLE =0, + PCR_REG_CHIP_CLK_REQD_STS, + PCR_REG_EC_SLEEP_ENABLE, + PCR_REG_EC_CLK_REQD_STS, + PCR_REG_HOST_SLEEP_ENABLE, + PCR_REG_HOST_CLK_REQD_STS, + PCR_REG_SYSTEM_SLEEP_CTRL, + PCR_REG_PROCESSOR_CLK_CTRL = 8, + PCR_REG_EC_SLEEP_ENABLE_2, + PCR_REG_EC_CLK_REQD_STS_2, + PCR_REG_SLOW_CLK_CTRL, + PCR_REG_OSCILLATOR_ID, + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS, + PCR_REG_CHIP_RESET_ENABLE, + PCR_REG_HOST_RESET_ENABLE, + PCR_REG_EC_RESET_ENABLE, + PCR_REG_EC_RESET_ENABLE_2, + PCR_REG_PWR_RESET_CTRL +}; +/* ---------------------------------------------------------------------- */ + +// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable +//PCR register group 0 - CHIP +#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \ + (((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u)) + +//PCR register group 1 - EC +#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u)) + +//PCR register group 2 - HOST +#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u)) + +//PCR register group 3 - EC 2 +#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \ + (((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \ + (((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u)) + + +//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR1_EC_INT_BITPOS (0u) +#define PCR1_EC_PECI_BITPOS (1u) +#define PCR1_EC_TACH0_BITPOS (2u) +#define PCR1_EC_PWM0_BITPOS (4u) +#define PCR1_EC_PMC_BITPOS (5u) +#define PCR1_EC_DMA_BITPOS (6u) +#define PCR1_EC_TFDP_BITPOS (7u) +#define PCR1_EC_CPU_BITPOS (8u) +#define PCR1_EC_WDT_BITPOS (9u) +#define PCR1_EC_SMB0_BITPOS (10u) +#define PCR1_EC_TACH1_BITPOS (11u) +#define PCR1_EC_PWM1_BITPOS (20u) +#define PCR1_EC_PWM2_BITPOS (21u) +#define PCR1_EC_PWM3_BITPOS (22u) +#define PCR1_EC_REG_BITPOS (29u) +#define PCR1_EC_BTIMER0_BITPOS (30u) +#define PCR1_EC_BTIMER1_BITPOS (31u) + +//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR2_HOST_LPC_BITPOS (0u) +#define PCR2_HOST_UART0_BITPOS (1u) +#define PCR2_HOST_GLBL_CFG_BITPOS (12u) +#define PCR2_HOST_ACPI_EC0_BITPOS (13u) +#define PCR2_HOST_ACPI_EC1_BITPOS (14u) +#define PCR2_HOST_ACPI_PM1_BITPOS (15u) +#define PCR2_HOST_8042EM_BITPOS (16u) +#define PCR2_HOST_RTC_BITPOS (18u) + +//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions +#define PCR3_EC2_ADC_BITPOS (3u) +#define PCR3_EC2_PS2_0_BITPOS (5u) +#define PCR3_EC2_PS2_1_BITPOS (6u) +#define PCR3_EC2_PS2_2_BITPOS (7u) +#define PCR3_EC2_PS2_3_BITPOS (8u) +#define PCR3_EC2_SPI0_BITPOS (9u) +#define PCR3_EC2_HTIMER_BITPOS (10u) +#define PCR3_EC2_KEYSCAN_BITPOS (11u) +#define PCR3_EC2_RPM_PWM_BITPOS (12u) +#define PCR3_EC2_SMB1_BITPOS (13u) +#define PCR3_EC2_SMB2_BITPOS (14u) +#define PCR3_EC2_SMB3_BITPOS (15u) +#define PCR3_EC2_LED0_BITPOS (16u) +#define PCR3_EC2_LED1_BITPOS (17u) +#define PCR3_EC2_LED2_BITPOS (18u) +#define PCR3_EC2_BCM_BITPOS (19u) +#define PCR3_EC2_SPI1_BITPOS (20u) +#define PCR3_EC2_BTIMER2_BITPOS (21u) +#define PCR3_EC2_BTIMER3_BITPOS (22u) +#define PCR3_EC2_BTIMER4_BITPOS (23u) +#define PCR3_EC2_BTIMER5_BITPOS (24u) +#define PCR3_EC2_LED3_BITPOS (25u) + +/* + * n = b[7:0] = PCR Reg Bit Position + * m = b[31:8] = PCRx Regs IDs + */ +//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul)) + +//PCRx_REGS_BIT positions +#define PCRx_REGS_POS_SLEEP_ENABLE (8u) +#define PCRx_REGS_POS_CLK_REQD_STS (16u) +#define PCRx_REGS_POS_RESET_ENABLE (24u) + + +/******************************************************************************/ +/** PCR Block IDS. + * These IDs are used to directly refer to a block + *******************************************************************************/ +typedef enum { + PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)), + PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)), + PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)), + PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)), + PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)), + PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)), + PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)), + PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)), + PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)), + PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)), + PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)), + PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)), + PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)), + PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)), + PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)), + PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)), + PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)), + PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)), + PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)), + PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)), + PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)), + PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)), + PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)), + PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)), + PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)), + PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)), + PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)), + PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)), + PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)), + PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)), + PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)), + PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)), + PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)), + PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)), + PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)), + PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)), + PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)), + PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)), + PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)), + PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)), + PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)), + PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)), + PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)), + PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)), + PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)), + PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)), + PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)), +} PCR_BLK_ID; + + +/******************************************************************************/ +/** PCR Processor ClK Divide Values + *******************************************************************************/ +enum PROCESSOR_CLK_DIVIDE_VALUE +{ + PCR_CPU_CLK_DIVIDE_1 = 1, + PCR_CPU_CLK_DIVIDE_4 = 4, + PCR_CPU_CLK_DIVIDE_16 = 16, + PCR_CPU_CLK_DIVIDE_48 = 48 +}; + +/******************************************************************************/ +/** System Sleep Modes + *******************************************************************************/ +enum SYSTEM_SLEEP_MODES +{ + SYSTEM_HEAVY_SLEEP_1 = 0, + SYSTEM_HEAVY_SLEEP_3 = 1, + SYSTEM_HEAVY_SLEEP_2 = 2, + SYSTEM_DEEPEST_SLEEP = 5 +}; + +/* Bitmask for System Sleep Control Register */ +#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0) +#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1) +#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2) + +/* Bitmask for Chip Sub-system Power Reset Status Register */ +#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2) +#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3) +#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5) +#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6) +#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10) +#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11) + +/* Bitmask for Processor Clock Control Register */ +#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8) + +/* Bitmask for Power Reset Control Register */ +#define PCR_iRESET_OUT_BITMASK (1UL<<0) + +/* ---------------------------------------------------------------------- */ +/* API - Functions to program Sleep Enable, CLK Reqd Status, * + * Reset Enable for a block * + * ---------------------------------------------------------------------- */ + /** Sets or Clears block specific bit in PCR Sleep Enable Register + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register + */ +void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag); + +/** Get Clock Required Status for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @return uint8_t - 1 if Clock Required Status set, else 0 + */ +uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id); + +/** Sets or Clears Reset Enable register bit for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register + */ +void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag); + +/* ---------------------------------------------------------------------- */ +/* API - Functions for entering low power modes */ +/* ---------------------------------------------------------------------- */ +/** Instructs all blocks to sleep by setting the Sleep Enable bits */ +void pcr_all_blocks_sleep(void); + +/** Clears the Sleep Enable bits for all blocks */ +void pcr_all_blocks_wake(void); + +/** Programs required sleep mode in System Sleep Control Register + * @param sleep_mode - see enum SYSTEM_SLEEP_MODES + */ +void pcr_system_sleep(uint8_t sleep_mode); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to program and read 32-bit values * + * from PCR Registers * + * ---------------------------------------------------------------------- */ + /** Write 32-bit value in the PCR Register + * @param pcr_reg_id - pcr register id + * @param value - 32-bit value + */ +void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value); + +/** Reads 32-bit value from the PCR Register + * @param pcr_reg_id - pcr register id + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_read(uint8_t pcr_reg_id); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to set, clr and get bits in * + * PCR Registers * + * ---------------------------------------------------------------------- */ + /** Sets bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set + */ +void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask); + +/** Clears bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to clear + */ +void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask); + +/** Read bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to read + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask); + +/** Sets or Clears bits in a PCR Register - Helper Function + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set or clear + * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register + */ +void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag); + +//Functions to operate on System Sleep Control Register + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to operate on System Sleep Control * + * Register * + * ---------------------------------------------------------------------- */ +/** Sets/Clears the Ring oscillator power down bit + * in System Sleep Control Register + * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit + */ +void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag); + +/** Sets/Clears the Ring oscillator output gate bit + * in System Sleep Control Register + * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit + */ +void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag); + +/** Sets/Clears the Core regulator standby bit + * in System Sleep Control Register + * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit + */ +void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag); + +/** Writes required sleep mode in System Sleep Control Register + * @param sleep_value - System Sleep control value - [D2, D1, D0] + */ +void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value); + +/** Reads the System Sleep Control PCR Register + * @return value - byte 0 of the system sleep control PCR register + */ +uint8_t p_pcr_system_sleep_ctrl_read(void); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to program to CLK Divide Value * + * ---------------------------------------------------------------------- */ + /** Writes the clock divide value in the Processor Clock Control Register + * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE + */ +void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to program the Slow Clock Control * + * Register * + * ---------------------------------------------------------------------- */ + /** Write the slow clock divide value in the Slow Clock Control Register + * @param slow_clk_divide_value - slow clk divide value + */ +void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Function to read the Oscillator Lock Status */ +/* ---------------------------------------------------------------------- */ +/** Reads the Oscillator Lock status bit in the Oscillator ID Register + * @return 1 if Oscillator Lock Status bit is set, else 0 + */ +uint8_t p_pcr_oscillator_lock_sts_get(void); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions to read various power status in * + * Chip Sub-System register * + * ---------------------------------------------------------------------- */ + /** Reads the VCC Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if VCC Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void); + +/** Reads the SIO Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if SIO Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void); + +/** Reads the VBAT Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if VBAT Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void); + +/** Clears the VBAT Reset Status bit + * in the Chip Subsystem Power Reset Status Register + */ +void p_pcr_chip_subsystem_vbat_reset_sts_clr(void); + +/** Reads the VCC1 Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if VCC1 Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void); + +/** Clears the VCC1 Reset Status bit + * in the Chip Subsystem Power Reset Status Register + */ +void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void); + +/** Reads the 32K_ACTIVE status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if 32_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void); + +/** Reads the PCICLK_ACTIVE status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if CICLK_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void); + +/* ---------------------------------------------------------------------- */ +/* Peripheral Function - Functions for Power Reset Control Register */ +/* ---------------------------------------------------------------------- */ +/** Reads the iRESET_OUT bit in the Power Reset Control Register + * @return 1 if iRESET_OUT bit is set, else 0 + */ +uint8_t p_pcr_iReset_Out_get(void); + +/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register + * @param 1 Set iRESET_OUT bit; 0 - Clear the bit + */ +void p_pcr_iReset_Out(uint8_t set_clr_flag); + +#endif // #ifndef _PCR_H +/* end pcr.h */ +/** @} + */ + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c new file mode 100644 index 000000000..e7454d84e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_api.c @@ -0,0 +1,133 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/11/24 06:28:28 $ +$Author: amohandas $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file pcr_api.c +* \brief Power, Clocks, and Resets API Source file +* \author jvasanth +* +* This file implements the PCR APIs +******************************************************************************/ + +/** @defgroup PCR + * @{ + */ + +#include "common_lib.h" +#include "pcr.h" + + +/* ------------------------------------------------------------------------------- */ +/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */ +/* ------------------------------------------------------------------------------- */ + +/** Sets or Clears block specific bit in PCR Sleep Enable Register + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register + */ +void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag) +{ + uint32_t bit_mask; + uint8_t pcr_reg_id; + + bit_mask = 1UL<<(pcr_block_id & 0xFFu); + pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu); + + p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); +} + + +/** Get Clock Required Status for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @return uint8_t - 1 if Clock Required Status set, else 0 + */ +uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id) +{ + uint32_t bit_mask; + uint8_t pcr_reg_id, retVal; + + bit_mask = 1UL<<(pcr_block_id & 0xFFu); + pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu); + + retVal = 0; + if (p_pcr_reg_get(pcr_reg_id, bit_mask)) + { + retVal = 1; + } + + return retVal; +} + +/** Sets or Clears Reset Enable register bit for the block + * @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT + * @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register + */ +void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag) +{ + uint32_t bit_mask; + uint8_t pcr_reg_id; + + bit_mask = 1UL<<(pcr_block_id & 0xFFu); + pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu); + + p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag); +} + + +/* ------------------------------------------------------------------------------- */ +/* Functions for entering low power modes */ +/* ------------------------------------------------------------------------------- */ + +/** Instructs all blocks to sleep by setting the Sleep Enable bits */ +void pcr_all_blocks_sleep(void) +{ + p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF); +} + +/** Clears the Sleep Enable bits for all blocks */ + void pcr_all_blocks_wake(void) +{ + p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0); + p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0); + p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0); +} + +/** Programs required sleep mode in System Sleep Control Register + * @param sleep_mode - see enum SYSTEM_SLEEP_MODES + */ +void pcr_system_sleep(uint8_t sleep_mode) +{ + p_pcr_system_sleep_ctrl_write(sleep_mode); +} + + +/* end pcr_api.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c new file mode 100644 index 000000000..af43e5df4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/pcr/pcr_perphl.c @@ -0,0 +1,490 @@ +/***************************************************************************** +* © 2015 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +****************************************************************************** + +Version Control Information (Perforce) +****************************************************************************** +$Revision: #1 $ +$DateTime: 2015/11/24 06:28:28 $ +$Author: amohandas $ +Last Change: Updated for tabs +******************************************************************************/ +/** @file pcr_perphl.c +* \brief Power, Clocks, and Resets Peripheral Source file +* \author jvasanth +* +* This file implements the PCR Peripheral functions +******************************************************************************/ + +/** @defgroup PCR + * @{ + */ + +#include "common_lib.h" +#include "pcr.h" + +/* ---------------------------------------------------------------------- */ +/* Generic functions to program and read 32-bit values from PCR Registers */ +/* ---------------------------------------------------------------------- */ +/** Writes 32-bit value in the PCR Register + * @param pcr_reg_id - pcr register id + * @param value - 32-bit value + */ +void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + *pPCR_Reg = value; +} + +/** Reads 32-bit value from the PCR Register + * @param pcr_reg_id - pcr register id + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_read(uint8_t pcr_reg_id) +{ + __IO uint32_t *pPCR_Reg; + uint32_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + retVal = *pPCR_Reg; + + return retVal; +} + +/* ---------------------------------------------------------------------- */ +/* Functions to set, clr and get bits in PCR Registers */ +/* ---------------------------------------------------------------------- */ + +/** Sets bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set + */ +void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + *pPCR_Reg |= bit_mask; +} + +/** Clears bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to clear + */ +void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + *pPCR_Reg &= ~bit_mask; +} + +/** Read bits in a PCR Register + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to read + * @return value - 32-bit value + */ +uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask) +{ + __IO uint32_t *pPCR_Reg; + uint32_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE); + + pPCR_Reg += pcr_reg_id; + + retVal = (*pPCR_Reg) & bit_mask; + + return retVal; +} + +/** Sets or Clears bits in a PCR Register - Helper Function + * @param pcr_reg_id - pcr register id + * @param bit_mask - Bit mask of bits to set or clear + * @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register + */ +void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag) +{ + if (set_clr_flag) + { + p_pcr_reg_set(pcr_reg_id, bit_mask); + } + else + { + p_pcr_reg_clr(pcr_reg_id, bit_mask); + } +} + +/* ---------------------------------------------------------------------- */ +/* Functions to operate on System Sleep Control Register */ +/* ---------------------------------------------------------------------- */ + +/** + * Sets/Clears the Ring oscillator power down bit + * in System Sleep Control Register + * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit + */ +void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + if (set_clr_flag) + { + *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; + } + else + { + *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK; + } +} + +/** Sets/Clears the Ring oscillator output gate bit + * in System Sleep Control Register + * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit + */ +void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + if (set_clr_flag) + { + *pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; + } + else + { + *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK; + } +} + +/** Sets/Clears the Core regulator standby bit + * in System Sleep Control Register + * @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit + */ +void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + if (set_clr_flag) + { + *pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; + } + else + { + *pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK; + } +} + +/** Writes required sleep mode in System Sleep Control Register + * @param sleep_value - System Sleep control value - [D2, D1, D0] + */ +void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + *pPCR_Reg = (sleep_value & 0x7); +} + +/** Reads the System Sleep Control PCR Register + * @return value - byte 0 of the system sleep control PCR register + */ +uint8_t p_pcr_system_sleep_ctrl_read(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL; + + retVal = (uint8_t)((*pPCR_Reg) & 0xFF); + + return retVal; +} + + + +/* ---------------------------------------------------------------------- */ +/* Function to program to CLK Divide Value */ +/* ---------------------------------------------------------------------- */ + +/** Writes the clock divide value in the Processor Clock Control Register + * @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE + */ +void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL; + + *pPCR_Reg = (clk_divide_value & 0xFF); + +} + +/* ---------------------------------------------------------------------- */ +/* Function to program the slow clock divide value */ +/* ---------------------------------------------------------------------- */ + +/** Write the slow clock divide value in the Slow Clock Control Register + * @param slow_clk_divide_value - slow clk divide value + */ +void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL; + + *pPCR_Reg = (slow_clk_divide_value & 0x3FF); + +} + +/* ---------------------------------------------------------------------- */ +/* Function to read the Oscillator Lock Status */ +/* ---------------------------------------------------------------------- */ + +/** Reads the Oscillator Lock status bit in the Oscillator ID Register + * @return 1 if Oscillator Lock Status bit is set, else 0 + */ +uint8_t p_pcr_oscillator_lock_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID; + + retVal = 0; + if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK) + { + retVal = 1; + } + + return retVal; + +} + +/* ---------------------------------------------------------------------- */ +/* Functions to read various power status in Chip Sub-System register */ +/* ---------------------------------------------------------------------- */ + +/** Reads the VCC Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if VCC Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Reads the SIO Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if SIO Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Reads the VBAT Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if VBAT Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Clears the VBAT Reset Status bit + * in the Chip Subsystem Power Reset Status Register + */ +void p_pcr_chip_subsystem_vbat_reset_sts_clr(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + // Write to clear + *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK; + +} + +/** Reads the VCC1 Reset Status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if VCC1 Reset Status bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Clears the VCC1 Reset Status bit + * in the Chip Subsystem Power Reset Status Register + */ +void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + // Write to clear + *pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK; + +} + +/** Reads the 32K_ACTIVE status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if 32_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK) + { + retVal = 1; + } + + return retVal; +} + +/** Reads the PCICLK_ACTIVE status bit + * in the Chip Subsystem Power Reset Status Register + * @return 1 if CICLK_ACTIVE bit is set, else 0 + */ +uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS; + + retVal = 0; + if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK) + { + retVal = 1; + } + return retVal; +} + +/* ---------------------------------------------------------------------- */ +/* Functions for Power Reset Control Register */ +/* ---------------------------------------------------------------------- */ + +/** Reads the iRESET_OUT bit in the Power Reset Control Register + * @return 1 if iRESET_OUT bit is set, else 0 + */ +uint8_t p_pcr_iReset_Out_get(void) +{ + __IO uint32_t *pPCR_Reg; + uint8_t retVal; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; + + retVal = 0; + if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK) + { + retVal = 1; + } + + return retVal; + +} + +/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register + * @param 1 Set iRESET_OUT bit; 0 - Clear the bit + */ +void p_pcr_iReset_Out(uint8_t set_clr_flag) +{ + __IO uint32_t *pPCR_Reg; + + pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL; + + *pPCR_Reg = (set_clr_flag & 0x1); +} + + +/* end pcr_perphl.c */ +/** @} + */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h new file mode 100644 index 000000000..2db4163c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/peripheral_library/platform.h @@ -0,0 +1,390 @@ +/**************************************************************************** +* © 2013 Microchip Technology Inc. and its subsidiaries. +* You may use this software and any derivatives exclusively with +* Microchip products. +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". +* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP +* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. +* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, +* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND +* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS +* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. +* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL +* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF +* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE +* OF THESE TERMS. +*/ + +/** @defgroup pwm pwm_c_wrapper + * @{ + */ +/** @file pwm_c_wrapper.cpp + \brief the pwm component C wrapper + This program is designed to allow the other C programs to be able to use this component + + There are entry points for all C wrapper API implementation + +Platform: This is ARC-based component + +Toolset: Metaware IDE(8.5.1) +Reference: smsc_reusable_fw_requirement.doc */ + +/******************************************************************************* + * SMSC version control information (Perforce): + * + * FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $ + * REVISION: $Revision: #1 $ + * DATETIME: $DateTime: 2015/12/23 15:37:58 $ + * AUTHOR: $Author: akrishnan $ + * + * Revision history (latest first): + * #xx + *********************************************************************************** + */ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ +#include +/* Platform Configuration PreProcessor Conditions */ +#define TOOLKEIL 1 +#define TOOLPC 2 +#define TOOLMW 3 +#define TOOLMDK 4 + +#define PCLINT 9 //added to satisfy PC Lint's need for a value here + +#ifdef __CC_ARM // Keil ARM MDK +#define TOOLSET TOOLMDK +#endif + +#if 0 +#ifdef _WIN32 //always defined by visual c++ +#define TOOLSET TOOLPC +#endif + +#ifdef __WIN32__ //always defined by borland +#define TOOLSET TOOLPC +#endif +#endif + + +#ifdef _ARC +#define TOOLSET TOOLMW // ARC Metaware +#endif + +#ifndef TOOLSET +//#error "ERROR: cfg.h TOOLSET not defined!" +#endif + +#if TOOLSET == TOOLMDK +#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */ +#define _KEIL_ 0 /* Make 1 for Keil Compiler */ +#define _PC_ 0 +#define _ARC_CORE_ 0 +#endif + +#if TOOLSET == TOOLKEIL +#define _KEIL_ARM_ 0 +#define _KEIL_ 1 /* Make 1 for Keil Compiler */ +#define _PC_ 0 +#define _ARC_CORE_ 0 +#endif + +#if TOOLSET == TOOLPC +#define _KEIL_ARM_ 0 +#define _KEIL_ 0 +#define _PC_ 1 /* Make 1 for PC Environment */ +#define _ARC_CORE_ 0 +#endif + +#if TOOLSET == TOOLMW +#define _KEIL_ARM_ 0 +#define _KEIL_ 0 +#define _PC_ 0 +#define _ARC_CORE_ 1 +#endif + +/* Short form for Standard Data Types */ +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned long UINT32; + +typedef volatile unsigned char REG8; + +typedef unsigned char BYTE; +typedef unsigned short WORD; +typedef unsigned long DWORD; + +typedef unsigned char UCHAR; +typedef unsigned short USHORT; +typedef unsigned long ULONG; + +typedef unsigned char BOOL; +typedef unsigned int UINT; + +/* signed types */ +typedef signed char INT8; +typedef signed short INT16; +typedef signed long INT32; + +typedef void VOID; + +/* union types */ +typedef union _BITS_8 +{ + UINT8 byte; + struct + { + UINT8 bit0: 1; + UINT8 bit1: 1; + UINT8 bit2: 1; + UINT8 bit3: 1; + UINT8 bit4: 1; + UINT8 bit5: 1; + UINT8 bit6: 1; + UINT8 bit7: 1; + }bit; +}BITS_8; + + +/* MACROS FOR Platform Portability */ + +/* macro for defining MMCR register */ +/* add MMCRARRAY() & EXTERNMMCRARRAY() */ +#if _KEIL_ +#define MMCR(name,address) volatile unsigned char xdata name _at_ address +#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address +#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address +#define EXTERNMMCR(name) extern volatile unsigned char xdata name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name +#define SFR(name,address) sfr name = address +#define SFRBIT(name,address) sbit name = address +#define EXTERNSFR(name) +#define BITADDRESSTYPE(name) bit name +#define XDATA xdata +#define CODE code +#define DATA data +#define IDATA idata +#define INTERRUPT(x) interrupt x +#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;) +#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;) +#define NULLPTR (char *)(0) +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() +#define DISABLE_INTERRUPTS() sfrIE_EAbit=0 +#define ENABLE_INTERRUPTS() sfrIE_EAbit=1 +#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; } +#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; } +#define ATOMIC_CPU_SLEEP() +#define NUM_IRQ_VECTORS 12 // DW-8051 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start +#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start +#define FUNC_NEVER_RETURNS +#define BEGIN_SMALL_DATA_BLOCK(x) +#define END_SMALL_DATA_BLOCK() +UINT32 soft_norm(UINT32 val); +#define NORM(x) soft_norm(x) +// +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if _PC_ +#define MMCR(name,address) volatile unsigned char name +#define MMCRARRAY(name,length,address) volatile unsigned char name[length] +#define MMCRTYPE(name,dtype,address) volatile dtype name +#define EXTERNMMCR(name) extern volatile unsigned char name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name +#define SFR(name,address) volatile unsigned char name +#define SFRBIT(name,address) volatile unsigned char name +#define EXTERNSFR(name) extern volatile unsigned char name +#define BITADDRESSTYPE(name) volatile unsigned char name +#define XDATA +#define CODE +#define DATA +#define IDATA +#define INTERRUPT(x) +#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;) +#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;) +#define NULLPTR (char *)(0) +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() +#define DISABLE_INTERRUPTS() +#define ENABLE_INTERRUPTS() +#define SAVE_DIS_INTERRUPTS(x) +#define RESTORE_INTERRUPTS(x) +#define ATOMIC_CPU_SLEEP() +#define NUM_IRQ_VECTORS 24 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define FUNC_NEVER_RETURNS +#define BEGIN_SMALL_DATA_BLOCK(x) +#define END_SMALL_DATA_BLOCK() +UINT32 soft_norm(UINT32 val); +#define NORM(x) soft_norm(x) +// +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if _ARC_CORE_ +// ARC C has no equivalent operator to specify address of a variable +// ARC MMCR's are 32-bit registers +#define MMCR(name,address) volatile unsigned char name +#define MMCRARRAY(name,length,address) volatile unsigned char name[length] +#define MMCRTYPE(name,dtype,address) volatile dtype name +#define EXTERNMMCR(name) extern volatile unsigned char name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name +#define SFR(name,address) volatile unsigned char name +#define SFRBIT(name,address) volatile unsigned char name +#define EXTERNSFR(name) extern volatile unsigned char name +#define BITADDRESSTYPE(name) +#define XDATA +#define CODE +#define DATA +#define IDATA +#define INTERRUPT(x) +#define SET_GLOBAL_INTR_ENABLE() (_enable()) +#define CLR_GLOBAL_INTR_ENABLE() (_disable()) +#define NULLPTR (char *)(0) +#define NULLVOIDPTR (void *)(0) +#define NULLFPTR (void (*)(void))0 +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() _nop() +#define DISABLE_INTERRUPTS() _disable() +#define ENABLE_INTERRUPTS() _enable() +#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); } +#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); } +#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop(); +#define NUM_IRQ_VECTORS 24 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 0 +#define DCCM_CODE_ALIAS_ADDR 0x00060000 +#define PLAT_ROM_IRQ_VECTOR_BASE 0 +#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR) +/// y #define IRQ_VECTABLE_IN_RAM 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS) +#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x) +#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data() +#define NORM(x) _norm(x) + +#define INLINE_FUNCTION(x) #pragma On_inline(x) + +// +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if _KEIL_ARM_ +// For ARM MDK compiler +// ARM MMCR's are 32-bit registers +#define MMCR(name,address) volatile unsigned char name +#define MMCRARRAY(name,length,address) volatile unsigned char name[length] +#define MMCRTYPE(name,dtype,address) volatile dtype name +#define EXTERNMMCR(name) extern volatile unsigned char name +#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[] +#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name +#define SFR(name,address) volatile unsigned char name +#define SFRBIT(name,address) volatile unsigned char name +#define EXTERNSFR(name) extern volatile unsigned char name +#define BITADDRESSTYPE(name) +#define XDATA +#define CODE +#define DATA +#define IDATA +#define INTERRUPT(x) +#define SET_GLOBAL_INTR_ENABLE() (__enable_irq()) +#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq()) +#define NULLPTR (char *)(0) +#define NULLVOIDPTR (void *)(0) +#define NULLFPTR (void (*)(void))0 +#define PLATFORM_TRIM_OSC() // TODO +#define PNOP() __NOP() +#define DISABLE_INTERRUPTS() __disable_irq() +#define ENABLE_INTERRUPTS() __enable_irq() +#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop(); + +#if 0 /* need further efforts if needed */ +#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); } +#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); } +#define NUM_IRQ_VECTORS 24 +#define IRQ_VECTOR_SIZE 8 +#define USE_INLINE_PATCHER 0 +#define DCCM_CODE_ALIAS_ADDR 0x00060000 +#define PLAT_ROM_IRQ_VECTOR_BASE 0 +#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR) +/// y #define IRQ_VECTABLE_IN_RAM 1 +#define IRQ_VECTABLE_IN_RAM 0 +#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x) +#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data() +#define INLINE_FUNCTION(x) #pragma On_inline(x) +#define USE_FUNC_REPLACEMENT 0 +#endif + +#if 0 +#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS) +#define NORM(x) _norm(x) +#else +/* for ARM MDK */ +#define FUNC_NEVER_RETURNS +UINT32 soft_norm(UINT32 val); +#define NORM(x) soft_norm(x) +#endif +#endif + +/* General Constants */ +#define FALSE 0x00 +#define TRUE !FALSE + +#define BIT_n_MASK(n) (1U << (n)) +#define BIT_0_MASK (1<<0) +#define BIT_1_MASK (1<<1) +#define BIT_2_MASK (1<<2) +#define BIT_3_MASK (1<<3) +#define BIT_4_MASK (1<<4) +#define BIT_5_MASK (1<<5) +#define BIT_6_MASK (1<<6) +#define BIT_7_MASK (1<<7) +#define BIT_8_MASK ((UINT16)1<<8) +#define BIT_9_MASK ((UINT16)1<<9) +#define BIT_10_MASK ((UINT16)1<<10) +#define BIT_11_MASK ((UINT16)1<<11) +#define BIT_12_MASK ((UINT16)1<<12) +#define BIT_13_MASK ((UINT16)1<<13) +#define BIT_14_MASK ((UINT16)1<<14) +#define BIT_15_MASK ((UINT16)1<<15) +#define BIT_16_MASK ((UINT32)1<<16) +#define BIT_17_MASK ((UINT32)1<<17) +#define BIT_18_MASK ((UINT32)1<<18) +#define BIT_19_MASK ((UINT32)1<<19) +#define BIT_20_MASK ((UINT32)1<<20) +#define BIT_21_MASK ((UINT32)1<<21) +#define BIT_22_MASK ((UINT32)1<<22) +#define BIT_23_MASK ((UINT32)1<<23) +#define BIT_24_MASK ((UINT32)1<<24) +#define BIT_25_MASK ((UINT32)1<<25) +#define BIT_26_MASK ((UINT32)1<<26) +#define BIT_27_MASK ((UINT32)1<<27) +#define BIT_28_MASK ((UINT32)1<<28) +#define BIT_29_MASK ((UINT32)1<<29) +#define BIT_30_MASK ((UINT32)1<<30) +#define BIT_31_MASK ((UINT32)1<<31) + + +/* For CEC application */ +#define ON 1 +#define OFF 0 + +#endif /*_PLATFORM_H_*/ + +/** @} + */ +