From: Peng Fan Date: Sun, 11 Dec 2016 11:24:30 +0000 (+0800) Subject: imx-common: cache: configure L2 Cache for i.MX6SLL X-Git-Tag: v2017.01-rc2~6^2~38 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a472e9bd6a51d67de38ca8fe65e1df344d19849e;p=u-boot imx-common: cache: configure L2 Cache for i.MX6SLL If L2 cache configured as OCRAM, reset it. Switch to use runtime check. Signed-off-by: Peng Fan Cc: Stefano Babic --- diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c index b77548821d..1c4a9a28c8 100644 --- a/arch/arm/imx-common/cache.c +++ b/arch/arm/imx-common/cache.c @@ -8,6 +8,7 @@ #include #include #include +#include #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -39,6 +40,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; unsigned int val; @@ -55,15 +57,14 @@ void v7_outer_cache_enable(void) */ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); -#if defined CONFIG_MX6SL - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - val = readl(&iomux->gpr[11]); - if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { - /* L2 cache configured as OCRAM, reset it */ - val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; - writel(val, &iomux->gpr[11]); + if (is_mx6sl() || is_mx6sll()) { + val = readl(&iomux->gpr[11]); + if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, &iomux->gpr[11]); + } } -#endif writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl);