From: Akshay Saraswat Date: Thu, 21 Mar 2013 02:13:13 +0000 (+0000) Subject: Exynos5: clock: Fix a typo bug in exynos clock init X-Git-Tag: v2013.04-rc3~1^2~76^2~12 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a4d40b856fb2674de55677bf73ec7d1821efd997;p=u-boot Exynos5: clock: Fix a typo bug in exynos clock init We intended to clear the bits of CLK_SRC_TOP2 register, instead we were writing on the reserved bits of src_core1 register. Since the default value of clk_src_top2 register were itself zero, this typo was not creating any big issue. But it is better to fix this error for better readability of the code. Signed-off-by: Hatim Ali Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index baa3042bcf..5b9e82fdf7 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -434,10 +434,10 @@ void system_clock_init() val = readl(&clk->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do {