From: Simon Glass Date: Sun, 17 Jan 2016 23:11:53 +0000 (-0700) Subject: x86: ivybridge: Move code from pch.c to bd82x6x.c X-Git-Tag: v2016.03-rc1~85 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a5ea3a7d4a29f4251c032385f89ef7776f081be8;p=u-boot x86: ivybridge: Move code from pch.c to bd82x6x.c This code relates to the PCH, so we should move it into the same file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 259a5df45e..7007d5f71e 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -14,7 +14,6 @@ obj-y += me_status.o obj-y += model_206ax.o obj-y += microcode_intel.o obj-y += northbridge.o -obj-y += pch.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 5cb41521e1..70a0aea3e0 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,134 @@ #define BIOS_CTRL 0xdc +static int pch_revision_id = -1; +static int pch_type = -1; + +/** + * pch_silicon_revision() - Read silicon revision ID from the PCH + * + * @dev: PCH device + * @return silicon revision ID + */ +static int pch_silicon_revision(struct udevice *dev) +{ + u8 val; + + if (pch_revision_id < 0) { + dm_pci_read_config8(dev, PCI_REVISION_ID, &val); + pch_revision_id = val; + } + + return pch_revision_id; +} + +int pch_silicon_type(struct udevice *dev) +{ + u8 val; + + if (pch_type < 0) { + dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); + pch_type = val; + } + + return pch_type; +} + +/** + * pch_silicon_supported() - Check if a certain revision is supported + * + * @dev: PCH device + * @type: PCH type + * @rev: Minimum required resion + * @return 0 if not supported, 1 if supported + */ +static int pch_silicon_supported(struct udevice *dev, int type, int rev) +{ + int cur_type = pch_silicon_type(dev); + int cur_rev = pch_silicon_revision(dev); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned try = IOBP_RETRY; + u32 data; + + while (try--) { + data = readl(RCB_REG(IOBPS)); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printf("IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, + u32 orvalue) +{ + u32 data; + + /* Set the address */ + writel(address, RCB_REG(IOBPIRI)); + + /* READ OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_READ_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = readl(RCB_REG(IOBPD)); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { + printf("IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) + writel(IOBPS_RW_BX, RCB_REG(IOBPS)); + else + writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); + if (!iobp_poll()) + return; + + /* Write IOBP data */ + writel(data, RCB_REG(IOBPD)); + if (!iobp_poll()) + return; +} + static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c deleted file mode 100644 index c7ce408253..0000000000 --- a/arch/x86/cpu/ivybridge/pch.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * From Coreboot - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include -#include -#include - -static int pch_revision_id = -1; -static int pch_type = -1; - -int pch_silicon_revision(struct udevice *dev) -{ - u8 val; - - if (pch_revision_id < 0) { - dm_pci_read_config8(dev, PCI_REVISION_ID, &val); - pch_revision_id = val; - } - - return pch_revision_id; -} - -int pch_silicon_type(struct udevice *dev) -{ - u8 val; - - if (pch_type < 0) { - dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val); - pch_type = val; - } - - return pch_type; -} - -int pch_silicon_supported(struct udevice *dev, int type, int rev) -{ - int cur_type = pch_silicon_type(dev); - int cur_rev = pch_silicon_revision(dev); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned try = IOBP_RETRY; - u32 data; - - while (try--) { - data = readl(RCB_REG(IOBPS)); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printf("IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, - u32 orvalue) -{ - u32 data; - - /* Set the address */ - writel(address, RCB_REG(IOBPIRI)); - - /* READ OPCODE */ - if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) - writel(IOBPS_RW_BX, RCB_REG(IOBPS)); - else - writel(IOBPS_READ_AX, RCB_REG(IOBPS)); - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = readl(RCB_REG(IOBPD)); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { - printf("IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0)) - writel(IOBPS_RW_BX, RCB_REG(IOBPS)); - else - writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); - if (!iobp_poll()) - return; - - /* Write IOBP data */ - writel(data, RCB_REG(IOBPD)); - if (!iobp_poll()) - return; -} diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 0f1aa01fe7..af3e8e747c 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -465,14 +465,6 @@ #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -/** - * pch_silicon_revision() - Read silicon revision ID from the PCH - * - * @dev: PCH device - * @return silicon revision ID - */ -int pch_silicon_revision(struct udevice *dev); - /** * pch_silicon_revision() - Read silicon device ID from the PCH * @@ -481,16 +473,6 @@ int pch_silicon_revision(struct udevice *dev); */ int pch_silicon_type(struct udevice *dev); -/** - * pch_silicon_supported() - Check if a certain revision is supported - * - * @dev: PCH device - * @type: PCH type - * @rev: Minimum required resion - * @return 0 if not supported, 1 if supported - */ -int pch_silicon_supported(struct udevice *dev, int type, int rev); - /** * pch_pch_iobp_update() - Update a pch register *