From: Helmut Raiger <helmut.raiger@hale.at>
Date: Thu, 27 Oct 2011 01:31:14 +0000 (+0000)
Subject: mx31: add ESD control registers
X-Git-Tag: v2011.12-rc1~228^2~88
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a6d9de436c3930addf98a54f62d936426a9917a4;p=u-boot

mx31: add ESD control registers

This allows to initialize DDR memory in C code.
Currently all mx31 boards use assembler code (lowlevel_init.S)

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
---

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index f487975e37..afdaa1ce6c 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -522,6 +522,17 @@ struct mx31_weim {
 	struct mx31_weim_cscr cscr[6];
 };
 
+/* ESD control registers */
+struct esdc_regs {
+	u32 ctl0;
+	u32 cfg0;
+	u32 ctl1;
+	u32 cfg1;
+	u32 misc;
+	u32 dly[5];
+	u32 dlyl;
+};
+
 #endif
 
 #define __REG(x)     (*((volatile u32 *)(x)))
@@ -600,6 +611,8 @@ struct mx31_weim {
 #define ESDCTL_BL(x)			((x) << 7)
 #define ESDCTL_PRCT(x)			((x) << 0)
 
+#define ESDCTL_BASE_ADDR	0xB8001000
+
 /* 13 fields of the upper CS control register */
 #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
 		cnc, wsc, ew, wws, edc) \