From: Kever Yang Date: Thu, 3 Aug 2017 12:07:45 +0000 (+0800) Subject: rockchip: rk322x: update MACRO for mmc clksel reg X-Git-Tag: v2017.09-rc3~71^2~2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a80b3b0378fdd700649124cb2f9cfe8c58390b73;p=u-boot rockchip: rk322x: update MACRO for mmc clksel reg The description for eMMC/SDIO/SDMMC src is not correct, update the CRU_CLKSEL11_CON value definition according to TRM. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h index 2a2f804f67..a7999ca5af 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -162,20 +162,17 @@ enum { /* CRU_CLKSEL11_CON */ EMMC_PLL_SHIFT = 12, EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, - EMMC_SEL_APLL = 0, - EMMC_SEL_DPLL, + EMMC_SEL_CPLL = 0, EMMC_SEL_GPLL, EMMC_SEL_24M, SDIO_PLL_SHIFT = 10, SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, - SDIO_SEL_APLL = 0, - SDIO_SEL_DPLL, + SDIO_SEL_CPLL = 0, SDIO_SEL_GPLL, SDIO_SEL_24M, MMC0_PLL_SHIFT = 8, MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, - MMC0_SEL_APLL = 0, - MMC0_SEL_DPLL, + MMC0_SEL_CPLL = 0, MMC0_SEL_GPLL, MMC0_SEL_24M, MMC0_DIV_SHIFT = 0,