From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Wed, 4 Mar 2009 21:28:50 +0000 (+0000)
Subject: Nicolas Pitre <nico@cam.org> making reset+halt on the
X-Git-Tag: v0.2.0~1105
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a8bd749d4edfeee9832a75daa1ce3a519285d5b2;p=openocd

Nicolas Pitre <nico@cam.org> making reset+halt on the
SheevaPlug 100% reliable (needs patch in target.c to fix "halt 0").

git-svn-id: svn://svn.berlios.de/openocd/trunk@1397 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/src/target/board/sheevaplug.cfg b/src/target/board/sheevaplug.cfg
index e9c68328..8e5c2655 100644
--- a/src/target/board/sheevaplug.cfg
+++ b/src/target/board/sheevaplug.cfg
@@ -3,8 +3,6 @@
 source [find interface/sheevaplug.cfg]
 source [find target/feroceon.cfg]
 
-$_TARGETNAME configure -event reset-init { sheevaplug_init }
-
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
 	-work-area-size 65536 \
@@ -17,6 +15,13 @@ nand device orion 0 0xd8000000
 
 proc sheevaplug_init { } {
 
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	jtag_reset 0 1
+	halt 0
+	jtag_reset 0 0
+	wait_halt
+
 	arm926ejs cp15 0 0 1 0 0x00052078
 
 	mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
@@ -90,8 +95,8 @@ proc sheevaplug_init { } {
 
 proc sheevaplug_reflash_uboot { } {
 
-	# reflash the u-Boot binary
-	#reset init
+	# reflash the u-Boot binary and reboot into it
+	sheevaplug_init
 	nand probe 0
 	nand erase 0 0 4
 	nand write 0 uboot.bin 0
@@ -101,8 +106,8 @@ proc sheevaplug_reflash_uboot { } {
 
 proc sheevaplug_load_uboot { } {
 
-	# load u-Boot into RAM
-	#reset init
+	# load u-Boot into RAM and execute it
+	sheevaplug_init
 	load_image /tmp/uboot.elf
 	verify_image uboot.elf
 	resume 0x00600000