From: Simon Glass <sjg@chromium.org>
Date: Tue, 20 Jan 2015 05:16:13 +0000 (-0700)
Subject: x86: dts: Add SPI flash MRC details for chromebook_link
X-Git-Tag: v2015.04-rc1~37^2~4
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=a9aff2f46a7f7d29a662531dbc181773f16a606d;p=u-boot

x86: dts: Add SPI flash MRC details for chromebook_link

Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 9490b169fb..45ada610b3 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,10 @@
 	model = "Google Link";
 	compatible = "google,link", "intel,celeron-ivybridge";
 
+	aliases {
+		spi0 = "/spi";
+	};
+
 	config {
 	       silent_console = <0>;
 	};
@@ -150,11 +154,20 @@
 	spi {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "intel,ich9";
+		compatible = "intel,ich-spi";
 		spi-flash@0 {
+			#size-cells = <1>;
+			#address-cells = <1>;
 			reg = <0>;
 			compatible = "winbond,w25q64", "spi-flash";
 			memory-map = <0xff800000 0x00800000>;
+			rw-mrc-cache {
+				label = "rw-mrc-cache";
+				/* Alignment: 4k (for updating) */
+				reg = <0x003e0000 0x00010000>;
+				type = "wiped";
+				wipe-value = [ff];
+			};
 		};
 	};