From: Aaron Carroll <aaronc@cse.unsw.edu.au>
Date: Wed, 2 Feb 2011 07:16:26 +0000 (+1100)
Subject: omap4430: fix reset sequence
X-Git-Tag: v0.5.0-rc1~198
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=aaf145c42201496007e0fc9168d9738cb0237717;p=openocd

omap4430: fix reset sequence

* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
  takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.

Signed-off-by: Aaron Carroll <aaronc@cse.unsw.edu.au>
---

diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 360ac662..69678eec 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -92,15 +92,10 @@ jtag configure $_CHIPNAME.jrc -event setup "
 	jtag tapenable $_CHIPNAME.m31_dap
 "
 
-proc omap4_dbginit {target} {
-	# General Cortex A9 debug initialisation
-	cortex_a9 dbginit
-}
-
-$_TARGETNAME configure -event reset-assert-post "omap4_dbginit $_TARGETNAME"
-
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.
 set PRM_RSTCTRL 0x4A307B00
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 0x1"
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
+$_CHIPNAME.m30 configure -event reset-assert { }
+$_CHIPNAME.m31 configure -event reset-assert { }