From: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Date: Thu, 19 Jun 2008 00:27:23 +0000 (-0500)
Subject: ColdFire: Fix power up issue for MCF5235
X-Git-Tag: v1.3.4-rc1~40^2^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ab4860b255239dbaecccdd002c8d11f4ef54dd75;p=u-boot

ColdFire: Fix power up issue for MCF5235

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
---

diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index c2c8fe8590..bd8a4e5e68 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
 		sdram->dacr0 =
 		    SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
 		    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+		asm("nop");
 
 		/* Initialize DMR0 */
 		sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+		asm("nop");
 
 		/* Set IP (bit 3) in DACR */
 		sdram->dacr0 |= SDRAMC_DARCn_IP;
@@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
 
 		/* Finish the configuration by issuing the MRS. */
 		sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
 		*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;