From: Marek Vasut <marex@denx.de>
Date: Mon, 20 Jul 2015 03:48:37 +0000 (+0200)
Subject: arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
X-Git-Tag: v2015.10-rc2~350
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ab48b19a660a81c907116514957a6db1cbb8dafa;p=u-boot

arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR

This is needed to access broken (read: Micron) SPI flashes which
are larger than 16 MiB and don't correctly support 4-byte addressing.

Signed-off-by: Marek Vasut <marex@denx.de>
---

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 24f2ec01b1..9ee4a75eb1 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -207,6 +207,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 #define CONFIG_CQSPI_DECODER		0
 #define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
 #endif
 
 #ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */