From: Lei Wen <[leiwen@marvell.com]>
Date: Tue, 1 Nov 2011 10:55:56 +0000 (+0530)
Subject: armada100: define CONFIG_SYS_CACHELINE_SIZE
X-Git-Tag: v2011.12-rc1~228^2~65
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456;p=u-boot

armada100: define CONFIG_SYS_CACHELINE_SIZE

By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
---

diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index d2094e5303..637f3130ef 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -33,6 +33,8 @@
 
 #include <asm/arch/armada100.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */