From: David Brownell <dbrownell@users.sourceforge.net>
Date: Tue, 8 Dec 2009 10:00:35 +0000 (-0800)
Subject: ARM: cygwin complile fixes
X-Git-Tag: v0.4.0-rc1~72
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ac19fc0da7e9b5542d5bcb9d6a6370efdeb2f1ee;p=openocd

ARM: cygwin complile fixes

It's as if despite integers being 32-bits, GCC refuses to
convert a "uint32_t" to one of them.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 407d2904..5c8ad6a0 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -158,14 +158,16 @@ static int evaluate_srs(uint32_t opcode,
 				"\t0x%8.8" PRIx32
 				"\tSRS%s\tSP%s, #%d",
 				address, opcode,
-				mode, wback, opcode & 0x1f);
+				mode, wback,
+				(unsigned)(opcode & 0x1f));
 		break;
 	case 0x08100000:
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32
 				"\t0x%8.8" PRIx32
 				"\tRFE%s\tr%d%s",
 				address, opcode,
-				mode, (opcode >> 16) & 0xf, wback);
+				mode,
+				(unsigned)((opcode >> 16) & 0xf), wback);
 		break;
 	default:
 		return evaluate_unknown(opcode, address, instruction);
@@ -3467,14 +3469,14 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
 	case 6:
 		sprintf(cp, "SRS%s\tsp%s, #%d", mode,
 				t ? "!" : "",
-				opcode & 0x1f);
+				(unsigned) (opcode & 0x1f));
 		return ERROR_OK;
 	case 1:
 		mode = "DB";
 		/* FALL THROUGH */
 	case 7:
 		sprintf(cp, "RFE%s\tr%d%s", mode,
-				(opcode >> 16) & 0xf,
+				(unsigned) ((opcode >> 16) & 0xf),
 				t ? "!" : "");
 		return ERROR_OK;
 	case 2: