From: richardbarry Date: Sat, 27 Aug 2011 14:20:58 +0000 (+0000) Subject: git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1565 1d2547de-c912-0410... X-Git-Tag: V7.0.2~45 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ac3bf09f566654d15085a39a971100d0e2556e6d;p=freertos git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1565 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit index 16cece4a1..4fa2c85c3 100644 Binary files a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit and b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.bit differ diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml index e392ae202..3c2d81d0d 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system.xml @@ -1,5 +1,5 @@ - + @@ -59,13 +59,13 @@ Base Family - + Number of Slave Slots Number of Master Slots - + AXI ID Widgth @@ -92,10 +92,10 @@ Master AXI Base Address - + Master AXI High Address - + Slave AXI Base ID @@ -104,7 +104,7 @@ Slave AXI Is Interconnect - + Slave AXI ACLK Ratio @@ -119,10 +119,10 @@ Interconnect Crossbar ACLK Frequency Ratio - + Slave AXI Supports Write - + Slave AXI Supports Read @@ -134,10 +134,10 @@ Propagate USER Signals - + AWUSER Signal Width - + ARUSER Signal Width @@ -149,7 +149,7 @@ BUSER Signal Width - + AXI Connectivity @@ -158,16 +158,16 @@ Master AXI Supports Reordering - + Master generates narrow bursts Slave accepts narrow bursts - + Slave AXI Write Acceptance - + Slave AXI Read Acceptance @@ -182,7 +182,7 @@ Master AXI Secure - + Master AXI Write FIFO Depth @@ -191,7 +191,7 @@ Slave AXI Write FIFO Delay - + Slave AXI Read FIFO Depth @@ -218,19 +218,19 @@ Master AXI Read FIFO Delay - + Slave AXI AW Register - + Slave AXI AR Register - + Slave AXI W Register - + Slave AXI R Register - + Slave AXI B Register @@ -285,60 +285,62 @@ - + - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -348,22 +350,22 @@ - + - + - + - + @@ -373,10 +375,10 @@ - + - + @@ -478,7 +480,7 @@ Master AXI Base Address - + Master AXI High Address @@ -1043,14 +1045,14 @@ I-Cache High Address - + Enable Instruction Cache Enable I-Cache Writes - - + + Size of the I-Cache in Bytes @@ -1093,14 +1095,14 @@ D-Cache High Address - + Enable Data Cache Enable D-Cache Writes - - + + Size of D-Cache in Bytes @@ -1345,90 +1347,90 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1962,7 +1964,7 @@ - + @@ -2009,7 +2011,7 @@ - + @@ -2974,7 +2976,7 @@ - + @@ -3014,6 +3016,11 @@ + + + + + @@ -3026,6 +3033,7 @@ + @@ -3152,7 +3160,7 @@ LMB BRAM High Address - + LMB Address Decode Mask @@ -3452,7 +3460,7 @@ LMB BRAM High Address - + LMB Address Decode Mask @@ -4230,7 +4238,7 @@ Base Address - + High Address @@ -4602,7 +4610,7 @@ - + @@ -5036,7 +5044,7 @@ - + @@ -5100,7 +5108,7 @@ - + @@ -5184,7 +5192,7 @@ - + @@ -5226,7 +5234,7 @@ - + @@ -5242,11 +5250,11 @@ - + - + @@ -5257,7 +5265,7 @@ - + @@ -5503,6 +5511,8 @@ + + @@ -5750,7 +5760,7 @@ - + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm index 7a8633606..4ccd72ac6 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_bd.bmm @@ -21,10 +21,10 @@ ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 ADDRESS_SPACE microblaze_0_bram_block_combined RAMB16 [0x00000000:0x00001FFF] BUS_BLOCK - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X0Y24; - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X0Y26; - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X0Y22; - microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X0Y28; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_0 [31:24] INPUT = microblaze_0_bram_block_combined_0.mem PLACED = X3Y26; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_1 [23:16] INPUT = microblaze_0_bram_block_combined_1.mem PLACED = X3Y28; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_2 [15:8] INPUT = microblaze_0_bram_block_combined_2.mem PLACED = X2Y30; + microblaze_0_bram_block/microblaze_0_bram_block/ramb16bwer_3 [7:0] INPUT = microblaze_0_bram_block_combined_3.mem PLACED = X2Y28; END_BUS_BLOCK; END_ADDRESS_SPACE; diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html index fc27d4cf6..8d96d046d 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_main.html @@ -64,7 +64,7 @@ Specifics Generated -Sat Aug 27 12:49:18 2011 +Sat Aug 27 15:05:44 2011 EDK Version 13.1 @@ -544,6 +544,18 @@ microblaze_0_ilmb microblaze_0_i_bram_ctrl +M_AXI_DC +MASTER +AXI +axi4_0 +2 Peripherals. + +M_AXI_IC +MASTER +AXI +axi4_0 +2 Peripherals. + DEBUG TARGET XIL_MBDEBUG3 @@ -1011,8 +1023,8 @@ C_ICACHE_HIGHADDR 0xC7FFFFFF -C_USE_ICACHE -0 +C_USE_ICACHE +1 C_ALLOW_ICACHE_WR 1 @@ -1020,8 +1032,8 @@ C_ADDR_TAG_BITS 17 -C_CACHE_BYTE_SIZE -8192 +C_CACHE_BYTE_SIZE +16384 C_ICACHE_USE_FSL 1 @@ -1101,8 +1113,8 @@ C_DCACHE_HIGHADDR 0xC7FFFFFF -C_USE_DCACHE -0 +C_USE_DCACHE +1 C_ALLOW_DCACHE_WR 1 @@ -1110,8 +1122,8 @@ C_DCACHE_ADDR_TAG 17 -C_DCACHE_BYTE_SIZE -8192 +C_DCACHE_BYTE_SIZE +16384 C_DCACHE_USE_FSL 1 @@ -1404,7 +1416,7 @@ 0x74800000 C_HIGHADDR -0x748FFFFF +0x7480FFFF C_SPLB_AWIDTH 32 @@ -1763,6 +1775,14 @@ INTERFACE TYPE INTERFACE NAME +microblaze_0 +MASTER +M_AXI_DC + +microblaze_0 +MASTER +M_AXI_IC + ETHERNET_dma MASTER M_AXI_SG @@ -2961,7 +2981,7 @@ SLAVE AXI axi4_0 -ETHERNET_dma +2 Peripherals.

@@ -3009,7 +3029,7 @@ 0x80000000 C_S0_AXI_HIGHADDR -0x87FFFFFF +0x807FFFFF C_S1_AXI_BASEADDR 0xFFFFFFFF @@ -3458,7 +3478,7 @@ 0 C_INTERCONNECT_S0_AXI_MASTERS -ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM +microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM C_INTERCONNECT_S0_AXI_AW_REGISTER 1 @@ -4394,19 +4414,19 @@ MASTER AXI axi4_0 -MCB_DDR3 +2 Peripherals. M_AXI_MM2S MASTER AXI axi4_0 -MCB_DDR3 +2 Peripherals. M_AXI_S2MM MASTER AXI axi4_0 -MCB_DDR3 +2 Peripherals. S_AXI_LITE SLAVE diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html index 6cc23975e..a178f79c0 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/SDK/SDK_Export/hw/system_mainNF.html @@ -73,7 +73,7 @@ Specifics Generated -Sat Aug 27 12:49:18 2011 +Sat Aug 27 15:05:44 2011 EDK Version 13.1 @@ -553,6 +553,18 @@ microblaze_0_ilmb microblaze_0_i_bram_ctrl +M_AXI_DC +MASTER +AXI +axi4_0 +2 Peripherals. + +M_AXI_IC +MASTER +AXI +axi4_0 +2 Peripherals. + DEBUG TARGET XIL_MBDEBUG3 @@ -1020,8 +1032,8 @@ C_ICACHE_HIGHADDR 0xC7FFFFFF -C_USE_ICACHE -0 +C_USE_ICACHE +1 C_ALLOW_ICACHE_WR 1 @@ -1029,8 +1041,8 @@ C_ADDR_TAG_BITS 17 -C_CACHE_BYTE_SIZE -8192 +C_CACHE_BYTE_SIZE +16384 C_ICACHE_USE_FSL 1 @@ -1110,8 +1122,8 @@ C_DCACHE_HIGHADDR 0xC7FFFFFF -C_USE_DCACHE -0 +C_USE_DCACHE +1 C_ALLOW_DCACHE_WR 1 @@ -1119,8 +1131,8 @@ C_DCACHE_ADDR_TAG 17 -C_DCACHE_BYTE_SIZE -8192 +C_DCACHE_BYTE_SIZE +16384 C_DCACHE_USE_FSL 1 @@ -1413,7 +1425,7 @@ 0x74800000 C_HIGHADDR -0x748FFFFF +0x7480FFFF C_SPLB_AWIDTH 32 @@ -1772,6 +1784,14 @@ INTERFACE TYPE INTERFACE NAME +microblaze_0 +MASTER +M_AXI_DC + +microblaze_0 +MASTER +M_AXI_IC + ETHERNET_dma MASTER M_AXI_SG @@ -2970,7 +2990,7 @@ SLAVE AXI axi4_0 -ETHERNET_dma +2 Peripherals.

@@ -3018,7 +3038,7 @@ 0x80000000 C_S0_AXI_HIGHADDR -0x87FFFFFF +0x807FFFFF C_S1_AXI_BASEADDR 0xFFFFFFFF @@ -3467,7 +3487,7 @@ 0 C_INTERCONNECT_S0_AXI_MASTERS -ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM +microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM C_INTERCONNECT_S0_AXI_AW_REGISTER 1 @@ -4403,19 +4423,19 @@ MASTER AXI axi4_0 -MCB_DDR3 +2 Peripherals. M_AXI_MM2S MASTER AXI axi4_0 -MCB_DDR3 +2 Peripherals. M_AXI_S2MM MASTER AXI axi4_0 -MCB_DDR3 +2 Peripherals. S_AXI_LITE SLAVE diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml index 7e444c01f..5371f8626 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/param_input.xml @@ -93,7 +93,7 @@ C_INTERCONNECT_S0_AXI_MASTERS - "ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM" + "microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM" C_INTERCONNECT_S0_AXI_R_REGISTER @@ -569,11 +569,11 @@ C_S0_AXI_HIGHADDR - "0x87ffffff" + "0x807FFFFF" C_S0_AXI_ID_WIDTH - "2" + "3" C_S0_AXI_PROTOCOL diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log index 937512d97..5855e82bc 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/MCB_DDR3/tcl.log @@ -1,8 +1,8 @@ ========================================================================= -Time: Sat Aug 27 12:49:03 GMT Daylight Time 2011 -Running: run_batch_mode 96333944 +Time: Sat Aug 27 15:05:27 GMT Daylight Time 2011 +Running: run_batch_mode 96334104 {COLLECTING: INSTANCE MCB_DDR3 } -{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} +{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} {COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 } {COLLECTING: C_INTERCONNECT_S0_AXI_ACLK_RATIO 100000000 UPDATE integer 1 } {COLLECTING: C_INTERCONNECT_S0_AXI_SECURE 0 OPTIONAL integer 0 } @@ -98,7 +98,7 @@ Running: run_batch_mode 96333944 {COLLECTING: C_MCB_PERFORMANCE STANDARD OPTIONAL STRING STANDARD } {COLLECTING: C_BYPASS_CORE_UCF 0 OPTIONAL 0 } {COLLECTING: C_S0_AXI_BASEADDR 0x80000000 OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF 0x80000000} -{COLLECTING: C_S0_AXI_HIGHADDR 0x87ffffff OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x87ffffff} +{COLLECTING: C_S0_AXI_HIGHADDR 0x807FFFFF OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x807FFFFF} {COLLECTING: C_S1_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } {COLLECTING: C_S1_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 } {COLLECTING: C_S2_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF } @@ -162,7 +162,7 @@ Running: run_batch_mode 96333944 {COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 } {COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 } {COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 } -{COLLECTING: C_S0_AXI_ID_WIDTH 2 UPDATE INTEGER 4 } +{COLLECTING: C_S0_AXI_ID_WIDTH 3 UPDATE INTEGER 4 } {COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 } {COLLECTING: C_S0_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 } {COLLECTING: C_S0_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 } @@ -255,7 +255,7 @@ Running: run_batch_mode 96333944 {SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AW_REGISTER : 1 integer OPTIONAL} {SENDING PARAMETER: C_INTERCONNECT_S0_AXI_B_REGISTER : 1 integer OPTIONAL} {SENDING PARAMETER: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE} -{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL} +{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL} {SENDING PARAMETER: C_INTERCONNECT_S0_AXI_R_REGISTER : 1 integer OPTIONAL} {SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL} {SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL} @@ -374,8 +374,8 @@ Running: run_batch_mode 96333944 {SENDING PARAMETER: C_S0_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL} {SENDING PARAMETER: C_S0_AXI_ENABLE : 1 INTEGER OPTIONAL} {SENDING PARAMETER: C_S0_AXI_ENABLE_AP : 0 INTEGER OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x87ffffff STD_LOGIC_VECTOR OPTIONAL} -{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 2 INTEGER UPDATE} +{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x807FFFFF STD_LOGIC_VECTOR OPTIONAL} +{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 3 INTEGER UPDATE} {SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT} {SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE} {SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL} @@ -502,7 +502,7 @@ Running: run_batch_mode 96333944 {SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} -{SET: IGNORE C_S0_AXI_HIGHADDR = 0x87ffffff (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_S0_AXI_HIGHADDR = 0x807FFFFF (BATCH:OPTIONAL::MHS:COMPVAL)} {SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)} @@ -513,7 +513,7 @@ Running: run_batch_mode 96333944 {SET: IGNORE C_S3_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: UPDREM C_S0_AXI_SUPPORTS_WRITE = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)} {SET: IGNORE C_S0_AXI_ADDR_WIDTH = 32 (BATCH:CONSTANT::MPD:MPDVAL)} -{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)} +{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)} {SET: IGNORE C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)} {SET: UPDREM C_MEM_DDR3_CAS_WR_LATENCY = 5 (BATCH:UPDATE::MPD:MPDVAL)} diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport index 452c0cddf..222336916 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport @@ -1,9 +1,9 @@
- 2011-08-27T11:01:38 + 2011-08-27T15:17:50 system - 2011-08-27T11:01:38 + 2011-08-27T15:17:49 C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise/system.xreport filter.filter C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/ise diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml index e70dd10d5..86498813d 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/__xps/system.xml @@ -1,8 +1,48 @@ - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interconnect @@ -10,12 +50,13 @@ + - + - + @@ -24,40 +65,40 @@ - - + + - + - - + + - - + + - + - + - - + + - + - + @@ -66,11 +107,11 @@ - - - - - + + + + + @@ -91,54 +132,54 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -148,22 +189,22 @@ - + - + - + - + @@ -173,10 +214,10 @@ - + - + @@ -230,7 +271,6 @@ - AXI Interconnect @@ -238,6 +278,7 @@ + @@ -252,7 +293,7 @@ - + @@ -458,7 +499,6 @@ - MicroBlaze @@ -466,6 +506,7 @@ + @@ -610,10 +651,10 @@ - + - + @@ -640,10 +681,10 @@ - + - + @@ -860,90 +901,90 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1477,7 +1518,7 @@ - + @@ -1524,7 +1565,7 @@ - + @@ -2478,9 +2519,6 @@ - - - @@ -2492,7 +2530,7 @@ - + @@ -2532,6 +2570,11 @@ + + + + + @@ -2544,8 +2587,11 @@ + - + + + Local Memory Bus (LMB) 1.0 @@ -2553,6 +2599,7 @@ + @@ -2590,7 +2637,6 @@ - Local Memory Bus (LMB) 1.0 @@ -2598,6 +2644,7 @@ + @@ -2635,7 +2682,6 @@ - LMB BRAM Controller @@ -2643,6 +2689,7 @@ + @@ -2873,7 +2920,6 @@ - LMB BRAM Controller @@ -2881,6 +2927,7 @@ + @@ -3111,7 +3158,6 @@ - Block RAM (BRAM) Block @@ -3119,6 +3165,7 @@ + @@ -3166,7 +3213,6 @@ - Processor System Reset Module @@ -3174,6 +3220,7 @@ + @@ -3235,7 +3282,6 @@ - Clock Generator @@ -3243,6 +3289,7 @@ + @@ -3368,7 +3415,6 @@ - MicroBlaze Debug Module (MDM) @@ -3376,12 +3422,13 @@ + - + @@ -3727,14 +3774,13 @@ - + - AXI UART (Lite) @@ -3742,6 +3788,7 @@ + @@ -3821,9 +3868,6 @@ - - - @@ -3831,7 +3875,9 @@ - + + + AXI General Purpose IO @@ -3839,6 +3885,7 @@ + @@ -3942,7 +3989,6 @@ - AXI General Purpose IO @@ -3950,6 +3996,7 @@ + @@ -4046,9 +4093,6 @@ - - - @@ -4056,7 +4100,9 @@ - + + + AXI S6 Memory Controller(DDR/DDR2/DDR3) @@ -4064,6 +4110,7 @@ + @@ -4071,7 +4118,7 @@ - + @@ -4135,7 +4182,7 @@ - + @@ -4219,7 +4266,7 @@ - + @@ -4261,7 +4308,7 @@ - + @@ -4277,11 +4324,11 @@ - + - + @@ -4292,7 +4339,7 @@ - + @@ -4538,6 +4585,8 @@ + + @@ -4785,7 +4834,7 @@ - + @@ -4816,7 +4865,6 @@ - AXI Ethernet @@ -4824,6 +4872,7 @@ + @@ -5136,9 +5185,6 @@ - - - @@ -5146,7 +5192,9 @@ - + + + AXI DMA Engine @@ -5154,6 +5202,7 @@ + @@ -5489,10 +5538,6 @@ - - - - @@ -5500,7 +5545,10 @@ - + + + + AXI Interrupt Controller @@ -5508,6 +5556,7 @@ + @@ -5591,6 +5640,13 @@ + + + + + + + @@ -5600,14 +5656,6 @@ - - - - - - - - AXI Timer/Counter @@ -5615,6 +5663,7 @@ + @@ -5692,9 +5741,6 @@ - - - @@ -5702,49 +5748,10 @@ - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters index 42835f226..ec65f7de2 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.filters @@ -1,4 +1,3 @@ - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui index f9ab6d94b..b5e00b4d7 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/etc/system.gui @@ -6,7 +6,7 @@ - + @@ -14,6 +14,7 @@ + @@ -34,7 +35,7 @@ - + @@ -198,13 +199,10 @@ - - - + - diff --git a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs index 8baa228ea..864094491 100644 --- a/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs +++ b/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs @@ -75,11 +75,11 @@ BEGIN microblaze PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0xc0000000 PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff - PARAMETER C_USE_ICACHE = 0 + PARAMETER C_USE_ICACHE = 1 PARAMETER C_ICACHE_ALWAYS_USED = 1 PARAMETER C_DCACHE_BASEADDR = 0xc0000000 PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff - PARAMETER C_USE_DCACHE = 0 + PARAMETER C_USE_DCACHE = 1 PARAMETER C_DCACHE_ALWAYS_USED = 1 PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1 PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1 @@ -99,10 +99,14 @@ BEGIN microblaze PARAMETER C_NUMBER_OF_PC_BRK = 7 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2 + PARAMETER C_CACHE_BYTE_SIZE = 16384 + PARAMETER C_DCACHE_BYTE_SIZE = 16384 BUS_INTERFACE M_AXI_DP = axi4lite_0 BUS_INTERFACE DEBUG = microblaze_0_debug BUS_INTERFACE DLMB = microblaze_0_dlmb BUS_INTERFACE ILMB = microblaze_0_ilmb + BUS_INTERFACE M_AXI_DC = axi4_0 + BUS_INTERFACE M_AXI_IC = axi4_0 PORT MB_RESET = proc_sys_reset_0_MB_Reset PORT CLK = clk_100_0000MHzPLL0 PORT INTERRUPT = microblaze_0_interrupt @@ -201,7 +205,7 @@ BEGIN mdm PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 PARAMETER C_BASEADDR = 0x74800000 - PARAMETER C_HIGHADDR = 0x748FFFFF + PARAMETER C_HIGHADDR = 0x7480FFFF BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug PORT S_AXI_ACLK = clk_50_0000MHzPLL0 @@ -274,14 +278,14 @@ BEGIN axi_s6_ddrx PARAMETER C_MCB_RZQ_LOC = K7 PARAMETER C_MCB_ZIO_LOC = R7 PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E - PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM + PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1 PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1 PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1 PARAMETER C_S0_AXI_BASEADDR = 0x80000000 - PARAMETER C_S0_AXI_HIGHADDR = 0x87ffffff + PARAMETER C_S0_AXI_HIGHADDR = 0x807FFFFF PARAMETER C_S0_AXI_STRICT_COHERENCY = 0 BUS_INTERFACE S0_AXI = axi4_0 PORT mcbx_dram_clk = mcbx_dram_clk