From: Michel Jaouen <michel.jaouen@stericsson.com>
Date: Mon, 19 Sep 2011 14:49:23 +0000 (+0200)
Subject: u8500 : config for L2 cache
X-Git-Tag: v0.6.0-rc1~566
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ac49e24149680e9a5c59845648c0031926b7c919;p=openocd

u8500 : config for L2 cache
---

diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index f6e2091f..073e01fa 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -131,7 +131,9 @@ proc enable_apetap {} {
 	set status [$_TARGETNAME_1 curstate]
     if {[string equal "unknown" $status]} {
 	$_TARGETNAME_1 arp_examine
+	cache_config l2x 0xa0412000 8
 	}
+
 	set status [$_TARGETNAME_2 curstate]
     if {[string equal "unknown" $status]} {
 	$_TARGETNAME_2 arp_examine
@@ -234,6 +236,9 @@ if { $_SMP == 1} {
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 }
 
+
+
+
 proc secsts1 { } {
 	global _CHIPNAME
         irscan $_CHIPNAME.jrc 0x3a
@@ -265,6 +270,7 @@ proc att { } {
 	} else {
 		echo "target secured"
 	}
+	
 }