From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Sun, 16 Aug 2009 11:58:40 +0000 (+0000)
Subject: michal smulski <michal.smulski@ooma.com> arm11 target config files
X-Git-Tag: v0.3.0-rc0~368
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ad23cb97b2726bdf4e338c0c24d6e279d0b64747;p=openocd

michal smulski <michal.smulski@ooma.com> arm11 target config files

git-svn-id: svn://svn.berlios.de/openocd/trunk@2583 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
new file mode 100644
index 00000000..ceb8de38
--- /dev/null
+++ b/tcl/target/c100.cfg
@@ -0,0 +1,65 @@
+# c100 config
+#
+#jtag_nsrst_delay 5000
+#jtag_ntrst_delay 3000
+#reset_config none
+reset_config trst_and_srst separate
+#reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME c100
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x27b3645b
+}
+
+if { [info exists DSPTAPID ] } {
+   set _DSPTAPID $DSPTAPID
+} else {
+   set _DSPTAPID 0x27b3645b
+}
+
+jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID
+
+
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# C100's ARAM 64k SRAM
+$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
+
+
+proc power_restore {} { puts "Sensed power restore. No action." } 
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+
+# issue telnet: reset init
+# issue gdb: monitor reset init
+$_TARGETNAME configure -event reset-init {
+	# Force target into ARM state.
+#	soft_reset_halt # not implemented on ARM11
+	puts "Halting C100.CPU"
+	halt
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+	# Force target into ARM state.
+#	soft_reset_halt # not implemented on ARM11
+	puts "Detected SRSRT asserted on C100.CPU"
+	
+}
+# Valid events: old-gdb_program_config, old-pre_resume, early-halted, halted, resumed, resume-start, resume-end, gdb-start, gdb-end, reset-start, reset-assert-pre, reset-assert-post, reset-deassert-pre, reset-deassert-post, reset-halt-pre, reset-halt-post, reset-wait-pre, reset-wait-post, reset-init, reset-end, examine-start, examine-end, debug-halted, debug-resumed, gdb-attach, gdb-detach, gdb-flash-write-start, gdb-flash-write-end, gdb-flash-erase-start, gdb-flash-erase-end, resume-start, resume-ok, or resume-end
diff --git a/tcl/target/telo.cfg b/tcl/target/telo.cfg
new file mode 100644
index 00000000..cb28e632
--- /dev/null
+++ b/tcl/target/telo.cfg
@@ -0,0 +1,9 @@
+source [find c100.cfg]
+
+# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
+# it's really 16MB but the upper 8mb is controller via gpio?
+flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+
+# 
+gdb_memory_map enable
+