From: Uwe Bonnes Date: Thu, 5 May 2016 20:13:19 +0000 (+0200) Subject: Cortex-M7: Give user a hint about single stepping problem up to r0p1. X-Git-Tag: v0.10.0-rc1~198 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=ae5883fb1d91c7e0e75911212c60f90da9f3732f;p=openocd Cortex-M7: Give user a hint about single stepping problem up to r0p1. http://www.keil.com/support/docs/3778.htm Change-Id: I452f76726f3bb269fa14cc785f329bfba5189489 Signed-off-by: Uwe Bonnes Reviewed-on: http://openocd.zylin.com/3467 Reviewed-by: Andreas Fritiofson Tested-by: jenkins --- diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 831d01a7..32b46d34 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -1923,6 +1923,13 @@ int cortex_m_examine(struct target *target) LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected", i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); + if (i == 7) { + uint8_t rev, patch; + rev = (cpuid >> 20) & 0xf; + patch = (cpuid >> 0) & 0xf; + if ((rev == 0) && (patch < 2)) + LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!"); + } LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); /* test for floating point feature on cortex-m4 */