From: wdenk Date: Wed, 20 Apr 2005 09:28:54 +0000 (+0000) Subject: Auto-size RAM on canmb board. X-Git-Tag: LABEL_2006_03_12_0025~304 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b2323ea6f9ae478680baa964bdd97d8567507e91;p=u-boot Auto-size RAM on canmb board. Cleanup. --- diff --git a/CHANGELOG b/CHANGELOG index 28d35e28fd..ba5e3dd14e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -6,6 +6,8 @@ Changes for U-Boot 1.1.3: Make PCI target address spaces on PMC405 and CPCI405 boards configurable via environment variables +* Auto-size RAM on canmb board. + * Add support for canmb board * Patch by Stefan Roese, 13 Apr 2005: diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index 172fcd7bc7..3d3abf7207 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -2,8 +2,8 @@ * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. * * See file CREDITS for list of people who contributed to this * project. @@ -28,64 +28,209 @@ #include #include -/***************************************************************************** - * initialize SDRAM/DDRAM controller. - * TBD: get data from I2C EEPROM - *****************************************************************************/ -long int initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT -#if 0 - ulong t; - ulong tap_del; +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m32s2-75.h" #endif - #define MODE_EN 0x80000000 - #define SOFT_PRE 2 - #define SOFT_REF 4 - - /* configure SDRAM start/end */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE; - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x8000000; - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2; +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; -#ifdef CFG_DRAM_DDR - /* set extended mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); #endif - /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400; + /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE; + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL; - /* write default TAP delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24; + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } #endif /* CFG_RAMBOOT */ - dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20) + - ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20); + return dramsize + dramsize2; +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ - /* return total ram size */ return dramsize; } -/***************************************************************************** - * print board identification - *****************************************************************************/ +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + int checkboard (void) { puts ("Board: CANMB\n"); diff --git a/doc/README.ocotea-PIBS-to-U-Boot b/doc/README.ocotea-PIBS-to-U-Boot index 6b276c5f8c..0044aa0f91 100644 --- a/doc/README.ocotea-PIBS-to-U-Boot +++ b/doc/README.ocotea-PIBS-to-U-Boot @@ -77,14 +77,14 @@ U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) IBM PowerPC 440 GX Rev. C Board: IBM 440GX Evaluation Board - VCO: 1066 MHz - CPU: 533 MHz - PLB: 152 MHz - OPB: 76 MHz - EPB: 76 MHz + VCO: 1066 MHz + CPU: 533 MHz + PLB: 152 MHz + OPB: 76 MHz + EPB: 76 MHz I2C: ready DRAM: 256 MB -FLASH: 5 MB +FLASH: 5 MB PCI: Bus Dev VenId DevId Class Int In: serial Out: serial diff --git a/drivers/netconsole.c b/drivers/netconsole.c index 6c27c08f2a..9cf6cd6339 100644 --- a/drivers/netconsole.c +++ b/drivers/netconsole.c @@ -153,11 +153,12 @@ int nc_start (void) nc_port = 6666; /* default port */ if (getenv ("ncip")) { + char *p; + nc_ip = getenv_IPaddr ("ncip"); if (!nc_ip) return -1; /* ncip is 0.0.0.0 */ - char *p = strchr (getenv ("ncip"), ':'); - if (p) + if ((p = strchr (getenv ("ncip"), ':')) != NULL) nc_port = simple_strtoul (p + 1, NULL, 10); } else nc_ip = ~0; /* ncip is not set */ @@ -188,13 +189,13 @@ void nc_putc (char c) void nc_puts (const char *s) { + int len; + if (output_recursion) return; output_recursion = 1; - int len = strlen (s); - - if (len > 512) + if ((len = strlen (s)) > 512) len = 512; nc_send_packet (s, len); @@ -204,6 +205,8 @@ void nc_puts (const char *s) int nc_getc (void) { + uchar c; + input_recursion = 1; net_timeout = 0; /* no timeout */ @@ -212,8 +215,8 @@ int nc_getc (void) input_recursion = 0; - uchar c = input_buffer[input_offset]; - input_offset++; + c = input_buffer[input_offset++]; + if (input_offset >= sizeof input_buffer) input_offset -= sizeof input_buffer; input_size--; diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 0bbf41cbc2..a8bea02e56 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -128,18 +128,6 @@ #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO -/* - * DRAM configuration - */ -#define CFG_DRAM_DDR 0 -#define CFG_DRAM_EMODE 0 -#define CFG_DRAM_MODE 0x00CD -#define CFG_DRAM_CONTROL 0x514F0000 -#define CFG_DRAM_CONFIG1 0xD2333A00 -#define CFG_DRAM_CONFIG2 0x8AD70004 -#define CFG_DRAM_TAP_DEL 0x08 -#define CFG_DRAM_RAM_SIZE 0x19 - /* * Environment settings */