From: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun, 12 Mar 2006 23:46:05 +0000 (+0100)
Subject: Fix bug in [id]cache_status commands for MPC85xx processors;
X-Git-Tag: LABEL_2006_04_18_1106~7^2~11
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b38dbd4622a2abeedf9fcb1806958d9afac0bbd4;p=u-boot

Fix bug in [id]cache_status commands for MPC85xx processors;
should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005
---

diff --git a/CHANGELOG b/CHANGELOG
index 51efb237fb..ac984168d4 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,11 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+  should look at LSB of L1CSRn registers to determine if L1 cache is
+  enabled, not the MSB.
+  Patch by Murray Jensen, 19 Jul 2005
+
 * Fix array overflow with fw_setenv on uninitialised environment
   Patch by Murray Jensen, 15 Jul 2005
 
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7ac65736bc..f96a4c3f8b 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -715,7 +715,7 @@ icache_disable:
 	.globl	icache_status
 icache_status:
 	mfspr	r3,L1CSR1
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	andi.	r3,r3,1
 	blr
 
 	.globl	dcache_enable
@@ -748,7 +748,7 @@ dcache_disable:
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3,L1CSR0
-	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	andi.	r3,r3,1
 	blr
 
 	.globl get_pir