From: Oleksij Rempel <linux@rempel-privat.de>
Date: Fri, 15 May 2015 07:03:54 +0000 (+0200)
Subject: cortex_a: remove cache handlers from cortex_a_write_phys_memory
X-Git-Tag: v0.10.0-rc1~348
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b55361d07fc02f626103355115274117aa05d330;p=openocd

cortex_a: remove cache handlers from cortex_a_write_phys_memory

This was needed for ahb access

Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2796
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
---

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 33e09662..3da58701 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2698,60 +2698,6 @@ static int cortex_a_write_phys_memory(struct target *target,
 		return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
 	}
 
-	/* REVISIT this op is generic ARMv7-A/R stuff */
-	if (retval == ERROR_OK && target->state == TARGET_HALTED) {
-		struct arm_dpm *dpm = armv7a->arm.dpm;
-
-		retval = dpm->prepare(dpm);
-		if (retval != ERROR_OK)
-			return retval;
-
-		/* The Cache handling will NOT work with MMU active, the
-		 * wrong addresses will be invalidated!
-		 *
-		 * For both ICache and DCache, walk all cache lines in the
-		 * address range. Cortex-A has fixed 64 byte line length.
-		 *
-		 * REVISIT per ARMv7, these may trigger watchpoints ...
-		 */
-
-		/* invalidate I-Cache */
-		if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
-			/* ICIMVAU - Invalidate Cache single entry
-			 * with MVA to PoU
-			 *      MCR p15, 0, r0, c7, c5, 1
-			 */
-			for (uint32_t cacheline = 0;
-				cacheline < size * count;
-				cacheline += 64) {
-				retval = dpm->instr_write_data_r0(dpm,
-						ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
-						address + cacheline);
-				if (retval != ERROR_OK)
-					return retval;
-			}
-		}
-
-		/* invalidate D-Cache */
-		if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
-			/* DCIMVAC - Invalidate data Cache line
-			 * with MVA to PoC
-			 *      MCR p15, 0, r0, c7, c6, 1
-			 */
-			for (uint32_t cacheline = 0;
-				cacheline < size * count;
-				cacheline += 64) {
-				retval = dpm->instr_write_data_r0(dpm,
-						ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
-						address + cacheline);
-				if (retval != ERROR_OK)
-					return retval;
-			}
-		}
-
-		/* (void) */ dpm->finish(dpm);
-	}
-
 	return retval;
 }