From: rtel Date: Wed, 9 Jul 2014 21:19:01 +0000 (+0000) Subject: Start of SAMA5D3 XPlained demo. X-Git-Tag: V8.1.0~20 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b5e8783f09b8eb7c8b8f3c6c9517cb9c667286fa;p=freertos Start of SAMA5D3 XPlained demo. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2272 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/ddram.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/ddram.icf new file mode 100644 index 000000000..1fce1cc5f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/ddram.icf @@ -0,0 +1,53 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_DDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_DDRAM_end__ = 0x20FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF; +define symbol __ICFEDIT_region_DDRAM_BUF_start__ = 0x23000000; +define symbol __ICFEDIT_region_DDRAM_BUF_end__ = 0x23FFFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x200; +define symbol __ICFEDIT_size_vectors__ = 0x200; +define symbol __ICFEDIT_size_cstack__ = 0x4000; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_DDRAM_start__; +export symbol __ICFEDIT_region_DDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_DDRAM_start__ size __ICFEDIT_size_startup__]; +define region DDRAM_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_DDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; +define region DMA_BUF_region = mem:[from __ICFEDIT_region_DDRAM_BUF_start__ to __ICFEDIT_region_DDRAM_BUF_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in DDRAM_region { readonly }; +place in DDRAM_region { readwrite }; +place in DDRAM_region { zeroinit }; +place in DMA_BUF_region {section region_dma_nocache }; +place in DDRAM_region { block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/ddram_flashloader.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/ddram_flashloader.icf new file mode 100644 index 000000000..d13e38469 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/ddram_flashloader.icf @@ -0,0 +1,45 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0; +define symbol __ICFEDIT_region_RAM_start__ = 0x70000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x73FFFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x0; +define symbol __ICFEDIT_size_irqstack__ = 0x0; +define symbol __ICFEDIT_size_fiqstack__ = 0x0; +define symbol __ICFEDIT_size_undstack__ = 0x0; +define symbol __ICFEDIT_size_abtstack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +//initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec }; + +place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}}; +place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .noinit, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}}; + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/norflash.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/norflash.icf new file mode 100644 index 000000000..745193aae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/norflash.icf @@ -0,0 +1,48 @@ +/**** start of ICF editor section. ###ICF###*/ + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_SRAM0_start__ = 0x00300000; +define symbol __ICFEDIT_region_SRAM0_end__ = 0x0030FFFF; +define symbol __ICFEDIT_region_SRAM1_start__ = 0x00310000; +define symbol __ICFEDIT_region_SRAM1_end__ = 0x0031FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x40; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x40; +define symbol __ICFEDIT_size_undstack__ = 0x40; +define symbol __ICFEDIT_size_abtstack__ = 0x40; +define symbol __ICFEDIT_size_heap__ = 0x400; + +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region SRAM0 = mem:[from __ICFEDIT_region_SRAM0_start__ to __ICFEDIT_region_SRAM0_end__]; +define region SRAM1 = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors }; + +place in ROM { readonly }; +place in SRAM0 { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + +define exported symbol fl_ram_end = (__ICFEDIT_region_SRAM0_end__ & 0xFFFFFFF8); diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/sram.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/sram.icf new file mode 100644 index 000000000..bf2203026 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/Linker Scripts/sram.icf @@ -0,0 +1,38 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { readonly section .noinit }; + +place in VEC_region { section .vectors }; +place in RAM_region { readonly }; +place in RAM_region { section .cstartup }; +place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/board.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/board.h new file mode 100644 index 000000000..5d832b793 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/board.h @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \page sama5d3x_ek_board_desc sama5d3-xplained - Board Description + * + * \section Purpose + * + * This file is dedicated to describe the sama5d3-xplained board. + * + * \section Contents + * + * - sama5d3-xplained + * - For sama5d3-xplained information, see \subpage sama5d3x_ek_board_info. + * - For operating frequency information, see \subpage sama5d3x_ek_opfreq. + * - For using portable PIO definitions, see \subpage sama5d3x_ek_piodef. + * - For on-board memories, see \subpage sama5d3x_ek_mem. + * - Several USB definitions are included here, see \subpage sama5d3x_ek_usb. + * - For External components, see \subpage sama5d3x_ek_extcomp. + * - For Individual chip definition, see \subpage sama5d3x_ek_chipdef. + * + * To get more software details and the full list of parameters related to the + * sama5d3-xplained board configuration, please have a look at the source file: + * \ref board.h\n + * + * \section Usage + * + * - The code for booting the board is provided by board_cstartup_xxx.c and + * board_lowlevel.c. + * - For using board PIOs, board characteristics (clock, etc.) and external + * components, see board.h. + * - For manipulating memories, see board_memories.h. + * + * This file can be used as a template and modified to fit a custom board, with + * specific PIOs usage or memory connections. + */ + +/** + * \file board.h + * + * Definition of sama5d3-xplained + * characteristics, sama5d3x-dependant PIOs and external components interfacing. + */ + +#ifndef _BOARD_ +#define _BOARD_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/** + * Libc porting layers + */ +#if defined ( __CC_ARM ) /* Keil uvision 4 */ +# include "include/rand.h" +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# include "include/rand.h" +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68/2010q1-188 */ +# include "include/rand.h" +# include "include/syscalls.h" /** RedHat Newlib minimal stub */ +#endif + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_board_info "sama5d3-xplained - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/** Name of the board */ +#define BOARD_NAME "sama5d3-xplained" +/** Board definition */ +#define sama5d3xek +/** Family definition (already defined) */ +#if !defined sama5d3x +#define sama5d3x +#endif +/** Core definition */ +#define cortexa5 + +#define BOARD_XPLAINED +//#define BOARD_EK +//#define BOARD_VB + +// #define BOARD_REV_A_EK +// #define BOARD_REV_B_EK +// #define BOARD_REV_C_EK +// #define BOARD_REV_D_EK + +// Low cost board +// #define BOARD_LCB + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_opfreq "sama5d3-xplained - Operating frequencies" + * This page lists several definition related to the board operating frequency + * (when using the initialization done by board_lowlevel.c). + * + * \section Definitions + * - \ref BOARD_MAINOSC + * - \ref BOARD_MCK + */ + +/** Frequency of the board main oscillator */ +#define BOARD_MAINOSC 12000000 + +/** Master clock frequency (when using board_lowlevel.c) */ +#define BOARD_MCK ((unsigned long)((BOARD_MAINOSC / 3 / 2) * 66 )) + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_piodef "sama5d3-xplained - PIO definitions" + * This pages lists all the pio definitions contained in board.h. The constants + * are named using the following convention: PIN_* for a constant which defines + * a single Pin instance (but may include several PIOs sharing the same + * controller), and PINS_* for a list of Pin instances. + * + * DBGU + * - \ref PINS_DBGU + * + * USART0 + * - \ref PIN_USART0_TXD + * - \ref PIN_USART0_RXD + * - \ref PIN_USART0_RTS + * - \ref PIN_USART0_CTS + * - \ref PIN_USART0_SCK + * + * TWI0 + * - \ref PIN_TWI_TWD0 + * - \ref PIN_TWI_TWCK0 + * - \ref PINS_TWI0 + * + * SPI0 + * - \ref PIN_SPI0_MISO + * - \ref PIN_SPI0_MOSI + * - \ref PIN_SPI0_SPCK + * - \ref PIN_SPI0_NPCS0 + * - \ref PINS_SPI0 + * + * SSC + * - \ref PIN_SSC_TD + * - \ref PIN_SSC_TK + * - \ref PIN_SSC_TF + * - \ref PIN_SSC_RD + * - \ref PIN_SSC_RK + * - \ref PIN_SSC_RF + * - \ref PINS_SSC_CODEC + * + * EMAC0 + * - \ref PIN_EMAC0_TXCK + * - \ref PIN_EMAC0_TX0 + * - \ref PIN_EMAC0_TX1 + * - \ref PIN_EMAC0_TX2 + * - \ref PIN_EMAC0_TX3 + * - \ref PIN_EMAC0_TXEN + * - \ref PIN_EMAC0_RXER + * - \ref PIN_EMAC0_RXDV + * - \ref PIN_EMAC0_RX0 + * - \ref PIN_EMAC0_RX1 + * - \ref PIN_EMAC0_RX2 + * - \ref PIN_EMAC0_RX3 + * - \ref PIN_EMAC0_MDC + * - \ref PIN_EMAC0_MDIO + * - \ref PIN_EMAC0_INTR + * - \ref PINS_EMAC0_MII + * - \ref PINS_EMAC0_RMII + * LCD + * - \ref PINS_LCD + * + * ADC + * - \ref PIN_ADTRG + * + * ISI + * - \ref PIN_ISI_MCK + * - \ref PIN_ISI_VSYNC + * - \ref PIN_ISI_HSYNC + * - \ref PIN_ISI_PCK + * - \ref PIN_ISI_PINS_DATA + * - \ref PINS_ISI + */ + +/** List of all DBGU pin definitions. */ + +/** DBGU Monitor IO pin (detect any DBGU operation). */ +#define PIN_DBGU_MON {PIO_PB30A_DRXD, PIOB, ID_PIOB, PIO_INPUT, PIO_IT_RISE_EDGE} +/** DBGU pin definition. */ +#define PINS_DBGU {PIO_PB30A_DRXD | PIO_PB31A_DTXD, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + +/** List of all USART pin definitions. */ + +/** USART0 TXD pin definition. */ +#define PIN_USART0_TXD {PIO_PD18A_TXD0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** USART0 RXD pin definition. */ +#define PIN_USART0_RXD {PIO_PD17A_RXD0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** USART0 RTS pin definition. */ +#define PIN_USART0_RTS {PIO_PD16A_RTS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** USART0 CTS pin definition. */ +#define PIN_USART0_CTS {PIO_PD15A_CTS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** USART0 SCK pin definition. */ +#define PIN_USART0_SCK {PIO_PD14A_SCK0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} + +/** USART1 TXD pin definition. */ +#define PIN_USART1_TXD {PIO_PB29A_TXD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 RXD pin definition. */ +#define PIN_USART1_RXD {PIO_PB28A_RXD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 RTS pin definition. */ +#define PIN_USART1_RTS {PIO_PB27A_RTS1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 CTS pin definition. */ +#define PIN_USART1_CTS {PIO_PB26A_CTS1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 SCK pin definition. */ +#define PIN_USART1_SCK {PIO_PB25A_SCK1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + +/** USART2 TXD pin definition. */ +#define PIN_USART2_TXD {PIO_PE26B_TXD2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 RXD pin definition. */ +#define PIN_USART2_RXD {PIO_PE25B_RXD2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 RTS pin definition. */ +#define PIN_USART2_RTS {PIO_PE24B_RTS2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 CTS pin definition. */ +#define PIN_USART2_CTS {PIO_PE23B_CTS2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 SCK pin definition. */ +#define PIN_USART2_SCK {PIO_PE20B_SCK2, PIOE, ID_PIOE, PIO_PERIPH_B, PIO_DEFAULT} + +/** PIN used for reset the smartcard */ +#define PIN_ISO7816_RSTMC {1 << 2, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/** Pins used for connect the smartcard */ +#define PINS_ISO7816 PIN_USART1_TXD, PIN_USART1_SCK, PIN_ISO7816_RSTMC + +/** List of all TWI pin definitions. */ + +/** TWI0 data pin */ +#define PIN_TWI_TWD0 {PIO_PA30A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI0 clock pin */ +#define PIN_TWI_TWCK0 {PIO_PA31A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI0 pins */ +#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 + +/** TWI1 data pin */ +#define PIN_TWI_TWD1 {PIO_PC26B_TWD1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/** TWI1 clock pin */ +#define PIN_TWI_TWCK1 {PIO_PC27B_TWCK1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/** TWI1 pins */ +#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 + + +/** List of all CAN pin deinitions. */ +/** CAN0 pin TX */ +#define PIN_CAN0_TX {PIO_PD15C_CANTX0, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +/** CAN0 pin RX */ +#define PIN_CAN0_RX {PIO_PD14C_CANRX0, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +/** CAN0 pins */ +#define PINS_CAN0 PIN_CAN0_TX, PIN_CAN0_RX +/** CAN1 pin TX */ +#define PIN_CAN1_TX {PIO_PB15B_CANTX1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT} +/** CAN1 pin RX */ +#define PIN_CAN1_RX {PIO_PB14B_CANRX1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT} +/** CAN0 pins */ +#define PINS_CAN1 PIN_CAN1_TX, PIN_CAN1_RX + + +/** List of all SPI pin definitions. */ + +/** SPI0 MISO pin definition. */ +#define PIN_SPI0_MISO {PIO_PD10A_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI0 MOSI pin definition. */ +#define PIN_SPI0_MOSI {PIO_PD11A_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI0 SPCK pin definition. */ +#define PIN_SPI0_SPCK {PIO_PD12A_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI0 chip select pin definition. */ +#define PIN_SPI0_NPCS0 {PIO_PD13A_SPI0_NPCS0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** List of SPI0 pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK + +/** SPI1 MISO pin definition. */ +#define PIN_SPI1_MISO {PIO_PC22A_SPI1_MISO, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI1 MOSI pin definition. */ +#define PIN_SPI1_MOSI {PIO_PC23A_SPI1_MOSI, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI1 SPCK pin definition. */ +#define PIN_SPI1_SPCK {PIO_PC24A_SPI1_SPCK, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI1 chip select pin definition. */ +#define PIN_SPI1_NPCS0 {PIO_PC25A_SPI1_NPCS0, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** List of SPI1 pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI1 PIN_SPI1_MISO, PIN_SPI1_MOSI, PIN_SPI1_SPCK + + +/** List of all SSC pin definitions. */ + +/** SSC pin Transmitter Data (TD) */ +#define PIN_SSC_TD {0x1 << 18, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin Transmitter Clock (TK) */ +#define PIN_SSC_TK {0x1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin Transmitter FrameSync (TF) */ +#define PIN_SSC_TF {0x1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin RD */ +#define PIN_SSC_RD {0x1 << 21, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin RK */ +#define PIN_SSC_RK {0x1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin RF */ +#define PIN_SSC_RF {0x1 << 20, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pins definition for codec. */ + +#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF, PIN_SSC_RD, PIN_SSC_RK, PIN_SSC_RF +#define PINS_SSC_HDMI PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF + +/** LCD pin list. */ +#define PINS_LCD_PIOA {0x3F00FFFF, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_LCD_PIOC {0x0000FC00, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +#define PINS_LCD_PIOE {0x18000000, PIOE, ID_PIOE, PIO_PERIPH_C, PIO_DEFAULT} + +#define PINS_LCD PINS_LCD_PIOA, PINS_LCD_PIOC ,PINS_LCD_PIOE +//#define PINS_LCD PINS_LCD_PIOA +/** ADC ADTRG pin (PD19). */ +#define PIN_ADTRG {PIO_PD19A_ADTRG, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP} + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_usb "sama5d3-xplained - USB device" + * + * \section Definitions + * - \ref BOARD_USB_BMATTRIBUTES + * - \ref CHIP_USB_UDP + * - \ref CHIP_USB_PULLUP_INTERNAL + * - \ref CHIP_USB_NUMENDPOINTS + * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE + * - \ref CHIP_USB_ENDPOINTS_BANKS + */ + +/** USB VBus pin */ +#define PIN_USB_VBUS {PIO_PE9, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP} +/** USB OverCurrent detection*/ +#define PIN_USB_OVCUR {PIO_PE5, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP} + +/** USB attributes configuration descriptor (bus or self powered, remote wakeup) */ +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_mem "sama5d3-xplained - Memories" + * This page lists definitions related to internal & external on-board memories. + * + * \section Sdram + * + * - \ref EBI_SDRAM_PINS + * + * \section Nandflash + * - \ref PINS_NANDFLASH + * - \ref BOARD_NF_IO_PINS + * - \ref BOARD_NF_CE_PIN + * - \ref BOARD_NF_RB_PIN + */ + +/** Nandflash IO pin definition.*/ +#define BOARD_NF_IO_PINS {0, 0, 0, 0, 0} +#define BOARD_NF_CE_PIN {0, 0, 0, 0, 0} +/** Nandflash controller peripheral pins definition. */ +#define PINS_NANDFLASH BOARD_NF_IO_PINS + +/** Address for transferring command bytes to the nandflash, CLE A22*/ +#define BOARD_NF_COMMAND_ADDR 0x60400000 +/** Address for transferring address bytes to the nandflash, ALE A21*/ +#define BOARD_NF_ADDRESS_ADDR 0x60200000 +/** Address for transferring data bytes to the nandflash.*/ +#define BOARD_NF_DATA_ADDR 0x60000000 + +/** Address for transferring command bytes to the norflash. */ +#define BOARD_NORFLASH_ADDR 0x10000000 +/** Default NOR bus size after power up reset */ +#define BOARD_NORFLASH_DFT_BUS_SIZE 16 + +/** Ddram type */ +#define DDRAM_MT47H64M16HR 0 +#define DDRAM_MT47H128M16RT 1 +#define BOARD_DDRAM_TYPE DDRAM_MT47H128M16RT + +/** PHY address */ +#define BOARD_EMAC_PHY_ADDR 1 +/** PHY Component */ +#define BOARD_EMAC_PHY_COMP_KSZ8051RNL 1 +/** Board EMAC power control - ALWAYS ON */ +#define BOARD_EMAC_POWER_ALWAYS_ON +/** Board EMAC work mode - RMII/MII ( 1 / 0 ) */ +#define BOARD_EMAC_MODE_RMII 1 + +/** The PIN list of PIO for EMAC */ +#define BOARD_EMAC_PINS {0x3FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT},\ + {(1<<12),PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP} + +/** The runtime pin configure list for EMAC */ +#define BOARD_EMAC_RUN_PINS BOARD_EMAC_PINS + +/** PHY address */ +#define BOARD_GMAC_PHY_ADDR 7 +#define BOARD_GMAC_PHY_COMP_KSZ9021RNL 1 +#define BOARD_GMAC_POWER_ALWAYS_ON +#define BOARD_GMAC_MODE_RGMII 1 + +/** The PIN list of PIO for GMAC 0x7FFFF 0x73BFF */ +#define BOARD_GMAC_PINS {0x73BFF, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT},\ + {(1<<25),PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP} + +#define BOARD_GMAC_MODE_PINS {0xF0, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} + +/** The runtime pin configure list for EMAC */ +#define BOARD_GMAC_RUN_PINS BOARD_GMAC_PINS + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_extcomp "sama5d3-xplained - External components" + * This page lists the definitions related to external on-board components + * located in the board.h file for the sama5d3-xplained. + * + * \section board_sdmmc SD/MMC + * - \ref BOARD_MCI0_PINS + * - \ref BOARD_MCI0_PIN_CD + * - \ref BOARD_MCI1_PINS + * - \ref BOARD_MCI1_PIN_CD + * - \ref BOARD_NUM_MCI + * + * \section board_emac EMAC + * - \ref BOARD_EMAC_RST_PINS + * - \ref BOARD_EMAC_PHY_ADDR + * - \ref BOARD_EMAC_RUN_PINS + * + * \section board_lcd LCD Properties + * - \ref BOARD_LCD_WIDTH + * - \ref BOARD_LCD_HEIGHT + * - \ref BOARD_LCD_IFWIDTH + * - \ref BOARD_LCD_FRAMESIZE + * - \ref BOARD_LCD_TIMING_VFP + * - \ref BOARD_LCD_TIMING_VBP + * - \ref BOARD_LCD_TIMING_VPW + * - \ref BOARD_LCD_TIMING_HFP + * - \ref BOARD_LCD_TIMING_HBP + * - \ref BOARD_LCD_TIMING_HPW + * - \ref BOARD_LCD_FRAMERATE + * - \ref BOARD_LCD_PIXELCLOCK + * + * \section board_ts Touchscreen ADC Properties + * - \ref BOARD_TOUCHSCREEN_ADCCLK + * - \ref BOARD_TOUCHSCREEN_STARTUP + * - \ref BOARD_TOUCHSCREEN_SHTIM + * - \ref BOARD_TOUCHSCREEN_DEBOUNCE + */ + + +/** MCI0 Card detect pin definition. (PE0) */ +#define BOARD_MCI0_PIN_CD {PIO_PE0, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP} +/** MCI0 has no WriteProtect pin */ +/** MCI1 Card detect pin definition. (PE1) */ +#define BOARD_MCI1_PIN_CD {PIO_PE1, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP} +/** MCI1 Write Protect pin Always to GND */ + +/** MCI0 power control. */ +#define BOARD_MCI0_PIN_POWER {PIO_PE2, PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_PULLUP} + +/** Total number of MCI interface */ +#define BOARD_NUM_MCI 2 +/** MCI0 IO pins definition. (PD0-PD9) */ +#define BOARD_MCI0_PINS {0x3FF, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** MCI1 IO pins definition. (PA2-PA4, PA11-PA13) */ +#define BOARD_MCI1_PINS {0x1F80000, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + + +/** Display width in pixels. */ +#define BOARD_LCD_WIDTH 800 +/** Display height in pixels. */ +#define BOARD_LCD_HEIGHT 480 + +/** Display interface width in bits. */ +#define BOARD_LCD_IFWIDTH 24 +/** Frame size in words (height * width * bpp / 32) */ +#define BOARD_LCD_FRAMESIZE (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT * BOARD_LCD_IFWIDTH / 32) + +/** Vertical front porch in number of lines. */ +#define BOARD_LCD_TIMING_VFP 22 +/** Vertical back porch in number of lines. */ +#define BOARD_LCD_TIMING_VBP 21 +/** Vertical pulse width in number of lines. */ +#define BOARD_LCD_TIMING_VPW 2 +/** Horizontal front porch in LCDDOTCLK cycles. */ +#define BOARD_LCD_TIMING_HFP 64 +/** Horizontal back porch in LCDDOTCLK cycles. */ +#define BOARD_LCD_TIMING_HBP 64 +/** Horizontal pulse width in LCDDOTCLK cycles. */ +#define BOARD_LCD_TIMING_HPW 128 + +/** Frame rate in Hz. */ +#define BOARD_LCD_FRAMERATE 40 + +/** Pixel clock rate in Hz (HS period * VS period * BOARD_LCD_FRAMERATE). */ +#define BOARD_LCD_PIXELCLOCK ((BOARD_LCD_TIMING_HPW+BOARD_LCD_TIMING_HBP+BOARD_LCD_WIDTH+BOARD_LCD_TIMING_HFP)\ + *(BOARD_LCD_TIMING_VPW+BOARD_LCD_TIMING_VBP+BOARD_LCD_HEIGHT+BOARD_LCD_TIMING_VFP)\ + *BOARD_LCD_FRAMERATE) + + +#define BOARD_ISI_VSYNC {PIO_PA30C_ISI_VSYNC, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +#define BOARD_ISI_HSYNC {PIO_PA31C_ISI_HSYNC, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +#define BOARD_ISI_PCK {PIO_PC30C_ISI_PCK, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +#define BOARD_ISI_PINS_DATA {0x00FF0000, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} + +#define PIN_ISI_RST {1 << 24, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_ISI_RSTN {1 << 29, PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT} + +#define PINS_ISI BOARD_ISI_VSYNC, BOARD_ISI_HSYNC, BOARD_ISI_PCK , BOARD_ISI_PINS_DATA + +/** Touchscreen ADC clock frequency to use. */ +#define BOARD_TOUCHSCREEN_ADCCLK 300000 /* 8MHz max */ +/** Touchscreen ADC startup time in µseconds. */ +#define BOARD_TOUCHSCREEN_STARTUP 40 +/** Touchscreen ADC track and hold time in nanoseconds. */ +#define BOARD_TOUCHSCREEN_SHTIM 2000 /* min 1µs at 8MHz */ +/** Touchscreen pen debounce time in nanoseconds. */ +#define BOARD_TOUCHSCREEN_DEBOUNCE 10000000 + +/** HDMI reset pins. */ +#define PIN_HDMI_RESET_L {PIO_PC31, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} +#define PIN_HDMI_RESET_H {PIO_PC31, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/*----------------------------------------------------------------------------*/ +/** + * \page sama5d3x_ek_chipdef "sama5d3-xplained - Individual chip definition" + * This page lists the definitions related to different chip's definition + * located in the board.h file for the sama5d3-xplained. + * + * LEDs + * - \ref PIN_LED_0 + * - \ref PIN_LED_1 + * - \ref PIN_LED_2 + * - \ref PINS_LEDS + * + * Push buttons + * - \ref PIN_PUSHBUTTON_1 + * - \ref PINS_PUSHBUTTONS + + * + * PCK0 + * - \ref PIN_PCK0 + * + * PCK1 + * - \ref PIN_PCK1 + */ + +#ifdef BOARD_VB +#define LED_BLUE 0 +#define LED_GREEN 1 +#define LED_RED 2 +#define LED_YELLOW 3 + +/** LED #0 pin definition (BLUE). */ +#define PIN_LED_0 {(1<<23), PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition (GREEN). */ +#define PIN_LED_1 {(1<<21), PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #2 pin definition (RED). */ +#define PIN_LED_2 {(1<<22), PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #3 pin definition (YELLOW). */ +#define PIN_LED_3 {(1<<5), PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT} + +/** List of all LEDs definitions. */ +#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2, PIN_LED_3 +#endif + +#if defined(BOARD_XPLAINED) +#define LED_BLUE 0 +#define LED_RED 1 + +/** LED #0 pin definition (LED_BLUE). */ +#define PIN_LED_0 {(PIO_PE23), PIOE, ID_PIOE, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #1 pin definition (LED_RED). */ +#define PIN_LED_1 {(PIO_PE24), PIOE, ID_PIOE, PIO_OUTPUT_0, PIO_DEFAULT} + +/** List of all LEDs definitions. */ +#define PINS_LEDS PIN_LED_0, PIN_LED_1 +#endif + +/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ +#define PIN_PUSHBUTTON_1 {PIO_PE29, PIOE, ID_PIOE, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1 + +/** Push button #1 index. */ +#define PUSHBUTTON_BP1 0 +/** Push button #2 index. */ +#define PUSHBUTTON_BP2 1 +/** Simulate Joystick Left */ +#define JOYSTICK_LEFT 1 +/** Simulate Joystick Right */ +#define JOYSTICK_RIGHT 0 + +#define NO_PUSHBUTTON + +/** PCK0 */ +#define PIN_PCK0 {PIO_PD30B_PCK0, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** PCK1 */ +#define PIN_PCK1 {PIO_PD31B_PCK1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** PCK2 */ +#define PIN_PCK2 {PIO_PC15B_PCK2, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + +/** PWM0 */ +#define PIN_PWM0_H {PIO_PA20B_PWMH0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWM0_L {PIO_PA21B_PWML0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWM0_FI {PIO_PC28B_PWMFI0, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + + +#define PIN_PWM1_H {PIO_PA22B_PWMH1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWM1_L {PIO_PA23B_PWML1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_PWM1_FI {PIO_PC31B_PWMFI1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + +/*---------------------------------------------------------------------------- + * Headers for board + *----------------------------------------------------------------------------*/ + +#include "include/board_lowlevel.h" +#include "include/board_memories.h" +#include "include/bmp.h" +#include "include/mii.h" +#include "include/gmii.h" +#include "include/emacd.h" +#include "include/macb.h" +#include "include/gmacd.h" +#include "include/gmacb.h" +#include "include/clock.h" +#include "include/dbgu_console.h" +#include "include/dbg_util.h" +#include "include/iso7816_4.h" +#include "include/dmad.h" +#include "include/dma_hardware_interface.h" +#include "include/hamming.h" + +#include "include/led.h" +#include "include/math.h" +#include "include/mcid.h" +#include "include/timetick.h" +#include "include/wav.h" +#include "include/wm8904.h" +#include "include/qt1070.h" + +#include "include/lcdd.h" +#include "include/lcd_draw.h" +#include "include/lcd_font10x14.h" +#include "include/lcd_font.h" +#include "include/lcd_color.h" +#include "include/tsd.h" +#include "include/tsd_com.h" +#include "include/cand.h" +#include "include/ov.h" +#include "include/omnivision.h" +#include "include/ovyuv.h" +#endif /* #ifndef _BOARD_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ads7843.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ads7843.h new file mode 100644 index 000000000..c2651846d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ads7843.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for ADS7843 driver. + */ + +#ifndef _ADS7843_ +#define _ADS7843_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void ADS7843_Initialize( void ) ; + +extern void ADS7843_Reset( void ) ; + +extern void ADS7843_GetPosition( uint32_t *px_pos, uint32_t *py_pos ) ; + +#endif /* #ifndef _ADS7843_H */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/bmp.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/bmp.h new file mode 100644 index 000000000..60470f329 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/bmp.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * \section Purpose + * + * Utility for BMP + * + */ + +#ifndef BMP_H +#define BMP_H + +/** BMP magic number ('BM'). */ +#define BMP_TYPE 0x4D42 + +/** headerSize must be set to 40 */ +#define BITMAPINFOHEADER 40 + +/*------------------------------------------------------------------------------ + * Exported types + *------------------------------------------------------------------------------*/ + +/* + * In case of IAR EWARM use, we define an empty macro to turn useless GCC and MDK __attribute__ keyword + */ +#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__ +# pragma pack( 1 ) +#endif + +/** BMP (Windows) File Header Format */ +typedef struct _BMPFileHeader +{ + /** signature, must be 4D42 hex */ + uint16_t type; + /** size of BMP file in bytes (unreliable) */ + uint32_t fileSize; + /** reserved, must be zero */ + uint16_t reserved1; + /** reserved, must be zero */ + uint16_t reserved2; + /** offset to start of image data in bytes */ + uint32_t offset; +} BMPFileHeader; + +/** BMP (Windows 2.x) Header */ +typedef struct _BMP2XHeader +{ + /** size of this header in bytes */ + uint32_t size; + /** image width in pixels */ + uint16_t width; + /** image height in pixels */ + uint16_t height; + /** number of color planes */ + uint16_t planes; + /** number of bits per pixel */ + uint16_t bitsPerPixel; +} BMP2XHeader; + +/** BMP (Windows 3.x) Header, 40 bytes */ +typedef struct _BMP3XHeader +{ + /** size of this header in bytes */ + uint32_t size; + /** image width in pixels */ + int32_t width; + /** image height in pixels */ + int32_t height; + /** number of color planes */ + uint16_t planes; + /** number of bits per pixel */ + uint16_t bitsPerPixel; + /** Compression methods used */ + uint32_t compression; + /** Size of bitmap in bytes */ + uint32_t sizeOfBitmap; + /** horizontal resolution in pixels per meter */ + int32_t xResolution; + /** vertical resolution in pixels per meter */ + int32_t yResolution; + /** number of colors in the image */ + uint32_t colorsUsed; + /** minimum number of important colors */ + uint32_t colorsImportant; +} BMP3XHeader; + +/** BMP (Windows 95, V4) Header, 108 bytes */ +typedef struct _BMP4Header +{ + /** size of this header in bytes */ + uint32_t size; + /** image width in pixels */ + int32_t width; + /** image height in pixels */ + int32_t height; + /** number of color planes */ + uint16_t planes; + /** number of bits per pixel */ + uint16_t bitsPerPixel; + /** Compression methods used */ + uint32_t compression; + /** Size of bitmap in bytes */ + uint32_t sizeOfBitmap; + /** horizontal resolution in pixels per meter */ + int32_t xResolution; + /** vertical resolution in pixels per meter */ + int32_t yResolution; + /** number of colors in the image */ + uint32_t colorsUsed; + /** minimum number of important colors */ + uint32_t colorsImportant; + + /** Mask identifying bits of red component */ + uint32_t redMask; + /** Mask identifying bits of green component */ + uint32_t greenMask; + /** Mask identifying bits of blue component */ + uint32_t blueMask; + /** Mask identifying bits of alpha component */ + uint32_t alphaMask; + /** Color space type */ + uint32_t csType; + /** X coordinate of red endpoint */ + int32_t redX; + /** Y coordinate of red endpoint */ + int32_t redY; + /** Z coordinate of red endpoint */ + int32_t redZ; + /** X coordinate of green endpoint */ + int32_t greenX; + /** Y coordinate of green endpoint */ + int32_t greenY; + /** Z coordinate of green endpoint */ + int32_t greenZ; + /** X coordinate of blue endpoint */ + int32_t blueX; + /** Y coordinate of blue endpoint */ + int32_t blueY; + /** Z coordinate of blue endpoint */ + int32_t blueZ; + /** Gamma red coordinate scale value */ + uint32_t gammaRed; + /** Gamma green coordinate scale value */ + uint32_t gammaGreen; + /** Gamma blue coordinate scale value */ + uint32_t gammaBlue; +} BMP4Header; + +/** BMP (Windows) Header Format */ +typedef struct _BMPHeader +{ + /* signature, must be 4D42 hex */ + uint16_t type; + /* size of BMP file in bytes (unreliable) */ + uint32_t fileSize; + /* reserved, must be zero */ + uint16_t reserved1; + /* reserved, must be zero */ + uint16_t reserved2; + /* offset to start of image data in bytes */ + uint32_t offset; + /* size of BITMAPINFOHEADER structure, must be 40 */ + uint32_t headerSize; + /* image width in pixels */ + uint32_t width; + /* image height in pixels */ + uint32_t height; + /* number of planes in the image, must be 1 */ + uint16_t planes; + /* number of bits per pixel (1, 4, 8, 16, 24, 32) */ + uint16_t bits; + /* compression type (0=none, 1=RLE-8, 2=RLE-4) */ + uint32_t compression; + /* size of image data in bytes (including padding) */ + uint32_t imageSize; + /* horizontal resolution in pixels per meter (unreliable) */ + uint32_t xresolution; + /* vertical resolution in pixels per meter (unreliable) */ + uint32_t yresolution; + /* number of colors in image, or zero */ + uint32_t ncolours; + /* number of important colors, or zero */ + uint32_t importantcolours; + +} BMPHeader ; // GCC + +#if defined __ICCARM__ || defined __CC_ARM || defined __GNUC__ +# pragma pack() +#endif + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +extern uint8_t BMP_IsValid(void *file); + +extern uint32_t BMP_GetFileSize(void *file); + +extern uint8_t BMP_Decode( + void *file, + uint8_t*buffer, + uint32_t width, + uint32_t height, + unsigned char bpp); + +extern void WriteBMPheader(uint32_t* pAddressHeader, + uint32_t bmpHSize, + uint32_t bmpVSize, + uint8_t bmpRgb, + uint8_t nbByte_Pixels); + +extern void BMP_displayHeader(uint32_t* pAddressHeader); + +extern void RGB565toBGR555( + uint8_t *fileSource, + uint8_t *fileDestination, + uint32_t width, + uint32_t height, + uint8_t bpp); + +#endif //#ifndef BMP_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/board_lowlevel.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/board_lowlevel.h new file mode 100644 index 000000000..f9d39693b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/board_lowlevel.h @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for the low-level initialization function. + * + */ + +#ifndef BOARD_LOWLEVEL_H +#define BOARD_LOWLEVEL_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void defaultSpuriousHandler( void ); +extern void defaultFiqHandler( void ); +extern void defaultIrqHandler( void ); +extern void LowLevelInit( void ) ; + +#endif /* BOARD_LOWLEVEL_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/board_memories.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/board_memories.h new file mode 100644 index 000000000..3f23e16cd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/board_memories.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for memories configuration on board. + * + */ + +#ifndef BOARD_MEMORIES_H +#define BOARD_MEMORIES_H + + // Micron MT47H128M16 ?16 Meg x 16 x 8 banks = 256 MBytes + // => 2 chips used => 512 MBytes + // data bus = 32 bits => 16 Meg x 32 x 8 Banks => 256 Meg * 16 available + +#define DDR2_MEM8SIZE 0x20000000 +#define DDR2_MEM16SIZE 0x10000000 +#define DDR2_MEM32SIZE 0x8000000 + +#define EXT_32_LPDDR2_8BANK_16_32_SOD200_SIZE 0x20000000 + + + +//void LPDDR2_AC_TIMING(LPDDR2 * st_ddr2, unsigned int f_base); +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void BOARD_RemapRom( void ); +extern void BOARD_RemapRam( void ); +extern void BOARD_ConfigureVddMemSel(uint8_t VddMemSel) ; +extern void BOARD_ConfigureDdram( uint8_t device ); +extern void BOARD_ConfigureSdram( void ); +extern void BOARD_ConfigureNandFlash( uint8_t busWidth ) ; +extern void BOARD_ConfigureNorFlash( uint8_t busWidth ) ; +extern void BOARD_ConfigureLpDdram(void); +#endif /* #ifndef BOARD_MEMORIES_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/cand.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/cand.h new file mode 100644 index 000000000..25f8e7b0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/cand.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ +/** + * \ingroup lib_board + * \addtogroup cand_module CAN Driver + * + * \section Purpose + * + * Implement driver functions for CAN operations. + * + * \section cand_usage Usage + * + * Uses following functions for CAN operations. + * -# Uses CAND_Handler() as peripheral interrupt handler. + * -# Uses CAND_Init() to initialize the driver and peripheral. + * -# Uses CAND_Activate() to enable the CAN interface. Then check + * CAND_IsReady() to find when CAN is synchronized for data transfer. + * -# To send a CAN message you can: + * -# Initialize mailbox with CAND_ResetMailbox() + * -# Start data transfer with CAND_Transfer() + * -# You can also start CAN message by: + * -# Initialize transfer with CAND_ConfigureTransfer(). Several + * transfers linked to different mailbox can be initialized. + * -# After configuration, transfers can be enabled by + * CAND_StartTransfers() at one time. + * -# To check if the transfer is done, CAND_IsTransferDone() is used. + * + * The following structs should be instanced for driver operations. + * -# \ref sCand : Driver instance struct. + * -# \ref sCandMbCfg : Mailbox configuration parameters list. + * -# \ref sCandTransfer : Message transfer operation parameters list. + * + */ + +#ifndef _CAND_H_ +#define _CAND_H_ +/**@{*/ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup cand_rc CAN Driver Status (Return Codes) + * @{*/ +/** Operation success */ +#define CAND_OK 0 +/** The driver/mailbox is busy */ +#define CAND_BUSY 1 +/** General error */ +#define CAND_ERROR 0x10 +/** Bad operation because of wrong state */ +#define CAND_ERR_STATE 0x11 +/** Bad operation for parameter error */ +#define CAND_ERR_PARAM 0xFE +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/* CAN Driver General callback */ +//typedef void(*CandCallback)(uint8_t bEvent, void* pArg); + +/** CAN Driver Mailbox settings */ +typedef struct _CandMbCfg { + uint32_t dwMsgMask; /**< Message ID Mask _MAMx */ + uint8_t bMsgType; /**< Message type */ + uint8_t bTxPriority; /**< Priority for TX */ +} sCandMbCfg; + +/** CAN Driver Transfer Parameters */ +typedef struct _CandTransfer { + //void* fCallback; /**< Callback function when transfer finished */ + //void* pArg; /**< Callback arguments */ + + uint32_t dwMsgID; /**< Message ID _MIDx */ + uint32_t msgData[2]; /**< Message data */ + uint8_t bMailbox; /**< Mailbox used */ + uint8_t bMsgLen; /**< Message length */ + uint8_t bState; /**< Transfer state */ + uint8_t bRC; /**< Transfer return code */ +} sCandTransfer; + +/** CAN Driver Transfer callback */ +typedef void(*CandTransferCallback)(sCandTransfer* pXfr); + +/** + * CAN Driver instance struct. + */ +typedef struct _Cand { + Can* pHw; /**< Pointer to HW register base */ + + //CandCallback fCallback; /**< Pointer to Callback function */ + //void* pArg; /**< Pointer to Callback argument */ + + sCandTransfer *pMbs[CAN_NUM_MAILBOX]; /**< Pointer list to mailboxes */ + + uint32_t dwMck; /**< MCK for baudrate calculating */ + uint16_t wBaudrate; /**< Current working baudrate */ + + uint8_t bID; /**< Peripheral ID */ + uint8_t bState; /**< CAN states */ +} sCand; + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t CAND_Init(sCand * pCand, + Can * pHw,uint8_t bID, + uint16_t wBaudrate,uint32_t dwMck); +extern void CAND_Activate(sCand * pCand); +extern void CAND_Sleep(sCand * pCand); +extern uint8_t CAND_IsReady(sCand * pCand); +extern void CAND_Handler(sCand * pCand); +extern uint8_t CAND_IsMailboxReady(sCand * pCand,uint8_t bMb); +extern void CAND_ResetMailbox(sCand * pCand,uint8_t bMb,sCandMbCfg * pCfg); +extern uint8_t CAND_ConfigureTransfer(sCand * pCand, + sCandMbCfg * pCfg, + sCandTransfer * pXfr); +extern uint8_t CAND_Transfer(sCand * pCand,sCandTransfer * pXfr); +extern void CAND_StartTransfers(sCand * pCand,uint32_t bmMbs); +extern uint8_t CAND_IsTransferDone(sCandTransfer * pXfr); +/**@}*/ +#endif /* #ifndef _CAN_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/clock.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/clock.h new file mode 100644 index 000000000..64bc33baf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/clock.h @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _CLOCK_ +#define _CLOCK_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void CLOCK_SetConfig( uint8_t configuration ) ; + +extern void CLOCK_DisplayMenu( void ) ; + +extern void CLOCK_UserChangeConfig( void ) ; + +extern uint16_t CLOCK_GetCurrMCK( void ) ; + +extern uint16_t CLOCK_GetCurrPCK( void ) ; + +#endif /* #ifndef _CLOCK_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dbg_util.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dbg_util.h new file mode 100644 index 000000000..e87e2cebb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dbg_util.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Implements DBG utility that uses DBGU and System tick to get byte or binary + * stream from DBGU console. + */ + +#ifndef _DBG_UTIL_ +#define _DBG_UTIL_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +extern uint8_t DbgReceiveByte(uint8_t * pByte,uint32_t timeOut); + +extern uint32_t DbgReceiveBinary(uint8_t start, + uint32_t address, + uint32_t maxSize); + +extern uint32_t DbgReceive1KXModem(uint8_t * pktBuffer, + uint32_t address, + uint32_t maxSize); + +#endif /* _DBG_UTIL_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dbgu_console.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dbgu_console.h new file mode 100644 index 000000000..42ab23932 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dbgu_console.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef _DBGU_CONSOLE_ +#define _DBGU_CONSOLE_ + +#include + +/** Console baudrate always using 115200. */ +#define CONSOLE_BAUDRATE 115200 + +extern void DBGU_ConsoleUseDBGU(void); +extern void DBGU_ConsoleUseUSART0(void); +extern void DBGU_ConsoleUseUSART1(void); + +extern void DBGU_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ; +extern void DBGU_PutChar( uint8_t uc ) ; +extern uint32_t DBGU_GetChar( void ) ; +extern uint32_t DBGU_IsRxReady( void ) ; + + +extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ; +extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ; +extern uint32_t DBGU_GetInteger( uint32_t* pdwValue ) ; +extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax ) ; +extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue ) ; + +#endif /* _DBGU_CONSOLE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dma_hardware_interface.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dma_hardware_interface.h new file mode 100644 index 000000000..63f383a88 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dma_hardware_interface.h @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _DMAD_IF_H +#define _DMAD_IF_H + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DMA hardware interface */ +typedef struct _DmaHardwareInterface { + uint8_t bDmac; /**< DMA Controller number */ + uint32_t bPeriphID; /**< Peripheral ID */ + uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/ + uint8_t bIfID; /**< DMA Interface ID */ +} DmaHardwareInterface; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t DMAIF_IsValidatedPeripherOnDma( uint8_t bDmac, uint8_t bPeriphID); +extern uint8_t DMAIF_Get_ChannelNumber (uint8_t bDmac, uint8_t bPeriphID, uint8_t bTransfer); + +#endif //#ifndef _DMAD_IF_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dmad.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dmad.h new file mode 100644 index 000000000..5140eed5b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/dmad.h @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _DMAD_H +#define _DMAD_H +/** \addtogroup dmad_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/** \addtogroup dmad_defines DMA Driver Defines + @{*/ +/*---------------------------------------------------------------------------- + * Consts + *----------------------------------------------------------------------------*/ +#define DMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */ +#define DMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */ + +#define DMAD_TRANSFER_TX 0 +#define DMAD_TRANSFER_RX 1 +/*---------------------------------------------------------------------------- + * MACRO + *----------------------------------------------------------------------------*/ + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_structs DMA Driver Structs + @{*/ + +/** DMA status or return code */ +typedef enum _DmadStatus { + DMAD_OK = 0, /**< Operation is sucessful */ + DMAD_BUSY, /**< Channel occupied or transfer not finished */ + DMAD_PARTIAL_DONE, /**< Partial of LLI finished (on each buffer done) */ + DMAD_ERROR, /**< Operation failed */ + DMAD_CANCELED /**< Operation canceled */ +} eDmadStatus, eDmadRC; + +/** DMA state for channel */ +typedef enum _DmadState { + DMAD_FREE = 0, /**< Free channel */ + DMAD_IN_USE, /**< Allocated to some peripheral */ + DMAD_IN_XFR, /**< Transferring something */ + DMAD_STALL /**< Error stall */ +} eDmadState; + +/** DMA transfer callback */ +typedef void (*DmadTransferCallback)(uint32_t status, void* pArg); + +/** DMA driver channel */ +typedef struct _DmadChannel { + DmadTransferCallback fCallback; /**< Callback */ + void* pArg; /**< Callback argument */ + + uint8_t bIrqOwner; /**< Uses DMA handler or external one */ + uint8_t bSrcPeriphID; /**< HW ID for source */ + uint8_t bDstPeriphID; /**< HW ID for destination */ + uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */ + uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */ + uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */ + uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */ + + volatile uint8_t state; /**< DMA channel state */ +} sDmadChannel; + +#if 0 +/** DMA driver controller */ +typedef struct _DmadController { + Dmac *pHw; /**< Pointer to controler HW base */ + sDmadChannel* dmadChannels; /**< Pointer to driver channels list */ + uint8_t* dmadIfUsage; /**< AHB Interface usage counting */ + uint8_t bHwID; /**< ID for DMAC */ + uint8_t bNumChannels; /**< Number of channels for this controller */ + uint8_t bNumAHBIf; /**< Number of AHB Interface */ + uint8_t reserved; +} sDmadController; +#endif + +/** DMA driver instance */ +typedef struct _Dmad { + Dmac *pDmacs[2]; + sDmadChannel dmaChannels[2][8]; + uint8_t numControllers; + uint8_t numChannels; + uint8_t pollingMode; + uint8_t pollingTimeout; +} sDmad; + +/** DMA driver channel ID */ +typedef struct _DmadChannelID { + uint8_t bDmac; /**< DMA Controller number */ + uint8_t bChannel; /**< Channel number */ +} sDmadChannelID; + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_functions DMA Driver Functionos + @{*/ +extern void DMAD_Initialize( sDmad *pDmad, + uint8_t bPollingMode ); + +extern void DMAD_Handler( sDmad *pDmad ); + +extern uint32_t DMAD_AllocateChannel( sDmad *pDmad, + uint8_t bSrcID, uint8_t bDstID); +extern eDmadRC DMAD_FreeChannel( sDmad *pDmad, uint32_t dwChannel ); + +extern eDmadRC DMAD_SetCallback( sDmad *pDmad, uint32_t dwChannel, + DmadTransferCallback fCallback, void* pArg ); + +extern eDmadRC DMAD_ConfigurePIP( sDmad *pDmad, uint32_t dwChannel, + uint32_t dwSrcPIP, uint32_t dwDstPIP ); + +extern eDmadRC DMAD_PrepareChannel( sDmad *pDmad, uint32_t dwChannel, + uint32_t dwCfg ); + +extern eDmadRC DMAD_IsTransferDone( sDmad *pDmad, uint32_t dwChannel ); + +extern eDmadRC DMAD_StartTransfer( sDmad *pDmad, uint32_t dwChannel ); +extern eDmadRC DMAD_StartTransfers( sDmad *pDmad, + uint8_t bDmac, uint32_t bmChannels ); + +extern eDmadRC DMAD_StopTransfer( sDmad *pDmad, uint32_t dwChannel ); +extern void DMAD_ClearAuto( sDmad *pDmad, uint32_t _dwChannel ); +extern eDmadRC DMAD_PrepareSingleTransfer( sDmad *pDmad, uint32_t dwChannel, + sDmaTransferDescriptor *pXfrDesc ); + +extern eDmadRC DMAD_PrepareMultiTransfer( sDmad *pDmad, uint32_t dwChannel, + sDmaTransferDescriptor *pXfrDesc ); +/** @}*/ +/**@}*/ +#endif //#ifndef _DMAD_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/emacd.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/emacd.h new file mode 100644 index 000000000..2db168177 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/emacd.h @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup emacd_module + * @{ + * Implement EMAC data transfer and PHY management functions. + * + * \section Usage + * -# Implement EMAC interrupt handler, which must invoke EMACD_Handler() + * to handle EMAC interrupt events. + * -# Implement sEmacd instance in application. + * -# Initialize the instance with EMACD_Init() and EMACD_InitTransfer(), + * so that EMAC data can be transmitted/received. + * -# Some management callbacks can be set by EMACD_SetRxCallback() + * and EMACD_SetTxWakeupCallback(). + * -# Send ethernet packets using EMACD_Send(), EMACD_TxLoad() is used + * to check the free space in TX queue. + * -# Check and obtain received ethernet packets via EMACD_Poll(). + * + * \sa \ref macb_module, \ref emac_module + * + * Related files:\n + * \ref emacd.c\n + * \ref emacd.h.\n + * + * \defgroup emacd_defines EMAC Driver Defines + * \defgroup emacd_types EMAC Driver Types + * \defgroup emacd_functions EMAC Driver Functions + */ +/**@}*/ + +#ifndef _EMACD_H_ +#define _EMACD_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup emacd_defines + @{*/ + +/** \addtogroup emacd_buf_size EMACD Default Buffer Size + @{*/ +#define EMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ +#define EMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ +/** @}*/ + +/** \addtogroup emacd_rc EMACD Return Codes + @{*/ +#define EMACD_OK 0 /**< Operation OK */ +#define EMACD_TX_BUSY 1 /**< TX in progress */ +#define EMACD_RX_NULL 1 /**< No data received */ +/** Buffer size not enough */ +#define EMACD_SIZE_TOO_SMALL 2 +/** Parameter error, TX packet invalid or RX size too small */ +#define EMACD_PARAM 3 +/** Transter is not initialized */ +#define EMACD_NOT_INITIALIZED 4 +/** @}*/ + +/** @}*/ +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ +/** \addtogroup emacd_types + @{*/ + +/** RX callback */ +typedef void (*fEmacdTransferCallback)(uint32_t status); +/** Wakeup callback */ +typedef void (*fEmacdWakeupCallback)(void); + +/** + * EMAC driver struct. + */ +typedef struct _EmacDriver { + + /** Pointer to HW register base */ + Emac *pHw; + + /** Pointer to allocated TX buffer + Section 3.6 of AMBA 2.0 spec states that burst should not cross + 1K Boundaries. + Receive buffer manager writes are burst of 2 words => 3 lsb bits + of the address shall be set to 0 + */ + uint8_t *pTxBuffer; + /** Pointer to allocated RX buffer */ + uint8_t *pRxBuffer; + + /** Pointer to Rx TDs (must be 8-byte aligned) */ + sEmacRxDescriptor *pRxD; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + sEmacTxDescriptor *pTxD; + + /** Optional callback to be invoked once a frame has been received */ + fEmacdTransferCallback fRxCb; + /** Optional callback to be invoked once several TD have been released */ + fEmacdWakeupCallback fWakupCb; + /** Optional callback list to be invoked once TD has been processed */ + fEmacdTransferCallback *fTxCbList; + + /** RX TD list size */ + uint16_t wRxListSize; + /** RX index for current processing TD */ + uint16_t wRxI; + + /** TX TD list size */ + uint16_t wTxListSize; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t wTxHead; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t wTxTail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t bWakeupThreshold; + /** HW ID */ + uint8_t bId; +} sEmacd; + +/** @}*/ + +/** \addtogroup emacd_functions + @{*/ + +/*--------------------------------------------------------------------------- + * PHY Exported functions + *---------------------------------------------------------------------------*/ + +/*--------------------------------------------------------------------------- + * EMAC Exported functions + *---------------------------------------------------------------------------*/ + +extern void EMACD_Init( sEmacd *pEmacd, + Emac *pHw, uint8_t bID, + uint8_t bCAF, uint8_t bNBC); + +extern uint8_t EMACD_InitTransfer( sEmacd *pEmacd, + uint8_t *pRxBuffer, sEmacRxDescriptor *pRxD, + uint16_t wRxSize, + uint8_t *pTxBuffer, sEmacTxDescriptor *pTxD, fEmacdTransferCallback *pTxCb, + uint16_t wTxSize); + +extern void EMACD_SetRxCallback( sEmacd *pEmacd, fEmacdTransferCallback fRxCb); + +extern uint8_t EMACD_SetTxWakeupCallback( sEmacd *pEmacd, + fEmacdWakeupCallback fWakeup, + uint8_t bThreshold ); + +extern void EMACD_Handler( sEmacd *pEmacd ); + +extern void EMACD_Reset( sEmacd * pEmacd ); + +extern uint8_t EMACD_Send(sEmacd * pEmacd, + void *pBuffer, + uint32_t size, + fEmacdTransferCallback fTxCallback); + +extern uint32_t EMACD_TxLoad( sEmacd *pEmacd ); + +extern uint8_t EMACD_Poll(sEmacd * pEmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize); + +/** @}*/ + +#endif // #ifndef _EMACD_H_ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmacb.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmacb.h new file mode 100644 index 000000000..7f8c794a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmacb.h @@ -0,0 +1,112 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmacb_module Ethernet GMACB Driver + *@{ + * Implement GEMAC PHY driver, that initialize the PHY to prepare for + * ethernet transfer. + * + * \section Usage + * -# EMAC related pins and Driver should be initialized at first. + * -# Initialize GMACB Driver instance by invoking GMACB_Init(). + * -# Initialize PHY connected via GMACB_InitPhy(), PHY address is + * automatically adjusted by attempt to read. + * -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so + * connection established. + * + * + * Related files:\n + * \ref gmacb.h\n + * \ref gmacb.c\n + * \ref gmii.h.\n + * + */ +/**@}*/ + +#ifndef _GMACB_H +#define _GMACB_H + + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** The reset length setting for external reset configuration */ +#define GMACB_RESET_LENGTH 0xD + +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ + + +/** The DM9161 instance */ +typedef struct _GMacb { + sGmacd *pGmacd; /**< Driver */ + /** The retry & timeout settings */ + uint32_t retryMax; + /** PHY address ( pre-defined by pins on reset ) */ + uint8_t phyAddress; +} GMacb; + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ +extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax); + +extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress); + +extern uint8_t GMACB_InitPhy(GMacb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pEmacPins, + uint32_t nbEmacPins); + +extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb); + +extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings); + +extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size); + +extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size); + +extern void GMACB_DumpRegisters(GMacb *pMacb); + +extern uint8_t GMACB_ResetPhy(GMacb *pMacb); + +#endif // #ifndef _GMACB_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmacd.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmacd.h new file mode 100644 index 000000000..b43d6636c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmacd.h @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmacd_module + * @{ + * Implement GMAC data transfer and PHY management functions. + * + * \section Usage + * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler() + * to handle GMAC interrupt events. + * -# Implement sGmacd instance in application. + * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(), + * so that GMAC data can be transmitted/received. + * -# Some management callbacks can be set by GMACD_SetRxCallback() + * and GMACD_SetTxWakeupCallback(). + * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used + * to check the free space in TX queue. + * -# Check and obtain received ethernet packets via GMACD_Poll(). + * + * \sa \ref gmacb_module, \ref gmac_module + * + * Related files:\n + * \ref gmacd.c\n + * \ref gmacd.h.\n + * + * \defgroup gmacd_defines GMAC Driver Defines + * \defgroup gmacd_types GMAC Driver Types + * \defgroup gmacd_functions GMAC Driver Functions + */ +/**@}*/ + +#ifndef _GMACD_H_ +#define _GMACD_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_defines + @{*/ + +/** \addtogroup gmacd_buf_size GMACD Default Buffer Size + @{*/ +#define GMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ +#define GMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ +/** @}*/ + +/** \addtogroup gmacd_rc GMACD Return Codes + @{*/ +#define GMACD_OK 0 /**< Operation OK */ +#define GMACD_TX_BUSY 1 /**< TX in progress */ +#define GMACD_RX_NULL 1 /**< No data received */ +/** Buffer size not enough */ +#define GMACD_SIZE_TOO_SMALL 2 +/** Parameter error, TX packet invalid or RX size too small */ +#define GMACD_PARAM 3 +/** Transter is not initialized */ +#define GMACD_NOT_INITIALIZED 4 +/** @}*/ + +/** @}*/ + +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_types + @{*/ + +/** RX callback */ +typedef void (*fGmacdTransferCallback)(uint32_t status); +/** Wakeup callback */ +typedef void (*fGmacdWakeupCallback)(void); + +/** + * GMAC driver struct. + */ +typedef struct _GmacDriver { + + /** Pointer to HW register base */ + Gmac *pHw; + + uint8_t *pTxBuffer; + /** Pointer to allocated RX buffer */ + uint8_t *pRxBuffer; + + /** Pointer to Rx TDs (must be 8-byte aligned) */ + sGmacRxDescriptor *pRxD; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + sGmacTxDescriptor *pTxD; + + /** Optional callback to be invoked once a frame has been received */ + fGmacdTransferCallback fRxCb; + /** Optional callback to be invoked once several TD have been released */ + fGmacdWakeupCallback fWakupCb; + /** Optional callback list to be invoked once TD has been processed */ + fGmacdTransferCallback *fTxCbList; + + /** RX TD list size */ + uint16_t wRxListSize; + /** RX index for current processing TD */ + uint16_t wRxI; + + /** TX TD list size */ + uint16_t wTxListSize; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t wTxHead; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t wTxTail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t bWakeupThreshold; + /** HW ID */ + uint8_t bId; +} sGmacd; + +/** @}*/ + +/** \addtogroup gmacd_functions + @{*/ + +/*--------------------------------------------------------------------------- + * GMAC Exported functions + *---------------------------------------------------------------------------*/ + +extern void GMACD_Handler(sGmacd *pGmacd ); + +extern void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC ); + +extern uint8_t GMACD_InitTransfer( sGmacd *pGmacd, + uint8_t *pRxBuffer, + sGmacRxDescriptor *pRxD, + uint16_t wRxSize, + uint8_t *pTxBuffer, + sGmacTxDescriptor *pTxD, + fGmacdTransferCallback *pTxCb, + uint16_t wTxSize); + +extern void GMACD_Reset(sGmacd *pGmacd); + +extern uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb ); + +extern uint32_t GMACD_TxLoad(sGmacd *pGmacd); + +extern uint8_t GMACD_Poll(sGmacd * pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize); + +extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb); + +extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold); + +/** @}*/ + +#endif // #ifndef _GMACD_H_ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmii.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmii.h new file mode 100644 index 000000000..e01a68cb8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/gmii.h @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _GMII_DEFINE_H +#define _GMII_DEFINE_H + + +//----------------------------------------------------------------------------- +/// Definitions +//----------------------------------------------------------------------------- +//IEEE defined Registers +#define GMII_BMCR 0 // Basic Mode Control Register +#define GMII_BMSR 1 // Basic Mode Status Register +#define GMII_PHYID1 2 // PHY Idendifier Register 1 +#define GMII_PHYID2 3 // PHY Idendifier Register 2 +#define GMII_ANAR 4 // Auto_Negotiation Advertisement Register +#define GMII_ANLPAR 5 // Auto_negotiation Link Partner Ability Register +#define GMII_ANER 6 // Auto-negotiation Expansion Register +#define GMII_ANNPR 7 // Auto-negotiation Next Page Register +#define GMII_ANLPNPAR 8 // Auto_negotiation Link Partner Next Page Ability Register +#define GMII_1000BTCR 9 // 1000Base-T Control +#define GMII_1000BTSR 10 // 1000Base-T Status +#define GMII_ERCR 11 // Extend Register - Control Register +#define GMII_ERDWR 12 // Extend Register - Data Write Register +#define GMII_ERDRR 13 // Extend Register - Data Read Register +//14 reserved +#define GMII_EMSR 15 // Extend MII Status Register + +//Vender Specific Register +//16 reserved +#define GMII_RLLMR 17 // Remote Loopback, LED Mode Register +#define GMII_LMDCDR 18 // LinkND - Cable Diagnostic Register +#define GMII_DPPSR 19 // Digital PMA/PCS Status +//20 reserved +#define GMII_RXERCR 21 // RXER Counter Register +//22-26 reserved +#define GMII_ICSR 27 // Interrupt Control/Status Register +#define GMII_DDC1R 28 // Digital Debug Control 1 Register +//29-30 reserved +#define GMII_PHYCR 31 // PHY Control Register + +//Extend Registers +#define GMII_CCR 256 // Common Control Register +#define GMII_SSR 257 // Strap Status Register +#define GMII_OMSOR 258 // Operation Mode Strap Override Register +#define GMII_OMSSR 259 // Operation Mode Strap Status Register +#define GMII_RCCPSR 260 // RGMII Clock and Control Pad Skew Register +#define GMII_RRDPSR 261 // RGMII RX Data Pad Skew Register +#define GMII_ATR 263 // Analog Test Register + + + +// Basic Mode Control Register (BMCR) +// Bit definitions: MII_BMCR +#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation +#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation +#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps +#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable +#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation +#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation +#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation +#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation +// Reserved 7 // Read as 0, ignore on write +#define GMII_SPEED_SELECT_MSB (1 << 6) // +// Reserved 5 to 0 // Read as 0, ignore on write + +// Basic Mode Status Register (BMSR) +// Bit definitions: MII_BMSR +#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable +#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable +#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable +#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable +#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable +// Reserved 10 to 9 // Read as 0, ignore on write +#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15 +// Reserved 7 +#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression +#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete +#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault +#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability +#define GMII_LINK_STATUS (1 << 2) // Link Status +#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect +#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability + +// PHY ID Identifier Register +// definitions: MII_PHYID1 +#define GMII_LSB_MASK 0x3F +#define GMII_OUI_MSB 0x0022 +#define GMII_OUI_LSB 0x05 + +// Auto-negotiation Advertisement Register (ANAR) +// Auto-negotiation Link Partner Ability Register (ANLPAR) +// Bit definitions: MII_ANAR, MII_ANLPAR +#define GMII_NP (1 << 15) // Next page Indication +// Reserved 7 +#define GMII_RF (1 << 13) // Remote Fault +// Reserved 12 // Write as 0, ignore on read +#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) + // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) +#define GMII_T4 (1 << 9) // 100BASE-T4 Support +#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support +#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support +#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support +#define GMII_10_HDX (1 << 5) // 10BASE-T Support +// Selector 4 to 0 // Protocol Selection Bits +#define GMII_AN_IEEE_802_3 0x0001 + +// Auto-negotiation Expansion Register (ANER) +// Bit definitions: MII_ANER +// Reserved 15 to 5 // Read as 0, ignore on write +#define GMII_PDF (1 << 4) // Local Device Parallel Detection Fault +#define GMII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able +#define GMII_NP_ABLE (1 << 2) // Local Device Next Page Able +#define GMII_PAGE_RX (1 << 1) // New Page Received +#define GMII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able + +// GMII_1000BTCR +#define GMII_1000BaseT_HALF_DUPLEX (1 << 8) +#define GMII_1000BaseT_FULL_DUPLEX (1 << 9) +#define GMII_MARSTER_SLAVE_ENABLE (1 << 12) +#define GMII_MARSTER_SLAVE_CONFIG (1 << 11) +#define GMII_PORT_TYPE (1 << 10) + +// GMII_1000BTSR +#define GMII_LINKP_1000BaseT_HALF_DUPLEX (1 << 10) +#define GMII_LINKP_1000BaseT_FULL_DUPLEX (1 << 11) + +// 1 master 0 slave +#endif // #ifndef _MII_DEFINE_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/hamming.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/hamming.h new file mode 100644 index 000000000..f5f4e394d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/hamming.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _HAMMING_ +#define _HAMMING_ + +/*------------------------------------------------------------------------------ + * Defines + *------------------------------------------------------------------------------*/ + +/** + * These are the possible errors when trying to verify a block of data encoded + * using a Hamming code: + * + * \section Errors + * - Hamming_ERROR_SINGLEBIT + * - Hamming_ERROR_ECC + * - Hamming_ERROR_MULTIPLEBITS + */ + +/** A single bit was incorrect but has been recovered. */ +#define Hamming_ERROR_SINGLEBIT 1 + +/** The original code has been corrupted. */ +#define Hamming_ERROR_ECC 2 + +/** Multiple bits are incorrect in the data and they cannot be corrected. */ +#define Hamming_ERROR_MULTIPLEBITS 3 + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +extern void Hamming_Compute256x( const uint8_t* pucData, uint32_t dwSize, uint8_t* pucCode ) ; + +extern uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode ) ; + +#endif /* _HAMMING_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/iso7816_4.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/iso7816_4.h new file mode 100644 index 000000000..2d3c6c040 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/iso7816_4.h @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/** \page + * + * \section Purpose + * + * Definition of methods for ISO7816 driver. + * + * \section Usage + * + * -# ISO7816_Init + * -# ISO7816_IccPowerOff + * -# ISO7816_XfrBlockTPDU_T0 + * -# ISO7816_Escape + * -# ISO7816_RestartClock + * -# ISO7816_StopClock + * -# ISO7816_toAPDU + * -# ISO7816_Datablock_ATR + * -# ISO7816_SetDataRateandClockFrequency + * -# ISO7816_StatusReset + * -# ISO7816_cold_reset + * -# ISO7816_warm_reset + * -# ISO7816_Decode_ATR + *----------------------------------------------------------------------------*/ + +#ifndef ISO7816_4_H +#define ISO7816_4_H + +/*------------------------------------------------------------------------------ + * Constants Definition + *----------------------------------------------------------------------------*/ + +/** Size max of Answer To Reset */ +#define ATR_SIZE_MAX 55 + +/** NULL byte to restart byte procedure */ +#define ISO_NULL_VAL 0x60 + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ISO7816_Init( const Pin pPinIso7816RstMC ); +extern void ISO7816_IccPowerOff(void); +extern uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength ); +extern void ISO7816_Escape( void ); +extern void ISO7816_RestartClock(void); +extern void ISO7816_StopClock( void ); +extern void ISO7816_toAPDU( void ); +extern void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength ); +extern void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate ); +extern uint8_t ISO7816_StatusReset( void ); +extern void ISO7816_cold_reset( void ); +extern void ISO7816_warm_reset( void ); +extern void ISO7816_Decode_ATR( uint8_t* pAtr ); + +#endif /* ISO7816_4_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_color.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_color.h new file mode 100644 index 000000000..43fb9ba55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_color.h @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef COLOR_H +#define COLOR_H + +/** + * \file + * + * RGB 24-bits color table definition. + * + */ + +/* + * RGB 24 Bpp + * RGB 888 + * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0 + */ +#define COLOR_BLACK 0x000000 +#define COLOR_WHITE 0xFFFFFF + +#define COLOR_BLUE 0x0000FF +#define COLOR_GREEN 0x00FF00 +#define COLOR_RED 0xFF0000 + +#define COLOR_NAVY 0x000080 +#define COLOR_DARKBLUE 0x00008B +#define COLOR_DARKGREEN 0x006400 +#define COLOR_DARKCYAN 0x008B8B +#define COLOR_CYAN 0x00FFFF +#define COLOR_TURQUOISE 0x40E0D0 +#define COLOR_INDIGO 0x4B0082 +#define COLOR_DARKRED 0x800000 +#define COLOR_OLIVE 0x808000 +#define COLOR_GRAY 0x808080 +#define COLOR_SKYBLUE 0x87CEEB +#define COLOR_BLUEVIOLET 0x8A2BE2 +#define COLOR_LIGHTGREEN 0x90EE90 +#define COLOR_DARKVIOLET 0x9400D3 +#define COLOR_YELLOWGREEN 0x9ACD32 +#define COLOR_BROWN 0xA52A2A +#define COLOR_DARKGRAY 0xA9A9A9 +#define COLOR_SIENNA 0xA0522D +#define COLOR_LIGHTBLUE 0xADD8E6 +#define COLOR_GREENYELLOW 0xADFF2F +#define COLOR_SILVER 0xC0C0C0 +#define COLOR_LIGHTGREY 0xD3D3D3 +#define COLOR_LIGHTCYAN 0xE0FFFF +#define COLOR_VIOLET 0xEE82EE +#define COLOR_AZUR 0xF0FFFF +#define COLOR_BEIGE 0xF5F5DC +#define COLOR_MAGENTA 0xFF00FF +#define COLOR_TOMATO 0xFF6347 +#define COLOR_GOLD 0xFFD700 +#define COLOR_ORANGE 0xFFA500 +#define COLOR_SNOW 0xFFFAFA +#define COLOR_YELLOW 0xFFFF00 + +#endif /* #define COLOR_H */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_draw.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_draw.h new file mode 100644 index 000000000..51dd2117c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_draw.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup lcdd_draw Drawing On LCD + * + * Interface for drawing function on LCD. + * + * \note Before drawing, canvas should be selected via + * LCDD_SelectCanvas(), or created by LCDD_CreateCanvas(). + * + * Following functions can use: + * - Simple drawing: + * - LCDD_Fill() + * - LCDD_DrawPixel() + * - LCDD_ReadPixel() + * - LCDD_DrawLine() + * - LCDD_DrawRectangle(), LCDD_DrawFilledRectangle() + * - LCDD_DrawCircle(), LCDD_DrawFilledCircle() + * - LCDD_DrawImage() + * - String related: + * - LCDD_DrawString() + * - LCDD_GetStringSize() + * + * \sa \ref lcdd_module, \ref lcdd_font + */ + +#ifndef DRAW_H +#define DRAW_H +/** \addtogroup lcdd_draw + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include +#include "lcd_gimp_image.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup lcdd_draw_func LCD Drawing Functions */ +/** @{*/ +extern void LCDD_Fill0( void ) ; + +extern void LCDD_Fill( uint32_t color ) ; + +extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t c ) ; + +extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y ) ; + +extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color ) ; + +extern void LCDD_DrawRectangle( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ; + +extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2, uint32_t dwColor ) ; + +extern void LCDD_DrawCircle( uint32_t x, uint32_t y, uint32_t r, uint32_t color ) ; +extern void LCDD_DrawFilledCircle(uint32_t dwX,uint32_t dwY,uint32_t dwR,uint32_t dwColor); + +extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color ) ; + +extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor ) ; + +extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight ) ; + +extern void LCDD_DrawImage( uint32_t x, uint32_t y, const uint8_t *pImage, uint32_t width, uint32_t height ) ; + +void LCDD_DrawGIMPImage( uint32_t dwX, uint32_t dwY, const SGIMPImage* pGIMPImage, uint32_t dwWidth, uint32_t dwHeight ) ; + +extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) ; +/** @}*/ +/**@}*/ +#endif /* #ifndef DRAW_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_font.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_font.h new file mode 100644 index 000000000..e76060202 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_font.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for draw font on LCD. + * + */ + +/** + * \addtogroup lcdd_font LCD Font Drawing + * + * \section Purpose + * + * The lcd_font.h files declares a font structure and a LCDD_DrawChar() function + * that must be implemented by a font definition file to be used with the + * LCDD_DrawString() method of draw.h. + * + * The font10x14.c implements the necessary variable and function for a 10x14 + * font. + * + * \note Before drawing fonts, canvas should be selected via + * LCDD_SelectCanvas(), or created by LCDD_CreateCanvas(). + * + * \section Usage + * + * -# Declare a gFont global variable with the necessary Font information. + * -# Implement an LCDD_DrawChar() function which displays the specified + * character on the LCD. + * -# Select or create canvas via LCDD_SelectCanvas() or LCDD_CreateCanvas(). + * -# Use the LCDD_DrawString() method defined in draw.h to display a complete + * string. + * + * \sa \ref lcdd_module, \ref lcdd_draw. + */ + +#ifndef _LCD_FONT_ +#define _LCD_FONT_ +/** \addtogroup lcdd_font + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** \brief Describes the font (width, height, supported characters, etc.) used by + * the LCD driver draw API. + */ +typedef struct _Font { + /* Font width in pixels. */ + uint8_t width; + /* Font height in pixels. */ + uint8_t height; +} Font; + +/*---------------------------------------------------------------------------- + * Variables + *----------------------------------------------------------------------------*/ + +extern const Font gFont; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup lcdd_font_func Font Functions */ +/** @{*/ + +extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color ) ; + +extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor ); +/** @}*/ +/**@}*/ +#endif /* #ifndef LCD_FONT_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_font10x14.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_font10x14.h new file mode 100644 index 000000000..427877a64 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_font10x14.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup lcdd_font + * @{ + * \addtogroup font_10x14 Font 10x14 + */ +/**@}*/ + +#ifndef _LCD_FONT_10x14_ +#define _LCD_FONT_10x14_ +/** \addtogroup font_10x14 + * @{ + */ + +#include + +extern const uint8_t pCharset10x14[] ; + +/** @}*/ +#endif /* #ifdef _LCD_FONT_10x14_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_gimp_image.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_gimp_image.h new file mode 100644 index 000000000..01d2e1e97 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcd_gimp_image.h @@ -0,0 +1,43 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _GIMP_IMAGE_ +#define _GIMP_IMAGE_ + +#include + +typedef struct _SGIMPImage +{ + uint32_t dwWidth; + uint32_t dwHeight; + uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */ + uint8_t* pucPixel_data ; +} SGIMPImage ; + +#endif // _GIMP_IMAGE_ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcdd.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcdd.h new file mode 100644 index 000000000..72cbad3b5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/lcdd.h @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** + * \ingroup lib_board + * \addtogroup lcdd_module LCD Driver + * + * \section Purpose + * + * Implement driver functions for LCD control and image display. + * - Implement basic LCD controler configuration. + * - Implement display functions for LCD layers. + * - Implement simple drawing functions. + * - Implement string display functions. + * + * \section lcdd_base_usage Usage + * + * Uses following functions for LCD basic configuration and displaying: + * -# Uses LCDD_Initialize() to initialize the controller and LCD. + * -# LCDD_On() and LCDD_Off() is used to turn LCD ON/OFF. + * -# LCDD_SetBacklight() is used to change LCD backlight level. + * -# To display a image (BMP format) on LCD, LCDD_ShowBMPRotated() + * LCDD_ShowBMPScaled() and LCDD_ShowBMP() can be used. + * -# To change configuration for an overlay layer, the following functions + * can use: + * -# LCDD_EnableLayer(), LCDD_IsLayerOn(): Turn ON/OFF layer, check status. + * -# LCDD_SetPosition(), LCDD_SetPrioty(), LCDD_EnableAlpha(), + * LCDD_SetAlpha(), LCDD_SetColorKeying(): Change display options. + * -# Shortcuts for layer display are as following: + * -# LCDD_ShowBase(), LCDD_StopBase() + * -# LCDD_ShowOvr1(), LCDD_StopOvr1() + * -# LCDD_ShowHeo(), LCDD_StopHeo() + * -# LCDD_ShowHcr(), LCDD_StopHcr() + * -# Drawing supporting fucntions, for drawing canvas: + * -# LCDD_CreateCanvas(): Create blank canvas on specified layer for + * drawing on + * -# LCDD_SelectCanvas(): Select a displayer as canvas to drawing on + * -# LCDD_GetCanvas(): Get current selected canvas layer + * + * For LCD drawing functions, refer to \ref lcdd_draw. + * + * For LCD string display, refer to \ref lcdd_font. + * + * @{ + * \defgroup lcdd_base LCD Driver General Operations + * @{ + * Implementation of LCD driver, Include LCD initialization, + * LCD on/off and LCD backlight control. + * + * \sa \ref lcdd_base_usage "LCD Driver General Usage" + * @} + * \defgroup lcdd_draw LCD Driver Simple Drawing + * @{ + * @} + * \defgroup lcdd_font LCD Driver Font Display + * @{ + * @} + * @} + */ + +#ifndef LCDD_H +#define LCDD_H +/** \addtogroup lcdd_base + * @{ + */ + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ + +/** \addtogroup lcdd_disp_id LCD display layers IDs + * @{ + */ +/** LCD controller ID, no display, configuration ONLY */ +#define LCDD_CONTROLLER 0 +/** LCD base layer, display fixed size image */ +#define LCDD_BASE 1 +/** LCD Overlay 1 */ +#define LCDD_OVR1 2 +/** LCD Overlay 2 */ +#define LCDD_OVR2 4 +/** LCD HighEndOverlay, support resize */ +#define LCDD_HEO 3 +/** LCD Cursor, max size 128x128 */ +#define LCDD_CUR 6 +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** LCD display layer information */ +typedef struct _LcddLayer { + void* pBuffer; /**< Display image buffer */ + uint16_t wImgW; /**< Display image width */ + uint16_t wImgH; /**< Display image height */ + uint8_t bMode; /**< Image bpp (16,24,32) for RGB mode */ + uint8_t bLayer; /**< Layer ID */ +} sLCDDLayer; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void LCDD_Initialize(void); + +extern void LCDD_On(void); +extern void LCDD_Off(void); +extern void LCDD_SetBacklight (uint32_t step); + +extern void LCDD_EnableLayer(uint8_t bLayer,uint8_t bEnDis); +extern uint8_t LCDD_IsLayerOn(uint8_t bLayer); +extern void LCDD_SetPosition(uint8_t bLayer,uint32_t x,uint32_t y); +extern void LCDD_SetPrioty(uint8_t bLayer,uint8_t bPri); +extern uint8_t LCDD_GetPrioty(uint8_t bLayer); +extern void LCDD_EnableAlpha(uint8_t bLayer,uint8_t bEnDisLA,uint8_t bEnDisGA); +extern void LCDD_SetAlpha(uint8_t bLayer, uint8_t bReverse, uint8_t bAlpha); +extern uint8_t LCDD_GetAlpha(uint8_t bLayer); +extern void LCDD_SetColorKeying(uint8_t bLayer, + uint8_t bDstSrc, + uint32_t dwColor,uint32_t dwMask); +extern void LCDD_DisableColorKeying(uint8_t bLayer); +extern void LCDD_SetCLUT(uint8_t bLayer, + uint32_t * pCLUT, + uint8_t bpp,uint8_t nbColors); + +extern void LCDD_Refresh(uint8_t bLayer); + +extern void *LCDD_ShowBMPRotated(uint8_t bLayer, + void * pBuffer,uint8_t bpp, + uint32_t x,uint32_t y,int32_t w,int32_t h, + uint32_t imgW,uint32_t imgH, + int16_t wRotate); +extern void *LCDD_ShowBMPScaled(uint8_t bLayer, + void * pBuffer,uint8_t bpp, + uint32_t x,uint32_t y,int32_t w,int32_t h, + uint32_t imgW,uint32_t imgH); +extern void *LCDD_ShowBMP(uint8_t bLayer, + void * pBuffer,uint8_t bpp, + uint32_t x,uint32_t y,int32_t w,int32_t h); + +extern void *LCDD_ShowBase(void * pBuffer, uint8_t bpp, uint8_t bScanBottomUp); +extern void LCDD_StopBase(void); + +extern void *LCDD_ShowOvr1(void * pBuffer, uint8_t bpp, + uint32_t x,uint32_t y,int32_t w,int32_t h); +extern void LCDD_StopOvr1(void); + +extern void *LCDD_ShowHeo(void * pBuffer, uint8_t bpp, + uint32_t x,uint32_t y,int32_t w,int32_t h, + uint32_t memW,uint32_t memH); +extern void LCDD_StopHeo(void); + +extern void *LCDD_ShowHcr(void * pBuffer, uint8_t bpp, + uint32_t x,uint32_t y,int32_t w,int32_t h); +extern void LCDD_StopHcr(void); + +extern sLCDDLayer *LCDD_GetCanvas(void); +extern uint8_t LCDD_SelectCanvas(uint8_t bLayer); +extern void *LCDD_CreateCanvas(uint8_t bLayer, + void * pBuffer,uint8_t bBPP, + uint16_t wX,uint16_t wY,uint16_t wW,uint16_t wH); +extern void LCDD_Flush_CurrentCanvas(void); +/** @}*/ +#endif /* #ifndef LCDD_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/led.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/led.h new file mode 100644 index 000000000..4f7da31a3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/led.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Small set of functions for simple and portable LED usage. + * + * \section Usage + * + * -# Configure one or more LEDs using LED_Configure and + * LED_ConfigureAll. + * -# Set, clear and toggle LEDs using LED_Set, LED_Clear and + * LED_Toggle. + * + * LEDs are numbered starting from 0; the number of LEDs depend on the + * board being used. All the functions defined here will compile properly + * regardless of whether the LED is defined or not; they will simply + * return 0 when a LED which does not exist is given as an argument. + * Also, these functions take into account how each LED is connected on to + * board; thus, \ref LED_Set might change the level on the corresponding pin + * to 0 or 1, but it will always light the LED on; same thing for the other + * methods. + */ + +#ifndef _LED_ +#define _LED_ + +#include + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +extern uint32_t LED_Configure( uint32_t dwLed ) ; + +extern uint32_t LED_Set( uint32_t dwLed ) ; + +extern uint32_t LED_Clear( uint32_t dwLed ) ; + +extern uint32_t LED_Toggle( uint32_t dwLed ) ; + +#endif /* #ifndef LED_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/macb.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/macb.h new file mode 100644 index 000000000..706df5a23 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/macb.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + +/** \addtogroup macb_module Ethernet MACB Driver + *@{ + * Implement EMAC PHY driver, that initialize the PHY to prepare for + * ethernet transfer. + * + * \section Usage + * -# EMAC related pins and Driver should be initialized at first. + * -# MAC address is set via EMAC_SetAddress(). + * -# Initialize MACB Driver instance by invoking MACB_Init(). + * -# Initialize PHY connected via MACB_InitPhy(), PHY address is + * automatically adjusted by attempt to read. + * -# Perform PHY auto negotiate through MACB_AutoNegotiate(), so + * connection established. + * -# Setup link speed by MACB_GetLinkSpeed() so link speed and + * duplex mode is desided. + * -# Now its time to send/receive ethernet packets via EMAC Driver + * - EMACD_Poll(): Polling received packets. + * - EMACD_Send(): Send a packet. + * + * \sa \ref emacd_module + * + * Related files:\n + * \ref macb.h\n + * \ref macb.c\n + * \ref mii.h.\n + * + * \defgroup eth_phy_mii MII/RMII Mode for PHY connection + * \defgroup macb_defines MACB Defines + * \defgroup macb_structs MACB Structs + * \defgroup macb_functions MACB Functions + */ +/**@}*/ + +#ifndef _MACB_H +#define _MACB_H + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup macb_defines + @{*/ + +/** The reset length setting for external reset configuration */ +#define MACB_RESET_LENGTH 0xD + +/** @}*/ +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ +/** \addtogroup macb_structs + @{*/ + +/** The DM9161 instance */ +typedef struct _Macb { + sEmacd *pEmacd; /**< Driver */ + uint32_t retryMax; /**< The retry & timeout settings */ + uint8_t phyAddress; /**< PHY address ( pre-defined by pins on reset ) */ + uint8_t speed; /**< 100M/10M speed */ + uint8_t fullDuplex; /**< Full duplex mode */ + uint8_t RMII; /**< RMII/MII mode */ +} Macb; + +/** @}*/ +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ +/** \addtogroup macb_functions + @{*/ + +extern void MACB_SetupTimeout(Macb *pMacb, uint32_t toMax); + +extern void MACB_Init(Macb *pMacb, sEmacd *pEmacd, uint8_t phyAddress); + +extern uint8_t MACB_InitPhy(Macb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pEmacPins, + uint32_t nbEmacPins); + +extern uint8_t MACB_FindValidPhy(Macb * pMacb,uint8_t addrStart); + +extern uint8_t MACB_ResetPhy(Macb * pMacb); + +extern uint8_t MACB_AutoNegotiate(Macb *pMacb, uint8_t rmiiMode); + +extern uint8_t MACB_GetLinkSpeed(Macb *pMacb, + uint8_t applySettings); + +extern void MACB_DumpRegisters(Macb * pMacb); + +/** @}*/ +#endif // #ifndef _MACB_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/math.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/math.h new file mode 100644 index 000000000..13d6bbf70 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/math.h @@ -0,0 +1,43 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef _MATH_ +#define _MATH_ + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +extern uint32_t min( uint32_t dwA, uint32_t dwB ) ; +extern uint32_t absv( int32_t lValue ) ; +extern uint32_t power( uint32_t dwX, uint32_t dwY ) ; + +#endif /* #ifndef _MATH_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/mcid.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/mcid.h new file mode 100644 index 000000000..d50f3dc24 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/mcid.h @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + +/** + * \ingroup sdmmc_hal + * \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib) + * + * \section Purpose + * + * This driver implements SD(IO)/MMC command operations and MCI configuration + * routines to perform SD(IO)/MMC access. It's used for upper layer + * (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations. + * + * \section Usage + * + * -# MCID_Init(): Initializes a MCI driver instance and the underlying + * peripheral. + * -# MCID_SendCmd(): Starts a MCI transfer which described by + * \ref sSdmmcCommand. + * -# MCID_CancelCmd(): Cancel a pending command. + * -# MCID_IsCmdCompleted(): Check if MCI transfer is finished. + * -# MCID_Handler(): Interrupt handler which is called by ISR handler. + * -# MCID_IOCtrl(): IO control function to report HW attributes to upper + * layer driver and modify HW settings (such as clock + * frequency, High-speed support, etc. See + * \ref sdmmc_ioctrls). + * + * \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI", + * \ref libsdmmc_module "SD/MMC Library" + * + * Related files:\n + * \ref mcid.h\n + * \ref mcid_dma.c.\n + */ + +#ifndef MCID_H +#define MCID_H +/** \addtogroup mcid_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/** \addtogroup mcid_defines MCI Driver Defines + * @{*/ + +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** MCI States */ +#define MCID_IDLE 0 /**< Idle */ +#define MCID_LOCKED 1 /**< Locked for specific slot */ +#define MCID_CMD 2 /**< Processing the command */ +#define MCID_ERROR 3 /**< Command error */ + +/** MCI Initialize clock 400K Hz */ +#define MCI_INITIAL_SPEED 400000 + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_structs MCI Driver Data Structs + * @{ + */ +#ifdef __cplusplus + extern "C" { +#endif + +/** + * \brief MCI Driver + */ +typedef struct _Mcid +{ + /** Pointer to a MCI peripheral. */ + Hsmci *pMciHw; + /** Pointer to a DMA driver */ + sDmad *pDmad; + /** Pointer to currently executing command. */ + void *pCmd; + /** MCK source, Hz */ + uint32_t dwMck; + /** DMA transfer channel */ + uint32_t dwDmaCh; + /** DMA transferred data index (bytes) */ + uint32_t dwXfrNdx; + /** DMA transfer size (bytes) */ + uint32_t dwXSize; + /** MCI peripheral identifier. */ + uint8_t bID; + /** Polling mode */ + uint8_t bPolling; + /** Reserved */ + uint8_t reserved; + /** state. */ + volatile uint8_t bState; +} sMcid; + +/** @}*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_functions MCI Driver Functions + @{*/ +extern void MCID_Init(sMcid * pMcid, + Hsmci * pMci, uint8_t bID, uint32_t dwMck, + sDmad * pDmad, + uint8_t bPolling); + +extern void MCID_Reset(sMcid * pMcid); + +extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot); + +extern uint32_t MCID_Release(sMcid * pMcid); + +extern void MCID_Handler(sMcid * pMcid); + +extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd); + +extern uint32_t MCID_CancelCmd(sMcid * pMcid); + +extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid); + +extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param); + +#ifdef __cplusplus +} +#endif +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/mii.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/mii.h new file mode 100644 index 000000000..787ef6e29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/mii.h @@ -0,0 +1,205 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MII_DEFINE_H +#define _MII_DEFINE_H +/** \addtogroup eth_phy_mii + @{*/ + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** \addtogroup mii_registers PHY registers Addresses + @{*/ +#define MII_BMCR 0 /**< Basic Mode Control Register */ +#define MII_BMSR 1 /**< Basic Mode Status Register */ +#define MII_PHYID1 2 /**< PHY Idendifier Register 1 */ +#define MII_PHYID2 3 /**< PHY Idendifier Register 2 */ +#define MII_ANAR 4 /**< Auto_Negotiation Advertisement Register */ +#define MII_ANLPAR 5 /**< Auto_negotiation Link Partner Ability Register */ +#define MII_ANER 6 /**< Auto-negotiation Expansion Register */ +#define MII_DSCR 16 /**< Specified Configuration Register */ +#define MII_DSCSR 17 /**< Specified Configuration and Status Register */ +#define MII_10BTCSR 18 /**< 10BASE-T Configuration and Satus Register */ +#define MII_PWDOR 19 /**< Power Down Control Register */ +#define MII_CONFIGR 20 /**< Specified config Register */ +#define MII_MDINTR 21 /**< Specified Interrupt Register */ +#define MII_RECR 22 /**< Specified Receive Error Counter Register */ +#define MII_DISCR 23 /**< Specified Disconnect Counter Register */ +#define MII_RLSR 24 /**< Hardware Reset Latch State Register */ +/** @}*/ + +/** \addtogroup phy_bmcr Basic Mode Control Register (BMCR, 0) + List Bit definitions: \ref MII_BMCR + @{*/ +#define MII_RESET (1ul << 15) /**< 1= Software Reset; 0=Normal Operation */ +#define MII_LOOPBACK (1ul << 14) /**< 1=loopback Enabled; 0=Normal Operation */ +#define MII_SPEED_SELECT (1ul << 13) /**< 1=100Mbps; 0=10Mbps */ +#define MII_AUTONEG (1ul << 12) /**< Auto-negotiation Enable */ +#define MII_POWER_DOWN (1ul << 11) /**< 1=Power down 0=Normal operation */ +#define MII_ISOLATE (1ul << 10) /**< 1 = Isolates 0 = Normal operation */ +#define MII_RESTART_AUTONEG (1ul << 9) /**< 1 = Restart auto-negotiation 0 = Normal operation */ +#define MII_DUPLEX_MODE (1ul << 8) /**< 1 = Full duplex operation 0 = Normal operation */ +#define MII_COLLISION_TEST (1ul << 7) /**< 1 = Collision test enabled 0 = Normal operation */ +/** Reserved bits: 6 to 0, Read as 0, ignore on write */ +/** @}*/ + +/** \addtogroup phy_bmsr Basic Mode Status Register (BMSR, 1) + List Bit definitions: \ref MII_BMSR + @{*/ +#define MII_100BASE_T4 (1ul << 15) /**< 100BASE-T4 Capable */ +#define MII_100BASE_TX_FD (1ul << 14) /**< 100BASE-TX Full Duplex Capable */ +#define MII_100BASE_T4_HD (1ul << 13) /**< 100BASE-TX Half Duplex Capable */ +#define MII_10BASE_T_FD (1ul << 12) /**< 10BASE-T Full Duplex Capable */ +#define MII_10BASE_T_HD (1ul << 11) /**< 10BASE-T Half Duplex Capable */ +/** Reserved bits: 10 to 7, Read as 0, ignore on write */ +#define MII_MF_PREAMB_SUPPR (1ul << 6) /**< MII Frame Preamble Suppression */ +#define MII_AUTONEG_COMP (1ul << 5) /**< Auto-negotiation Complete */ +#define MII_REMOTE_FAULT (1ul << 4) /**< Remote Fault */ +#define MII_AUTONEG_ABILITY (1ul << 3) /**< Auto Configuration Ability */ +#define MII_LINK_STATUS (1ul << 2) /**< Link Status */ +#define MII_JABBER_DETECT (1ul << 1) /**< Jabber Detect */ +#define MII_EXTEND_CAPAB (1ul << 0) /**< Extended Capability */ +/** @}*/ + +/** \addtogroup phy_id PHY ID Identifier Register (PHYID, 2,3) + List definitions: \ref MII_PHYID1, \ref MII_PHYID2 + @{*/ +#define MII_LSB_MASK 0x3F /**< Mask for PHY ID LSB */ + +#if defined(BOARD_EMAC_PHY_COMP_DM9161) +#define MII_OUI_MSB 0x0181 +#define MII_OUI_LSB 0x2E +//#define MII_PHYID1_OUI 0x606E // OUI: Organizationally Unique Identifier +//#define MII_ID 0x0181b8a0 +#elif defined(BOARD_EMAC_PHY_COMP_LAN8700) +#define MII_OUI_MSB 0x0007 +#define MII_OUI_LSB 0x30 +#elif defined(BOARD_EMAC_PHY_COMP_KSZ8051RNL) +#define MII_OUI_MSB 0x0022 +#define MII_OUI_LSB 0x05 +#else +#error no PHY Ethernet component defined ! +#endif +/** @}*/ + +/** \addtogroup phy_neg Auto-negotiation (ANAR, 4; ANLPAR, 5) + - Auto-negotiation Advertisement Register (ANAR) + - Auto-negotiation Link Partner Ability Register (ANLPAR) + Lists Bit definitions: \ref MII_ANAR, \ref MII_ANLPAR + @{*/ +#define MII_NP (1ul << 15) /**< Next page Indication */ +#define MII_ACK (1ul << 14) /**< Acknowledge */ +#define MII_RF (1ul << 13) /**< Remote Fault */ +/** Reserved: 12 to 11, Write as 0, ignore on read */ +#define MII_FCS (1ul << 10) /**< Flow Control Support */ +#define MII_T4 (1ul << 9) /**< 100BASE-T4 Support */ +#define MII_TX_FDX (1ul << 8) /**< 100BASE-TX Full Duplex Support */ +#define MII_TX_HDX (1ul << 7) /**< 100BASE-TX Support */ +#define MII_10_FDX (1ul << 6) /**< 10BASE-T Full Duplex Support */ +#define MII_10_HDX (1ul << 5) /**< 10BASE-T Support */ +/** Selector: 4 to 0, Protocol Selection Bits */ +#define MII_AN_IEEE_802_3 0x0001 +/** @}*/ + +/** \addtogroup phy_neg_exp Auto-negotiation Expansion Register (ANER, 6) + List Bit definitions: \ref MII_ANER + @{*/ +/** Reserved: 15 to 5, Read as 0, ignore on write */ +#define MII_PDF (1ul << 4) /**< Local Device Parallel Detection Fault */ +#define MII_LP_NP_ABLE (1ul << 3) /**< Link Partner Next Page Able */ +#define MII_NP_ABLE (1ul << 2) /**< Local Device Next Page Able */ +#define MII_PAGE_RX (1ul << 1) /**< New Page Received */ +#define MII_LP_AN_ABLE (1ul << 0) /**< Link Partner Auto-negotiation Able */ +/** @}*/ + +/** \addtogroup phy_dscr Specified Configuration Register (DSCR, 16) + List Bit definitions: \ref MII_DSCR + @{*/ +#define MII_BP4B5B (1ul << 15) /**< Bypass 4B5B Encoding and 5B4B Decoding */ +#define MII_BP_SCR (1ul << 14) /**< Bypass Scrambler/Descrambler Function */ +#define MII_BP_ALIGN (1ul << 13) /**< Bypass Symbol Alignment Function */ +#define MII_BP_ADPOK (1ul << 12) /**< BYPASS ADPOK */ +#define MII_REPEATER (1ul << 11) /**< Repeater/Node Mode */ +#define MII_TX (1ul << 10) /**< 100BASE-TX Mode Control */ +#define MII_FEF (1ul << 9) /**< Far end Fault enable */ +#define MII_RMII_ENABLE (1ul << 8) /**< Reduced MII Enable */ +#define MII_F_LINK_100 (1ul << 7) /**< Force Good Link in 100Mbps */ +#define MII_SPLED_CTL (1ul << 6) /**< Speed LED Disable */ +#define MII_COLLED_CTL (1ul << 5) /**< Collision LED Enable */ +#define MII_RPDCTR_EN (1ul << 4) /**< Reduced Power Down Control Enable */ +#define MII_SM_RST (1ul << 3) /**< Reset State Machine */ +#define MII_MFP_SC (1ul << 2) /**< MF Preamble Suppression Control */ +#define MII_SLEEP (1ul << 1) /**< Sleep Mode */ +#define MII_RLOUT (1ul << 0) /**< Remote Loopout Control */ +/** @}*/ + +/** \addtogroup phy_dscsr Specified Configuration and Status Register (DSCSR, 17) + List Bit definitions: \ref MII_DSCSR + @{*/ +#define MII_100FDX (1ul << 15) /**< 100M Full Duplex Operation Mode */ +#define MII_100HDX (1ul << 14) /**< 100M Half Duplex Operation Mode */ +#define MII_10FDX (1ul << 13) /**< 10M Full Duplex Operation Mode */ +#define MII_10HDX (1ul << 12) /**< 10M Half Duplex Operation Mode */ +/** @}*/ + +/** \addtogroup phy_10btcsr 10BASE-T Configuration/Status (10BTCSR, 18) + List Bit definitions: \ref MII_10BTCSR + @{*/ +/** Reserved: 18 to 15, Read as 0, ignore on write */ +#define MII_LP_EN (1ul << 14) /**< Link Pulse Enable */ +#define MII_HBE (1ul << 13) /**< Heartbeat Enable */ +#define MII_SQUELCH (1ul << 12) /**< Squelch Enable */ +#define MII_JABEN (1ul << 11) /**< Jabber Enable */ +#define MII_10BT_SER (1ul << 10) /**< 10BASE-T GPSI Mode */ +/** Reserved: 9 to 1, Read as 0, ignore on write */ +#define MII_POLR (1ul << 0) /**< Polarity Reversed */ +/** @}*/ + +/** \addtogroup phy_mdintr Specified Interrupt Register (MDINTR, 21) + List Bit definitions: \ref MII_MDINTR + @{*/ +#define MII_INTR_PEND (1ul << 15) /**< Interrupt Pending */ +/** Reserved: 14 to 12, Reserved */ +#define MII_FDX_MASK (1ul << 11) /**< Full-duplex Interrupt Mask */ +#define MII_SPD_MASK (1ul << 10) /**< Speed Interrupt Mask */ +#define MII_LINK_MASK (1ul << 9) /**< Link Interrupt Mask */ +#define MII_INTR_MASK (1ul << 8) /**< Master Interrupt Mask */ +/** Reserved: 7 to 5, Reserved */ +#define MII_FDX_CHANGE (1ul << 4) /**< Duplex Status Change Interrupt */ +#define MII_SPD_CHANGE (1ul << 3) /**< Speed Status Change Interrupt */ +#define MII_LINK_CHANGE (1ul << 2) /**< Link Status Change Interrupt */ +/** Reserved: 1, Reserved */ +#define MII_INTR_STATUS (1ul << 0) /**< Interrupt Status */ +/** @}*/ + +/**@}*/ +#endif // #ifndef _MII_DEFINE_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/omnivision.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/omnivision.h new file mode 100644 index 000000000..3ea99ce99 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/omnivision.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef OMNIVISION_H +#define OMNIVISION_H + + +/*--------------------------------------------------------------------------- + * TYPE + *---------------------------------------------------------------------------*/ +/** define a structure for ovxxxx register initialization values */ +struct ov_reg +{ + /* Register to be written */ + uint16_t reg; + /* Value to be written in the register */ + uint8_t val; +}; + + +/*--------------------------------------------------------------------------- + * DEFINITAION + *---------------------------------------------------------------------------*/ +#define OV_2640 0x00 +#define OV_2643 0x01 +#define OV_5640 0x02 +#define OV_7740 0x03 +#define OV_9740 0x04 +#define OV_UNKNOWN 0xFF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint8_t ov_init(Twid *pTwid); +extern void ov_DumpRegisters8(Twid *pTwid); +extern void ov_DumpRegisters16(Twid *pTwid); +extern uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist); +extern uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist); +extern uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData); +extern uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData); +extern uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val); +extern uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val); +extern void isOV5640_AF_InitDone(Twid *pTwid); +extern uint32_t ov_5640_AF_single(Twid *pTwid); +extern uint32_t ov_5640_AF_continue(Twid *pTwid); +extern uint32_t ov_5640_AFPause(Twid *pTwid); +extern uint32_t ov_5640_AFrelease(Twid *pTwid); + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ov.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ov.h new file mode 100644 index 000000000..929039cc3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ov.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef OV_H +#define OV_H + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** Captor capture size */ +struct capture_size { + uint32_t width; + uint32_t height; +}; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ov_configure(Twid *pTwid, uint8_t type, uint32_t width, uint32_t heigth); +extern void ov_5640Afc_Firmware(Twid *pTwid); +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ovyuv.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ovyuv.h new file mode 100644 index 000000000..7bcca6d84 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/ovyuv.h @@ -0,0 +1,57 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _YUV_H_ +#define _YUV_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Exported variable + *---------------------------------------------------------------------------*/ +extern const struct ov_reg ov2640_yuv_vga[]; + +extern const struct ov_reg ov2643_yuv_vga[]; +extern const struct ov_reg ov2643_yuv_swvga[]; +extern const struct ov_reg ov2643_yuv_uxga[]; + +extern const struct ov_reg ov5640_yuv_vga[]; +extern const struct ov_reg ov5640_yuv_sxga[]; +extern const struct ov_reg ov5640_afc[]; + +extern const struct ov_reg ov7740_yuv_vga[]; +extern const struct ov_reg ov9740_yuv_sxga[]; +extern const struct ov_reg ov9740_yuv_vga[]; + +#endif // #ifndef _YUV_H_ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/qt1070.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/qt1070.h new file mode 100644 index 000000000..c0671df0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/qt1070.h @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Implementation QT1070 driver. + * + */ + +#ifndef QT1070_H +#define QT1070_H + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** Slave address */ +#define QT1070_SLAVE_ADDRESS 0x1B + +/** Internal Register Address Allocation */ + +/** Chip ID register*/ +#define QT1070_CHIP_ID 0 +/** Firmware version register*/ +#define QT1070_REG_FIRMWARE_VERSION 1 +/** Detection status*/ +#define QT1070_REG_DETECTION_STATUS 2 +/** Key status*/ +#define QT1070_REG_KEY_STATUS 3 +/** Key signal */ +#define QT1070_REG_KEY0_SIGNAL_MSB 4 +#define QT1070_REG_KEY0_SIGNAL_LSB 5 +#define QT1070_REG_KEY1_SIGNAL_MSB 6 +#define QT1070_REG_KEY1_SIGNAL_LSB 7 +#define QT1070_REG_KEY2_SIGNAL_MSB 8 +#define QT1070_REG_KEY2_SIGNAL_LSB 9 +#define QT1070_REG_KEY3_SIGNAL_MSB 10 +#define QT1070_REG_KEY3_SIGNAL_LSB 11 +#define QT1070_REG_KEY4_SIGNAL_MSB 12 +#define QT1070_REG_KEY4_SIGNAL_LSB 13 +#define QT1070_REG_KEY5_SIGNAL_MSB 14 +#define QT1070_REG_KEY5_SIGNAL_LSB 15 +#define QT1070_REG_KEY6_SIGNAL_MSB 16 +#define QT1070_REG_KEY6_SIGNAL_LSB 17 + +/** Reference date */ +#define QT1070_REG_REFDATA0_MSB 18 +#define QT1070_REG_REFDATA0_LSB 19 +#define QT1070_REG_REFDATA1_MSB 20 +#define QT1070_REG_REFDATA1_LSB 21 +#define QT1070_REG_REFDATA2_MSB 22 +#define QT1070_REG_REG_REFDATA2_LSB 23 +#define QT1070_REG_REFDATA3_MSB 24 +#define QT1070_REG_REG_REFDATA3_LSB 25 +#define QT1070_REG_REFDATA4_MSB 26 +#define QT1070_REG_REFDATA4_LSB 27 +#define QT1070_REG_REFDATA5_MSB 28 +#define QT1070_REG_REFDATA5_LSB 29 +#define QT1070_REG_REFDATA6_MSB 30 +#define QT1070_REG_REFDATA6_LSB 31 + +/** Negative threshold level */ +#define QT1070_REG_NTHR_KEY0 32 +#define QT1070_REG_NTHR_KEY1 33 +#define QT1070_REG_NTHR_KEY2 34 +#define QT1070_REG_NTHR_KEY3 35 +#define QT1070_REG_NTHR_KEY4 36 +#define QT1070_REG_NTHR_KEY5 37 +#define QT1070_REG_NTHR_KEY6 38 + +/** Adjacent key suppression level */ +#define QT1070_REG_AVEAKS_KEY0 39 +#define QT1070_REG_AVEAKS_KEY1 40 +#define QT1070_REG_AVEAKS_KEY2 41 +#define QT1070_REG_AVEAKS_KEY3 42 +#define QT1070_REG_AVEAKS_KEY4 43 +#define QT1070_REG_AVEAKS_KEY5 44 +#define QT1070_REG_AVEAKS_KEY6 45 + +/** Detection interator conter for key*/ +#define QT1070_REG_DI_KEY0 46 +#define QT1070_REG_DI_KEY1 47 +#define QT1070_REG_DI_KEY2 48 +#define QT1070_REG_DI_KEY3 49 +#define QT1070_REG_DI_KEY4 50 +#define QT1070_REG_DI_KEY5 51 +#define QT1070_REG_DI_KEY6 52 + +/** Low power mode */ +#define QT1070_REG_LOWPOWER_MODE 54 +/** Maximum on duration */ +#define QT1070_REG_MAX_DURATION 55 +/** Calibrate */ +#define QT1070_REG_CALIRATE 56 +/** Reset */ +#define QT1070_REG_RESET 57 + +/** Detection Status. */ +/** This bit is set during a calibration sequence.*/ +#define QT_CALIBRATE_BIT 7 +/** This bit is set if the time to acquire all key signals exceeds 8 ms*/ +#define QT_OVERFLOW_BIT 6 +/** This bit is set if Comms mode is enabled. */ +#define QT_COMMSENABLED_BIT 5 +/** This bit is set if any keys are in detect. */ +#define QT_TOUCH_BIT 0 + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t QT1070_GetChipId(Twid *pTwid); +extern uint8_t QT1070_GetFirmwareVersion(Twid *pTwid); +extern uint8_t QT1070_GetDetection_Status(Twid *pTwid); +extern uint8_t QT1070_GetKey_Status(Twid *pTwid); +extern uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key); +extern uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key); +extern void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold); +extern void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks); +extern void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di); +extern void QT1070_StartCalibrate(Twid *pTwid); +extern void QT1070_StartReset(Twid *pTwid); +#endif // QT1070_H + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/rand.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/rand.h new file mode 100644 index 000000000..f58ff8af6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/rand.h @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * \file + * + * \section Purpose + * Small function for gererating random number. + * + *------------------------------------------------------------------------------*/ + +#ifndef _RAND_ +#define _RAND_ + +/*------------------------------------------------------------------------------ + * Global Functions + *------------------------------------------------------------------------------*/ + +extern void srand( uint32_t dwSeed ) ; +extern uint32_t rand( void ) ; + +#endif /* #ifndef _RAND_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/syscalls.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/syscalls.h new file mode 100644 index 000000000..10e81a373 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/syscalls.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file syscalls.h + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern caddr_t _sbrk ( int incr ) ; + +extern int link( char *old, char *new ) ; + +extern int _close( int file ) ; + +extern int _fstat( int file, struct stat *st ) ; + +extern int _isatty( int file ) ; + +extern int _lseek( int file, int ptr, int dir ) ; + +extern int _read(int file, char *ptr, int len) ; + +extern int _write( int file, char *ptr, int len ) ; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/timetick.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/timetick.h new file mode 100644 index 000000000..fdeb9beac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/timetick.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Methods and definitions for Global time tick and wait functions. + * + * Defines a common and simpliest use of Time Tick, to increase tickCount + * every 1ms, the application can get this value through GetTickCount(). + * + * \par Usage + * + * -# Configure the System Tick with TimeTick_Configure() when MCK changed + * \note + * Must be done before any invoke of GetTickCount(), Wait() or Sleep(). + * -# Uses GetTickCount to get current tick value. + * -# Uses Wait to wait several ms. + * -# Uses Sleep to enter wait for interrupt mode to wait several ms. + * + */ + +#ifndef _TIMETICK_ +#define _TIMETICK_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ; + +extern void TimeTick_Increment( uint32_t dwInc ) ; + +extern uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick); + +extern uint32_t GetTickCount( void ) ; + +extern void Wait( volatile uint32_t dwMs ) ; + +extern void Sleep( volatile uint32_t dwMs ) ; + +#endif /* _TIMETICK_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/tsd.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/tsd.h new file mode 100644 index 000000000..77d2ad912 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/tsd.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** + * \addtogroup tsd_module TouchScreen Driver + * + * \section Purpose + * + * This unit provides a very powerful touchscreen driver which handles all the + * complexity. This includes touchscreen calibration, retrieving measurements, + * configuring the TSADC, etc. + * + * \section Usage + * + * -# Implement ADC interrupt handler in application, to invoke TSD_Handler() + * to handle ADC sampling events for touchscreen monitor. + * -# Call TSD_Initialize() to initialize ADC used for touchscreen. + * -# Call TSD_Calibrate() to do touchscreen calibration with LCD, and enable + * touchscreen monitor if calibration success. + * -# Call TSD_Enable() to enable or disable touchscreen monitoring. + * -# Declare a global TSD_PenPressed() function anywhere in your code. This + * function will get called every time the pen is pressed on the screen. + * -# Declare a global TSD_PenMoved() function, which will get called whenever + * the pen stays in contact with the screen but changes position. + * -# Declare a global TSD_PenReleased() function, which will be invoked as the + * pen is lifted from the screen. + */ + +#ifndef TSD_H +#define TSD_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +extern void TSD_Handler(uint32_t dwAdcStatus); +extern void TSD_Initialize(void); +extern void TSD_DeInitialize(void); +extern void TSD_Enable(uint8_t bEnDis); +extern uint8_t TSD_Calibrate(void); + +/* calibration used functions */ +extern void TSD_GetRawMeasurement(uint32_t * pData); +extern void TSD_WaitPenPressed(void); +extern void TSD_WaitPenReleased(void); + +/* callbacks */ +extern void TSD_PenPressed(uint32_t x, uint32_t y, uint32_t pressure); +extern void TSD_PenMoved(uint32_t x, uint32_t y, uint32_t pressure); +extern void TSD_PenReleased(uint32_t x, uint32_t y); + +#endif //#ifndef TSD_H diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/tsd_com.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/tsd_com.h new file mode 100644 index 000000000..2869c1b69 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/tsd_com.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +#ifndef TSD_COM_H +#define TSD_COM_H + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +extern void TSDCom_InterpolateMeasurement( + const uint32_t *pData, + uint32_t *pPoint); + +uint8_t TSDCom_Calibrate(void); + +uint8_t TSDCom_IsCalibrationOk(void); + +void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size); +void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size); + +#endif /* #ifndef TSD_COM_H */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/wav.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/wav.h new file mode 100644 index 000000000..be75b9157 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/wav.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef WAV_H +#define WAV_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +/* Standard WAV file header information. */ +typedef struct _WavHeader +{ + /* Contains the letters "RIFF" in ASCII form. */ + unsigned int chunkID; + /* Size of the rest of the chunk following this number.*/ + unsigned int chunkSize; + /* Contains the letters "WAVE".*/ + unsigned int format; + /* Contains the letters "fmt ".*/ + unsigned int subchunk1ID; + /* 16 for PCM. This is the size of the rest of the Subchunk which follows this number.*/ + unsigned int subchunk1Size; + /* PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some form of compression.*/ + unsigned short audioFormat; + /* Mono = 1, Stereo = 2, etc.*/ + unsigned short numChannels; + /* 8000, 44100, etc.*/ + unsigned int sampleRate; + /* SampleRate * NumChannels * BitsPerSample/8*/ + unsigned int byteRate; + /* NumChannels * BitsPerSample/8*/ + unsigned short blockAlign; + /* 8 bits = 8, 16 bits = 16, etc.*/ + unsigned short bitsPerSample; + /* Contains the letters "data".*/ + unsigned int subchunk2ID; + /* Number of bytes in the data.*/ + unsigned int subchunk2Size; + +} WavHeader; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern unsigned char WAV_IsValid(const WavHeader *header); + +extern void WAV_DisplayInfo(const WavHeader *header); + +#endif //#ifndef WAV_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/wm8904.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/wm8904.h new file mode 100644 index 000000000..e2c4dac78 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/include/wm8904.h @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +#ifndef WM8904_H +#define WM8904_H + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define WM8904_CSB_STATE (0x0 << 0) + +/** Slave address */ +#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE + + +/** Reset register*/ +#define WM8904_REG_RESET 0x00 + +/** Bias control 0 register*/ +#define WM8904_REG_BIAS_CTRL0 0x04 + +/** VMID control 0 register*/ +#define WM8904_REG_VMID_CTRL0 0x05 + +/** MIC Bias control 0 register*/ +#define WM8904_REG_MICBIAS_CTRL0 0x06 + +/** Bias control 1 register*/ +#define WM8904_REG_BIAS_CTRL1 0x07 + +/** Power management control 0 register*/ +#define WM8904_REG_POWER_MANG0 0x0C +/** Power management control 2 register*/ +#define WM8904_REG_POWER_MANG2 0x0E +/** Power management control 3 register*/ +#define WM8904_REG_POWER_MANG3 0x0F +/** Power management control 6 register*/ +#define WM8904_REG_POWER_MANG6 0x12 + +/** Clock rate0 register*/ +#define WM8904_REG_CLOCK_RATE0 0x14 +/** Clock rate1 register*/ +#define WM8904_REG_CLOCK_RATE1 0x15 + +/** Clock rate2 register*/ +#define WM8904_REG_CLOCK_RATE2 0x16 + +/** Audio interface0 register*/ +#define WM8904_REG_AUD_INF0 0x18 + +/** Audio interface1 register*/ +#define WM8904_REG_AUD_INF1 0x19 +/** Audio interface2 register*/ +#define WM8904_REG_AUD_INF2 0x1A +/** Audio interface3 register*/ +#define WM8904_REG_AUD_INF3 0x1B + +/** ADC digital 0 register*/ +#define WM8904_REG_ADC_DIG0 0x20 +/** ADC digital 1 register*/ +#define WM8904_REG_ADC_DIG1 0x21 + +/** Analogue left input 0 register*/ +#define WM8904_REG_ANALOGUE_LIN0 0x2C +/** Analogue right input 0 register*/ +#define WM8904_REG_ANALOGUE_RIN0 0x2D + +/** Analogue left input 1 register*/ +#define WM8904_REG_ANALOGUE_LIN1 0x2E +/** Analogue right input 1 register*/ +#define WM8904_REG_ANALOGUE_RIN1 0x2F + +/** Analogue left output 1 register*/ +#define WM8904_REG_ANALOGUE_LOUT1 0x39 +/** Analogue right output 1 register*/ +#define WM8904_REG_ANALOGUE_ROUT1 0x3A + +/** Analogue left output 2 register*/ +#define WM8904_REG_ANALOGUE_LOUT2 0x3B +/** Analogue right output 2 register*/ +#define WM8904_REG_ANALOGUE_ROUT2 0x3C + +/** Analogue output 12 ZC register*/ +#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D + +/** DC servo 0 register*/ +#define WM8904_REG_DC_SERVO0 0x43 + +/** Analogue HP 0 register*/ +#define WM8904_REG_ANALOGUE_HP0 0x5A + +/** Charge pump 0 register*/ +#define WM8904_REG_CHARGE_PUMP0 0x62 + +/** Class W 0 register*/ +#define WM8904_REG_CLASS0 0x68 + +/** FLL control 1 register*/ +#define WM8904_REG_FLL_CRTL1 0x74 +/** FLL control 2 register*/ +#define WM8904_REG_FLL_CRTL2 0x75 +/** FLL control 3 register*/ +#define WM8904_REG_FLL_CRTL3 0x76 +/** FLL control 4 register*/ +#define WM8904_REG_FLL_CRTL4 0x77 +/** FLL control 5 register*/ +#define WM8904_REG_FLL_CRTL5 0x78 + +/** DUMMY register*/ +#define WM8904_REG_END 0xFF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr); +extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, uint16_t data); +extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device ); +extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value); +extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device); +#endif // WM8904_H + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-ddram.mac b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-ddram.mac new file mode 100644 index 000000000..7344e06e7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-ddram.mac @@ -0,0 +1,547 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: sama5d3x-ek-ddram.mac +// User setup file for CSPY debugger. +// +// --------------------------------------------------------- + +__var __tempo_var; +__var __dummy_read; +__var __data_test; +__var __mac_i; + +__var REG_CKGR_MOR; +__var CKGR_MOR_MOSCXTEN; +__var CKGR_MOR_MOSCXTBY; +__var CKGR_MOR_MOSCRCEN; +__var CKGR_MOR_MOSCSEL; +__var REG_CKGR_MCFR; +__var CKGR_MCFR_MAINFRDY; +__var REG_PMC_SR; +__var PMC_SR_MCKRDY; +__var PMC_SR_LOCKA; +__var PMC_PCK_CSS_MAIN_CLK; +__var REG_CKGR_PLLAR; +__var REG_PMC_PLLICPR; +__var REG_PMC_MCKR; +__var PMC_MCKR_PLLADIV2_DIV2; +__var PMC_MCKR_PRES_Msk; +__var PMC_MCKR_PRES_CLOCK; +__var PMC_MCKR_MDIV_Msk; +__var PMC_MCKR_MDIV_PCK_DIV3; +__var PMC_MCKR_CSS_PLLA_CLK; +__var PMC_SR_MOSCSELS; + +/********************************************************************* +* +* execUserReset() : JTAG set initially to Full Speed +*/ +execUserReset() +{ + __message "------------------------------ execUserReset ---------------------------------"; + CheckNoRemap(); + __message "-------------------------------Set PC Reset ----------------------------------"; + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR +} + +/********************************************************************* +* +* execUserPreload() : JTAG set initially to 32kHz +*/ +execUserPreload() +{ + __message "------------------------------ execUserPreload ---------------------------------"; + __hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) + + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR + // DDR reset + //MPDDRC->MPDDRC_LPR = MPDDRC_LPR_LPCB_DEEP_PWD |MPDDRC_LPR_CLK_FR_ENABLED; + __writeMemory32(0x07,0xFFFFEA1C,"Memory"); + // Disable DDR clock + //PMC->PMC_PCDR1 |= (1 << (ID_MPDDRC-32)); + __tempo_var = __readMemory32(0xFFFFFD08,"Memory"); + __tempo_var |= 0x00020000; + __writeMemory32(__tempo_var,0xFFFFFD04,"Memory"); // Enable MPDDR controller clock + + // PMC->PMC_SCDR |= PMC_SCER_DDRCK; + __tempo_var = __readMemory32(0xFFFFFC08,"Memory"); + __tempo_var |= 0x00000084; + __writeMemory32(__tempo_var,0xFFFFFC04,"Memory"); // System Clock Enable Register : Enable DDR clock + + + + + PMC_SelectExt12M_Osc(); + PMC_SwitchMck2Main(); + PMC_SetPllA(); + PMC_SetMckPllaDiv(); + PMC_SetMckPrescaler(); + PMC_SetMckDivider(); + PMC_SwitchMck2Pll(); + __message "------------ PLL set to 792 MHz, MCK set to 132 MHz ------------"; + +//#define DDRAM_MT47H64M16HR 0 +//#define DDRAM_MT47H128M16RT 1 +//#define BOARD_DDRAM_TYPE DDRAM_MT47H128M16RT + + __initDDR2(1); //* Init DDR2 memory + __message "------------ DDR2 is initialized ------------"; + + CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000 + Watchdog(); //* Watchdog Disable + + //* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + __mac_i=__readMemory32(0xFFFFEE40,"Memory"); + __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; +} + + +/********************************************************************* +* +* CheckRemap() +* +* Function description +* Check the Remap. +*/ + +CheckNoRemap() +{ + __tempo_var = __readMemory32(0x00000000,"Memory"); + + if (__tempo_var == 0xAA55AA55) + { + __data_test = 0x55AA55AA; + } + else + { + __data_test = 0xAA55AA55; + } + + __writeMemory32(__data_test,0x00000000,"Memory"); + + __dummy_read = __readMemory32(0x00000000,"Memory"); + + __writeMemory32(__tempo_var,0x00000000,"Memory"); + + if (__dummy_read == __data_test) + { + __message " ------------------------ The Remap is already done ------------------------"; + } + else + { + __message " ------------------------ The Remap is not DONE ------------------------"; + __writeMemory32(0x00000001,0xFFFFED00,"Memory"); + __delay(2); + __writeMemory32(0x00000001,0x00800000,"Memory"); + __delay(50); + __message "------------ The Remap was executed ------------"; + } +} + +/********************************************************************* +* +* _Watchdog() +* +* Function description +* Clear Watchdog +*/ + +Watchdog() +{ + // Watchdog Disable + __writeMemory32(0x00008000,0xFFFFFE44,"Memory"); + __message " ------------------------ Watchdog Disable ------------------------"; +} + +/********************************************************************* +* +* PMC_SelectExt12M_Osc() +* +* Function description +* Select external 12MHz oscillator +*/ +PMC_SelectExt12M_Osc() +{ + REG_CKGR_MOR = 0xFFFFFC20; + CKGR_MOR_MOSCXTEN = (0x1 << 0); /*(CKGR_MOR) Main Crystal Oscillator Enable */ + CKGR_MOR_MOSCXTBY = (0x1 << 1); /*(CKGR_MOR) Main Crystal Oscillator Bypass */ + CKGR_MOR_MOSCRCEN = (0x1 << 3); /*(CKGR_MOR) Main On-Chip RC Oscillator Enable */ + CKGR_MOR_MOSCSEL = (0x1 << 24); /*(CKGR_MOR) Main Oscillator Selection */ + REG_CKGR_MCFR = 0xFFFFFC24; /*(PMC) Main Clock Frequency Register */ + CKGR_MCFR_MAINFRDY = (0x1 << 16); /*(CKGR_MCFR) Main Clock Ready */ + REG_PMC_SR = 0xFFFFFC68; /*(PMC) Status Register */ + PMC_SR_MOSCSELS = (0x1 << 16); /*(PMC_SR) Main Oscillator Selection Status */ + PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */ + + /* enable external OSC 12 MHz */ + __tempo_var = __readMemory32(REG_CKGR_MOR,"Memory"); + __tempo_var |= CKGR_MOR_MOSCXTEN | (0x37 << 16); + __writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory"); + + /* wait Main CLK Ready */ + while(!((__readMemory32(REG_CKGR_MCFR,"Memory")) & CKGR_MCFR_MAINFRDY)); + + /* disable external OSC 12 MHz bypass */ + __tempo_var = __readMemory32(REG_CKGR_MOR,"Memory"); + __tempo_var = (__tempo_var & ~CKGR_MOR_MOSCXTBY) | (0x37 << 16); + __writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory"); + + /* switch MAIN clock to external OSC 12 MHz*/ + __tempo_var = __readMemory32(REG_CKGR_MOR,"Memory"); + __tempo_var |= CKGR_MOR_MOSCSEL | (0x37 << 16); + __writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory"); + + /* wait MAIN clock status change for external OSC 12 MHz selection*/ + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MOSCSELS)); + + /* in case when MCK is running on MAIN CLK */ + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY)); + + /* disable internal RC 12 MHz*/ + //__tempo_var = __readMemory32(REG_CKGR_MOR,"Memory"); + //__tempo_var = (__tempo_var & ~CKGR_MOR_MOSCRCEN) | (0x37 << 16); + //__writeMemory32(__tempo_var,REG_CKGR_MOR,"Memory"); + //__mac_i=__readMemory32(REG_CKGR_MOR,"Memory"); + __message " -------- PMC_SelectExt12M_Osc ---------- REG_CKGR_MOR 0x",__mac_i:%X; +} + +/********************************************************************* +* +* PMC_SwitchMck2Main() +* +* Function description +* Switch PMC from MCK to main clock. +*/ +PMC_SwitchMck2Main() +{ + REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */ + PMC_PCK_CSS_MAIN_CLK = (0x1 << 0); /*(PMC_PCK[3]) Main Clock is selected */ + PMC_SR_MCKRDY = (0x1 << 3); /*(PMC_SR) Master Clock Status */ + REG_PMC_SR = 0xFFFFFC68; /*(PMC) Status Register */ + + /* Select Main Oscillator as input clock for PCK and MCK */ + __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory"); + __tempo_var = (__tempo_var & ~0x03)| PMC_PCK_CSS_MAIN_CLK ; + __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory"); + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY)); + __mac_i=__readMemory32(REG_PMC_MCKR,"Memory"); + __message " --------- PMC_SwitchMck2Main ----------- REG_PMC_MCKR 0x",__mac_i:%X; +} + +/********************************************************************* +* +* PMC_SetPllA() +* +* Function description +* Configure PLLA Registe. +*/ + +PMC_SetPllA() +{ + REG_CKGR_PLLAR = 0xFFFFFC28; /*(PMC) PLLA Register */ + REG_PMC_PLLICPR = 0xFFFFFC80; /*(PMC) PLL Charge Pump Current Register */ + REG_PMC_SR = 0xFFFFFC68; /*(PMC) Status Register */ + PMC_SR_LOCKA = (0x1 << 1); /*(PMC_SR) PLLA Lock Status */ + + __writeMemory32(((0x1 << 29) | (0x3F << 8) | ( 0 << 14) | (65 << 18) | 1 ), REG_CKGR_PLLAR,"Memory"); + __writeMemory32((0x03<<8), REG_PMC_PLLICPR,"Memory"); + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_LOCKA)); + __mac_i=__readMemory32(REG_CKGR_PLLAR,"Memory"); + __message " --------- PMC_SetPllA ---------------- REG_CKGR_PLLAR 0x",__mac_i:%X; +} + +/********************************************************************* +* +* PMC_SetMckPllaDiv() +* +* Function description +* Configure MCK PLLA divider. +*/ +PMC_SetMckPllaDiv() +{ + REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */ + PMC_MCKR_PLLADIV2_DIV2 = (0x1 << 12); /*(PMC_MCKR) PLLA clock frequency is divided by 2. */ + + __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory"); + if ((__tempo_var & PMC_MCKR_PLLADIV2_DIV2) != PMC_MCKR_PLLADIV2_DIV2) + { + __tempo_var |= PMC_MCKR_PLLADIV2_DIV2; + __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory"); + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY)); + } +} + +/********************************************************************* +* +* PMC_SetMckPrescaler() +* +* Function description +* Configure MCK Prescaler. +*/ +PMC_SetMckPrescaler() +{ + REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */ + PMC_MCKR_PRES_Msk = (0x7 << 4); /*(PMC_MCKR) Master/Processor Clock Prescaler */ + PMC_MCKR_PRES_CLOCK = (0x0 << 4); /*(PMC_MCKR) Selected clock */ + + /* Change MCK Prescaler divider in PMC_MCKR register */ + __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory"); + __tempo_var = (__tempo_var & ~PMC_MCKR_PRES_Msk) | PMC_MCKR_PRES_CLOCK; + __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory"); + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY)); + __mac_i=__readMemory32(REG_PMC_MCKR,"Memory"); + __message " --------- PMC_SetMckPrescaler -------------- REG_PMC_MCKR 0x",__mac_i:%X; +} + +/********************************************************************* +* +* PMC_SetMckDivider() +* +* Function description +* Configure MCK Divider. +*/ +PMC_SetMckDivider() +{ + REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */ + PMC_MCKR_MDIV_Msk = (0x3 << 8); /*(PMC_MCKR) Master Clock Division */ + PMC_MCKR_MDIV_PCK_DIV3 = (0x3 << 8); /*(PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */ + + /* change MCK Prescaler divider in PMC_MCKR register */ + __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory"); + __tempo_var = (__tempo_var & ~PMC_MCKR_MDIV_Msk) | PMC_MCKR_MDIV_PCK_DIV3; + __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory"); + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY)); + __mac_i=__readMemory32(REG_PMC_MCKR,"Memory"); + __message " --------- PMC_SetMckDivider -------------- REG_PMC_MCKR 0x",__mac_i:%X; +} + +/********************************************************************* +* +* PMC_SwitchMck2Pll() +* +* Function description +* Switch PMC from MCK to PLL clock. +*/ +PMC_SwitchMck2Pll() +{ + REG_PMC_MCKR = 0xFFFFFC30; /*(PMC) Master Clock Register */ + PMC_MCKR_CSS_PLLA_CLK = (0x2 << 0); /*(PMC_MCKR) PLLACK/PLLADIV2 is selected */ + + /* Select PLL as input clock for PCK and MCK */ + __tempo_var = __readMemory32(REG_PMC_MCKR,"Memory"); + __tempo_var = (__tempo_var & ~0x03) | PMC_MCKR_CSS_PLLA_CLK; + __writeMemory32(__tempo_var, REG_PMC_MCKR,"Memory"); + while(!((__readMemory32(REG_PMC_SR,"Memory")) & PMC_SR_MCKRDY)); + __mac_i=__readMemory32(REG_PMC_MCKR,"Memory"); + __message " --------- PMC_SwitchMck2Pll -------------- REG_PMC_MCKR 0x",__mac_i:%X; +} + + + +// --------------------------------------------------------------------------- +// Function Name : __initDDR2 +// Object : Set DDR2 memory for working at 133 Mhz +// --------------------------------------------------------------------------- + +__initDDR2(type) +{ + +// ------------------ DDR Controller Registers -------------- + + +// 0xFFFFEA00 Mode Register MPDDRC_MR +// 0xFFFFEA04 Refresh Timer Register MPDDRC_RTR +// 0xFFFFEA08 Configuration Register MPDDRC_CR +// 0xFFFFEA0C Timing Parameter 0 Register MPDDRC_TPR0 +// 0xFFFFEA10 Timing Parameter 1 Register MPDDRC_TPR1 +// 0xFFFFEA14 Timing Parameter 2 Register MPDDRC_TPR2 +// 0xFFFFEA1C Low-power Register MPDDRC_LPR +// 0xFFFFEA20 Memory Device Register MPDDRC_MD +// 0xFFFFEA28 LPDDR2 Low-power Register MPDDRC_LPDDR2_LPR +// 0xFFFFEA2C LPDDR2 Calibration and MR4 Register MPDDRC_LPDDR2_CAL_MR4 +// 0xFFFFEA30 LPDDR2 Timing Calibration Register MPDDRC_LPDDR2_TIM_CAL +// 0xFFFFEA34 IO Calibration MPDDRC_IO_CALIBR +// 0xFFFFEA38 OCMS Register MPDDRC_OCMS +// 0xFFFFEA3C OCMS KEY1 Register MPDDRC_OCMS_KEY1 Write-only +// 0xFFFFEA40 OCMS KEY2 Register MPDDRC_OCMS_KEY2 Write-only +// 0xFFFFEA74 DLL Master Offset Register MPDDRC_DLL_MOR +// 0xFFFFEA78 DLL Slave Offset Register MPDDRC_DLL_SOR +// 0xFFFFEA7C DLL Master Status Register MPDDRC_DLL_MSR Read-only +// 0xFFFFEA80 DLL Slave 0 Status Register MPDDRC_DLL_S0SR Read-only +// 0xFFFFEA84 DLL Slave 1 Status Register MPDDRC_DLL_S1SR Read-only +// 0xFFFFEAE4 Write Protect Control Register MPDDRC_WPCR +// 0xFFFFEAE8 Write Protect Status Register MPDDRC_WPSR Read-only + +// ----------------------------------------------- + +// ---------------- DDR2 Timings (133MHz) ----------------- + + // -------- Configuration Register +// n_row = 14 +// n_col = 10 +// n_bank = 8 + // -------- Refresh Timer Register +// t_refresh = 520 + // -------- Timing 0 Register +// t_tras = TRAS 6 +// t_trcd = TRCD 2 +// t_twr = TWR 2 +// t_trc = TRC 8 +// t_trp = TRP 2 +// t_trrd = TRRD 2 +// t_twtr = TWTR 2 +// t_tmrd = TMRD 2 + // -------- Timing 1 Register +// t_trfc = TRFC 26/14 +// t_txsnr = TXSNR 28/16 +// t_txsrd = TXSRD 208 +// t_txp = TXP 2 + // -------- Timing 2 Register +// t_txard = TXARD 7 +// t_tards = TXARDS 7 +// t_trpa = TRPA 3 +// t_trtp = TRTP 2 +// t_tfaw = TFAW 10 +// ----------------------------------------------- + if (type == 0) { + __message " --------- Configure MT47H128M16 DDR2 "; + } else { + __message " --------- Configure MT47H64M16 DDR2 "; + } + __delay(2); + __writeMemory32(0x00008000,0xFFFFFE44,"Memory"); // Disable Watchdog + __writeMemory32(0x10000,0xFFFFEA1C,"Memory"); + __writeMemory32(0x00020000,0xFFFFFD00,"Memory"); // Enable MPDDR controller clock + __writeMemory32(0x00000004,0xFFFFFC00,"Memory"); // System Clock Enable Register : Enable DDR clock + +// __writeMemory32(0x00000020,0xFFFFEA24,"Memory"); // DDRSDRC High Speed Register (MPDDRC_HS) : hidden option -> calibration during autorefresh +// __writeMemory32(0x00030000,0xF0038004,"Memory"); // SFR_DDRCFG DDR Configuration Force DDR_DQ and DDR_DQS input buffer always on + + __writeMemory32(0x01010101,0xFFFFEA78,"Memory"); // MPDDRC DLL Slave Offset Register : set DLL Slave x Delay Line Offset + __writeMemory32(0xC5011F07,0xFFFFEA74,"Memory"); // MPDDRC DLL Master Offset Register : DLL Master Delay Line Offset + DLL CLK90 Delay Line Offset + DLL Offset Selection + +// __writeMemory32(0x00000028,0xFFFFEA24,"Memory"); // DDRSDRC High Speed Register : enable calibration during autorefresh +// __writeMemory32(0x00030001,0xF0038004,"Memory"); // SFR_DDRCFG DDR Configuration : Force DDR_DQ and DDR_DQS input buffer always on + __writeMemory32(0x01010101,0xFFFFEA78,"Memory"); // MPDDRC DLL Slave Offset Register : set DLL Slave x Delay Line Offset + __writeMemory32(0xC5011f07,0xFFFFEA74,"Memory"); // MPDDRC DLL Master Offset Register : DLL Master Delay Line Offset + DLL CLK90 Delay Line Offset + DLL Offset Selection + __writeMemory32(0x00870303,0xFFFFEA34,"Memory"); // MPDDRC I/O Calibration Register : set Resistor Divider + IO Calibration (delay between an IO Calibration Command and any Valid commands) + __writeMemory32(0x00001100,0xFFFFEA80,"Memory"); + __writeMemory32(0x00001100,0xFFFFEA84,"Memory"); + __writeMemory32(0x00001100,0xFFFFEA88,"Memory"); + __writeMemory32(0x00001100,0xFFFFEA8C,"Memory"); + +// __writeMemory32(0x00000028,0xFFFFEA24,"Memory"); // DDRSDRC High Speed Register : enable calibration during autorefresh +// __writeMemory32(0x00030001,0xF0038004,"Memory"); // SFR_DDRCFG DDR Configuration : Force DDR_DQ and DDR_DQS input buffer always on + + + __writeMemory32(0x00000006,0xFFFFEA20,"Memory"); // Memory Device Register : 32bit mode - DDR2 mode + if (type == 0) { + __writeMemory32(0x00B0003D,0xFFFFEA08,"Memory"); // Configuration Register : row = 13, column(DDR) = 10, CAS 3, DLL reset disable, phase error correction is enabled / normal driver strength + } else { + __writeMemory32(0x00B0004D,0xFFFFEA08,"Memory"); // Configuration Register : row = 14, column(DDR) = 10, CAS 3, DLL reset disable, phase error correction is enabled / normal driver strength + } + __writeMemory32(0x22228326,0xFFFFEA0C,"Memory"); // Timing 0 Register : tras | trcd | twr | trc | trp | trrd | twtr | tmrd + __writeMemory32(0x02C81C1A,0xFFFFEA10,"Memory"); // Timing 1 Register : trfc | txsnr | txsrd | txp + __writeMemory32(0x00072278,0xFFFFEA14,"Memory"); // Timing 2 Register : txard | tards | trpa | trtp | tfaw + __writeMemory32(0x00000001,0xFFFFEA00,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); // wait 1 ms + + + __writeMemory32(0x00000001,0xFFFFEA00,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + __writeMemory32(0x00000001,0xFFFFEA00,"Memory"); // Mode register : command NOP --> ENABLE CLOCK output + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + + __writeMemory32(0x00000002,0xFFFFEA00,"Memory"); // Mode register : command All Banks Precharge + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + + __writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR2 BA0=0 BA1=1 + if (type == 0) { + __writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } else { + __writeMemory32(0x00000000,0x28000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } + __delay(1); + + + __writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR3 BA0=1 BA1=1 + if (type == 0) { + __writeMemory32(0x00000000,0x26000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } else { + __writeMemory32(0x00000000,0x2C000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } + + __delay(1); + __writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : command Extended Load Mode Register : Set EMR Ext Mode Reg EMSR1 BA0=1 BA1=0 ENABLE DLL + + if (type == 0) { + __writeMemory32(0x00000000,0x22000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } else { + __writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } + __delay(1); + + __writeMemory32(0x00B000BD,0xFFFFEA08,"Memory"); // Configuration Register : Enable DLL reset + + __writeMemory32(0x00000003,0xFFFFEA00,"Memory"); // Mode register : command RESET DLL + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + __writeMemory32(0x00000002,0xFFFFEA00,"Memory"); // Mode register : command All Banks Precharge + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); // Mode register : 2 * command Auto-Refresh + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + __writeMemory32(0x00000004,0xFFFFEA00,"Memory"); // Mode register : + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + + __writeMemory32(0x00B0003D,0xFFFFEA08,"Memory"); // Configuration Register : disable DLL reset + + __writeMemory32(0x00000003,0xFFFFEA00,"Memory"); // Mode register : MRS initialize device operation (CAS latency, burst length and disable DLL reset) + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + + __writeMemory32(0x00B0703D,0xFFFFEA08,"Memory"); // Configuration Register : OCD default value + + __writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : EMRS1 OCD Default values + if (type == 0) { + __writeMemory32(0x00000000,0x22000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } else { + __writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } + __delay(1); + + __writeMemory32(0x00B0003D,0xFFFFEA08,"Memory"); // Configuration Register : OCD exit + + __writeMemory32(0x00000005,0xFFFFEA00,"Memory"); // Mode register : EMRS1 OCD exit + if (type == 0) { + __writeMemory32(0x00000000,0x22000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } else { + __writeMemory32(0x00000000,0x24000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + } + __delay(1); + __writeMemory32(0x00000000,0xFFFFEA00,"Memory"); // Mode register : command Normal mode + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + __writeMemory32(0x00000000,0x20000000,"Memory"); // DDR2 memory : access memory to validate preeceeding command + __delay(1); + + __writeMemory32(0x00300408,0xFFFFEA04,"Memory"); // Refresh Timer register : 520 for 133 MHz + + __message "------------------------------- DDR2 memory init for 133 MHz ----------------------------------"; +} + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-norflash.mac b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-norflash.mac new file mode 100644 index 000000000..7af2f8824 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-norflash.mac @@ -0,0 +1,108 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: sama5d3x-ek-sram.mac +// User setup file for CSPY debugger. +// +// --------------------------------------------------------- + +__var __tempo_var; +__var __dummy_read; +__var __data_test; +__var __mac_i; + +/********************************************************************* +* +* execUserReset() : JTAG set initially to Full Speed +*/ +execUserReset() +{ +// __message "------------------------------ execUserReset ---------------------------------"; +// CheckNoRemap(); +// __message "-------------------------------Set PC Reset ----------------------------------"; +// __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR +} + +/********************************************************************* +* +* execUserPreload() : JTAG set initially to 32kHz +*/ +execUserPreload() +{ +// __message "------------------------------ execUserPreload ---------------------------------"; + //__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) + +// __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR +// CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000 + Watchdog(); //* Watchdog Disable + + //* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R +// __mac_i=__readMemory32(0xFFFFEE40,"Memory"); +// __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; +} + + +/********************************************************************* +* +* CheckRemap() +* +* Function description +* Check the Remap. +*/ + +CheckNoRemap() +{ + __tempo_var = __readMemory32(0x00000000,"Memory"); + + if (__tempo_var == 0xAA55AA55) + { + __data_test = 0x55AA55AA; + } + else + { + __data_test = 0xAA55AA55; + } + + __writeMemory32(__data_test,0x00000000,"Memory"); + + __dummy_read = __readMemory32(0x00000000,"Memory"); + + __writeMemory32(__tempo_var,0x00000000,"Memory"); + + if (__dummy_read == __data_test) + { + __message " ------------------------ The Remap is already done ------------------------"; + } + else + { + __message " ------------------------ The Remap is not DONE ------------------------"; + __writeMemory32(0x00000001,0xFFFFED00,"Memory"); + __delay(2); + __writeMemory32(0x00000001,0x00800000,"Memory"); + __delay(50); + __message "------------ The Remap was executed ------------"; + } +} + +/********************************************************************* +* +* _Watchdog() +* +* Function description +* Clear Watchdog +*/ + +Watchdog() +{ + // Watchdog Disable + __writeMemory32(0x00008000,0xFFFFFE44,"Memory"); + __message " ------------------------ Watchdog Disable ------------------------"; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-sram.mac b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-sram.mac new file mode 100644 index 000000000..164e7a9de --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x-ek-sram.mac @@ -0,0 +1,108 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: sama5d3x-ek-sram.mac +// User setup file for CSPY debugger. +// +// --------------------------------------------------------- + +__var __tempo_var; +__var __dummy_read; +__var __data_test; +__var __mac_i; + +/********************************************************************* +* +* execUserReset() : JTAG set initially to Full Speed +*/ +execUserReset() +{ + __message "------------------------------ execUserReset ---------------------------------"; + //CheckNoRemap(); + __message "-------------------------------Set PC Reset ----------------------------------"; + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR +} + +/********************************************************************* +* +* execUserPreload() : JTAG set initially to 32kHz +*/ +execUserPreload() +{ + __message "------------------------------ execUserPreload ---------------------------------"; + //__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz) + + __writeMemory32(0xD3,0x98,"Register"); //* Set CPSR + //CheckNoRemap(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000 + Watchdog(); //* Watchdog Disable + + //* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + __mac_i=__readMemory32(0xFFFFEE40,"Memory"); + __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; +} + + +/********************************************************************* +* +* CheckRemap() +* +* Function description +* Check the Remap. +*/ + +CheckNoRemap() +{ + __tempo_var = __readMemory32(0x00000000,"Memory"); + + if (__tempo_var == 0xAA55AA55) + { + __data_test = 0x55AA55AA; + } + else + { + __data_test = 0xAA55AA55; + } + + __writeMemory32(__data_test,0x00000000,"Memory"); + + __dummy_read = __readMemory32(0x00000000,"Memory"); + + __writeMemory32(__tempo_var,0x00000000,"Memory"); + + if (__dummy_read == __data_test) + { + __message " ------------------------ The Remap is already done ------------------------"; + } + else + { + __message " ------------------------ The Remap is not DONE ------------------------"; + __writeMemory32(0x00000001,0xFFFFED00,"Memory"); + __delay(2); + __writeMemory32(0x00000001,0x00800000,"Memory"); + __delay(50); + __message "------------ The Remap was executed ------------"; + } +} + +/********************************************************************* +* +* _Watchdog() +* +* Function description +* Clear Watchdog +*/ + +Watchdog() +{ + // Watchdog Disable + __writeMemory32(0x00008000,0xFFFFFE44,"Memory"); + __message " ------------------------ Watchdog Disable ------------------------"; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/ddram.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/ddram.icf new file mode 100644 index 000000000..1fce1cc5f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/ddram.icf @@ -0,0 +1,53 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_DDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_DDRAM_end__ = 0x20FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF; +define symbol __ICFEDIT_region_DDRAM_BUF_start__ = 0x23000000; +define symbol __ICFEDIT_region_DDRAM_BUF_end__ = 0x23FFFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x200; +define symbol __ICFEDIT_size_vectors__ = 0x200; +define symbol __ICFEDIT_size_cstack__ = 0x4000; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_DDRAM_start__; +export symbol __ICFEDIT_region_DDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_DDRAM_start__ size __ICFEDIT_size_startup__]; +define region DDRAM_region = mem:[from __ICFEDIT_region_DDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_DDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; +define region DMA_BUF_region = mem:[from __ICFEDIT_region_DDRAM_BUF_start__ to __ICFEDIT_region_DDRAM_BUF_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in DDRAM_region { readonly }; +place in DDRAM_region { readwrite }; +place in DDRAM_region { zeroinit }; +place in DMA_BUF_region {section region_dma_nocache }; +place in DDRAM_region { block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/ddram_flashloader.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/ddram_flashloader.icf new file mode 100644 index 000000000..d13e38469 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/ddram_flashloader.icf @@ -0,0 +1,45 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 0x0; +define symbol __ICFEDIT_region_RAM_start__ = 0x70000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x73FFFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x0; +define symbol __ICFEDIT_size_irqstack__ = 0x0; +define symbol __ICFEDIT_size_fiqstack__ = 0x0; +define symbol __ICFEDIT_size_undstack__ = 0x0; +define symbol __ICFEDIT_size_abtstack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +//initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ {section .intvec }; + +place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}}; +place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .noinit, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}}; + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/norflash.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/norflash.icf new file mode 100644 index 000000000..745193aae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/norflash.icf @@ -0,0 +1,48 @@ +/**** start of ICF editor section. ###ICF###*/ + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_SRAM0_start__ = 0x00300000; +define symbol __ICFEDIT_region_SRAM0_end__ = 0x0030FFFF; +define symbol __ICFEDIT_region_SRAM1_start__ = 0x00310000; +define symbol __ICFEDIT_region_SRAM1_end__ = 0x0031FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_svcstack__ = 0x40; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x40; +define symbol __ICFEDIT_size_undstack__ = 0x40; +define symbol __ICFEDIT_size_abtstack__ = 0x40; +define symbol __ICFEDIT_size_heap__ = 0x400; + +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region SRAM0 = mem:[from __ICFEDIT_region_SRAM0_start__ to __ICFEDIT_region_SRAM0_end__]; +define region SRAM1 = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors }; + +place in ROM { readonly }; +place in SRAM0 { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + +define exported symbol fl_ram_end = (__ICFEDIT_region_SRAM0_end__ & 0xFFFFFFF8); diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf new file mode 100644 index 000000000..bf2203026 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/resources/ewarm/sama5d3x/sram.icf @@ -0,0 +1,38 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x300000; +define symbol __ICFEDIT_region_RAM_end__ = 0x31FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy with packing=none { readwrite }; +do not initialize { readonly section .noinit }; + +place in VEC_region { section .vectors }; +place in RAM_region { readonly }; +place in RAM_region { section .cstartup }; +place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/bmp.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/bmp.c new file mode 100644 index 000000000..098377ecb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/bmp.c @@ -0,0 +1,315 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ + +/// BMP offset for header +#define IMAGE_OFFSET 0x100 + +/*---------------------------------------------------------------------------- + * Internal types + *----------------------------------------------------------------------------*/ +/** Describe the BMP palette */ +typedef struct _BMPPaletteEntry +{ + /** Blue value */ + uint8_t b; + /** Green value */ + uint8_t g; + /** Red value */ + uint8_t r; + /** Filler character value */ + uint8_t filler; +} BMPPaletteEntry ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Test if BMP is valid. + * \param file Buffer holding the file to examinate. + * \return 1 if the header of a BMP file is valid; otherwise returns 0. + */ +uint8_t BMP_IsValid( void *file ) +{ + return ((BMPHeader*) file)->type == BMP_TYPE ; +} + +/** + * \brief Returns the size of a BMP image given at least its header (the file does + * not have to be complete). + * \param file Pointer to the buffer which holds the BMP file. + * \return size of BMP image + */ +uint32_t BMP_GetFileSize( void *file ) +{ + return ((BMPHeader *) file)->fileSize ; +} + +/** + * \brief Write a BMP header + * \param pAddressHeader Begin address of the BMP + * \param bmpHSize BMP heigth size + * \param bmpVSize BMP width size + * \param bmpRgb Type of BMP (YUV or RGB) + * \param nbByte_Pixels Number of byte per pixels + */ +void WriteBMPheader( uint32_t* pAddressHeader, uint32_t bmpHSize, uint32_t bmpVSize, uint8_t bmpRgb, uint8_t nbByte_Pixels ) +{ + uint32_t i; + uint32_t* fill; + BMPHeader *Header; + bmpRgb = bmpRgb; + + fill = pAddressHeader; + for ( i=0 ; i < IMAGE_OFFSET ; i+=4 ) + { + *fill++ = 0; + } + + Header = (BMPHeader*) pAddressHeader; + + Header->type = BMP_TYPE; + Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET; + Header->reserved1 = 0; + Header->reserved2 = 0; + Header->offset = IMAGE_OFFSET; + Header->headerSize = BITMAPINFOHEADER; + Header->width = bmpHSize; + Header->height = bmpVSize; + Header->planes = 1; + Header->bits = nbByte_Pixels * 8; + Header->compression = 0; + Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels; + Header->xresolution = 0; + Header->yresolution = 0; + Header->ncolours = 0; + Header->importantcolours = 0; +} + + +/** + * \brief Debug function, dislay BMP header + * \param pAddressHeader Address of the BMP + */ +void BMP_displayHeader( uint32_t* pAddressHeader ) +{ + #if (TRACE_LEVEL >= TRACE_LEVEL_INFO) + BMPHeader *header; + + header = (BMPHeader*) pAddressHeader; + + TRACE_INFO("BMP\n\r"); + TRACE_INFO("type 0x%X \n\r", header->type); + TRACE_INFO("fileSize %ld \n\r", header->fileSize); + TRACE_INFO("reserved1 %d \n\r", header->reserved1); + TRACE_INFO("reserved2 %d \n\r", header->reserved2); + TRACE_INFO("offset %ld \n\r", header->offset); + TRACE_INFO("headerSize %ld \n\r", header->headerSize); + TRACE_INFO("width %ld \n\r", header->width); + TRACE_INFO("height %ld \n\r", header->height); + TRACE_INFO("planes %d \n\r", header->planes); + TRACE_INFO("bits %d \n\r", header->bits); + TRACE_INFO("compression %ld \n\r", header->compression); + TRACE_INFO("imageSize %ld \n\r", header->imageSize); + TRACE_INFO("xresolution %ld \n\r", header->xresolution); + TRACE_INFO("yresolution %ld \n\r", header->yresolution); + TRACE_INFO("ncolours %ld \n\r", header->ncolours); + TRACE_INFO("importantcolours %ld\n\r", header->importantcolours); + #else + pAddressHeader = pAddressHeader; + #endif +} + +/** + * \brief Loads a BMP image located at the given address, decodes it and stores the + * resulting image inside the provided buffer. Image must have the specified + * width & height. + * If no buffer is provided, this function simply checks if it is able to + * decode the image. + * \param file Buffer which holds the BMP file. + * \param buffer Buffer in which to store the decoded image. + * \param width Buffer width in pixels. + * \param height Buffer height in pixels. + * \param bpp Number of bits per pixels that the buffer stores. + * \return 0 if the image has been loaded; otherwise returns an error code. + */ +uint8_t BMP_Decode( void *file, uint8_t *buffer, uint32_t width, uint32_t height, uint8_t bpp ) +{ + BMPHeader *header; + uint32_t i, j; + uint8_t r, g, b; + uint8_t *image; + + // Read header information + header = (BMPHeader*) file; + + // Verify that the file is valid + if ( !BMP_IsValid( file ) ) + { + TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type); + + return 1; + } + + // Check that parameters match + if ( (header->compression != 0) || (header->width != width) || (header->height != height)) + { + TRACE_ERROR("BMP_Decode: File format not supported\n\r"); + TRACE_ERROR(" -> .compression = %u\n\r", (unsigned int)header->compression); + TRACE_ERROR(" -> .width = %u\n\r", (unsigned int)header->width); + TRACE_ERROR(" -> .height = %u\n\r", (unsigned int)header->height); + TRACE_ERROR(" -> .bits = %d\n\r", header->bits); + + return 2; + } + + // Get image data + image = (uint8_t *) ((uint32_t) file + header->offset); + + // Check that the bpp resolution is supported + // Only a 24-bit output & 24- or 8-bit input are supported + if ( bpp != 24 ) + { + TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r"); + + return 3; + } + else + { + if (header->bits == 24) + { + // Decoding is ok + if (!buffer) return 0; + + // Get image data (swapping red & blue) + for ( i=0 ; i < height ; i++ ) + { + for ( j=0 ; j < width; j++ ) + { + r = image[((height - i - 1) * width + j) * 3 + 2]; + g = image[((height - i - 1) * width + j) * 3 + 1]; + b = image[((height - i - 1) * width + j) * 3]; + + #if defined(BOARD_LCD_RGB565) + // Interlacing + r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5); + g = (g << 1) & 0xF8; + b = b & 0xF8; + + buffer[(i * width + j) * 3] = b; + buffer[(i * width + j) * 3 + 1] = g; + buffer[(i * width + j) * 3 + 2] = r; + + #else + buffer[(i * width + j) * 3] = r; + buffer[(i * width + j) * 3 + 1] = g; + buffer[(i * width + j) * 3 + 2] = b; + #endif //#if defined(BOARD_LCD_RGB565) + } + } + } + else + { + if ( header->bits == 8 ) + { + // Decoding is ok + if (!buffer) return 0; + + // Retrieve palette + BMPPaletteEntry palette[256]; + memcpy( palette, (uint8_t *) ((uint32_t) file + sizeof( BMPHeader )), header->offset - sizeof( BMPHeader ) ) ; + + // Decode image (reversing row order) + for ( i=0 ; i < height ; i++ ) + { + for (j=0; j < width; j++) + { + r = palette[image[(height - i - 1) * width + j]].r; + g = palette[image[(height - i - 1) * width + j]].g; + b = palette[image[(height - i - 1) * width + j]].b; + + buffer[(i * width + j) * 3] = r; + buffer[(i * width + j) * 3 + 1] = g; + buffer[(i * width + j) * 3 + 2] = b; + } + } + } + else + { + + TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r"); + TRACE_INFO("header->bits 0x%X \n\r", header->bits); + return 4 ; + } + } + } + + return 0 ; +} + +/** + * \brief Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD) + * + * \param fileSource Buffer which holds the RGB file + * \param fileDestination Buffer in which to store the decoded image + * \param width Buffer width in pixels. + * \param height Buffer height in pixels. + * \param bpp Number of bits per pixels that the buffer stores. + */ +void RGB565toBGR555( uint8_t *fileSource, uint8_t *fileDestination, uint32_t width, uint32_t height, uint8_t bpp ) +{ + uint32_t i; + uint32_t j; + uint32_t row; + + for (i=0; i < height*(bpp/8); i++) + { + row = (i*width*(bpp/8)); + + for (j=0; j <= width*(bpp/8); j+=2) + { + fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F) + | (fileSource[row+j]&0xE0); + fileDestination[row+j+1] = (fileSource[row+j+1]&0x03) + | ((fileSource[row+j]&0x1F)<<2); + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_cstartup_gnu.S b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_cstartup_gnu.S new file mode 100644 index 000000000..590d563b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_cstartup_gnu.S @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + + +#define AIC 0xFFFFF000 +#define AIC_IVR 0x10 +#define AIC_EOICR 0x38 + +#define IRQ_STACK_SIZE 8*3*4 + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + + .align 4 + .arm + +/* Exception vectors + *******************/ + .section .vectors, "a", %progbits + +resetVector: + ldr pc, =resetHandler /* Reset */ +undefVector: + b undefVector /* Undefined instruction */ +swiVector: + b swiVector /* Software interrupt */ +prefetchAbortVector: + b prefetchAbortVector /* Prefetch abort */ +dataAbortVector: + b dataAbortVector /* Data abort */ +reservedVector: + b reservedVector /* Reserved for future use */ +irqVector: + b irqHandler /* Interrupt */ +fiqVector: + /* Fast interrupt */ +//------------------------------------------------------------------------------ +/// Handles a fast interrupt request by branching to the address defined in the +/// AIC. +//------------------------------------------------------------------------------ +fiqHandler: + b fiqHandler + +//------------------------------------------------------------------------------ +/// Handles incoming interrupt requests by branching to the corresponding +/// handler, as defined in the AIC. Supports interrupt nesting. +//------------------------------------------------------------------------------ +irqHandler: + /* Save interrupt context on the stack to allow nesting */ + SUB lr, lr, #4 + STMFD sp!, {lr} + MRS lr, SPSR + STMFD sp!, {r0, lr} + + /* Write in the IVR to support Protect Mode */ + LDR lr, =AIC + LDR r0, [r14, #AIC_IVR] + STR lr, [r14, #AIC_IVR] + + /* Branch to interrupt handler in Supervisor mode */ + MSR CPSR_c, #ARM_MODE_SVC + STMFD sp!, {r1-r3, r4, r12, lr} + + /* Check for 8-byte alignment and save lr plus a */ + /* word to indicate the stack adjustment used (0 or 4) */ + AND r1, sp, #4 + SUB sp, sp, r1 + STMFD sp!, {r1, lr} + + BLX r0 + + LDMIA sp!, {r1, lr} + ADD sp, sp, r1 + + LDMIA sp!, {r1-r3, r4, r12, lr} + MSR CPSR_c, #ARM_MODE_IRQ | I_BIT + + /* Acknowledge interrupt */ + LDR lr, =AIC + STR lr, [r14, #AIC_EOICR] + + /* Restore interrupt context and branch back to calling code */ + LDMIA sp!, {r0, lr} + MSR SPSR_cxsf, lr + LDMIA sp!, {pc}^ + + +//------------------------------------------------------------------------------ +/// Initializes the chip and branches to the main() function. +//------------------------------------------------------------------------------ + .section .textEntry + .global entry + +entry: +resetHandler: + + CPSIE A + +/* Enable VFP */ + /* - Enable access to CP10 and CP11 in CP15.CACR */ + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0xf00000 + mcr p15, 0, r0, c1, c0, 2 +/* - Enable access to CP10 and CP11 in CP15.NSACR */ +/* - Set FPEXC.EN (B30) */ + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + +/* Useless instruction for referencing the .vectors section */ + ldr r0, =resetVector + +/* Set pc to actual code location (i.e. not in remap zone) */ + ldr pc, =1f + +/* Initialize the prerelocate segment */ +1: + ldr r0, =_efixed + ldr r1, =_sprerelocate + ldr r2, =_eprerelocate +1: + cmp r1, r2 + ldrcc r3, [r0], #4 + strcc r3, [r1], #4 + bcc 1b + +/* Perform low-level initialization of the chip using LowLevelInit() */ + ldr sp, =_sstack + stmfd sp!, {r0} + ldr r0, =LowLevelInit + blx r0 + +/* Initialize the postrelocate segment */ + + ldmfd sp!, {r0} + ldr r1, =_spostrelocate + ldr r2, =_epostrelocate +1: + cmp r1, r2 + ldrcc r3, [r0], #4 + strcc r3, [r1], #4 + bcc 1b + +/* Clear the zero segment */ + ldr r0, =_szero + ldr r1, =_ezero + mov r2, #0 +1: + cmp r0, r1 + strcc r2, [r0], #4 + bcc 1b + +/* Setup stacks + **************/ +/* IRQ mode */ + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + ldr sp, =_sstack + sub r4, sp, #IRQ_STACK_SIZE + +/* Supervisor mode (interrupts enabled) */ + msr CPSR_c, #ARM_MODE_SVC | F_BIT + mov sp, r4 + +/*Initialize the C library */ + ldr r3, =__libc_init_array + mov lr, pc + bx r3 + +/* Branch to main() + ******************/ + ldr r0, =main + blx r0 + +/* Loop indefinitely when program is finished */ +1: + b 1b + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_cstartup_iar.s b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_cstartup_iar.s new file mode 100644 index 000000000..7e3a2ced5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_cstartup_iar.s @@ -0,0 +1,200 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + IAR startup file for AT91SAMA5D3X microcontrollers. + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +//#define __ASSEMBLY__ +//#include "board.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#define AIC 0xFFFFF000 +#define AIC_IVR 0x10 +#define AIC_EOICR 0x38 + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + +/* + Exception vectors + */ + SECTION .vectors:CODE:NOROOT(2) + + PUBLIC resetVector + PUBLIC irqHandler + + EXTERN Undefined_Handler + EXTERN SWI_Handler + EXTERN Prefetch_Handler + EXTERN Abort_Handler + EXTERN FIQ_Handler + + ARM + +__iar_init$$done: ; The interrupt vector is not needed + ; until after copy initialization is done + +resetVector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR pc, =resetHandler ; Reset + LDR pc, Undefined_Addr ; Undefined instructions + LDR pc, SWI_Addr ; Software interrupt (SWI/SYS) + LDR pc, Prefetch_Addr ; Prefetch abort + LDR pc, Abort_Addr ; Data abort + B . ; RESERVED + LDR pc, =irqHandler ; IRQ + LDR pc, FIQ_Addr ; FIQ + +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +FIQ_Addr: DCD FIQ_Handler + +/* + Handles incoming interrupt requests by branching to the corresponding + handler, as defined in the AIC. Supports interrupt nesting. + */ +irqHandler: + /* Save interrupt context on the stack to allow nesting */ + SUB lr, lr, #4 + STMFD sp!, {lr} + MRS lr, SPSR + STMFD sp!, {r0, lr} + + /* Write in the IVR to support Protect Mode */ + LDR lr, =AIC + LDR r0, [r14, #AIC_IVR] + STR lr, [r14, #AIC_IVR] + + /* Branch to interrupt handler in Supervisor mode */ + MSR CPSR_c, #ARM_MODE_SYS + STMFD sp!, {r1-r3, r4, r12, lr} + + /* Check for 8-byte alignment and save lr plus a */ + /* word to indicate the stack adjustment used (0 or 4) */ + AND r1, sp, #4 + SUB sp, sp, r1 + STMFD sp!, {r1, lr} + + BLX r0 + + LDMIA sp!, {r1, lr} + ADD sp, sp, r1 + + LDMIA sp!, {r1-r3, r4, r12, lr} + MSR CPSR_c, #ARM_MODE_IRQ | I_BIT + + /* Acknowledge interrupt */ + LDR lr, =AIC + STR lr, [r14, #AIC_EOICR] + + /* Restore interrupt context and branch back to calling code */ + LDMIA sp!, {r0, lr} + MSR SPSR_cxsf, lr + LDMIA sp!, {pc}^ + + +/* + After a reset, execution starts here, the mode is ARM, supervisor + with interrupts disabled. + Initializes the chip and branches to the main() function. + */ + SECTION .cstartup:CODE:NOROOT(2) + + PUBLIC resetHandler + EXTERN LowLevelInit + EXTERN ?main + REQUIRE resetVector + ARM + +resetHandler: + CPSIE A + /* Enable VFP */ + /* - Enable access to CP10 and CP11 in CP15.CACR */ + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0xf00000 + mcr p15, 0, r0, c1, c0, 2 + /* - Enable access to CP10 and CP11 in CP15.NSACR */ + /* - Set FPEXC.EN (B30) */ + fmrx r0, fpexc + orr r0, r0, #0x40000000 + fmxr fpexc, r0 + /* Set pc to actual code location (i.e. not in remap zone) */ + LDR pc, =label + + /* Perform low-level initialization of the chip using LowLevelInit() */ +label: + LDR r0, =LowLevelInit + LDR r4, =SFE(CSTACK) + MOV sp, r4 + BLX r0 + + /* Set up the interrupt stack pointer. */ + MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode + LDR sp, =SFE(IRQ_STACK) + + /* Set up the SYS stack pointer. */ + MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode + LDR sp, =SFE(CSTACK) + + /* Branch to main() */ + LDR r0, =?main + BLX r0 + + /* Loop indefinitely when program is finished */ +loop4: + B loop4 + END diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c new file mode 100644 index 000000000..3e0b86334 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_lowlevel.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Provides the low-level initialization function that called on chip startup. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ +/** + * \brief Default spurious interrupt handler. Infinite loop. + */ +void defaultSpuriousHandler( void ) +{ + while (1); +} + +/** + * \brief Default handler for fast interrupt requests. Infinite loop. + */ +void defaultFiqHandler( void ) +{ + while (1); +} + +/** + * \brief Default handler for standard interrupt requests. Infinite loop. + */ +void defaultIrqHandler( void ) +{ + while (1); +} + +/** + * \brief Performs the low-level initialization of the chip. + * This includes EFC and master clock configuration. + * It also enable a low level on the pin NRST triggers a user reset. + */ +extern WEAK void LowLevelInit( void ) +{ + uint32_t i; + if ((uint32_t)LowLevelInit < DDR_CS_ADDR) /* Code not in external mem */ { + PMC_SelectExt12M_Osc(); + PMC_SwitchMck2Main(); + PMC_SetPllA( CKGR_PLLAR_STUCKTO1 | + CKGR_PLLAR_PLLACOUNT(0x3F) | + CKGR_PLLAR_OUTA(0x0) | + CKGR_PLLAR_MULA(65) | + CKGR_PLLAR_DIVA(1), + 0x3u << 8); + PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2_DIV2); + PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK); + PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3); + PMC_SwitchMck2Pll(); + } + +#if 0 + uint32_t abcdsr; + /* Configure PCK1 to measure MCK */ + PIOD->PIO_IDR = (1<<31); + abcdsr = PIOD->PIO_ABCDSR[0]; + PIOD->PIO_ABCDSR[0] = ((1<<31) | abcdsr); + abcdsr = PIOD->PIO_ABCDSR[1]; + PIOD->PIO_ABCDSR[1] &= (~(1<<31) & abcdsr); + PIOD->PIO_PDR = (1<<31); + + /* Disable programmable clock 1 output */ + REG_PMC_SCDR = PMC_SCER_PCK1; + /* Enable the DAC master clock */ + PMC->PMC_PCK[1] = PMC_PCK_CSS_MCK_CLK | PMC_PCK_PRES_CLOCK; + /* Enable programmable clock 1 output */ + REG_PMC_SCER = PMC_SCER_PCK1; + /* Wait for the PCKRDY1 bit to be set in the PMC_SR register*/ + while ((REG_PMC_SR & PMC_SR_PCKRDY1) == 0); +#endif + /* select FIQ */ + AIC->AIC_SSR = 0; + AIC->AIC_SVR = (unsigned int) defaultFiqHandler; + + for (i = 1; i < 31; i++) + { + AIC->AIC_SSR = i; + AIC->AIC_SVR = (unsigned int) defaultIrqHandler; + } + + AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler; + + /* Disable all interrupts */ + for (i = 1; i < 31; i++) + { + AIC->AIC_SSR = i; + AIC->AIC_IDCR = 1 ; + } + /* Clear All pending interrupts flags */ + for (i = 1; i < 31; i++) + { + AIC->AIC_SSR = i; + AIC->AIC_ICCR = 1 ; + } + /* Perform 8 IT acknoledge (write any value in EOICR) */ + for (i = 0; i < 8 ; i++) + { + AIC->AIC_EOICR = 0; + } + /* Remap */ + BOARD_RemapRam(); +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_memories.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_memories.c new file mode 100644 index 000000000..e5df72a49 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/board_memories.c @@ -0,0 +1,708 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup ddrd_module + * + * The DDR/SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises + * four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved + * to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. + * + * \section ddr2 Configures DDR2 + * + * The DDR2-SDRAM devices are initialized by the following sequence: + *
    + *
  • EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.
    • + *
  • Step 1: Program the memory device type
    • + *
  • Step 2: + * -# Program the features of DDR2-SDRAM device into the Configuration Register. + * -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T0PR. + * -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T1PR. + * -# Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR.
    • + *
  • Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock.
    • + *
  • Step 4: An NOP command is issued to the DDR2-SDRAM
    • + *
  • Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
    • + *
  • Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.
    • + *
  • Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0.
    • + *
  • Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.
    • + *
  • Step 9: Program DLL field into the Configuration Register.
    • + *
  • Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.
    • + *
  • Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
    • + *
  • Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register.
    • + *
  • Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
    • + *
  • Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices.
    • + *
  • Step 15: Program OCD field into the Configuration Register to high (OCD calibration default).
    • + *
  • Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
    • + *
  • Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit).
    • + *
  • Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
    • + *
  • Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register.
    • + *
  • Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 or 7.81.
    • + *
+*/ +/*@{*/ +/*@}*/ + +/** \addtogroup sdram_module + * + * \section sdram Configures SDRAM + * + * The SDR-SDRAM devices are initialized by the following sequence: + *
    + *
  • EBI Chip Select 1 is assigned to the DDR2SDR Controller, Enable DDR2 clock x2 in PMC.
    • + *
  • Step 1. Program the memory device type into the Memory Device Register
    • + *
  • Step 2. Program the features of the SDR-SDRAM device into the Timing Register and into the Configuration Register.
    • + *
  • Step 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register.
    • + *
  • Step 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must + * set Mode to 1 in the Mode Register. Perform a write access to any SDR-SDRAM address to acknowledge this command. + * Now the clock which drives SDR-SDRAM device is enabled.
    • + *
  • Step 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the + * Mode Register . Perform a write access to any SDRSDRAM address to acknowledge this command.
    • + *
  • Step 6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register. + * Once in the idle state, two AUTO REFRESH cycles must be performed.
    • + *
  • Step 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRSDRAM + * devices, in particular CAS latency and burst length.
    • + *
  • Step 8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The write + * address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0
    • + *
  • Step 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and perform a write access at any location in the SDRAM to acknowledge this command.
    • + *
  • Step 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register
    • +*
+*/ +/*@{*/ +/*@}*/ + + + +/** + * \file + * + * Implementation of memories configuration on board. + * + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definiation + *----------------------------------------------------------------------------*/ + + +#define DDRC2_MODE_NORMAL_CMD (0x0) // (HDDRSDRC2) Normal Mode +#define DDRC2_MODE_NOP_CMD (0x1) // (HDDRSDRC2) Issue a NOP Command at every access +#define DDRC2_MODE_PRCGALL_CMD (0x2) // (HDDRSDRC2) Issue a All Banks Precharge Command at every access +#define DDRC2_MODE_LMR_CMD (0x3) // (HDDRSDRC2) Issue a Load Mode Register at every access +#define DDRC2_MODE_RFSH_CMD (0x4) // (HDDRSDRC2) Issue a Refresh +#define DDRC2_MODE_EXT_LMR_CMD (0x5) // (HDDRSDRC2) Issue an Extended Load Mode Register +#define DDRC2_MODE_DEEP_CMD (0x6) // (HDDRSDRC2) Enter Deep Power Mode +#define DDRC2_MODE_Reserved (0x7) // (HDDRSDRC2) Reserved value + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Changes the mapping of the chip so that the remap area mirrors the + * internal ROM or the EBI CS0. + */ +void BOARD_RemapRom( void ) +{ + MATRIX->MATRIX_MRCR = MATRIX_MRCR_RCB0; + AXIMX->AXIMX_REMAP = 0; +} + +/** + * \brief Changes the mapping of the chip so that the remap area mirrors the + * internal RAM. + */ + +void BOARD_RemapRam( void ) +{ + MATRIX->MATRIX_MRCR = MATRIX_MRCR_RCB0; + AXIMX->AXIMX_REMAP = AXIMX_REMAP_REMAP0; +} + +/** + * \brief Initialize Vdd EBI drive + * \param 0: 1.8V 1: 3.3V + */ +void BOARD_ConfigureVddMemSel( uint8_t VddMemSel ) +{ + ( void ) VddMemSel; +} + +#define DDR2_BA0(r) (1 << (25 + r)) +#define DDR2_BA1(r) (1 << (26 + r)) + +/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x74) MPDDRC DLL Slave Offset Register -------- */ +// SxOFF: DLL Slave x Delay Line Offset ([x=0..1][x=0..3]) +#define MPDDRC_DLL_SOR_S0_OFF_Pos 0 +#define MPDDRC_DLL_SOR_S0_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S0_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 0 Delay Line Offset */ +#define MPDDRC_DLL_SOR_S0_OFF(value) ((MPDDRC_DLL_SOR_S0_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S0_OFF_Pos))) +#define MPDDRC_DLL_SOR_S1_OFF_Pos 8 +#define MPDDRC_DLL_SOR_S1_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S1_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 1 Delay Line Offset */ +#define MPDDRC_DLL_SOR_S1_OFF(value) ((MPDDRC_DLL_SOR_S1_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S1_OFF_Pos))) +#define MPDDRC_DLL_SOR_S2_OFF_Pos 16 +#define MPDDRC_DLL_SOR_S2_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S2_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 2 Delay Line Offset */ +#define MPDDRC_DLL_SOR_S2_OFF(value) ((MPDDRC_DLL_SOR_S2_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S2_OFF_Pos))) +#define MPDDRC_DLL_SOR_S3_OFF_Pos 24 +#define MPDDRC_DLL_SOR_S3_OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S3_OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 3 Delay Line Offset */ +#define MPDDRC_DLL_SOR_S3_OFF(value) ((MPDDRC_DLL_SOR_S3_OFF_Msk & ((value) << MPDDRC_DLL_SOR_S3_OFF_Pos))) + + +/** + * \brief Configures DDR2 (MT47H128M16RT 128MB/ MT47H64M16HR) + MT47H64M16HR : 8 Meg x 16 x 8 banks + Refresh count: 8K + Row address: A[12:0] (8K) + Column address A[9:0] (1K) + Bank address BA[2:0] a(24,25) (8) + */ + +void BOARD_ConfigureDdram( uint8_t device ) +{ + volatile uint8_t *pDdr = (uint8_t *) DDR_CS_ADDR; + volatile uint32_t i; + volatile uint32_t cr = 0; + volatile uint32_t dummy_value; + + dummy_value = 0x00000000; + + /* Enable DDR2 clock x2 in PMC */ + PMC->PMC_PCER1 = (1 << (ID_MPDDRC-32)); + PMC->PMC_SCER |= PMC_SCER_DDRCK; + MPDDRC->MPDDRC_LPR = 0; + + MPDDRC->MPDDRC_DLL_SOR = 0x101 | MPDDRC_DLL_SOR_S1_OFF(0x0) | MPDDRC_DLL_SOR_S2_OFF(0x1) | MPDDRC_DLL_SOR_S3_OFF(0x1); + MPDDRC->MPDDRC_DLL_MOR = (0xC5000000) | MPDDRC_DLL_MOR_MOFF(7) | MPDDRC_DLL_MOR_CLK90OFF(0x1F) | MPDDRC_DLL_MOR_SELOFF; // Key = 0xc5000000 + dummy_value = MPDDRC->MPDDRC_IO_CALIBR; + dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk; + dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk; + dummy_value |= MPDDRC_IO_CALIBR_RDIV_RZQ_48; + dummy_value |= MPDDRC_IO_CALIBR_TZQIO(3); + MPDDRC->MPDDRC_IO_CALIBR = dummy_value; + *(uint32_t *)0xFFFFEA80 = 0x1100; + *(uint32_t *)0xFFFFEA84 = 0x1100; + *(uint32_t *)0xFFFFEA88 = 0x1100; + *(uint32_t *)0xFFFFEA8C = 0x1100; + +/* Step 1: Program the memory device type */ + /* DBW = 0 (32 bits bus wide); Memory Device = 6 = DDR2-SDRAM = 0x00000006*/ + MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_DDR2_SDRAM; + +/* Step 2: Program the features of DDR2-SDRAM device into the Timing Register.*/ + if (device == DDRAM_MT47H128M16RT) + { + MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_14 | + MPDDRC_CR_NC_10 | + MPDDRC_CR_CAS_4_DDR2 | + MPDDRC_CR_NB_8 | + MPDDRC_CR_DLL_RESET_DISABLED | + MPDDRC_CR_DQMS_NOT_SHARED | + MPDDRC_CR_ENRDM_OFF | + MPDDRC_CR_UNAL_SUPPORTED | + MPDDRC_CR_NDQS_DISABLED | + MPDDRC_CR_OCD(0x0); + } + if (device == DDRAM_MT47H64M16HR) + { + MPDDRC->MPDDRC_CR = MPDDRC_CR_NR_13 | + MPDDRC_CR_NC_10 | + MPDDRC_CR_CAS_3_DDR2| + MPDDRC_CR_NB_8 | + MPDDRC_CR_DLL_RESET_DISABLED | + MPDDRC_CR_DQMS_NOT_SHARED | + MPDDRC_CR_ENRDM_OFF | + MPDDRC_CR_UNAL_SUPPORTED | + MPDDRC_CR_NDQS_DISABLED | + MPDDRC_CR_OCD(0x0); + } + + MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS(6) // 6 * 7.5 = 45 ns + | MPDDRC_TPR0_TRCD(2) // 2 * 7.5 = 15 ns + | MPDDRC_TPR0_TWR(3) // 3 * 7.5 = 22.5 ns + | MPDDRC_TPR0_TRC(8) // 8 * 7.5 = 60 ns + | MPDDRC_TPR0_TRP(2) // 2 * 7.5 = 15 ns + | MPDDRC_TPR0_TRRD(2) // 2 * 7.5 = 15 ns + | MPDDRC_TPR0_TWTR(2) // 2 clock cycle + | MPDDRC_TPR0_TMRD(2); // 2 clock cycles + + MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC(0x1A) // 18 * 7.5 = 135 ns (min 127.5 ns for 1Gb DDR) + | MPDDRC_TPR1_TXSNR(0x1C) // 20 * 7.5 > 142.5ns TXSNR: Exit self refresh delay to non read command + | MPDDRC_TPR1_TXSRD(0xC8) // min 200 clock cycles, TXSRD: Exit self refresh delay to Read command + | MPDDRC_TPR1_TXP(0x2); // 2 * 7.5 = 15 ns + + MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD(8) // min 2 clock cycles + | MPDDRC_TPR2_TXARDS(7)// min 7 clock cycles + | MPDDRC_TPR2_TRPA(2) // min 18ns + | MPDDRC_TPR2_TRTP(2) // 2 * 7.5 = 15 ns (min 7.5ns) + | MPDDRC_TPR2_TFAW(7) ; + + /* DDRSDRC Low-power Register */ + for (i = 0; i < 13300; i++) { + asm("nop"); + } + MPDDRC->MPDDRC_LPR = MPDDRC_LPR_LPCB_DISABLED | + MPDDRC_LPR_CLK_FR_DISABLED | + MPDDRC_LPR_TIMEOUT_0 | + MPDDRC_LPR_APDE_SLOW ; + +/* Step 3: An NOP command is issued to the DDR2-SDRAM. Program the NOP command into + the Mode Register, the application must set MODE to 1 in the Mode Register. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD; + /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */ + *pDdr = 0; /* Now clocks which drive DDR2-SDRAM device are enabled.*/ + + /* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. (6 core cycles per iteration, core is at 396MHz: min 13200 loops) */ + for (i = 0; i < 13300; i++) { + asm("nop"); + } + +/* Step 4: An NOP command is issued to the DDR2-SDRAM */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD; + /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/ + *pDdr = 0; /* Now CKE is driven high.*/ + /* wait 400 ns min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 5: An all banks precharge command is issued to the DDR2-SDRAM. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD; + /* Perform a write access to any DDR2-SDRAM address to acknowledge this command.*/ + *pDdr = 0; + /* wait 400 ns min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD; + *((uint8_t *)(pDdr + DDR2_BA1(device))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. */ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD; + *((uint8_t *)(pDdr + DDR2_BA1(device) + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.*/ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + + /* Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD; + *((uint8_t *)(pDdr + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. */ + /* An additional 200 cycles of clock are required for locking DLL */ + for (i = 0; i < 10000; i++) { + asm("nop"); + } + +/* Step 9: Program DLL field into the Configuration Register.*/ + cr = MPDDRC->MPDDRC_CR; + MPDDRC->MPDDRC_CR = cr | MPDDRC_CR_DLL_RESET_ENABLED; + +/* Step 10: A Mode Register set (MRS) cycle is issued to reset DLL. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD; + *(pDdr) = 0; /* The write address must be chosen so that BA[1:0] bits are set to 0. */ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 11: An all banks precharge command is issued to the DDR2-SDRAM. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_PRCGALL_CMD; + *(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD; + *(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + /* Configure 2nd CBR. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_RFSH_CMD; + *(pDdr) = 0; /* Perform a write access to any DDR2-SDRAM address to acknowledge this command */ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). */ + cr = MPDDRC->MPDDRC_CR; + MPDDRC->MPDDRC_CR = cr & (~MPDDRC_CR_DLL_RESET_ENABLED); + +/* Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LMR_CMD; + *(pDdr) = 0; /* The write address must be chosen so that BA[1:0] are set to 0. */ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). */ + cr = MPDDRC->MPDDRC_CR; + MPDDRC->MPDDRC_CR = cr | MPDDRC_CR_OCD(0x07); + +/* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD; + *((uint8_t *)(pDdr + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit). */ + // cr = MPDDRC->MPDDRC_CR; + // MPDDRC->MPDDRC_CR = cr & (~ MPDDRC_CR_OCD(0x07)); + +/* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.*/ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_EXT_LMR_CMD; + *((uint8_t *)(pDdr + DDR2_BA0(device))) = 0; /* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.*/ + /* wait 2 cycles min */ + for (i = 0; i < 100; i++) { + asm("nop"); + } + +/* Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register. */ + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NORMAL_CMD; + *(pDdr) = 0; + +/* Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs. + With a 100MHz frequency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d. */ + /* For MT47H64M16HR, The refresh period is 64ms (commercial), This equates to an average + refresh rate of 7.8125¦Ìs (commercial), To ensure all rows of all banks are properly + refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) */ + /* ((64 x 10(^-3))/8192) x133 x (10^6) */ + //MPDDRC->MPDDRC_RTR = MPDDRC_RTR_COUNT(300); /* Set Refresh timer 7.8125 us*/ + MPDDRC->MPDDRC_RTR = 0x00300408; + /* OK now we are ready to work on the DDRSDR */ + /* wait for end of calibration */ + for (i = 0; i < 500; i++) { + asm(" nop"); + } +} + + +/** + * \brief Configures the EBI for Sdram (LPSDR Micron MT48H8M16) access. + */ +void BOARD_ConfigureSdram( void ) +{ +} + +/** \brief Configures the EBI for NandFlash access at 133Mhz. + */ +void BOARD_ConfigureNandFlash( uint8_t busWidth ) +{ + PMC_EnablePeripheral(ID_SMC); + SMC->SMC_CS_NUMBER[3].SMC_SETUP = 0 + | SMC_SETUP_NWE_SETUP(1) + | SMC_SETUP_NCS_WR_SETUP(1) + | SMC_SETUP_NRD_SETUP(2) + | SMC_SETUP_NCS_RD_SETUP(1); + + SMC->SMC_CS_NUMBER[3].SMC_PULSE = 0 + | SMC_PULSE_NWE_PULSE(5) + | SMC_PULSE_NCS_WR_PULSE(7) + | SMC_PULSE_NRD_PULSE(5) + | SMC_PULSE_NCS_RD_PULSE(7); + + SMC->SMC_CS_NUMBER[3].SMC_CYCLE = 0 + | SMC_CYCLE_NWE_CYCLE(8) + | SMC_CYCLE_NRD_CYCLE(9); + + SMC->SMC_CS_NUMBER[3].SMC_TIMINGS = SMC_TIMINGS_TCLR(3) + | SMC_TIMINGS_TADL(10) + | SMC_TIMINGS_TAR(3) + | SMC_TIMINGS_TRR(4) + | SMC_TIMINGS_TWB(5) + | SMC_TIMINGS_RBNSEL(3) + |(SMC_TIMINGS_NFSEL); + SMC->SMC_CS_NUMBER[3].SMC_MODE = SMC_MODE_READ_MODE | + SMC_MODE_WRITE_MODE | + ((busWidth == 8 )? SMC_MODE_DBW_BIT_8 :SMC_MODE_DBW_BIT_16) | + SMC_MODE_TDF_CYCLES(1); +} + +void BOARD_ConfigureNorFlash( uint8_t busWidth ) +{ + uint32_t dbw; + PMC_EnablePeripheral(ID_SMC); + if (busWidth == 8) + { + dbw = SMC_MODE_DBW_BIT_8; + } + else { + dbw = SMC_MODE_DBW_BIT_16; + } + /* Configure SMC, NCS0 is assigned to a norflash */ + SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0x00020001; + SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0x0B0B0A0A; + SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0x000E000B; + SMC->SMC_CS_NUMBER[0].SMC_TIMINGS = 0x00000000; + SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE_WRITE_MODE + | SMC_MODE_READ_MODE + | dbw + | SMC_MODE_EXNW_MODE_DISABLED + | SMC_MODE_TDF_CYCLES(1); + +} + +// ----------------------------------------------------------------------------- +// Function Name : LPDDR2_Initialize +// Object : +// ----------------------------------------------------------------------------- + +void BOARD_ConfigureLpDdram( void) +{ + volatile uint32_t i; + volatile uint32_t dummy_value; + PMC->PMC_PCER1 = (1 << (ID_MPDDRC-32)); + PMC->PMC_SCER |= PMC_SCER_DDRCK; + /* -------------------- Additional DDR2 setting ------------------------ */ + + MPDDRC->MPDDRC_DLL_SOR = MPDDRC_DLL_SOR_S0_OFF(0x4) | MPDDRC_DLL_SOR_S1_OFF(0x3) | MPDDRC_DLL_SOR_S2_OFF(0x4) | MPDDRC_DLL_SOR_S3_OFF(0x4); // design recommendation + MPDDRC->MPDDRC_DLL_MOR = (0xC5000000) | MPDDRC_DLL_MOR_MOFF(7) | MPDDRC_DLL_MOR_CLK90OFF(0x1F) | MPDDRC_DLL_MOR_SELOFF; // Key = 0xc5000000 + + dummy_value = MPDDRC->MPDDRC_IO_CALIBR; + dummy_value &= ~MPDDRC_IO_CALIBR_RDIV_Msk; + dummy_value &= ~MPDDRC_IO_CALIBR_TZQIO_Msk; + dummy_value |= (0x4 << 0); + dummy_value |= MPDDRC_IO_CALIBR_TZQIO(3); + + MPDDRC->MPDDRC_IO_CALIBR = dummy_value; + /* DDRSDRC High Speed Register (MPDDRC_HS) : hidden option -> calibration during autorefresh */ + *(uint32_t *)0xFFFFEA24 |= (1 << 5); + + /* SFR_DDRCFG DDR Configuration Force DDR_DQ and DDR_DQS input buffer always on */ + *(uint32_t *)0xF0038004 |= (0x3 << 16); + + /* Initialization sequence STEP 1 + Program the memory device type into the Memory Device Register */ + + /* Memory device = LPDDR2 => MPDDRC_MD_MD_LPDDR2_SDRAM + Data bus width = 32 bits => 0x0 (The system is in 64 bits, thus memory data bus width should be 32 bits) */ + MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_LPDDR2_SDRAM; + + +/* Initialization sequence STEP 2 + Program the features of Low-power DDR2-SDRAM device into the Timing Register + (asynchronous timing, trc, tras, etc.) and into the Configuration Register (number of + columns, rows, banks, CAS latency and output drive strength) (see Section 8.3 on + page 35, Section 8.4 on page 39 and Section 80.5 on page 41). */ + MPDDRC->MPDDRC_CR = MPDDRC_CR_NC_10 | + MPDDRC_CR_NR_14 | + MPDDRC_CR_CAS_5_LPDDR2 | + MPDDRC_CR_NB_8 | + MPDDRC_CR_UNAL_SUPPORTED | + MPDDRC_CR_ENRDM_ON; + MPDDRC->MPDDRC_LPDDR2_LPR |= MPDDRC_LPDDR2_LPR_DS(0x3); + + MPDDRC->MPDDRC_TPR0 = MPDDRC_TPR0_TRAS (6) | // 03 - TRAS tRAS Row active time + MPDDRC_TPR0_TRCD (2) | // 04 - TRC tRCD RAS-to-CAS delay + MPDDRC_TPR0_TWR (3) | // 05 - TWR tWR WRITE recovery time + MPDDRC_TPR0_TRC (8) | // 06 - TRC tRC ACTI-to-ACTIVT command period + MPDDRC_TPR0_TRP (3) | // 07 - TRP tRPpb Row precharge time + MPDDRC_TPR0_TRRD (2) | // 08 - TRRD tRRD Active bank a to active bank b + MPDDRC_TPR0_TWTR (2) | // 09 - TWTR-tWTR Internal WRITE-to-READcommand delay + MPDDRC_TPR0_TMRD (3); // 10 - TMRD-tMRD + + MPDDRC->MPDDRC_TPR1 = MPDDRC_TPR1_TRFC (17) | // 11 - TRFC tRFCab Refresh cycle time + MPDDRC_TPR1_TXSNR (18) | // 12 - TXSNR SELF REFRESH exit to next valid delay + MPDDRC_TPR1_TXSRD (14) | // 13 - TXSRD Exit Self Refresh + MPDDRC_TPR1_TXP (2); // 14 - TXP-tXP Exit power-down + + MPDDRC->MPDDRC_TPR2 = MPDDRC_TPR2_TXARD (1) | // 15 - TXARD-txARD + MPDDRC_TPR2_TXARDS (1) | // 16 - TXARDS-txARDs + MPDDRC_TPR2_TRPA (3) | // 17 - TRPA-tRPpab Row precharge time (all banks) + MPDDRC_TPR2_TRTP (2) | // 18 - TRTP-tRTP + MPDDRC_TPR2_TFAW (8); // 19 - TFAW-tFAW + +/* Initialization sequence STEP 3 + An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP + command into the Mode Register, the application must set the MODE (MDDRC Command + Mode) field to 1 in the Mode Register (see Section 8.1 on page 32). Perform a + write access to any Low-power DDR2-SDRAM address to acknowledge this command. + Now, clocks which drive Low-power DDR2-SDRAM devices are enabled. + A minimum pause of 100 ns must be observed to precede any signal toggle. */ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD; // NOP to ENABLE CLOCK output + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 100; i++) { + asm(" nop"); + } // Delay loop (at least 100 ns) + +/* Initialization sequence STEP 4 + An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP + command into the Mode Register, the application must set MODE to 1 in the Mode + Register (see Section 8.1 on page 32). Perform a write access to any Low-power + DDR2-SDRAM address to acknowledge this command. Now, CKE is driven high. + A minimum pause of 200 us must be satisfied before Reset Command. +*/ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_NOP_CMD; // NOP to drive CKE high + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 10000; i++) { + asm(" nop"); + } // Delay loop (at least 200 us) + +/* Initialization sequence STEP 5 + A reset command is issued to the Low-power DDR2-SDRAM. Program + LPDDR2_CMD in the MODE (MDDRC Command Mode) and MRS (Mode Register + Select LPDDR2) field of the Mode Register, the application must set MODE to 7 and + MRS to 63. (see Section 8.1 on page 32). Perform a write access to any Low-power + DDR2-SDRAM address to acknowledge this command. Now, the reset command is issued. + A minimum pause of 1us must be satisfied before any commands. */ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MRS(0x3F) | MPDDRC_MR_MODE_LPDDR2_CMD; + *(unsigned int *)DDR_CS_ADDR = 0x00000000; + for (i = 0; i < 500; i++) { asm(" nop"); } + +/* Initialization sequence STEP 6 + A Mode Register Read command is issued to the Low-power DDR2-SDRAM. Program + LPPDR2_CMD in the MODE and MRS field of the Mode Register, the + application must set MODE to 7 and must set MRS field to 0. (see Section 8.1 on + page 32). Perform a write access to any Low-power DDR2-SDRAM address to + acknowledge this command. Now, the Mode Register Read command is issued. + A minimum pause of 10 us must be satisfied before any commands. */ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x00); + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 5000; i++) {asm(" nop"); } + +/* Initialization sequence STEP 7 + A calibration command is issued to the Low-power DDR2-SDRAM. Program the type + of calibration into the Configuration Register, ZQ field, RESET value (see Section 8.3 + ”MPDDRC Configuration Register?on page 37). In the Mode Register, program the + MODE field to LPDDR2_CMD value, and the MRS field; the application must set + MODE to 7 and MRS to 10 (see Section 8.1 LPDDRC Mode Register?on page 34). + Perform a write access to any Low-power DDR2-SDRAM address to acknowledge + this command. Now, the ZQ Calibration command is issued. Program the type of calibration + into the Configuration Register, ZQ field */ + + MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_ZQ_Msk; + MPDDRC->MPDDRC_CR |= MPDDRC_CR_ZQ_RESET; + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x0A); + // Mode Register Read command. MODE = 0x7 and MRS = 0x0A + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 500; i++) {asm(" nop"); } + MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_ZQ_Msk; + MPDDRC->MPDDRC_CR |= MPDDRC_CR_ZQ_SHORT; + +/* Initialization sequence STEP 8 + A Mode Register Write command is issued to the Low-power DDR2-SDRAM. Program + LPPDR2_CMD in the MODE and MRS field in the Mode Register, the + application must set MODE to 7 and must set MRS field to 0.5 (see Section 8.1 on + page 32). The Mode Register Write command cycle is issued to program the parameters + of the Low-power DDR2-SDRAM devices, in particular burst length. Perform a + write access to any Low-power DDR2-SDRAM address to acknowledge this command. + Now, the Mode Register Write command is issued. */ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x01); + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 500; i++) { + asm(" nop"); + } + +/* Initialization sequence STEP 9 + Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program + LPPDR2_CMD in the MODE and MRS field in the Mode Register, the + application must set MODE to 7 and must set MRS field to 2. (see Section 8.1 on + page 32). The Mode Register Write command cycle is issued to program the parameters + of the Low-power DDR2-SDRAM devices, in particular CAS latency. Perform a + write access to any Low-power DDR2-SDRAM address to acknowledge this command. + Now, the Mode Register Write command is issued. */ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x02); + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 500; i++) { + asm(" nop"); + } + +/* Initialization sequence STEP 10 + A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program + LPPDR2_CMD in the MODE and MRS field of the Mode Register, the + application must set MODE to 7 and must set MRS field to 3. (see Section 8.1 on + page 32). The Mode Register Write command cycle is issued to program the parameters + of the Low-power DDR2-SDRAM devices, in particular Drive Strength and Slew + Rate. Perform a write access to any Low-power DDR2-SDRAM address to acknowledge + this command. Now, the Mode Register Write command is issued. */ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x03); //0x00000307; + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 500; i++) { + asm(" nop"); + } + +/* Initialization sequence STEP 11 + A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program + LPPDR2_CMD in the MODE and MRS field of the Mode Register, the + application must set MODE to 7 and must set MRS field to 16. (see Section 8.1 on + page 32). Mode Register Write command cycle is issued to program the parameters + of the Low-power DDR2-SDRAM devices, in particular Partial Array Self Refresh + (PASR). Perform a write access to any Low-power DDR2-SDRAM address to + acknowledge this command. Now, the Mode Register Write command is issued.*/ + + MPDDRC->MPDDRC_MR = MPDDRC_MR_MODE_LPDDR2_CMD | MPDDRC_MR_MRS(0x10);// 0x00001007; + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Access to memory + for (i = 0; i < 500; i++) { + asm(" nop"); + } + +/* Initialization sequence STEP 12 + Write the refresh rate into the COUNT field in the Refresh Timer register (see page + 33). (Refresh rate = delay between refresh cycles). The Low-power DDR2-SDRAM + device requires a refresh every 7.81 ìs. With a 100 MHz frequency, the refresh timer + count register must to be set with (7.81/100 MHz) = 781 i.e. 0x030d. */ + MPDDRC->MPDDRC_RTR &= ~MPDDRC_RTR_COUNT_Msk; + MPDDRC->MPDDRC_RTR |= MPDDRC_RTR_COUNT(1030); + MPDDRC->MPDDRC_MR = 0x00000000; // Set Normal mode + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Perform + for (i = 0; i < 500; i++) { + asm(" nop"); + } + /* Launch short ZQ calibration */ + MPDDRC->MPDDRC_CR &= ~MPDDRC_CR_ZQ_Msk; // Enable short calibration in the CR + MPDDRC->MPDDRC_CR |= MPDDRC_CR_ZQ_SHORT; + MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED; + *(unsigned int *)DDR_CS_ADDR = 0x00000000; // Perform + + /* Calculate ZQS: search for tZQCS in the memory datasheet => tZQCS = 180 ns*/ + MPDDRC->MPDDRC_LPDDR2_TIM_CAL = MPDDRC_LPDDR2_TIM_CAL_ZQCS(12); +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/cand.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/cand.c new file mode 100644 index 000000000..b15a8b967 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/cand.c @@ -0,0 +1,617 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ +/** \addtogroup cand_module + *@{*/ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + +#if defined(REG_CAN0_MR) || defined(REG_CAN_MR) + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup cand_states CAN Driver states + * @{*/ +#define CAND_STATE_DISABLED 0 /**< Power-up reset, controller is disabled */ +#define CAND_STATE_INIT 1 /**< Initializing */ +#define CAND_STATE_SLEEP 2 /**< Low-power mode */ +#define CAND_STATE_SYNC 3 /**< Synchronizating */ +#define CAND_STATE_ERROR 4 /**< Error halt */ +#define CAND_STATE_ACTIVATED 5 /**< Bus synchronization is done */ +#define CAND_STATE_XFR 6 /**< Transfer in progress */ +/** @}*/ + +/** \addtogroup cand_xfr_states CAN Transfer states + * @{*/ +#define CAND_XFR_DISABLED 0 /**< Transfer not used */ +#define CAND_XFR_HALTED 1 /**< Error halt */ +#define CAND_XFR_IDLE 2 /**< No transfer */ +#define CAND_XFR_TX 3 /**< Transferring data */ +/** @}*/ + +/** \addtogroup cand_reg_bits CAN Register Bitfields + * @{*/ +/** CAN mailbox event statuses bits */ +#define CAN_MB_EVENTS 0xFF +/** CAN errors statuses bits */ +#define CAN_ERRS (0 \ + /*|CAN_SR_ERRA*/ \ + /*|CAN_SR_WARN*/ \ + /*|CAN_SR_ERRP*/ \ + /*|CAN_SR_BOFF*/ \ + /*|CAN_SR_SLEEP*/ \ + /*|CAN_SR_WAKEUP*/ \ + /*|CAN_SR_TOVF*/ \ + /*|CAN_SR_TSTP*/ \ + |CAN_SR_CERR \ + |CAN_SR_SERR \ + |CAN_SR_AERR \ + |CAN_SR_FERR \ + |CAN_SR_BERR \ + /*|CAN_SR_RBSY*/ \ + /*|CAN_SR_TBSY*/ \ + /*|CAN_SR_OVLSY*/ \ + ) +/** CAN mailbox ID mask */ +#define CAN_ID_MASK (CAN_MID_MIDE | CAN_MID_MIDvA_Msk | CAN_MID_MIDvB_Msk) + +#define CAN_MMR_MOT(x) (((x)<bState == CAND_XFR_TX) return 0; + /* MB in a state that acceps modification */ + return 1; +} + +/** + * Reset mailbox with specified configuration value. + * \param pCand Pointer to CAN Driver instance. + * \param pCfg Pointer to list of configurations. + */ +static void CAND_ResetMb(sCand *pCand, uint8_t bMb, sCandMbCfg *pCfg) +{ + Can *pCan = pCand->pHw; + CAN_DisableIt(pCan, (1 << bMb) & CAN_MB_EVENTS); + CAN_MessageControl(pCan, bMb, 0); + CAN_ConfigureMessageMode(pCan, bMb, 0); + if (pCand->pMbs[bMb]) + { + pCand->pMbs[bMb] = CAND_XFR_DISABLED; + pCand->pMbs[bMb] = NULL; + } + if (pCfg) + { + CAN_ConfigureMessageAcceptanceMask(pCan, bMb, pCfg->dwMsgMask); + CAN_ConfigureMessageMode(pCan, bMb, CAN_MMR_MOT(pCfg->bMsgType) + | CAN_MMR_PRIOR(pCfg->bTxPriority)); + } +} + +/** + * Initialize transfer on specific Mailbox. + * \param pCand Pointer to CAN Driver instance. + * \param pXfr Pointer to CAN Transfer instance. + * \param bStart Start transfer immediately. + */ +static void CAND_InitXfr(sCand *pCand, sCandTransfer *pXfr, uint8_t bStart) +{ + Can *pCan = pCand->pHw; + uint8_t bMb = pXfr->bMailbox; + uint32_t dwMmr = CAN_GetMessageMode(pCan, bMb); + + if (pXfr == NULL) + return; + /* Log tranfser */ + pCand->pMbs[bMb] = pXfr; + /* Set transfer state */ + if (bStart) + { + pXfr->bState = CAND_XFR_TX; + pCand->bState = CAND_STATE_XFR; + } + /* Reset transfer state */ + else + pXfr->bState = CAND_XFR_IDLE; + /* Fill ID */ + CAN_ConfigureMessageID(pCan, bMb, pXfr->dwMsgID); + /* Fill data registers */ + CAN_SetMessage(pCan, bMb, pXfr->msgData); + /* Start TX if not RX */ + if ((dwMmr & CAN_MMR_MOT_Msk) > CAN_MMR_MOT_MB_RX_OVERWRITE) + { + CAN_MessageControl(pCan, bMb, + CAN_MCR_MDLC(pXfr->bMsgLen) + | (bStart ? CAN_MCR_MTCR : 0) ); + } +} + +/** + * Finish transfer on specific Mailbox. + * \param pCand Pointer to CAN Driver instance. + * \param pXfr Pointer to CAN Transfer instance. + * \param bSC Status code. + */ +static void CAND_EndXfr(sCand *pCand, sCandTransfer *pXfr, uint8_t bSC) +{ + if (!pCand) return; + /* Return status */ + pXfr->bRC = bSC; + if (bSC >= CAND_ERROR) + pXfr->bState = CAND_XFR_HALTED; + else if(pXfr->bState == CAND_XFR_TX) + pXfr->bState = CAND_XFR_IDLE; + /* Invoke callbacks */ +} + +/** + * Disable all mailboxes + */ +static void CAND_ResetMailboxes(sCand *pCand) +{ + uint32_t i; + /* Reset all mailboxes */ + for (i = 0; i < CAN_NUM_MAILBOX; i ++) + { + CAND_ResetMb(pCand, i, NULL); + } + pCand->bState = CAND_STATE_INIT; +} + +/** + * Handler for CAN errors + */ +static void CAND_ErrorHandler(sCand *pCand, uint32_t dwErrS) +{ + pCand = pCand; + uint32_t ecr; + TRACE_INFO("CAN[%x]: 0x%08x\n\r", pCand->pHw, dwErrS); + #if 1 + ecr = (pCand->pHw)->CAN_ECR; + ecr = ecr; /*Dummy */ + if (dwErrS & CAN_SR_ERRA) + { + + TRACE_ERROR_WP("-E- Active Mode: TEC %u, REC %u\n\r", + (unsigned int)((ecr & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos), + (unsigned int)((ecr & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos)); + } + if (dwErrS & CAN_SR_WARN) + { + TRACE_ERROR_WP("Warning Limit: TEC %u, REC %u\n\r", + (unsigned int)((ecr & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos), + (unsigned int)((ecr & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos)); + } + if (dwErrS & CAN_SR_ERRP) + { + TRACE_ERROR_WP("-E- Passive Mode: TEC %u, REC %u\n\r", + (unsigned int)((ecr & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos), + (unsigned int)((ecr & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos)); + } + if (dwErrS & CAN_SR_BOFF) + { + TRACE_ERROR_WP("Bus Off Mode, TEC %u\n\r", (unsigned int)((((pCand->pHw)->CAN_ECR) & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos)); + } + #endif + if (dwErrS & CAN_SR_CERR) + { + TRACE_ERROR_WP("-E- MB CRC\n\r"); + } + if (dwErrS & CAN_SR_SERR) + { + TRACE_ERROR_WP("-E- MB Stuffing\n\r"); + } + if (dwErrS & CAN_SR_AERR) + { + TRACE_ERROR_WP("-E- Ack\n\r"); + } + if (dwErrS & CAN_SR_FERR) + { + TRACE_ERROR_WP("-E- Form\n\r"); + } + if (dwErrS & CAN_SR_BERR) + { + TRACE_ERROR_WP("-E- Bit\n\r"); + } +} + +/** + * Handler for messages + * \param pCand Pointer to CAN Driver instance. + */ +static void CAND_MessageHandler(sCand *pCand) +{ + Can *pCan = pCand->pHw; + sCandTransfer *pXfr; + uint8_t bMb; + uint32_t dwMsr; + for (bMb = 0; bMb < CAN_NUM_MAILBOX; bMb ++) + { + /* Mailbox used ? */ + pXfr = pCand->pMbs[bMb]; + if (pXfr == NULL) + continue; + /* Mailbox ready ? */ + dwMsr = CAN_GetMessageStatus(pCan, bMb); + if ((dwMsr & CAN_MSR_MRDY) != CAN_MSR_MRDY) + continue; + /* Handle data */ + switch (CAN_GetMessageMode(pCan, bMb) & CAN_MMR_MOT_Msk) + { + case CAN_MMR_MOT_MB_RX_OVERWRITE: /** Next data overwrite current */ + /*pXfr->bState = CAND_XFR_RX_ONE;*/ + case CAN_MMR_MOT_MB_RX: + case CAN_MMR_MOT_MB_CONSUMER: /** TX then RX message */ + pXfr->bMsgLen = (dwMsr & CAN_MSR_MDLC_Msk) >> CAN_MSR_MDLC_Pos; + CAN_GetMessage(pCan, bMb, pXfr->msgData); + CAND_EndXfr(pCand, pXfr, CAND_OK); + break; + + case CAN_MMR_MOT_MB_TX: + case CAN_MMR_MOT_MB_PRODUCER: /** RX then TX message */ + CAND_EndXfr(pCand, pXfr, CAND_OK); + break; + + default: + TRACE_ERROR("MB[%d] disabled\n\r", bMb); + CAND_EndXfr(pCand, pXfr, CAND_ERROR); + break; + } + /*if (pXfr->bState != CAND_XFR_RX_ONE)*/ + { + /* Disable mailbox interrupt */ + CAN_DisableIt(pCan, 1 << bMb); + /* Unlink transfer */ + pCand->pMbs[bMb] = NULL; + } + } + /* All transfer finished ? */ + if ((CAN_GetItMask(pCan)&CAN_MB_EVENTS) == 0) + pCand->bState = CAND_STATE_ACTIVATED; +} + +/*---------------------------------------------------------------------------- + * Exported Functions + *----------------------------------------------------------------------------*/ + +/** + * Initialize CAN Driver with specific baudrate. + * \param pCand Pointer to CAN Driver instance. + * \param pHw Pointer to CAN controller HW base address. + * \param bID ID for CAN controller. + * \param wBaudrate Expected baudrate. + * \param dwMck Current MCK used. + */ +uint8_t CAND_Init(sCand* pCand, + Can *pHw, uint8_t bID, + uint16_t wBaudrate, uint32_t dwMck) +{ + + pCand->pHw = pHw; + pCand->bID = bID; + PMC_EnablePeripheral(pCand->bID); + /* Reserved */ + //pCand->fCallback = NULL; + //pCand->pArg = NULL; + + /* Disable all interrupts */ + CAN_DisableIt(pHw, 0xFFFFFFFF); + + /* (Re)initialize baudrate */ + if (wBaudrate) + { + pCand->dwMck = dwMck; + pCand->wBaudrate = wBaudrate; + if (!CAN_CalcBaudrate(pHw, wBaudrate, dwMck)) + return CAND_ERROR; + } + + /* Reset CAN mode */ + CAN_ConfigureMode(pHw, 0); + + /* Reset all mailboxes */ + CAND_ResetMailboxes(pCand); + + /* Enable the interrupts for error cases */ + CAN_EnableIt(pHw, CAN_ERRS); + + return CAND_OK; +} + +/** + * Activate CAN. + * \param pCand Pointer to CAN Driver instance. + */ +void CAND_Activate(sCand *pCand) +{ + Can *pCan = pCand->pHw; + if (pCand->bState > CAND_STATE_SYNC) + return; + /* Disable low-power mode */ + CAN_EnableLowPower(pCan, 0); + /* Start sync state */ + pCand->bState = CAND_STATE_SYNC; + /* Enable CAN and wait interrupt */ + CAN_EnableIt(pCan, CAN_IER_WAKEUP); + CAN_Enable(pCan, 1); +} +#if 0 +/** + * Find good baudrate (activated). + */ +void CAND_AutoBaudrate(sCand *pCand, uint16_t *pBuadList, uint16_t wListSize) +{ +} +#endif +/** + * Put into sleep mode + * \param pCand Pointer to CAN Driver instance. + */ +void CAND_Sleep(sCand *pCand) +{ + Can *pCan = pCand->pHw; + CAN_EnableIt(pCan, CAN_IER_SLEEP); + CAN_EnableLowPower(pCan, 1); +} + +/** + * Check if CAN is ready to transfer messages. + * \param pCand Pointer to CAN Driver instance. + */ +uint8_t CAND_IsReady(sCand *pCand) +{ + return (pCand->bState >= CAND_STATE_ACTIVATED); +} + +/** + * Interrupt handler for CAN Driver. + * \param pCand Pointer to CAN Driver instance. + */ +void CAND_Handler(sCand *pCand) +{ + Can *pHw = pCand->pHw; + uint32_t dwSr = CAN_GetStatus(pHw); + //uint32_t dwSm = CAN_GetItMask(pHw); + TRACE_INFO("%d:%8x\n\r", (pHw==CAN0)?0:1, dwSr); + /* Errors */ + if (dwSr & CAN_ERRS) + { + pCand->bState = CAND_STATE_ERROR; + CAND_ErrorHandler(pCand, (dwSr & CAN_ERRS)); + CAN_DisableIt(pHw, dwSr & CAN_ERRS); + } + else + { + /* Wakeup and bus synchronization done */ + if (pCand->bState > CAND_STATE_ACTIVATED) + { + /* Mailbox events */ + if (dwSr & CAN_MB_EVENTS) + { + CAND_MessageHandler(pCand); + } + } + else if (dwSr & CAN_SR_WAKEUP) + { + CAN_DisableIt(pHw, CAN_IDR_WAKEUP); + pCand->bState = CAND_STATE_ACTIVATED; + } + } + /* Low-power Mode enabled */ + if (dwSr & CAN_SR_SLEEP) + { + CAN_DisableIt(pHw, CAN_IDR_SLEEP); + pCand->bState = CAND_STATE_SLEEP; + } + /* Timestamp */ + if (dwSr & CAN_SR_TSTP) + { + } + /* Timer overflow */ + if (dwSr & CAN_SR_TOVF) + { + } +} + +/** + * Check if the mailbox is ready to configure or transfer. + * \param pCand Pointer to CAN Driver instance. + * \param bMb Mailbox number. + * \return 1 if mailbox is free. + */ +uint8_t CAND_IsMailboxReady(sCand *pCand, uint8_t bMb) +{ + return (CAND_IsMbReady(pCand->pMbs[bMb])); +} + +/** + * Reset the CAN Mailbox (with configuration). + * \param pCand Pointer to CAN Driver instance. + * \param bMb Mailbox number. + * \param pCfg Pointer to Mailbox configuration instance. + * NULL to reset and disable the mailbox. + */ +void CAND_ResetMailbox(sCand *pCand, uint8_t bMb, sCandMbCfg *pCfg) +{ + CAND_ResetMb(pCand, bMb, pCfg); +} + +/** + * Configure the CAN Mailbox for message transfer. + * \param pCand Pointer to CAN Driver instance. + * \param pCfg Pointer to Mailbox configuration instance. + * NULL to use old configuration. + * \param pXfr Pointer to transfer configuration instance. + */ +uint8_t CAND_ConfigureTransfer(sCand *pCand, + sCandMbCfg *pCfg, + sCandTransfer *pXfr) +{ + uint8_t bMb = pXfr->bMailbox; + sCandTransfer *pTx = pCand->pMbs[bMb]; + + if (!CAND_IsMbReady(pTx)) + return CAND_BUSY; + if (pCfg) + CAND_ResetMb(pCand, bMb, pCfg); + CAND_InitXfr(pCand, pXfr, 0); + return CAND_OK; +} + +/** + * Transfer CAN message through a configured mailbox. + * The transfer will not start until it's started by CAND_StartTransfers(). + * \note For data receiving, if there is previous pending message in + * mailbox, the RX operation will return this message data. + * \param pCand Pointer to CAN Driver instance. + * \param pXfr Pointer to transfer configuration instance. + * \param bStart 1 to start the transfer immediately. + */ +uint8_t CAND_Transfer(sCand *pCand, sCandTransfer *pXfr) +{ + Can *pCan = pCand->pHw; + sCandTransfer *pTx; + uint8_t bMb = pXfr->bMailbox; + + pTx = pCand->pMbs[bMb]; + if (!CAND_IsMbReady(pTx)) return CAND_BUSY; + if (0 == CAN_GetMessageMode(pCan, bMb)) + return CAND_ERR_STATE; + /* Configure and start transfer */ + CAND_InitXfr(pCand, pXfr, 1); + /* Enable interrupts statuses */ + CAN_EnableIt(pCan, (CAN_ID_MASK & (1 << bMb))|CAN_ERRS); + return CAND_OK; +} + +/** + * Start configured transfers (by CAND_ConfigureTransfer()). + * \note For data receiving, if there is previous pending message in + * mailbox, the RX operation will return this message data. + * \param pCand Pointer to CAN Driver instance. + * \param bmMbs Mailbox bitmap. + */ +void CAND_StartTransfers(sCand *pCand, uint32_t bmMbs) +{ + Can *pCan = pCand->pHw; + sCandTransfer *pTx; + uint8_t bMb; + uint32_t bmTx = 0; + uint32_t bmRx = 0; + uint32_t dwMMR; + /* Scan mailboxes that not started */ + for (bMb = 0; bMb < CAN_NUM_MAILBOX; bMb ++) + { + if ((bmMbs & (1 << bMb)) == 0) + continue; + /* Check if the mailbox is ready to transfer */ + pTx = pCand->pMbs[bMb]; + if (pTx == NULL) + { + /* Ignore the mailbox */ + bmMbs &= ~(1 << bMb); + continue; + } + if (pTx->bState > CAND_XFR_IDLE) + { + /* Ignore the mailbox */ + bmMbs &= ~(1 << bMb); + continue; + } + dwMMR = CAN_GetMessageMode(pCan, bMb); + /* Disabled ? */ + if ( 0 == dwMMR ) + { + /* Ignore the mailbox */ + bmMbs &= ~(1 << bMb); + continue; + } + /* RX ? */ + else if ((dwMMR & CAN_MMR_MOT_Msk) <= CAN_MMR_MOT_MB_RX_OVERWRITE) + { + bmRx |= 1 << bMb; + } + /* TX ! */ + else + { + bmTx |= 1 << bMb; + } + + /* Change transfer state */ + pTx->bState = CAND_XFR_TX; + + /* Nothing to start */ + if (bmMbs == 0) + return; + } + /* Change CAN state */ + pCand->bState = CAND_STATE_XFR; + /* Start transfers */ + CAN_Command(pCan, bmTx); + /* Enable interrupts */ + CAN_EnableIt(pCan, bmMbs | CAN_ERRS); +} + +/** + * Check if the transfer is finished. + * \return 1 if it's ready to transfer data. + */ +uint8_t CAND_IsTransferDone(sCandTransfer *pXfr) +{ + return CAND_IsMbReady(pXfr); +} + +#endif +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/clock.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/clock.c new file mode 100644 index 000000000..cf015450d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/clock.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/* + * \brief Describes a possible clock configuration (processor clock & master clock), + * including the necessary register values. + */ +typedef struct _ClockConfiguration +{ + + /** Processor clock frequency (in MHz). */ + uint16_t pck; + /** Master clock frequency (in MHz). */ + uint16_t mck; + /** CKGR_PLL reqister value. */ + uint32_t pllr; + /** PMC_MCKR register value. */ + uint32_t mckr; +} ClockConfiguration ; + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/* Clock configurations for the AT91SAM3S4-EK */ +#define CKGR_MUL_SHIFT 16 +#define CKGR_PLLCOUNT_SHIFT 8 +#define CKGR_DIV_SHIFT 0 + +/* Clock configuration for the AT91SAM3S */ +static const ClockConfiguration clockConfigurations[] = { + {133, 133, CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_MULA(199) + | CKGR_PLLAR_OUTA(0) | CKGR_PLLAR_PLLACOUNT(64) | CKGR_PLLAR_DIVA(3), + PMC_MCKR_CSS_SLOW_CLK | PMC_MCKR_PRES_CLOCK | PMC_MCKR_MDIV_PCK_DIV3 + | PMC_MCKR_PLLADIV2_DIV2 | PMC_MCKR_CSS_PLLA_CLK} +}; + +/* Number of available clock configurations */ +#define NB_CLOCK_CONFIGURATION (sizeof(clockConfigurations)/sizeof(clockConfigurations[0])) + +/* Current clock configuration */ +uint32_t currentConfig = 0; /* 0 have to be the default configuration */ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Sets the specified clock configuration. + * + * \param configuration Index of the configuration to set. + */ +void CLOCK_SetConfig(uint8_t configuration) +{ + TRACE_DEBUG("Setting clock configuration #%d ... ", configuration); + currentConfig = configuration; + + /* Switch to main oscillator in two operations */ + //C->PMC_MCKR = (PMC->PMC_MCKR & (uint32_t)~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; + while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0); + + /* Configure PLL */ + PMC->CKGR_PLLAR = clockConfigurations[configuration].pllr; + while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); + + /* Configure master clock in two operations */ + //C->PMC_MCKR = (clockConfigurations[configuration].mckr & (uint32_t)~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; + while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0); + PMC->PMC_MCKR = clockConfigurations[configuration].mckr; + while ((PMC->PMC_SR & PMC_SR_MCKRDY) == 0); + + /* DBGU reconfiguration */ + DBGU_Configure(115200, clockConfigurations[configuration].mck*1000000); + TRACE_DEBUG("done.\n\r"); +} + +/** + * \brief Display the user menu on the DBGU. + */ +void CLOCK_DisplayMenu(void) +{ + uint32_t i; + + printf("\n\rMenu Clock configuration:\n\r"); + for (i = 0; i < NB_CLOCK_CONFIGURATION; i++) { + + printf(" %u: Set PCK = %3u MHz, MCK = %3u MHz %s\n\r", + (unsigned int)i, + (unsigned int)clockConfigurations[i].pck, + (unsigned int)clockConfigurations[i].mck, + (currentConfig==i)?"(curr)":""); + } +} + +/** + * \brief Get the current MCK + */ +uint16_t CLOCK_GetCurrMCK(void) +{ + return clockConfigurations[currentConfig].mck; +} + +/** + * \brief Get the current PCK + */ +uint16_t CLOCK_GetCurrPCK(void) +{ + return clockConfigurations[currentConfig].pck; +} + +/** + * \brief Change clock configuration. + */ +void CLOCK_UserChangeConfig(void) +{ + uint8_t key = 0; + + while (1) + { + CLOCK_DisplayMenu(); + key = DBGU_GetChar(); + + if ((key >= '0') && (key <= ('0' + NB_CLOCK_CONFIGURATION - 1))) + { + CLOCK_SetConfig(key - '0'); + break; + } + } +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbg_util.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbg_util.c new file mode 100644 index 000000000..3765b9bc0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbg_util.c @@ -0,0 +1,315 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * Implement simple DBGU usage as stream receiver. + */ + +/*------------------------------- + * Headers + *-------------------------------*/ + +#include + +/*------------------------------- + * Defines + *-------------------------------*/ + +/** Data RX timeout in binary start up */ +#define TIMEOUT_RX_START (1000*20) +/** Data RX timeout default value */ +#define TIMEOUT_RX (200) + +/* ASCII Character Codes */ +#define SOH 0x01 +#define STX 0x02 +#define EOT 0x04 +#define CTRL_D 0x04 /**< Transfer Done */ +#define ACK 0x06 +#define NAK 0x15 +#define CAN 0x18 /**< Cancel transfer */ +#define CTRL_X 0x24 + +/* 1K XMODEM Parameters */ +#define SOH_LENGTH 128 +#define STX_LENGTH 1024 +#define SOH_TIMEOUT 1000 + +/*------------------------------- + * Local functions + *-------------------------------*/ + +/** + * \brief Compute the CRC + */ +static uint16_t _GetCRC(uint8_t bByte, uint16_t wCrc) +{ + int32_t cnt; + uint8_t newBit; + for (cnt = 7; cnt >= 0; cnt --) + { + newBit = ((wCrc >> 15) & 0x1) ^ ((bByte >> cnt) & 0x1); + wCrc <<= 1; + if (newBit) wCrc ^= (0x1021); + } + return wCrc; + +} + +/*------------------------------- + * Exported functions + *-------------------------------*/ + +/** + * \brief Receives byte with timeout. + * \param pByte pointer to locate received byte, can be NULL + * to discard data. + * \param timeOut timeout setting, in number of ticks. + */ +uint8_t DbgReceiveByte(uint8_t* pByte, uint32_t timeOut) +{ + uint32_t tick; + uint32_t delay; + tick = GetTickCount(); + while(1) + { + if (DBGU_IsRxReady()) + { + uint8_t tmp = DBGU_GetChar(); + if (pByte) *pByte = tmp; + return 1; + } + + if (timeOut == 0) + { /* Never timeout */ + } + else + { + delay = GetDelayInTicks(tick, GetTickCount()); + if (delay > timeOut) + { + return 0; + } + } + } +} + +/** + * \brief Receives raw binary file through DBGU. + * \param bStart 1 to start a new data stream. + * \param address receiving data address + * \param maxSize max receive data size in bytes + * \return number of received bytes + */ +uint32_t DbgReceiveBinary(uint8_t bStart, uint32_t address, uint32_t maxSize) +{ + volatile uint32_t tick0; + uint32_t delay; + uint8_t *pBuffer = (uint8_t*)address; + uint8_t xSign = 0; + uint32_t rxCnt = 0; + + if (maxSize == 0) return 0; + + if (bStart) + { + printf("\n\r-- Please start binary data in %d seconds:\n\r", + TIMEOUT_RX_START / 1000); + tick0 = GetTickCount(); + while(1) + { + if (DBGU_IsRxReady()) + { + pBuffer[rxCnt ++] = DBGU_GetChar(); + DBGU_PutChar(' '); + break; + } + else + { + delay = GetDelayInTicks(tick0, GetTickCount()); + if ((delay % 1000) == 0) + { + if (xSign == 0) + { + DBGU_PutChar('*'); + xSign = 1; + } + } + else if (xSign) + { + xSign = 0; + } + + if (delay > TIMEOUT_RX_START) + { + printf("\n\rRX timeout!\n\r"); + return rxCnt; + } + } + } + } + /* Get data */ + while(1) + { + tick0 = GetTickCount(); + while(1) + { + if (DBGU_IsRxReady()) + { + pBuffer[rxCnt ++] = DBGU_GetChar(); + if ((rxCnt % (10*1024)) == 0) + { + DBGU_PutChar('.'); + } + if (rxCnt >= maxSize) + { + /* Wait until file transfer finished */ + return rxCnt; + } + break; + } + delay = GetDelayInTicks(tick0, GetTickCount()); + if (delay > TIMEOUT_RX) + { + return rxCnt; + } + } + } +} + +/** + * \brief Receives raw binary file through DBGU. + * + * \note When "CCC..", uses Ctrl + D to exit. + * + * \param pktBuffer 1K size packet buffer + * \param address receiving data address + * \param maxSize max receive data size in bytes + * \return number of received bytes + */ +uint32_t DbgReceive1KXModem(uint8_t* pktBuffer, + uint32_t address, + uint32_t maxSize) +{ + uint8_t inChar; + uint32_t i, index = 0, pktLen = 0; + uint8_t pktNum = 0, prevPktNum = 0; + uint32_t error = 0; + uint16_t inCrc, myCrc; + uint8_t inCheckSum = 0xFF, checkSum = 0; + uint8_t *pBuffer = (uint8_t*)address; + uint32_t totalLen = 0; + + DBGU_PutChar('C'); + while (1) + { + if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) + { + DBGU_PutChar('C'); + continue; + } + /* Done */ + if (EOT == inChar) + { + error = 0; + DBGU_PutChar(ACK); + break; + } + else if (CAN == inChar) + { + error = 2; + } + else if (CTRL_X == inChar) + { + error = 3; + } + else if (SOH == inChar) + { + pktLen = SOH_LENGTH; + } + else if (STX == inChar) + { + pktLen = STX_LENGTH; + } + else continue; + /* Get Packet Number */ + if (!DbgReceiveByte(&pktNum, SOH_TIMEOUT)) error = 4; + /* Get 1's complement of packet number */ + if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 5; + /* Get 1 packet of information. */ + checkSum = 0; myCrc = 0; index = 0; + for (i = 0; i < pktLen; i ++) + { + if (!DbgReceiveByte(&inChar, SOH_TIMEOUT)) error = 6; + checkSum += inChar; + myCrc = _GetCRC(inChar, myCrc); + if (pktNum != prevPktNum) + { + pktBuffer[index ++] = inChar; + } + } + /* Get CRC bytes */ + if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7; + inCrc = inCheckSum << 8; + if (!DbgReceiveByte(&inCheckSum, SOH_TIMEOUT)) error = 7; + inCrc += inCheckSum; + /* If CRC error, NAK */ + if (error || (inCrc != myCrc)) + { + DBGU_PutChar(NAK); + error = 0; + } + /* Save packet, ACK and next */ + else + { + prevPktNum = pktNum; + + /* Buffer full? */ + if (totalLen + pktLen > maxSize) + { + /* Copy until buffer full? */ + /* Stop transfer */ + DBGU_PutChar(CAN); + return totalLen; + } + + /* Copy the packet */ + for (i = 0; i < pktLen; i ++) + { + pBuffer[totalLen + i] = pktBuffer[i]; + } + totalLen += pktLen; + DBGU_PutChar(ACK); + } + } + + return totalLen; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbgu_console.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbgu_console.c new file mode 100644 index 000000000..84d439595 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dbgu_console.c @@ -0,0 +1,457 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implements DBGU console. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** The Pheripheral has no HW ID */ +#define ID_NOTUSED 0xFF + +/** Usart Hw ID (ID_USART0) */ +#define CONSOLE_ID (pDbgPort->bID) +/** Usart Hw interface used by the console (USART0). */ +#define CONSOLE_DBGU ((Dbgu*)pDbgPort->pHw) +/** Pins description list */ +#define CONSOLE_PINLIST (pDbgPort->pPioList) +/** Pins description list size */ +#define CONSOLE_PINLISTSIZE (pDbgPort->bPioListSize) + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** + * Debug port struct + */ +typedef struct _DbgPort { + const void* pHw; + const Pin* pPioList; + const uint8_t bPioListSize; + const uint8_t bID; +} sDbgPort; + +/*---------------------------------------------------------------------------- + * Variables + *----------------------------------------------------------------------------*/ + +/** Pins for DBGU */ +static const Pin pinsDbgu[] = {PINS_DBGU}; +/** Pins for USART0 */ +static const Pin pinsUs0[] = {PIN_USART0_TXD, PIN_USART0_RXD}; +/** Pins for USART1 */ +static const Pin pinsUs1[] = {PIN_USART1_TXD, PIN_USART1_RXD}; + +/** Uses DBGU as debug port */ +static sDbgPort dbgpDbgu = +{ + DBGU, + pinsDbgu, PIO_LISTSIZE(pinsDbgu), + ID_DBGU +}; +/** Uses USART0 as debug port */ +static sDbgPort dbgpUs0 = +{ + USART0, + pinsUs0, PIO_LISTSIZE(pinsUs0), + ID_USART0 +}; + +/** Uses USART0 as debug port */ +static sDbgPort dbgpUs1 = +{ + USART1, + pinsUs1, PIO_LISTSIZE(pinsUs1), + ID_USART1 +}; + +/** Current used debug port */ +static sDbgPort *pDbgPort = &dbgpDbgu; +/** Console initialize status */ +uint8_t _bConsoleIsInitialized = 0; + +/** + * \brief Select USART0 as DBGU port. + */ +void DBGU_ConsoleUseUSART0(void) +{ + pDbgPort = &dbgpUs0; + _bConsoleIsInitialized = 0; +} +/** + * \brief Select USART1 as DBGU port. + */ +void DBGU_ConsoleUseUSART1(void) +{ + pDbgPort = &dbgpUs1; + _bConsoleIsInitialized = 0; +} + +/** + * \brief Select DBGU as DBGU port. + */ +void DBGU_ConsoleUseDBGU(void) +{ + pDbgPort = &dbgpDbgu; + _bConsoleIsInitialized = 0; +} + +/** + * \brief Configures an DBGU peripheral with the specified parameters. + * + * \param baudrate Baudrate at which the DBGU should operate (in Hz). + * \param masterClock Frequency of the system master clock (in Hz). + */ +extern void DBGU_Configure( uint32_t baudrate, uint32_t masterClock) +{ + + /* Configure PIO */ + PIO_Configure(CONSOLE_PINLIST, CONSOLE_PINLISTSIZE); + + if ( ID_NOTUSED != CONSOLE_ID ) + { + PMC_EnablePeripheral(CONSOLE_ID); + } + + /* Configure mode register */ + if (CONSOLE_DBGU!= DBGU ) { + CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE | US_MR_CHRL_8_BIT; + } + else { + CONSOLE_DBGU->DBGU_MR = DBGU_MR_CHMODE_NORM | DBGU_MR_PAR_NONE; + } + /* Reset and disable receiver & transmitter */ + CONSOLE_DBGU->DBGU_CR = DBGU_CR_RSTRX | DBGU_CR_RSTTX; + CONSOLE_DBGU->DBGU_IDR = 0xFFFFFFFF; + CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXDIS | DBGU_CR_TXDIS; + /* Configure baudrate */ + CONSOLE_DBGU->DBGU_BRGR = (masterClock / baudrate) / 16; + /* Enable receiver and transmitter */ + CONSOLE_DBGU->DBGU_CR = DBGU_CR_RXEN | DBGU_CR_TXEN; + _bConsoleIsInitialized = 1 ; +#if defined(__GNUC__) + setvbuf(stdout, (char*)NULL, _IONBF, 0); +#endif +} + +/** + * \brief Outputs a character on the DBGU line. + * + * \note This function is synchronous (i.e. uses polling). + * \param c Character to send. + */ +extern void DBGU_PutChar( uint8_t c ) +{ + if ( !_bConsoleIsInitialized ) + { + DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK); + } + + /* Wait for the transmitter to be ready */ + while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_TXEMPTY) == 0 ) ; + + /* Send character */ + CONSOLE_DBGU->DBGU_THR=c ; +} + +/** + * \brief Input a character from the DBGU line. + * + * \note This function is synchronous + * \return character received. + */ +extern uint32_t DBGU_GetChar( void ) +{ + if ( !_bConsoleIsInitialized ) + { + DBGU_Configure(CONSOLE_BAUDRATE, BOARD_MCK); + } + + while ( (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) == 0 ) ; + return CONSOLE_DBGU->DBGU_RHR ; +} + +/** + * \brief Check if there is Input from DBGU line. + * + * \return true if there is Input. + */ +extern uint32_t DBGU_IsRxReady( void ) +{ + if ( !_bConsoleIsInitialized ) + { + //DBGU_Configure( CONSOLE_BAUDRATE, BOARD_MCK ) ; + } + return (CONSOLE_DBGU->DBGU_SR & DBGU_SR_RXRDY) > 0 ; +} + +/** + * Displays the content of the given frame on the DBGU. + * + * \param pucFrame Pointer to the frame to dump. + * \param dwSize Buffer size in bytes. + */ +extern void DBGU_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) +{ + uint32_t dw ; + + for ( dw=0 ; dw < dwSize ; dw++ ) + { + printf( "%02X ", pucFrame[dw] ) ; + } + + printf( "\n\r" ) ; +} + +/** + * Displays the content of the given buffer on the DBGU. + * + * \param pucBuffer Pointer to the buffer to dump. + * \param dwSize Buffer size in bytes. + * \param dwAddress Start address to display + */ +extern void DBGU_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) +{ + uint32_t i ; + uint32_t j ; + uint32_t dwLastLineStart ; + uint8_t* pucTmp ; + + for ( i=0 ; i < (dwSize / 16) ; i++ ) + { + printf( "0x%08X: ", (unsigned int )(dwAddress + ( i * 16) )) ; + pucTmp = (uint8_t*)&pucBuffer[i*16] ; + + for ( j=0 ; j < 4 ; j++ ) + { + printf( "%02X%02X%02X%02X ", pucTmp[0], pucTmp[1], pucTmp[2], pucTmp[3] ) ; + pucTmp += 4 ; + } + + pucTmp=(uint8_t*)&pucBuffer[i*16] ; + + for ( j=0 ; j < 16 ; j++ ) + { + DBGU_PutChar( *pucTmp++ ) ; + } + + printf( "\n\r" ) ; + } + + if ( (dwSize%16) != 0 ) + { + dwLastLineStart=dwSize - (dwSize%16) ; + + printf( "0x%08X: ", (unsigned int ) (dwAddress + dwLastLineStart )) ; + for ( j=dwLastLineStart ; j < dwLastLineStart+16 ; j++ ) + { + if ( (j!=dwLastLineStart) && (j%4 == 0) ) + { + printf( " " ) ; + } + + if ( j < dwSize ) + { + printf( "%02X", pucBuffer[j] ) ; + } + else + { + printf(" ") ; + } + } + + printf( " " ) ; + for ( j=dwLastLineStart ; j < dwSize ; j++ ) + { + DBGU_PutChar( pucBuffer[j] ) ; + } + + printf( "\n\r" ) ; + } +} + +/** + * Reads an integer + * + * \param pdwValue Pointer to the uint32_t variable to contain the input value. + */ +extern uint32_t DBGU_GetInteger( uint32_t* pdwValue ) +{ + uint8_t ucKey ; + uint8_t ucNbNb=0 ; + uint32_t dwValue=0 ; + + while ( 1 ) + { + ucKey=DBGU_GetChar() ; + DBGU_PutChar( ucKey ) ; + + if ( ucKey >= '0' && ucKey <= '9' ) + { + dwValue = (dwValue * 10) + (ucKey - '0'); + ucNbNb++ ; + } + else + { + if ( ucKey == 0x0D || ucKey == ' ' ) + { + if ( ucNbNb == 0 ) + { + printf( "\n\rWrite a number and press ENTER or SPACE!\n\r" ) ; + return 0 ; + } + else + { + printf( "\n\r" ) ; + *pdwValue=dwValue ; + + return 1 ; + } + } + else + { + printf( "\n\r'%c' not a number!\n\r", ucKey ) ; + + return 0 ; + } + } + } +} + +/** + * Reads an integer and check the value + * + * \param pdwValue Pointer to the uint32_t variable to contain the input value. + * \param dwMin Minimum value + * \param dwMax Maximum value + */ +extern uint32_t DBGU_GetIntegerMinMax( uint32_t* pdwValue, uint32_t dwMin, uint32_t dwMax ) +{ + uint32_t dwValue=0 ; + + if ( DBGU_GetInteger( &dwValue ) == 0 ) + { + return 0 ; + } + + if ( dwValue < dwMin || dwValue > dwMax ) + { + printf( "\n\rThe number have to be between %u and %u\n\r", (unsigned int)dwMin, (unsigned int)dwMax ) ; + + return 0 ; + } + + printf( "\n\r" ) ; + + *pdwValue = dwValue ; + + return 1 ; +} + +/** + * Reads an hexadecimal number + * + * \param pdwValue Pointer to the uint32_t variable to contain the input value. + */ +extern uint32_t DBGU_GetHexa32( uint32_t* pdwValue ) +{ + uint8_t ucKey ; + uint32_t dw = 0 ; + uint32_t dwValue = 0 ; + + for ( dw=0 ; dw < 8 ; dw++ ) + { + ucKey = DBGU_GetChar() ; + DBGU_PutChar( ucKey ) ; + + if ( ucKey >= '0' && ucKey <= '9' ) + { + dwValue = (dwValue * 16) + (ucKey - '0') ; + } + else + { + if ( ucKey >= 'A' && ucKey <= 'F' ) + { + dwValue = (dwValue * 16) + (ucKey - 'A' + 10) ; + } + else + { + if ( ucKey >= 'a' && ucKey <= 'f' ) + { + dwValue = (dwValue * 16) + (ucKey - 'a' + 10) ; + } + else + { + printf( "\n\rIt is not a hexa character!\n\r" ) ; + + return 0 ; + } + } + } + } + + printf("\n\r" ) ; + *pdwValue = dwValue ; + + return 1 ; +} + +#if defined __ICCARM__ /* IAR Ewarm 5.41+ */ +/** + * \brief Outputs a character on the DBGU. + * + * \param c Character to output. + * + * \return The character that was output. + */ +extern WEAK signed int putchar( signed int c ) +{ + DBGU_PutChar( c ) ; + + return c ; +} +#endif // defined __ICCARM__ + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dma_hardware_interface.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dma_hardware_interface.c new file mode 100644 index 000000000..f1a5dac10 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dma_hardware_interface.c @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup dmad_module + * + * \section DmaHw Dma Hardware Interface Usage + *
    + *
  • The DMA controller can handle the transfer between peripherals and memory + * and so receives the triggers from the peripherals. The hardware interface number + * are getting from DMAIF_Get_ChannelNumber().
    • + + *
  • DMAIF_IsValidatedPeripherOnDma() helps to check if the given DMAC has associated + * peripheral identifier coded by the given peripheral.
    • + * + *
+*/ +/*@{*/ +/*@}*/ + +/** \file */ + /*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ +/** Array of DMA Channel definition for SAMA5 chip*/ +static const DmaHardwareInterface dmaHwIf[] = { + /* dmac, peripheral, T/R, Channel Number*/ + {0, ID_HSMCI0, 0, 0}, + {0, ID_HSMCI0, 1, 0}, + {0, ID_SPI0, 0, 1}, + {0, ID_SPI0, 1, 2}, + {0, ID_USART0, 0, 3}, + {0, ID_USART0, 1, 4}, + {0, ID_USART1, 0, 5}, + {0, ID_USART1, 1, 6}, + {0, ID_TWI0, 0, 7}, + {0, ID_TWI0, 1, 8}, + {0, ID_TWI1, 0, 9}, + {0, ID_TWI1, 1, 10}, + {0, ID_UART0, 0, 11}, + {0, ID_UART0, 1, 12}, + {0, ID_SSC0, 0, 13}, + {0, ID_SSC0, 1, 14}, + /* dmac 1 */ + {1, ID_HSMCI1, 0, 0}, + {1, ID_HSMCI1, 1, 0}, + {1, ID_HSMCI2, 0, 1}, + {1, ID_HSMCI2, 1, 1}, + {1, ID_ADC, 1, 2}, + {1, ID_SSC1, 0, 3}, + {1, ID_SSC1, 1, 4}, + {1, ID_UART1, 0, 5}, + {1, ID_UART1, 1, 6}, + {1, ID_USART2, 0, 7}, + {1, ID_USART2, 1, 8}, + {1, ID_USART3, 0, 9}, + {1, ID_USART3, 1, 10}, + {1, ID_TWI2, 0, 11}, + {1, ID_TWI2, 1, 12}, + {1, ID_DBGU, 0, 13}, + {1, ID_DBGU, 1, 14}, + {1, ID_SPI1, 0, 15}, + {1, ID_SPI1, 1, 16}, + {1, ID_SHA, 0, 17}, + {1, ID_AES, 0, 18}, + {1, ID_AES, 1, 19}, + {1, ID_TDES, 0, 20}, + {1, ID_TDES, 1, 21} +}; + +/*---------------------------------------------------------------------------- + * Consts + *----------------------------------------------------------------------------*/ + /** Number of recognized peripheral identifier code for DMA0/1. */ +#define NUMPERIPHERAL (sizeof(dmaHwIf) / sizeof (DmaHardwareInterface)) + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Get peripheral identifier coded for hardware handshaking interface + * + * \param bDmac DMA Controller number. + * \param bPeriphID Peripheral ID. + * \param bTransfer Transfer type 0: Tx, 1 :Rx. + * \return 0-15 peripheral identifier coded. + * 0xff : no associated peripheral identifier coded. + */ +uint8_t DMAIF_Get_ChannelNumber (uint8_t bDmac, + uint8_t bPeriphID, + uint8_t bTransfer) +{ + uint8_t i; + for (i = 0; i < NUMPERIPHERAL; i++) + { + if ((dmaHwIf[i].bDmac == bDmac) && (dmaHwIf[i].bPeriphID == bPeriphID) && (dmaHwIf[i].bTransfer == bTransfer)) + { + return dmaHwIf[i].bIfID; + } + } + return 0xff; +} + +/** + * \brief Check if the given DMAC has associated peripheral identifier coded by + * the given peripheral. + * + * \param bDmac DMA Controller number. + * \param bPeriphID Peripheral ID (0xff : memory only). + * \return 1: Is a validated peripher. 0: no associated peripheral identifier coded. + */ +uint8_t DMAIF_IsValidatedPeripherOnDma( uint8_t bDmac, uint8_t bPeriphID) +{ + uint8_t i; + /* It is always validated when transfer to memory */ + if (bPeriphID == 0xFF) { + return 1; + } + for (i = 0; i < NUMPERIPHERAL; i++) + { + if ((dmaHwIf[i].bDmac == bDmac) && (dmaHwIf[i].bPeriphID == bPeriphID)) + { + return 1; + } + } + return 0; +} + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dmad.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dmad.c new file mode 100644 index 000000000..fff110d1a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/dmad.c @@ -0,0 +1,610 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup dmad_module + * + * \section DmaConfig Dma Configuration Usage + * + * To configure a DMA channel, the user has to follow these few steps : + *
    + *
  • Initialize a DMA driver instance by DMAD_Initialize().
    • + *
  • choose an available (disabled) channel using DMAD_AllocateChannel().
    • + *
  • After the DMAC selected channel has been programmed, DMAD_PrepareChannel() is to enable + * clock and dma peripheral of the DMA, and set Configuration register to set up the transfer type + * (memory or non-memory peripheral for source and destination) and flow control device.
    • + *
  • Configure DMA multi-buffer transfers using DMAD_PrepareMultiTransfer() to set up the chain of Linked List Items, + * single-buffer transfers using DMAD_PrepareSingleTransfer().
    • + *
  • Invoke DMAD_StartTransfer() to start DMA transfer, or DMAD_StopTransfer() to force stop DMA transfer.
    • + *
  • If picture-in-picture mode is enabled, DMAD_ConfigurePIP() helps to configure PIP mode.
    • + *
  • Once the buffer of data is transferred, DMAD_IsTransferDone() checks if DMA transfer is finished.
    • + *
  • DMAD_Handler() handles DMA interrupt, and invoking DMAD_SetCallback() if provided.
    • + *
+ * + * Related files:\n + * \ref dmad.h\n + * \ref dmad.c.\n + */ + +/** \file */ + +/** \addtogroup dmad_functions + @{*/ + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Try to allocate a DMA channel for on given controller. + * \param pDmad Pointer to DMA driver instance. + * \param bDmac DMA controller ID (0 ~ 1). + * \param bSrcID Source peripheral ID, 0xFF for memory. + * \param bDstID Destination peripheral ID, 0xFF for memory. + * \return Channel number if allocation sucessful, return + * DMAD_ALLOC_FAILED if allocation failed. + */ +static uint32_t DMAD_AllocateDmacChannel( sDmad *pDmad, + uint8_t bDmac, + uint8_t bSrcID, + uint8_t bDstID) +{ + uint32_t i; + + /* Can't support peripheral to peripheral */ + if ((( bSrcID != DMAD_TRANSFER_MEMORY ) && ( bDstID != DMAD_TRANSFER_MEMORY ))) + { + return DMAD_ALLOC_FAILED; + } + /* dma transfer from peripheral to memory */ + if ( bDstID == DMAD_TRANSFER_MEMORY) + { + if( (!DMAIF_IsValidatedPeripherOnDma(bDmac, bSrcID)) ) + { + return DMAD_ALLOC_FAILED; + } + } + /* dma transfer from memory to peripheral */ + if ( bSrcID == DMAD_TRANSFER_MEMORY ) + { + if( (!DMAIF_IsValidatedPeripherOnDma(bDmac, bDstID)) ) + { + return DMAD_ALLOC_FAILED; + } + } + for (i = 0; i < pDmad->numChannels; i ++) + { + if ( pDmad->dmaChannels[bDmac][i].state == DMAD_FREE ) + { + /* Allocate the channel */ + pDmad->dmaChannels[bDmac][i].state = DMAD_IN_USE; + /* Get general informations */ + pDmad->dmaChannels[bDmac][i].bSrcPeriphID = bSrcID; + pDmad->dmaChannels[bDmac][i].bDstPeriphID = bDstID; + pDmad->dmaChannels[bDmac][i].bSrcTxIfID = + DMAIF_Get_ChannelNumber(bDmac, bSrcID, 0); + pDmad->dmaChannels[bDmac][i].bSrcRxIfID = + DMAIF_Get_ChannelNumber(bDmac, bSrcID, 1); + pDmad->dmaChannels[bDmac][i].bDstTxIfID = + DMAIF_Get_ChannelNumber(bDmac, bDstID, 0); + pDmad->dmaChannels[bDmac][i].bDstTxIfID = + DMAIF_Get_ChannelNumber(bDmac, bDstID, 1); + + return ((bDmac << 8)) | ((i) & 0xFF); + } + } + return DMAD_ALLOC_FAILED; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Initialize DMA driver instance. + * \param pDmad Pointer to DMA driver instance. + * \param bPollingMode Polling DMA transfer: + * 1. Via DMAD_IsTransferDone(); or + * 2. Via DMAD_Handler(). + */ +void DMAD_Initialize( sDmad *pDmad, + uint8_t bPollingMode ) +{ + uint32_t i, j; + + assert( pDmad != NULL ) ; + + pDmad->pDmacs[0] = DMAC0; + pDmad->pDmacs[1] = DMAC1; + pDmad->pollingMode = bPollingMode; + pDmad->numControllers = 2; + pDmad->numChannels = 8; + + for (i = 0; i < pDmad->numControllers; i ++) + { + for (j = 0; j < pDmad->numChannels; j ++) + { + pDmad->dmaChannels[i][j].fCallback = 0; + pDmad->dmaChannels[i][j].pArg = 0; + + pDmad->dmaChannels[i][j].bIrqOwner = 0; + pDmad->dmaChannels[i][j].bSrcPeriphID = 0; + pDmad->dmaChannels[i][j].bDstPeriphID = 0; + pDmad->dmaChannels[i][j].bSrcTxIfID = 0; + pDmad->dmaChannels[i][j].bSrcRxIfID = 0; + pDmad->dmaChannels[i][j].bDstTxIfID = 0; + pDmad->dmaChannels[i][j].bDstRxIfID = 0; + + pDmad->dmaChannels[i][j].state = DMAD_FREE; + } + } +} + +/** + * \brief DMA interrupt handler + * \param pDmad Pointer to DMA driver instance. + */ +void DMAD_Handler( sDmad *pDmad ) +{ + Dmac *pDmac; + sDmadChannel *pCh; + uint32_t _iController, iChannel; + uint32_t dmaSr, chSr; + uint32_t dmaRc = DMAD_OK; + + assert( pDmad != NULL ) ; + + for (_iController = 0; _iController < pDmad->numControllers; _iController ++) + { + pDmac = pDmad->pDmacs[_iController]; + + /* Check raw status but not masked one for polling mode support */ + dmaSr = DMAC_GetStatus( pDmac ); + if ((dmaSr & 0x00FFFFFF) == 0) continue; + + chSr = DMAC_GetChannelStatus( pDmac ); + //printf("iDma(%x,%x)\n\r", dmaSr, chSr); + + for (iChannel = 0; iChannel < pDmad->numChannels; iChannel ++) + { + uint8_t bExec = 1; + + pCh = &pDmad->dmaChannels[_iController][iChannel]; + /* Error */ + if (dmaSr & (DMAC_EBCIDR_ERR0 << iChannel)) + { + DMAC_DisableChannel( pDmac, iChannel ); + if (pCh->state > DMAD_IN_USE) pCh->state = DMAD_STALL; + dmaRc = DMAD_ERROR; + } + /* Chained buffer complete */ + else if (dmaSr & (DMAC_EBCIDR_CBTC0 << iChannel)) + { + DMAC_DisableChannel( pDmac, iChannel ); + if (pCh->state > DMAD_IN_USE) pCh->state = DMAD_IN_USE; + dmaRc = DMAD_OK; + + } + /* Buffer complete */ + else if (dmaSr & (DMAC_EBCIDR_BTC0 << iChannel)) + { + dmaRc = DMAD_PARTIAL_DONE; + /* Re-enable */ + if ((chSr & (DMAC_CHSR_ENA0 << iChannel)) == 0) + { + DMAC_EnableChannel( pDmac, iChannel ); + } + } + else + { + bExec = 0; + } + /* Execute callback */ + if (bExec && pCh->fCallback) + { + pCh->fCallback(dmaRc, pCh->pArg); + } + } + } +} + +/** + * \brief Allocate a DMA channel for upper layer. + * \param pDmad Pointer to DMA driver instance. + * \param bSrcID Source peripheral ID, 0xFF for memory. + * \param bDstID Destination peripheral ID, 0xFF for memory. + * \return Channel number if allocation sucessful, return + * DMAD_ALLOC_FAILED if allocation failed. + */ +uint32_t DMAD_AllocateChannel( sDmad *pDmad, + uint8_t bSrcID, + uint8_t bDstID) +{ + uint32_t _iController; + uint32_t _dwChannel = DMAD_ALLOC_FAILED; + + for ( _iController = 0; _iController < pDmad->numControllers; _iController ++) + { + _dwChannel = DMAD_AllocateDmacChannel( pDmad, _iController, + bSrcID, bDstID ); + if (_dwChannel != DMAD_ALLOC_FAILED) + break; + } + return _dwChannel; +} + +/** + * \brief Free the specified DMA channel. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eDmadRC DMAD_FreeChannel( sDmad *pDmad, uint32_t _dwChannel ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + switch ( pDmad->dmaChannels[_iController][iChannel].state ) + { + + case DMAD_IN_XFR: + return DMAD_BUSY; + + case DMAD_IN_USE: + pDmad->dmaChannels[_iController][iChannel].state = DMAD_FREE; + break; + } + return DMAD_OK; +} + +/** + * \brief Set the callback function for DMA channel transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + * \param fCallback Pointer to callback function. + * \param pArg Pointer to optional argument for callback. + */ +eDmadRC DMAD_SetCallback( sDmad *pDmad, uint32_t _dwChannel, + DmadTransferCallback fCallback, void* pArg ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + return DMAD_BUSY; + + pDmad->dmaChannels[_iController][iChannel].fCallback = fCallback; + pDmad->dmaChannels[_iController][iChannel].pArg = pArg; + + return DMAD_OK; +} + +/** + * \brief Configure Picture-in-Picture mode for DMA transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + * \param srcPIP Source PIP setting. + * \param dstPIP Destination PIP setting. + */ +eDmadRC DMAD_ConfigurePIP( sDmad *pDmad, + uint32_t _dwChannel, + uint32_t dwSrcPIP, + uint32_t dwDstPIP ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + Dmac *pDmac = pDmad->pDmacs[_iController]; + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + return DMAD_BUSY; + + DMAC_SetPipMode(pDmac, iChannel, dwSrcPIP, dwDstPIP); + return DMAD_OK; +} + +/** + * \brief Enable clock of the DMA peripheral, Enable the dma peripheral, + * configure configuration register for DMA transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + * \param dwCfg Configuration value. + */ +eDmadRC DMAD_PrepareChannel( sDmad *pDmad, + uint32_t _dwChannel, + uint32_t dwCfg ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + uint32_t _dwdmaId; + + assert( pDmad != NULL ) ; + Dmac *pDmac = pDmad->pDmacs[_iController]; + + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + return DMAD_BUSY; + DMAC_SetCFG( pDmac, iChannel, dwCfg ); + + _dwdmaId = (_iController == 0) ? ID_DMAC0 : ID_DMAC1; + /* Enable clock of the DMA peripheral */ + if (!PMC_IsPeriphEnabled( _dwdmaId )) + { + PMC_EnablePeripheral( _dwdmaId ); + } + /* Enables the DMAC peripheral. */ + DMAC_Enable( pDmac ); + /* Disables DMAC interrupt for the given channel. */ + DMAC_DisableIt (pDmac, + (DMAC_EBCIDR_BTC0 << iChannel) + |(DMAC_EBCIDR_CBTC0 << iChannel) + |(DMAC_EBCIDR_ERR0 << iChannel) ); + /* Disable the given dma channel. */ + DMAC_DisableChannel( pDmac, iChannel ); + /* Clear dummy status */ + DMAC_GetChannelStatus( pDmac ); + DMAC_GetStatus (pDmac); + return DMAD_OK; +} + +/** + * \brief Check if DMA transfer is finished. + * In polling mode DMAD_Handler() is polled. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eDmadRC DMAD_IsTransferDone( sDmad *pDmad, uint32_t _dwChannel ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + { + if ( pDmad->pollingMode ) DMAD_Handler( pDmad ); + return DMAD_BUSY; + } + return DMAD_OK; +} + +/** + * \brief Clear the automatic mode that services the next-to-last + buffer transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + */ +void DMAD_ClearAuto( sDmad *pDmad, uint32_t _dwChannel ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + Dmac *pDmac; + assert( pDmad != NULL ) ; + + pDmac = pDmad->pDmacs[_iController]; + DMAC_DisableAutoMode( pDmac, iChannel ); +} + +/** + * \brief Start DMA transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eDmadRC DMAD_StartTransfer( sDmad *pDmad, uint32_t _dwChannel ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + Dmac *pDmac = pDmad->pDmacs[_iController]; + + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + else if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + return DMAD_BUSY; + /* Change state to transferring */ + pDmad->dmaChannels[_iController][iChannel].state = DMAD_IN_XFR; + + if ( pDmad->pollingMode == 0 ) + { + /* Monitor status in interrupt handler */ + DMAC_EnableIt(pDmac, (DMAC_EBCIDR_BTC0 << iChannel) + |(DMAC_EBCIDR_CBTC0 << iChannel) + |(DMAC_EBCIDR_ERR0 << iChannel) ); + } + DMAC_EnableChannel(pDmac, iChannel); + return DMAD_OK; +} + +/** + * \brief Start DMA transfers on the same controller. + * \param pDmad Pointer to DMA driver instance. + * \param bDmac DMA Controller number. + * \param bmChannels Channels bitmap. + */ +eDmadRC DMAD_StartTransfers( sDmad *pDmad, uint8_t bDmac, uint32_t bmChannels ) +{ + uint32_t iChannel; + uint32_t bmChs = 0, bmIts = 0; + + assert( pDmad != NULL ) ; + Dmac *pDmac = pDmad->pDmacs[bDmac]; + + for (iChannel = 0; iChannel < pDmad->numChannels; iChannel ++) + { + uint32_t bmChBit = 1 << iChannel; + + /* Skipped channels */ + if ( pDmad->dmaChannels[bDmac][iChannel].state == DMAD_FREE ) + continue; + else if ( pDmad->dmaChannels[bDmac][iChannel].state == DMAD_IN_XFR ) + continue; + /* Log to start bit map */ + if (bmChannels & bmChBit) + { + bmChs |= bmChBit; + bmIts |= ( (DMAC_EBCIDR_BTC0 << iChannel) + |(DMAC_EBCIDR_CBTC0 << iChannel) + |(DMAC_EBCIDR_ERR0 << iChannel) ); + /* Change state */ + pDmad->dmaChannels[bDmac][iChannel].state = DMAD_IN_XFR; + } + } + + DMAC_EnableChannels(pDmac, bmChs); + if ( pDmad->pollingMode == 0 ) + { + /* Monitor status in interrupt handler */ + DMAC_EnableIt( pDmac, bmIts ); + } + + return DMAD_OK; +} + +/** + * \brief Stop DMA transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eDmadRC DMAD_StopTransfer( sDmad *pDmad, uint32_t _dwChannel ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + Dmac *pDmac = pDmad->pDmacs[_iController]; + sDmadChannel *pCh = &pDmad->dmaChannels[_iController][iChannel]; + + uint32_t to = 0x1000; + + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + + if ( pDmad->dmaChannels[_iController][iChannel].state != DMAD_IN_XFR ) + return DMAD_OK; + + /* Suspend */ + DMAC_SuspendChannel(pDmac, iChannel); + + /* Poll empty */ + for (;to; to --) + { + if (DMAC_GetChannelStatus(pDmac) & (DMAC_CHSR_EMPT0 << iChannel)) + { + break; + } + } + + /* Disable channel */ + DMAC_DisableChannel(pDmac, iChannel); + /* Disable interrupts */ + DMAC_DisableIt(pDmac, (DMAC_EBCIDR_BTC0 << iChannel) + |(DMAC_EBCIDR_CBTC0 << iChannel) + |(DMAC_EBCIDR_ERR0 << iChannel) ); + /* Clear pending status */ + DMAC_GetChannelStatus(pDmac); + DMAC_GetStatus(pDmac); + /* Resume */ + DMAC_RestoreChannel(pDmac, iChannel); + /* Change state */ + pDmad->dmaChannels[_iController][iChannel].state = DMAD_IN_USE; + /* Invoke callback */ + if (pCh->fCallback) pCh->fCallback(DMAD_CANCELED, pCh->pArg); + return DMAD_OK; +} + +/** + * \brief Configure DMA for a single transfer. + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eDmadRC DMAD_PrepareSingleTransfer( sDmad *pDmad, + uint32_t _dwChannel, + sDmaTransferDescriptor *pXfrDesc ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + Dmac *pDmac = pDmad->pDmacs[_iController]; + + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + return DMAD_BUSY; + + DMAC_SetSourceAddr(pDmac, iChannel, pXfrDesc->dwSrcAddr); + DMAC_SetDestinationAddr(pDmac, iChannel, pXfrDesc->dwDstAddr); + DMAC_SetDescriptorAddr(pDmac, iChannel, 0, 0); + DMAC_SetControlA(pDmac, iChannel, pXfrDesc->dwCtrlA); + DMAC_SetControlB(pDmac, iChannel, pXfrDesc->dwCtrlB); + + return DMAD_OK; +} + +/** + * \brief Configure DMA multi-buffer transfers using linked lists + * \param pDmad Pointer to DMA driver instance. + * \param _dwChannel ControllerNumber << 8 | ChannelNumber. + * \param pXfrDesc Pointer to DMA Linked List. + */ +eDmadRC DMAD_PrepareMultiTransfer( sDmad *pDmad, + uint32_t _dwChannel, + sDmaTransferDescriptor *pXfrDesc ) +{ + uint8_t _iController = (_dwChannel >> 8); + uint8_t iChannel = (_dwChannel) & 0xFF; + + assert( pDmad != NULL ) ; + Dmac *pDmac = pDmad->pDmacs[_iController]; + + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_FREE ) + return DMAD_ERROR; + if ( pDmad->dmaChannels[_iController][iChannel].state == DMAD_IN_XFR ) + return DMAD_BUSY; + + DMAC_SetDescriptorAddr( pDmac, iChannel, (uint32_t)pXfrDesc, 0 ); + DMAC_SetControlB( pDmac, iChannel, 0); + + return DMAD_OK; +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/emacd.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/emacd.c new file mode 100644 index 000000000..69eaa8afa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/emacd.c @@ -0,0 +1,712 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include +#include + +/** \addtogroup EMACD_defines + @{*/ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** Error bits for TX */ +#define EMAC_TX_ERR_BITS \ + (EMAC_TXD_bmERROR | EMAC_TXD_bmUNDERRUN | EMAC_TXD_bmEXHAUSTED) + +/*--------------------------------------------------------------------------- + * Circular buffer management + *---------------------------------------------------------------------------*/ + +/** Return count in buffer */ +#define CIRC_CNT(head,tail,size) (((head) - (tail)) % (size)) + +/** Return space available, 0..size-1. always leave one free char as a completely full buffer + has head == tail, which is the same as empty */ +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +/** Return count up to the end of the buffer. Carefully avoid accessing head and tail more than once, + so they can change underneath us without returning inconsistent results */ +#define CIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = ((head) + end) % (size); \ + n < end ? n : end;}) + +/** Return space available up to the end of the buffer */ +#define CIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) % (size); \ + n <= end ? n : end+1;}) + +/** Increment head or tail */ +#define CIRC_INC(headortail,size) \ + headortail++; \ + if(headortail >= size) { \ + headortail = 0; \ + } + +/** Circular buffer is empty ? */ +#define CIRC_EMPTY(head, tail) (head == tail) + +/** Clear circular buffer */ +#define CIRC_CLEAR(head, tail) (head = tail = 0) + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Internal variables + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ + +/** + * Disable TX & reset registers and descriptor list + * \param pDrv Pointer to EMAC Driver instance. + */ +static void EMACD_ResetTx(sEmacd *pDrv) +{ + Emac *pHw = pDrv->pHw; + uint8_t *pTxBuffer = pDrv->pTxBuffer; + sEmacTxDescriptor *pTd = pDrv->pTxD; + + uint32_t Index; + uint32_t Address; + + /* Disable TX */ + EMAC_TransmitEnable(pHw, 0); + + /* Setup the TX descriptors. */ + CIRC_CLEAR(pDrv->wTxHead, pDrv->wTxTail); + for(Index = 0; Index < pDrv->wTxListSize; Index++) + { + Address = (uint32_t)(&(pTxBuffer[Index * EMAC_TX_UNITSIZE])); + pTd[Index].addr = Address; + pTd[Index].status.val = EMAC_TXD_bmUSED; + } + pTd[pDrv->wTxListSize - 1].status.val = EMAC_TXD_bmUSED | EMAC_TXD_bmWRAP; + + /* Transmit Buffer Queue Pointer Register */ + EMAC_SetTxQueue(pHw, (uint32_t)pTd); +} + +/** + * Disable RX & reset registers and descriptor list + * \param pDrv Pointer to EMAC Driver instance. + */ +static void EMACD_ResetRx(sEmacd *pDrv) +{ + Emac *pHw = pDrv->pHw; + uint8_t *pRxBuffer = pDrv->pRxBuffer; + sEmacRxDescriptor *pRd = pDrv->pRxD; + + uint32_t Index; + uint32_t Address; + + /* Disable RX */ + EMAC_ReceiveEnable(pHw, 0); + + /* Setup the RX descriptors. */ + pDrv->wRxI = 0; + for(Index = 0; Index < pDrv->wRxListSize; Index++) + { + Address = (uint32_t)(&(pRxBuffer[Index * EMAC_RX_UNITSIZE])); + /* Remove EMAC_RXD_bmOWNERSHIP and EMAC_RXD_bmWRAP */ + pRd[Index].addr.val = Address & EMAC_RXD_ADDR_MASK; + pRd[Index].status.val = 0; + } + pRd[pDrv->wRxListSize - 1].addr.val |= EMAC_RXD_bmWRAP; + + /* Receive Buffer Queue Pointer Register */ + EMAC_SetRxQueue(pHw, (uint32_t) pRd); +} + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * EMAC Interrupt handler + */ +void EMACD_Handler( sEmacd *pEmacd ) +{ + Emac *pHw = pEmacd->pHw; + uint32_t isr; + uint32_t rsr; + uint32_t tsr; + sEmacTxDescriptor *pTxTd; + fEmacdTransferCallback *pTxCb = NULL; + uint32_t rxStatusFlag; + uint32_t txStatusFlag; + + isr = EMAC_GetItStatus(pHw); + rsr = EMAC_GetRxStatus(pHw); + tsr = EMAC_GetTxStatus(pHw); + + isr &= ~(EMAC_GetItMask(pHw) | 0xFFC300); + + /* RX packet */ + if ((isr & EMAC_ISR_RCOMP) || (rsr & EMAC_RSR_REC)) + { + asm("nop"); + rxStatusFlag = EMAC_RSR_REC; + /* Check OVR */ + if (rsr & EMAC_RSR_OVR) + { + rxStatusFlag |= EMAC_RSR_OVR; + } + /* Check BNA */ + if (rsr & EMAC_RSR_BNA) + { + rxStatusFlag |= EMAC_RSR_BNA; + } + /* Clear status */ + EMAC_ClearRxStatus(pHw, rxStatusFlag); + + /* Invoke callbacks */ + if (pEmacd->fRxCb) + { + pEmacd->fRxCb(rxStatusFlag); + } + } + + /* TX packet */ + if ((isr & EMAC_ISR_TCOMP) || (tsr & EMAC_TSR_COMP)) { + asm("nop"); + txStatusFlag = EMAC_TSR_COMP; + + /* A frame transmitted */ + + /* Check RLE */ + if (tsr & EMAC_TSR_RLES) + { + /* Status RLE & Number of discarded buffers */ + txStatusFlag = EMAC_TSR_RLES + | CIRC_CNT(pEmacd->wTxHead, + pEmacd->wTxTail, + pEmacd->wTxListSize) + ; + pTxCb = &pEmacd->fTxCbList[pEmacd->wTxTail]; + EMACD_ResetTx(pEmacd); + TRACE_INFO("Tx RLE!!\n\r"); + EMAC_TransmitEnable(pHw, 1); + } + /* Check COL */ + if (tsr & EMAC_TSR_COL) + { + txStatusFlag |= EMAC_TSR_COL; + } + /* Check BEX */ + if (tsr & EMAC_TSR_BEX) + { + txStatusFlag |= EMAC_TSR_BEX; + } + /* Check UND */ + if (tsr & EMAC_TSR_UND) + { + txStatusFlag |= EMAC_TSR_UND; + } + /* Clear status */ + EMAC_ClearTxStatus(pHw, txStatusFlag); + + if (!CIRC_EMPTY(pEmacd->wTxHead, pEmacd->wTxTail)) + { + // Check the buffers + do { + pTxTd = &pEmacd->pTxD[pEmacd->wTxTail]; + pTxCb = &pEmacd->fTxCbList[pEmacd->wTxTail]; + /* Any error? + Exit if buffer has not been sent yet */ + if ((pTxTd->status.val & EMAC_TXD_bmUSED) == 0) + { + break; + } + + /* Notify upper layer that a packet has been sent */ + if (*pTxCb) + { + (*pTxCb)(txStatusFlag); + } + + CIRC_INC( pEmacd->wTxTail, pEmacd->wTxListSize ); + } while (CIRC_CNT(pEmacd->wTxHead, pEmacd->wTxTail, pEmacd->wTxListSize)); + } + + if (tsr & EMAC_TSR_RLES) + { + /* Notify upper layer RLE */ + if (*pTxCb) + { + (*pTxCb)(txStatusFlag); + } + } + + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, send will be successfull. */ + if( (CIRC_SPACE(pEmacd->wTxHead, + pEmacd->wTxTail, + pEmacd->wTxListSize) >= pEmacd->bWakeupThreshold) + && pEmacd->fWakupCb) + { + pEmacd->fWakupCb(); + } + } + + /* PAUSE Frame */ + if (isr & EMAC_ISR_PFRE) + { + TRACE_INFO("Pause!\n\r"); + } + if (isr & EMAC_ISR_PTZ) + { + TRACE_INFO("Pause TO!\n\r"); + } +} + +/** + * Initialize the EMAC Driver with HW settings. + * \param pEmacd Pointer to EMAC Driver instance. + * \param pHw Pointer to HW address for registers. + * \param bID HW ID for power management. + * \param bCAF Enable/Disable CopyAllFrame. + * \param bNBC Enable/Disable NoBroadCast. + */ +void EMACD_Init(sEmacd *pEmacd, + Emac *pHw, uint8_t bID, + uint8_t bCAF, uint8_t bNBC ) +{ + + TRACE_DEBUG("EMACD_Init\n\r"); + + /* Initialize struct */ + pEmacd->pHw = pHw; + pEmacd->bId = bID; + + /* Power ON */ + PMC_EnablePeripheral(bID); + + /* Disable TX & RX and more */ + EMAC_NetworkControl(pHw, 0); + EMAC_DisableIt(pHw, ~0u); + + EMAC_ClearStatistics(pHw); + + /* Clear all status bits in the receive status register. */ + EMAC_ClearRxStatus(pHw, EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA); + + /* Clear all status bits in the transmit status register */ + EMAC_ClearTxStatus(pHw, EMAC_TSR_UBR | EMAC_TSR_COL | EMAC_TSR_RLES + | EMAC_TSR_BEX | EMAC_TSR_COMP | EMAC_TSR_UND); + + /* Clear interrupts */ + EMAC_GetItStatus(pHw); + + /* Enable the copy of data into the buffers + ignore broadcasts, and don't copy FCS. */ + EMAC_Configure(pHw, EMAC_GetConfigure(pHw) | EMAC_NCFGR_DRFCS | EMAC_NCFGR_PAE); + + EMAC_CpyAllEnable(pHw, bCAF); + EMAC_BroadcastDisable(pHw, bNBC); + +} + +/** + * Initialize necessary allocated buffer lists for EMAC Driver to transfer data. + * Must be invoked after EMACD_Init() but before RX/TX start. + * \param pEmacd Pointer to EMAC Driver instance. + * \param pRxBuffer Pointer to allocated buffer for RX. The address should + * be 8-byte aligned and the size should be + * EMAC_RX_UNITSIZE * wRxSize. + * \param pRxD Pointer to allocated RX descriptor list. + * \param wRxSize RX size, in number of registered units (RX descriptors). + * \param pTxBuffer Pointer to allocated buffer for TX. The address should + * be 8-byte aligned and the size should be + * EMAC_TX_UNITSIZE * wTxSize. + * \param pTxD Pointer to allocated TX descriptor list. + * \param pTxCb Pointer to allocated TX callback list. + * \param wTxSize TX size, in number of registered units (TX descriptors). + * \return EMACD_OK or EMACD_PARAM. + * \note If input address is not 8-byte aligned the address is automatically + * adjusted and the list size is reduced by one. + */ +extern uint8_t EMACD_InitTransfer( sEmacd *pEmacd, + uint8_t *pRxBuffer, sEmacRxDescriptor *pRxD, + uint16_t wRxSize, + uint8_t *pTxBuffer, sEmacTxDescriptor *pTxD, fEmacdTransferCallback *pTxCb, + uint16_t wTxSize) +{ + Emac *pHw = pEmacd->pHw; + + if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return EMACD_PARAM; + + /* Assign RX buffers */ + if ( ((uint32_t)pRxBuffer & 0x7) + || ((uint32_t)pRxD & 0x7) ) + { + wRxSize --; + TRACE_DEBUG("RX list address adjusted\n\r"); + } + pEmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8); + pEmacd->pRxD = (sEmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8); + pEmacd->wRxListSize = wRxSize; + + /* Assign TX buffers */ + if ( ((uint32_t)pTxBuffer & 0x7) + || ((uint32_t)pTxD & 0x7) ) + { + wTxSize --; + TRACE_DEBUG("TX list address adjusted\n\r"); + } + pEmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8); + pEmacd->pTxD = (sEmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8); + pEmacd->wTxListSize = wTxSize; + pEmacd->fTxCbList = pTxCb; + + /* Reset TX & RX */ + EMACD_ResetRx(pEmacd); + EMACD_ResetTx(pEmacd); + + /* Enable Rx and Tx, plus the stats register. */ + EMAC_TransmitEnable(pHw, 1); + EMAC_ReceiveEnable(pHw, 1); + EMAC_StatisticsWriteEnable(pHw, 1); + + /* Setup the interrupts for TX (and errors) */ + EMAC_EnableIt(pHw, EMAC_IER_RXUBR + | EMAC_IER_TUND + | EMAC_IER_RLE + | EMAC_IER_TXERR + | EMAC_IER_TCOMP + | EMAC_IER_ROVR + | EMAC_IER_HRESP + | EMAC_IER_PFR + | EMAC_IER_PTZ); + return EMACD_OK; +} + +/** + * Reset TX & RX queue & statistics + * \param pEmacd Pointer to EMAC Driver instance. + */ +void EMACD_Reset(sEmacd *pEmacd) +{ + Emac *pHw = pEmacd->pHw; + + EMACD_ResetRx(pEmacd); + EMACD_ResetTx(pEmacd); + EMAC_NetworkControl(pHw, EMAC_NCR_TE | EMAC_NCR_RE + | EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT); +} + +/** + * Send a packet with EMAC. + * If the packet size is larger than transfer buffer size error returned. + * If packet transfer status is monitored, specify callback for each packet. + * \param pEmacd Pointer to EMAC Driver instance. + * \param buffer The buffer to be send + * \param size The size of buffer to be send + * \param fTxCb TX callback. + * \return EMACD_OK, EMACD_PARAM or EMACD_TX_BUSY. + */ +uint8_t EMACD_Send( sEmacd *pEmacd, + void *pBuffer, + uint32_t size, + fEmacdTransferCallback fTxCb ) +{ + Emac *pHw = pEmacd->pHw; + + volatile sEmacTxDescriptor *pTxTd; + volatile fEmacdTransferCallback *pfTxCb; + + TRACE_DEBUG("EMAC_Send\n\r"); + + /* Check parameter */ + if (size > EMAC_TX_UNITSIZE) { + TRACE_ERROR("EMAC driver does not split send packets."); + TRACE_ERROR("%d bytes max in one packet (%u bytes requested)\n\r", + EMAC_TX_UNITSIZE, (unsigned int)size); + return EMACD_PARAM; + } + + /* Pointers to the current TxTd */ + pTxTd = &pEmacd->pTxD[pEmacd->wTxHead]; + /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */ + if( CIRC_SPACE(pEmacd->wTxHead, pEmacd->wTxTail, pEmacd->wTxListSize) == 0) + { + //if ((pTxTd->status & EMAC_TXD_bmUSED) != 0) + { + //EMAC_ResetTx(); + //TRACE_WARNING("Circ Full but FREE TD found\n\r"); + //AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE; + } + //else + { + return EMACD_TX_BUSY; + } + } + + /* Pointers to the current Tx Callback */ + pfTxCb = &pEmacd->fTxCbList[pEmacd->wTxHead]; + /* Setup/Copy data to transmition buffer */ + if (pBuffer && size) + { + /* Driver manage the ring buffer */ + memcpy((void *)pTxTd->addr, pBuffer, size); + } + + /* Tx Callback */ + *pfTxCb = fTxCb; + /* Update TD status */ + + /* The buffer size defined is length of ethernet frame + so it's always the last buffer of the frame. */ + if (pEmacd->wTxHead == pEmacd->wTxListSize-1) + { + pTxTd->status.val = + (size & EMAC_TXD_LEN_MASK) | EMAC_TXD_bmLAST | EMAC_TXD_bmWRAP; + } + else + { + pTxTd->status.val = (size & EMAC_TXD_LEN_MASK) | EMAC_TXD_bmLAST; + } + + CIRC_INC(pEmacd->wTxHead, pEmacd->wTxListSize); + /* Now start to transmit if it is not already done */ + EMAC_TransmissionStart(pHw); + return EMACD_OK; +} + +/** + * Return current load of TX. + * \param pEmacd Pointer to EMAC Driver instance. + */ +uint32_t EMACD_TxLoad(sEmacd *pEmacd) +{ + uint16_t head = pEmacd->wTxHead; + uint16_t tail = pEmacd->wTxTail; + return CIRC_CNT(head, tail, pEmacd->wTxListSize); +} + +/** + * Receive a packet with EMAC + * If not enough buffer for the packet, the remaining data is lost but right + * frame length is returned. + * \param pEmacd Pointer to EMAC Driver instance. + * \param pFrame Buffer to store the frame + * \param frameSize Size of the frame + * \param pRcvSize Received size + * \return OK, no data, or frame too small + */ +uint8_t EMACD_Poll( sEmacd * pEmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize) +{ + uint16_t bufferLength; + uint32_t tmpFrameSize=0; + uint8_t *pTmpFrame=0; + uint32_t tmpIdx = pEmacd->wRxI; + volatile sEmacRxDescriptor *pRxTd = &pEmacd->pRxD[pEmacd->wRxI]; + char isFrame = 0; + + if (pFrame == NULL) return EMACD_PARAM; + + /* Set the default return value */ + *pRcvSize = 0; + + /* Process received RxTd */ + while ((pRxTd->addr.val & EMAC_RXD_bmOWNERSHIP) == EMAC_RXD_bmOWNERSHIP) + { + /* A start of frame has been received, discard previous fragments */ + if ((pRxTd->status.val & EMAC_RXD_bmSOF) == EMAC_RXD_bmSOF) + { + /* Skip previous fragment */ + while (tmpIdx != pEmacd->wRxI) + { + pRxTd = &pEmacd->pRxD[pEmacd->wRxI]; + pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP); + CIRC_INC(pEmacd->wRxI, pEmacd->wRxListSize); + } + /* Reset the temporary frame pointer */ + pTmpFrame = pFrame; + tmpFrameSize = 0; + /* Start to gather buffers in a frame */ + isFrame = 1; + } + + /* Increment the pointer */ + CIRC_INC(tmpIdx, pEmacd->wRxListSize); + asm("nop"); + /* Copy data in the frame buffer */ + if (isFrame) + { + if (tmpIdx == pEmacd->wRxI) + { + TRACE_INFO("no EOF (Invalid of buffers too small)\n\r"); + do + { + + pRxTd = &pEmacd->pRxD[pEmacd->wRxI]; + pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP); + CIRC_INC(pEmacd->wRxI, pEmacd->wRxListSize); + } while(tmpIdx != pEmacd->wRxI); + return EMACD_RX_NULL; + } + /* Copy the buffer into the application frame */ + bufferLength = EMAC_RX_UNITSIZE; + if ((tmpFrameSize + bufferLength) > frameSize) + { + bufferLength = frameSize - tmpFrameSize; + } + + memcpy(pTmpFrame, (void*)(pRxTd->addr.val & EMAC_RXD_ADDR_MASK), bufferLength); + pTmpFrame += bufferLength; + tmpFrameSize += bufferLength; + + /* An end of frame has been received, return the data */ + if ((pRxTd->status.val & EMAC_RXD_bmEOF) == EMAC_RXD_bmEOF) + { + + /* Frame size from the EMAC */ + *pRcvSize = (pRxTd->status.val & EMAC_RXD_LEN_MASK); + + TRACE_INFO("packet %d-%d (%d)\n\r", pEmacd->wRxI, tmpIdx, *pRcvSize); + /* All data have been copied in the application frame buffer => release TD */ + while (pEmacd->wRxI != tmpIdx) + { + pRxTd = &pEmacd->pRxD[pEmacd->wRxI]; + pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP); + CIRC_INC(pEmacd->wRxI, pEmacd->wRxListSize); + } + + /* Application frame buffer is too small all data have not been copied */ + if (tmpFrameSize < *pRcvSize) + { + TRACE_INFO("size req %u size allocated %u\n\r", (unsigned int)(*pRcvSize), (unsigned int)frameSize); + + return EMACD_SIZE_TOO_SMALL; + } + + return EMACD_OK; + } + } + /* SOF has not been detected, skip the fragment */ + else + { + pRxTd->addr.val &= ~(EMAC_RXD_bmOWNERSHIP); + pEmacd->wRxI = tmpIdx; + } + + /* Process the next buffer */ + pRxTd = &pEmacd->pRxD[tmpIdx]; + } + return EMACD_RX_NULL; +} + +/** + * Register/Clear RX callback. Callback will be invoked after the next received + * frame. + * + * When EMACD_Poll() returns EMACD_RX_NULL the application task call + * EMACD_SetRxCallback() to register fRxCb() callback and enters suspend state. + * The callback is in charge to resume the task once a new frame has been + * received. The next time EMACD_Poll() is called, it will be successfull. + * + * This function is usually invoked from the RX callback itself with NULL + * callback, to unregister. Once the callback has resumed the application task, + * there is no need to invoke the callback again. + * + * \param pEmacd Pointer to EMAC Driver instance. + * \param fRxCb RX callback. + */ +void EMACD_SetRxCallback(sEmacd * pEmacd, fEmacdTransferCallback fRxCb) +{ + Emac *pHw = pEmacd->pHw; + + if (fRxCb == NULL) + { + EMAC_DisableIt(pHw, EMAC_IDR_RCOMP); + pEmacd->fRxCb = NULL; + } + else + { + pEmacd->fRxCb = fRxCb; + EMAC_EnableIt(pHw, EMAC_IER_RCOMP); + } +} + +/** + * Register/Clear TX wakeup callback. + * + * When EMACD_Send() returns EMACD_TX_BUSY (all TD busy) the application + * task calls EMACD_SetTxWakeupCallback() to register fWakeup() callback and + * enters suspend state. The callback is in charge to resume the task once + * several TD have been released. The next time EMACD_Send() will be called, + * it shall be successfull. + * + * This function is usually invoked with NULL callback from the TX wakeup + * callback itself, to unregister. Once the callback has resumed the + * application task, there is no need to invoke the callback again. + * + * \param pEmacd Pointer to EMAC Driver instance. + * \param fWakeup Wakeup callback. + * \param bThreshould Number of free TD before wakeup callback invoked. + * \return EMACD_OK, EMACD_PARAM on parameter error. + */ +uint8_t EMACD_SetTxWakeupCallback(sEmacd * pEmacd, + fEmacdWakeupCallback fWakeup, + uint8_t bThreshold) +{ + if (fWakeup == NULL) + { + pEmacd->fWakupCb = NULL; + } + else + { + if (bThreshold <= pEmacd->wTxListSize) + { + pEmacd->fWakupCb = fWakeup; + pEmacd->bWakeupThreshold = bThreshold; + } + else + { + return EMACD_PARAM; + } + } + + return EMACD_OK; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacb.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacb.c new file mode 100644 index 000000000..76f517daf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacb.c @@ -0,0 +1,618 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** Default max retry count */ +#define GMACB_RETRY_MAX 300000 + +/** Default max retry count */ +#define GACB_RETRY_MAX 1000000 + +/*--------------------------------------------------------------------------- + * Local functions + *---------------------------------------------------------------------------*/ + + +/** + * Wait PHY operation complete. + * Return 1 if the operation completed successfully. + * May be need to re-implemented to reduce CPU load. + * \param retry: the retry times, 0 to wait forever until complete. + */ +static uint8_t GMACB_WaitPhy( Gmac *pHw, uint32_t retry ) +{ + volatile uint32_t retry_count = 0; + + while (!GMAC_IsIdle(pHw)) + { + if(retry == 0) continue; + retry_count ++; + if (retry_count >= retry) + { + return 0; + } + } + return 1; +} + +/** + * Read PHY register. + * Return 1 if successfully, 0 if timeout. + * \param pHw HW controller address + * \param PhyAddress PHY Address + * \param Address Register Address + * \param pValue Pointer to a 32 bit location to store read data + * \param retry The retry times, 0 to wait forever until complete. + */ +static uint8_t GMACB_ReadPhy(Gmac *pHw, + uint8_t PhyAddress, + uint8_t Address, + uint32_t *pValue, + uint32_t retry) +{ + GMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0); + if ( GMACB_WaitPhy(pHw, retry) == 0 ) + { + TRACE_ERROR("TimeOut GMACB_ReadPhy\n\r"); + return 0; + } + *pValue = GMAC_PHYData(pHw); + return 1; +} + +/** + * Write PHY register + * Return 1 if successfully, 0 if timeout. + * \param pHw HW controller address + * \param PhyAddress PHY Address + * \param Address Register Address + * \param Value Data to write ( Actually 16 bit data ) + * \param retry The retry times, 0 to wait forever until complete. + */ +static uint8_t GMACB_WritePhy(Gmac *pHw, + uint8_t PhyAddress, + uint8_t Address, + uint32_t Value, + uint32_t retry) +{ + GMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value); + if ( GMACB_WaitPhy(pHw, retry) == 0 ) + { + TRACE_ERROR("TimeOut GMACB_WritePhy\n\r"); + return 0; + } + return 1; +} + + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * \brief Find a valid PHY Address ( from 0 to 31 ). + * \param pMacb Pointer to the MACB instance + * \return 0xFF when no valid PHY Address found. + */ +static uint8_t GMACB_FindValidPhy(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + + uint32_t retryMax; + uint32_t value=0; + uint8_t rc; + uint8_t phyAddress; + uint8_t cnt; + + TRACE_DEBUG("GMACB_FindValidPhy\n\r"); + + GMAC_EnableMdio(pHw); + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + /* Check current phyAddress */ + rc = phyAddress; + if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1, &value, retryMax) == 0 ) { + TRACE_ERROR("GMACB PROBLEM\n\r"); + } + TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress); + + /* Find another one */ + if (value != GMII_OUI_MSB) { + + rc = 0xFF; + for(cnt = 0; cnt < 32; cnt ++) { + + phyAddress = (phyAddress + 1) & 0x1F; + if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1, &value, retryMax) == 0 ) { + TRACE_ERROR("MACB PROBLEM\n\r"); + } + TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress); + if (value == GMII_OUI_MSB) { + + rc = phyAddress; + break; + } + } + } + GMAC_DisableMdio(pHw); + if (rc != 0xFF) { + TRACE_INFO("** Valid PHY Found: %d\n\r", rc); + GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax); + TRACE_DEBUG("_BMSR : 0x%X, addr: %d\n\r", value, phyAddress); + GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTSR, &value, retryMax); + TRACE_DEBUG("_1000BTSR : 0x%X, addr: %d\n\r", value, phyAddress); + GMACB_ReadPhy(pHw, phyAddress, GMII_EMSR, &value, retryMax); + TRACE_DEBUG("_EMSR : 0x%X, addr: %d\n\r", value, phyAddress); + } + return rc; +} + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + +/** + * \brief Dump all the useful registers. + * \param pMacb Pointer to the MACB instance + */ +void GMACB_DumpRegisters(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + + uint8_t phyAddress; + uint32_t retryMax; + uint32_t value; + + TRACE_INFO("GMACB_DumpRegisters\n\r"); + + GMAC_EnableMdio(pHw); + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + TRACE_INFO("GMII MACB @%d) Registers:\n\r", phyAddress); + + GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax); + TRACE_INFO(" _BMCR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax); + TRACE_INFO(" _BMSR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &value, retryMax); + TRACE_INFO(" _ANAR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &value, retryMax); + TRACE_INFO(" _ANLPAR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANER, &value, retryMax); + TRACE_INFO(" _ANER : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANNPR, &value, retryMax); + TRACE_INFO(" _ANNPR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPNPAR, &value, retryMax); + TRACE_INFO(" _ANLPNPAR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTCR, &value, retryMax); + TRACE_INFO(" _1000BTCR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTSR, &value, retryMax); + TRACE_INFO(" _1000BTSR : 0x%X\n\r", value); + + GMACB_ReadPhy(pHw, phyAddress, GMII_EMSR, &value, retryMax); + TRACE_INFO(" _EMSR : 0x%X\n\r", value); + TRACE_INFO(" \n\r"); + + GMACB_ReadPhy(pHw, phyAddress, GMII_RLLMR, &value, retryMax); + TRACE_INFO(" _RLLMR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_LMDCDR, &value, retryMax); + TRACE_INFO(" _LMDCDR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_DPPSR, &value, retryMax); + TRACE_INFO(" _DPPSR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_RXERCR, &value, retryMax); + TRACE_INFO(" _RXERCR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ICSR, &value, retryMax); + TRACE_INFO(" _ICSR : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_DDC1R, &value, retryMax); + TRACE_INFO(" _DDC1R : 0x%X\n\r", value); + GMACB_ReadPhy(pHw, phyAddress, GMII_PHYCR, &value, retryMax); + TRACE_INFO(" _PHYCR : 0x%X\n\r", value); + TRACE_INFO(" \n\r"); + + value = GMII_CCR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _CCR : 0x%X\n\r", value); + value = GMII_SSR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _SSR : 0x%X\n\r", value); + value = GMII_OMSOR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _OMSOR : 0x%X\n\r", value); + value = GMII_OMSSR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _OMSSR : 0x%X\n\r", value); + value = GMII_RCCPSR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _RCCPSR : 0x%X\n\r", value); + value = GMII_RRDPSR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _RCCPSR : 0x%X\n\r", value); + value = GMII_ATR; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + GMACB_ReadPhy(pHw, phyAddress, GMII_ERDRR, &value, retryMax); + TRACE_INFO(" _ATR : 0x%X\n\r", value); + + GMAC_DisableMdio(pHw); +} + +/** + * \brief Setup the maximum timeout count of the driver. + * \param pMacb Pointer to the MACB instance + * \param toMax Timeout maxmum count. + */ +void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax) +{ + pMacb->retryMax = toMax; +} + +/** + * \brief Initialize the MACB instance. + * \param pMacb Pointer to the MACB instance + * \param phyAddress The PHY address used to access the PHY + */ +void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress) +{ + pMacb->pGmacd = pGmacd; + pMacb->phyAddress = phyAddress; + /* Initialize timeout by default */ + pMacb->retryMax = GMACB_RETRY_MAX; +} + + +/** + * \brief Issue a SW reset to reset all registers of the PHY. + * \param pMacb Pointer to the MACB instance + * \return 1 if successfully, 0 if timeout. + */ +uint8_t GMACB_ResetPhy(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + uint32_t retryMax; + uint32_t bmcr = GMII_RESET; + uint8_t phyAddress; + uint32_t timeout = 10; + uint8_t ret = 1; + + TRACE_INFO(" GMACB_ResetPhy\n\r"); + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + GMAC_EnableMdio(pHw); + bmcr = GMII_RESET; + GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, bmcr, retryMax); + + do { + GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &bmcr, retryMax); + timeout--; + } while ((bmcr & GMII_RESET) && timeout); + + GMAC_DisableMdio(pHw); + + if (!timeout) { + ret = 0; + } + + return( ret ); +} + +/** + * \brief Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII) + * The RXDV pin is used to select test mode on reset (pulled up for test mode) + * The above pins should be predefined for corresponding settings in resetPins + * The GMAC peripheral pins are configured after the reset done. + * \param pMacb Pointer to the MACB instance + * \param mck Main clock setting to initialize clock + * \param resetPins Pointer to list of PIOs to configure before HW RESET + * (for PHY power on reset configuration latch) + * \param nbResetPins Number of PIO items that should be configured + * \param emacPins Pointer to list of PIOs for the EMAC interface + * \param nbEmacPins Number of PIO items that should be configured + * \return 1 if RESET OK, 0 if timeout. + */ +uint8_t GMACB_InitPhy(GMacb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pEmacPins, + uint32_t nbEmacPins) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + uint8_t rc = 1; + uint8_t phy; + + /* Perform RESET */ + TRACE_DEBUG("RESET PHY\n\r"); + + if (pResetPins) { + /* Configure PINS */ + PIO_Configure(pResetPins, nbResetPins); + } + /* Configure EMAC runtime pins */ + if (rc) { + + PIO_Configure(pEmacPins, nbEmacPins); + rc = GMAC_SetMdcClock(pHw, mck ); + if (!rc) { + TRACE_ERROR("No Valid MDC clock\n\r"); + return 0; + } + + /* Check PHY Address */ + phy = GMACB_FindValidPhy(pMacb); + if (phy == 0xFF) { + TRACE_ERROR("PHY Access fail\n\r"); + return 0; + } + if(phy != pMacb->phyAddress) { + pMacb->phyAddress = phy; + GMACB_ResetPhy(pMacb); + } + } + else { + TRACE_ERROR("PHY Reset Timeout\n\r"); + } + return rc; +} + +/** + * \brief Issue a Auto Negotiation of the PHY + * \param pMacb Pointer to the MACB instance + * \return 1 if successfully, 0 if timeout. + */ +uint8_t GMACB_AutoNegotiate(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + uint32_t retryMax; + uint32_t value; + uint32_t phyAnar; + uint32_t phyAnalpar; + uint32_t gbaseTC; + uint32_t gbaseTS; + uint32_t retryCount= 0; + uint8_t phyAddress; + uint8_t rc = 1; + uint32_t duplex, speed; + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + GMAC_EnableMdio(pHw); + + if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID1, &value, retryMax)) + { + TRACE_ERROR("Pb GEMAC_ReadPhy Id1\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress); + if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID2, &phyAnar, retryMax)) + { + TRACE_ERROR("Pb GMACB_ReadPhy Id2\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar); + + if( ( value == GMII_OUI_MSB ) + && ( ((phyAnar>>10)&GMII_LSB_MASK) == GMII_OUI_LSB ) ) + { + TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F)); + TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0x7)); + } + else + { + TRACE_ERROR("Problem OUI value\n\r"); + } + + value = GMII_RCCPSR | 0x8000; + GMACB_WritePhy(pHw,phyAddress, GMII_ERCR, value, retryMax); + //value = 0xF0F4; + value = 0xF2F4; + GMACB_WritePhy(pHw,phyAddress, GMII_ERDWR, value, retryMax); + value = GMII_RRDPSR | 0x8000; + GMACB_WritePhy(pHw, phyAddress, GMII_ERCR, value, retryMax); + //value = 0x3028; + value = 0x2222; + GMACB_WritePhy(pHw,phyAddress, GMII_ERDWR, value, retryMax); + + value = 0xFF00; + rc = GMACB_WritePhy(pHw,phyAddress, GMII_ICSR, value, retryMax); + + /* Set the Auto_negotiation Advertisement Register, MII advertising for Next page + 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &phyAnar, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + phyAnar = GMII_TX_FDX | GMII_TX_HDX | + GMII_10_FDX | GMII_10_HDX | GMII_AN_IEEE_802_3; + rc = GMACB_WritePhy(pHw,phyAddress, GMII_ANAR, phyAnar, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Read & modify 1000Base-T control register */ + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTCR, &gbaseTC, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + gbaseTC |= GMII_1000BaseT_HALF_DUPLEX |GMII_1000BaseT_FULL_DUPLEX; + rc = GMACB_WritePhy(pHw, phyAddress, GMII_1000BTCR, gbaseTC, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Read & modify control register */ + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Restart Auto_negotiation */ + value |= GMII_RESTART_AUTONEG; + rc = GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + TRACE_DEBUG(" _BMCR: 0x%X\n\r", value); + + /* Check AutoNegotiate complete */ + while (1) + { + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax); + if (rc == 0) + { + TRACE_ERROR("rc==0\n\r"); + goto AutoNegotiateExit; + } + /* Done successfully */ + if (value & GMII_AUTONEG_COMP) + { + printf("AutoNegotiate complete\n\r"); + break; + } + /* Timeout check */ + if (retryMax) + { + if (++ retryCount >= retryMax) + { + GMACB_DumpRegisters(pMacb); + TRACE_ERROR("TimeOut\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + } + } + + /*Set local link mode */ + while(1) + { + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_1000BTSR, &gbaseTS, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + /* Setup the EMAC link speed */ + if ((gbaseTS & GMII_LINKP_1000BaseT_FULL_DUPLEX) && + (gbaseTC & GMII_1000BaseT_FULL_DUPLEX)) + { + /* set RGMII for 1000BaseTX and Full Duplex */ + duplex = GMAC_DUPLEX_FULL; + speed = GMAC_SPEED_1000M; + break; + } + else if ((gbaseTS & GMII_LINKP_1000BaseT_HALF_DUPLEX) && + (gbaseTC & GMII_1000BaseT_HALF_DUPLEX)) + { + /* set RGMII for 1000BaseT and Half Duplex*/ + duplex = GMAC_DUPLEX_HALF; + speed = GMAC_SPEED_1000M; + break; + } + + /* Get the AutoNeg Link partner base page */ + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &phyAnalpar, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Setup the EMAC link speed */ + if ((phyAnar & phyAnalpar) & GMII_TX_FDX) + { + /* set RGMII for 100BaseTX and Full Duplex */ + duplex = GMAC_DUPLEX_FULL; + speed = GMAC_SPEED_100M; + break; + } + else if ((phyAnar & phyAnalpar) & GMII_10_FDX) + { + /* set RGMII for 10BaseT and Full Duplex */ + duplex = GMAC_DUPLEX_FULL; + speed = GMAC_SPEED_10M; + break; + } + else if ((phyAnar & phyAnalpar) & GMII_TX_HDX) + { + /* set RGMII for 100BaseTX and half Duplex */ + duplex = GMAC_DUPLEX_HALF; + speed = GMAC_SPEED_100M; + break; + } + else if ((phyAnar & phyAnalpar) & GMII_10_HDX) + { + /* set RGMII for 10BaseT and half Duplex */ + duplex = GMAC_DUPLEX_HALF; + speed = GMAC_SPEED_10M; + break; + } + } + + /* Setup GMAC mode */ + GMAC_EnableRGMII(pHw, duplex, speed); + +AutoNegotiateExit: + GMAC_DisableMdio(pHw); + return rc; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacd.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacd.c new file mode 100644 index 000000000..062ef0f71 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/gmacd.c @@ -0,0 +1,715 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + /** \file */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include +#include + +/** \addtogroup gmacd_defines + @{*/ + + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +/** Return count in buffer */ +#define GCIRC_CNT(head,tail,size) (((head) - (tail)) % (size)) + +/** Return space available, 0..size-1. always leave one free char as a completely full buffer + has head == tail, which is the same as empty */ +#define GCIRC_SPACE(head,tail,size) GCIRC_CNT((tail),((head)+1),(size)) + +/** Return count up to the end of the buffer. Carefully avoid accessing head and tail more than once, + so they can change underneath us without returning inconsistent results */ +#define GCIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = ((head) + end) % (size); \ + n < end ? n : end;}) + +/** Return space available up to the end of the buffer */ +#define GCIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) % (size); \ + n <= end ? n : end+1;}) + +/** Increment head or tail */ +#define GCIRC_INC(headortail,size) \ + headortail++; \ + if(headortail >= size) { \ + headortail = 0; \ + } + +/** Circular buffer is empty ? */ +#define GCIRC_EMPTY(head, tail) (head == tail) + +/** Clear circular buffer */ +#define GCIRC_CLEAR(head, tail) (head = tail = 0) + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +/// The buffer addresses written into the descriptors must be aligned so the +/// last few bits are zero. These bits have special meaning for the GMAC +/// peripheral and cannot be used as part of the address. +#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC) +#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask + +// receive buffer descriptor bits +#define GMAC_RX_OWNERSHIP_BIT (1 << 0) +#define GMAC_RX_WRAP_BIT (1 << 1) +#define GMAC_RX_SOF_BIT (1 << 14) +#define GMAC_RX_EOF_BIT (1 << 15) + +// Transmit buffer descriptor bits +#define GMAC_TX_LAST_BUFFER_BIT (1 << 15) +#define GMAC_TX_WRAP_BIT (1 << 30) +#define GMAC_TX_USED_BIT (1 << 31) +#define GMAC_TX_RLE_BIT (1 << 29) /// Retry Limit Exceeded +#define GMAC_TX_UND_BIT (1 << 28) /// Tx Buffer Underrun +#define GMAC_TX_ERR_BIT (1 << 27) /// Exhausted in mid-frame +#define GMAC_TX_ERR_BITS \ + (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT) + +/*--------------------------------------------------------------------------- + * Local functions + *---------------------------------------------------------------------------*/ + +/** + * \brief Disable TX & reset registers and descriptor list + * \param pDrv Pointer to GMAC Driver instance. + */ +static void GMACD_ResetTx(sGmacd *pDrv ) +{ + Gmac *pHw = pDrv->pHw; + uint8_t *pTxBuffer = pDrv->pTxBuffer; + sGmacTxDescriptor *pTd = pDrv->pTxD; + uint32_t Index; + uint32_t Address; + + /* Disable TX */ + GMAC_TransmitEnable(pHw, 0); + /* Setup the TX descriptors. */ + GCIRC_CLEAR(pDrv->wTxHead, pDrv->wTxTail); + for(Index = 0; Index < pDrv->wTxListSize; Index++) { + Address = (uint32_t)(&(pTxBuffer[Index * GMAC_TX_UNITSIZE])); + pTd[Index].addr = Address; + pTd[Index].status.val = (uint32_t)GMAC_TX_USED_BIT; + } + pTd[pDrv->wTxListSize - 1].status.val = GMAC_TX_USED_BIT | GMAC_TX_WRAP_BIT; + /* Transmit Buffer Queue Pointer Register */ + GMAC_SetTxQueue(pHw, (uint32_t)pTd); +} + +/** + * \brief Disable RX & reset registers and descriptor list + * \param pDrv Pointer to GMAC Driver instance. + */ +static void GMACD_ResetRx(sGmacd *pDrv ) +{ + Gmac *pHw = pDrv->pHw; + uint8_t *pRxBuffer = pDrv->pRxBuffer; + sGmacRxDescriptor *pRd = pDrv->pRxD; + + uint32_t Index; + uint32_t Address; + + /* Disable RX */ + GMAC_ReceiveEnable(pHw, 0); + + /* Setup the RX descriptors. */ + pDrv->wRxI = 0; + for(Index = 0; Index < pDrv->wRxListSize; Index++) + { + Address = (uint32_t)(&(pRxBuffer[Index * GMAC_RX_UNITSIZE])); + /* Remove GMAC_RXD_bmOWNERSHIP and GMAC_RXD_bmWRAP */ + pRd[Index].addr.val = Address & GMAC_ADDRESS_MASK; + pRd[Index].status.val = 0; + } + pRd[pDrv->wRxListSize - 1].addr.val |= GMAC_RX_WRAP_BIT; + + /* Receive Buffer Queue Pointer Register */ + GMAC_SetRxQueue(pHw, (uint32_t) pRd); +} + + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + + +/** + * \brief GMAC Interrupt handler + * \param pGmacd Pointer to GMAC Driver instance. + */ +void GMACD_Handler(sGmacd *pGmacd ) +{ + Gmac *pHw = pGmacd->pHw; + sGmacTxDescriptor *pTxTd; + fGmacdTransferCallback *pTxCb = NULL; + uint32_t isr; + uint32_t rsr; + uint32_t tsr; + + uint32_t rxStatusFlag; + uint32_t txStatusFlag; + isr = GMAC_GetItStatus(pHw); + rsr = GMAC_GetRxStatus(pHw); + tsr = GMAC_GetTxStatus(pHw); + + isr &= ~(GMAC_GetItMask(pHw)| 0xF8030300); + + /* RX packet */ + if ((isr & GMAC_ISR_RCOMP) || (rsr & GMAC_RSR_REC)) { + asm("nop"); + rxStatusFlag = GMAC_RSR_REC; + /* Frame received */ + /* Check OVR */ + if (rsr & GMAC_RSR_RXOVR) { + rxStatusFlag |= GMAC_RSR_RXOVR; + } + /* Check BNA */ + if (rsr & GMAC_RSR_BNA) { + rxStatusFlag |= GMAC_RSR_BNA; + } + /* Check HNO */ + if (rsr & GMAC_RSR_HNO) { + rxStatusFlag |= GMAC_RSR_HNO; + } + /* Clear status */ + GMAC_ClearRxStatus(pHw, rxStatusFlag); + + /* Invoke callbacks */ + if (pGmacd->fRxCb) + { + pGmacd->fRxCb(rxStatusFlag); + } + } + + /* TX packet */ + if ((isr & GMAC_ISR_TCOMP) || (tsr & GMAC_TSR_TXCOMP)) { + asm("nop"); + txStatusFlag = GMAC_TSR_TXCOMP; + + /* A frame transmitted Check RLE */ + if (tsr & GMAC_TSR_RLE) { + /* Status RLE & Number of discarded buffers */ + txStatusFlag = GMAC_TSR_RLE + | GCIRC_CNT(pGmacd->wTxHead, + pGmacd->wTxTail, + pGmacd->wTxListSize); + pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail]; + GMACD_ResetTx(pGmacd); + TRACE_INFO("Tx RLE!!\n\r"); + GMAC_TransmitEnable(pHw, 1); + } + /* Check COL */ + if (tsr & GMAC_TSR_COL) { + txStatusFlag |= GMAC_TSR_COL; + } + /* Check TFC */ + if (tsr & GMAC_TSR_TFC) { + txStatusFlag |= GMAC_TSR_TFC; + } + /* Check UND */ + if (tsr & GMAC_TSR_UND) { + txStatusFlag |= GMAC_TSR_UND; + } + /* Check HRESP */ + if (tsr & GMAC_TSR_HRESP) { + txStatusFlag |= GMAC_TSR_HRESP; + } + /* Check LCO */ + if (tsr & GMAC_TSR_LCO) { + txStatusFlag |= GMAC_TSR_LCO; + } + /* Clear status */ + GMAC_ClearTxStatus(pHw, txStatusFlag); + + if (!GCIRC_EMPTY(pGmacd->wTxHead, pGmacd->wTxTail)) + { + /* Check the buffers */ + do { + pTxTd = &pGmacd->pTxD[pGmacd->wTxTail]; + pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail]; + /* Exit if buffer has not been sent yet */ + + if ((pTxTd->status.val & (uint32_t)GMAC_TX_USED_BIT) == 0) { + break; + } + /* Notify upper layer that a packet has been sent */ + if (*pTxCb) { + (*pTxCb)(txStatusFlag); + } + GCIRC_INC( pGmacd->wTxTail, pGmacd->wTxListSize ); + } while (GCIRC_CNT(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize)); + } + + if (tsr & GMAC_TSR_RLE) { + /* Notify upper layer RLE */ + if (*pTxCb) { + (*pTxCb)(txStatusFlag); + } + } + + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, send will be successfull. */ + if((GCIRC_SPACE(pGmacd->wTxHead, + pGmacd->wTxTail, + pGmacd->wTxListSize) >= pGmacd->bWakeupThreshold) && pGmacd->fWakupCb) + { + pGmacd->fWakupCb(); + } + } + + /* PAUSE Frame */ + if (isr & GMAC_ISR_PFNZ) TRACE_INFO("Pause!\n\r"); + if (isr & GMAC_ISR_PTZ) TRACE_INFO("Pause TO!\n\r"); +} + + +/** + * \brief Initialize the GMAC with the Gmac controller address + * \param pGmacd Pointer to GMAC Driver instance. + * \param pHw Pointer to HW address for registers. + * \param bID HW ID for power management + * \param enableCAF Enable/Disable CopyAllFrame. + * \param enableNBC Enable/Disable NoBroadCast. + */ + void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC ) +{ + uint32_t dwNcfgr; + + /* Check parameters */ + assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX); + + TRACE_DEBUG("GMAC_Init\n\r"); + + /* Initialize struct */ + pGmacd->pHw = pHw; + pGmacd->bId = bID; + + /* Power ON */ + PMC_EnablePeripheral(bID); + + /* Disable TX & RX and more */ + GMAC_NetworkControl(pHw, 0); + GMAC_DisableIt(pHw, ~0u); + + GMAC_ClearStatistics(pHw); + /* Clear all status bits in the receive status register. */ + GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO); + + /* Clear all status bits in the transmit status register */ + GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE + | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP + | GMAC_TSR_UND | GMAC_TSR_HRESP | GMAC_TSR_LCO); + + /* Clear interrupts */ + GMAC_GetItStatus(pHw); + + /* Enable the copy of data into the buffers + ignore broadcasts, and don't copy FCS. */ + dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_GBE | GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_64; + if( enableCAF ) { + dwNcfgr |= GMAC_NCFGR_CAF; + } + if( enableNBC ) { + dwNcfgr |= GMAC_NCFGR_NBC; + } + + GMAC_Configure(pHw, dwNcfgr); +} + + +/** + * Initialize necessary allocated buffer lists for GMAC Driver to transfer data. + * Must be invoked after GMACD_Init() but before RX/TX start. + * \param pGmacd Pointer to GMAC Driver instance. + * \param pRxBuffer Pointer to allocated buffer for RX. The address should + * be 8-byte aligned and the size should be + * GMAC_RX_UNITSIZE * wRxSize. + * \param pRxD Pointer to allocated RX descriptor list. + * \param wRxSize RX size, in number of registered units (RX descriptors). + * \param pTxBuffer Pointer to allocated buffer for TX. The address should + * be 8-byte aligned and the size should be + * GMAC_TX_UNITSIZE * wTxSize. + * \param pTxD Pointer to allocated TX descriptor list. + * \param pTxCb Pointer to allocated TX callback list. + * \param wTxSize TX size, in number of registered units (TX descriptors). + * \return GMACD_OK or GMACD_PARAM. + * \note If input address is not 8-byte aligned the address is automatically + * adjusted and the list size is reduced by one. + */ +uint8_t GMACD_InitTransfer( sGmacd *pGmacd, + uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD, + uint16_t wRxSize, + uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb, + uint16_t wTxSize) +{ + Gmac *pHw = pGmacd->pHw; + + if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM; + + /* Assign RX buffers */ + if ( ((uint32_t)pRxBuffer & 0x7) + || ((uint32_t)pRxD & 0x7) ) + { + wRxSize --; + TRACE_DEBUG("RX list address adjusted\n\r"); + } + pGmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8); + pGmacd->pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8); + pGmacd->wRxListSize = wRxSize; + + /* Assign TX buffers */ + if ( ((uint32_t)pTxBuffer & 0x7) + || ((uint32_t)pTxD & 0x7) ) + { + wTxSize --; + TRACE_DEBUG("TX list address adjusted\n\r"); + } + pGmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8); + pGmacd->pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8); + pGmacd->wTxListSize = wTxSize; + pGmacd->fTxCbList = pTxCb; + + /* Reset TX & RX */ + GMACD_ResetRx(pGmacd); + GMACD_ResetTx(pGmacd); + + /* Enable Rx and Tx, plus the stats register. */ + GMAC_TransmitEnable(pHw, 1); + GMAC_ReceiveEnable(pHw, 1); + GMAC_StatisticsWriteEnable(pHw, 1); + + /* Setup the interrupts for TX (and errors) */ + GMAC_EnableIt(pHw, GMAC_IER_MFS + |GMAC_IER_RCOMP + |GMAC_IER_RXUBR + |GMAC_IER_TXUBR + |GMAC_IER_TUR + |GMAC_IER_RLEX + |GMAC_IER_TFC + |GMAC_IER_TCOMP + |GMAC_IER_ROVR + |GMAC_IER_HRESP + |GMAC_IER_PFNZ + |GMAC_IER_PTZ + |GMAC_IER_PFTR + |GMAC_IER_EXINT + |GMAC_IER_DRQFR + |GMAC_IER_SFR + |GMAC_IER_DRQFT + |GMAC_IER_SFT + |GMAC_IER_PDRQFR + |GMAC_IER_PDRSFR + |GMAC_IER_PDRQFT + |GMAC_IER_PDRSFT); + //0x03FCFCFF + return GMACD_OK; +} + + +/** + * Reset TX & RX queue & statistics + * \param pGmacd Pointer to GMAC Driver instance. + */ +void GMACD_Reset(sGmacd *pGmacd) +{ + Gmac *pHw = pGmacd->pHw; + + GMACD_ResetRx(pGmacd); + GMACD_ResetTx(pGmacd); + //memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats)); + GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN + | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT); +} + +/** + * \brief Send a packet with GMAC. If the packet size is larger than transfer buffer size + * error returned. If packet transfer status is monitored, specify callback for each packet. + * \param pGmacd Pointer to GMAC Driver instance. + * \param buffer The buffer to be send + * \param size The size of buffer to be send + * \param fGMAC_TxCallback Threshold Wakeup callback + * \param fWakeUpCb TX Wakeup + * \return OK, Busy or invalid packet + */ +uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb ) +{ + Gmac *pHw = pGmacd->pHw; + sGmacTxDescriptor *pTxTd; + volatile fGmacdTransferCallback *pfTxCb; + + TRACE_DEBUG("GMAC_Send\n\r"); + /* Check parameter */ + if (size > GMAC_TX_UNITSIZE) { + + TRACE_ERROR("GMAC driver does not split send packets."); + return GMACD_PARAM; + } + + /* Pointers to the current TxTd */ + pTxTd = &pGmacd->pTxD[pGmacd->wTxHead]; + /* If no free TxTd, buffer can't be sent */ + if( GCIRC_SPACE(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize) == 0) + return GMACD_TX_BUSY; + /* Pointers to the current Tx Callback */ + pfTxCb = &pGmacd->fTxCbList[pGmacd->wTxHead]; + /* Sanity check */ + + /* Setup/Copy data to transmition buffer */ + if (pBuffer && size) { + // Driver manage the ring buffer + memcpy((void *)pTxTd->addr, pBuffer, size); + } + /* Tx Callback */ + *pfTxCb = fTxCb; + + /* Update TD status. The buffer size defined is length of ethernet frame + so it's always the last buffer of the frame. */ + if (pGmacd->wTxHead == pGmacd->wTxListSize-1) { + pTxTd->status.val = + (size & GMAC_LENGTH_FRAME) | GMAC_TX_LAST_BUFFER_BIT | GMAC_TX_WRAP_BIT; + } + else { + pTxTd->status.val = (size & GMAC_LENGTH_FRAME) | GMAC_TX_LAST_BUFFER_BIT; + } + + GCIRC_INC(pGmacd->wTxHead, pGmacd->wTxListSize); + + //CP15_flush_dcache_for_dma ((uint32_t)(pTxTd), ((uint32_t)(pTxTd) + sizeof(pTxTd))); + /* Tx packets count */ + + /* Now start to transmit if it is not already done */ + GMAC_TransmissionStart(pHw); + + return GMACD_OK; +} + + +/** + * Return current load of TX. + * \param pGmacd Pointer to GMAC Driver instance. + */ +uint32_t GMACD_TxLoad(sGmacd *pGmacd) +{ + uint16_t head = pGmacd->wTxHead; + uint16_t tail = pGmacd->wTxTail; + return GCIRC_CNT(head, tail, pGmacd->wTxListSize); +} + +/** + * \brief Receive a packet with GMAC. + * If not enough buffer for the packet, the remaining data is lost but right + * frame length is returned. + * \param pGmacd Pointer to GMAC Driver instance. + * \param pFrame Buffer to store the frame + * \param frameSize Size of the frame + * \param pRcvSize Received size + * \return OK, no data, or frame too small + */ +uint8_t GMACD_Poll(sGmacd * pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize) +{ + + uint16_t bufferLength; + uint32_t tmpFrameSize = 0; + uint8_t *pTmpFrame = 0; + uint32_t tmpIdx = pGmacd->wRxI; + volatile sGmacRxDescriptor *pRxTd = &pGmacd->pRxD[pGmacd->wRxI]; + uint8_t isFrame = 0; + + if (pFrame == NULL) return GMACD_PARAM; + + /* Set the default return value */ + *pRcvSize = 0; + + /* Process received RxTd */ + while ((pRxTd->addr.val & GMAC_RX_OWNERSHIP_BIT) == GMAC_RX_OWNERSHIP_BIT) + { + /* A start of frame has been received, discard previous fragments */ + if ((pRxTd->status.val & GMAC_RX_SOF_BIT) == GMAC_RX_SOF_BIT) + { + /* Skip previous fragment */ + while (tmpIdx != pGmacd->wRxI) + { + pRxTd = &pGmacd->pRxD[pGmacd->wRxI]; + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize); + } + pTmpFrame = pFrame; + tmpFrameSize = 0; + /* Start to gather buffers in a frame */ + isFrame = 1; + } + /* Increment the pointer */ + GCIRC_INC(tmpIdx, pGmacd->wRxListSize); + asm("nop"); + /* Copy data in the frame buffer */ + if (isFrame) { + if (tmpIdx == pGmacd->wRxI) + { + TRACE_INFO("no EOF (Invalid of buffers too small)\n\r"); + + do { + pRxTd = &pGmacd->pRxD[pGmacd->wRxI]; + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize); + } while(tmpIdx != pGmacd->wRxI); + return GMACD_RX_NULL; + } + + /* Copy the buffer into the application frame */ + bufferLength = GMAC_RX_UNITSIZE; + if ((tmpFrameSize + bufferLength) > frameSize) + { + bufferLength = frameSize - tmpFrameSize; + } + + memcpy(pTmpFrame, (void*)(pRxTd->addr.val & GMAC_ADDRESS_MASK), bufferLength); + pTmpFrame += bufferLength; + tmpFrameSize += bufferLength; + + /* An end of frame has been received, return the data */ + if ((pRxTd->status.val & GMAC_RX_EOF_BIT) == GMAC_RX_EOF_BIT) + { + /* Frame size from the GMAC */ + *pRcvSize = (pRxTd->status.val & GMAC_LENGTH_FRAME); + + /* Application frame buffer is too small all data have not been copied */ + if (tmpFrameSize < *pRcvSize) { + return GMACD_SIZE_TOO_SMALL; + } + TRACE_DEBUG("packet %d-%d (%d)\n\r", pGmacd->wRxI, tmpIdx, *pRcvSize); + /* All data have been copied in the application frame buffer => release TD */ + while (pGmacd->wRxI != tmpIdx) + { + pRxTd = &pGmacd->pRxD[pGmacd->wRxI]; + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + GCIRC_INC(pGmacd->wRxI, pGmacd->wRxListSize); + } + return GMACD_OK; + } + } + + /* SOF has not been detected, skip the fragment */ + else { + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + pGmacd->wRxI = tmpIdx; + } + + /* Process the next buffer */ + pRxTd = &pGmacd->pRxD[tmpIdx]; + } + return GMACD_RX_NULL; +} + +/** + * \brief Registers pRxCb callback. Callback will be invoked after the next received + * frame. When GMAC_Poll() returns GMAC_RX_NO_DATA the application task call GMAC_Set_RxCb() + * to register pRxCb() callback and enters suspend state. The callback is in charge + * to resume the task once a new frame has been received. The next time GMAC_Poll() + * is called, it will be successfull. + * \param pGmacd Pointer to GMAC Driver instance. + * \param pRxCb Pointer to callback function + * \return OK, no data, or frame too small + */ + +void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb) +{ + Gmac *pHw = pGmacd->pHw; + + if (fRxCb == NULL) + { + GMAC_DisableIt(pHw, GMAC_IDR_RCOMP); + pGmacd->fRxCb = NULL; + } + else + { + pGmacd->fRxCb = fRxCb; + GMAC_EnableIt(pHw, GMAC_IER_RCOMP); + } +} + + +/** + * Register/Clear TX wakeup callback. + * + * When GMACD_Send() returns GMACD_TX_BUSY (all TD busy) the application + * task calls GMACD_SetTxWakeupCallback() to register fWakeup() callback and + * enters suspend state. The callback is in charge to resume the task once + * several TD have been released. The next time GMACD_Send() will be called, + * it shall be successfull. + * + * This function is usually invoked with NULL callback from the TX wakeup + * callback itself, to unregister. Once the callback has resumed the + * application task, there is no need to invoke the callback again. + * + * \param pGmacd Pointer to GMAC Driver instance. + * \param fWakeup Wakeup callback. + * \param bThreshould Number of free TD before wakeup callback invoked. + * \return GMACD_OK, GMACD_PARAM on parameter error. + */ +uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold) +{ + if (fWakeup == NULL) + { + pGmacd->fWakupCb = NULL; + } + else + { + if (bThreshold <= pGmacd->wTxListSize) + { + pGmacd->fWakupCb = fWakeup; + pGmacd->bWakeupThreshold = bThreshold; + } + else + { + return GMACD_PARAM; + } + } + + return GMACD_OK; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/hamming.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/hamming.c new file mode 100644 index 000000000..0461de1d7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/hamming.c @@ -0,0 +1,338 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Internal function + *----------------------------------------------------------------------------*/ + +/** + * Counts and return the number of bits set to '1' in the given byte. + * \param byte Byte to count. + */ +static uint8_t CountBitsInByte(uint8_t byte) +{ + uint8_t count = 0; + + while (byte > 0) + { + if (byte & 1) + { + count++; + } + byte >>= 1; + } + + return count; +} + +/** + * Counts and return the number of bits set to '1' in the given hamming code. + * \param code Hamming code. + */ +static uint8_t CountBitsInCode256(uint8_t *code) +{ + return CountBitsInByte(code[0]) + CountBitsInByte(code[1]) + CountBitsInByte(code[2]); +} + +/** + * Calculates the 22-bit hamming code for a 256-bytes block of data. + * \param data Data buffer to calculate code for. + * \param code Pointer to a buffer where the code should be stored. + */ +static void Compute256(const uint8_t *data, uint8_t *code) +{ + uint32_t i; + uint8_t columnSum = 0; + uint8_t evenLineCode = 0; + uint8_t oddLineCode = 0; + uint8_t evenColumnCode = 0; + uint8_t oddColumnCode = 0; + + // Xor all bytes together to get the column sum; + // At the same time, calculate the even and odd line codes + for (i=0; i < 256; i++) + { + columnSum ^= data[i]; + + // If the xor sum of the byte is 0, then this byte has no incidence on + // the computed code; so check if the sum is 1. + if ((CountBitsInByte(data[i]) & 1) == 1) + { + // Parity groups are formed by forcing a particular index bit to 0 + // (even) or 1 (odd). + // Example on one byte: + // + // bits (dec) 7 6 5 4 3 2 1 0 + // (bin) 111 110 101 100 011 010 001 000 + // '---'---'---'----------. + // | + // groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 | + // P2' ooooooo eeeeeee ooooooo eeeeeee P2 | + // P1' ooo eee ooo eee ooo eee ooo eee P1 | + // | + // We can see that: | + // - P4 -> bit 2 of index is 0 --------------------' + // - P4' -> bit 2 of index is 1. + // - P2 -> bit 1 of index if 0. + // - etc... + // We deduce that a bit position has an impact on all even Px if + // the log2(x)nth bit of its index is 0 + // ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3) + // and on all odd Px' if the log2(x)nth bit of its index is 1 + // ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5) + // + // As such, we calculate all the possible Px and Px' values at the + // same time in two variables, evenLineCode and oddLineCode, such as + // evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1 + // oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1' + // + evenLineCode ^= (255 - i); + oddLineCode ^= i; + } + } + + // At this point, we have the line parities, and the column sum. First, We + // must caculate the parity group values on the column sum. + for (i=0; i < 8; i++) + { + if (columnSum & 1) + { + evenColumnCode ^= (7 - i); + oddColumnCode ^= i; + } + columnSum >>= 1; + } + + // Now, we must interleave the parity values, to obtain the following layout: + // Code[0] = Line1 + // Code[1] = Line2 + // Code[2] = Column + // Line = Px' Px P(x-1)- P(x-1) ... + // Column = P4' P4 P2' P2 P1' P1 PadBit PadBit + code[0] = 0; + code[1] = 0; + code[2] = 0; + + for (i=0; i < 4; i++) + { + code[0] <<= 2; + code[1] <<= 2; + code[2] <<= 2; + + // Line 1 + if ((oddLineCode & 0x80) != 0) + { + code[0] |= 2; + } + + if ((evenLineCode & 0x80) != 0) + { + code[0] |= 1; + } + + // Line 2 + if ((oddLineCode & 0x08) != 0) + { + code[1] |= 2; + } + + if ((evenLineCode & 0x08) != 0) + { + code[1] |= 1; + } + + // Column + if ((oddColumnCode & 0x04) != 0) + { + code[2] |= 2; + } + + if ((evenColumnCode & 0x04) != 0) + { + code[2] |= 1; + } + + oddLineCode <<= 1; + evenLineCode <<= 1; + oddColumnCode <<= 1; + evenColumnCode <<= 1; + } + + // Invert codes (linux compatibility) + code[0] = (~(uint32_t)code[0]); + code[1] = (~(uint32_t)code[1]); + code[2] = (~(uint32_t)code[2]); + + TRACE_DEBUG("Computed code = %02X %02X %02X\n\r", + code[0], code[1], code[2]); +} + +/** + * Verifies and corrects a 256-bytes block of data using the given 22-bits + * hamming code. + * + * \param data Data buffer to check. + * \param originalCode Hamming code to use for verifying the data. + * + * \return 0 if there is no error, otherwise returns a HAMMING_ERROR code. + */ +static uint8_t Verify256( uint8_t* pucData, const uint8_t* pucOriginalCode ) +{ + /* Calculate new code */ + uint8_t computedCode[3] ; + uint8_t correctionCode[3] ; + + Compute256( pucData, computedCode ) ; + + /* Xor both codes together */ + correctionCode[0] = computedCode[0] ^ pucOriginalCode[0] ; + correctionCode[1] = computedCode[1] ^ pucOriginalCode[1] ; + correctionCode[2] = computedCode[2] ^ pucOriginalCode[2] ; + + TRACE_DEBUG( "Correction code = %02X %02X %02X\n\r", correctionCode[0], correctionCode[1], correctionCode[2] ) ; + + // If all bytes are 0, there is no error + if ( (correctionCode[0] == 0) && (correctionCode[1] == 0) && (correctionCode[2] == 0) ) + { + return 0 ; + } + + /* If there is a single bit error, there are 11 bits set to 1 */ + if ( CountBitsInCode256( correctionCode ) == 11 ) + { + // Get byte and bit indexes + uint8_t byte = correctionCode[0] & 0x80; + byte |= (correctionCode[0] << 1) & 0x40; + byte |= (correctionCode[0] << 2) & 0x20; + byte |= (correctionCode[0] << 3) & 0x10; + + byte |= (correctionCode[1] >> 4) & 0x08; + byte |= (correctionCode[1] >> 3) & 0x04; + byte |= (correctionCode[1] >> 2) & 0x02; + byte |= (correctionCode[1] >> 1) & 0x01; + + uint8_t bit = (correctionCode[2] >> 5) & 0x04; + bit |= (correctionCode[2] >> 4) & 0x02; + bit |= (correctionCode[2] >> 3) & 0x01; + + /* Correct bit */ + printf("Correcting byte #%d at bit %d\n\r", byte, bit ) ; + pucData[byte] ^= (1 << bit) ; + + return Hamming_ERROR_SINGLEBIT ; + } + + /* Check if ECC has been corrupted */ + if ( CountBitsInCode256( correctionCode ) == 1 ) + { + return Hamming_ERROR_ECC ; + } + /* Otherwise, this is a multi-bit error */ + else + { + return Hamming_ERROR_MULTIPLEBITS ; + } +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Computes 3-bytes hamming codes for a data block whose size is multiple of + * 256 bytes. Each 256 bytes block gets its own code. + * \param data Data to compute code for. + * \param size Data size in bytes. + * \param code Codes buffer. + */ +void Hamming_Compute256x( const uint8_t *pucData, uint32_t dwSize, uint8_t* puCode ) +{ + TRACE_DEBUG("Hamming_Compute256x()\n\r"); + + while ( dwSize > 0 ) + { + Compute256( pucData, puCode ) ; + + pucData += 256; + puCode += 3; + dwSize -= 256; + } +} + +/** + * Verifies 3-bytes hamming codes for a data block whose size is multiple of + * 256 bytes. Each 256-bytes block is verified with its own code. + * + * \return 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hamming_ERROR_ECC + * or Hamming_ERROR_MULTIPLEBITS. + * + * \param data Data buffer to verify. + * \param size Size of the data in bytes. + * \param code Original codes. + */ +uint8_t Hamming_Verify256x( uint8_t* pucData, uint32_t dwSize, const uint8_t* pucCode ) +{ + uint8_t error ; + uint8_t result = 0 ; + + TRACE_DEBUG( "Hamming_Verify256x()\n\r" ) ; + + while ( dwSize > 0 ) + { + error = Verify256( pucData, pucCode ) ; + + if ( error == Hamming_ERROR_SINGLEBIT ) + { + result = Hamming_ERROR_SINGLEBIT ; + } + else + { + if ( error ) + { + return error ; + } + } + + pucData += 256; + pucCode += 3; + dwSize -= 256; + } + + return result ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/iso7816_4.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/iso7816_4.c new file mode 100644 index 000000000..63e9ea555 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/iso7816_4.c @@ -0,0 +1,613 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * ISO 7816 driver + * + * \section Usage + * + * Explanation on the usage of the code made available through the header file. + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +/** Case for APDU commands*/ +#define CASE1 1 +#define CASE2 2 +#define CASE3 3 + +/** Flip flop for send and receive char */ +#define USART_SEND 0 +#define USART_RCV 1 + +#if !defined(BOARD_ISO7816_BASE_USART) + #define BOARD_ISO7816_BASE_USART USART1 + #define BOARD_ISO7816_ID_USART ID_USART1 +#endif + +/*----------------------------------------------------------------------------- + * Internal variables + *-----------------------------------------------------------------------------*/ +/** Variable for state of send and receive froom USART */ +static uint8_t StateUsartGlobal = USART_RCV; +/** Pin reset master card */ +static Pin st_pinIso7816RstMC; + +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ + +/** + * Get a character from ISO7816 + * \param pCharToReceive Pointer for store the received char + * \return 0: if timeout else status of US_CSR + */ +static uint32_t ISO7816_GetChar( uint8_t *pCharToReceive ) +{ + uint32_t status; + uint32_t timeout=0; + + if( StateUsartGlobal == USART_SEND ) { + while((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_TXEMPTY) == 0) {} + BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + StateUsartGlobal = USART_RCV; + } + + /* Wait USART ready for reception */ + while( ((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_RXRDY) == 0) ) { + if(timeout++ > 12000 * (BOARD_MCK/1000000)) { + TRACE_DEBUG("TimeOut\n\r"); + return( 0 ); + } + } + + TRACE_DEBUG("T: %u\n\r", timeout); + + + /* At least one complete character has been received and US_RHR has not yet been read. */ + + /* Get a char */ + *pCharToReceive = ((BOARD_ISO7816_BASE_USART->US_RHR) & 0xFF); + + status = (BOARD_ISO7816_BASE_USART->US_CSR&(US_CSR_OVRE|US_CSR_FRAME| + US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK| + (1<<10))); + + if (status != 0 ) { + /* TRACE_DEBUG("R:0x%X\n\r", status); */ + TRACE_DEBUG("R:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_CSR); + TRACE_DEBUG("Nb:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_NER ); + BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA; + } + + /* Return status */ + return( status ); +} + + +/** + * Send a char to ISO7816 + * \param CharToSend char to be send + * \return status of US_CSR + */ +static uint32_t ISO7816_SendChar( uint8_t CharToSend ) +{ + uint32_t status; + + if( StateUsartGlobal == USART_RCV ) { + BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + StateUsartGlobal = USART_SEND; + } + + /* Wait USART ready for transmit */ + while((BOARD_ISO7816_BASE_USART->US_CSR & US_CSR_TXRDY) == 0) {} + /* There is no character in the US_THR */ + + /* Transmit a char */ + BOARD_ISO7816_BASE_USART->US_THR = CharToSend; + + status = (BOARD_ISO7816_BASE_USART->US_CSR&(US_CSR_OVRE|US_CSR_FRAME| + US_CSR_PARE|US_CSR_TIMEOUT|US_CSR_NACK| + (1<<10))); + + if (status != 0 ) { + TRACE_DEBUG("E:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_CSR); + TRACE_DEBUG("Nb:0x%X\n\r", BOARD_ISO7816_BASE_USART->US_NER ); + BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA; + } + + /* Return status */ + return( status ); +} + + +/** + * Iso 7816 ICC power on + */ +static void ISO7816_IccPowerOn( void ) +{ + /* Set RESET Master Card */ + PIO_Set(&st_pinIso7816RstMC); +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Iso 7816 ICC power off + */ +void ISO7816_IccPowerOff( void ) +{ + /* Clear RESET Master Card */ + PIO_Clear(&st_pinIso7816RstMC); +} + +/** + * Transfert Block TPDU T=0 + * \param pAPDU APDU buffer + * \param pMessage Message buffer + * \param wLength Block length + * \return Message index + */ +uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength ) +{ + uint16_t NeNc; + uint16_t indexApdu = 4; + uint16_t indexMessage = 0; + uint8_t SW1 = 0; + uint8_t procByte; + uint8_t cmdCase; + uint8_t ins; + + TRACE_DEBUG("pAPDU[0]=0x%X\n\r",pAPDU[0]); + TRACE_DEBUG("pAPDU[1]=0x%X\n\r",pAPDU[1]); + TRACE_DEBUG("pAPDU[2]=0x%X\n\r",pAPDU[2]); + TRACE_DEBUG("pAPDU[3]=0x%X\n\r",pAPDU[3]); + TRACE_DEBUG("pAPDU[4]=0x%X\n\r",pAPDU[4]); + TRACE_DEBUG("pAPDU[5]=0x%X\n\r",pAPDU[5]); + TRACE_DEBUG("wlength=%d\n\r",wLength); + + ISO7816_SendChar( pAPDU[0] ); /* CLA */ + ISO7816_SendChar( pAPDU[1] ); /* INS */ + ISO7816_SendChar( pAPDU[2] ); /* P1 */ + ISO7816_SendChar( pAPDU[3] ); /* P2 */ + ISO7816_SendChar( pAPDU[4] ); /* P3 */ + + /* Handle the four structures of command APDU */ + indexApdu = 4; + + if( wLength == 4 ) { + cmdCase = CASE1; + NeNc = 0; + } + else if( wLength == 5) { + cmdCase = CASE2; + NeNc = pAPDU[4]; /* C5 */ + if (NeNc == 0) { + NeNc = 256; + } + } + else if( wLength == 6) { + NeNc = pAPDU[4]; /* C5 */ + cmdCase = CASE3; + } + else if( wLength == 7) { + NeNc = pAPDU[4]; /* C5 */ + if( NeNc == 0 ) { + cmdCase = CASE2; + NeNc = (pAPDU[5]<<8)+pAPDU[6]; + } + else { + cmdCase = CASE3; + } + } + else { + NeNc = pAPDU[4]; /* C5 */ + if( NeNc == 0 ) { + cmdCase = CASE3; + NeNc = (pAPDU[5]<<8)+pAPDU[6]; + } + else { + cmdCase = CASE3; + } + } + + TRACE_DEBUG("CASE=0x%X NeNc=0x%X\n\r", cmdCase, NeNc); + + /* Handle Procedure Bytes */ + do { + ISO7816_GetChar(&procByte); + ins = procByte ^ 0xff; + /* Handle NULL */ + if ( procByte == ISO_NULL_VAL ) { + TRACE_DEBUG("INS\n\r"); + continue; + } + /* Handle SW1 */ + else if ( ((procByte & 0xF0) ==0x60) || ((procByte & 0xF0) ==0x90) ) { + TRACE_DEBUG("SW1\n\r"); + SW1 = 1; + } + /* Handle INS */ + else if ( pAPDU[1] == procByte) { + TRACE_DEBUG("HdlINS\n\r"); + if (cmdCase == CASE2) { + /* receive data from card */ + do { + ISO7816_GetChar(&pMessage[indexMessage++]); + } while( 0 != --NeNc ); + } + else { + /* Send data */ + do { + ISO7816_SendChar(pAPDU[indexApdu++]); + } while( 0 != --NeNc ); + } + } + /* Handle INS ^ 0xff */ + else if ( pAPDU[1] == ins) { + TRACE_DEBUG("HdlINS+\n\r"); + if (cmdCase == CASE2) { + /* receive data from card */ + ISO7816_GetChar(&pMessage[indexMessage++]); + } + else { + ISO7816_SendChar(pAPDU[indexApdu++]); + } + NeNc--; + } + else { + /* ?? */ + TRACE_DEBUG("procByte=0x%X\n\r", procByte); + break; + } + } while (NeNc != 0); + + /* Status Bytes */ + if (SW1 == 0) { + ISO7816_GetChar(&pMessage[indexMessage++]); /* SW1 */ + } + else { + pMessage[indexMessage++] = procByte; + } + ISO7816_GetChar(&pMessage[indexMessage++]); /* SW2 */ + + return( indexMessage ); + +} + +/** + * Escape ISO7816 + */ +void ISO7816_Escape( void ) +{ + TRACE_DEBUG("For user, if needed\n\r"); +} + +/** + * Restart clock ISO7816 + */ +void ISO7816_RestartClock( void ) +{ + TRACE_DEBUG("ISO7816_RestartClock\n\r"); + BOARD_ISO7816_BASE_USART->US_BRGR = 13; +} + +/** + * Stop clock ISO7816 + */ +void ISO7816_StopClock( void ) +{ + TRACE_DEBUG("ISO7816_StopClock\n\r"); + BOARD_ISO7816_BASE_USART->US_BRGR = 0; +} + +/** + * T0 APDU + */ +void ISO7816_toAPDU( void ) +{ + TRACE_DEBUG("ISO7816_toAPDU\n\r"); + TRACE_DEBUG("Not supported at this time\n\r"); +} + +/** + * Answer To Reset (ATR) + * \param pAtr ATR buffer + * \param pLength Pointer for store the ATR length + */ +void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength ) +{ + uint32_t i; + uint32_t j; + uint32_t y; + + *pLength = 0; + + /* Read ATR TS */ + ISO7816_GetChar(&pAtr[0]); + /* Read ATR T0 */ + ISO7816_GetChar(&pAtr[1]); + y = pAtr[1] & 0xF0; + i = 2; + + /* Read ATR Ti */ + while (y) { + + if (y & 0x10) { /* TA[i] */ + ISO7816_GetChar(&pAtr[i++]); + } + if (y & 0x20) { /* TB[i] */ + ISO7816_GetChar(&pAtr[i++]); + } + if (y & 0x40) { /* TC[i] */ + ISO7816_GetChar(&pAtr[i++]); + } + if (y & 0x80) { /* TD[i] */ + ISO7816_GetChar(&pAtr[i]); + y = pAtr[i++] & 0xF0; + } + else { + y = 0; + } + } + + /* Historical Bytes */ + y = pAtr[1] & 0x0F; + for( j=0; j < y; j++ ) { + ISO7816_GetChar(&pAtr[i++]); + } + + *pLength = i; + +} + +/** + * Set data rate and clock frequency + * \param dwClockFrequency ICC clock frequency in KHz. + * \param dwDataRate ICC data rate in bpd + */ +void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, uint32_t dwDataRate ) +{ + uint8_t ClockFrequency; + + /* Define the baud rate divisor register */ + /* CD = MCK / SCK */ + /* SCK = FIDI x BAUD = 372 x 9600 */ + /* BOARD_MCK */ + /* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */ + BOARD_ISO7816_BASE_USART->US_BRGR = BOARD_MCK / (dwClockFrequency*1000); + + ClockFrequency = BOARD_MCK / BOARD_ISO7816_BASE_USART->US_BRGR; + + BOARD_ISO7816_BASE_USART->US_FIDI = (ClockFrequency)/dwDataRate; + +} + +/** + * Pin status for ISO7816 RESET + * \return 1 if the Pin RstMC is high; otherwise 0. + */ +uint8_t ISO7816_StatusReset( void ) +{ + return PIO_Get(&st_pinIso7816RstMC); +} + +/** + * cold reset + */ +void ISO7816_cold_reset( void ) +{ + volatile uint32_t i; + + /* tb: wait 400 cycles*/ + for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) { + } + + BOARD_ISO7816_BASE_USART->US_RHR; + BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + + ISO7816_IccPowerOn(); +} + +/** + * Warm reset + */ +void ISO7816_warm_reset( void ) +{ + volatile uint32_t i; + + ISO7816_IccPowerOff(); + + /* tb: wait 400 cycles */ + for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) { + } + + BOARD_ISO7816_BASE_USART->US_RHR; + BOARD_ISO7816_BASE_USART->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + + ISO7816_IccPowerOn(); +} + +/** + * Decode ATR trace + * \param pAtr pointer on ATR buffer + */ +void ISO7816_Decode_ATR( uint8_t* pAtr ) +{ + uint32_t i; + uint32_t j; + uint32_t y; + uint8_t offset; + + printf("\n\r"); + printf("ATR: Answer To Reset:\n\r"); + printf("TS = 0x%X Initial character ",pAtr[0]); + if( pAtr[0] == 0x3B ) { + + printf("Direct Convention\n\r"); + } + else { + if( pAtr[0] == 0x3F ) { + + printf("Inverse Convention\n\r"); + } + else { + printf("BAD Convention\n\r"); + } + } + + printf("T0 = 0x%X Format caracter\n\r",pAtr[1]); + printf(" Number of historical bytes: K = %d\n\r", pAtr[1]&0x0F); + printf(" Presence further interface byte:\n\r"); + if( pAtr[1]&0x80 ) { + printf("TA "); + } + if( pAtr[1]&0x40 ) { + printf("TB "); + } + if( pAtr[1]&0x20 ) { + printf("TC "); + } + if( pAtr[1]&0x10 ) { + printf("TD "); + } + if( pAtr[1] != 0 ) { + printf(" present\n\r"); + } + + i = 2; + y = pAtr[1] & 0xF0; + + /* Read ATR Ti */ + offset = 1; + while (y) { + + if (y & 0x10) { /* TA[i] */ + printf("TA[%d] = 0x%X ", offset, pAtr[i]); + if( offset == 1 ) { + printf("FI = %d ", (pAtr[i]>>8)); + printf("DI = %d", (pAtr[i]&0x0F)); + } + printf("\n\r"); + i++; + } + if (y & 0x20) { /* TB[i] */ + printf("TB[%d] = 0x%X\n\r", offset, pAtr[i]); + i++; + } + if (y & 0x40) { /* TC[i] */ + printf("TC[%d] = 0x%X ", offset, pAtr[i]); + if( offset == 1 ) { + printf("Extra Guard Time: N = %d", pAtr[i]); + } + printf("\n\r"); + i++; + } + if (y & 0x80) { /* TD[i] */ + printf("TD[%d] = 0x%X\n\r", offset, pAtr[i]); + y = pAtr[i++] & 0xF0; + } + else { + y = 0; + } + offset++; + } + + /* Historical Bytes */ + printf("Historical bytes:\n\r"); + y = pAtr[1] & 0x0F; + for( j=0; j < y; j++ ) { + + printf(" 0x%X", pAtr[i]); + if( (pAtr[i] > 0x21) && (pAtr[i] < 0x7D) ) { /* ASCII */ + printf("(%c) ", pAtr[i]); + } + i++; + } + printf("\n\r\n\r"); + +} + +/** Initializes a ISO driver + * \param pPinIso7816RstMC Pin ISO 7816 Rst MC + */ +void ISO7816_Init( const Pin pPinIso7816RstMC ) +{ + TRACE_DEBUG("ISO_Init\n\r"); + + /* Pin ISO7816 initialize */ + st_pinIso7816RstMC = pPinIso7816RstMC; + + USART_Configure( BOARD_ISO7816_BASE_USART, + US_MR_USART_MODE_IS07816_T_0 + | US_MR_USCLKS_MCK + | US_MR_NBSTOP_1_BIT + | US_MR_PAR_EVEN + | US_MR_CHRL_8_BIT + | US_MR_CLKO + | (3<<24), /* MAX_ITERATION */ + 1, + 0); + + /* Configure USART */ + PMC_EnablePeripheral(BOARD_ISO7816_ID_USART); + /* Disable interrupts */ + BOARD_ISO7816_BASE_USART->US_IDR = (uint32_t) -1; + + BOARD_ISO7816_BASE_USART->US_FIDI = 372; /* by default */ + /* Define the baud rate divisor register */ + /* CD = MCK / SCK */ + /* SCK = FIDI x BAUD = 372 x 9600 */ + /* BOARD_MCK */ + /* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */ + BOARD_ISO7816_BASE_USART->US_BRGR = BOARD_MCK / (372*9600); + + /* Write the Timeguard Register */ + BOARD_ISO7816_BASE_USART->US_TTGR = 5; + + USART_SetTransmitterEnabled(BOARD_ISO7816_BASE_USART, 1); + USART_SetReceiverEnabled(BOARD_ISO7816_BASE_USART, 1); + +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_draw.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_draw.c new file mode 100644 index 000000000..266277c9f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_draw.c @@ -0,0 +1,635 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup lcdd_draw + * + * Implementation of draw function on LCD, Include draw text, image + * and basic shapes (line, rectangle, circle). + * + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Local variable + *----------------------------------------------------------------------------*/ + +/** Front color cache */ +static uint32_t dwFrontColor; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * Hide canvas layer + */ +static void _HideCanvas(void) +{ + //LCDD_EnableLayer(LCDD_GetCanvas()->bLayer, 0); +} + +/** + * Update canvas + */ +static void _ShowCanvas(void) +{ + //LCDD_EnableLayer(LCDD_GetCanvas()->bLayer, 1); +} + +/** + * Set front color + * \param dwColor Pixel color. + */ +static void _SetFrontColor(uint32_t dwColor) +{ + dwFrontColor = dwColor; +} + +/** + * \brief Draw a pixel on LCD of front color. + * + * \param dwX X-coordinate of pixel. + * \param dwY Y-coordinate of pixel. + */ +static void _DrawPixel( uint32_t dwX, uint32_t dwY ) +{ + sLCDDLayer *pDisp = LCDD_GetCanvas(); + uint8_t* buffer = pDisp->pBuffer; + uint16_t w = pDisp->wImgW; + //uint16_t h = pDisp->wImgH; + uint16_t cw = pDisp->bMode/8; /* color width */ + uint32_t rw = w * cw; /* row width in bytes */ + //uint8_t r, g, b; + uint8_t *pPix; + + if (buffer == NULL) + return; + + if (rw & 0x3) rw = (rw | 0x3) + 1; /* 4-byte aligned rows */ + pPix = &buffer[dwY * rw + cw * dwX]; + + switch (pDisp->bMode) + { + case 16: /* TRGB 1555 */ + pPix[0] = (dwFrontColor ) & 0xFF; + pPix[1] = (dwFrontColor >> 8) & 0xFF; + break; + case 24: /* RGB 888 */ + pPix[0] = (dwFrontColor ) & 0xFF; + pPix[1] = (dwFrontColor >> 8) & 0xFF; + pPix[2] = (dwFrontColor >> 16) & 0xFF; + break; + case 32: /* ARGB 8888 */ + pPix[0] = (dwFrontColor ) & 0xFF; + pPix[1] = (dwFrontColor >> 8) & 0xFF; + pPix[2] = (dwFrontColor >> 16) & 0xFF; + pPix[3] = (dwFrontColor >> 24) & 0xFF; + break; + } +} + +/** + * \brief Fill rectangle with front color. + * \param dwX1 X-coordinate of top left. + * \param dwY1 Y-coordinate of top left. + * \param dwX2 X-coordinate of bottom right. + * \param dwY1 Y-coordinate of bottom right. + */ +static void _FillRect( uint32_t dwX1, uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 ) +{ + sLCDDLayer *pDisp = LCDD_GetCanvas(); + uint16_t w = pDisp->wImgW; + uint16_t cw = pDisp->bMode/8; /* color width */ + uint32_t rw = w * cw; /* row width in bytes */ + uint8_t *base = pDisp->pBuffer; + uint8_t *buffer = pDisp->pBuffer; + uint32_t fillStart, fillEnd; + uint32_t i; + if (buffer == NULL) return; + + /* 4-byte aligned rows */ + if (rw & 0x3) rw = (rw | 0x3) + 1; + /* Buffer address for the starting row */ + base = &buffer[dwY1*rw]; + + fillStart = dwX1 * cw; + fillEnd = dwX2 * cw; + + #if 1 /* Memcopy pixel */ + buffer = base; + for (; dwY1 <= dwY2; dwY1 ++) + { + for (i = fillStart; i <= fillEnd; i += cw) + { + memcpy(&buffer[i], &dwFrontColor, cw); + } + buffer = &buffer[rw]; + } + #endif + + #if 0 /* Pixel by pixel */ + for (; dwY1 <= dwY2; dwY1 ++) + { + for (i = dwX1; i <= dwX2; i ++) + { + _DrawPixel(i, dwY1); + } + } + #endif + + #if 0 /* Optimized */ + /* First row */ + for (i = fillStart; i <= fillEnd; i += cw) + { + memcpy(&base[i], &dwFrontColor, cw); + } + /* Next rows, copy first */ + buffer = &base[rw + fillStart]; + for (i = dwY1 + 1; i <= dwY2; i ++) + { + memcpy(buffer, &base[fillStart], fillEnd - fillStart + cw); + buffer = &buffer[rw]; + } + #endif +} + +/** + * \brief Draw a line on LCD, which is not horizontal or vertical. + * + * \param dwX1 X-coordinate of line start. + * \param dwY1 Y-coordinate of line start. + * \param dwX2 X-coordinate of line end. + * \param dwY2 Y-coordinate of line end. + */ +static uint32_t _DrawLineBresenham( uint32_t dwX1, uint32_t dwY1, + uint32_t dwX2, uint32_t dwY2 ) +{ + int dx, dy ; + int i ; + int xinc, yinc, cumul ; + int x, y ; + + x = dwX1 ; + y = dwY1 ; + dx = dwX2 - dwX1 ; + dy = dwY2 - dwY1 ; + + xinc = ( dx > 0 ) ? 1 : -1 ; + yinc = ( dy > 0 ) ? 1 : -1 ; + dx = ( dx > 0 ) ? dx : -dx ; + dy = ( dy > 0 ) ? dy : -dy ; + + _DrawPixel( x, y ) ; + + if ( dx > dy ) + { + cumul = dx / 2 ; + for ( i = 1 ; i <= dx ; i++ ) + { + x += xinc ; + cumul += dy ; + + if ( cumul >= dx ) + { + cumul -= dx ; + y += yinc ; + } + _DrawPixel( x, y ) ; + } + } + else + { + cumul = dy / 2 ; + for ( i = 1 ; i <= dy ; i++ ) + { + y += yinc ; + cumul += dx ; + + if ( cumul >= dy ) + { + cumul -= dy ; + x += xinc ; + } + + _DrawPixel( x, y ) ; + } + } + + return 0 ; +} + + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Fills the given LCD buffer with a particular color. + * + * \param color Fill color. + */ +void LCDD_Fill( uint32_t dwColor ) +{ + sLCDDLayer *pDisp = LCDD_GetCanvas(); + _SetFrontColor(dwColor); + _HideCanvas(); + _FillRect( 0, 0, pDisp->wImgW, pDisp->wImgH ); + _ShowCanvas(); +} + +void LCDD_Fill0(void) +{ + sLCDDLayer *pDisp = LCDD_GetCanvas(); + _HideCanvas(); + _SetFrontColor(0xFF0000); + _FillRect( 0, 0, pDisp->wImgW/3, pDisp->wImgH ); + _SetFrontColor(0x00FF00); + _FillRect( pDisp->wImgW/3, 0, pDisp->wImgW/3+pDisp->wImgW/3, pDisp->wImgH ); + _SetFrontColor(0x0000FF); + _FillRect( pDisp->wImgW/3+pDisp->wImgW/3, 0, pDisp->wImgW, pDisp->wImgH ); + _ShowCanvas(); +} +/** + * \brief Draw a pixel on LCD of given color. + * + * \param x X-coordinate of pixel. + * \param y Y-coordinate of pixel. + * \param color Pixel color. + */ +extern void LCDD_DrawPixel( uint32_t x, uint32_t y, uint32_t color ) +{ + _SetFrontColor(color); + _HideCanvas(); + _DrawPixel(x, y); + _ShowCanvas(); +} + +/** + * \brief Read a pixel from LCD. + * + * \param x X-coordinate of pixel. + * \param y Y-coordinate of pixel. + * + * \return color Readed pixel color. + */ +extern uint32_t LCDD_ReadPixel( uint32_t x, uint32_t y ) +{ + sLCDDLayer *pDisp = LCDD_GetCanvas(); + uint8_t* buffer = pDisp->pBuffer; + uint16_t w = pDisp->wImgW; + //uint16_t h = pDisp->wImgH; + uint16_t cw = pDisp->bMode/8; /* color width */ + uint32_t rw = w * cw; /* row width in bytes */ + uint8_t *pPix; + uint32_t color = 0; + + if (buffer == NULL) return 0; + + if (rw & 0x3) rw = (rw | 0x3) + 1; /* 4-byte aligned rows */ + pPix = &buffer[x * rw + cw * y]; + + switch (pDisp->bMode) + { + case 16: /* TRGB 1555 */ + color = pPix[0] | (pPix[1] << 8); + break; + case 24: /* RGB 888 */ + color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16); + break; + case 32: /* ARGB 8888 */ + color = pPix[0] | (pPix[1] << 8) | (pPix[2] << 16) | (pPix[3] << 24); + break; + } + return color; +} + +/** + * \brief Draw a line on LCD, horizontal and vertical line are supported. + * + * \param x1 X-coordinate of line start. + * \param y1 Y-coordinate of line start. + * \param x2 X-coordinate of line end. + * \param y2 Y-coordinate of line end. + * \param color Pixel color. + */ +extern void LCDD_DrawLine( uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2, uint32_t color ) +{ + _SetFrontColor(color); + if ( (x1 == x2) || (y1 == y2) ) + { + LCDD_DrawFilledRectangle(x1, y1, x2, y2, color); + } + else + { + _HideCanvas(); + _DrawLineBresenham(x1, y1, x2, y2); + _ShowCanvas(); + } +} + +/** + * \brief Draws a rectangle on LCD, at the given coordinates. + * + * \param x X-coordinate of upper-left rectangle corner. + * \param y Y-coordinate of upper-left rectangle corner. + * \param width Rectangle width in pixels. + * \param height Rectangle height in pixels. + * \param color Rectangle color. + */ +extern void LCDD_DrawRectangle( uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint32_t color ) +{ + uint32_t x1 = x + width - 1; + uint32_t y1 = y + height - 1; + + _SetFrontColor(color); + _HideCanvas(); + _FillRect(x , y , x1, y ); + _FillRect(x1, y , x1, y1); + _FillRect(x , y , x , y1); + _FillRect(x , y1, x1, y1); + _ShowCanvas(); +} + +/** + * \brief Draws a rectangle with fill inside on LCD, at the given coordinates. + * + * \param dwX1 X-coordinate of upper-left rectangle corner. + * \param dwY1 Y-coordinate of upper-left rectangle corner. + * \param dwX2 X-coordinate of down-right rectangle corner. + * \param dwY2 Y-coordinate of down-right rectangle corner. + * \param color Rectangle color. + */ +extern void LCDD_DrawFilledRectangle( uint32_t dwX1, uint32_t dwY1, + uint32_t dwX2, uint32_t dwY2, + uint32_t dwColor ) +{ + _SetFrontColor(dwColor); + _HideCanvas(); + _FillRect(dwX1, dwY1, dwX2, dwY2); + _ShowCanvas(); +} + +/** + * \brief Draws a circle on LCD, at the given coordinates. + * + * \param dwX X-coordinate of circle center. + * \param dwY Y-coordinate of circle center. + * \param dwR circle radius. + * \param dwColor circle color. + */ +extern void LCDD_DrawCircle( uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t dwColor ) +{ + int32_t d; /* Decision Variable */ + uint32_t curX; /* Current X Value */ + uint32_t curY; /* Current Y Value */ + + if (dwR == 0) return; + _SetFrontColor(dwColor); + + d = 3 - (dwR << 1); + curX = 0; + curY = dwR; + + _HideCanvas(); + while (curX <= curY) + { + _DrawPixel(dwX + curX, dwY + curY); + _DrawPixel(dwX + curX, dwY - curY); + _DrawPixel(dwX - curX, dwY + curY); + _DrawPixel(dwX - curX, dwY - curY); + _DrawPixel(dwX + curY, dwY + curX); + _DrawPixel(dwX + curY, dwY - curX); + _DrawPixel(dwX - curY, dwY + curX); + _DrawPixel(dwX - curY, dwY - curX); + + if (d < 0) { + d += (curX << 2) + 6; + } + else { + d += ((curX - curY) << 2) + 10; + curY--; + } + curX++; + } + _ShowCanvas(); +} + + +/** + * \brief Draws a filled circle on LCD, at the given coordinates. + * + * \param dwX X-coordinate of circle center. + * \param dwY Y-coordinate of circle center. + * \param dwR circle radius. + * \param dwColor circle color. + */ +void LCDD_DrawFilledCircle( uint32_t dwX, uint32_t dwY, uint32_t dwR, uint32_t dwColor ) +{ + signed int d ; // Decision Variable + uint32_t dwCurX ; // Current X Value + uint32_t dwCurY ; // Current Y Value + uint32_t dwXmin, dwYmin; + + if (dwR == 0) return; + _SetFrontColor(dwColor); + + d = 3 - (dwR << 1) ; + dwCurX = 0 ; + dwCurY = dwR ; + + _HideCanvas(); + while ( dwCurX <= dwCurY ) + { + dwXmin = (dwCurX > dwX) ? 0 : dwX-dwCurX; + dwYmin = (dwCurY > dwY) ? 0 : dwY-dwCurY; + _FillRect( dwXmin, dwYmin, dwX+dwCurX, dwYmin ) ; + _FillRect( dwXmin, dwY+dwCurY, dwX+dwCurX, dwY+dwCurY ) ; + dwXmin = (dwCurY > dwX) ? 0 : dwX-dwCurY; + dwYmin = (dwCurX > dwY) ? 0 : dwY-dwCurX; + _FillRect( dwXmin, dwYmin, dwX+dwCurY, dwYmin ) ; + _FillRect( dwXmin, dwY+dwCurX, dwX+dwCurY, dwY+dwCurX ) ; + + if ( d < 0 ) + { + d += (dwCurX << 2) + 6 ; + } + else + { + d += ((dwCurX - dwCurY) << 2) + 10; + dwCurY-- ; + } + + dwCurX++ ; + } + _ShowCanvas(); +} + +/** + * \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks + * will be honored. + * + * \param x X-coordinate of string top-left corner. + * \param y Y-coordinate of string top-left corner. + * \param pString String to display. + * \param color String color. + */ +extern void LCDD_DrawString( uint32_t x, uint32_t y, const char *pString, uint32_t color ) +{ + uint32_t xorg = x; + while (*pString) + { + if (*pString == '\n') + { + y += gFont.height + 2; x = xorg; + } + else + { + LCDD_DrawChar(x, y, *pString, color); + x += gFont.width + 2; + } + pString ++; + } +} + +/** + * \brief Draws a string inside a LCD buffer, at the given coordinates + * with given background color. Line breaks will be honored. + * + * \param x X-coordinate of string top-left corner. + * \param y Y-coordinate of string top-left corner. + * \param pString String to display. + * \param fontColor String color. + * \param bgColor Background color. + */ +extern void LCDD_DrawStringWithBGColor( uint32_t x, uint32_t y, const char *pString, uint32_t fontColor, uint32_t bgColor ) +{ + uint32_t xorg = x; + while (*pString) + { + if (*pString == '\n') + { + y += gFont.height + 2; x = xorg; + } + else + { + LCDD_DrawCharWithBGColor(x, y, *pString, fontColor, bgColor); + x += gFont.width + 2; + } + pString ++; + } +} + +/** + * \brief Returns the width & height in pixels that a string will occupy on the screen + * if drawn using LCDD_DrawString. + * + * \param pString String. + * \param pWidth Pointer for storing the string width (optional). + * \param pHeight Pointer for storing the string height (optional). + * + * \return String width in pixels. + */ +extern void LCDD_GetStringSize( const char *pString, uint32_t *pWidth, uint32_t *pHeight ) +{ + uint32_t width = 0; + uint32_t height = gFont.height; + while (*pString) + { + if (*pString == '\n') height += gFont.height + 2; + else width += gFont.height + 2; + pString ++; + } + if (width > 0) width -= 2; + + if (pWidth) *pWidth = width; + if (pHeight)*pHeight = height; +} + +/** + * \brief Draw a raw image at given position on LCD. + * + * \param x X-coordinate of image start. + * \param y Y-coordinate of image start. + * \param pImage Image buffer. + * \param width Image width. + * \param height Image height. + */ +void LCDD_DrawImage( uint32_t dwX, uint32_t dwY, const uint8_t *pImage, uint32_t dwWidth, uint32_t dwHeight ) +{ + sLCDDLayer *pDisp = LCDD_GetCanvas(); + uint16_t cw = pDisp->bMode/8; /* color width */ + uint32_t rw = pDisp->wImgW * cw; /* Row width in bytes */ + uint32_t rws = dwWidth * cw; /* Source Row Width */ + uint32_t rl = (rw & 0x3) ? ((rw | 0x3) + 1) : rw; /* Aligned length*/ + uint32_t rls = (rws & 0x3) ? ((rws | 0x3) + 1) : rws; /* Aligned length */ + uint8_t *pSrc, *pDst; + uint32_t i; + + pSrc = (uint8_t*)pImage; + pDst = pDisp->pBuffer; + pDst = &pDst[dwX*cw + dwY*rl]; + + for (i = 0; i < dwHeight; i ++) + { + memcpy(pDst, pSrc, rws); + pSrc = &pSrc[rls]; + pDst = &pDst[rl]; + } +} + + +/** + * \brief Clear a window with an color. + * + * \param dwX X-coordinate of the window. + * \param dwY Y-coordinate of the window. + * \param dwWidth window width. + * \param dwHeight window height. + * \param dwColor background color + */ +extern void LCDD_ClearWindow( uint32_t dwX, uint32_t dwY, uint32_t dwWidth, uint32_t dwHeight, uint32_t dwColor ) +{ + _SetFrontColor(dwColor); + _HideCanvas(); + _FillRect(0, 0, dwX + dwWidth - 1, dwY + dwHeight - 1); + _ShowCanvas(); +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_font.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_font.c new file mode 100644 index 000000000..c10fcc1c2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_font.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * + * Implementation of draw font on LCD. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Global variable describing the font being instancied. */ +const Font gFont = {10, 14}; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Draws an ASCII character on LCD. + * + * \param x X-coordinate of character upper-left corner. + * \param y Y-coordinate of character upper-left corner. + * \param c Character to output. + * \param color Character color. + */ +extern void LCDD_DrawChar( uint32_t x, uint32_t y, uint8_t c, uint32_t color ) +{ + uint32_t row, col ; + + assert( (c >= 0x20) && (c <= 0x7F) ) ; + + for ( col = 0 ; col < 10 ; col++ ) + { + for ( row = 0 ; row < 8 ; row++ ) + { + if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 ) + { + LCDD_DrawPixel( x+col, y+row, color ) ; + } + } + + for (row = 0; row < 6; row++ ) + { + if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1) + { + LCDD_DrawPixel( x+col, y+row+8, color ) ; + } + } + } +} + +/** + * \brief Draws an ASCII character on LCD with given background color. + * + * \param x X-coordinate of character upper-left corner. + * \param y Y-coordinate of character upper-left corner. + * \param c Character to output. + * \param fontColor Character color. + * \param bgColor Background color. + */ +extern void LCDD_DrawCharWithBGColor( uint32_t x, uint32_t y, uint8_t c, uint32_t fontColor, uint32_t bgColor ) +{ + uint32_t row, col ; + + assert( (c >= 0x20) && (c <= 0x7F) ) ; + + for (col = 0; col < 10; col++) + { + for (row = 0 ; row < 8 ; row++) + { + if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1 ) + { + LCDD_DrawPixel( x+col, y+row, fontColor ) ; + } + else + { + LCDD_DrawPixel( x+col, y+row, bgColor ) ; + } + } + + for ( row = 0 ; row < 6 ; row++ ) + { + if ( (pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1 ) + { + LCDD_DrawPixel( x+col, y+row+8, fontColor ) ; + } + else + { + LCDD_DrawPixel( x+col, y+row+8, bgColor ) ; + } + } + } +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_font10x14.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_font10x14.c new file mode 100644 index 000000000..0a6b9fb31 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcd_font10x14.c @@ -0,0 +1,239 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Font 10x14 table definition. + * + */ + +/** \addtogroup font_10x14 + *@{ + */ +#include "board.h" + +/** Char set of font 10x14 */ +const uint8_t pCharset10x14[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC, + 0xFF, 0xCC, 0x00, 0x00, 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0x3C, 0x0C, 0x7C, 0x0C, 0xEC, + 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, + 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8, + 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, + 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C, + 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C, + 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, + 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, + 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, + 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, + 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC +} ; + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcdd.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcdd.c new file mode 100644 index 000000000..c3a3ee587 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/lcdd.c @@ -0,0 +1,1640 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include +#include + +#ifdef LCDC +/** \addtogroup lcdd_base + * Implementation of LCD driver, Include LCD initialization, + * LCD on/off and LCD backlight control. + */ +/**@{*/ + +/*---------------------------------------------------------------------------- + * Local types + *----------------------------------------------------------------------------*/ + +/** DMA descriptor for LCDC */ +typedef struct _LCDCDescriptor { + uint32_t addr; + uint32_t ctrl; + uint32_t next; +}sLCDCDescriptor; + +/** CULT information */ +typedef struct _CLUTInfo { + uint8_t bpp; + uint8_t nbColors; +}sCLUTInfo; + +/** LCDC General Layer information */ +typedef struct _Layer { + sLCDCDescriptor dmaD; + void* pBuffer; + sCLUTInfo clut; + uint16_t reserved; +} sLayer; + +/** LCDC HEO Layer information */ +typedef struct _HeoLayer { + sLCDCDescriptor dmaD[3]; + void* pBuffer; + sCLUTInfo clut; + uint16_t reserved; +} sHeoLayer; + +/** Pins for LCDC */ +static const Pin pPinsLCD[] = {PINS_LCD}; + +/** Current selected canvas information */ +static sLCDDLayer lcddCanvas; +/** Base Layer */ + +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma data_alignment=64 +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((aligned(64))) +#endif +static sLayer lcddBase; + +/** Overlay 1 Layer */ +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma data_alignment=64 +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((aligned(64))) +#endif +static sLayer lcddOvr1; + +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma data_alignment=64 +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((aligned(64))) +#endif +static sLayer lcddOvr2; + +/** High End Overlay Layer */ +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma data_alignment=64 +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((aligned(64))) +#endif +static sHeoLayer lcddHeo; + +/** Hardware cursor Layer */ +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma data_alignment=64 +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((aligned(64))) +#endif +static sLayer lcddHcc; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * Return a pointer to layer. + * \param bLayer Layer ID. + */ +static sLayer *pLayer( uint8_t bLayer ) +{ + switch( bLayer ) + { + case LCDD_BASE: return &lcddBase; + case LCDD_OVR1: return &lcddOvr1; + case LCDD_OVR2: return &lcddOvr2; + case LCDD_HEO: return (sLayer*)&lcddHeo; + case LCDD_CUR: return &lcddHcc; + } + return NULL; +} + +/** + * Return true if Pixel stride supported. + * \param bLayer Layer ID. + */ +static uint8_t LCDD_IsPStrideSupported( uint8_t bLayer ) +{ + switch( bLayer ) + { + case LCDD_OVR1: case LCDD_OVR2:case LCDD_HEO: return 1; + default: return 0; + } +} + +/** + * Return a pointer to enable register. + * (Starts following register list: _ER, _DR, _SR, _IER, _IDR, _IMR, _ISR) + * \param bLayer Layer ID. + */ +static volatile uint32_t *pEnableReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_CONTROLLER: return (volatile uint32_t*)&pHw->LCDC_LCDEN; + case LCDD_BASE: return (volatile uint32_t*)&pHw->LCDC_BASECHER; + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1CHER; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2CHER; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCHER; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRCHER; + } + return NULL; +} + +/** + * Return a pointer to blender configuration register. + * \param bLayer Layer ID. + */ +static volatile uint32_t *pBlenderReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_BASE: return (volatile uint32_t *)&pHw->LCDC_BASECFG4; + case LCDD_OVR1: return (volatile uint32_t *)&pHw->LCDC_OVR1CFG9; + case LCDD_OVR2: return (volatile uint32_t *)&pHw->LCDC_OVR2CFG9; + case LCDD_HEO: return (volatile uint32_t *)&pHw->LCDC_HEOCFG12; + case LCDD_CUR: return (volatile uint32_t *)&pHw->LCDC_HCRCFG9; + } + return NULL; +} + +/** + * Return a pointer to DMA head register. + * (Starts following register list: _HEAD, _ADDRESS, _CONTROL, _NEXT) + * \param bLayer Layer ID. + */ +static volatile uint32_t *pHeadReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_BASE: return (volatile uint32_t*)&pHw->LCDC_BASEHEAD; + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1HEAD; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2HEAD; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOHEAD; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRHEAD; + } + return NULL; +} + +/** + * Return a pointer to layer configure register. + * (Including: _CFG0, _CFG1 (RGB mode ...)) + * \param bLayer Layer ID. + */ +static volatile uint32_t *pCfgReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_BASE: return (volatile uint32_t*)&pHw->LCDC_BASECFG0; + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1CFG0; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2CFG0; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCFG0; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRCFG0; + } + return NULL; +} + +/** + * Return a pointer to Window configure register. + * (Including: X Y register, W H register) + * \param bLayer Layer ID. + */ +static volatile uint32_t *pWinReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1CFG2; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2CFG2; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCFG2; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRCFG2; + } + return NULL; +} + +/** + * Return a pointer to striding regiters. + * \param bLayer Layer ID. + */ +static volatile uint32_t *pStrideReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_BASE: return (volatile uint32_t*)&pHw->LCDC_BASECFG2; + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1CFG4; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2CFG4; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCFG5; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRCFG4; + } + return NULL; +} + +/** + * Return a pointer to Color configure regiters. + * (Including: RGB Default, RGB Key, RGB Mask) + * Note that base layer only has one register (default). + * \param bLayer Layer ID. + */ +static volatile uint32_t *pColorReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_BASE: return (volatile uint32_t*)&pHw->LCDC_BASECFG3; + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1CFG6; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2CFG6; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCFG9; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRCFG6; + } + return NULL; +} + +/** + * Return a pointer to scaling register. + * \param bLayer Layer ID. + */ +static volatile uint32_t *pScaleReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCFG13; + } + return NULL; +} + +/** + * Return bits per pixel from RGB mode settings. + * (Note the bits is bits occupied in memory, including reserved) + */ +static uint32_t LCDD_GetBitsPerPixel(uint32_t modeReg) +{ + switch (modeReg) + { + /* RGB mode */ + case LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444: + case LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444: + case LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444: + case LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565: + case LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555: + return 2*8; + + case LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666PACKED: + case LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED: + case LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED: + return 3*8; + + case LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666: + case LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666: + case LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888: + case LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888: + case LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888: + case LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888: + return 3*8; + + /* CLUT mode */ + + case LCDC_HEOCFG1_CLUTMODE_CLUT_1BPP | LCDC_HEOCFG1_CLUTEN: return 1; + case LCDC_HEOCFG1_CLUTMODE_CLUT_2BPP | LCDC_HEOCFG1_CLUTEN: return 2; + case LCDC_HEOCFG1_CLUTMODE_CLUT_4BPP | LCDC_HEOCFG1_CLUTEN: return 4; + case LCDC_HEOCFG1_CLUTMODE_CLUT_8BPP | LCDC_HEOCFG1_CLUTEN: return 8; + + /* YUV mode */ + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR: + return 32; + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR: + case LCDC_HEOCFG1_YUVEN | LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR: + return 16; + } + return 0; +} + +/** + * Enable a LCDC DMA channel + */ +static void LCDD_SetDMA( void* pBuffer, + sLCDCDescriptor *pTD, + uint32_t regAddr) +{ + volatile uint32_t *pDmaR = (volatile uint32_t*)regAddr; + /* Modify descriptor */ + pTD->addr = (uint32_t)pBuffer; + pTD->ctrl = LCDC_BASECTRL_DFETCH; + pTD->next = (uint32_t)pTD; + /* Modify registers */ + pDmaR[1] = (uint32_t)pBuffer; + pDmaR[2] = LCDC_BASECTRL_DFETCH; + pDmaR[3] = (uint32_t)pTD; +} + +/** + * Disable a LCDC DMA channel + */ +static void LCDD_ClearDMA( sLCDCDescriptor *pTD, uint32_t regAddr ) +{ + uint32_t *pReg = (uint32_t *)regAddr; + volatile uint32_t *pRegCtrl = (volatile uint32_t*)&pReg[1]; + volatile uint32_t *pRegNext = (volatile uint32_t*)&pReg[2]; + + /* Modify descriptor */ + if (pTD) + { + pTD->ctrl &= ~LCDC_BASECTRL_DFETCH; + pTD->next = (uint32_t)pTD; + } + /* Modify control registers */ + *pRegCtrl &= ~LCDC_BASECTRL_DFETCH; + *pRegNext = (uint32_t)pTD; +} + +/** + * Return scaling factor + */ +static uint32_t LCDD_CalcScaleFactor(uint32_t targetW, uint32_t imgW) +{ + uint32_t factor; + + factor = 2048 * (imgW + 1) / (targetW + 1); + + //factor = 1024 * (imgW + 1) / (targetW + 1); + //if (targetW > imgW * 2) + // factor -= 7; + return factor; +} + +/** + * Return a pointer to Color Palette lookup regiters. + * \param bLayer Layer ID. + */ +static volatile uint32_t *pCLUTReg( uint8_t bLayer ) +{ + Lcdc *pHw = LCDC; + switch( bLayer ) + { + case LCDD_BASE: return (volatile uint32_t*)&pHw->LCDC_BASECLUT[0]; + case LCDD_OVR1: return (volatile uint32_t*)&pHw->LCDC_OVR1CLUT[0]; + case LCDD_OVR2: return (volatile uint32_t*)&pHw->LCDC_OVR2CLUT[0]; + case LCDD_HEO: return (volatile uint32_t*)&pHw->LCDC_HEOCLUT[0]; + case LCDD_CUR: return (volatile uint32_t*)&pHw->LCDC_HCRCLUT[0]; + } + return NULL; +} + +/** + * Build 8-bit color palette (actually true color) + */ +static void LCDD_BuildCLUT8(volatile uint32_t* pCLUT) +{ + uint32_t r, g, b; /* 3:3:2 */ + for (r = 0; r < 8; r ++) + { + for (g = 0; g < 8; g ++) + { + for (b = 0; b < 4; b ++) + { + *pCLUT ++ = (r << (16 + 5)) + + (g << (8 + 5)) + + (b << (0 + 6)); + } + } + } +} + +/** + * Build 4-bit color palette (16 color) + */ +static void LCDD_BuildCLUT4(volatile uint32_t* pCLUT) +{ + uint32_t r, g, b; + for (r = 0; r < 4; r ++) + { + for (g = 0; g < 2; g ++) + { + for (b = 0; b < 2; b ++) + { + *pCLUT ++ = (r << (16 + 6)) + + (g << (8 + 7)) + + (b << (0 + 7)); + } + } + } +} + +/** + * Build 2-bit color palette (4 gray) + */ +static void LCDD_BuildCLUT2(volatile uint32_t* pCLUT) +{ + pCLUT[0] = 0x000000; + pCLUT[1] = 0x505050; + pCLUT[2] = 0xA0A0A0; + pCLUT[3] = 0xFFFFFF; +} + +/** + * Build 1-bit color palette (black & white) + */ +static void LCDD_BuildCLUT1(volatile uint32_t* pCLUT) +{ + pCLUT[0] = 0x000000; + pCLUT[1] = 0xFFFFFF; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes the LCD controller. + * Configure SMC to access LCD controller at 64MHz MCK. + */ +void LCDD_Initialize( void ) +{ + Lcdc *pHw = LCDC; + Pmc *pPmc = PMC; + + /* Configure PIO */ + PIO_Configure(pPinsLCD, PIO_LISTSIZE(pPinsLCD)); + + LCDD_Off(); + + /* Reset CLUT information */ + lcddBase.clut.bpp = 0; + lcddOvr1.clut.bpp = 0; + lcddOvr2.clut.bpp = 0; + lcddHeo.clut.bpp = 0; + lcddHcc.clut.bpp = 0; + + /* Reset layer information */ + lcddBase.pBuffer = NULL; + lcddOvr1.pBuffer = NULL; + lcddOvr2.pBuffer = NULL; + lcddHeo.pBuffer = NULL; + lcddHcc.pBuffer = NULL; + + /* No canvas selected */ + lcddCanvas.pBuffer = NULL; + + /* Enable peripheral clock */ + PMC_EnablePeripheral(ID_LCDC); + pPmc->PMC_SCER = (0x1u << 3); + + /* Timing Engine Configuration */ + + /* Disable interrupt */ + pHw->LCDC_LCDIDR = 0xFFFFFFFF; + + /* Configure channels */ + + /* Base */ + pHw->LCDC_BASECFG0 = LCDC_BASECFG0_DLBO | LCDC_BASECFG0_BLEN_AHB_INCR16; + pHw->LCDC_BASECFG1 = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED; + + /* Overlay 1, GA 0xFF */ + pHw->LCDC_OVR1CFG0 = LCDC_OVR1CFG0_DLBO | LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR16 + | LCDC_OVR1CFG0_ROTDIS + ; + pHw->LCDC_OVR1CFG1 = LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED; + pHw->LCDC_OVR1CFG9 = LCDC_OVR1CFG9_GA(0xFF) | LCDC_OVR1CFG9_GAEN; + + /* Overlay 2, GA 0xFF */ + pHw->LCDC_OVR2CFG0 = LCDC_OVR2CFG0_DLBO | LCDC_OVR2CFG0_BLEN_AHB_INCR16 + | LCDC_OVR2CFG0_ROTDIS + ; + pHw->LCDC_OVR2CFG1 = LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888_PACKED; + pHw->LCDC_OVR2CFG9 = LCDC_OVR2CFG9_GA(0xFF) | LCDC_OVR2CFG9_GAEN; + + /* High End Overlay, GA 0xFF */ + pHw->LCDC_HEOCFG0 = LCDC_HEOCFG0_DLBO | LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR16 + | LCDC_HEOCFG0_ROTDIS + ; + pHw->LCDC_HEOCFG1 = LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED; + pHw->LCDC_HEOCFG12 = LCDC_HEOCFG12_GA(0xFF) | LCDC_HEOCFG12_GAEN; + + /* Hardware Cursor, GA 0xFF, Key #000000 */ + pHw->LCDC_HCRCFG0 = LCDC_HCRCFG0_DLBO | LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR16; + pHw->LCDC_HCRCFG1 = LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED; + pHw->LCDC_HCRCFG7 = 0x000000; + pHw->LCDC_HCRCFG8 = 0xFFFFFF; + pHw->LCDC_HCRCFG9 = LCDC_HCRCFG9_GA(0xFF) | LCDC_HCRCFG9_GAEN; + + LCDD_On(); +} + +/** + * Check if specified layer is working. + * \param bLayer Layer ID. + * \return 1 if layer is on. + */ +uint8_t LCDD_IsLayerOn( uint8_t bLayer ) +{ + volatile uint32_t *pReg = pEnableReg(bLayer); + if (pReg) return ((pReg[2] & LCDC_BASECHSR_CHSR) > 0); + return 0; +} + +/** + * Enable(turn on)/Disable(hide) specified layer. + * \param bLayer Layer ID. + * \param bEnDis Enable/Disable. + */ +void LCDD_EnableLayer( uint8_t bLayer, uint8_t bEnDis ) +{ + volatile uint32_t *pReg = pEnableReg(bLayer); + volatile uint32_t *pBlR = pBlenderReg(bLayer); + if (pReg && bLayer > LCDD_CONTROLLER) + { + if (bEnDis) + { + pReg[0] = LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN; + pBlR[0] |= LCDC_HEOCFG12_DMA | LCDC_HEOCFG12_OVR; + } + else + { + pReg[1] = LCDC_BASECHDR_CHDIS; + pBlR[0] &= ~(LCDC_HEOCFG12_DMA | LCDC_HEOCFG12_OVR); + } + } +} + +/** + * Refresh layer + * \param bLayer Layer ID. + */ +void LCDD_Refresh( uint8_t bLayer ) +{ + volatile uint32_t *pBlR = pBlenderReg(bLayer); + volatile uint32_t *pEnR = pEnableReg(bLayer); + if (pBlR) + { + if (pEnR[2] & LCDC_OVR1CHSR_CHSR) + { + pBlR[0] |= LCDC_HEOCFG12_DMA; + pEnR[0] = LCDC_OVR1CHER_UPDATEEN; + } + } +} + +/** + * Set display window position. + * \param bLayer Layer ID. + * \param x X position. + * \param y Y position. + */ +void LCDD_SetPosition( uint8_t bLayer, + uint32_t x, uint32_t y ) +{ + volatile uint32_t *pChReg = pEnableReg(bLayer); + volatile uint32_t *pXyReg = pWinReg(bLayer); + uint32_t w, h; + + w = (pXyReg[1] & LCDC_OVR1CFG3_XSIZE_Msk) >> LCDC_OVR1CFG3_XSIZE_Pos; + h = (pXyReg[1] & LCDC_OVR1CFG3_YSIZE_Msk) >> LCDC_OVR1CFG3_YSIZE_Pos; + + if (x+w >= BOARD_LCD_WIDTH) x = BOARD_LCD_WIDTH - w; + if (y+h >= BOARD_LCD_HEIGHT) y = BOARD_LCD_HEIGHT - h; + + if (pXyReg) + { + pXyReg[0] = LCDC_OVR1CFG2_XPOS(x) | LCDC_OVR1CFG2_YPOS(y); + if (pChReg[2] & LCDC_OVR1CHSR_CHSR) + pChReg[0] = LCDC_OVR1CHER_UPDATEEN; + } +} + +/** + * Set Prioty of layer (only for HEO now). + * \param bLayer Layer ID (HEO). + * \param bPri Prority value. + */ +void LCDD_SetPrioty( uint8_t bLayer, uint8_t bPri ) +{ + Lcdc * pHw = LCDC; + if ( bLayer != LCDD_HEO ) return; + if (bPri) + pHw->LCDC_HEOCFG12 |= LCDC_HEOCFG12_VIDPRI; + else + pHw->LCDC_HEOCFG12 &= ~LCDC_HEOCFG12_VIDPRI; + pHw->LCDC_HEOCHER = LCDC_HEOCHER_UPDATEEN; +} + +/** + * Return Prioty of layer (only for HEO now). + * \param bLayer Layer ID (HEO). + */ +uint8_t LCDD_GetPrioty( uint8_t bLayer ) +{ + Lcdc * pHw = LCDC; + if ( bLayer != LCDD_HEO ) return 0; + return (pHw->LCDC_HEOCFG12 & LCDC_HEOCFG12_VIDPRI) > 0; +} + +/** + * Global & Local Alpha Enable/Disable + * \param bLayer Layer ID. + * \param bEnDisLA Enable/Disable local alpha. + * \param bEnDisGA Enable/Disable global alpha. + */ +void LCDD_EnableAlpha( uint8_t bLayer, + uint8_t bEnDisLA, + uint8_t bEnDisGA ) +{ + volatile uint32_t *pEnR = pEnableReg(bLayer); + volatile uint32_t *pCfgR = pBlenderReg(bLayer); + uint32_t cfg; + if (pCfgR) + { + cfg = (*pCfgR) & ~(LCDC_OVR1CFG9_LAEN | LCDC_OVR1CFG9_GAEN); + if (bEnDisGA) cfg |= LCDC_OVR1CFG9_GAEN; + if (bEnDisLA) cfg |= LCDC_OVR1CFG9_LAEN; + (*pCfgR) = cfg; + + pEnR[0] = LCDC_OVR1CHER_UPDATEEN; + } +} + +/** + * Set alpha value + * \param bLayer Layer ID (OVR1, HEO or CUR). + * \param bReverse Reverse alpha (alpha -> 1 - alpha). + * \param bAlpha Global alpha value. + */ +void LCDD_SetAlpha( uint8_t bLayer, + uint8_t bReverse, + uint8_t bAlpha ) +{ + volatile uint32_t *pEnR = pEnableReg(bLayer); + volatile uint32_t *pCfgR = pBlenderReg(bLayer); + uint32_t cfg; + + if (pCfgR) + { + cfg = (*pCfgR) & ~(LCDC_OVR1CFG9_REVALPHA | LCDC_OVR1CFG9_GA_Msk); + if (bReverse) cfg |= LCDC_OVR1CFG9_REVALPHA; + (*pCfgR) = cfg | LCDC_OVR1CFG9_GA(bAlpha); + + pEnR[0] = LCDC_OVR1CHER_UPDATEEN; + } +} + +/** + * Get alpha value + * \param bLayer Layer ID (OVR1, HEO or CUR). + */ +uint8_t LCDD_GetAlpha( uint8_t bLayer ) +{ + Lcdc * pHw = LCDC; + volatile uint32_t *pCfg; + uint32_t bmMask = LCDC_OVR1CFG9_GA_Msk; + uint32_t bShift = LCDC_OVR1CFG9_GA_Pos; + + switch( bLayer ) + { + case LCDD_OVR1: pCfg = (volatile uint32_t *)&pHw->LCDC_OVR1CFG9; break; + case LCDD_OVR2: pCfg = (volatile uint32_t *)&pHw->LCDC_OVR2CFG9; break; + case LCDD_HEO: pCfg = (volatile uint32_t *)&pHw->LCDC_HEOCFG9; break; + case LCDD_CUR: pCfg = (volatile uint32_t *)&pHw->LCDC_HCRCFG9; break; + default: return 0; + } + + return (((*pCfg) >> bShift) & bmMask); +} + +/** + * Enable and Set Color Keying + * \param bLayer Layer ID (OVR1, HEO or CUR). + * \param bDstSrc Destination/Source keying. + * \param dwColor Color to matching. + * \param dwMask Color bit mask. + */ +void LCDD_SetColorKeying( uint8_t bLayer, uint8_t bDstSrc, + uint32_t dwColor, uint32_t dwMask ) +{ + volatile uint32_t *pEnR = pEnableReg(bLayer); + volatile uint32_t *pBCfgR = pBlenderReg(bLayer); + volatile uint32_t *pColorR = pColorReg(bLayer); + if (pBCfgR == NULL) return; + /* Select the Overlay to Blit */ + /* Dest/Source Keying */ + if (bDstSrc) *pBCfgR |= LCDC_HEOCFG12_DSTKEY; + else *pBCfgR &= ~LCDC_HEOCFG12_DSTKEY; + /* Activate Color Keying */ + *pBCfgR |= LCDC_HEOCFG12_CRKEY; + /* Program Color Keying */ + pColorR[1] = dwColor; + pColorR[2] = dwMask; + /* Update */ + pEnR[0] = LCDC_HEOCHER_UPDATEEN; +} + +/** + * Disable Color Keying + * \param bLayer Layer ID (OVR1, HEO or CUR). + */ +void LCDD_DisableColorKeying( uint8_t bLayer ) +{ + volatile uint32_t *pEnR = pEnableReg(bLayer); + volatile uint32_t *pBCfgR = pBlenderReg(bLayer); + volatile uint32_t *pColorR = pColorReg(bLayer); + if (pBCfgR == NULL) return; + *pBCfgR &= ~LCDC_HEOCFG12_CRKEY; + pColorR[2] = 0; + /* Update */ + pEnR[0] = LCDC_HEOCHER_UPDATEEN; +} + +/** + * Set Color Lookup Table + * \param bLayer Layer ID (OVR1, HEO or CUR). + * \param pCLUT Pointer to color lookup table. + * \param bpp Bits Per Pixel (1, 2, 4, 8). + * \param nbColors Number of colors indexed in table. + */ +void LCDD_SetCLUT( uint8_t bLayer, + uint32_t *pCLUT, + uint8_t bpp, uint8_t nbColors ) +{ + //Lcdc *pHw = LCDC; + volatile uint32_t* pCLUTR = pCLUTReg(bLayer); + sCLUTInfo * pInfo = &pLayer(bLayer)->clut; + + if (pInfo == NULL) return; + + pInfo->bpp = bpp; + /* Customize CLUT */ + if (pCLUT) + { + uint32_t i; + if (nbColors == 0) nbColors = 1 << bpp; + pInfo->nbColors = nbColors; + for (i = 0; i < nbColors; i ++) pCLUTR[i] = pCLUT[i]; + } + /* Build CLUT */ + else + { + pInfo->nbColors = 1 << bpp; + switch (bpp) + { + case 1: LCDD_BuildCLUT1(pCLUTR); break; + case 2: LCDD_BuildCLUT2(pCLUTR); break; + case 4: LCDD_BuildCLUT4(pCLUTR); break; + case 8: LCDD_BuildCLUT8(pCLUTR); break; + } + } +} + +/** + * Display an image on specified layer. + * (Image scan origion: Left -> Right, Top -> Bottom.) + * \note w & h should be the rotated result. + * \note for LCDD_BASE: x, y don't care. w always > 0. + * \note for LCDD_HEO:imgW & imgH is used. + * \param bLayer Layer ID (OVR1, HEO or CUR). + * \param pBuffer Pointer to image data. + * \param bPP Bits Per Pixel. + * - 16: TRGB 1555 + * - 24: RGB 888 packed + * - 32: ARGB 8888 + * \param x X position. + * \param y Y position. + * \param w Width (<0 means Right -> Left data). + * \param h Height (<0 means Bottom -> Top data). + * \param imgW Source image width. + * \param imgH Source image height. + * \param wRotate Rotation (clockwise, 0, 90, 180, 270 accepted). + */ +void *LCDD_ShowBMPRotated( uint8_t bLayer, + void* pBuffer, uint8_t bpp, + uint32_t x, uint32_t y, + int32_t w, int32_t h, + uint32_t imgW, uint32_t imgH, + int16_t wRotate) +{ + + //Lcdc *pHw = LCDC; + sLayer *pLD = pLayer(bLayer); + //sCLUTInfo *pClut = &pLD->clut; + sLCDCDescriptor *pTD = &pLD->dmaD; + volatile uint32_t *pEnR = pEnableReg(bLayer); + volatile uint32_t *pDmaR = pHeadReg(bLayer); + volatile uint32_t *pWinR = pWinReg(bLayer); + volatile uint32_t *pStrR = pStrideReg(bLayer); + volatile uint32_t *pSclR = pScaleReg(bLayer); + volatile uint32_t *pBlR = pBlenderReg(bLayer); + volatile uint32_t *pCfgR = pCfgReg(bLayer); + uint8_t bPStride = LCDD_IsPStrideSupported(bLayer); + + uint8_t bBottomUp = (h < 0); + uint8_t bRightLeft = (w < 0); + uint32_t padding = 0; + int32_t srcW, srcH; + uint32_t bitsPRow, bytesPRow; + uint32_t bytesPPix = bpp >> 3; + + void* pOldBuffer = pLD->pBuffer; + + if (pCfgR == NULL) return pOldBuffer; + + //printf("Show %x @ %d: (%d,%d)+(%d,%d) img %d x %d * %d\n\r", pBuffer, bLayer, x, y, w, h, imgW, imgH, bpp); + + switch (bpp) + { + case 16: /* RGB 565 */ + if((pCfgR[1] & LCDC_HEOCFG1_YUVEN)!= LCDC_HEOCFG1_YUVEN) + { + pCfgR[1] = LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565;//LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555; + } + break; + case 24: /* RGB 888 packed */ + pCfgR[1] = LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED; + break; + case 32: /* ARGB 8888 */ + pCfgR[1] = LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888; + break; + default: return pOldBuffer; + } + /* Windows position & size check */ + if (h < 0) h =- h; + if (w < 0) w =- w; + if (x + w > BOARD_LCD_WIDTH) + { + //printf("! w %d -> %d\n\r", w, BOARD_LCD_WIDTH-x); + w = BOARD_LCD_WIDTH - x; + } + if (y + h > BOARD_LCD_HEIGHT) + { + //printf("! h %d -> %d\n\r", h, BOARD_LCD_HEIGHT-y); + h = BOARD_LCD_HEIGHT - y; + } + if (w == 0) w ++; + if (h == 0) h ++; + if (imgW == 0) imgW ++; + if (imgH == 0) imgH ++; + + /* Only 0,(-)90,(-)180,(-)270 accepted */ + switch(wRotate) + { + case 0: case 90: case 180: case 270: + break; + case -90: case -180: case -270: + wRotate += 360; + break; + default: return NULL; + } + + /* Setup display buffer & window */ + if (pBuffer) pLD->pBuffer = pBuffer; + else pBuffer = pLD->pBuffer; + + /* Set display buffer & mode */ + bitsPRow = imgW * bpp; + bytesPRow = bitsPRow >> 3; + if (bitsPRow & 0x7) bytesPRow ++; + if (bytesPRow & 0x3) padding = 4 - (bytesPRow & 0x3); + + /* No X mirror supported layer, no Right->Left scan */ + if (!bPStride) bRightLeft = 0; + + /* --------- Mirror & then rotate --------- */ + /* Normal direction: Left,Top -> Right,Down */ + if ( (!bRightLeft && !bBottomUp && wRotate == 0) + || ( bRightLeft && bBottomUp && wRotate == 180) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* X0 ++ */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(0); + /* Y0 ++ */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(padding); + /* Pointer to Left,Top (x0,y0) */ + } + /* X mirror: Right,Top -> Left,Down */ + else if ( ( bRightLeft && !bBottomUp && wRotate == 0) + ||(!bRightLeft && bBottomUp && wRotate == 180) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* X1 -- */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(0-2*bytesPPix); + /* Y0 ++ */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(bytesPRow*2+padding-2*bytesPPix); + /* Pointer to Right,Top (x1,y0) */ + pBuffer = (void*)((uint32_t)pBuffer + + bytesPPix*(imgW-1)); + } + /* Y mirror: Left,Down -> Right,Top */ + else if ( (!bRightLeft && bBottomUp && wRotate == 0) + ||( bRightLeft && !bBottomUp && wRotate == 180) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* X0 ++ */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(0); + /* Y1 -- */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(0-(bytesPRow*2+padding)); + /* Pointer to Left,Down (x0,y1) */ + pBuffer = (void*)((uint32_t)pBuffer + + (bytesPRow+padding)*(imgH-1)); + } + /* X,Y mirror: Right,Top -> Left,Down */ + else if ( ( bRightLeft && bBottomUp && wRotate == 0) + ||(!bRightLeft && !bBottomUp && wRotate == 180) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* X1 -- */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(0-2*bytesPPix); + /* Y1 -- */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(0-(bytesPPix*2+padding)); + /* Pointer to Left,Down (x1,y1) */ + pBuffer = (void*)((uint32_t)pBuffer + + (bytesPRow+padding)*(imgH-1) + + (bytesPPix)*(imgW-1)); + } + /* Rotate 90: Down,Left -> Top,Right (with w,h swap) */ + else if ( (!bRightLeft && !bBottomUp && wRotate == 90) + ||( bRightLeft && bBottomUp && wRotate == 270) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* Y -- as pixels in row */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(0-(bytesPPix+bytesPRow+padding)); + /* X ++ as rows */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE((bytesPRow+padding)*(imgH-1)); + /* Pointer to Bottom,Left */ + pBuffer = (void*)((uint32_t)pBuffer + + (bytesPRow+padding)*(imgH-1)); + } + /* Rotate 270: Top,Right -> Down,Left (with w,h swap) */ + else if ( (!bRightLeft && !bBottomUp && wRotate == 270) + ||( bRightLeft && bBottomUp && wRotate == 90) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* Y ++ as pixels in row */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(bytesPRow+padding-bytesPPix); + /* X -- as rows */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(0-2*bytesPPix-(bytesPRow+padding)*(imgH-1)); + /* Pointer to top right */ + pBuffer = (void*)((uint32_t)pBuffer + + bytesPPix*(imgW-1)); + } + /* Mirror X then Rotate 90: Down,Right -> Top,Left */ + else if ( ( bRightLeft && !bBottomUp && wRotate == 90) + ||(!bRightLeft && bBottomUp && wRotate == 270) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* Y -- as pixels in row */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(0-(bytesPPix+bytesPRow+padding)); + /* X -- as rows */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(0-2*bytesPPix+(bytesPRow+padding)*(imgH-1)); + /* Pointer to down right (x1,y1) */ + pBuffer = (void*)((uint32_t)pBuffer + + (bytesPRow+padding)*(imgH-1) + + (bytesPPix)*(imgW-1)); + } + /* Mirror Y then Rotate 90: Top,Left -> Down,Right */ + else if ( (!bRightLeft && bBottomUp && wRotate == 90) + ||( bRightLeft && !bBottomUp && wRotate == 270) ) + { + /* No rotation optimization */ + pCfgR[0] |= LCDC_HEOCFG0_ROTDIS; + /* Y ++ as pixels in row */ + if (bPStride) pStrR[1] = LCDC_HEOCFG6_PSTRIDE(bytesPRow+padding-bytesPPix); + /* X ++ as rows */ + pStrR[0] = LCDC_HEOCFG5_XSTRIDE(0-(bytesPRow+padding)*(imgH-1)); + /* Pointer to top left (x0,y0) */ + } + /** DMA is running, just add new descriptor to queue */ + if (pBlR[0] & LCDC_HEOCFG12_DMA) + { + pTD->addr = (uint32_t)pBuffer; + pTD->ctrl = LCDC_HEOCTRL_DFETCH; + pTD->next = (uint32_t)pTD; + pDmaR[0] = (uint32_t)pTD; + pEnR[0] = LCDC_HEOCHER_A2QEN; + } + else + { + /* 2. Write the channel descriptor (DSCR) structure in the system memory by + writing DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control + and DSCR.CHXNEXT next descriptor location. + 3. If more than one descriptor is expected, the DFETCH field of + DSCR.CHXCTRL is set to one to enable the descriptor fetch operation. + 4. Write the DSCR.CHXNEXT register with the address location of the + descriptor structure and set DFETCH field of the DSCR.CHXCTRL register + to one. */ + LCDD_SetDMA(pBuffer, pTD, (uint32_t)pDmaR); + } + CP15_flush_dcache_for_dma ((uint32_t)pTD, ((uint32_t)pTD) + sizeof(pTD)); + /* Set window & position */ + if (pWinR) + { + pWinR[0] = LCDC_HEOCFG2_XPOS(x) | LCDC_HEOCFG2_YPOS(y); + pWinR[1] = LCDC_HEOCFG3_XSIZE(w-1) | LCDC_HEOCFG3_YSIZE(h-1); + } + /* Scaling setup */ + if (pSclR) + { + + /* Image size only used in scaling */ + /* Scaling target */ + if (wRotate == 90 || wRotate == 270) + { + srcW = imgH; srcH = imgW; + } + else + { + srcW = imgW; srcH = imgH; + } + pWinR[2] = LCDC_HEOCFG4_XMEM_SIZE(srcW-1) | LCDC_HEOCFG4_YMEM_SIZE(srcH-1); + /* Scaled */ + if (w != srcW || h != srcH) + { + uint16_t wYf, wXf; + wXf = LCDD_CalcScaleFactor(w, srcW); + wYf = LCDD_CalcScaleFactor(h, srcH); + //printf("- Scale(%d,%d)\n\r", wXf, wYf); + pSclR[0] = LCDC_HEOCFG13_YFACTOR(wYf) + | LCDC_HEOCFG13_XFACTOR(wXf) + | LCDC_HEOCFG13_SCALEN + ; + } + /* Disable scaling */ + else + { + pSclR[0] = 0; + } + } + /* Enable DMA */ + if (pBuffer) + { + pBlR[0] |= LCDC_HEOCFG12_DMA + | LCDC_HEOCFG12_OVR + ; + } + /* Enable & Update */ + /* 5. Enable the relevant channel by writing one to the CHEN field of the + CHXCHER register. */ + pEnR[0] = LCDC_HEOCHER_UPDATEEN | LCDC_HEOCHER_CHEN; + + /* 6. An interrupt may be raised if unmasked when the descriptor has been + loaded. */ + + return pOldBuffer; +} + +/** + * Display an image on specified layer. + * (Image scan: Left -> Right, Top -> Bottom.) + * \param bLayer Layer ID (OVR1, HEO or CUR). + * \param pBuffer Pointer to image data. + * \param bPP Bits Per Pixel. + * - 16: TRGB 1555 + * - 24: RGB 888 packed + * - 32: ARGB 8888 + * \param x X position. + * \param y Y position. + * \param w Width (<0 means Right -> Left data). + * \param h Height (<0 means Bottom -> Top data). + * \param imgW Source image width. + * \param imgH Source image height. + * \return Pointer to old display image data. + */ +void *LCDD_ShowBMPScaled( uint8_t bLayer, + void* pBuffer, uint8_t bpp, + uint32_t x, uint32_t y, + int32_t w, int32_t h, + uint32_t imgW, uint32_t imgH ) +{ + return LCDD_ShowBMPRotated(bLayer, pBuffer, bpp, + x, y, w, h, imgW, imgH, 0); +} + +/** + * Display an image on specified layer. + * (Image scan: Left -> Right, Top -> Bottom.) + * \param bLayer Layer ID (OVR1, HEO or CUR). + * \param pBuffer Pointer to image data. + * \param bPP Bits Per Pixel. + * - 16: TRGB 1555 + * - 24: RGB 888 packed + * - 32: ARGB 8888 + * \param x X position. + * \param y Y position. + * \param w Width + * \param h Height (<0 means Bottom -> Top data). + * \return Pointer to old display image data. + */ +void *LCDD_ShowBMP( uint8_t bLayer, + void* pBuffer, uint8_t bpp, + uint32_t x, uint32_t y, + int32_t w, int32_t h ) +{ + return LCDD_ShowBMPRotated(bLayer, pBuffer, bpp, + x, y, w, h, + w, (h < 0) ? (-h) : h, + 0); +} + +/** + * Start display on base layer + * \param pBuffer Pointer to image data. + * \param bpp Bits Per Pixel. + * \param bBottomUp Scan from bottom to top. + * \return Pointer to old display image data. + */ +void *LCDD_ShowBase( void* pBuffer, uint8_t bpp, uint8_t bBottomUp ) +{ + return LCDD_ShowBMP(LCDD_BASE, pBuffer, bpp, + 0, 0, + BOARD_LCD_WIDTH, + bBottomUp ? -BOARD_LCD_HEIGHT : BOARD_LCD_HEIGHT); +} + +/** + * Stop display on base layer + */ +void LCDD_StopBase( void ) +{ + Lcdc *pHw = LCDC; + + if (!(pHw->LCDC_BASECHSR & LCDC_BASECHSR_CHSR)) + return; + + /* 1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure + will disable the channel at the end of the frame. */ + /* 2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the + channel at the end of the frame. */ + LCDD_ClearDMA(&lcddBase.dmaD, (uint32_t)&pHw->LCDC_BASEADDR); + + /* 3. Writing one to the CHDIS field of the CHXCHDR register will disable + the channel at the end of the frame. */ + pHw->LCDC_BASECHDR = LCDC_BASECHDR_CHDIS; + + /* 4. Writing one to the CHRST field of the CHXCHDR register will disable + the channel immediately. This may occur in the middle of the image. */ + + /* 5. Poll CHSR field in the CHXCHSR register until the channel is + successfully disabled. */ + while (pHw->LCDC_BASECHSR & LCDC_BASECHSR_CHSR); +} + +/** + * Start display on overlay 1 layer + */ +void *LCDD_ShowOvr1( void* pBuffer, uint8_t bpp, + uint32_t x, uint32_t y, int32_t w, int32_t h ) +{ + return LCDD_ShowBMP(LCDD_OVR1, + pBuffer, bpp, x, y, w, h); +} + +/** + * Stop display on overlay 1 layer + */ +void LCDD_StopOvr1( void ) +{ + Lcdc *pHw = LCDC; + + if (!(pHw->LCDC_OVR1CHSR & LCDC_OVR1CHSR_CHSR)) + return; + + /* 1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure + will disable the channel at the end of the frame. */ + /* 2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the + channel at the end of the frame. */ + LCDD_ClearDMA(&lcddOvr1.dmaD, (uint32_t)&pHw->LCDC_OVR1ADDR); + + /* 3. Writing one to the CHDIS field of the CHXCHDR register will disable + the channel at the end of the frame. */ + pHw->LCDC_OVR1CHDR = LCDC_OVR1CHDR_CHDIS; + + /* 4. Writing one to the CHRST field of the CHXCHDR register will disable + the channel immediately. This may occur in the middle of the image. */ + + /* 5. Poll CHSR field in the CHXCHSR register until the channel is + successfully disabled. */ + while (pHw->LCDC_OVR1CHSR & LCDC_OVR1CHSR_CHSR); +} + +/** + * Start display on High End Overlay layer + */ +void * LCDD_ShowHeo( void *pBuffer, uint8_t bpp, + uint32_t x, uint32_t y, int32_t w, int32_t h, + uint32_t imgW, uint32_t imgH ) +{ + return LCDD_ShowBMPRotated(LCDD_HEO, + pBuffer, bpp, + x, y, w, h, + imgW,imgH, + 0); +} + +/** + * Stop display on High End Overlay layer + */ +void LCDD_StopHeo( void ) +{ + Lcdc *pHw = LCDC; + + if (!(pHw->LCDC_HEOCHSR & LCDC_HEOCHSR_CHSR)) + return; + + /* 1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure + will disable the channel at the end of the frame. */ + /* 2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the + channel at the end of the frame. */ + LCDD_ClearDMA(&lcddHeo.dmaD[0], (uint32_t)&pHw->LCDC_HEOADDR); + LCDD_ClearDMA(&lcddHeo.dmaD[1], (uint32_t)&pHw->LCDC_HEOUADDR); + LCDD_ClearDMA(&lcddHeo.dmaD[2], (uint32_t)&pHw->LCDC_HEOVADDR); + + /* 3. Writing one to the CHDIS field of the CHXCHDR register will disable + the channel at the end of the frame. */ + pHw->LCDC_HEOCHDR = LCDC_HEOCHDR_CHDIS; + + /* 4. Writing one to the CHRST field of the CHXCHDR register will disable + the channel immediately. This may occur in the middle of the image. */ + + /* 5. Poll CHSR field in the CHXCHSR register until the channel is + successfully disabled. */ + while (pHw->LCDC_HEOCHSR & LCDC_HEOCHSR_CHSR); +} + +/** + * Start display on Hardware Cursor layer + * (Default transparent color is set to #000000, black) + */ +void *LCDD_ShowHcr( void* pBuffer, uint8_t bpp, + uint32_t x, uint32_t y, int32_t w, int32_t h ) +{ + Lcdc *pHw = LCDC; + + /* Enable default transparent keying */ + if (!(pHw->LCDC_HCRCFG9 & LCDC_HCRCFG9_CRKEY)) + { + pHw->LCDC_HCRCFG7 = 0x000000; + pHw->LCDC_HCRCFG8 = 0xFFFFFF; + pHw->LCDC_HCRCFG9 |= LCDC_HCRCFG9_CRKEY; + } + return LCDD_ShowBMP(LCDD_CUR, + pBuffer, bpp, + x, y, w, h); +} + +/** + * Stop display on Hardware Cursor layer + */ +void LCDD_StopHcr( void ) +{ + Lcdc *pHw = LCDC; + + if (!(pHw->LCDC_HCRCHDR & LCDC_HCRCHSR_CHSR)) + return; + + /* 1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure + will disable the channel at the end of the frame. */ + /* 2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the + channel at the end of the frame. */ + LCDD_ClearDMA(&lcddHcc.dmaD, (uint32_t)&pHw->LCDC_HCRADDR); + + /* 3. Writing one to the CHDIS field of the CHXCHDR register will disable + the channel at the end of the frame. */ + pHw->LCDC_HCRCHDR = LCDC_HCRCHDR_CHDIS; + + /* 4. Writing one to the CHRST field of the CHXCHDR register will disable + the channel immediately. This may occur in the middle of the image. */ + + /* 5. Poll CHSR field in the CHXCHSR register until the channel is + successfully disabled. */ + while (pHw->LCDC_HCRCHSR & LCDC_HCRCHSR_CHSR); +} + + +/** + * \brief Turn on the LCD. + */ +void LCDD_On(void) +{ + Pmc *pPmc = PMC; + Lcdc *pHw = LCDC; + + /* Enable peripheral clock */ + PMC_EnablePeripheral(ID_LCDC); + pPmc->PMC_SCER = (0x1u << 3); + + /* 1. Configure LCD timing parameters, signal polarity and clock period. */ + pHw->LCDC_LCDCFG0 = LCDC_LCDCFG0_CLKDIV((BOARD_MCK*2)/BOARD_LCD_PIXELCLOCK-2) + |LCDC_LCDCFG0_CGDISHCR + |LCDC_LCDCFG0_CGDISHEO + |LCDC_LCDCFG0_CGDISOVR1 + |LCDC_LCDCFG0_CGDISOVR2 + |LCDC_LCDCFG0_CGDISBASE + |LCDC_LCDCFG0_CLKPWMSEL + |LCDC_LCDCFG0_CLKSEL + |LCDC_LCDCFG0_CLKPOL; + + pHw->LCDC_LCDCFG1 = LCDC_LCDCFG1_VSPW(BOARD_LCD_TIMING_VPW-1) + |LCDC_LCDCFG1_HSPW(BOARD_LCD_TIMING_HPW-1); + + pHw->LCDC_LCDCFG2 = LCDC_LCDCFG2_VBPW(BOARD_LCD_TIMING_VBP) + |LCDC_LCDCFG2_VFPW(BOARD_LCD_TIMING_VFP-1); + + pHw->LCDC_LCDCFG3 = LCDC_LCDCFG3_HBPW(BOARD_LCD_TIMING_HBP-1) + |LCDC_LCDCFG3_HFPW(BOARD_LCD_TIMING_HFP-1); + + pHw->LCDC_LCDCFG4 = LCDC_LCDCFG4_RPF(BOARD_LCD_HEIGHT-1) + |LCDC_LCDCFG4_PPL(BOARD_LCD_WIDTH-1); + + pHw->LCDC_LCDCFG5 = LCDC_LCDCFG5_GUARDTIME(30) + |LCDC_LCDCFG5_MODE_OUTPUT_24BPP + |LCDC_LCDCFG5_DISPDLY + |LCDC_LCDCFG5_VSPDLYS + |LCDC_LCDCFG5_VSPOL + |LCDC_LCDCFG5_HSPOL; + + pHw->LCDC_LCDCFG6 = LCDC_LCDCFG6_PWMCVAL(0xF0) + |LCDC_LCDCFG6_PWMPOL + |LCDC_LCDCFG6_PWMPS(6); + + /* 2. Enable the Pixel Clock by writing one to the CLKEN field of the + LCDC_LCDEN register. */ + pHw->LCDC_LCDEN = LCDC_LCDEN_CLKEN; + /* 3. Poll CLKSTS field of the LCDC_LCDSR register to check that the clock + is running. */ + while(!(pHw->LCDC_LCDSR & LCDC_LCDSR_CLKSTS)); + + /* 4. Enable Horizontal and Vertical Synchronization by writing one to the + SYNCEN field of the LCDC_LCDEN register. */ + pHw->LCDC_LCDEN = LCDC_LCDEN_SYNCEN; + /* 5. Poll LCDSTS field of the LCDC_LCDSR register to check that the + synchronization is up. */ + while(!(pHw->LCDC_LCDSR & LCDC_LCDSR_LCDSTS)); + + /* 6. Enable the display power signal writing one to the DISPEN field of the + LCDC_LCDEN register. */ + pHw->LCDC_LCDEN = LCDC_LCDEN_DISPEN; + /* 7. Poll DISPSTS field of the LCDC_LCDSR register to check that the power + signal is activated. */ + while(!(pHw->LCDC_LCDSR & LCDC_LCDSR_DISPSTS)); + /* 8. Enable backlight */ + pHw->LCDC_LCDEN = LCDC_LCDEN_PWMEN; +} + +/** + * \brief Turn off the LCD. + */ +void LCDD_Off(void) +{ + Lcdc *pHw = LCDC; + Pmc *pPmc = PMC; + + /* 1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure + will disable the channel at the end of the frame. */ + + /* 2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the + channel at the end of the frame. */ + + /* Disable all DMA channel descriptors */ + LCDD_ClearDMA(&lcddBase.dmaD, (uint32_t)&pHw->LCDC_BASEADDR); + LCDD_ClearDMA(&lcddOvr1.dmaD, (uint32_t)&pHw->LCDC_OVR1ADDR); + LCDD_ClearDMA(&lcddOvr2.dmaD, (uint32_t)&pHw->LCDC_OVR2ADDR); + LCDD_ClearDMA(&lcddHeo.dmaD[0], (uint32_t)&pHw->LCDC_HEOADDR); + LCDD_ClearDMA(&lcddHeo.dmaD[1], (uint32_t)&pHw->LCDC_HEOUADDR); + LCDD_ClearDMA(&lcddHeo.dmaD[2], (uint32_t)&pHw->LCDC_HEOVADDR); + LCDD_ClearDMA(&lcddHcc.dmaD, (uint32_t)&pHw->LCDC_HCRADDR); + + /* 3. Writing one to the CHDIS field of the CHXCHDR register will disable + the channel at the end of the frame. */ + + /* Disable DMA channels */ + pHw->LCDC_BASECHDR = LCDC_BASECHDR_CHDIS; + pHw->LCDC_OVR1CHDR = LCDC_OVR1CHDR_CHDIS; + pHw->LCDC_HEOCHDR = LCDC_HEOCHDR_CHDIS; + pHw->LCDC_HCRCHDR = LCDC_HCRCHDR_CHDIS; + pHw->LCDC_BASECFG4 = 0; + + /* 4. Writing one to the CHRST field of the CHXCHDR register will disable + the channel immediately. This may occur in the middle of the image. */ + + /* 5. Poll CHSR field in the CHXCHSR register until the channel is + successfully disabled. */ + while (pHw->LCDC_BASECHSR & LCDC_BASECHSR_CHSR); + while (pHw->LCDC_OVR1CHSR & LCDC_OVR1CHSR_CHSR); + while (pHw->LCDC_HEOCHSR & LCDC_HEOCHSR_CHSR); + while (pHw->LCDC_HCRCHDR & LCDC_HCRCHSR_CHSR); + + + /* Timing Engine Power Down Software Operation */ + + /* Disable backlight */ + pHw->LCDC_LCDDIS = LCDC_LCDDIS_PWMDIS; + while (pHw->LCDC_LCDSR & LCDC_LCDSR_PWMSTS); + + /* 1. Disable the DISP signal writing DISPDIS field of the LCDC_LCDDIS + register. */ + pHw->LCDC_LCDDIS = LCDC_LCDDIS_DISPDIS; + /* 2. Poll DISPSTS field of the LCDC_LCDSR register to verify that the DISP + is no longer activated. */ + while (pHw->LCDC_LCDSR & LCDC_LCDSR_DISPSTS); + + /* 3. Disable the hsync and vsync signals by writing one to SYNCDIS field of + the LCDC_LCDDIS register. */ + pHw->LCDC_LCDDIS = LCDC_LCDDIS_SYNCDIS; + /* 4. Poll LCDSTS field of the LCDC_LCDSR register to check that the + synchronization is off. */ + while (pHw->LCDC_LCDSR & LCDC_LCDSR_LCDSTS); + + /* 5. Disable the Pixel clock by writing one in the CLKDIS field of the + LCDC_LCDDIS register. */ + pHw->LCDC_LCDDIS = LCDC_LCDDIS_CLKDIS; + /* 6. Poll CLKSTS field of the LCDC_LCDSR register to check that Pixel Clock + is disabled. */ + while(pHw->LCDC_LCDSR & LCDC_LCDSR_CLKSTS); + + /* Disable peripheral clock */ + PMC_DisablePeripheral(ID_LCDC); + /* LCD Clock Disable */ + pPmc->PMC_SCDR = (0x1u << 3); + +} + +/** + * \brief Set the backlight of the LCD. + * + * \param level Backlight brightness level [1..255], + * 255 means maximum brightness. + */ +void LCDD_SetBacklight (uint32_t level) +{ + Lcdc *pHw = LCDC; + uint32_t cfg = pHw->LCDC_LCDCFG6 & ~LCDC_LCDCFG6_PWMCVAL_Msk; + + pHw->LCDC_LCDCFG6 = cfg | LCDC_LCDCFG6_PWMCVAL(level); +} + +/** + * Get canvas layer for LCDD_Draw* + * \return Layer information pointer. + */ +sLCDDLayer *LCDD_GetCanvas(void) +{ + return &lcddCanvas; +} + +/** + * Flush the current canvas layer* + */ +void LCDD_Flush_CurrentCanvas(void) +{ + sLCDDLayer *pCurrentLayer; + uint32_t base, height, width; + pCurrentLayer = LCDD_GetCanvas(); + base = (uint32_t)pCurrentLayer->pBuffer; + height = pCurrentLayer->wImgH; + width = pCurrentLayer->wImgW; + CP15_flush_dcache_for_dma ((uint32_t)base, ((uint32_t)base) + height*width*4); +} + +/** + * Select an LCD layer as canvas layer. + * Then all drawing operations will apply to current display buffer + * of selected layer. + * \note If there is no display buffer for the layer (not running) + * selection fails. + */ +uint8_t LCDD_SelectCanvas(uint8_t bLayer) +{ + sLayer *pLD = pLayer(bLayer); + volatile uint32_t *pXyR = pWinReg(bLayer); + volatile uint32_t *pCfR = pCfgReg(bLayer); + + if (pLD == NULL) return 0; + + lcddCanvas.pBuffer = (void*)pLD->pBuffer; + if (pXyR) + { + lcddCanvas.wImgW = (pXyR[1] & LCDC_HEOCFG3_XSIZE_Msk) >> LCDC_HEOCFG3_XSIZE_Pos; + lcddCanvas.wImgH = (pXyR[1] & LCDC_HEOCFG3_YSIZE_Msk) >> LCDC_HEOCFG3_YSIZE_Pos; + } + else + { + lcddCanvas.wImgW = BOARD_LCD_WIDTH; + lcddCanvas.wImgH = BOARD_LCD_HEIGHT; + } + lcddCanvas.bMode = LCDD_GetBitsPerPixel(pCfR[1] & LCDC_HEOCFG1_RGBMODE_Msk); + lcddCanvas.bLayer = bLayer; + + return 1; +} + +/** + * Create a blank canvas on a display layer for further operations. + * \param bLayer Layer ID. + * \param pBuffer Pointer to canvas display buffer. + * \param bBPP Bits Per Pixel. + * \param wX Canvas X coordinate on base. + * \param wY Canvas Y coordinate on base. + * \param wW Canvas width. + * \param wH Canvas height. + * \note The content in buffer is destroied. + */ +void *LCDD_CreateCanvas(uint8_t bLayer, + void* pBuffer, uint8_t bBPP, + uint16_t wX, uint16_t wY, + uint16_t wW, uint16_t wH ) +{ + void* pOldBuffer; + uint32_t maxW = BOARD_LCD_WIDTH; + uint32_t maxH = BOARD_LCD_HEIGHT; + + uint32_t bitsPR, bytesPR; + + switch (bLayer) + { + case LCDD_BASE: + wX = 0; wY = 0; + break; + case LCDD_OVR1:case LCDD_OVR2: case LCDD_HEO: + /* Size check */ + if (wX + wW > BOARD_LCD_WIDTH || wY + wH > BOARD_LCD_HEIGHT) + return NULL; + break; + case LCDD_CUR: + /* Size check */ + if (wX + wW > BOARD_LCD_WIDTH || wY + wH > BOARD_LCD_HEIGHT + || wW > 128 || wH > 128) + return NULL; + maxW = maxH = 128; + break; + } + if (wW == 0) wW = maxW - wX; + if (wH == 0) wH = maxH - wY; + + bitsPR = wW * bBPP; + bytesPR = (bitsPR&0x7) ? (bitsPR/8 + 1) : (bitsPR/8); + memset(pBuffer, 0xFF, bytesPR*wH); + pOldBuffer = LCDD_ShowBMPRotated(bLayer, pBuffer, bBPP, + wX, wY, wW, wH, wW, wH, + 0); + + lcddCanvas.bLayer = bLayer; + lcddCanvas.bMode = bBPP; + lcddCanvas.pBuffer = pBuffer; + lcddCanvas.wImgW = wW; + lcddCanvas.wImgH = wH; + + return pOldBuffer; +} + +/**@}*/ +#endif /* ifdef LCDC */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/led.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/led.c new file mode 100644 index 000000000..3e27a969c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/led.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Local Variables + *------------------------------------------------------------------------------*/ + +#ifdef PINS_LEDS +static const Pin pinsLeds[] = { PINS_LEDS } ; +static const uint32_t numLeds = PIO_LISTSIZE( pinsLeds ) ; +#endif + +/*------------------------------------------------------------------------------ + * Global Functions + *------------------------------------------------------------------------------*/ + +/** + * Configures the pin associated with the given LED number. If the LED does + * not exist on the board, the function does nothing. + * \param led Number of the LED to configure. + * \return 1 if the LED exists and has been configured; otherwise 0. + */ +extern uint32_t LED_Configure( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + // Check that LED exists + if ( dwLed >= numLeds) + { + + return 0; + } + + // Configure LED + return ( PIO_Configure( &pinsLeds[dwLed], 1 ) ) ; +#else + return 0 ; +#endif +} + +/** + * Turns the given LED on if it exists; otherwise does nothing. + * \param led Number of the LED to turn on. + * \return 1 if the LED has been turned on; 0 otherwise. + */ +extern uint32_t LED_Set( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + /* Check if LED exists */ + if ( dwLed >= numLeds ) + { + return 0 ; + } + + /* Turn LED on */ + if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 ) + { + + PIO_Set( &pinsLeds[dwLed] ) ; + } + else + { + PIO_Clear( &pinsLeds[dwLed] ) ; + } + + return 1 ; +#else + return 0 ; +#endif +} + +/** + * Turns a LED off. + * + * \param led Number of the LED to turn off. + * \return 1 if the LED has been turned off; 0 otherwise. + */ +extern uint32_t LED_Clear( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + /* Check if LED exists */ + if ( dwLed >= numLeds ) + { + return 0 ; + } + + /* Turn LED off */ + if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 ) + { + PIO_Clear( &pinsLeds[dwLed] ) ; + } + else + { + PIO_Set( &pinsLeds[dwLed] ) ; + } + + return 1 ; +#else + return 0 ; +#endif +} + +/** + * Toggles the current state of a LED. + * + * \param led Number of the LED to toggle. + * \return 1 if the LED has been toggled; otherwise 0. + */ +extern uint32_t LED_Toggle( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + /* Check if LED exists */ + if ( dwLed >= numLeds ) + { + return 0 ; + } + + /* Toggle LED */ + if ( PIO_GetOutputDataStatus( &pinsLeds[dwLed] ) ) + { + PIO_Clear( &pinsLeds[dwLed] ) ; + } + else + { + PIO_Set( &pinsLeds[dwLed] ) ; + } + + return 1 ; +#else + return 0 ; +#endif +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/macb.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/macb.c new file mode 100644 index 000000000..8ef6d7208 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/macb.c @@ -0,0 +1,648 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** Default max retry count */ +#define MACB_RETRY_MAX 1000000 + +/*--------------------------------------------------------------------------- + * Local functions + *---------------------------------------------------------------------------*/ + +/** + * Wait PHY operation complete. + * Return 1 if the operation completed successfully. + * May be need to re-implemented to reduce CPU load. + * \param retry: the retry times, 0 to wait forever until complete. + */ +static uint8_t EMAC_WaitPhy( Emac *pHw, uint32_t retry ) +{ + volatile uint32_t retry_count = 0; + + while (!EMAC_IsIdle(pHw)) + { + if(retry == 0) continue; + retry_count ++; + if (retry_count >= retry) + { + return 0; + } + } + return 1; +} + +/** + * Read PHY register. + * Return 1 if successfully, 0 if timeout. + * \param pHw HW controller address + * \param PhyAddress PHY Address + * \param Address Register Address + * \param pValue Pointer to a 32 bit location to store read data + * \param retry The retry times, 0 to wait forever until complete. + */ +static uint8_t EMAC_ReadPhy(Emac *pHw, + uint8_t PhyAddress, + uint8_t Address, + uint32_t *pValue, + uint32_t retry) +{ + EMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0); + if ( EMAC_WaitPhy(pHw, retry) == 0 ) + { + TRACE_ERROR("TimeOut EMAC_ReadPhy\n\r"); + return 0; + } + *pValue = EMAC_PHYData(pHw); + return 1; +} + +/** + * Write PHY register + * Return 1 if successfully, 0 if timeout. + * \param pHw HW controller address + * \param PhyAddress PHY Address + * \param Address Register Address + * \param Value Data to write ( Actually 16 bit data ) + * \param retry The retry times, 0 to wait forever until complete. + */ +static uint8_t EMAC_WritePhy(Emac *pHw, + uint8_t PhyAddress, + uint8_t Address, + uint32_t Value, + uint32_t retry) +{ + EMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value); + if ( EMAC_WaitPhy(pHw, retry) == 0 ) + { + TRACE_ERROR("TimeOut EMAC_WritePhy\n\r"); + return 0; + } + return 1; +} + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * Find a valid PHY Address ( from addrStart to 31 ). + * Check BMSR register ( not 0 nor 0xFFFF ) + * Return 0xFF when no valid PHY Address found. + * \param pMacb Pointer to the MACB instance + */ +uint8_t MACB_FindValidPhy(Macb *pMacb, uint8_t addrStart) +{ + sEmacd *pDrv = pMacb->pEmacd; + Emac *pHw = pDrv->pHw; + + uint32_t retryMax; + uint32_t value=0; + uint8_t rc; + uint8_t phyAddress; + uint8_t cnt; + + TRACE_DEBUG("MACB_FindValidPhy\n\r"); + + EMAC_ManagementEnable(pHw, 1); + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + /* Check current phyAddress */ + rc = phyAddress; + if( EMAC_ReadPhy(pHw, phyAddress, MII_PHYID1, &value, retryMax) == 0 ) + { + TRACE_ERROR("MACB PROBLEM\n\r"); + } + TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress); + + /* Find another one */ + if (value != MII_OUI_MSB) + { + rc = 0xFF; + for(cnt = 0; cnt < 32; cnt ++) + { + phyAddress = (phyAddress + 1) & 0x1F; + if( EMAC_ReadPhy(pHw, phyAddress, MII_PHYID1, &value, retryMax) == 0 ) + { + TRACE_ERROR("MACB PROBLEM\n\r"); + } + TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress); + if (value == MII_OUI_MSB) + { + rc = phyAddress; + break; + } + } + } + + EMAC_ManagementEnable(pHw, 0); + + if (rc != 0xFF) + { + + printf("** Valid PHY Found: %d\n\r", rc); + EMAC_ReadPhy(pHw, phyAddress, MII_DSCSR, &value, retryMax); + TRACE_DEBUG("_DSCSR : 0x%X, addr: %d\n\r", value, phyAddress); + + } + return rc; +} + +/** + * Dump all the useful registers + * \param pMacb Pointer to the MACB instance + */ +void MACB_DumpRegisters(Macb *pMacb) +{ + sEmacd *pDrv = pMacb->pEmacd; + Emac *pHw = pDrv->pHw; + + uint8_t phyAddress; + uint32_t retryMax; + uint32_t value; + + TRACE_INFO("MACB_DumpRegisters\n\r"); + + EMAC_ManagementEnable(pHw, 1); + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + TRACE_INFO("%cMII MACB (@%d) Registers:\n\r", + pMacb->RMII ? 'R' : ' ', + phyAddress); + + EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &value, retryMax); + TRACE_INFO(" _BMCR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_BMSR, &value, retryMax); + TRACE_INFO(" _BMSR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_ANAR, &value, retryMax); + TRACE_INFO(" _ANAR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_ANLPAR, &value, retryMax); + TRACE_INFO(" _ANLPAR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_ANER, &value, retryMax); + TRACE_INFO(" _ANER : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_DSCR, &value, retryMax); + TRACE_INFO(" _DSCR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_DSCSR, &value, retryMax); + TRACE_INFO(" _DSCSR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_10BTCSR, &value, retryMax); + TRACE_INFO(" _10BTCSR: 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_PWDOR, &value, retryMax); + TRACE_INFO(" _PWDOR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_CONFIGR, &value, retryMax); + TRACE_INFO(" _CONFIGR: 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_MDINTR, &value, retryMax); + TRACE_INFO(" _MDINTR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_RECR, &value, retryMax); + TRACE_INFO(" _RECR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_DISCR, &value, retryMax); + TRACE_INFO(" _DISCR : 0x%X\n\r", value); + EMAC_ReadPhy(pHw, phyAddress, MII_RLSR, &value, retryMax); + TRACE_INFO(" _RLSR : 0x%X\n\r", value); + + EMAC_ManagementEnable(pHw, 0); +} + +/** + * Setup the maximum timeout count of the driver. + * \param pMacb Pointer to the MACB instance + * \param toMax Timeout maxmum count. + */ +void MACB_SetupTimeout(Macb *pMacb, uint32_t toMax) +{ + pMacb->retryMax = toMax; +} + +/** + * Initialize the MACB instance + * \param pMacb Pointer to the MACB instance + * \param pEmac Pointer to the Emac instance for the MACB + * \param phyAddress The PHY address used to access the PHY + * ( pre-defined by pin status on PHY reset ) + */ +void MACB_Init(Macb *pMacb, sEmacd *pEmacd, uint8_t phyAddress) +{ + pMacb->pEmacd = pEmacd; + pMacb->phyAddress = phyAddress; + /* Initialize timeout by default */ + pMacb->retryMax = MACB_RETRY_MAX; +} + +/** + * Issue a SW reset to reset all registers of the PHY + * Return 1 if successfully, 0 if timeout. + * \param pMacb Pointer to the MACB instance + */ +uint8_t MACB_ResetPhy(Macb *pMacb) +{ + sEmacd *pDrv = pMacb->pEmacd; + Emac *pHw = pDrv->pHw; + + uint32_t retryMax; + uint32_t bmcr = MII_RESET; + uint8_t phyAddress; + uint32_t timeout = 10; + uint8_t ret = 1; + + TRACE_INFO(" MACB_ResetPhy\n\r"); + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + EMAC_ManagementEnable(pHw, 1); + + bmcr = MII_RESET; + EMAC_WritePhy(pHw, phyAddress, MII_BMCR, bmcr, retryMax); + + do + { + EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &bmcr, retryMax); + timeout--; + } while ((bmcr & MII_RESET) && timeout); + + EMAC_ManagementEnable(pHw, 0); + + if (!timeout) + { + ret = 0; + } + + return( ret ); +} + +/** + * Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII) + * The RXDV pin is used to select test mode on reset (pulled up for test mode) + * The above pins should be predefined for corresponding settings in resetPins + * The EMAC peripheral pins are configured after the reset done. + * Return 1 if RESET OK, 0 if timeout. + * \param pMacb Pointer to the MACB instance + * \param mck Main clock setting to initialize clock + * \param resetPins Pointer to list of PIOs to configure before HW RESET + * (for PHY power on reset configuration latch) + * \param nbResetPins Number of PIO items that should be configured + * \param emacPins Pointer to list of PIOs for the EMAC interface + * \param nbEmacPins Number of PIO items that should be configured + */ + +uint8_t MACB_InitPhy(Macb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pEmacPins, + uint32_t nbEmacPins) +{ + sEmacd *pDrv = pMacb->pEmacd; + Emac *pHw = pDrv->pHw; + + uint8_t rc = 1; + uint8_t phy; + + /* Perform RESET */ + TRACE_DEBUG("RESET PHY\n\r"); + + if (pResetPins) + { + /* Configure PINS */ + PIO_Configure(pResetPins, nbResetPins); + /* Execute reset */ + RSTC_SetExtResetLength(MACB_RESET_LENGTH); + RSTC_ExtReset(); + /* Get NRST level */ + /* Wait for end hardware reset */ + while (!RSTC_GetNrstLevel()); + } + /* Configure EMAC runtime pins */ + if (rc) + { + PIO_Configure(pEmacPins, nbEmacPins); + rc = EMAC_SetClock( pHw, mck ); + if (!rc) + { + TRACE_ERROR("No Valid MDC clock\n\r"); + return 0; + } + + /* Check PHY Address */ + phy = MACB_FindValidPhy(pMacb, 0); + if (phy == 0xFF) + { + TRACE_ERROR("PHY Access fail\n\r"); + return 0; + } + if(phy != pMacb->phyAddress) + { + pMacb->phyAddress = phy; + MACB_ResetPhy(pMacb); + } + + } + else + { + TRACE_ERROR("PHY Reset Timeout\n\r"); + } + + return rc; +} + +/** + * Issue a Auto Negotiation of the PHY + * Return 1 if successfully, 0 if timeout. + * \param pMacb Pointer to the MACB instance + */ +uint8_t MACB_AutoNegotiate(Macb *pMacb, uint8_t rmiiMode) +{ + sEmacd *pDrv = pMacb->pEmacd; + Emac *pHw = pDrv->pHw; + + uint32_t retryMax; + uint32_t value; + uint32_t phyAnar; + uint32_t phyAnalpar; + uint32_t retryCount= 0; + uint8_t phyAddress; + uint8_t bFD = 0; + uint8_t bSP = 0; + uint8_t rc = 1; + + pMacb->RMII = rmiiMode; + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + EMAC_ManagementEnable(pHw, 1); + + if (!EMAC_ReadPhy(pHw, phyAddress, MII_PHYID1, &value, retryMax)) + { + TRACE_ERROR("Pb EMAC_ReadPhy Id1\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress); + if (!EMAC_ReadPhy(pHw, phyAddress, MII_PHYID2, &phyAnar, retryMax)) + { + TRACE_ERROR("Pb EMAC_ReadPhy Id2\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar); + + if( ( value == MII_OUI_MSB ) + && ( ((phyAnar>>10)&MII_LSB_MASK) == MII_OUI_LSB ) ) + { + TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F)); + TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0x7)); + } + else + { + TRACE_ERROR("Problem OUI value\n\r"); + } + + /* Setup control register */ + rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + value &= ~MII_AUTONEG; /* Remove autonegotiation enable */ + value &= ~(MII_LOOPBACK|MII_POWER_DOWN); + value |= MII_ISOLATE; /* Electrically isolate PHY */ + rc = EMAC_WritePhy(pHw, phyAddress, MII_BMCR, value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Set the Auto_negotiation Advertisement Register + MII advertising for Next page + 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + phyAnar = MII_TX_FDX | MII_TX_HDX | + MII_10_FDX | MII_10_HDX | MII_AN_IEEE_802_3; + rc = EMAC_WritePhy(pHw, phyAddress, MII_ANAR, phyAnar, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Read & modify control register */ + rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMCR, &value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + value |= MII_SPEED_SELECT | MII_AUTONEG | MII_DUPLEX_MODE; + rc = EMAC_WritePhy(pHw, phyAddress, MII_BMCR, value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Restart Auto_negotiation */ + value |= MII_RESTART_AUTONEG; + value &= ~MII_ISOLATE; + rc = EMAC_WritePhy(pHw, phyAddress, MII_BMCR, value, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + TRACE_DEBUG(" _BMCR: 0x%X\n\r", value); + + /* Check AutoNegotiate complete */ + while (1) + { + rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMSR, &value, retryMax); + if (rc == 0) + { + TRACE_ERROR("_BMSR Rd err\n\r"); + goto AutoNegotiateExit; + } + /* Done successfully */ + if (value & MII_AUTONEG_COMP) + { + printf("AutoNegotiate complete\n\r"); + break; + } + + /* Timeout check */ + if (retryMax) + { + if (++ retryCount >= retryMax) + { + MACB_DumpRegisters(pMacb); + TRACE_ERROR("TimeOut\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + } + } + + /* Get the AutoNeg Link partner base page */ + rc = EMAC_ReadPhy(pHw, phyAddress, MII_ANLPAR, &phyAnalpar, retryMax); + if (rc == 0) + { + goto AutoNegotiateExit; + } + + /* Setup the EMAC link speed */ + if ((phyAnar & phyAnalpar) & MII_TX_FDX) + { + /* set MII for 100BaseTX and Full Duplex */ + bSP = 1; bFD = 1; + } + else if ((phyAnar & phyAnalpar) & MII_10_FDX) + { + /* set MII for 10BaseT and Full Duplex */ + bSP = 0; bFD = 1; + } + else if ((phyAnar & phyAnalpar) & MII_TX_HDX) + { + // set MII for 100BaseTX and half Duplex + bSP = 1; bFD = 0; + } + else if ((phyAnar & phyAnalpar) & MII_10_HDX) + { + // set MII for 10BaseT and half Duplex + bSP = 0; bFD = 0; + } + EMAC_SetSpeed(pHw, bSP); + EMAC_FullDuplexEnable(pHw, bFD); + + EMAC_RMIIEnable(pHw, rmiiMode); + EMAC_TransceiverClockEnable(pHw, 1); + +AutoNegotiateExit: + EMAC_ManagementEnable(pHw, 0); + return rc; +} + +/** + * Get the Link & speed settings, and automatically setup the EMAC with the + * settings. + * Return 1 if link found, 0 if no ethernet link. + * \param pMacb Pointer to the MACB instance + * \param applySetting Apply the settings to EMAC interface + */ +uint8_t MACB_GetLinkSpeed(Macb *pMacb, uint8_t applySetting) +{ + sEmacd *pDrv = pMacb->pEmacd; + Emac *pHw = pDrv->pHw; + + uint32_t retryMax; + uint32_t stat1; + uint32_t stat2; + uint8_t phyAddress, bSP, bFD; + uint8_t rc = 1; + + TRACE_DEBUG("MACB_GetLinkSpeed\n\r"); + bSP = 0; bFD = 0; + EMAC_ManagementEnable(pHw, 1); + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + rc = EMAC_ReadPhy(pHw, phyAddress, MII_BMSR, &stat1, retryMax); + if (rc == 0) + { + goto GetLinkSpeedExit; + } + + if ((stat1 & MII_LINK_STATUS) == 0) + { + TRACE_ERROR("Pb: LinkStat: 0x%x\n\r", (unsigned int)stat1); + rc = 0; + goto GetLinkSpeedExit; + } + + if (applySetting == 0) + { + TRACE_WARNING("Speed #%d not applied\n\r", applySetting); + bSP = 0; bFD = 0; + goto GetLinkSpeedExit; + } + + /* Re-configure Link speed */ + rc = EMAC_ReadPhy(pHw, phyAddress, MII_DSCSR, &stat2, retryMax); + if (rc == 0) + { + TRACE_ERROR("Pb _DSCSR: rc 0x%x\n\r", rc); + goto GetLinkSpeedExit; + } + + if ((stat1 & MII_100BASE_TX_FD) && (stat2 & MII_100FDX)) + { + /* set Emac for 100BaseTX and Full Duplex */ + bSP = 1; bFD = 1; + } + + if ((stat1 & MII_10BASE_T_FD) && (stat2 & MII_10FDX)) + { + /* set MII for 10BaseT and Full Duplex */ + bSP= 0; bFD = 1; + } + + if ((stat1 & MII_100BASE_T4_HD) && (stat2 & MII_100HDX)) + { + /* set MII for 100BaseTX and Half Duplex */ + bSP = 1; bFD = 0; + } + + if ((stat1 & MII_10BASE_T_HD) && (stat2 & MII_10HDX)) + { + /* set MII for 10BaseT and Half Duplex */ + bSP = 0; bFD = 0; + } + EMAC_SetSpeed(pHw, bSP); + EMAC_FullDuplexEnable(pHw, bFD); + + /* Start the EMAC transfers */ + TRACE_DEBUG("MACB_GetLinkSpeed passed\n\r"); + +GetLinkSpeedExit: + EMAC_ManagementEnable(pHw, 0); + return rc; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/math.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/math.c new file mode 100644 index 000000000..9713cc774 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/math.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +/** + * Returns the minimum value between two integers. + * + * \param a First integer to compare. + * \param b Second integer to compare. + */ +extern uint32_t min( uint32_t dwA, uint32_t dwB ) +{ + if ( dwA < dwB ) + { + return dwA ; + } + else + { + return dwB ; + } +} + +/*------------------------------------------------------------------------------ + * Returns the absolute value of an integer. + * + * \param value Integer value. + * + * \note Do not call this function "abs", problem with gcc ! + */ +extern uint32_t absv( int32_t lValue ) +{ + if ( lValue < 0 ) + { + return -lValue ; + } + else + { + return lValue ; + } +} + +/*------------------------------------------------------------------------------ + * Computes and returns x power of y. + * + * \param x Value. + * \param y Power. + */ +extern uint32_t power( uint32_t dwX, uint32_t dwY ) +{ + uint32_t dwResult = 1 ; + + while ( dwY > 0 ) + { + dwResult *= dwX ; + dwY-- ; + } + + return dwResult ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/mcid_dma.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/mcid_dma.c new file mode 100644 index 000000000..ff971a814 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/mcid_dma.c @@ -0,0 +1,1027 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * + * Implement for SD/MMC low level commands. + * + * \sa \ref hsmci_module, \ref sdmmc_module + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include "libsdmmc.h" + +#include + +/*---------------------------------------------------------------------------- + * Local constants + *----------------------------------------------------------------------------*/ +/** \addtorgoup mcid_defines + * @{*/ + +/** Enable MCI */ +#define MCI_ENABLE(pMciHw) HSMCI_Enable(pMciHw) +/** Disable MCI */ +#define MCI_DISABLE(pMciHw) HSMCI_Disable(pMciHw) +/** Reset MCI */ +#define MCI_RESET(pMciHw) HSMCI_Reset(pMciHw, 0) + +/** Return halfword(16-bit) count from byte count */ +#define toHWCOUNT(byteCnt) (((byteCnt)&0x1) ? (((byteCnt)/2)+1) : ((byteCnt)/2)) +/** Return word(32-bit) count from byte count */ +#define toWCOUNT(byteCnt) (((byteCnt)&0x3) ? (((byteCnt)/4)+1) : ((byteCnt)/4)) + + +/** Bit mask for status register errors. */ +#define STATUS_ERRORS ((uint32_t)(HSMCI_SR_UNRE \ + | HSMCI_SR_OVRE \ + | HSMCI_SR_ACKRCVE \ + | HSMCI_SR_CSTOE \ + | HSMCI_SR_DTOE \ + | HSMCI_SR_DCRCE \ + | HSMCI_SR_RTOE \ + | HSMCI_SR_RENDE \ + | HSMCI_SR_RCRCE \ + | HSMCI_SR_RDIRE \ + | HSMCI_SR_RINDE)) + +/** Bit mask for response errors */ +#define STATUS_ERRORS_RESP ((uint32_t)(HSMCI_SR_CSTOE \ + | HSMCI_SR_RTOE \ + | HSMCI_SR_RENDE \ + | HSMCI_SR_RCRCE \ + | HSMCI_SR_RDIRE \ + | HSMCI_SR_RINDE)) + +/** Bit mask for data errors */ +#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \ + | HSMCI_SR_OVRE \ + | HSMCI_SR_DTOE \ + | HSMCI_SR_DCRCE)) + +/** Max DMA size in a single transfer */ +#define MAX_DMA_SIZE (DMAC_MAX_BT_SIZE & 0xFFFFFF00) + +/** SD/MMC memory Single block */ +#define _CMDR_SDMEM_SINGLE \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_SINGLE) +/** SD/MMC memory Multi block */ +#define _CMDR_SDMEM_MULTI \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_MULTIPLE) +/** SDIO byte transfer */ +#define _CMDR_SDIO_BYTE \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BYTE) +/** SDIO block transfer */ +#define _CMDR_SDIO_BLOCK \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BLOCK) + +/** @}*/ +/*--------------------------------------------------------------------------- + * Local types + *---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Local variable + *----------------------------------------------------------------------------*/ + +//#define MCID_DBG 0 +//static uint8_t bMcidDBG = 0; + +/** HAL for SD/MMC bus mode (MCI interface) */ +static sSdHalFunctions sdHal = { + (fSdmmcLock)MCID_Lock, + (fSdmmcRelease)MCID_Release, + (fSdmmcSendCommand)MCID_SendCmd, + (fSdmmcIOCtrl)MCID_IOCtrl +}; + +/*--------------------------------------------------------------------------- + * Internal functions + *---------------------------------------------------------------------------*/ + +/** \addtogroup mcid_functions + *@{ + */ + +/** + * Enable MCI peripheral access clock + */ +static uint8_t _PeripheralEnable(uint32_t id) +{ + if (PMC_IsPeriphEnabled(id)) return 0; + PMC_EnablePeripheral(id); + return 1; +} + + +/** + * \brief Start DMA transfer for HSMCI. + * Replace DMAD driver start function since there is DMADONE handler in HSMCI. + * \param pDmad Pointer to DMA driver instance. + * \param dwCh ControllerNumber << 8 | ChannelNumber. + */ +static void _MciDMAStart( sDmad *pDmad, uint32_t dwCh) +{ + uint8_t iController = (dwCh >> 8); + uint8_t iChannel = (dwCh) & 0xFF; + Dmac *pDmac = pDmad->pDmacs[iController]; + + DMAC_EnableChannel(pDmac, iChannel); + if ( pDmad->pollingMode == 0 ) + { + /* Monitor error status in interrupt handler */ + //DMAC_EnableIt(pDmac, (DMAC_EBCIDR_ERR0 << iChannel)|(DMAC_EBCIDR_CBTC0 << iChannel) ); + } +} + +/** + * HSMCI DMA R/W prepare + */ +static uint32_t _MciDMAPrepare(sMcid *pMcid, uint8_t bRd) +{ + sDmad *pDmad = pMcid->pDmad; + uint8_t iController, iChNb; + + /* Allocate a channel */ + pMcid->dwDmaCh = DMAD_AllocateChannel(pDmad, pMcid->bID, DMAD_TRANSFER_MEMORY); + if (pMcid->dwDmaCh == DMAD_ALLOC_FAILED) + { + return SDMMC_ERROR_BUSY; + } + DMAD_SetCallback(pDmad, pMcid->dwDmaCh, + (DmadTransferCallback)NULL, + NULL); + iController = pMcid->dwDmaCh >> 8; + if (bRd) + { + iChNb = DMAIF_Get_ChannelNumber(iController, pMcid->bID, DMAD_TRANSFER_RX); + DMAD_PrepareChannel( pDmad, pMcid->dwDmaCh, DMAC_CFG_SRC_PER(iChNb) + |DMAC_CFG_SRC_H2SEL + |DMAC_CFG_SOD + |DMAC_CFG_FIFOCFG_ALAP_CFG ); + } + else + { + iChNb = DMAIF_Get_ChannelNumber(iController, pMcid->bID, DMAD_TRANSFER_TX); + DMAD_PrepareChannel( pDmad, pMcid->dwDmaCh, DMAC_CFG_DST_PER(iChNb) + |DMAC_CFG_DST_H2SEL + |DMAC_CFG_SOD + |DMAC_CFG_FIFOCFG_ALAP_CFG ); + } + return SDMMC_SUCCESS; +} + +/** + * HSMCI DMA R/W + * \return 1 if DMA started. + */ + +/* Linked lists for multi transfer buffer chaining structure instance. */ + +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma location = "region_dma_nocache" +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((__section__(".region_dma_nocache"))) +#endif +static sDmaTransferDescriptor LLI_R[256]; + +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma location = "region_dma_nocache" +#elif defined ( __GNUC__ ) /* GCC CS3 */ +__attribute__((__section__(".region_dma_nocache"))) +#endif +static sDmaTransferDescriptor LLI_W[256]; + +static uint32_t _MciDMA(sMcid *pMcid, uint32_t bFByte, uint8_t bRd) +{ + Hsmci *pHw = pMcid->pMciHw; + sDmad *pDmad = pMcid->pDmad; + sSdmmcCommand *pCmd = pMcid->pCmd; + uint8_t i; + sDmaTransferDescriptor td; + uint32_t totalSize = pCmd->wNbBlocks * pCmd->wBlockSize; + uint32_t maxXSize; + uint32_t memAddress; + uint8_t bMByte; + + if (pMcid->dwXfrNdx >= totalSize) + { + return 0; + } + /* Prepare DMA transfer */ +if(pCmd->wBlockSize != 1){ + pMcid->dwXSize = totalSize - pMcid->dwXfrNdx; + if (bRd) + { + for ( i = 0; i < pCmd->wNbBlocks; i++) + { + //LLI_R[i].dwSrcAddr = (uint32_t)&(pHw->HSMCI_FIFO[i]); + LLI_R[i].dwSrcAddr = (uint32_t)&(pHw->HSMCI_RDR); + LLI_R[i].dwDstAddr = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize]; + LLI_R[i].dwCtrlA = DMAC_CTRLA_SRC_WIDTH_WORD | + DMAC_CTRLA_DST_WIDTH_WORD | + //DMAC_CTRLA_SCSIZE_CHK_32| + pCmd->wBlockSize /4 ; + LLI_R[i].dwCtrlB = DMAC_CTRLB_FC_PER2MEM_DMA_FC | + //DMAC_CTRLB_SRC_INCR_INCREMENTING | + DMAC_CTRLB_SRC_INCR_FIXED | + DMAC_CTRLB_DST_INCR_INCREMENTING | + DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM | + DMAC_CTRLB_DST_DSCR_FETCH_DISABLE | + DMAC_CTRLB_IEN | + DMAC_CTRLB_SIF_AHB_IF2 | + DMAC_CTRLB_DIF_AHB_IF0; + if ( i == pCmd->wNbBlocks - 1) + LLI_R[i].dwDscAddr = 0; + else + LLI_R[i].dwDscAddr = (uint32_t)&LLI_R[ i + 1 ]; + } + DMAD_PrepareMultiTransfer(pDmad, pMcid->dwDmaCh, &LLI_R[0]); + } + else { + for ( i = 0; i < pCmd->wNbBlocks; i++) + { + LLI_W[i].dwSrcAddr = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize]; + //LLI_W[i].dwDstAddr = (uint32_t)&(pHw->HSMCI_FIFO[i]); + LLI_W[i].dwDstAddr = (uint32_t)&(pHw->HSMCI_TDR); + LLI_W[i].dwCtrlA = DMAC_CTRLA_SRC_WIDTH_WORD | + DMAC_CTRLA_DST_WIDTH_WORD | + //DMAC_CTRLA_DCSIZE_CHK_32 | + pCmd->wBlockSize /4 ; + LLI_W[i].dwCtrlB = DMAC_CTRLB_FC_MEM2PER_DMA_FC | + DMAC_CTRLB_SRC_INCR_INCREMENTING | + //DMAC_CTRLB_DST_INCR_INCREMENTING | + DMAC_CTRLB_DST_INCR_FIXED | + DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE | + DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM | + DMAC_CTRLB_IEN | + DMAC_CTRLB_SIF_AHB_IF0 | + DMAC_CTRLB_DIF_AHB_IF2; + if ( i == pCmd->wNbBlocks - 1) + LLI_W[i].dwDscAddr = 0; + else + LLI_W[i].dwDscAddr = (uint32_t)&LLI_W[ i + 1 ]; + } + DMAD_PrepareMultiTransfer(pDmad, pMcid->dwDmaCh, &LLI_W[0]); + } + _MciDMAStart(pDmad, pMcid->dwDmaCh); +}else { + + /* Memory address and alignment */ + memAddress = (uint32_t)&pCmd->pData[pMcid->dwXfrNdx]; + bMByte = bFByte ? 1 : (((memAddress & 0x3) || (totalSize & 0x3))); + /* P to M: Max size is P size */ + if (bRd) + { + maxXSize = bFByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4); + } + /* M to P: Max size is M size */ + else + { + maxXSize = bMByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4); + } + /* Update index */ + pMcid->dwXSize = totalSize - pMcid->dwXfrNdx; + if (pMcid->dwXSize > maxXSize) + { + pMcid->dwXSize = maxXSize; + } + /* Prepare DMA transfer */ + if (bRd) + { + CP15_coherent_dcache_for_dma ((uint32_t)memAddress, ((uint32_t)memAddress + (pMcid->dwXSize))); + /* RX: bytes or words */ + uint32_t btR = DMAC_CTRLA_BTSIZE(bFByte ? pMcid->dwXSize : toWCOUNT(pMcid->dwXSize)); + td.dwSrcAddr = (uint32_t)&(pHw->HSMCI_RDR); + td.dwDstAddr = memAddress; + td.dwCtrlA = btR + | (bFByte ? DMAC_CTRLA_SRC_WIDTH_BYTE + : DMAC_CTRLA_SRC_WIDTH_WORD) + | (bMByte ? DMAC_CTRLA_DST_WIDTH_BYTE + : DMAC_CTRLA_DST_WIDTH_WORD) ; + td.dwCtrlB = DMAC_CTRLB_SRC_DSCR | DMAC_CTRLB_DST_DSCR + | DMAC_CTRLB_FC_PER2MEM_DMA_FC + | DMAC_CTRLB_SRC_INCR_FIXED + | DMAC_CTRLB_DST_INCR_INCREMENTING + | DMAC_CTRLB_IEN + | DMAC_CTRLB_SIF_AHB_IF2 + | DMAC_CTRLB_DIF_AHB_IF0 ; + td.dwDscAddr = 0; + } + else + { + /* TX: Always words */ + uint32_t btW = DMAC_CTRLA_BTSIZE(toWCOUNT(pMcid->dwXSize)); + CP15_coherent_dcache_for_dma ((uint32_t)memAddress, ((uint32_t)memAddress + (pMcid->dwXSize))); + td.dwSrcAddr = memAddress; + td.dwDstAddr = (uint32_t)&(pHw->HSMCI_TDR); + td.dwCtrlA = btW + | (bMByte ? DMAC_CTRLA_SRC_WIDTH_BYTE : DMAC_CTRLA_SRC_WIDTH_WORD) + | (bFByte ? DMAC_CTRLA_DST_WIDTH_BYTE : DMAC_CTRLA_DST_WIDTH_WORD); + td.dwCtrlB = DMAC_CTRLB_SRC_DSCR | DMAC_CTRLB_DST_DSCR + | DMAC_CTRLB_FC_MEM2PER_DMA_FC + | DMAC_CTRLB_SRC_INCR_INCREMENTING + | DMAC_CTRLB_DST_INCR_FIXED + | DMAC_CTRLB_IEN + | DMAC_CTRLB_SIF_AHB_IF0 + | DMAC_CTRLB_DIF_AHB_IF2; + td.dwDscAddr = 0; + } + DMAD_PrepareSingleTransfer(pDmad, pMcid->dwDmaCh, &td); + _MciDMAStart(pDmad, pMcid->dwDmaCh); + } + + return 1; +} + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * Reset MCI HW interface and disable it. + * \param keepSettings Keep old register settings, including + * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. + */ +static void MCI_Reset(sMcid *pMci, uint8_t keepSettings) +{ + Hsmci *pMciHw = pMci->pMciHw; + + assert(pMci); + assert(pMci->pMciHw); + + HSMCI_Reset( pMciHw, keepSettings ); +} + +/** + * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is + * MCK/2 and corresponds to CLKDIV = 0 + * \param pMci Pointer to the low level MCI driver. + * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. + * \param mck MCK to generate MCI Clock, in Hz + * \return The actual speed used, 0 for fail. + */ +static uint32_t MCI_SetSpeed( sMcid* pMci, uint32_t mciSpeed, uint32_t mck ) +{ + Hsmci *pMciHw = pMci->pMciHw; + uint32_t clkdiv; + assert(pMci); + assert(pMciHw); + + if((mck % mciSpeed) == 0) + { + clkdiv = mck /mciSpeed; + } + else + { + clkdiv = ((mck + mciSpeed)/mciSpeed); + } + mciSpeed = mck / clkdiv; + + /* Modify MR */ + HSMCI_DivCtrl( pMciHw, clkdiv, 0x7); + return (mciSpeed); +} + +/** + */ +static void _FinishCmd( sMcid* pMcid, uint8_t bStatus ) +{ + sSdmmcCommand *pCmd = pMcid->pCmd; + sDmad *pDmad = pMcid->pDmad; + //uint32_t memAddress; + /* Release DMA channel (if used) */ + if (pMcid->dwDmaCh != DMAD_ALLOC_FAILED) + { + DMAD_FreeChannel(pDmad, pMcid->dwDmaCh); + pMcid->dwDmaCh = DMAD_ALLOC_FAILED; + } + /* Release command */ + pMcid->pCmd = NULL; + pMcid->bState = MCID_LOCKED; + pCmd->bStatus = bStatus; + /* Invoke callback */ + if (pCmd->fCallback) + { + (pCmd->fCallback)(pCmd->bStatus, pCmd->pArg); + } +} + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * Initialize MCI driver. + */ +void MCID_Init(sMcid *pMcid, + Hsmci *pMci, uint8_t bID, uint32_t dwMck, + sDmad *pDmad, + uint8_t bPolling) +{ + uint16_t clkDiv; + + assert(pMcid); + assert(pMci); + + /* Initialize driver struct */ + pMcid->pMciHw = pMci; + pMcid->pCmd = NULL; + + pMcid->pDmad = pDmad; + pMcid->dwDmaCh = DMAD_ALLOC_FAILED; + pMcid->dwXfrNdx = 0; + + pMcid->dwMck = dwMck; + + pMcid->bID = bID; + pMcid->bPolling = bPolling; + pMcid->bState = MCID_IDLE; + + _PeripheralEnable( bID ); + + MCI_RESET( pMci ); + MCI_DISABLE ( pMci ); + HSMCI_DisableIt( pMci, 0xFFFFFFFF ); + HSMCI_ConfigureDataTO( pMci, HSMCI_DTOR_DTOCYC(0xFF) + |HSMCI_DTOR_DTOMUL_1048576 ); + HSMCI_ConfigureCompletionTO( pMci , HSMCI_CSTOR_CSTOCYC(0xFF) + |HSMCI_CSTOR_CSTOMUL_1048576 ); + /* Set the Mode Register: 400KHz */ + clkDiv = (dwMck / (MCI_INITIAL_SPEED << 1)) - 1; + HSMCI_ConfigureMode( pMci, (clkDiv | HSMCI_MR_PWSDIV(0x7)) ); + + HSMCI_Enable( pMci ); + HSMCI_Configure( pMci, HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL ); + /* Enable DMA */ + HSMCI_EnableDma( pMci, 1 ); + //_PeripheralDisable( bID ); +} + +/** + * Lock the MCI driver for slot N access + */ +uint32_t MCID_Lock(sMcid *pMcid, uint8_t bSlot) +{ + Hsmci *pHw = pMcid->pMciHw; + uint32_t sdcr; + + assert(pMcid); + assert(pMcid->pMciHw); + + if (bSlot > 0) + { + return SDMMC_ERROR_PARAM; + } + if (pMcid->bState >= MCID_LOCKED) + { + return SDMMC_ERROR_LOCKED; + } + pMcid->bState = MCID_LOCKED; + sdcr = pHw->HSMCI_SDCR & ~(uint32_t)HSMCI_SDCR_SDCSEL_Msk; + pHw->HSMCI_SDCR = sdcr | (bSlot << HSMCI_SDCR_SDCSEL_Pos); + return SDMMC_OK; +} + +/** + * Release the driver. + */ +uint32_t MCID_Release(sMcid *pMcid) +{ + assert(pMcid); + + if (pMcid->bState >= MCID_CMD) + { + return SDMMC_ERROR_BUSY; + } + pMcid->bState = MCID_IDLE; + return SDMMC_OK; +} + +/** + * SD/MMC command. + */ +uint32_t MCID_SendCmd(sMcid *pMcid, void *pCommand) +{ + Hsmci *pHw = pMcid->pMciHw; + sSdmmcCommand *pCmd = pCommand; + uint32_t mr, ier; + uint32_t cmdr; + + assert(pMcid); + assert(pMcid->pMciHw); + assert(pCmd); + if (!MCID_IsCmdCompleted(pMcid)) + { + return SDMMC_ERROR_BUSY; + } + pMcid->bState = MCID_CMD; + pMcid->pCmd = pCmd; + + //_PeripheralEnable(pMcid->bID); + MCI_DISABLE(pHw); + mr = HSMCI_GetMode(pHw) & (~(uint32_t)(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF |HSMCI_MR_FBYTE)); + /* Special: PowerON Init */ + if (pCmd->cmdOp.wVal == SDMMC_CMD_POWERONINIT){ + HSMCI_ConfigureMode(pHw, mr); + ier = HSMCI_IER_XFRDONE; + } + /* Normal command: idle the bus */ + else if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR) + { + //printf("S "); + + HSMCI_ConfigureMode(pHw, mr); + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP; + } + /* No data transfer */ + else if ((pCmd->cmdOp.wVal & SDMMC_CMD_CNODATA(0xF)) == SDMMC_CMD_CNODATA(0)) + { + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP; + /* R3 response, no CRC */ + if (pCmd->cmdOp.bmBits.respType == 3) + { + ier &= ~(uint32_t)HSMCI_IER_RCRCE; + } + } + /* Data command but no following */ + else if (pCmd->wNbBlocks == 0 || pCmd->pData == 0) + { + HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF + | HSMCI_MR_RDPROOF); + HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks); + ier = HSMCI_IER_CMDRDY | STATUS_ERRORS_RESP; + } + /* Command? with data */ + else + { + /* Setup block size */ + if (pCmd->cmdOp.bmBits.sendCmd) + { + HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks); + } + /* Block size is 0, force byte */ + if (pCmd->wBlockSize == 0) + pCmd->wBlockSize = 1; + + /* Force byte transfer */ + if (pCmd->wBlockSize & 0x3) + { + mr |= HSMCI_MR_FBYTE; + } + /* Set block size & MR */ + HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF + | HSMCI_MR_RDPROOF + | (pCmd->wBlockSize << 16)); + /* DMA write */ + if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX) + { + if (_MciDMAPrepare(pMcid, 0)) + { + _FinishCmd(pMcid, SDMMC_ERROR_BUSY); + return SDMMC_ERROR_BUSY; + } + _MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),0); + if (pCmd->bCmd != 25) { + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA; + } + if (pCmd->bCmd == 53) { + ier = HSMCI_IER_DMADONE| STATUS_ERRORS_DATA; + } + else { + //NOTBUSY DMADONE FIFOEMPTY XFRDONE + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA; + } + } + else + { + if (_MciDMAPrepare(pMcid, 1)) + { + _FinishCmd(pMcid, SDMMC_ERROR_BUSY); + return SDMMC_ERROR_BUSY; + } + _MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),1); + if (pCmd->bCmd != 18) { + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA; + } + else { + ier = HSMCI_IER_NOTBUSY | HSMCI_IER_XFRDONE |HSMCI_IER_FIFOEMPTY |HSMCI_IER_DMADONE | STATUS_ERRORS_DATA; + } + } + } + MCI_ENABLE(pHw); + if (pCmd->cmdOp.wVal & (SDMMC_CMD_bmPOWERON | SDMMC_CMD_bmCOMMAND)) + { + //uint32_t cmdr; + cmdr = pCmd->bCmd; + + if (pCmd->cmdOp.bmBits.powerON) + { + cmdr |= (HSMCI_CMDR_OPDCMD | HSMCI_CMDR_SPCMD_INIT); + } + if (pCmd->cmdOp.bmBits.odON) + { + cmdr |= HSMCI_CMDR_OPDCMD; + } + if (pCmd->cmdOp.bmBits.sendCmd) + { + cmdr |= HSMCI_CMDR_MAXLAT; + } + switch(pCmd->cmdOp.bmBits.xfrData) + { + case SDMMC_CMD_TX: + if (pCmd->cmdOp.bmBits.ioCmd) + { + cmdr |= (pCmd->wBlockSize == 1) ? + _CMDR_SDIO_BYTE : + _CMDR_SDIO_BLOCK; + } + else + { + cmdr |= (pCmd->wNbBlocks == 1) ? + _CMDR_SDMEM_SINGLE : + _CMDR_SDMEM_MULTI; + } + break; + + case SDMMC_CMD_RX: + if (pCmd->cmdOp.bmBits.ioCmd) + { + cmdr |= HSMCI_CMDR_TRDIR_READ + |((pCmd->wBlockSize == 1) ? + _CMDR_SDIO_BYTE : + _CMDR_SDIO_BLOCK) + ; + } + else + { + cmdr |= HSMCI_CMDR_TRDIR_READ + |((pCmd->wNbBlocks == 1) ? + _CMDR_SDMEM_SINGLE : + _CMDR_SDMEM_MULTI) + ; + } + break; + + case SDMMC_CMD_STOPXFR: + cmdr |= HSMCI_CMDR_TRCMD_STOP_DATA; + break; + } + switch(pCmd->cmdOp.bmBits.respType) + { + case 3: case 4: + /* ignore CRC error */ + ier &= ~(uint32_t)HSMCI_IER_RCRCE; + case 1: case 5: case 6: case 7: + cmdr |= HSMCI_CMDR_RSPTYP_48_BIT; + break; + case 2: + cmdr |= HSMCI_CMDR_RSPTYP_136_BIT; + break; + /* No response, ignore RTOE */ + default: + ier &= ~(uint32_t)HSMCI_IER_RTOE; + } + + pHw->HSMCI_ARGR = pCmd->dwArg; + pHw->HSMCI_CMDR = cmdr; + } + + /* Ignore CRC error for R3 & R4 */ + if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR) + { + ier &= ~STATUS_ERRORS_DATA; + } + + /* Enable status flags */ + HSMCI_EnableIt(pHw, ier); + + return SDMMC_OK; +} +static uint32_t dwMsk; +/** + * Process pending events on the given MCI driver. + */ +void MCID_Handler(sMcid *pMcid) +{ + Hsmci *pHw = pMcid->pMciHw; + sSdmmcCommand *pCmd = pMcid->pCmd; + //uint32_t dwSr, dwMsk, dwMaskedSr; + uint32_t dwSr, dwMaskedSr; + assert(pMcid); + assert(pMcid->pMciHw); + + /* Do nothing if no pending command */ + if (pCmd == NULL) + { + if (pMcid->bState >= MCID_CMD) + { + pMcid->bState = MCID_LOCKED; + } + return; + } + + /* Read status */ + dwSr = HSMCI_GetStatus(pHw); + dwMsk = HSMCI_GetItMask(pHw); + dwMaskedSr = dwSr & dwMsk; + /* Check errors */ + if (dwMaskedSr & STATUS_ERRORS) + { + //printf("STATUS_ERRORS "); + if (dwMaskedSr & HSMCI_SR_RTOE) + { + pCmd->bStatus = SDMMC_ERROR_NORESPONSE; + } + else + { + if (pCmd->bCmd != 19) { + pCmd->bStatus = SDMMC_ERROR; } + } + if (pCmd->bCmd != 12) pMcid->bState = MCID_ERROR; + } + dwMsk &= ~STATUS_ERRORS; + + /* Check command complete */ + if (dwMaskedSr & HSMCI_SR_CMDRDY) + { + HSMCI_DisableIt(pHw, HSMCI_IDR_CMDRDY); + dwMsk &= ~(uint32_t)HSMCI_IMR_CMDRDY; + } + + /* Check transfer done */ + if (dwMaskedSr & HSMCI_SR_XFRDONE) + { + //printf("XFRDONE "); + HSMCI_DisableIt(pHw, HSMCI_IDR_XFRDONE); + dwMsk &= ~(uint32_t)HSMCI_IMR_XFRDONE; + } + /* Check if not busy */ + if (dwMaskedSr & HSMCI_SR_NOTBUSY) + { + //printf("NOTBUSY "); + HSMCI_DisableIt(pHw, HSMCI_IDR_NOTBUSY); + dwMsk &= ~(uint32_t)HSMCI_IMR_NOTBUSY; + } + /* Check if TX ready */ + if (dwMaskedSr & HSMCI_SR_TXRDY) + { + //printf("TXRDY "); + dwMsk &= ~(uint32_t)HSMCI_IMR_TXRDY; + } + /* Check if DMA finished */ + if (dwMaskedSr & HSMCI_SR_DMADONE) + { + //printf("DMADONE "); + uint8_t bGoon, bFByte = HSMCI_IsFByteEnabled(pHw); + if (bFByte) { + pMcid->dwXfrNdx += pMcid->dwXSize; + /* Next transfer */ + bGoon = _MciDMA(pMcid, bFByte, (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_RX)); + if (bGoon) + { + /* Go on: Waiting DMADONE */ + } + else + { + /* Disable DMA done */ + HSMCI_DisableIt(pHw, HSMCI_IDR_DMADONE); + /* For TX, check FIFOEMPTY - BLKE - TXRDY */ + if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX) + { + HSMCI_EnableIt(pHw, HSMCI_IER_FIFOEMPTY); + } + else + { + dwMsk &= ~(uint32_t)HSMCI_IMR_DMADONE; + } + } + } + else + { + HSMCI_DisableIt(pHw, HSMCI_IDR_DMADONE); + dwMsk &= ~(uint32_t)HSMCI_IMR_DMADONE; + } + } + /* Check if FIFO empty (all data sent) */ + if (dwMaskedSr & HSMCI_SR_FIFOEMPTY) + { + //printf("FIFOEMPTY "); + /* Disable FIFO empty */ + HSMCI_DisableIt(pHw, HSMCI_IDR_FIFOEMPTY); + dwMsk &= ~(uint32_t)HSMCI_IMR_FIFOEMPTY; + } + /* All none error mask done, complete the command */ + if (0 == dwMsk || pMcid->bState == MCID_ERROR) + { + /* Error reset */ + if (pMcid->bState == MCID_ERROR) + { + MCI_Reset(pMcid, 1); + } + else + { + pCmd->bStatus = SDMMC_SUCCESS; + + if (pCmd->pResp) + { + uint8_t bRspSize, i; + switch(pCmd->cmdOp.bmBits.respType) + { + case 1: case 3: case 4: case 5: case 6: case 7: + bRspSize = 1; + break; + + case 2: + bRspSize = 4; + break; + + default: + bRspSize = 0; + } + for (i = 0; i < bRspSize; i ++) + { + pCmd->pResp[i] = HSMCI_GetResponse(pHw); + } + } + } + /* Disable interrupts */ + HSMCI_DisableIt(pHw, HSMCI_GetItMask(pHw)); + /* Disable peripheral */ + //_PeripheralDisable(pMcid->bID); + /* Command is finished */ + _FinishCmd(pMcid, pCmd->bStatus); + + } +} + +/** + * Cancel pending SD/MMC command. + */ +uint32_t MCID_CancelCmd(sMcid *pMcid) +{ + if (pMcid->bState == MCID_IDLE) + { + return SDMMC_ERROR_STATE; + } + if (pMcid->bState == MCID_CMD) + { + /* Cancel ... */ + MCI_Reset(pMcid, 1); + /* Command is finished */ + _FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL); + } + return SDMMC_OK; +} + +/** + * Reset MCID and disable HW + */ +void MCID_Reset(sMcid * pMcid) +{ + Hsmci *pHw = pMcid->pMciHw; + + MCID_CancelCmd(pMcid); + + //_PeripheralEnable(pMcid->bID); + + /* Disable */ + MCI_DISABLE(pHw); + /* MR reset */ + HSMCI_ConfigureMode(pHw, HSMCI_GetMode(pHw) & (HSMCI_MR_CLKDIV_Msk + | HSMCI_MR_PWSDIV_Msk)); + /* BLKR reset */ + HSMCI_ConfigureTransfer(pHw, 0, 0); + + /* Cancel ... */ + MCI_Reset(pMcid, 1); + //_PeripheralDisable(pMcid->bID); + + if (pMcid->bState == MCID_CMD) + { + /* Command is finished */ + _FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL); + } +} + +/** + * Check if the command is finished + */ +uint32_t MCID_IsCmdCompleted(sMcid *pMcid) +{ + sSdmmcCommand *pCmd = pMcid->pCmd; + + if (pMcid->bPolling) + { + MCID_Handler(pMcid); + } + if (pMcid->bState == MCID_CMD) + { + return 0; + } + if (pCmd) + { + return 0; + } + return 1; +} + +/** + * IO control functions + */ +uint32_t MCID_IOCtrl(sMcid *pMcid, uint32_t bCtl, uint32_t param) +{ + Hsmci *pMciHw = pMcid->pMciHw; + assert(pMcid); + assert(pMcid->pMciHw); + + //mciDis = _PeripheralEnable(pMcid->bID); + + switch (bCtl) + { + case SDMMC_IOCTL_BUSY_CHECK: + *(uint32_t*)param = !MCID_IsCmdCompleted(pMcid); + break; + + case SDMMC_IOCTL_POWER: + return SDMMC_ERROR_NOT_SUPPORT; + + case SDMMC_IOCTL_RESET: + MCID_Reset(pMcid); + return SDMMC_SUCCESS; + + case SDMMC_IOCTL_CANCEL_CMD: + return MCID_CancelCmd(pMcid); + + case SDMMC_IOCTL_SET_CLOCK: + *(uint32_t*)param = MCI_SetSpeed(pMcid, + *(uint32_t*)param, + pMcid->dwMck); + break; + + case SDMMC_IOCTL_SET_HSMODE: + HSMCI_HsEnable( pMciHw, *(uint32_t*)param ); + *(uint32_t*)param = HSMCI_IsHsEnabled( pMciHw ); + + break; + + case SDMMC_IOCTL_SET_BUSMODE: + HSMCI_SetBusWidth( pMciHw, *(uint32_t*)param ); + break; + + case SDMMC_IOCTL_GET_BUSMODE: + //*(uint32_t*)param = 8; /* Max 4-bit bus */ + break; + + case SDMMC_IOCTL_GET_HSMODE: + *(uint32_t*)param = 1; /* Supported */ + break; + + default: + return SDMMC_ERROR_NOT_SUPPORT; + + } + return SDMMC_OK; +} + +/** + * Initialize the SD/MMC card driver struct for SD/MMC bus mode + * \note defined in SD/MMC bus mode low level (Here uses MCI interface) + */ +void SDD_InitializeSdmmcMode(sSdCard * pSd,void * pDrv,uint8_t bSlot) +{ + SDD_Initialize(pSd, pDrv, bSlot, &sdHal); +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/omnivision.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/omnivision.c new file mode 100644 index 000000000..c399da936 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/omnivision.c @@ -0,0 +1,421 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + +/** Slave address of OMNIVISION chips. */ +#define OV_CAPTOR_ADDRESS_1 0x30 +#define OV_CAPTOR_ADDRESS_2 0x21 +#define OV_CAPTOR_ADDRESS_3 0x3c +#define OV_CAPTOR_ADDRESS_4 0x10 + +/** terminating list entry for register in configuration file */ +#define OV_REG_TERM 0xFF +#define OV_REG_DELAY 0xFFFF +/** terminating list entry for value in configuration file */ +#define OV_VAL_TERM 0xFF + +static const Pin pin_ISI_RST= PIN_ISI_RST; +static uint8_t twiSlaveAddr = OV_CAPTOR_ADDRESS_1; +/*---------------------------------------------------------------------------- + * Local Functions + *----------------------------------------------------------------------------*/ +static void ov_reset(void) +{ + volatile uint32_t i; + PIO_Configure(&pin_ISI_RST, 1); + PIO_Clear(&pin_ISI_RST); + for(i = 0; i < 6000; i++ ); + PIO_Set(&pin_ISI_RST); + for(i = 0; i<6000; i++ ); +} + + +/** + * \brief Read PID and VER + * \param pTwid TWI interface + * \return VER | (PID<<8) + */ +static uint16_t ov_id8(Twid *pTwid) +{ + uint8_t id, ver; + uint8_t status; + // OV_PID + status = ov_read_reg8(pTwid, 0x0A, &id); + if( status != 0 ) return 0; + TRACE_INFO("PID = 0x%X\n\r", id); + + // OV_VER + status = ov_read_reg8(pTwid, 0x0B, &ver); + if( status != 0 ) return 0; + TRACE_INFO("VER = 0x%X\n\r", ver); + + return((uint16_t)(id <<8) | ver); +} + +/** + * \brief Read PID and VER + * \param pTwid TWI interface + * \return VER | (PID<<8) + */ +static uint16_t ov_id16(Twid *pTwid) +{ + uint8_t id, ver; + // OV_PID + ov_read_reg16(pTwid, 0x300A, &id); + TRACE_INFO("PID = 0x%X\n\r", id); + + // OV_VER + ov_read_reg16(pTwid, 0x300B, &ver); + TRACE_INFO("VER = 0x%X\n\r", ver); + + return((uint16_t)(id <<8) | ver); +} + +/** + * \brief Read PID and VER + * \param pTwid TWI interface + * \return VER | (PID<<8) + */ +static uint16_t ov_id(Twid *pTwid) +{ + uint16_t id; + printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr); + twiSlaveAddr = OV_CAPTOR_ADDRESS_1; + id = ov_id8(pTwid); + if (id == 0) { + twiSlaveAddr = OV_CAPTOR_ADDRESS_2; + printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr); + id = ov_id8(pTwid); + if (id == 0) { + twiSlaveAddr = OV_CAPTOR_ADDRESS_3; + printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr); + id = ov_id16(pTwid); + if (id == 0) { + twiSlaveAddr = OV_CAPTOR_ADDRESS_4; + printf("-I- Try TWI address 0x%x \n\r", twiSlaveAddr); + id = ov_id16(pTwid); + } + } + } + return id; +} + + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ +/** + * \brief Read a value from a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be read + * \param isize Internal address size in bytes. + * \param pData Data read + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData) +{ + uint8_t status; + + status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, ®, 1, 0); + status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_read_reg pb\n\r"); + } + return status; +} + +/** + * \brief Read a value from a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be read + * \param pData Data read + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData) +{ + uint8_t status; + uint8_t reg8[2]; + reg8[0] = reg>>8; + reg8[1] = reg & 0xff; + + status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, reg8, 2, 0); + status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0); + if( status != 0 ) { + + TRACE_ERROR("ov_read_reg pb\n\r"); + } + return status; +} + +/** + * \brief Write a value to a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be writen + * \param pData Data written + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val) +{ + uint8_t status; + + status = TWID_Write(pTwid, twiSlaveAddr, reg, 1, &val, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_write_reg pb\n\r"); + } + + return status; +} + +/** + * \brief Write a value to a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be writen + * \param pData Data written + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val) +{ + uint8_t status; + status = TWID_Write(pTwid, twiSlaveAddr, reg, 2, &val, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_write_reg pb\n\r"); + } + + return status; +} + + +/** + * \brief Initialize a list of OV registers. + * The list of registers is terminated by the pair of values + * \param pTwid TWI interface + * \param pReglist Register list to be written + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist) +{ + uint32_t err; + uint32_t size=0; + const struct ov_reg *pNext = pReglist; + volatile uint32_t delay; + + TRACE_DEBUG("ov_write_regs:"); + while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) { + err = ov_write_reg8(pTwid, pNext->reg, pNext->val); + + size++; + for(delay=0;delay<=10000;delay++); + if (err == TWID_ERROR_BUSY){ + TRACE_ERROR("ov_write_regs: TWI ERROR\n\r"); + return err; + } + //printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val); + pNext++; + } + TRACE_DEBUG_WP("\n\r"); + return 0; +} + + +/** + * \brief Initialize a list of OV registers. + * The list of registers is terminated by the pair of values + * \param pTwid TWI interface + * \param pReglist Register list to be written + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist) +{ + uint32_t err = 0; + uint32_t size = 0; + const struct ov_reg *pNext = pReglist; + volatile uint32_t delay; + + TRACE_DEBUG("ov_write_regs:"); + while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) { + err = ov_write_reg16(pTwid, pNext->reg, pNext->val); + size++; + for(delay = 0;delay <= 10000; delay++); + if (err == TWID_ERROR_BUSY){ + TRACE_ERROR("ov_write_regs: TWI ERROR\n\r"); + return err; + } + //printf("(0x%02x,0x%02x) \n\r", pNext->reg,pNext->val); + pNext++; + } + TRACE_DEBUG_WP("\n\r"); + return 0; +} + +void isOV5640_AF_InitDone(Twid *pTwid) +{ + uint8_t value = 0; + while(1){ + ov_read_reg16(pTwid, 0x3029, &value); + if (value == 0x70) break; + } +} + +/** + * \brief AF for OV 5640 + * \param pTwid TWI interface + * \return 0 if no error; otherwize TWID_ERROR_BUSY + */ +uint32_t ov_5640_AF_single(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3023, 1); + ov_write_reg16(pTwid, 0x3022, 3); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) break; + } + return 0; +} + +uint32_t ov_5640_AF_continue(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3024, 1); + ov_write_reg16(pTwid, 0x3022, 4); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) break; + } + return 0; +} + +uint32_t ov_5640_AFPause(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3023, 1); + ov_write_reg16(pTwid, 0x3022, 6); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) break; + } + return 0; +} + +uint32_t ov_5640_AFrelease(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3023, 1); + ov_write_reg16(pTwid, 0x3022, 8); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) break; + } + return 0; +} + +/** + * \brief Dump all register + * \param pTwid TWI interface + */ +void ov_DumpRegisters8(Twid *pTwid) +{ + uint32_t i; + uint8_t value; + + TRACE_INFO_WP("Dump all camera register\n\r"); + for(i = 0; i <= 0x5C; i++) { + value = 0; + ov_read_reg8(pTwid, i, &value); + TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value); + if( ((i+1)%5) == 0 ) { + TRACE_INFO_WP("\n\r"); + } + } + TRACE_INFO_WP("\n\r"); +} + +/** + * \brief Dump all register + * \param pTwid TWI interface + */ +void ov_DumpRegisters16(Twid *pTwid) +{ + uint32_t i; + uint8_t value; + + TRACE_INFO_WP("Dump all camera register\n\r"); + for(i = 3000; i <= 0x305C; i++) { + value = 0; + ov_read_reg16(pTwid, i, &value); + TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value); + if( ((i+1)%5) == 0 ) { + TRACE_INFO_WP("\n\r"); + } + } + TRACE_INFO_WP("\n\r"); +} + +/** + * \brief Sequence For correct operation of the sensor + * \param pTwid TWI interface + * \return OV type + */ +uint8_t ov_init(Twid *pTwid) +{ + uint16_t id = 0; + uint8_t ovType; + ov_reset(); + id = ov_id(pTwid); + switch (id) { + case 0x7740: case 0x7742: + ovType = OV_7740; + break; + case 0x9740: case 0x9742: + ovType = OV_9740; + break; + case 0x2642: case 0x2640: + ovType = OV_2640; + break; + case 0x2643: + ovType = OV_2643; + break; + case 0x5640: + ovType = OV_5640; + break; + default: + ovType = OV_UNKNOWN; + TRACE_ERROR("Can not support product ID %x \n\r", id); + break; + } + return ovType; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov.c new file mode 100644 index 000000000..b04eea8c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + +const static struct capture_size ov_sizes[] = { +// {width, height} + /// VGA + { 640, 360 }, + { 640, 480 }, + // SWVGA + { 800, 600 }, + /// SXGA + {1280, 960 }, + {1280, 720 }, + /// UXGA + {1600, 1200 }, +}; + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configure the OV for a specified image size, pixel format, + * and frame period. + */ +void ov_configure(Twid *pTwid, uint8_t ovType, uint32_t width, uint32_t heigth) +{ + const struct ov_reg *reg_conf; + uint8_t goodCaptureSize = 0; + uint8_t i; + + reg_conf = ov5640_yuv_vga; + TRACE_DEBUG("ovxxx_configure\n\r"); + for( i = 0; i< sizeof(ov_sizes); i++ ) { + if( ov_sizes[i].width == width ) { + if( ov_sizes[i].height != heigth ) { + TRACE_INFO("ov configure vsize not define\n\r"); + } + else { + goodCaptureSize = 1; + break; + } + } + } + if( goodCaptureSize == 0 ) { + TRACE_ERROR("Problem size\n\r"); + while(1); + } + switch (ovType){ + case OV_2640: { + // Default value + reg_conf = ov2640_yuv_vga; + // common register initialization + switch(width) { + case 640: //VGA + printf("-I- VGA 640 x 480\n\r"); + reg_conf = ov2640_yuv_vga; + break; + default: + TRACE_DEBUG("ov2640_configure problem\n\r"); + break; + } + break; + } + case OV_7740: { + // Default value + reg_conf = ov7740_yuv_vga; + // common register initialization + switch(width) { + case 640: //VGA + printf("-I- VGA 640 x 480\n\r"); + reg_conf = ov7740_yuv_vga; + break; + default: + TRACE_DEBUG("ov7740_configure problem\n\r"); + break; + } + break; + } + case OV_9740: { + // Default value + reg_conf = ov9740_yuv_vga; + // common register initialization + switch(width) { + case 640: //VGA + printf("-I- VGA 640 x 360\n\r"); + reg_conf = ov9740_yuv_vga; + break; + case 1280: //VGA + printf("-I- VGA 1280 x 720\n\r"); + reg_conf = ov9740_yuv_sxga; + break; + default: + TRACE_DEBUG("ov9740_configure problem\n\r"); + break; + } + break; + } + case OV_2643: { + // Default value + reg_conf = ov2643_yuv_vga; + // common register initialization + switch(width) { + case 1600: //UXGA + printf("-I- UXGA 1600 x 1200 \n\r"); + reg_conf = ov2643_yuv_uxga; + break; + case 800: //SWVGA + printf("-I- SWVGA 800 x 600\n\r"); + reg_conf = ov2643_yuv_swvga; + break; + case 640: //VGA + printf("-I- VGA 640 x 480\n\r"); + reg_conf = ov2643_yuv_vga; + break; + default: + TRACE_DEBUG("ov2643_configure problem\n\r"); + break; + } + break; + } + case OV_5640: { + // Default value + reg_conf = ov5640_yuv_vga; + // common register initialization + switch(width) { + case 640: //VGA + printf("-I- VGA 640 x 480\n\r"); + reg_conf = ov5640_yuv_vga; + break; + case 1280: //SXGA + printf("-I- SXGA 1280 x 720\n\r"); + reg_conf = ov5640_yuv_sxga; + break; + default: + TRACE_DEBUG("ov5640_configure problem\n\r"); + break; + } + break; + } + } + if ((ovType == OV_5640) || (ovType == OV_9740)) + ov_write_regs16(pTwid, reg_conf); + else + ov_write_regs8(pTwid, reg_conf); +} + + +/** + * \brief Configure the OV 5640 afc fireware. + */ +void ov_5640Afc_Firmware(Twid *pTwid) +{ + const struct ov_reg *reg_conf; + reg_conf = ov5640_afc; + ov_write_regs16(pTwid, reg_conf); +} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov2640_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov2640_config.c new file mode 100644 index 000000000..15edfcb17 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov2640_config.c @@ -0,0 +1,286 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/* + * ID + */ + + + +/*------------------------------------------------------------------------------ + * Local Variables + *------------------------------------------------------------------------------*/ + +const struct ov_reg ov2640_yuv_vga[]= { + {0xff, 0x01}, //dsp + {0x12, 0x80}, //reset + {0xff, 0x00}, //sensor + {0x2c, 0xff}, //? + {0x2e, 0xdf}, //ADDVSH, VSYNC msb=223 + {0xff, 0x01}, //dsp + {0x3c, 0x32}, //? + {0x11, 0x00}, //clock rate off + {0x09, 0x02}, //2 capablity + standby mode + {0x04, 0x28}, //? ?????????????????????????????????? + {0x13, 0xe5}, // + {0x14, 0x48}, //Auto agc + {0x2c, 0x0c}, //? + {0x33, 0x78}, //? + {0x3a, 0x33}, //? + {0x3b, 0xfb}, //? + {0x3e, 0x00}, //? + {0x43, 0x11}, //? + {0x16, 0x10}, //? + {0x39, 0x02}, //? + {0x35, 0x88}, //? + {0x22, 0x0a}, //? + {0x37, 0x40}, //? + {0x23, 0x00}, //? + {0x34, 0xa0}, //startpoint 0 + {0x36, 0x1a}, //? XXXXXXXXXXXXXXXX + {0x06, 0x02}, //? + {0x07, 0xc0}, //? + {0x0d, 0xb7}, //? + {0x0e, 0x01}, //? + {0x4c, 0x00}, //? + {0x4a, 0x81}, //? + {0x21, 0x99}, //? + {0x24, 0x3a}, // Luminance high + {0x25, 0x32}, // Luminance low + //{0x24, 0x10}, // Luminance high + //{0x25, 0x03}, // Luminance low + + {0x26, 0xF3}, // Fast mode large Step Range Threshold + {0x5c, 0x00}, //? + {0x63, 0x00}, //? + {0x5d, 0x55}, //zone + {0x5e, 0x7d}, //zone + {0x5f, 0x7d}, //zone + {0x60, 0x55}, //zone + {0x61, 0x70}, //Histogram low + {0x62, 0x80}, //Histogram high + {0x7c, 0x05}, //? + {0x20, 0x80}, //? + {0x28, 0x30}, //? + {0x6c, 0x00}, //? + {0x6d, 0x80}, //? + {0x6e, 0x00}, //? + {0x70, 0x02}, //? + {0x71, 0x94}, //? + {0x73, 0xc1}, //? + {0x3d, 0x34}, //? + {0x5a, 0x57}, //? + {0x4f, 0xbb}, //50Hz + {0x50, 0x9c}, //60Hz + + {0xff, 0x00}, //dsp + {0xe5, 0x7f}, //? + {0xf9, 0xc0}, //MicroC reset,Boot + {0x41, 0x24}, //? + {0xe0, 0x14}, //JPEG,DVP reset + {0x76, 0xff}, //? + {0x33, 0xa0}, //? + {0x42, 0x20}, //? + {0x43, 0x18}, //? + {0x4c, 0x00}, //? + {0x87, 0xd0}, //Module Enable BPC+WPC 11010000 + {0x88, 0x3f}, //? + {0xd7, 0x03}, //? + {0xd9, 0x10}, //? + {0xd3, 0x82}, //Auto mode + {0xc8, 0x08}, //? + {0xc9, 0x80}, //? + {0x7c, 0x00}, //SDE indirect register access: address + {0x7d, 0x02}, //SDE indirect register data + {0x7c, 0x03}, // + {0x7d, 0x48}, // + {0x7d, 0x48}, // + {0x7c, 0x08}, // + {0x7d, 0x20}, // + {0x7d, 0x10}, // + {0x7d, 0x0e}, // + {0x90, 0x00}, //? + {0x91, 0x0e}, //? + {0x91, 0x1a}, //? + {0x91, 0x31}, //? + {0x91, 0x5a}, //? + {0x91, 0x69}, //? + {0x91, 0x75}, //? + {0x91, 0x7e}, //? + {0x91, 0x88}, //? + {0x91, 0x8f}, //? + {0x91, 0x96}, //? + {0x91, 0xa3}, //? + {0x91, 0xaf}, //? + {0x91, 0xc4}, //? + {0x91, 0xd7}, //? + {0x91, 0xe8}, //? + {0x91, 0x20}, //? + {0x92, 0x00}, //? + {0x93, 0x06}, //? + {0x93, 0xe3}, //? + {0x93, 0x05}, //? + {0x93, 0x05}, //? + {0x93, 0x00}, //? + {0x93, 0x02}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x96, 0x00}, //? + {0x97, 0x08}, //? + {0x97, 0x19}, //? + {0x97, 0x02}, //? + {0x97, 0x0c}, //? + {0x97, 0x24}, //? + {0x97, 0x30}, //? + {0x97, 0x28}, //? + {0x97, 0x26}, //? + {0x97, 0x02}, //? + {0x97, 0x98}, //? + {0x97, 0x80}, //? + {0x97, 0x00}, //? + {0x97, 0x00}, //? + {0xc3, 0xed}, //Module enable + {0xa4, 0x00}, //? + {0xa8, 0x00}, //? + {0xc5, 0x11}, //? + {0xc6, 0x51}, //? + {0xbf, 0x80}, //? + {0xc7, 0x10}, //? + {0xb6, 0x66}, //? + {0xb8, 0xa5}, //? + {0xb7, 0x64}, //? + {0xb9, 0x7c}, //? + {0xb3, 0xaf}, //? + {0xb4, 0x97}, //? + {0xb5, 0xff}, //? + {0xb0, 0xc5}, //? + {0xb1, 0x94}, //? + {0xb2, 0x0f}, //? + {0xc4, 0x5c}, //? + {0xc0, 0xc8}, // HSIZE8[7:0] 1600 + {0xc1, 0x96}, // VSIZE8[7:0] 1200 + {0x86, 0x1d}, //Module enable + {0x50, 0x00}, //? + {0x51, 0x90}, //H_SIZE[7:0] (real/4) 1600 + {0x52, 0x18}, //V_SIZE[7:0] (real/4) 1120 + {0x53, 0x00}, //OFFSET_X[7:0] + {0x54, 0x00}, //OFFSET_Y[7:0] + {0x55, 0x88}, //V_SIZE[8]=1 H_SIZE[8] + {0x57, 0x00}, //? + {0x5a, 0x90}, //OUTW + {0x5b, 0x18}, //OUTH + {0x5c, 0x05}, //OUTW8 ,OUTH8 + {0xc3, 0xed}, // + {0x7f, 0x00}, //? + {0xda, 0x04}, //Image output format select ------ RAW + {0xe5, 0x1f}, //? + {0xe1, 0x67}, //? + {0xe0, 0x00}, //Reset + {0xdd, 0xff}, //? + {0x05, 0x00}, //Bypass DSP no + {0xC2, 0x08 | 0x04 | 0x02 }, + + {0xff, 0x01}, //Sensor + {0x11, 0x01}, //? + {0xff, 0x01}, //Sensor + {0x12, 0x40}, //Preview mode + {0x17, 0x11}, //? + {0x18, 0x43}, //? + {0x19, 0x00}, //? + {0x1a, 0x4b}, //? + {0x32, 0x09}, //? + {0x4f, 0xca}, //? + {0x50, 0xa8}, //10 101 000 V_DIVDER = 5 + {0x5a, 0x23}, // OUTW 23 + {0x6d, 0x00}, //? + {0x3d, 0x38}, //? + {0x39, 0x12}, //? + {0x35, 0xda}, //? + {0x22, 0x1a}, //? + {0x37, 0xc3}, //? + {0x23, 0x00}, //? + {0x34, 0xc0}, //? + {0x36, 0x1a}, //? + {0x06, 0x88}, //? + {0x07, 0xc0}, //? + {0x0d, 0x87}, //? + {0x0e, 0x41}, //? + {0x4c, 0x00}, //? + {0x48, 0x00}, //? + {0x5B, 0x00}, //OUTH + {0x42, 0x03}, //? + {0xff, 0x00}, //DSP + + {0xe0, 0x04}, //Reset DVP + {0xc0, 0x64}, // HSIZE8[7:0] 400 + {0xc1, 0x4B}, // VSIZE8[7:0] 300 + {0x8c, 0x00}, //? + {0x86, 0x1D}, //Modle enable + {0xd3, 0x82}, //Auto mode DVP PCLK=2 + {0xe0, 0x00}, //Reset + + {0xff, 0x00}, //DSP + {0xc0, 0x64}, // HSIZE8[7:0] 400 + {0xc1, 0x4B}, // VSIZE8[7:0] 300 + {0x8c, 0x00}, //? + {0x86, 0x3D}, //? + {0x50, 0x00}, //? + {0x51, 0xC8}, //H_SIZE[7:0] (real/4) 800 + {0x52, 0x96}, //V_SIZE[7:0] (real/4) 600 + {0x53, 0x00}, //OFFSET + {0x54, 0x00}, //OFFSET + {0x55, 0x00}, //H_SIZE[8],V_SIZE[8] + {0x5a, 0xA0}, //OUTW[0-7] 160? + {0x5b, 0x78}, //OUTH[0-7] 120? + {0x5c, 0x00}, //OUTW8,OUTH8 + {0xd3, 0x04}, //? + {0xFF, 0x00}, + {0xE0, 0x04}, + {0xE1, 0x67}, + {0xD7, 0x01}, + {0xDA, 0x00}, //Image output format select ------ YUV422 + {0xD3, 0x82}, + {0xE0, 0x00}, + {0xFF, 0xFF} + }; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov2643_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov2643_config.c new file mode 100644 index 000000000..6e259ce18 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov2643_config.c @@ -0,0 +1,676 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/* + * ID + */ +#define MANUFACTURER_ID 0x7FA2 + + +/*------------------------------------------------------------------------------ + * Local Variables + *------------------------------------------------------------------------------*/ + +const struct ov_reg ov2643_yuv_uxga[]= { + {0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb4}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + + {0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb4}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + {0xFF, 0xFF} +}; + +const struct ov_reg ov2643_yuv_swvga[]= { +{0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb4}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + + {0x3d, 0x48}, + {0x0e, 0xb8}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x21, 0x98}, + {0x22, 0x00}, + {0x23, 0x06}, + {0x24, 0x32}, + {0x25, 0x04}, + {0x26, 0x25}, + {0x27, 0x84}, + {0x28, 0x40}, + {0x29, 0x04}, + {0x2a, 0xce}, + {0x2b, 0x02}, + {0x2c, 0x8a}, + {0x12, 0x09}, + {0x39, 0xd0}, + {0xcd, 0x13}, + {0xde, 0x7c}, + {0x3d, 0x08}, + {0x15, 0x42}, + {0xde, 0x7c}, + {0x0f, 0x24}, + {0xFF, 0xFF} +}; + +const struct ov_reg ov2643_yuv_vga[]= { +{0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb4}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + + {0x13, 0x00}, + {0x3d, 0x48}, + {0x0e, 0xb8}, + {0x20, 0x02}, + {0x21, 0x18}, + {0x22, 0x00}, + {0x23, 0x42}, + {0x24, 0x28}, + {0x25, 0x04}, + {0x26, 0x1e}, + {0x27, 0x04}, + {0x28, 0x40}, + {0x29, 0x04}, + {0x2a, 0xce}, + {0x2b, 0x02}, + {0x2c, 0x8a}, + {0x12, 0x09}, + {0x39, 0xd0}, + {0xcd, 0x13}, + {0xde, 0x7c}, + {0x3d, 0x08}, + {0x13, 0xff}, + {0x15, 0x42}, + {0xFF, 0xFF} +}; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov5640_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov5640_config.c new file mode 100644 index 000000000..a22f18bcb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov5640_config.c @@ -0,0 +1,4799 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Local Variables + *------------------------------------------------------------------------------*/ + +const struct ov_reg ov5640_yuv_vga[]= { + {0x3103, 0x11}, + {0x3008, 0x82}, + {0xFFFF, 0x05}, + {0x3008, 0x42}, + {0x3103, 0x03}, + {0x3017, 0xff}, + {0x3018, 0xff}, + + {0x3034, 0x1a}, + {0x3035, 0x11}, + {0x3036, 0x5b}, + {0x3037, 0x13}, + {0x3108, 0x01}, + {0x303d, 0x20}, + + {0x3630, 0x36}, + {0x3631, 0x0e}, + {0x3632, 0xe2}, + {0x3633, 0x12}, + {0x3621, 0xe0}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3905, 0x02}, + {0x3906, 0x10}, + {0x3901, 0x0a}, + {0x3731, 0x12}, + {0x3600, 0x08}, + {0x3601, 0x33}, + {0x302d, 0x60}, + {0x3620, 0x52}, + {0x371b, 0x20}, + {0x471c, 0x50}, + {0x3a13, 0x43}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3635, 0x13}, + {0x3636, 0x03}, + {0x3634, 0x40}, + {0x3622, 0x01}, + {0x3c01, 0x34}, + {0x3c04, 0x28}, + {0x3c05, 0x98}, + {0x3c06, 0x00}, + {0x3c07, 0x08}, + {0x3c08, 0x00}, + {0x3c09, 0x1c}, + {0x3c0a, 0x9c}, + {0x3c0b, 0x40}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x3f}, + {0x3806, 0x07}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3810, 0x00}, + {0x3811, 0x10}, + {0x3812, 0x00}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x64}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a08, 0x01}, + {0x3a09, 0x27}, + {0x3a0a, 0x00}, + {0x3a0b, 0xf6}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4001, 0x02}, + {0x4004, 0x02}, + {0x3000, 0x00}, + {0x3002, 0x1c}, + {0x3004, 0xff}, + {0x3006, 0xc3}, + {0x300e, 0x58}, + {0x302e, 0x00}, + {0x4300, 0x30}, + {0x501f, 0x00}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x440e, 0x00}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x4837, 0x22}, + {0x3824, 0x02}, + {0x5000, 0xa7}, + {0x5001, 0xa3}, + {0x5180, 0xff}, + {0x5181, 0xf2}, + {0x5182, 0x00}, + {0x5183, 0x14}, + {0x5184, 0x25}, + {0x5185, 0x24}, + {0x5186, 0x09}, + {0x5187, 0x09}, + {0x5188, 0x09}, + {0x5189, 0x75}, + {0x518a, 0x54}, + {0x518b, 0xe0}, + {0x518c, 0xb2}, + {0x518d, 0x42}, + {0x518e, 0x3d}, + {0x518f, 0x56}, + {0x5190, 0x46}, + {0x5191, 0xf8}, + {0x5192, 0x04}, + {0x5193, 0x70}, + {0x5194, 0xf0}, + {0x5195, 0xf0}, + {0x5196, 0x03}, + {0x5197, 0x01}, + {0x5198, 0x04}, + {0x5199, 0x12}, + {0x519a, 0x04}, + {0x519b, 0x00}, + {0x519c, 0x06}, + {0x519d, 0x82}, + {0x519e, 0x38}, + {0x5381, 0x1e}, + {0x5382, 0x5b}, + {0x5383, 0x08}, + {0x5384, 0x0a}, + {0x5385, 0x7e}, + {0x5386, 0x88}, + {0x5387, 0x7c}, + {0x5388, 0x6c}, + {0x5389, 0x10}, + {0x538a, 0x01}, + {0x538b, 0x98}, + {0x5300, 0x08}, + {0x5301, 0x30}, + {0x5302, 0x10}, + {0x5303, 0x00}, + {0x5304, 0x08}, + {0x5305, 0x30}, + {0x5306, 0x08}, + {0x5307, 0x16}, + {0x5309, 0x08}, + {0x530a, 0x30}, + {0x530b, 0x04}, + {0x530c, 0x06}, + {0x5480, 0x01}, + {0x5481, 0x08}, + {0x5482, 0x14}, + {0x5483, 0x28}, + {0x5484, 0x51}, + {0x5485, 0x65}, + {0x5486, 0x71}, + {0x5487, 0x7d}, + {0x5488, 0x87}, + {0x5489, 0x91}, + {0x548a, 0x9a}, + {0x548b, 0xaa}, + {0x548c, 0xb8}, + {0x548d, 0xcd}, + {0x548e, 0xdd}, + {0x548f, 0xea}, + {0x5490, 0x1d}, + {0x5580, 0x02}, + {0x5583, 0x40}, + {0x5584, 0x10}, + {0x5589, 0x10}, + {0x558a, 0x00}, + {0x558b, 0xf8}, + {0x5800, 0x23}, + {0x5801, 0x14}, + {0x5802, 0x0f}, + {0x5803, 0x0f}, + {0x5804, 0x12}, + {0x5805, 0x26}, + {0x5806, 0x0c}, + {0x5807, 0x08}, + {0x5808, 0x05}, + {0x5809, 0x05}, + {0x580a, 0x08}, + {0x580b, 0x0d}, + {0x580c, 0x08}, + {0x580d, 0x03}, + {0x580e, 0x00}, + {0x580f, 0x00}, + {0x5810, 0x03}, + {0x5811, 0x09}, + {0x5812, 0x07}, + {0x5813, 0x03}, + {0x5814, 0x00}, + {0x5815, 0x01}, + {0x5816, 0x03}, + {0x5817, 0x08}, + {0x5818, 0x0d}, + {0x5819, 0x08}, + {0x581a, 0x05}, + {0x581b, 0x06}, + {0x581c, 0x08}, + {0x581d, 0x0e}, + {0x581e, 0x29}, + {0x581f, 0x17}, + {0x5820, 0x11}, + {0x5821, 0x11}, + {0x5822, 0x15}, + {0x5823, 0x28}, + {0x5824, 0x46}, + {0x5825, 0x26}, + {0x5826, 0x08}, + {0x5827, 0x26}, + {0x5828, 0x64}, + {0x5829, 0x26}, + {0x582a, 0x24}, + {0x582b, 0x22}, + {0x582c, 0x24}, + {0x582d, 0x24}, + {0x582e, 0x06}, + {0x582f, 0x22}, + {0x5830, 0x40}, + {0x5831, 0x42}, + {0x5832, 0x24}, + {0x5833, 0x26}, + {0x5834, 0x24}, + {0x5835, 0x22}, + {0x5836, 0x22}, + {0x5837, 0x26}, + {0x5838, 0x44}, + {0x5839, 0x24}, + {0x583a, 0x26}, + {0x583b, 0x28}, + {0x583c, 0x42}, + {0x583d, 0xce}, + {0x5025, 0x00}, + {0x3a0f, 0x30}, + {0x3a10, 0x28}, + {0x3a1b, 0x30}, + {0x3a1e, 0x26}, + {0x3a11, 0x60}, + {0x3a1f, 0x14}, + {0x3008, 0x02}, +#if 1 + {0x3503, 0x00}, + {0x3c07, 0x08}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3803, 0x04}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x62}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4004, 0x02}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x3824, 0x02}, + {0x5001, 0xa3}, + +#endif + {0xFF, 0xFF} +}; + +const struct ov_reg ov5640_yuv_sxga[]= { + {0x3103, 0x11}, + {0x3008, 0x82}, + {0xFFFF, 0x05}, + {0x3008, 0x42}, + {0x3103, 0x03}, + {0x3017, 0xff}, + {0x3018, 0xff}, +#if 0 + {0x3034, 0x1a}, + {0x3035, 0x11}, + {0x3036, 0x27}, + {0x3037, 0x12}, + {0x3108, 0x01}, +#endif + + {0x3034, 0x1a}, + {0x3035, 0x11}, + {0x3036, 0x5b}, + {0x3037, 0x13}, + {0x3108, 0x01}, + {0x303d, 0x20}, + + {0x3630, 0x36}, + {0x3631, 0x0e}, + {0x3632, 0xe2}, + {0x3633, 0x12}, + {0x3621, 0xe0}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3905, 0x02}, + {0x3906, 0x10}, + {0x3901, 0x0a}, + {0x3731, 0x12}, + {0x3600, 0x08}, + {0x3601, 0x33}, + {0x302d, 0x60}, + {0x3620, 0x52}, + {0x371b, 0x20}, + {0x471c, 0x50}, + {0x3a13, 0x43}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3635, 0x13}, + {0x3636, 0x03}, + {0x3634, 0x40}, + {0x3622, 0x01}, + {0x3c01, 0x34}, + {0x3c04, 0x28}, + {0x3c05, 0x98}, + {0x3c06, 0x00}, + {0x3c07, 0x08}, + {0x3c08, 0x00}, + {0x3c09, 0x1c}, + {0x3c0a, 0x9c}, + {0x3c0b, 0x40}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x3f}, + {0x3806, 0x07}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3810, 0x00}, + {0x3811, 0x10}, + {0x3812, 0x00}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x64}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a08, 0x01}, + {0x3a09, 0x27}, + {0x3a0a, 0x00}, + {0x3a0b, 0xf6}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4001, 0x02}, + {0x4004, 0x02}, + {0x3000, 0x00}, + {0x3002, 0x1c}, + {0x3004, 0xff}, + {0x3006, 0xc3}, + {0x300e, 0x58}, + {0x302e, 0x00}, + {0x4300, 0x30}, + {0x501f, 0x00}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x440e, 0x00}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x4837, 0x22}, + {0x3824, 0x02}, + {0x5000, 0xa7}, + {0x5001, 0xa3}, + {0x5180, 0xff}, + {0x5181, 0xf2}, + {0x5182, 0x00}, + {0x5183, 0x14}, + {0x5184, 0x25}, + {0x5185, 0x24}, + {0x5186, 0x09}, + {0x5187, 0x09}, + {0x5188, 0x09}, + {0x5189, 0x75}, + {0x518a, 0x54}, + {0x518b, 0xe0}, + {0x518c, 0xb2}, + {0x518d, 0x42}, + {0x518e, 0x3d}, + {0x518f, 0x56}, + {0x5190, 0x46}, + {0x5191, 0xf8}, + {0x5192, 0x04}, + {0x5193, 0x70}, + {0x5194, 0xf0}, + {0x5195, 0xf0}, + {0x5196, 0x03}, + {0x5197, 0x01}, + {0x5198, 0x04}, + {0x5199, 0x12}, + {0x519a, 0x04}, + {0x519b, 0x00}, + {0x519c, 0x06}, + {0x519d, 0x82}, + {0x519e, 0x38}, + {0x5381, 0x1e}, + {0x5382, 0x5b}, + {0x5383, 0x08}, + {0x5384, 0x0a}, + {0x5385, 0x7e}, + {0x5386, 0x88}, + {0x5387, 0x7c}, + {0x5388, 0x6c}, + {0x5389, 0x10}, + {0x538a, 0x01}, + {0x538b, 0x98}, + {0x5300, 0x08}, + {0x5301, 0x30}, + {0x5302, 0x10}, + {0x5303, 0x00}, + {0x5304, 0x08}, + {0x5305, 0x30}, + {0x5306, 0x08}, + {0x5307, 0x16}, + {0x5309, 0x08}, + {0x530a, 0x30}, + {0x530b, 0x04}, + {0x530c, 0x06}, + {0x5480, 0x01}, + {0x5481, 0x08}, + {0x5482, 0x14}, + {0x5483, 0x28}, + {0x5484, 0x51}, + {0x5485, 0x65}, + {0x5486, 0x71}, + {0x5487, 0x7d}, + {0x5488, 0x87}, + {0x5489, 0x91}, + {0x548a, 0x9a}, + {0x548b, 0xaa}, + {0x548c, 0xb8}, + {0x548d, 0xcd}, + {0x548e, 0xdd}, + {0x548f, 0xea}, + {0x5490, 0x1d}, + {0x5580, 0x02}, + {0x5583, 0x40}, + {0x5584, 0x10}, + {0x5589, 0x10}, + {0x558a, 0x00}, + {0x558b, 0xf8}, + {0x5800, 0x23}, + {0x5801, 0x14}, + {0x5802, 0x0f}, + {0x5803, 0x0f}, + {0x5804, 0x12}, + {0x5805, 0x26}, + {0x5806, 0x0c}, + {0x5807, 0x08}, + {0x5808, 0x05}, + {0x5809, 0x05}, + {0x580a, 0x08}, + {0x580b, 0x0d}, + {0x580c, 0x08}, + {0x580d, 0x03}, + {0x580e, 0x00}, + {0x580f, 0x00}, + {0x5810, 0x03}, + {0x5811, 0x09}, + {0x5812, 0x07}, + {0x5813, 0x03}, + {0x5814, 0x00}, + {0x5815, 0x01}, + {0x5816, 0x03}, + {0x5817, 0x08}, + {0x5818, 0x0d}, + {0x5819, 0x08}, + {0x581a, 0x05}, + {0x581b, 0x06}, + {0x581c, 0x08}, + {0x581d, 0x0e}, + {0x581e, 0x29}, + {0x581f, 0x17}, + {0x5820, 0x11}, + {0x5821, 0x11}, + {0x5822, 0x15}, + {0x5823, 0x28}, + {0x5824, 0x46}, + {0x5825, 0x26}, + {0x5826, 0x08}, + {0x5827, 0x26}, + {0x5828, 0x64}, + {0x5829, 0x26}, + {0x582a, 0x24}, + {0x582b, 0x22}, + {0x582c, 0x24}, + {0x582d, 0x24}, + {0x582e, 0x06}, + {0x582f, 0x22}, + {0x5830, 0x40}, + {0x5831, 0x42}, + {0x5832, 0x24}, + {0x5833, 0x26}, + {0x5834, 0x24}, + {0x5835, 0x22}, + {0x5836, 0x22}, + {0x5837, 0x26}, + {0x5838, 0x44}, + {0x5839, 0x24}, + {0x583a, 0x26}, + {0x583b, 0x28}, + {0x583c, 0x42}, + {0x583d, 0xce}, + {0x5025, 0x00}, + {0x3a0f, 0x30}, + {0x3a10, 0x28}, + {0x3a1b, 0x30}, + {0x3a1e, 0x26}, + {0x3a11, 0x60}, + {0x3a1f, 0x14}, + {0x3008, 0x02}, + +#if 1 + {0x3503, 0x00}, + {0x3c07, 0x08}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3803, 0x04}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x62}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4004, 0x02}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x3824, 0x02}, + {0x5001, 0xa3}, +#endif + {0x3c07,0x08}, + {0x3820,0x41}, + {0x3821,0x07}, + {0x3800,0x00}, + {0x3801,0x00}, + {0x3802,0x00}, + {0x3803,0x04}, + {0x3804,0x0a}, + {0x3805,0x3f}, + {0x3806,0x07}, + {0x3807,0x9b}, + {0x3808,0x05}, + {0x3809,0x00}, + {0x380a,0x02}, + {0x380b,0xd0}, + {0x380c,0x07}, + {0x380d,0x68}, + {0x380e,0x03}, + {0x380f,0xd8}, + {0x3810,0x00}, + {0x3811,0x10}, + {0x3812,0x00}, + {0x3813,0x7e}, + {0x3814,0x31}, + {0x3815,0x31}, + {0x3618,0x00}, + {0x3612,0x29}, + {0x3709,0x52}, + {0x370c,0x03}, + {0x3a02,0x0b}, + {0x3a03,0x88}, + {0x3a14,0x0b}, + {0x3a15,0x88}, + {0x4004,0x02}, + {0x3002,0x1c}, + {0x3006,0xc3}, + {0x4713,0x03}, + {0x4407,0x04}, + {0x460b,0x35}, + {0x460c,0x20}, + {0x4837,0x22}, + {0x3824,0x02}, + {0x5001,0xa3}, + {0x3034,0x1a}, + {0x3035,0x11}, + {0x3036,0x46}, + {0x3037,0x13}, + {0x3503,0x03}, + {0xFF, 0xFF} +}; + +const struct ov_reg ov5640_afc[]= { +{0x3000 ,0x20 }, +{0x8000 ,0x02 }, +{0x8001 ,0x0f }, +{0x8002 ,0xe0 }, +{0x8003 ,0x02 }, +{0x8004 ,0x09 }, +{0x8005 ,0x28 }, +{0x8006 ,0xc2 }, +{0x8007 ,0x01 }, +{0x8008 ,0x22 }, +{0x8009 ,0x22 }, +{0x800a ,0x00 }, +{0x800b ,0x02 }, +{0x800c ,0x0d }, +{0x800d ,0xea }, +{0x800e ,0x30 }, +{0x800f ,0x01 }, +{0x8010 ,0x03 }, +{0x8011 ,0x02 }, +{0x8012 ,0x02 }, +{0x8013 ,0xa6 }, +{0x8014 ,0x30 }, +{0x8015 ,0x02 }, +{0x8016 ,0x03 }, +{0x8017 ,0x02 }, +{0x8018 ,0x02 }, +{0x8019 ,0xa6 }, +{0x801a ,0x90 }, +{0x801b ,0x51 }, +{0x801c ,0xa5 }, +{0x801d ,0xe0 }, +{0x801e ,0x78 }, +{0x801f ,0x93 }, +{0x8020 ,0xf6 }, +{0x8021 ,0xa3 }, +{0x8022 ,0xe0 }, +{0x8023 ,0x08 }, +{0x8024 ,0xf6 }, +{0x8025 ,0xa3 }, +{0x8026 ,0xe0 }, +{0x8027 ,0x08 }, +{0x8028 ,0xf6 }, +{0x8029 ,0xe5 }, +{0x802a ,0x1f }, +{0x802b ,0x70 }, +{0x802c ,0x4f }, +{0x802d ,0x75 }, +{0x802e ,0x1e }, +{0x802f ,0x20 }, +{0x8030 ,0xd2 }, +{0x8031 ,0x35 }, +{0x8032 ,0xd3 }, +{0x8033 ,0x78 }, +{0x8034 ,0x4f }, +{0x8035 ,0xe6 }, +{0x8036 ,0x94 }, +{0x8037 ,0x00 }, +{0x8038 ,0x18 }, +{0x8039 ,0xe6 }, +{0x803a ,0x94 }, +{0x803b ,0x00 }, +{0x803c ,0x40 }, +{0x803d ,0x07 }, +{0x803e ,0xe6 }, +{0x803f ,0xfe }, +{0x8040 ,0x08 }, +{0x8041 ,0xe6 }, +{0x8042 ,0xff }, +{0x8043 ,0x80 }, +{0x8044 ,0x03 }, +{0x8045 ,0x12 }, +{0x8046 ,0x0c }, +{0x8047 ,0x67 }, +{0x8048 ,0x78 }, +{0x8049 ,0x7e }, +{0x804a ,0xa6 }, +{0x804b ,0x06 }, +{0x804c ,0x08 }, +{0x804d ,0xa6 }, +{0x804e ,0x07 }, +{0x804f ,0x78 }, +{0x8050 ,0x8b }, +{0x8051 ,0xa6 }, +{0x8052 ,0x09 }, +{0x8053 ,0x18 }, +{0x8054 ,0x76 }, +{0x8055 ,0x01 }, +{0x8056 ,0x12 }, +{0x8057 ,0x0c }, +{0x8058 ,0x67 }, +{0x8059 ,0x78 }, +{0x805a ,0x4e }, +{0x805b ,0xa6 }, +{0x805c ,0x06 }, +{0x805d ,0x08 }, +{0x805e ,0xa6 }, +{0x805f ,0x07 }, +{0x8060 ,0x78 }, +{0x8061 ,0x8b }, +{0x8062 ,0xe6 }, +{0x8063 ,0x78 }, +{0x8064 ,0x6e }, +{0x8065 ,0xf6 }, +{0x8066 ,0x75 }, +{0x8067 ,0x1f }, +{0x8068 ,0x01 }, +{0x8069 ,0x78 }, +{0x806a ,0x93 }, +{0x806b ,0xe6 }, +{0x806c ,0x78 }, +{0x806d ,0x90 }, +{0x806e ,0xf6 }, +{0x806f ,0x78 }, +{0x8070 ,0x94 }, +{0x8071 ,0xe6 }, +{0x8072 ,0x78 }, +{0x8073 ,0x91 }, +{0x8074 ,0xf6 }, +{0x8075 ,0x78 }, +{0x8076 ,0x95 }, +{0x8077 ,0xe6 }, +{0x8078 ,0x78 }, +{0x8079 ,0x92 }, +{0x807a ,0xf6 }, +{0x807b ,0x22 }, +{0x807c ,0x79 }, +{0x807d ,0x90 }, +{0x807e ,0xe7 }, +{0x807f ,0xd3 }, +{0x8080 ,0x78 }, +{0x8081 ,0x93 }, +{0x8082 ,0x96 }, +{0x8083 ,0x40 }, +{0x8084 ,0x05 }, +{0x8085 ,0xe7 }, +{0x8086 ,0x96 }, +{0x8087 ,0xff }, +{0x8088 ,0x80 }, +{0x8089 ,0x08 }, +{0x808a ,0xc3 }, +{0x808b ,0x79 }, +{0x808c ,0x93 }, +{0x808d ,0xe7 }, +{0x808e ,0x78 }, +{0x808f ,0x90 }, +{0x8090 ,0x96 }, +{0x8091 ,0xff }, +{0x8092 ,0x78 }, +{0x8093 ,0x88 }, +{0x8094 ,0x76 }, +{0x8095 ,0x00 }, +{0x8096 ,0x08 }, +{0x8097 ,0xa6 }, +{0x8098 ,0x07 }, +{0x8099 ,0x79 }, +{0x809a ,0x91 }, +{0x809b ,0xe7 }, +{0x809c ,0xd3 }, +{0x809d ,0x78 }, +{0x809e ,0x94 }, +{0x809f ,0x96 }, +{0x80a0 ,0x40 }, +{0x80a1 ,0x05 }, +{0x80a2 ,0xe7 }, +{0x80a3 ,0x96 }, +{0x80a4 ,0xff }, +{0x80a5 ,0x80 }, +{0x80a6 ,0x08 }, +{0x80a7 ,0xc3 }, +{0x80a8 ,0x79 }, +{0x80a9 ,0x94 }, +{0x80aa ,0xe7 }, +{0x80ab ,0x78 }, +{0x80ac ,0x91 }, +{0x80ad ,0x96 }, +{0x80ae ,0xff }, +{0x80af ,0x12 }, +{0x80b0 ,0x0c }, +{0x80b1 ,0xb0 }, +{0x80b2 ,0x79 }, +{0x80b3 ,0x92 }, +{0x80b4 ,0xe7 }, +{0x80b5 ,0xd3 }, +{0x80b6 ,0x78 }, +{0x80b7 ,0x95 }, +{0x80b8 ,0x96 }, +{0x80b9 ,0x40 }, +{0x80ba ,0x05 }, +{0x80bb ,0xe7 }, +{0x80bc ,0x96 }, +{0x80bd ,0xff }, +{0x80be ,0x80 }, +{0x80bf ,0x08 }, +{0x80c0 ,0xc3 }, +{0x80c1 ,0x79 }, +{0x80c2 ,0x95 }, +{0x80c3 ,0xe7 }, +{0x80c4 ,0x78 }, +{0x80c5 ,0x92 }, +{0x80c6 ,0x96 }, +{0x80c7 ,0xff }, +{0x80c8 ,0x12 }, +{0x80c9 ,0x0c }, +{0x80ca ,0xb0 }, +{0x80cb ,0x12 }, +{0x80cc ,0x0c }, +{0x80cd ,0x67 }, +{0x80ce ,0x78 }, +{0x80cf ,0x8a }, +{0x80d0 ,0xe6 }, +{0x80d1 ,0x25 }, +{0x80d2 ,0xe0 }, +{0x80d3 ,0x24 }, +{0x80d4 ,0x4e }, +{0x80d5 ,0xf8 }, +{0x80d6 ,0xa6 }, +{0x80d7 ,0x06 }, +{0x80d8 ,0x08 }, +{0x80d9 ,0xa6 }, +{0x80da ,0x07 }, +{0x80db ,0x78 }, +{0x80dc ,0x8a }, +{0x80dd ,0xe6 }, +{0x80de ,0x24 }, +{0x80df ,0x6e }, +{0x80e0 ,0xf8 }, +{0x80e1 ,0xa6 }, +{0x80e2 ,0x09 }, +{0x80e3 ,0x90 }, +{0x80e4 ,0x0e }, +{0x80e5 ,0x93 }, +{0x80e6 ,0xe4 }, +{0x80e7 ,0x93 }, +{0x80e8 ,0x24 }, +{0x80e9 ,0xff }, +{0x80ea ,0xff }, +{0x80eb ,0xe4 }, +{0x80ec ,0x34 }, +{0x80ed ,0xff }, +{0x80ee ,0xfe }, +{0x80ef ,0x78 }, +{0x80f0 ,0x8a }, +{0x80f1 ,0xe6 }, +{0x80f2 ,0x24 }, +{0x80f3 ,0x01 }, +{0x80f4 ,0xfd }, +{0x80f5 ,0xe4 }, +{0x80f6 ,0x33 }, +{0x80f7 ,0xfc }, +{0x80f8 ,0xd3 }, +{0x80f9 ,0xed }, +{0x80fa ,0x9f }, +{0x80fb ,0xee }, +{0x80fc ,0x64 }, +{0x80fd ,0x80 }, +{0x80fe ,0xf8 }, +{0x80ff ,0xec }, +{0x8100 ,0x64 }, +{0x8101 ,0x80 }, +{0x8102 ,0x98 }, +{0x8103 ,0x40 }, +{0x8104 ,0x04 }, +{0x8105 ,0x7f }, +{0x8106 ,0x00 }, +{0x8107 ,0x80 }, +{0x8108 ,0x05 }, +{0x8109 ,0x78 }, +{0x810a ,0x8a }, +{0x810b ,0xe6 }, +{0x810c ,0x04 }, +{0x810d ,0xff }, +{0x810e ,0x78 }, +{0x810f ,0x8a }, +{0x8110 ,0xa6 }, +{0x8111 ,0x07 }, +{0x8112 ,0xe5 }, +{0x8113 ,0x1f }, +{0x8114 ,0xb4 }, +{0x8115 ,0x01 }, +{0x8116 ,0x0a }, +{0x8117 ,0xe6 }, +{0x8118 ,0x60 }, +{0x8119 ,0x03 }, +{0x811a ,0x02 }, +{0x811b ,0x02 }, +{0x811c ,0xa6 }, +{0x811d ,0x75 }, +{0x811e ,0x1f }, +{0x811f ,0x02 }, +{0x8120 ,0x22 }, +{0x8121 ,0x78 }, +{0x8122 ,0x4e }, +{0x8123 ,0xe6 }, +{0x8124 ,0xfe }, +{0x8125 ,0x08 }, +{0x8126 ,0xe6 }, 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+{0x8fe5 ,0xfd }, +{0x8fe6 ,0x75 }, +{0x8fe7 ,0x81 }, +{0x8fe8 ,0xcd }, +{0x8fe9 ,0x02 }, +{0x8fea ,0x0c }, +{0x8feb ,0xc4 }, +{0x8fec ,0x8f }, +{0x8fed ,0x82 }, +{0x8fee ,0x8e }, +{0x8fef ,0x83 }, +{0x8ff0 ,0x75 }, +{0x8ff1 ,0xf0 }, +{0x8ff2 ,0x04 }, +{0x8ff3 ,0xed }, +{0x8ff4 ,0x02 }, +{0x8ff5 ,0x07 }, +{0x8ff6 ,0x06 }, +{0x3022 ,0x00 }, +{0x3023 ,0x00 }, +{0x3024 ,0x00 }, +{0x3025 ,0x00 }, +{0x3026 ,0x00 }, +{0x3027 ,0x00 }, +{0x3028 ,0x00 }, +{0x3029 ,0x7F }, +{0x3000 ,0x00 }, +{0x3004, 0xff }, +{0x3005, 0xF7 }, + +{0xFF, 0xFF} +}; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov7740_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov7740_config.c new file mode 100644 index 000000000..8fac279b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov7740_config.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/* + * ID + */ + + + +/*------------------------------------------------------------------------------ + * Local Variables + *------------------------------------------------------------------------------*/ + +const struct ov_reg ov7740_yuv_vga[]= { +{0x12 ,0x80}, +//{0x11 ,0x07}, + +{0x55 ,0x40}, +{0x11 ,0x02}, + +{0x12 ,0x00}, +{0xd5 ,0x10}, +{0x0c ,0x12}, +{0x0d ,0x34}, +{0x17 ,0x25}, +{0x18 ,0xa0}, +{0x19 ,0x03}, +{0x1a ,0xf0}, +{0x1b ,0x89}, //;was 81 +{0x22 ,0x03}, //;new +{0x29 ,0x18}, //;was 17 +{0x2b ,0xf8}, +{0x2c ,0x01}, +{0x31 ,0xa0}, +{0x32 ,0xf0}, +{0x33 ,0xc4}, //;was44 +{0x35 ,0x05}, //;new +{0x36 ,0x3f}, +{0x04 ,0x60}, +{0x27 ,0x80}, //;delete "42 3a b4" +{0x3d ,0x0f}, +{0x3e ,0x80}, +{0x3f ,0x40}, +{0x40 ,0x7f}, +{0x41 ,0x6a}, +{0x42 ,0x29}, +{0x44 ,0x22}, //;was 11 +{0x45 ,0x41}, +{0x47 ,0x02}, +{0x49 ,0x64}, +{0x4a ,0xa1}, +{0x4b ,0x40}, +{0x4c ,0x1a}, +{0x4d ,0x50}, +{0x4e ,0x13}, +{0x64 ,0x00}, +{0x67 ,0x88}, +{0x68 ,0x1a}, + +{0x14 ,0x28}, //;38/28/18 for 16/8/4x gain ceiling +{0x24 ,0x3c}, +{0x25 ,0x30}, +{0x26 ,0x72}, +{0x50 ,0x97}, +{0x51 ,0x1f}, //;0fc/7e/3f/1f for 60/30/15/7.5fps, 60Hz +{0x52 ,0x00}, //;[7:6]/[5:4] 2 msb for 60/50Hz +{0x53 ,0x00}, +{0x20 ,0x00}, +{0x21 ,0xcf}, //;01/23/57/cf for 60/30/15/7.5fps +{0x50, 0x4b}, // ;12e/97/4b/25 for 60/30/15/7.5fps, 50Hz +{0x38 ,0x14}, +{0xe9 ,0x00}, +{0x56 ,0x55}, +{0x57 ,0xff}, +{0x58 ,0xff}, +{0x59 ,0xff}, +{0x5f ,0x04}, +{0xec ,0x00}, +{0x13 ,0xff}, + +{0x80 ,0x7f}, //;[6]/[5] for BPC/WPC +{0x81 ,0x3f}, +{0x82 ,0x32}, +{0x83 ,0x01}, +{0x38 ,0x11}, +{0x84 ,0x70}, +{0x85 ,0x00}, +{0x86 ,0x03}, +{0x87 ,0x01}, +{0x88 ,0x05}, +{0x89 ,0x30}, +{0x8d ,0x30}, +{0x8f ,0x85}, +{0x93 ,0x30}, +{0x95 ,0x85}, +{0x99 ,0x30}, +{0x9b ,0x85}, + +{0x9c ,0x08}, +{0x9d ,0x12}, +{0x9e ,0x23}, +{0x9f ,0x45}, +{0xa0 ,0x55}, +{0xa1 ,0x64}, +{0xa2 ,0x72}, +{0xa3 ,0x7f}, +{0xa4 ,0x8b}, +{0xa5 ,0x95}, +{0xa6 ,0xa7}, +{0xa7 ,0xb5}, +{0xa8 ,0xcb}, +{0xa9 ,0xdd}, +{0xaa ,0xec}, +{0xab ,0x1a}, + +{0xce ,0x78}, +{0xcf ,0x6e}, +{0xd0 ,0x0a}, +{0xd1 ,0x0c}, +{0xd2 ,0x84}, +{0xd3 ,0x90}, +{0xd4 ,0x1e}, + +{0x5a ,0x24}, +{0x5b ,0x1f}, +{0x5c ,0x88}, +{0x5d ,0x60}, + +{0xac ,0x6e}, +{0xbe ,0xff}, +{0xbf ,0x00}, + +{0x0f ,0x1d}, +{0x0f ,0x1f}, +{0xFF, 0xFF} +}; diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov9740_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov9740_config.c new file mode 100644 index 000000000..f2b9e85d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/ov9740_config.c @@ -0,0 +1,602 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Local Variables + *------------------------------------------------------------------------------*/ + +const struct ov_reg ov9740_yuv_vga[]= { +//@@ VGA 640x360 bin YUV DVP 60FPS (Full speed) +{0x0103,0x01}, +{0x3026,0x00}, +{0x3027,0x00}, +{0x3002,0xe8}, +{0x3004,0x03}, +{0x3005,0xff}, +{0x3703,0x42}, +{0x3704,0x10}, +{0x3705,0x45}, +{0x3603,0xaa}, +{0x3632,0x27}, +{0x3620,0x66}, +{0x3621,0xc0}, +{0x0202,0x03}, +{0x0203,0x43}, +{0x3833,0x04}, +{0x3835,0x02}, +{0x4702,0x04}, +{0x4704,0x00}, +{0x4706,0x08}, +{0x3819,0x6e}, +{0x3817,0x94}, +{0x3a18,0x00}, +{0x3a19,0x7f}, +{0x5003,0xa7}, +{0x3631,0x5e}, +{0x3633,0x50}, +{0x3630,0xd2}, +{0x3604,0x0c}, +{0x3601,0x40}, +{0x3602,0x16}, +{0x3610,0xa1}, +{0x3612,0x24}, +{0x034a,0x02}, +{0x034b,0xd3}, +{0x034c,0x02}, +{0x034d,0x80}, +{0x034e,0x01}, +{0x034f,0x68}, +{0x0202,0x01}, +{0x0203,0x9e}, +{0x381a,0x44}, +{0x3707,0x14}, +{0x3622,0x9f}, +{0x5841,0x04}, +{0x4002,0x45}, +{0x5000,0x01}, +{0x5001,0x00}, +{0x3406,0x00}, +{0x5000,0xff}, +{0x5001,0xef}, +{0x5003,0xff}, +{0x4005,0x18}, +{0x3503,0x10}, +{0x3a11,0xa0}, +{0x3a1b,0x50}, +{0x3a0f,0x50}, +{0x3a10,0x4c}, +{0x3a1e,0x4c}, +{0x3a1f,0x26}, +{0x3104,0x20}, +{0x0305,0x03}, +{0x0307,0x5f}, +{0x0303,0x01}, +{0x0301,0x0a}, +{0x3010,0x01}, +{0x300c,0x02}, +{0x0340,0x02}, +{0x0341,0x08}, +{0x0342,0x04}, +{0x0343,0xc0}, +{0x0101,0x01}, +{0x3a08,0x01}, +{0x3a09,0x38}, +{0x3a0e,0x01}, +{0x3a14,0x09}, +{0x3a15,0xc0}, +{0x3a0a,0x01}, +{0x3a0b,0x02}, +{0x3a0d,0x02}, +{0x3a02,0x10}, +{0x3a03,0x30}, +{0x3c0a,0x9c}, +{0x3c0b,0x3f}, +{0x529a,0x1 }, +{0x529b,0x2 }, +{0x529c,0x3 }, +{0x529d,0x5 }, +{0x529e,0x5 }, +{0x529f,0x28}, +{0x52a0,0x32}, +{0x52a2,0x0 }, +{0x52a3,0x2 }, +{0x52a4,0x0 }, +{0x52a5,0x4 }, +{0x52a6,0x0 }, +{0x52a7,0x8 }, +{0x52a8,0x0 }, +{0x52a9,0x10}, +{0x52aa,0x0 }, +{0x52ab,0x38}, +{0x52ac,0x0 }, +{0x52ad,0x3c}, +{0x52ae,0x0 }, +{0x52af,0x4c}, +{0x5842,0x02}, +{0x5843,0x5e}, +{0x5844,0x04}, +{0x5845,0x32}, +{0x5846,0x03}, +{0x5847,0x29}, +{0x5848,0x02}, +{0x5849,0xcc}, +{0x5800,0x22}, +{0x5801,0x1e}, +{0x5802,0x1a}, +{0x5803,0x1a}, +{0x5804,0x1f}, +{0x5805,0x26}, +{0x5806,0xe }, +{0x5807,0x9 }, +{0x5808,0x7 }, +{0x5809,0x8 }, +{0x580a,0xb }, +{0x580b,0x11}, +{0x580c,0x5 }, +{0x580d,0x2 }, +{0x580e,0x0 }, +{0x580f,0x0 }, +{0x5810,0x3 }, +{0x5811,0x7 }, +{0x5812,0x4 }, +{0x5813,0x1 }, +{0x5814,0x0 }, +{0x5815,0x0 }, +{0x5816,0x3 }, +{0x5817,0x7 }, +{0x5818,0xc }, +{0x5819,0x8 }, +{0x581a,0x6 }, +{0x581b,0x6 }, +{0x581c,0x9 }, +{0x581d,0x10}, +{0x581e,0x20}, +{0x581f,0x1b}, +{0x5820,0x17}, +{0x5821,0x18}, +{0x5822,0x1d}, +{0x5823,0x23}, +{0x5824,0x5b}, +{0x5825,0x6e}, +{0x5826,0x6e}, +{0x5827,0x7e}, +{0x5828,0xab}, +{0x5829,0x5e}, +{0x582a,0x8a}, +{0x582b,0x8a}, +{0x582c,0x8a}, +{0x582d,0x9d}, +{0x582e,0x5b}, +{0x582f,0x88}, +{0x5830,0x88}, +{0x5831,0x98}, +{0x5832,0x9a}, +{0x5833,0x4e}, +{0x5834,0x8a}, +{0x5835,0x79}, +{0x5836,0x7a}, +{0x5837,0xad}, +{0x5838,0x9b}, +{0x5839,0x9d}, +{0x583a,0xad}, +{0x583b,0x8e}, +{0x583c,0x5c}, +{0x583e,0x08}, +{0x583f,0x04}, +{0x5840,0x10}, +{0x5480,0x07}, +{0x5481,0x16}, +{0x5482,0x2c}, +{0x5483,0x4d}, +{0x5484,0x59}, +{0x5485,0x64}, +{0x5486,0x6e}, +{0x5487,0x76}, +{0x5488,0x7f}, +{0x5489,0x86}, +{0x548a,0x94}, +{0x548b,0xa3}, +{0x548c,0xba}, +{0x548d,0xd2}, +{0x548e,0xe9}, +{0x548f,0x1e}, +{0x5490,0x0f}, +{0x5491,0xff}, +{0x5492,0x0e}, +{0x5493,0x34}, +{0x5494,0x07}, +{0x5495,0x1a}, +{0x5496,0x04}, +{0x5497,0x0e}, +{0x5498,0x03}, +{0x5499,0x82}, +{0x549a,0x03}, +{0x549b,0x20}, +{0x549c,0x02}, +{0x549d,0xd7}, +{0x549e,0x02}, +{0x549f,0xa5}, +{0x54a0,0x02}, +{0x54a1,0x75}, +{0x54a2,0x02}, +{0x54a3,0x55}, +{0x54a4,0x02}, +{0x54a5,0x1c}, +{0x54a6,0x01}, +{0x54a7,0xea}, +{0x54a8,0x01}, +{0x54a9,0xae}, +{0x54aa,0x01}, +{0x54ab,0x7c}, +{0x54ac,0x01}, +{0x54ad,0x57}, +{0x5180,0xf0}, +{0x5181,0x00}, +{0x5182,0x41}, +{0x5183,0x42}, +{0x5184,0x8f}, +{0x5185,0x63}, +{0x5186,0xce}, +{0x5187,0xa8}, +{0x5188,0x17}, +{0x5189,0x1f}, +{0x518a,0x27}, +{0x518b,0x41}, +{0x518c,0x34}, +{0x518d,0xf0}, +{0x518e,0x10}, +{0x518f,0xff}, +{0x5190,0x00}, +{0x5191,0xff}, +{0x5192,0x00}, +{0x5193,0xff}, +{0x5194,0x00}, +{0x5380,0x1 }, +{0x5381,0x0 }, +{0x5382,0x0 }, +{0x5383,0x17}, +{0x5384,0x0 }, +{0x5385,0x1 }, +{0x5386,0x0 }, +{0x5387,0x0 }, +{0x5388,0x0 }, +{0x5389,0xad}, +{0x538a,0x0 }, +{0x538b,0x11}, +{0x538c,0x0 }, +{0x538d,0x0 }, +{0x538e,0x0 }, +{0x538f,0x7 }, +{0x5390,0x0 }, +{0x5391,0x80}, +{0x5392,0x0 }, +{0x5393,0xa0}, +{0x5394,0x18}, +{0x3c0a,0x9c}, +{0x3c0b,0x3f}, +{0x5501,0x14}, +{0x5502,0x00}, +{0x5503,0x40}, +{0x5504,0x00}, +{0x5505,0x80}, +{0x0100,0x01}, +{0xFF, 0xFF} +}; + + + +const struct ov_reg ov9740_yuv_sxga[]= { +//@@ WXGA 1280x720 YUV DVP 15FPS for card reader +{0x0103, 0x01}, +{0x3026, 0x00}, +{0x3027, 0x00}, +{0x3002, 0xe8}, +{0x3004, 0x03}, +{0x3005, 0xff}, +{0x3406, 0x00}, +{0x3603, 0xaa}, +{0x3632, 0x27}, +{0x3620, 0x66}, +{0x3621, 0xc0}, +{0x3631, 0x5e}, +{0x3633, 0x50}, +{0x3630, 0xd2}, +{0x3604, 0x0c}, +{0x3601, 0x40}, +{0x3602, 0x16}, +{0x3610, 0xa1}, +{0x3612, 0x24}, +{0x3622, 0x9f}, +{0x3703, 0x42}, +{0x3704, 0x10}, +{0x3705, 0x45}, +{0x3707, 0x14}, +{0x3833, 0x04}, +{0x3835, 0x03}, +{0x3819, 0x6e}, +{0x3817, 0x94}, +{0x3503, 0x10}, +{0x3a18, 0x00}, +{0x3a19, 0x7f}, +{0x3a11, 0xa0}, +{0x3a1a, 0x05}, +{0x3a1b, 0x50}, +{0x3a0f, 0x50}, +{0x3a10, 0x4c}, +{0x3a1e, 0x4c}, +{0x3a1f, 0x26}, +{0x4002, 0x45}, +{0x4005, 0x18}, +{0x4702, 0x04}, +{0x4704, 0x00}, +{0x4706, 0x08}, +{0x5000, 0xff}, +{0x5001, 0xef}, +{0x5003, 0xff}, + +{0x3104,0x20}, +{0x0305,0x03}, +{0x0307,0x70}, +{0x0303,0x01}, +{0x0301,0x0a}, +{0x3010,0x01}, +{0x300c,0x02}, + +{0x0340, 0x03}, +{0x0341, 0x07}, +{0x0342, 0x06}, +{0x0343, 0x62}, +{0x034b, 0xd1}, +{0x034c, 0x05}, +{0x034d, 0x00}, +{0x034e, 0x02}, +{0x034f, 0xd0}, +{0x0101, 0x01}, +{0x3a08, 0x00}, +{0x3a09, 0xe8}, +{0x3a0e, 0x03}, +{0x3a14, 0x15}, +{0x3a15, 0xc6}, +{0x3a0a, 0x00}, +{0x3a0b, 0xc0}, +{0x3a0d, 0x04}, +{0x3a02, 0x18}, +{0x3a03, 0x20}, +{0x3c0a, 0x9c}, +{0x3c0b, 0x3f}, +{0x529a, 0x1 }, +{0x529b, 0x2 }, +{0x529c, 0x3 }, +{0x529d, 0x5 }, +{0x529e, 0x5 }, +{0x529f, 0x28}, +{0x52a0, 0x32}, +{0x52a2, 0x0 }, +{0x52a3, 0x2 }, +{0x52a4, 0x0 }, +{0x52a5, 0x4 }, +{0x52a6, 0x0 }, +{0x52a7, 0x8 }, +{0x52a8, 0x0 }, +{0x52a9, 0x10}, +{0x52aa, 0x0 }, +{0x52ab, 0x38}, +{0x52ac, 0x0 }, +{0x52ad, 0x3c}, +{0x52ae, 0x0 }, +{0x52af, 0x4c}, +{0x5842, 0x02}, +{0x5843, 0x5e}, +{0x5844, 0x04}, +{0x5845, 0x32}, +{0x5846, 0x03}, +{0x5847, 0x29}, +{0x5848, 0x02}, +{0x5849, 0xcc}, +{0x5800, 0x22}, +{0x5801, 0x1e}, +{0x5802, 0x1a}, +{0x5803, 0x1a}, +{0x5804, 0x1f}, +{0x5805, 0x26}, +{0x5806, 0xe }, +{0x5807, 0x9 }, +{0x5808, 0x7 }, +{0x5809, 0x8 }, +{0x580a, 0xb }, +{0x580b, 0x11}, +{0x580c, 0x5 }, +{0x580d, 0x2 }, +{0x580e, 0x0 }, +{0x580f, 0x0 }, +{0x5810, 0x3 }, +{0x5811, 0x7 }, +{0x5812, 0x4 }, +{0x5813, 0x1 }, +{0x5814, 0x0 }, +{0x5815, 0x0 }, +{0x5816, 0x3 }, +{0x5817, 0x7 }, +{0x5818, 0xc }, +{0x5819, 0x8 }, +{0x581a, 0x6 }, +{0x581b, 0x6 }, +{0x581c, 0x9 }, +{0x581d, 0x10}, +{0x581e, 0x20}, +{0x581f, 0x1b}, +{0x5820, 0x17}, +{0x5821, 0x18}, +{0x5822, 0x1d}, +{0x5823, 0x23}, +{0x5824, 0x5b}, +{0x5825, 0x6e}, +{0x5826, 0x6e}, +{0x5827, 0x7e}, +{0x5828, 0xab}, +{0x5829, 0x5e}, +{0x582a, 0x8a}, +{0x582b, 0x8a}, +{0x582c, 0x8a}, +{0x582d, 0x9d}, +{0x582e, 0x5b}, +{0x582f, 0x88}, +{0x5830, 0x88}, +{0x5831, 0x98}, +{0x5832, 0x9a}, +{0x5833, 0x4e}, +{0x5834, 0x8a}, +{0x5835, 0x79}, +{0x5836, 0x7a}, +{0x5837, 0xad}, +{0x5838, 0x9b}, +{0x5839, 0x9d}, +{0x583a, 0xad}, +{0x583b, 0x8e}, +{0x583c, 0x5c}, +{0x583e, 0x08}, +{0x583f, 0x04}, +{0x5840, 0x10}, +{0x5480, 0x07}, +{0x5481, 0x16}, +{0x5482, 0x2c}, +{0x5483, 0x4d}, +{0x5484, 0x59}, +{0x5485, 0x64}, +{0x5486, 0x6e}, +{0x5487, 0x76}, +{0x5488, 0x7f}, +{0x5489, 0x86}, +{0x548a, 0x94}, +{0x548b, 0xa3}, +{0x548c, 0xba}, +{0x548d, 0xd2}, +{0x548e, 0xe9}, +{0x548f, 0x1e}, +{0x5490, 0x0f}, +{0x5491, 0xff}, +{0x5492, 0x0e}, +{0x5493, 0x34}, +{0x5494, 0x07}, +{0x5495, 0x1a}, +{0x5496, 0x04}, +{0x5497, 0x0e}, +{0x5498, 0x03}, +{0x5499, 0x82}, +{0x549a, 0x03}, +{0x549b, 0x20}, +{0x549c, 0x02}, +{0x549d, 0xd7}, +{0x549e, 0x02}, +{0x549f, 0xa5}, +{0x54a0, 0x02}, +{0x54a1, 0x75}, +{0x54a2, 0x02}, +{0x54a3, 0x55}, +{0x54a4, 0x02}, +{0x54a5, 0x1c}, +{0x54a6, 0x01}, +{0x54a7, 0xea}, +{0x54a8, 0x01}, +{0x54a9, 0xae}, +{0x54aa, 0x01}, +{0x54ab, 0x7c}, +{0x54ac, 0x01}, +{0x54ad, 0x57}, +{0x5180, 0xf0}, +{0x5181, 0x00}, +{0x5182, 0x41}, +{0x5183, 0x42}, +{0x5184, 0x8f}, +{0x5185, 0x63}, +{0x5186, 0xce}, +{0x5187, 0xa8}, +{0x5188, 0x17}, +{0x5189, 0x1f}, +{0x518a, 0x27}, +{0x518b, 0x41}, +{0x518c, 0x34}, +{0x518d, 0xf0}, +{0x518e, 0x10}, +{0x518f, 0xff}, +{0x5190, 0x00}, +{0x5191, 0xff}, +{0x5192, 0x00}, +{0x5193, 0xff}, +{0x5194, 0x00}, +{0x5380, 0x1 }, +{0x5381, 0x0 }, +{0x5382, 0x0 }, +{0x5383, 0x17}, +{0x5384, 0x0 }, +{0x5385, 0x1 }, +{0x5386, 0x0 }, +{0x5387, 0x0 }, +{0x5388, 0x0 }, +{0x5389, 0xad}, +{0x538a, 0x0 }, +{0x538b, 0x11}, +{0x538c, 0x0 }, +{0x538d, 0x0 }, +{0x538e, 0x0 }, +{0x538f, 0x7 }, +{0x5390, 0x0 }, +{0x5391, 0x80}, +{0x5392, 0x0 }, +{0x5393, 0xa0}, +{0x5394, 0x18}, +{0x3c0a, 0x9c}, +{0x3c0b, 0x3f}, +{0x5501, 0x14}, +{0x5502, 0x00}, +{0x5503, 0x40}, +{0x5504, 0x00}, +{0x5505, 0x80}, +{0x5308, 0x40}, +{0x5309, 0x60}, +{0x3a11, 0xd0}, +{0x3a1b, 0x78}, +{0x3a0f, 0x78}, +{0x3a10, 0x68}, +{0x3a1e, 0x68}, +{0x3a1f, 0x40}, +{0x0100, 0x01}, +{0xFF, 0xFF} +}; + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/qt1070.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/qt1070.c new file mode 100644 index 000000000..c9ff9d1fa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/qt1070.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Implementation QT1070 driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Read one byte of data from QT1070 Register. + * + * \param pTwid Pointer to twi driver structure. + * \param regAddr Register address to read. + * \return value in the given register. + */ +static uint8_t QT1070_ReadReg(Twid *pTwid, uint8_t regAddr) +{ + uint8_t data; + TWID_Write(pTwid, QT1070_SLAVE_ADDRESS, 0, 0, ®Addr, 1, 0); + TWID_Read(pTwid, QT1070_SLAVE_ADDRESS, 0, 0, &data, 1, 0); + return data; +} + +/** + * \brief Write one byte of data to QT1070 Register. + * + * \param pTwid Pointer to twi driver structure. + * \param regAddr Register address to write. + * \param data Data to write. + */ +static void QT1070_WriteReg(Twid *pTwid, uint32_t regAddr, uint8_t data) +{ + TWID_Write(pTwid, QT1070_SLAVE_ADDRESS, regAddr, 1, &data, 1, 0); +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Get qt1070 chip ID. + * + * \param pTwid Pointer to twi driver structure. + * \return Chip Id + */ + +uint8_t QT1070_GetChipId(Twid *pTwid) +{ + return QT1070_ReadReg( pTwid, QT1070_CHIP_ID); +} + +/** + * \brief Get qt1070 firmware version number. + * + * \param pTwid Pointer to twi driver structure. + * \return Firmware version number. + */ + +uint8_t QT1070_GetFirmwareVersion(Twid *pTwid) +{ + return QT1070_ReadReg( pTwid, QT1070_REG_FIRMWARE_VERSION); +} + + /** + * \brief Get qt1070 detection status. + * + * \param pTwid Pointer to twi driver structure. + * \return Dectection status. + */ + +uint8_t QT1070_GetDetection_Status(Twid *pTwid) +{ + return QT1070_ReadReg( pTwid, QT1070_REG_DETECTION_STATUS); +} + +/** + * \brief Get qt1070 Key status. + * + * \param pTwid Pointer to twi driver structure. + * \return Key status. + */ +uint8_t QT1070_GetKey_Status(Twid *pTwid) +{ + return QT1070_ReadReg( pTwid, QT1070_REG_KEY_STATUS); +} + +/** + * \brief Get qt1070 key signal value in the given Key. These are the key's + * of 16-bit key signals which are accessed as two 8-bit bytes,stored MSB first + * + * \param pTwid Pointer to twi driver structure. + * \param key Key index. + * \return Key signal value. + */ +uint16_t QT1070_GetKey_Signal(Twid *pTwid, uint8_t key) +{ + uint8_t data[2]; + data[0] = QT1070_ReadReg( pTwid, QT1070_REG_KEY0_SIGNAL_MSB + key * 2); + data[1] = QT1070_ReadReg( pTwid, QT1070_REG_KEY0_SIGNAL_LSB + key * 2); + return (data[0] << 8) | data[1]; +} + +/** + * \brief Get qt1070 key reference data in the given Key. These are the key's + * of 16-bit key reference data which are accessed as two 8-bit bytes, stored MSB first + * + * \param pTwid Pointer to twi driver structure. + * \param key Key index. + * \return Key reference data. + */ +uint16_t QT1070_GetKey_Reference(Twid *pTwid, uint8_t key) +{ + uint8_t data[2]; + data[0] = QT1070_ReadReg( pTwid, QT1070_REG_REFDATA0_MSB + key * 2); + data[1] = QT1070_ReadReg( pTwid, QT1070_REG_REFDATA0_LSB + key * 2); + return (data[0] << 8) | data[1]; +} + +/** + * \brief Set the threshold value for the given Key. + * + * \param pTwid Pointer to twi driver structure. + * \param key Key index. + * \param threshold Threshold value. + */ +void QT1070_SetThreshold(Twid *pTwid, uint8_t key, uint8_t threshold) +{ + // Do not use a setting of 0 as this causes a key to go into detection + // when its signal is equal to its reference. + if ( threshold ) + { + QT1070_WriteReg(pTwid, QT1070_REG_NTHR_KEY0 + key, threshold); + } +} + +/** + * \brief Set Averaging factor and adjacent key suppression for the given Key. + * + * \param pTwid Pointer to twi driver structure. + * \param key Key index. + * \param Ave Averaging factor. + * \param Aks AKS group index. + */ +void QT1070_SetAveAks(Twid *pTwid, uint8_t key, uint8_t Ave, uint8_t Aks) +{ + QT1070_WriteReg(pTwid, QT1070_REG_AVEAKS_KEY0 + key, (Ave << 3) | Aks ); +} + +/** + * \brief Set DI level for the given Key. This 8-bit value controls the number + * of consecutive measurement that must be confirmed as having passed the key threshold + * before that key is registered as being in detect. + * + * \param pTwid Pointer to twi driver structure. + * \param key Key index. + * \param di DI level. + */ + +void QT1070_SetDetectionIntegrator(Twid *pTwid, uint8_t key, uint8_t di) +{ + QT1070_WriteReg(pTwid, QT1070_REG_DI_KEY0 + key, di); +} + +/** + * \brief Start a calibration cycle, the CALIBTATE flag in the detection status + * register is set when the calibration begins and clears when the calibration + * has finished. + * + * \param pTwid Pointer to twi driver structure. + */ + +void QT1070_StartCalibrate(Twid *pTwid) +{ + QT1070_WriteReg(pTwid, QT1070_REG_CALIRATE , 1); +} + +/** + * \brief Reset the qt1070 device. + * + * \param pTwid Pointer to twi driver structure. + */ + +void QT1070_StartReset(Twid *pTwid) +{ + QT1070_WriteReg(pTwid, QT1070_REG_RESET , 1); +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/rand.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/rand.c new file mode 100644 index 000000000..dcde75125 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/rand.c @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*------------------------------------------------------------------------------ + * Header + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Global Variables + *------------------------------------------------------------------------------*/ + +static uint32_t _dwRandNext=1 ; + +/*------------------------------------------------------------------------------ + * Exported Functions + *------------------------------------------------------------------------------*/ + +/** + * Initialize the seed for rand generator. + * + * \param seed rand initiation seed + */ +extern void srand( uint32_t dwSeed ) +{ + _dwRandNext = dwSeed ; +} + +/** + * Return a random number, maxinum assumed to be 65536 + */ +extern uint32_t rand( void ) +{ + _dwRandNext = _dwRandNext * 1103515245 + 12345 ; + + return (uint32_t)(_dwRandNext/131072) % 65536 ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/timetick.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/timetick.c new file mode 100644 index 000000000..82a304f29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/timetick.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * Implement simple PIT usage as system tick. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Tick Counter united by ms */ +static volatile uint32_t _dwTickCount = 0 ; + +/*---------------------------------------------------------------------------- + * Exported Functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Handler for Sytem Tick interrupt. + */ +extern void TimeTick_Increment( uint32_t dwInc ) +{ + _dwTickCount += dwInc; +} + +/** + * \brief Configures the PIT & reset tickCount. + * Systick interrupt handler will generates 1ms interrupt and increase a + * tickCount. + * \note IRQ handler must be configured before invoking this function. + * \note PIT is enabled automatically in this function. + * \param new_mck Current master clock. + */ +extern uint32_t TimeTick_Configure( uint32_t new_mck ) +{ + _dwTickCount = 0 ; + PIT_Init( 1000, new_mck / 1000000 ); + PIT_EnableIT(); + PIT_Enable(); + return 0; +} + +/** + * Get Delayed number of tick + * \param startTick Start tick point. + * \param endTick End tick point. + */ +extern uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick) +{ + if (endTick >= startTick) return (endTick - startTick); + return (endTick + (0xFFFFFFFF - startTick) + 1); +} + +/** + * \brief Get current Tick Count, in ms. + */ +extern uint32_t GetTickCount( void ) +{ + return _dwTickCount ; +} + +/** + * \brief Sync Wait for several ms + */ +extern void Wait( volatile uint32_t dwMs ) +{ + uint32_t dwStart ; + uint32_t dwCurrent ; + + dwStart = _dwTickCount ; + do + { + dwCurrent = _dwTickCount ; + } while ( dwCurrent - dwStart < dwMs ) ; +} + +/** + * \brief Sync Sleep for several ms + */ +extern void Sleep( volatile uint32_t dwMs ) +{ + uint32_t dwStart ; + uint32_t dwCurrent ; + __ASM("CPSIE I"); + dwStart = _dwTickCount ; + + do + { + dwCurrent = _dwTickCount ; + + if ( dwCurrent - dwStart > dwMs ) + { + break ; + } + __ASM("WFI"); + } while( 1 ) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/trace.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/trace.c new file mode 100644 index 000000000..455a7a448 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/trace.c @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Internal variables + *------------------------------------------------------------------------------*/ + +/** Trace level can be set at applet initialization */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + uint32_t dwTraceLevel = TRACE_LEVEL ; +#endif + +/** + * Initializes the DBGU Console + * + * \param dwBaudRate U(S)ART baudrate. + * \param dwMCk Master clock frequency. + */ +extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) +{ + const Pin pinsDBUG[] = { PINS_DBGU } ; + + PIO_Configure( pinsDBUG, PIO_LISTSIZE( pinsDBUG ) ) ; + + DBGU_Configure( dwBaudRate, dwMCk ) ; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/tsd_com.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/tsd_com.c new file mode 100644 index 000000000..43e3bab8f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/tsd_com.c @@ -0,0 +1,384 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +/** \addtogroup tsd_module + *@{ + */ + + +#include +#include + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/** Size in pixels of calibration points. */ +#define POINTS_SIZE 4 +/** Maximum difference in pixels between the test point and the measured point. + */ +#define POINTS_MAX_XERROR 10 +/** Maximum difference in pixels between the test point and the measured point. + */ +#define POINTS_MAX_YERROR 8 + +/** Delay at the end of calibartion for result display (positive or negative) */ +#define DELAY_RESULT_DISPLAY 4000000 + +/** Clear Strings on LCD */ +#if 1 +#define CLEAR_STRING() LCDD_Fill(COLOR_WHITE) +#else +#define CLEAR_STRING() \ + LCDD_DrawFilledRectangle(strX - 3*strW, strY, \ + strX + 20*strW, strY + 6*strH, COLOR_WHITE) +#endif + +/*---------------------------------------------------------------------------- + * Local types + *----------------------------------------------------------------------------*/ + +/** + * Point used during the touchscreen calibration process. + */ +typedef struct _CalibrationPoint { + + /** Coordinate of point along the X-axis of the screen. */ + uint32_t x; + /** Coordinate of point along the Y-axis of the screen. */ + uint32_t y; + /** Calibration data of point. */ + uint32_t data[2]; + +} CalibrationPoint; + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Calibration display title */ +static const char* strTitle = "LCD Calibration"; + +/** indicates if the touch screen has been calibrated. + If not, Callback functions are not called */ +static volatile uint8_t bCalibrationOk = 0; +/** Slope for interpoling touchscreen measurements along the X-axis. */ +static int32_t xSlope; +/** Slope for interpoling touchscreen measurements along the Y-axis. */ +static int32_t ySlope; + +/** Calibration points */ +static CalibrationPoint calibrationPoints[] = { + + /* Top-left corner calibration point */ + { + BOARD_LCD_WIDTH / 10, + BOARD_LCD_HEIGHT / 10, + {0, 0} + }, + /* Top-right corner calibration point */ + { + BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10, + BOARD_LCD_HEIGHT / 10, + {0, 0} + }, + /* Bottom-right corner calibration point */ + { + BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10, + BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10, + {0, 0} + }, + /* Bottom-left corner calibration point */ + { + BOARD_LCD_WIDTH / 10, + BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10, + {0, 0} + } +}; + +/** Test point */ +static const CalibrationPoint testPoint = { + BOARD_LCD_WIDTH / 2, + BOARD_LCD_HEIGHT / 2, + {0, 0} +}; + +/*---------------------------------------------------------------------------- + * External functions + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * Display a calibration point on the given buffer. + * \param pPoint Calibration point to display. + */ +static void DrawCalibrationPoint( + const CalibrationPoint *pPoint) +{ + LCDD_DrawFilledRectangle(pPoint->x - POINTS_SIZE / 2, + pPoint->y - POINTS_SIZE / 2, + pPoint->x + POINTS_SIZE, + pPoint->y + POINTS_SIZE, + COLOR_RED); +} + +/** + * Clears a calibration point from the given buffer. + * \param pLcdBuffer LCD buffer to draw on. + * \param pPoint Calibration point to clear. + */ +static void ClearCalibrationPoint( + const CalibrationPoint *pPoint) +{ + LCDD_DrawFilledRectangle(pPoint->x - POINTS_SIZE, + pPoint->y - POINTS_SIZE, + pPoint->x + POINTS_SIZE, + pPoint->y + POINTS_SIZE, + COLOR_WHITE); +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Indicates if the calibration of the touch screen is Ok + * \return 1 calibration Ok, 0 if not + */ +uint8_t TSDCom_IsCalibrationOk(void) +{ + return bCalibrationOk; +} + +/** + * Interpolates the provided raw measurements using the previously calculated + * slope. The resulting x and y coordinates are stored in an array. + * \param pData Raw measurement data, as returned by TSD_GetRawMeasurement(). + * \param pPoint Array in which x and y will be stored. + */ +void TSDCom_InterpolateMeasurement(const uint32_t *pData, uint32_t *pPoint) +{ + pPoint[0] = calibrationPoints[0].x + - (((int32_t) calibrationPoints[0].data[0] - (int32_t) pData[0]) * 1024) + / xSlope; + + pPoint[1] = calibrationPoints[0].y + - (((int32_t) calibrationPoints[0].data[1] - (int32_t) pData[1]) * 1024) + / ySlope; + /* Is pPoint[0] negative ? */ + if(pPoint[0] & 0x80000000) pPoint[0] = 0; + /* Is pPoint[0] bigger than the LCD width ? */ + if(pPoint[0] > BOARD_LCD_WIDTH) pPoint[0] = BOARD_LCD_WIDTH; + /* Is pPoint[1] negative ? */ + if(pPoint[1] & 0x80000000) pPoint[1] = 0; + /* Is pPoint[1] bigger than the LCD width ? */ + if(pPoint[1] > BOARD_LCD_HEIGHT) pPoint[1] = BOARD_LCD_HEIGHT; +} + +/** + * Performs the calibration process using the provided buffer to display + * information. + * \param pLcdBuffer LCD buffer to display. + * \return True if calibration was successful; otherwise false. + */ +uint8_t TSDCom_Calibrate(void) +{ + uint32_t i; // to keep the tempo with gcc code optimisation + int32_t slope1, slope2; + CalibrationPoint measuredPoint; + uint8_t xOk, yOk; + int32_t xDiff, yDiff; + uint32_t strX = BOARD_LCD_WIDTH / 2 - 75, strY = 60; + uint32_t strW, strH; + + LCDD_GetStringSize("P", &strW, &strH); + /* Calibration setup */ + LCDD_Fill(COLOR_WHITE); + LCDD_Flush_CurrentCanvas(); + LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK); + LCDD_Flush_CurrentCanvas(); + LCDD_DrawString(strX - 2*strW, strY + 3*strH, + " Touch the dots to\ncalibrate the screen", COLOR_DARKBLUE); + LCDD_Flush_CurrentCanvas(); + /* Calibration points */ + for (i = 0; i < 4; i++) { + + DrawCalibrationPoint(&calibrationPoints[i]); + LCDD_Flush_CurrentCanvas(); + /* Wait for touch & end of conversion */ + TSD_WaitPenPressed(); + TSD_GetRawMeasurement(calibrationPoints[i].data); + ClearCalibrationPoint(&calibrationPoints[i]); + LCDD_Flush_CurrentCanvas(); + /* Wait for contact loss */ + TSD_WaitPenReleased(); + printf("P%d: (%d,%d)\n\r", (unsigned int)i, (unsigned int)calibrationPoints[i].data[0], (unsigned int)calibrationPoints[i].data[1]); + } + + /* Calculate slopes using the calibration data + * Theory behind those calculations: + * - We suppose the touchscreen measurements are linear, so the following equations are true (simple + * linear regression) for any two 'a' and 'b' points of the screen: + * dx = (a.data[0] - b.data[0]) / (a.x - b.x) + * dy = (a.data[1] - b.data[1]) / (a.y - b.y) + * + * - We calculate dx and dy (called xslope and yslope here) using the calibration points. + * + * - We can then use dx and dy to infer the position of a point 'p' given the measurements performed + * by the touchscreen ('c' is any of the calibration points): + * dx = (p.data[0] - c.data[0]) / (p.x - c.x) + * dy = (p.data[1] - c.data[1]) / (p.y - c.y) + * Thus: + * p.x = c.x - (p.data[0] - c.data[0]) / dx + * p.y = c.y - (p.data[1] - c.data[1]) / dy + * + * - Since there are four calibration points, dx and dy can be calculated twice, so we average + * the two values. + */ + slope1 = ((int32_t) calibrationPoints[0].data[0]) - ((int32_t) calibrationPoints[1].data[0]); + slope1 *= 1024; + slope1 /= ((int32_t) calibrationPoints[0].x) - ((int32_t) calibrationPoints[1].x); + slope2 = ((int32_t) calibrationPoints[2].data[0]) - ((int32_t) calibrationPoints[3].data[0]); + slope2 *= 1024; + slope2 /= ((int32_t) calibrationPoints[2].x) - ((int32_t) calibrationPoints[3].x); + xSlope = (slope1 + slope2) / 2; + + slope1 = ((int32_t) calibrationPoints[0].data[1]) - ((int32_t) calibrationPoints[2].data[1]); + slope1 *= 1024; + slope1 /= ((int32_t) calibrationPoints[0].y) - ((int32_t) calibrationPoints[2].y); + slope2 = ((int32_t) calibrationPoints[1].data[1]) - ((int32_t) calibrationPoints[3].data[1]); + slope2 *= 1024; + slope2 /= ((int32_t) calibrationPoints[1].y) - ((int32_t) calibrationPoints[3].y); + ySlope = (slope1 + slope2) / 2; + + printf("Slope: %d, %d\n\r", (unsigned int)xSlope, (unsigned int)ySlope); + + /* Test point */ + CLEAR_STRING(); + LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK); + LCDD_DrawString(strX - 2*strW, strY + 3*strH, + " Touch the point to\nvalidate calibration", COLOR_DARKBLUE); + LCDD_Flush_CurrentCanvas(); + DrawCalibrationPoint(&testPoint); + LCDD_Flush_CurrentCanvas(); + /* Wait for touch & end of conversion */ + TSD_WaitPenPressed(); + + TSD_GetRawMeasurement(measuredPoint.data); + TSDCom_InterpolateMeasurement(measuredPoint.data, (uint32_t *) &measuredPoint); + DrawCalibrationPoint(&measuredPoint); + LCDD_Flush_CurrentCanvas(); + /* Check resulting x and y */ + xDiff = (int32_t) measuredPoint.x - (int32_t) testPoint.x; + yDiff = (int32_t) measuredPoint.y - (int32_t) testPoint.y; + xOk = (xDiff >= -POINTS_MAX_XERROR) && (xDiff <= POINTS_MAX_XERROR); + yOk = (yDiff >= -POINTS_MAX_YERROR) && (yDiff <= POINTS_MAX_YERROR); + + /* Wait for contact loss */ + TSD_WaitPenReleased(); + + printf("TP: %d, %d -> %d, %d\n\r", + (unsigned int)measuredPoint.data[0], (unsigned int)measuredPoint.data[1], + (unsigned int)measuredPoint.x, (unsigned int)measuredPoint.y); + + /* Check calibration result */ + if (xOk && yOk) { + + bCalibrationOk = 1; + CLEAR_STRING(); + LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK); + LCDD_DrawString(strX + 3*strW, strY + 2*strH, "Success !", COLOR_GREEN); + LCDD_Flush_CurrentCanvas(); + } + else { + + bCalibrationOk = 0; + CLEAR_STRING(); + LCDD_DrawString(strX, strY, strTitle, COLOR_BLACK); + LCDD_DrawString(strX + strW, strY + 2*strH, "Error too big", COLOR_RED); + LCDD_Flush_CurrentCanvas(); + TRACE_WARNING("X %u, Y %u; Diff %d, %d\n\r", + (unsigned int)(measuredPoint.x), (unsigned int)(measuredPoint.y), (unsigned int)xDiff, (unsigned int)yDiff); + } + + /* Slight delay */ + for (i = 0; i < DELAY_RESULT_DISPLAY; i++); + LCDD_Flush_CurrentCanvas(); + return (xOk && yOk); +} + +/** + * Read calibrate data to buffer. + * \param pBuffer Data buffer. + * \param size Size of data buffer in bytes. + */ +void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size) +{ + uint8_t *pDest = (uint8_t *)pBuffer; + + memcpy(pDest, (void const *)&bCalibrationOk, sizeof(bCalibrationOk)); + pDest += sizeof(bCalibrationOk); + memcpy(pDest, &xSlope, sizeof(xSlope)); + pDest += sizeof(xSlope); + memcpy(pDest, &ySlope, sizeof(ySlope)); + pDest += sizeof(ySlope); + memcpy(pDest, &calibrationPoints[0].data, sizeof(calibrationPoints[0].data)); + pDest += sizeof(calibrationPoints[0].data); +} + +/** + * Restore calibrate data with buffer data. + * \param pBuffer Data buffer. + * \param size Size of data buffer in bytes. + */ +void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size) +{ + uint8_t *pSrc = (uint8_t *)pBuffer; + + memcpy((void *)&bCalibrationOk, pSrc, sizeof(bCalibrationOk)); + pSrc += sizeof(bCalibrationOk); + memcpy(&xSlope, pSrc, sizeof(xSlope)); + pSrc += sizeof(xSlope); + memcpy(&ySlope, pSrc, sizeof(ySlope)); + pSrc += sizeof(ySlope); + memcpy(&calibrationPoints[0].data, pSrc, sizeof(calibrationPoints[0].data)); + pSrc += sizeof(calibrationPoints[0].data); +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/tsd_tsadc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/tsd_tsadc.c new file mode 100644 index 000000000..0cc925666 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/tsd_tsadc.c @@ -0,0 +1,378 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +#include + +#ifdef REG_ADC_TSMR +/** \addtogroup tsd_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/** SWAP X & Y */ +#define TS_XY_SWAP + +/** Status that used for touchscreen */ +#define TS_STATUSES ( ADC_ISR_PENS | ADC_ISR_PEN | ADC_ISR_NOPEN \ + | ADC_ISR_XRDY | ADC_ISR_YRDY | ADC_ISR_PRDY ) + +/*---------------------------------------------------------------------------- + * Local types + *----------------------------------------------------------------------------*/ + +/** X value is ready */ +#define TS_X_RDY (1 << 0) +/** Y value is ready */ +#define TS_Y_RDY (1 << 1) +/** Pressure value is ready */ +#define TS_P_RDY (1 << 2) +/** Pen status */ +#define TS_PEN_STAT (1 << 7) +/** All data is ready (X,Y & P) */ +#define TS_DATA_RDY (TS_X_RDY|TS_Y_RDY|TS_P_RDY) + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Raw register value */ +static uint32_t dwRaw[3]; +/** Touchscreen data sampling results */ +static uint32_t dwTsData[3]; +/** Last Touchscreen sampling results */ +static uint32_t dwLastTsData[3]; +/** Touchscreen data ready */ +static uint8_t bTsFlags = 0; + +/*---------------------------------------------------------------------------- + * External functions + *----------------------------------------------------------------------------*/ + +extern uint32_t TSD_GetRaw(uint32_t i); + +/** + * Return raw register value. + */ +uint32_t TSD_GetRaw(uint32_t i) +{ + return dwRaw[i]; +} + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/** + * Interrupt handler for the TouchScreen. + * Handles pen press, pen move and pen release events + * by invoking three callback functions. + */ +void TSD_Handler(uint32_t dwAdcStatus) +{ + Adc *pAdc = ADC; + + uint32_t status; + + /* TSADC status */ + status = dwAdcStatus; + status &= /*ADC_GetItMask(pAdc) &*/ TS_STATUSES; + if (status == 0) return; + + /* Pen released */ + if (status & ADC_ISR_NOPEN) + { + if ((bTsFlags & TS_PEN_STAT) == 0) + { + /* Register last data */ + memcpy(dwLastTsData, dwTsData, sizeof(dwTsData)); + /* Invoke PenReleased callback */ + if (TSDCom_IsCalibrationOk()) + TSD_PenReleased(dwTsData[0], dwTsData[1]); + } + bTsFlags = 0; + /* Stop periodic trigger & enable pen */ + ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER); + ADC_SetTsDebounce(pAdc, BOARD_TOUCHSCREEN_DEBOUNCE); + ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG); + /* Disable pen release detect */ + ADC_DisableIt(pAdc, ADC_IDR_NOPEN); + /* Enable pen press detect */ + ADC_EnableIt(pAdc, ADC_IER_PEN); + } + /* Pen pressed */ + else if (status & ADC_ISR_PEN) + { + bTsFlags |= TS_PEN_STAT; + /* Configure for peripdic trigger */ + ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_AVG8CONV); + ADC_SetTsDebounce(pAdc, 300); /* 300ns */ + ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PERIOD_TRIG); + /* Disable pen press detect */ + ADC_DisableIt(pAdc, ADC_IDR_PEN); + /* Enable pen release detect */ + ADC_EnableIt(pAdc, ADC_IER_NOPEN|ADC_IER_XRDY|ADC_IER_YRDY|ADC_IER_PRDY); + } + else if (status & ADC_ISR_PENS) + { + /* X */ + if (status & ADC_ISR_XRDY) + { + bTsFlags |= TS_X_RDY; + } + /* Y */ + if (status & ADC_ISR_YRDY) + { + bTsFlags |= TS_Y_RDY; + } + /* P: (X/1024)*[(Z2/Z1)-1] */ + if (status & ADC_ISR_PRDY) + { + bTsFlags |= TS_P_RDY; + } + } + /* X,Y,P are ready */ + if ((bTsFlags & TS_DATA_RDY) == TS_DATA_RDY) + { + uint32_t xpos, z2, z1; + bTsFlags &= ~TS_DATA_RDY; + + /* Get X,Y */ + TSD_GetRawMeasurement(dwRaw); + + /* Interprate X,Y */ + TSDCom_InterpolateMeasurement(dwRaw, dwTsData); + + /* Get P: Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1] */ + dwRaw[2] = ADC_GetTsPressure(pAdc); + #ifdef TS_XY_SWAP + xpos = (dwRaw[1]); + #else + xpos = (dwRaw[0]); + #endif + xpos = (xpos & ADC_XPOSR_XPOS_Msk) >> ADC_XPOSR_XPOS_Pos; + z2 = (dwRaw[2] & ADC_PRESSR_Z2_Msk) >> ADC_PRESSR_Z2_Pos; + z1 = (dwRaw[2] & ADC_PRESSR_Z1_Msk) >> ADC_PRESSR_Z1_Pos; + dwTsData[2] = (xpos) * (z2 - z1) / z1; + + /* PenPress */ + if (bTsFlags & TS_PEN_STAT) + { + bTsFlags &= ~TS_PEN_STAT; + /* Invoke PenPress callback */ + if (TSDCom_IsCalibrationOk()) + TSD_PenPressed(dwTsData[0], dwTsData[1], dwTsData[2]); + } + /* Periodic if data change invoke callback */ + if (dwTsData[0] != dwLastTsData[0] + || dwTsData[1] != dwLastTsData[1] + || dwTsData[2] != dwLastTsData[2] ) + { + /* Register last data */ + memcpy(dwLastTsData, dwTsData, sizeof(dwTsData)); + /* Invoke PenMoved callback */ + if (TSDCom_IsCalibrationOk()) + TSD_PenMoved(dwTsData[0], dwTsData[1], dwTsData[2]); + } + + } +} + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * Reads and store a touchscreen measurement in the provided array. + * The value stored are: + * - data[0] = XPOS * 1024 / XSCALE + * - data[1] = YPOS * 1024 / YSCALE + * \param pData Array where the measurements will be stored + */ +void TSD_GetRawMeasurement(uint32_t *pData) +{ + Adc *pAdc = ADC; + uint32_t xr, yr; + #ifdef TS_XY_SWAP + yr = ADC_GetTsXPosition(pAdc); + xr = ADC_GetTsYPosition(pAdc); + #else + xr = ADC_GetTsXPosition(pAdc); + yr = ADC_GetTsYPosition(pAdc); + #endif + pData[0] = ((xr & ADC_XPOSR_XPOS_Msk) >> ADC_XPOSR_XPOS_Pos) * 1024 * 4; + pData[0] /= ((xr & ADC_XPOSR_XSCALE_Msk) >> ADC_XPOSR_XSCALE_Pos); + pData[1] = ((yr & ADC_YPOSR_YPOS_Msk) >> ADC_YPOSR_YPOS_Pos) * 1024 * 4; + pData[1] /= ((yr & ADC_YPOSR_YSCALE_Msk) >> ADC_YPOSR_YSCALE_Pos); +} + +/** + * Wait pen pressed + */ +void TSD_WaitPenPressed(void) +{ + Adc *pAdc = ADC; + uint8_t bFlags = 0; + uint32_t dwStatus; + /* Wait for touch & end of conversion */ + while (1) + { + dwStatus = ADC_GetStatus(pAdc); + if (dwStatus & ADC_ISR_PEN) bFlags |= 8; + if (dwStatus & ADC_ISR_XRDY)bFlags |= 1; + if (dwStatus & ADC_ISR_YRDY)bFlags |= 2; + if (dwStatus & ADC_ISR_PRDY)bFlags |= 4; + if (bFlags == 0xF) break; + } +} + +/** + * Wait pen released + */ +void TSD_WaitPenReleased(void) +{ + Adc *pAdc = ADC; + + /* Wait for contact loss */ + while((ADC_GetStatus(pAdc) & ADC_ISR_NOPEN) == 0); +} + +/** + * Initializes the touchscreen driver and starts the calibration process. When + * finished, the touchscreen is operational. + * The configuration is taken from the board.h of the device being compiled. + * Important: the LCD driver must have been initialized prior to calling this + * function. + */ +void TSD_Initialize(void) +{ + Adc *pAdc = ADC; + + bTsFlags = 0; + + /* Configuration */ + PMC_EnablePeripheral(ID_ADC); + + ADC_SetClock(pAdc, BOARD_TOUCHSCREEN_ADCCLK, BOARD_MCK); + ADC_SetStartupTime(pAdc, BOARD_TOUCHSCREEN_STARTUP); + ADC_SetTrackingTime(pAdc, BOARD_TOUCHSCREEN_SHTIM); + + ADC_SetTriggerPeriod(pAdc, 20000000); /* 20ms */ + + ADC_SetTsMode(pAdc, ADC_TSMR_TSMODE_4_WIRE); + ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER); + + ADC_SetTsPenDetect(pAdc, 1); + ADC_SetTsDebounce(pAdc, BOARD_TOUCHSCREEN_DEBOUNCE); + + pAdc->ADC_MR &= ~(3<<28); + pAdc->ADC_ACR = 0x102; +} + +/** + * Enable/Disable TSD capturing + */ +void TSD_Enable(uint8_t bEnDis) +{ + Adc *pAdc = ADC; + if (bEnDis) + { + ADC_SetTsAverage(pAdc, ADC_TSMR_TSAV_NO_FILTER); + ADC_TsCalibration(pAdc); + ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG); + ADC_EnableIt(pAdc, ADC_IER_PEN); + } + else + { + ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_NO_TRIGGER); + ADC_DisableIt(pAdc, TS_STATUSES); + ADC_GetStatus(pAdc); + ADC_GetTsXPosition(pAdc); + ADC_GetTsYPosition(pAdc); + ADC_GetTsPressure(pAdc); + } +} + +/** + * Do touchscreen calibration + * \param pLcdBuffer LCD buffer to use for displaying the calibration info. + * \return 1 if calibration is Ok, 0 else + */ +uint8_t TSD_Calibrate(void) +{ + Adc *pAdc = ADC; + uint8_t ret = 0; + + /* Calibration is done only once */ + if(TSDCom_IsCalibrationOk()) return 1; + + /* Disable touch */ + TSD_Enable(0); + + /* Enable capturing */ + ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_PEN_TRIG); + + /* Do calibration */ + ret = TSDCom_Calibrate(); + + /* Configure interrupt generation + Do it only if the calibration is Ok. */ + //TSD_Enable(ret); + + return ret; +} + +/** + * Reset/stop the touchscreen + */ +void TSD_DeInitialize(void) +{ + Adc *pAdc = ADC; + /* Disable TS related interrupts */ + ADC_DisableIt(pAdc, TS_STATUSES); + /* Disable Trigger */ + ADC_SetTriggerMode(pAdc, ADC_TRGR_TRGMOD_NO_TRIGGER); + /* Disable TS mode */ + ADC_SetTsMode(pAdc, ADC_TSMR_TSMODE_NONE); + bTsFlags = 0; +} + +/**@}*/ +#endif /* #ifdef REG_ADC_TSMR */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/wav.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/wav.c new file mode 100644 index 000000000..2a74b0391 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/wav.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + +/*---------------------------------------------------------------------------- + * Definiation + *----------------------------------------------------------------------------*/ + +/* WAV letters "RIFF" */ +#define WAV_CHUNKID 0x46464952 +/* WAV letters "WAVE"*/ +#define WAV_FORMAT 0x45564157 +/* WAV letters "fmt "*/ +#define WAV_SUBCHUNKID 0x20746D66 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Check if the header of a Wav file is valid ot not. + * + * \param file Buffer holding the file to examinate. + * \return 1 if the header of a Wav file is valid; otherwise returns 0. + */ +unsigned char WAV_IsValid(const WavHeader *header) +{ + return ((header->chunkID == WAV_CHUNKID) + && (header->format == WAV_FORMAT) + && (header->subchunk1Size == 0x10)); +} + +/** + * \brief Display the information of the WAV file (sample rate, stereo/mono + * and frame size). + * + * \param header Wav head information. + */ + +void WAV_DisplayInfo(const WavHeader *header) +{ + printf( "Wave file header information\n\r"); + printf( "--------------------------------\n\r"); + printf( " - Chunk ID = 0x%08X\n\r", header->chunkID); + printf( " - Chunk Size = %u\n\r", header->chunkSize); + printf( " - Format = 0x%08X\n\r", header->format); + printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID); + printf( " - Subchunk1 Size = %u\n\r", header->subchunk1Size); + printf( " - Audio Format = 0x%04X\n\r", header->audioFormat); + printf( " - Num. Channels = %d\n\r", header->numChannels); + printf( " - Sample Rate = %u\n\r", header->sampleRate); + printf( " - Byte Rate = %u\n\r", header->byteRate); + printf( " - Block Align = %d\n\r", header->blockAlign); + printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample); + printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID); + printf( " - Subchunk2 Size = %u\n\r", header->subchunk2Size); +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/wm8904.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/wm8904.c new file mode 100644 index 000000000..718e787b9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libboard_sama5d3x-ek/source/wm8904.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Read data from WM8904 Register. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param regAddr Register address to read. + * \return value in the given register. + */ +uint16_t WM8904_Read(Twid *pTwid, + uint32_t device, + uint32_t regAddr) +{ + uint16_t bitsDataRegister; + uint8_t Tdata[2]={0,0}; + + TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0); + bitsDataRegister = (Tdata[0] << 8) | Tdata[1]; + return bitsDataRegister; +} + +/** + * \brief Write data to WM8904 Register. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param regAddr Register address to read. + * \param data Data to write + */ +void WM8904_Write(Twid *pTwid, + uint32_t device, + uint32_t regAddr, + uint16_t data) +{ + uint8_t tmpData[2]; + + tmpData[0] = (data & 0xff00) >> 8; + tmpData[1] = data & 0xff; + TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0); +} + +/** + * \brief Init WM8904 to DAC mode. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \return 0. + */ +uint8_t WM8904_Init(Twid *pTwid, + uint32_t device) + +{ + /* Software reset */ + WM8904_Write(pTwid, device, WM8904_REG_RESET, 0x0000); + + /* POBCTRL=1, ISEL=10, STARTUP_BIAS_ENA=0, BIAS_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_BIAS_CTRL0, 0x0019); + + /* VMID_BUF_ENA=1, VMID_RES=01, VMID_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_VMID_CTRL0, 0x0043); + + /* MICDET_ENA=1, MICBIAS_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_MICBIAS_CTRL0, 0x0003); + + /* ? */ + WM8904_Write(pTwid, device, WM8904_REG_BIAS_CTRL1, 0xC000); + + /* INL_ENA=1, INR_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_POWER_MANG0, 0x0003); + + /* HPL_PGA_ENA=1, HPR_PGA_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_POWER_MANG2, 0x0003); + + /* DACL_ENA=1, DACR_ENA=1, ADCL_ENA=1, ADCR_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_POWER_MANG6, 0x000F); + + /* TOCLK_RATE_DIV16=0,TOCLK_RATE_X4=0, SR_MODE=0, MCLK_DIV=0 */ + WM8904_Write(pTwid, device, WM8904_REG_CLOCK_RATE0, 0x845E); + + /* SYSCLK_SRC=1, CLK_SYS_ENA=1, CLK_DSP_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_CLOCK_RATE2, 0x4006); + + /* AIFADC_TCM=0, AIFADC_TCM_CHAN=0, BCLK_DIR=1 */ + WM8904_Write(pTwid, device, WM8904_REG_AUD_INF1, 0x404A); + + /* LRCLK=1, LRCLK_RATE=0x40 */ + WM8904_Write(pTwid, device, WM8904_REG_AUD_INF3, 0x0840); + + /* DAC_MCNO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_MUTE=0 */ + WM8904_Write(pTwid, device, WM8904_REG_ADC_DIG1, 0x0000); + + /* LINMUTE=0, LIN_VOL= 0 db */ + WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_LIN0, 0x0005); + + /* RINMUTE=0, RIN_VOL= 0 db */ + WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_RIN0, 0x0005); + + /* IN2L */ + WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_LIN1, 0x0010); + + /* IN2R*/ + WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_RIN1, 0x0010); + + /* HPOUTR_MUTE=1, HPOUTRZC=1, HPOUTR_VOL=0x1D */ + WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_ROUT1, 0x00AD); + + /* DCS_ENA_CHAN_1=1, DCS_ENA_CHAN_0=1 */ + WM8904_Write(pTwid, device, WM8904_REG_DC_SERVO0, 0x0003); + + /* HPL_RMV_SHORT=1, HPL_ENA_OUTp=1, HPL_ENA_DLY=1, HPL_ENA=1 + HPR_RMV_SHORT=1, HPR_ENA_OUTp=1, HPR_ENA_DLY=1, HPR_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_ANALOGUE_HP0, 0x00FF); + + /* CP_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_CHARGE_PUMP0, 0x0001); + + /* CP_DYN_PWR=1 */ + WM8904_Write(pTwid, device, WM8904_REG_CLASS0, 0x0005); + + /* FLL_FRACN_ENA=0, FLL_ENA=0 */ + WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL1, 0x0000); + /* FLL_FRACN_ENA=1, FLL_ENA=1 */ + WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL1, 0x0005); + /* FLL_FRATIO=4, FLL_OUTDIV= 7 */ + WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL2, 0x0704); + /* Fractional multiply for Fref = 0x8000 */ + WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL3, 0x8000); + /* FLL_GAIN=0, FLL_N=0x176 */ + WM8904_Write(pTwid, device, WM8904_REG_FLL_CRTL4, 0x1760); + WM8904_Write(pTwid, device, WM8904_REG_END, 0x55AA); + return 0; +} + +void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device) +{ + //{ 0x0005, 44}, /** R44 - Analogue Left Input 0 */ + //{ 0x0005, 45}, /** R45 - Analogue Right Input 0 */ + //{ 0x0000, 46}, /** R46 - Analogue Left Input 1 */ + //{ 0x0010, 47}, /** R47 - Analogue Right Input 1 */ + WM8904_Write(pTwid, device, 0x2C, 0x0008); + WM8904_Write(pTwid, device, 0x2D, 0x0005); + WM8904_Write(pTwid, device, 0x2E, 0x0000); + WM8904_Write(pTwid, device, 0x2F, 0x0010); +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/chip.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/chip.h new file mode 100644 index 000000000..e94e3031c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/chip.h @@ -0,0 +1,80 @@ +#ifndef _LIB_CHIP_SAMA5D3X_ +#define _LIB_CHIP_SAMA5D3X_ + +/* + * Peripherals registers definitions + */ +#if defined sama5d3x + #include "include/SAMA5D3X.h" +#else + #warning Library does not support the specified chip, specifying ata5miura. + #define sama5d3x + #include "include/SAMA5D3X.h" +#endif + + +/* Define attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ + #define WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ + #define WEAK __weak +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ + #define WEAK __attribute__ ((weak)) +#endif + +/* Define NO_INIT attribute and compiler specific symbols */ +#if defined ( __CC_ARM ) + #define NO_INIT + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#elif defined ( __ICCARM__ ) + #define NO_INIT __no_init + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ +#elif defined ( __GNUC__ ) + #define __ASM asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define NO_INIT +#endif + +#define CP15_PRESENT + +/* + * Peripherals + */ +#include "include/mmu.h" +#include "cp15/cp15.h" +#include "include/rstc.h" +#include "include/adc.h" +#include "include/async.h" +#include "include/emac.h" +#include "include/gmac.h" +#include "include/hsmci.h" +#include "include/irq.h" +#include "include/fuse.h" +#include "include/pio.h" +#include "include/pio_it.h" +#include "include/pmc.h" +#include "include/pwmc.h" +#include "include/rtc.h" +#include "include/smcNfc.h" +#include "include/spi.h" +#include "include/ssc.h" +#include "include/tc.h" +#include "include/twi.h" +#include "include/twid.h" +#include "include/usart.h" +#include "include/pit.h" +#include "include/dmac.h" +#include "include/udphs.h" +#include "include/emac.h" +#include "include/can.h" +#include "include/trace.h" +#include "include/wdt.h" +#include "include/video.h" +#include "include/isi.h" +#include "include/aes.h" +#include "include/sha.h" +#include "include/tdes.h" +#include "include/trng.h" +#endif /* _LIB_CHIP_SAMA5D3X_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/core.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/core.h new file mode 100644 index 000000000..85b51deee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/core.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +// core list +//------------------- +// arm7tdmi +// arm926ej_s +// arm1176jzf_s +// cortexm3 + +#ifndef _CORE_H +#define _CORE_H + +#define cortex_a5 + +#endif // #ifndef _CORE_H \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15.c new file mode 100644 index 000000000..b60c540fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15.c @@ -0,0 +1,276 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Reg Reads Writes +//---------------------------------------------------------------------------- +// 0 ID code Unpredictable +// 0 cache type Unpredictable +// 0 TCM status Unpredictable +// 1 Control Control +// 2 Translation table base Translation table base +// 3 Domain access control Domain access control +// 4 (Reserved) +// 5 Data fault status Data fault status +// 5 Instruction fault status Instruction fault status +// 6 Fault address Fault address +// 7 cache operations cache operations +// 8 Unpredictable TLB operations +// 9 cache lockdown cache lockdown +// 9 TCM region TCM region +// 10 TLB lockdown TLB lockdown +// 11 (Reserved) +// 12 (Reserved) +// 13 FCSE PID FCSE PID +// 13 Context ID Context ID +// 14 (Reserved) +// 15 Test configuration Test configuration +//----------------------------------------------------------------------------- + + +/** \page cp15_f CP15 Functions. + * + * \section CP15 function Usage + * + * Methods to manage the Coprocessor 15. Coprocessor 15, or System Control + * Coprocessor CP15, is used to configure and control all the items in the + * list below: + *
    + *
  • ARM core + *
  • caches (Icache, Dcache and write buffer) + *
  • TCM + *
  • MMU + *
  • Other system options + *
+ * \section Usage + * + * -# Enable or disable D cache with Enable_D_cache and Disable_D_cache + * -# Enable or disable I cache with Enable_I_cache and Disable_I_cache + * + * Related files:\n + * \ref cp15.h\n + * \ref cp15.c.\n + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#if defined(__ICCARM__) + #include +#endif +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Check Instruction cache + * \return 0 if I_cache disable, 1 if I_cache enable + */ +unsigned int CP15_IsIcacheEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & (1 << CP15_I_BIT)) != 0); +} + + +/** + * \brief Enable Instruction cache + */ +void CP15_EnableIcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is disabled + if ((control & (1 << CP15_I_BIT)) == 0) { + + control |= (1 << CP15_I_BIT); + CP15_WriteControl(control); + TRACE_INFO("I cache enabled.\n\r"); + } +#if !defined(OP_BOOTSTRAP_on) + else { + + TRACE_INFO("I cache is already enabled.\n\r"); + } +#endif +} + + +/** + * \brief Disable Instruction cache + */ +void CP15_DisableIcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is enabled + if ((control & (1 << CP15_I_BIT)) != 0) { + + control &= ~(1ul << CP15_I_BIT); + CP15_WriteControl(control); + TRACE_INFO("I cache disabled.\n\r"); + } + else { + + TRACE_INFO("I cache is already disabled.\n\r"); + } +} + +/** + * \brief Check MMU + * \return 0 if MMU disable, 1 if MMU enable + */ +unsigned int CP15_IsMMUEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & (1 << CP15_M_BIT)) != 0); +} + + +/** + * \brief Enable MMU + */ +void CP15_EnableMMU(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if MMU is disabled + if ((control & (1 << CP15_M_BIT)) == 0) { + + control |= (1 << CP15_M_BIT); + CP15_WriteControl(control); + TRACE_INFO("MMU enabled.\n\r"); + } + else { + + TRACE_INFO("MMU is already enabled.\n\r"); + } +} + + +/** + * \brief Disable MMU + */ +void CP15_DisableMMU(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if MMU is enabled + if ((control & (1 << CP15_M_BIT)) != 0) { + + control &= ~(1ul << CP15_M_BIT); + control &= ~(1ul << CP15_C_BIT); + CP15_WriteControl(control); + TRACE_INFO("MMU disabled.\n\r"); + } + else { + + TRACE_INFO("MMU is already disabled.\n\r"); + } +} + + +/** + * \brief Check D_cache + * \return 0 if D_cache disable, 1 if D_cache enable (with MMU of course) + */ +unsigned int CP15_IsDcacheEnabled(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0); +} + +/** + * \brief Enable Data cache + */ +void CP15_EnableDcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + if( !CP15_IsMMUEnabled() ) { + TRACE_ERROR("Do nothing: MMU not enabled\n\r"); + } + else { + // Check if cache is disabled + if ((control & (1 << CP15_C_BIT)) == 0) { + + control |= (1 << CP15_C_BIT); + CP15_WriteControl(control); + TRACE_INFO("D cache enabled.\n\r"); + } + else { + + TRACE_INFO("D cache is already enabled.\n\r"); + } + } +} + +/** + * \brief Disable Data cache + */ +void CP15_DisableDcache(void) +{ + unsigned int control; + + control = CP15_ReadControl(); + + // Check if cache is enabled + if ((control & (1 << CP15_C_BIT)) != 0) { + + control &= ~(1ul << CP15_C_BIT); + CP15_WriteControl(control); + TRACE_INFO("D cache disabled.\n\r"); + } + else { + + TRACE_INFO("D cache is already disabled.\n\r"); + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15.h new file mode 100644 index 000000000..807a7e00c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15.h @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _CP15_H +#define _CP15_H + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define CP15_L4_BIT 15 // Determines if the T bit is set when load instructions + // change the PC: + // 0 = loads to PC set the T bit + // 1 = loads to PC do not set T bit + +#define CP15_RR_BIT 14 // RR bit Replacement strategy for Icache and Dcache: + // 0 = Random replacement + // 1 = Round-robin replacement. + +#define CP15_V_BIT 13 // V bit Location of exception vectors: + // 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C + // 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C + +#define CP15_I_BIT 12 // I bit Icache enable/disable: + // 0 = Icache disabled + // 1 = Icache enabled + +#define CP15_R_BIT 9 // R bit ROM protection + +#define CP15_S_BIT 8 // S bit System protection + +#define CP15_B_BIT 7 // B bit Endianness: + // 0 = Little-endian operation + // 1 = Big-endian operation. + +#define CP15_C_BIT 2 // C bit Dcache enable/disable: + // 0 = cache disabled + // 1 = cache enabled + +#define CP15_A_BIT 1 // A bit Alignment fault enable/disable: + // 0 = Data address alignment fault checking disabled + // 1 = Data address alignment fault checking enabled + +#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled. + // 0 = disabled + // 1 = enabled + +/** No access Any access generates a domain fault. */ +#define CP15_DOMAIN_NO_ACCESS 0x00 +/** Client Accesses are checked against the access permission bits in the section or page descriptor. */ +#define CP15_DOMAIN_CLIENT_ACCESS 0x01 +/** Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated. */ +#define CP15_DOMAIN_MANAGER_ACCESS 0x03 + + +/*------------------------------------------------------------------------------ */ +/* Exported functions */ +/*------------------------------------------------------------------------------ */ +extern unsigned int CP15_ReadID(void); +extern unsigned int CP15_ReadControl(void); +extern void CP15_WriteControl(unsigned int value); +extern void CP15_WriteTTB(unsigned int value); +extern void CP15_WriteDomainAccessControl(unsigned int value); + +extern void CP15_InvalidateIcacheInnerSharable(void); +extern void CP15_InvalidateBTBinnerSharable(void); +extern void CP15_InvalidateIcache(void); +extern void CP15_InvalidateIcacheByMva(void); +extern void CP15_FlushBTB(void); +extern void CP15_FlushBTBbyMva(void); +extern void CP15_InvalidateDcacheLineByMva(void); +extern void CP15_InvalidateDcacheLineBySetWay(void); +extern void CP15_CleanDCacheByMva(void); +extern void CP15_CleanDCacheBySetWay(void); +extern void CP15_CleanDCacheMva(void); +extern void CP15_CleanInvalidateDcacheLineByMva(void); +extern void CP15_CleanInvalidateDcacheLine(void); + +extern void CP15_coherent_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_invalidate_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_clean_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_flush_dcache_for_dma (uint32_t startAddr, uint32_t endAddr ); +extern void CP15_flush_kern_dcache_for_dma (uint32_t startAddr, uint32_t size ); + + +/*------------------------------------------------------------------------------ */ +/* Exported functions from CP15.c */ +/*------------------------------------------------------------------------------ */ + +/** MMU (Status/Enable/Disable) */ +extern unsigned int CP15_IsMMUEnabled(void); +extern void CP15_EnableMMU(void); +extern void CP15_DisableMMU(void); + +/** I cache (Status/Enable/Disable) */ +extern unsigned int CP15_IsIcacheEnabled(void); +extern void CP15_EnableIcache(void); +extern void CP15_DisableIcache(void); + +/** D cache (Status/Enable/Disable) */ +extern unsigned int CP15_IsDcacheEnabled(void); +extern void CP15_EnableDcache(void); +extern void CP15_DisableDcache(void); + +#endif // #ifndef _CP15_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_gcc.S b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_gcc.S new file mode 100644 index 000000000..b91724fef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_gcc.S @@ -0,0 +1,459 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA, + * OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + + +/** \file */ + + +/** + * \addtogroup cp15_cache Cache Operations + * + * \section Usage + * + * They are performed as MCR instructions and only operate on a level 1 cache associated with + * ATM v7 processor. + * The supported operations are: + *
    + *
  • Any of these operations can be applied to + * -# any data cache + * -# any unified cache. + *
  • Invalidate by MVA + * Performs an invalidate of a data or unified cache line based on the address it contains. + *
  • Invalidate by set/way + * Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
  • Clean by MVA + * Performs a clean of a data or unified cache line based on the address it contains. + *
  • Clean by set/way + * Performs a clean of a data or unified cache line based on its location in the cache hierarchy. + *
  • Clean and Invalidate by MVA + * Performs a clean and invalidate of a data or unified cache line based on the address it contains. + *
  • Clean and Invalidate by set/way + * Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
+ * + * Related files:\n + * \ref cp15.h\n + * \ref cp15_arm_gnu.S \n + */ + +/*---------------------------------------------------------------------------- + * Functions to access CP15 coprocessor register + *----------------------------------------------------------------------------*/ + .global CP15_ReadID + .global CP15_ReadControl + .global CP15_WriteControl + .global CP15_WriteDomainAccessControl + .global CP15_WriteTTB + .global CP15_InvalidateIcacheInnerSharable + .global CP15_InvalidateBTBinnerSharable + .global CP15_InvalidateIcache + .global CP15_InvalidateIcacheByMva + .global CP15_FlushBTB + .global CP15_FlushBTBbyMva + .global CP15_InvalidateDcacheLineByMva + .global CP15_InvalidateDcacheLineBySetWay + .global CP15_CleanDCacheByMva + .global CP15_CleanDCacheBySetWay + .global CP15_CleanDCacheMva + .global CP15_CleanInvalidateDcacheLineByMva + .global CP15_CleanInvalidateDcacheLine + .global CP15_coherent_dcache_for_dma + .global CP15_invalidate_dcache_for_dma + .global CP15_clean_dcache_for_dma + .global CP15_flush_dcache_for_dma + .global CP15_flush_kern_dcache_for_dma + +/** + * \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers. + * Reading from this register returns the device ID, the cache type, or the TCM status + * depending on the value of Opcode_2 used. + */ + .section .CP15_ReadID + .global CP15_ReadID +CP15_ReadID: + mov r0, #0 + mrc p15, 0, r0, c0, c0, 0 + bx lr + +/** + * \brief Register c1 is the Control Register for the ARM926EJ-S processor. + * This register specifies the configuration used to enable and disable the + * caches and MMU. It is recommended that you access this register using a + * read-modify-write sequence + */ + .section .CP15_ReadControl + .global CP15_ReadControl +CP15_ReadControl: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 0 + bx lr + + .section .CP15_WriteControl + .global CP15_WriteControl +CP15_WriteControl: + mcr p15, 0, r0, c1, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + bx lr + + .section .CP15_WriteDomainAccessControl + .global CP15_WriteDomainAccessControl +CP15_WriteDomainAccessControl: + mcr p15, 0, r0, c3, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + bx lr + +/** + * \brief ARMv7A architecture supports two translation tables + * Configure translation table base (TTB) control register cp15,c2 + * to a value of all zeros, indicates we are using TTB register 0. + * write the address of our page table base to TTB register 0. + */ + + .section .CP15_WriteTTB + .global CP15_WriteTTB +CP15_WriteTTB: + mcr p15, 0, r0, c2, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + bx lr + + +/** + * \brief Invalidate I cache predictor array inner Sharable + */ + .section .CP15_InvalidateIcacheInnerSharable + .global CP15_InvalidateIcacheInnerSharable +CP15_InvalidateIcacheInnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 0 + bx lr + + +/** + * \brief Invalidate entire branch predictor array inner Sharable + */ + .section .CP15_InvalidateBTBinnerSharable + .global CP15_InvalidateBTBinnerSharable +CP15_InvalidateBTBinnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 + bx lr + +/** + * \brief Invalidate all instruction caches to PoU, also flushes branch target cache + */ + .section .CP15_InvalidateIcache + .global CP15_InvalidateIcache +CP15_InvalidateIcache: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + +/** + * \brief Invalidate instruction caches by VA to PoU + */ + .section .CP15_InvalidateIcacheByMva + .global CP15_InvalidateIcacheByMva +CP15_InvalidateIcacheByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 1 + bx lr + +/** + * \brief Flush entire branch predictor array + */ + .section .CP15_FlushBTB + .global CP15_FlushBTB +CP15_FlushBTB: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 + bx lr + +/** + * \brief Flush branch predictor array entry by MVA + */ + .section .CP15_FlushBTBbyMva + .global CP15_FlushBTBbyMva +CP15_FlushBTBbyMva: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 7 + bx lr + +/** + * \brief Invalidate data cache line by VA to Poc + */ + .section .CP15_InvalidateDcacheLineByMva + .global CP15_InvalidateDcacheLineByMva +CP15_InvalidateDcacheLineByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c6, 1 + bx lr + + +/** + * \brief Invalidate data cache line by set/way + */ + .section .CP15_InvalidateDcacheLineBySetWay + .global CP15_InvalidateDcacheLineBySetWay +CP15_InvalidateDcacheLineBySetWay: + mov r0, #0 + mcr p15, 0, r0, c7, c6, 2 + bx lr + + +/** + * \brief Clean data cache line by MVA + */ + .section .CP15_CleanDCacheByMva + .global CP15_CleanDCacheByMva +CP15_CleanDCacheByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 1 + bx lr + + +/** + * \brief Clean data cache line by Set/way + */ + .section .CP15_CleanDCacheBySetWay + .global CP15_CleanDCacheBySetWay +CP15_CleanDCacheBySetWay: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 2 + bx lr + +/** + * \brief Clean unified cache line by MVA + */ + .section .CP15_CleanDCacheMva + .global CP15_CleanDCacheMva +CP15_CleanDCacheMva: + mov r0, #0 + mcr p15, 0, r0, c7, c11, 1 + bx lr + + +/** + * \brief Clean and invalidate data cache line by VA to PoC + */ + .section .CP15_CleanInvalidateDcacheLineByMva + .global CP15_CleanInvalidateDcacheLineByMva +CP15_CleanInvalidateDcacheLineByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c14, 1 + bx lr + + +/** + * \brief Clean and Incalidate data cache line by Set/Way + */ + .section .CP15_CleanInvalidateDcacheLine + .global CP15_CleanInvalidateDcacheLine +CP15_CleanInvalidateDcacheLine: + mov r0, #0 + mcr p15, 0, r0, c7, c14, 2 + bx lr + +/** + * \brief Ensure that the I and D caches are coherent within specified + * region. This is typically used when code has been written to + * a memory region, and will be executed. + * \param start virtual start address of region + * \param end virtual end address of region + */ + .section .CP15_coherent_dcache_for_dma + .global CP15_coherent_dcache_for_dma +CP15_coherent_dcache_for_dma: + + mrc p15, 0, r3, c0, c0, 1 + lsr r3, r3, #16 + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 + + sub r3, r2, #1 + bic r12, r0, r3 +1: + mcr p15, 0, r12, c7, c11, 1 + add r12, r12, r2 + cmp r12, r1 + blo 1b + dsb + + mrc p15, 0, r3, c0, c0, 1 + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 + + sub r3, r2, #1 + bic r12, r0, r3 +2: + mcr p15, 0, r12, c7, c5, 1 + add r12, r12, r2 + cmp r12, r1 + blo 2b + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 + mcr p15, 0, r0, c7, c5, 6 + dsb + isb + bx lr + + +/** + * \brief Invalidate the data cache within the specified region; we will + * be performing a DMA operation in this region and we want to + * purge old data in the cache. + * \param start virtual start address of region + * \param end virtual end address of region + */ + .section .CP15_invalidate_dcache_for_dma + .global CP15_invalidate_dcache_for_dma +CP15_invalidate_dcache_for_dma: + + mrc p15, 0, r3, c0, c0, 1 + lsr r3, r3, #16 + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 + + sub r3, r2, #1 + tst r0, r3 + bic r0, r0, r3 + + mcrne p15, 0, r0, c7, c14, 1 + + tst r1, r3 + bic r1, r1, r3 + mcrne p15, 0, r1, c7, c14, 1 +3: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, r2 + cmp r0, r1 + blo 3b + dsb + bx lr + + +/** + * \brief Clean the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + .section .CP15_clean_dcache_for_dma + .global CP15_clean_dcache_for_dma +CP15_clean_dcache_for_dma: + mrc p15, 0, r3, c0, c0, 1 + lsr r3, r3, #16 + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 + + sub r3, r2, #1 + bic r0, r0, r3 +4: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, r2 + cmp r0, r1 + blo 4b + dsb + bx lr + + +/** + * \brief Flush the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + .section .CP15_flush_dcache_for_dma + .global CP15_flush_dcache_for_dma +CP15_flush_dcache_for_dma: + mrc p15, 0, r3, c0, c0, 1 + lsr r3, r3, #16 + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 + sub r3, r2, #1 + bic r0, r0, r3 +5: + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, r2 + cmp r0, r1 + blo 5b + dsb + bx lr + + +/** + * \brief CP15_flush_kern_dcache_for_dma + * Ensure that the data held in the page kaddr is written back to the page in question. + * \param start virtual start address of region + * \param end virtual end address of region + */ + .section .CP15_flush_kern_dcache_for_dma + .global CP15_flush_kern_dcache_for_dma +CP15_flush_kern_dcache_for_dma: + mrc p15, 0, r3, c0, c0, 1 + lsr r3, r3, #16 + and r3, r3, #0xf + mov r2, #4 + mov r2, r2, lsl r3 + + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 + + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb + bx lr + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s new file mode 100644 index 000000000..4861c05c4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/cp15/cp15_asm_iar.s @@ -0,0 +1,471 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES// LOSS OF USE, DATA, + * OR PROFITS// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + + +/** \file */ +/** + * \addtogroup cp15_cache Cache Operations + * + * \section Usage + * + * They are performed as MCR instructions and only operate on a level 1 cache associated with + * ATM v7 processor. + * The supported operations are: + *
    + *
  • Any of these operations can be applied to + * -# any data cache + * -# any unified cache. + *
  • Invalidate by MVA + * Performs an invalidate of a data or unified cache line based on the address it contains. + *
  • Invalidate by set/way + * Performs an invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
  • Clean by MVA + * Performs a clean of a data or unified cache line based on the address it contains. + *
  • Clean by set/way + * Performs a clean of a data or unified cache line based on its location in the cache hierarchy. + *
  • Clean and Invalidate by MVA + * Performs a clean and invalidate of a data or unified cache line based on the address it contains. + *
  • Clean and Invalidate by set/way + * Performs a clean and invalidate of a data or unified cache line based on its location in the cache hierarchy. + *
+ * + * Related files:\n + * \ref cp15.h\n + * \ref cp15_arm_iar.s \n + */ + + + MODULE ?cp15 + + //// Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#define __ASSEMBLY__ + + +/*---------------------------------------------------------------------------- + * Functions to access CP15 coprocessor register + *----------------------------------------------------------------------------*/ + PUBLIC CP15_ReadID + PUBLIC CP15_ReadControl + PUBLIC CP15_WriteControl + PUBLIC CP15_WriteDomainAccessControl + PUBLIC CP15_WriteTTB + PUBLIC CP15_InvalidateIcacheInnerSharable + PUBLIC CP15_InvalidateBTBinnerSharable + PUBLIC CP15_InvalidateIcache + PUBLIC CP15_InvalidateIcacheByMva + PUBLIC CP15_FlushBTB + PUBLIC CP15_FlushBTBbyMva + PUBLIC CP15_InvalidateDcacheLineByMva + PUBLIC CP15_InvalidateDcacheLineBySetWay + PUBLIC CP15_CleanDCacheByMva + PUBLIC CP15_CleanDCacheBySetWay + PUBLIC CP15_CleanDCacheMva + PUBLIC CP15_CleanInvalidateDcacheLineByMva + PUBLIC CP15_CleanInvalidateDcacheLine + PUBLIC CP15_coherent_dcache_for_dma + PUBLIC CP15_invalidate_dcache_for_dma + PUBLIC CP15_clean_dcache_for_dma + PUBLIC CP15_flush_dcache_for_dma + PUBLIC CP15_flush_kern_dcache_for_dma + +/** + * \brief Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers. + * Reading from this register returns the device ID, the cache type, or the TCM status + * depending on the value of Opcode_2 used. + */ + SECTION .CP15_ReadID:DATA:NOROOT(2) + PUBLIC CP15_ReadID +CP15_ReadID: + mov r0, #0 + mrc p15, 0, r0, c0, c0, 0 + bx lr + +/** + * \brief Register c1 is the Control Register for the ARM926EJ-S processor. + * This register specifies the configuration used to enable and disable the + * caches and MMU. It is recommended that you access this register using a + * read-modify-write sequence + */ + SECTION .CP15_ReadControl:CODE:NOROOT(2) + PUBLIC CP15_ReadControl +CP15_ReadControl: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 0 + bx lr + + SECTION .CP15_WriteControl:CODE:NOROOT(2) + PUBLIC CP15_WriteControl +CP15_WriteControl: + mcr p15, 0, r0, c1, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + bx lr + + SECTION .CP15_WriteDomainAccessControl:CODE:NOROOT(2) + PUBLIC CP15_WriteDomainAccessControl +CP15_WriteDomainAccessControl: + mcr p15, 0, r0, c3, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + bx lr + +/** + * \brief ARMv7A architecture supports two translation tables + * Configure translation table base (TTB) control register cp15,c2 + * to a value of all zeros, indicates we are using TTB register 0. + * write the address of our page table base to TTB register 0. + */ + SECTION .CP15_WriteTTB:CODE:NOROOT(2) + PUBLIC CP15_WriteTTB +CP15_WriteTTB: + mcr p15, 0, r0, c2, c0, 0 + nop + nop + nop + nop + nop + nop + nop + nop + bx lr + +/** + * \brief Invalidate I cache predictor array inner Sharable + */ + SECTION .CP15_InvalidateIcacheInnerSharable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcacheInnerSharable +CP15_InvalidateIcacheInnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 0 + bx lr + +/** + * \brief Invalidate entire branch predictor array inner Sharable + */ + SECTION .CP15_InvalidateBTBinnerSharable:CODE:NOROOT(2) + PUBLIC CP15_InvalidateBTBinnerSharable +CP15_InvalidateBTBinnerSharable: + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 + bx lr + +/** + * \brief Invalidate all instruction caches to PoU, also flushes branch target cache + */ + SECTION .CP15_InvalidateIcache:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcache +CP15_InvalidateIcache: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + +/** + * \brief Invalidate instruction caches by VA to PoU + */ + SECTION .CP15_InvalidateIcacheByMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateIcacheByMva +CP15_InvalidateIcacheByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 1 + bx lr + +/** + * \brief Flush entire branch predictor array + */ + SECTION .CP15_FlushBTB:CODE:NOROOT(2) + PUBLIC CP15_FlushBTB +CP15_FlushBTB: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 + bx lr + +/** + * \brief Flush branch predictor array entry by MVA + */ + SECTION .CP15_FlushBTBbyMva:CODE:NOROOT(2) + PUBLIC CP15_FlushBTBbyMva +CP15_FlushBTBbyMva: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 7 + bx lr + +/** + * \brief Invalidate data cache line by VA to Poc + */ + SECTION .CP15_InvalidateDcacheLineByMva:CODE:NOROOT(2) + PUBLIC CP15_InvalidateDcacheLineByMva +CP15_InvalidateDcacheLineByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c6, 1 + bx lr + +/** + * \brief Invalidate data cache line by set/way + */ + SECTION .CP15_InvalidateDcacheLineBySetWay:CODE:NOROOT(2) + PUBLIC CP15_InvalidateDcacheLineBySetWay +CP15_InvalidateDcacheLineBySetWay: + mov r0, #0 + mcr p15, 0, r0, c7, c6, 2 + bx lr + +/** + * \brief Clean data cache line by MVA + */ + SECTION .CP15_CleanDCacheByMva:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheByMva +CP15_CleanDCacheByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 1 + bx lr + +/** + * \brief Clean data cache line by Set/way + */ + SECTION .CP15_CleanDCacheBySetWay:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheBySetWay +CP15_CleanDCacheBySetWay: + mov r0, #0 + mcr p15, 0, r0, c7, c10, 2 + bx lr + +/** + * \brief Clean unified cache line by MVA + */ + SECTION .CP15_CleanDCacheMva:CODE:NOROOT(2) + PUBLIC CP15_CleanDCacheMva +CP15_CleanDCacheMva: + mov r0, #0 + mcr p15, 0, r0, c7, c11, 1 + bx lr + +/** + * \brief Clean and invalidate data cache line by VA to PoC + */ + SECTION .CP15_CleanInvalidateDcacheLineByMva:CODE:NOROOT(2) + PUBLIC CP15_CleanInvalidateDcacheLineByMva +CP15_CleanInvalidateDcacheLineByMva: + mov r0, #0 + mcr p15, 0, r0, c7, c14, 1 + bx lr + +/** + * \brief Clean and Incalidate data cache line by Set/Way + */ + SECTION .CP15_CleanInvalidateDcacheLine:CODE:NOROOT(2) + PUBLIC CP15_CleanInvalidateDcacheLine +CP15_CleanInvalidateDcacheLine: + mov r0, #0 + mcr p15, 0, r0, c7, c14, 2 + bx lr + +/** + * \brief Ensure that the I and D caches are coherent within specified + * region. This is typically used when code has been written to + * a memory region, and will be executed. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_coherent_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_coherent_dcache_for_dma +CP15_coherent_dcache_for_dma: +// dcache_line_size r2, r3 + + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r12, r0, r3 +loop1: + mcr p15, 0, r12, c7, c11, 1 // clean D line to the point of unification + add r12, r12, r2 + cmp r12, r1 + blo loop1 + dsb + +// .macro icache_line_size, reg, tmp + mrc p15, 0, r3, c0, c0, 1 // read ctr + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r12, r0, r3 +loop2: + mcr p15, 0, r12, c7, c5, 1 // invalidate I line + add r12, r12, r2 + cmp r12, r1 + blo loop2 + mov r0, #0 + mcr p15, 0, r0, c7, c1, 6 //invalidate BTB Inner Shareable + mcr p15, 0, r0, c7, c5, 6 // invalidate BTB + dsb + isb + bx lr + + +/** + * \brief Invalidate the data cache within the specified region; we will + * be performing a DMA operation in this region and we want to + * purge old data in the cache. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_invalidate_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_invalidate_dcache_for_dma +CP15_invalidate_dcache_for_dma: + +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + tst r0, r3 + bic r0, r0, r3 + + mcrne p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line + + tst r1, r3 + bic r1, r1, r3 + mcrne p15, 0, r1, c7, c14, 1 // clean & invalidate D / U line +loop3: + mcr p15, 0, r0, c7, c6, 1 // invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop3 + dsb + bx lr + + +/** + * \brief Clean the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_clean_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_clean_dcache_for_dma +CP15_clean_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + sub r3, r2, #1 + bic r0, r0, r3 +loop4: + mcr p15, 0, r0, c7, c10, 1 // clean D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop4 + dsb + bx lr + + +/** + * \brief Flush the data cache within the specified region + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_flush_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_flush_dcache_for_dma +CP15_flush_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + sub r3, r2, #1 + bic r0, r0, r3 +loop5: + mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + blo loop5 + dsb + bx lr + + +/** + * \brief CP15_flush_kern_dcache_for_dma + * Ensure that the data held in the page kaddr is written back to the page in question. + * \param start virtual start address of region + * \param end virtual end address of region + */ + SECTION .CP15_flush_kern_dcache_for_dma:CODE:NOROOT(2) + PUBLIC CP15_flush_kern_dcache_for_dma +CP15_flush_kern_dcache_for_dma: +// dcache_line_size r2, r3 + mrc p15, 0, r3, c0, c0, 1 // read ctr + lsr r3, r3, #16 + and r3, r3, #0xf // cache line size encoding + mov r2, #4 // bytes per word + mov r2, r2, lsl r3 // actual cache line size + + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 + + mcr p15, 0, r0, c7, c14, 1 // clean & invalidate D line / unified line + add r0, r0, r2 + cmp r0, r1 + blo 1b + dsb + bx lr + END + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/SAMA5D3X.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/SAMA5D3X.h new file mode 100644 index 000000000..594e54d55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/SAMA5D3X.h @@ -0,0 +1,1048 @@ +/* %ATMEL_LICENCE% */ + +#ifndef _SAMA5D3x_ +#define _SAMA5D3x_ + +/** \addtogroup SAMA5D3x_definitions SAMA5D3x definitions + This file defines all structures and symbols for SAMA5D3x: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +typedef enum IRQn +{ + FIQ_IRQn = 0, /**< 0 SAMA5D3x Advanced Interrupt Controller (FIQ) */ + SYS_IRQn = 1, /**< 1 SAMA5D3x System Controller Interrupt (SYS) */ + DBGU_IRQn = 2, /**< 2 SAMA5D3x Debug Unit Interrupt (DBGU) */ + PIT_IRQn = 3, /**< 3 SAMA5D3x Periodic Interval Timer Interrupt (PIT) */ + WDT_IRQn = 4, /**< 4 SAMA5D3x Watchdog timer Interrupt (WDT) */ + SMC_IRQn = 5, /**< 5 SAMA5D3x Multi-bit ECC Interrupt (SMC) */ + PIOA_IRQn = 6, /**< 6 SAMA5D3x Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 7, /**< 7 SAMA5D3x Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 8, /**< 8 SAMA5D3x Parallel I/O Controller C (PIOC) */ + PIOD_IRQn = 9, /**< 9 SAMA5D3x Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 10, /**< 10 SAMA5D3x Parallel I/O Controller E (PIOE) */ + SMD_IRQn = 11, /**< 11 SAMA5D3x SMD Soft Modem (SMD) */ + USART0_IRQn = 12, /**< 12 SAMA5D3x USART 0 (USART0) */ + USART1_IRQn = 13, /**< 13 SAMA5D3x USART 1 (USART1) */ + USART2_IRQn = 14, /**< 14 SAMA5D3x USART 2 (USART2) */ + USART3_IRQn = 15, /**< 15 SAMA5D3x USART 3 (USART3) */ + UART0_IRQn = 16, /**< 16 SAMA5D3x UART 0 (UART0) */ + UART1_IRQn = 17, /**< 17 SAMA5D3x UART 1 (UART1) */ + TWI0_IRQn = 18, /**< 18 SAMA5D3x Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 19, /**< 19 SAMA5D3x Two-Wire Interface 1 (TWI1) */ + TWI2_IRQn = 20, /**< 20 SAMA5D3x Two-Wire Interface 2 (TWI2) */ + HSMCI0_IRQn = 21, /**< 21 SAMA5D3x High Speed Multimedia Card Interface 0 (HSMCI0) */ + HSMCI1_IRQn = 22, /**< 22 SAMA5D3x High Speed Multimedia Card Interface 1 (HSMCI1) */ + HSMCI2_IRQn = 23, /**< 23 SAMA5D3x High Speed Multimedia Card Interface 2 (HSMCI2) */ + SPI0_IRQn = 24, /**< 24 SAMA5D3x Serial Peripheral Interface 0 (SPI0) */ + SPI1_IRQn = 25, /**< 25 SAMA5D3x Serial Peripheral Interface 1 (SPI1) */ + TC0_IRQn = 26, /**< 26 SAMA5D3x Timer Counter 0 (ch. 0, 1, 2) (TC0) */ + TC1_IRQn = 27, /**< 27 SAMA5D3x Timer Counter 1 (ch. 3, 4, 5) (TC1) */ + PWM_IRQn = 28, /**< 28 SAMA5D3x Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 29, /**< 29 SAMA5D3x Touch Screen ADC Controller (ADC) */ + DMAC0_IRQn = 30, /**< 30 SAMA5D3x DMA Controller 0 (DMAC0) */ + DMAC1_IRQn = 31, /**< 31 SAMA5D3x DMA Controller 1 (DMAC1) */ + UHPHS_IRQn = 32, /**< 32 SAMA5D3x USB Host High Speed (UHPHS) */ + UDPHS_IRQn = 33, /**< 33 SAMA5D3x USB Device High Speed (UDPHS) */ + GMAC_IRQn = 34, /**< 34 SAMA5D3x Gigabit Ethernet MAC (GMAC) */ + EMAC_IRQn = 35, /**< 35 SAMA5D3x Ethernet MAC (EMAC) */ + LCDC_IRQn = 36, /**< 36 SAMA5D3x LCD Controller (LCDC) */ + ISI_IRQn = 37, /**< 37 SAMA5D3x Image Sensor Interface (ISI) */ + SSC0_IRQn = 38, /**< 38 SAMA5D3x Synchronous Serial Controller 0 (SSC0) */ + SSC1_IRQn = 39, /**< 39 SAMA5D3x Synchronous Serial Controller 1 (SSC1) */ + CAN0_IRQn = 40, /**< 40 SAMA5D3x CAN controller 0 (CAN0) */ + CAN1_IRQn = 41, /**< 41 SAMA5D3x CAN controller 1 (CAN1) */ + SHA_IRQn = 42, /**< 42 SAMA5D3x Secure Hash Algorithm (SHA) */ + AES_IRQn = 43, /**< 43 SAMA5D3x Advanced Encryption Standard (AES) */ + TDES_IRQn = 44, /**< 44 SAMA5D3x Triple Data EncryptionStandard (TDES) */ + TRNG_IRQn = 45, /**< 45 SAMA5D3x True Random Number Generator (TRNG) */ + ARM_IRQn = 46, /**< 46 SAMA5D3x Performance Monitor Unit (ARM) */ + IRQ_IRQn = 47, /**< 47 SAMA5D3x Advanced Interrupt Controller (IRQ) */ + FUSE_IRQn = 48, /**< 48 SAMA5D3x Fuse Controller (FUSE) */ + MPDDRC_IRQn = 49, /**< 49 SAMA5D3x MPDDR controller (MPDDRC) */ + + PERIPH_COUNT_IRQn = 50 /**< Number of peripheral IDs */ +} IRQn_Type; + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMA5D3x */ +/* ************************************************************************** */ +/** \addtogroup SAMA5D3x_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_aic.h" +#include "component/component_aximx.h" +#include "component/component_bsc.h" +#include "component/component_can.h" +#include "component/component_dbgu.h" +#include "component/component_dmac.h" +#include "component/component_emac.h" +#include "component/component_gmac.h" +#include "component/component_fuse.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_isi.h" +#include "component/component_lcdc.h" +#include "component/component_matrix.h" +#include "component/component_mpddrc.h" +#include "component/component_pio.h" +#include "component/component_pit.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_sckc.h" +#include "component/component_sfr.h" +#include "component/component_shdwc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_udphs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +#include "component/component_aes.h" +#include "component/component_sha.h" +#include "component/component_tdes.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMA5D31 */ +/* ************************************************************************** */ +/** \addtogroup SAMA5D31_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_smd.h" +#include "instance/instance_aximx.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_hsmci0.h" +#include "instance/instance_spi0.h" +#include "instance/instance_ssc0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_uart0.h" +#include "instance/instance_pwm.h" +#include "instance/instance_lcdc.h" +#include "instance/instance_isi.h" +#include "instance/instance_sfr.h" +#include "instance/instance_hsmci1.h" +#include "instance/instance_hsmci2.h" +#include "instance/instance_spi1.h" +#include "instance/instance_ssc1.h" +#include "instance/instance_adc.h" +#include "instance/instance_twi2.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usart3.h" +#include "instance/instance_uart1.h" +#include "instance/instance_emac.h" +#include "instance/instance_gmac.h" +#include "instance/instance_udphs.h" +#include "instance/instance_trng.h" +#include "instance/instance_smc.h" +#include "instance/instance_fuse.h" +#include "instance/instance_dmac0.h" +#include "instance/instance_dmac1.h" +#include "instance/instance_mpddrc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_dbgu.h" +#include "instance/instance_aic.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_pmc.h" +#include "instance/instance_rstc.h" +#include "instance/instance_shdwc.h" +#include "instance/instance_pit.h" +#include "instance/instance_wdt.h" +#include "instance/instance_sckc.h" +#include "instance/instance_bsc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rtc.h" +#include "instance/instance_aes.h" +#include "instance/instance_sha.h" +#include "instance/instance_tdes.h" +/*@}*/ + + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMA5D3x */ +/* ************************************************************************** */ +/** \addtogroup SAMA5D3x_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_FIQ ( 0) /**< \brief Advanced Interrupt Controller (FIQ) */ +#define ID_SYS ( 1) /**< \brief System Controller Interrupt (SYS) */ +#define ID_DBGU ( 2) /**< \brief Debug Unit Interrupt (DBGU) */ +#define ID_PIT ( 3) /**< \brief Periodic Interval Timer Interrupt (PIT) */ +#define ID_WDT ( 4) /**< \brief Watchdog timer Interrupt (WDT) */ +#define ID_SMC ( 5) /**< \brief Multi-bit ECC Interrupt (SMC) */ +#define ID_PIOA ( 6) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB ( 7) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC ( 8) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_PIOD ( 9) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (10) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_SMD (11) /**< \brief SMD Soft Modem (SMD) */ +#define ID_USART0 (12) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (13) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (14) /**< \brief USART 2 (USART2) */ +#define ID_USART3 (15) /**< \brief USART 3 (USART3) */ +#define ID_UART0 (16) /**< \brief UART 0 (UART0) */ +#define ID_UART1 (17) /**< \brief UART 1 (UART1) */ +#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_TWI2 (20) /**< \brief Two-Wire Interface 2 (TWI2) */ +#define ID_HSMCI0 (21) /**< \brief High Speed Multimedia Card Interface 0 (HSMCI0) */ +#define ID_HSMCI1 (22) /**< \brief High Speed Multimedia Card Interface 1 (HSMCI1) */ +#define ID_HSMCI2 (23) /**< \brief High Speed Multimedia Card Interface 2 (HSMCI2) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_TC0 (26) /**< \brief Timer Counter 0 (ch. 0, 1, 2) (TC0) */ +#define ID_TC1 (27) /**< \brief Timer Counter 1 (ch. 3, 4, 5) (TC1) */ +#define ID_PWM (28) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (29) /**< \brief Touch Screen ADC Controller (ADC) */ +#define ID_DMAC0 (30) /**< \brief DMA Controller 0 (DMAC0) */ +#define ID_DMAC1 (31) /**< \brief DMA Controller 1 (DMAC1) */ +#define ID_UHPHS (32) /**< \brief USB Host High Speed (UHPHS) */ +#define ID_UDPHS (33) /**< \brief USB Device High Speed (UDPHS) */ +#define ID_GMAC (34) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_EMAC (35) /**< \brief Ethernet MAC (EMAC) */ +#define ID_LCDC (36) /**< \brief LCD Controller (LCDC) */ +#define ID_ISI (37) /**< \brief Image Sensor Interface (ISI) */ +#define ID_SSC0 (38) /**< \brief Synchronous Serial Controller 0 (SSC0) */ +#define ID_SSC1 (39) /**< \brief Synchronous Serial Controller 1 (SSC1) */ +#define ID_CAN0 (40) /**< \brief CAN controller 0 (CAN0) */ +#define ID_CAN1 (41) /**< \brief CAN controller 1 (CAN1) */ +#define ID_SHA (42) /**< \brief Secure Hash Algorithm (SHA) */ +#define ID_AES (43) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TDES (44) /**< \brief Triple Data EncryptionStandard (TDES) */ +#define ID_TRNG (45) /**< \brief True Random Number Generator (TRNG) */ +#define ID_ARM (46) /**< \brief Performance Monitor Unit (ARM) */ +#define ID_IRQ (47) /**< \brief Advanced Interrupt Controller (IRQ) */ +#define ID_FUSE (48) /**< \brief Fuse Controller (FUSE) */ +#define ID_MPDDRC (49) /**< \brief MPDDR controller (MPDDRC) */ + +#define ID_PERIPH_COUNT (50) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMA5D3x */ +/* ************************************************************************** */ +/** \addtogroup SAMA5D3x_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SMD (0x00400000U) /**< \brief (SMD ) Base Address */ +#define AXIMX (0x00800000U) /**< \brief (AXIMX ) Base Address */ +#define HSMCI0 (0xF0000000U) /**< \brief (HSMCI0) Base Address */ +#define SPI0 (0xF0004000U) /**< \brief (SPI0 ) Base Address */ +#define SSC0 (0xF0008000U) /**< \brief (SSC0 ) Base Address */ +#define CAN0 (0xF000C000U) /**< \brief (CAN0 ) Base Address */ +#define TC0 (0xF0010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0xF0014000U) /**< \brief (TWI0 ) Base Address */ +#define TWI1 (0xF0018000U) /**< \brief (TWI1 ) Base Address */ +#define USART0 (0xF001C000U) /**< \brief (USART0) Base Address */ +#define USART1 (0xF0020000U) /**< \brief (USART1) Base Address */ +#define UART0 (0xF0024000U) /**< \brief (UART0 ) Base Address */ +#define GMAC (0xF0028000U) /**< \brief (GMAC ) Base Address */ +#define PWM (0xF002C000U) /**< \brief (PWM ) Base Address */ +#define LCDC (0xF0030000U) /**< \brief (LCDC ) Base Address */ +#define ISI (0xF0034000U) /**< \brief (ISI ) Base Address */ +#define SFR (0xF0038000U) /**< \brief (SFR ) Base Address */ +#define HSMCI1 (0xF8000000U) /**< \brief (HSMCI1) Base Address */ +#define HSMCI2 (0xF8004000U) /**< \brief (HSMCI2) Base Address */ +#define SPI1 (0xF8008000U) /**< \brief (SPI1 ) Base Address */ +#define SSC1 (0xF800C000U) /**< \brief (SSC1 ) Base Address */ +#define CAN1 (0xF8010000U) /**< \brief (CAN1 ) Base Address */ +#define TC1 (0xF8014000U) /**< \brief (TC1 ) Base Address */ +#define ADC (0xF8018000U) /**< \brief (ADC ) Base Address */ +#define TWI2 (0xF801C000U) /**< \brief (TWI2 ) Base Address */ +#define USART2 (0xF8020000U) /**< \brief (USART2) Base Address */ +#define USART3 (0xF8024000U) /**< \brief (USART3) Base Address */ +#define UART1 (0xF8028000U) /**< \brief (UART1 ) Base Address */ +#define EMAC (0xF802C000U) /**< \brief (EMAC ) Base Address */ +#define UDPHS (0xF8030000U) /**< \brief (UDPHS ) Base Address */ +#define SHA (0xF8034000U) /**< \brief (SHA ) Base Address */ +#define AES (0xF8038000U) /**< \brief (AES ) Base Address */ +#define TDES (0xF803C000U) /**< \brief (TDES ) Base Address */ +#define TRNG (0xF8040000U) /**< \brief (TRNG ) Base Address */ +#define SMC (0xFFFFC000U) /**< \brief (SMC ) Base Address */ +#define FUSE (0xFFFFE400U) /**< \brief (FUSE ) Base Address */ +#define DMAC0 (0xFFFFE600U) /**< \brief (DMAC0 ) Base Address */ +#define DMAC1 (0xFFFFE800U) /**< \brief (DMAC1 ) Base Address */ +#define MPDDRC (0xFFFFEA00U) /**< \brief (MPDDRC) Base Address */ +#define MATRIX (0xFFFFEC00U) /**< \brief (MATRIX) Base Address */ +#define DBGU (0xFFFFEE00U) /**< \brief (DBGU ) Base Address */ +#define AIC (0xFFFFF000U) /**< \brief (AIC ) Base Address */ +#define PIOA (0xFFFFF200U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0xFFFFF400U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0xFFFFF600U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0xFFFFF800U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0xFFFFFA00U) /**< \brief (PIOE ) Base Address */ +#define PMC (0xFFFFFC00U) /**< \brief (PMC ) Base Address */ +#define RSTC (0xFFFFFE00U) /**< \brief (RSTC ) Base Address */ +#define SHDWC (0xFFFFFE10U) /**< \brief (SHDWC ) Base Address */ +#define PIT (0xFFFFFE30U) /**< \brief (PIT ) Base Address */ +#define WDT (0xFFFFFE40U) /**< \brief (WDT ) Base Address */ +#define SCKC (0xFFFFFE50U) /**< \brief (SCKC ) Base Address */ +#define BSC (0xFFFFFE54U) /**< \brief (BSC ) Base Address */ +#define GPBR (0xFFFFFE60U) /**< \brief (GPBR ) Base Address */ +#define RTC (0xFFFFFEB0U) /**< \brief (RTC ) Base Address */ +#else +#define SMD ((Smd *)0x00400000U) /**< \brief (SMD ) Base Address */ +#define AXIMX ((Aximx *)0x00800000U) /**< \brief (AXIMX ) Base Address */ +#define HSMCI0 ((Hsmci *)0xF0000000U) /**< \brief (HSMCI0) Base Address */ +#define SPI0 ((Spi *)0xF0004000U) /**< \brief (SPI0 ) Base Address */ +#define SSC0 ((Ssc *)0xF0008000U) /**< \brief (SSC0 ) Base Address */ +#define CAN0 ((Can *)0xF000C000U) /**< \brief (CAN0 ) Base Address */ +#define TC0 ((Tc *)0xF0010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0xF0014000U) /**< \brief (TWI0 ) Base Address */ +#define TWI1 ((Twi *)0xF0018000U) /**< \brief (TWI1 ) Base Address */ +#define USART0 ((Usart *)0xF001C000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0xF0020000U) /**< \brief (USART1) Base Address */ +#define UART0 ((Uart *)0xF0024000U) /**< \brief (UART0 ) Base Address */ +#define GMAC ((Gmac *)0xF0028000U) /**< \brief (GMAC ) Base Address */ +#define PWM ((Pwm *)0xF002C000U) /**< \brief (PWM ) Base Address */ +#define LCDC ((Lcdc *)0xF0030000U) /**< \brief (LCDC ) Base Address */ +#define ISI ((Isi *)0xF0034000U) /**< \brief (ISI ) Base Address */ +#define SFR ((Sfr *)0xF0038000U) /**< \brief (SFR ) Base Address */ +#define HSMCI1 ((Hsmci *)0xF8000000U) /**< \brief (HSMCI1) Base Address */ +#define HSMCI2 ((Hsmci *)0xF8004000U) /**< \brief (HSMCI2) Base Address */ +#define SPI1 ((Spi *)0xF8008000U) /**< \brief (SPI1 ) Base Address */ +#define SSC1 ((Ssc *)0xF800C000U) /**< \brief (SSC1 ) Base Address */ +#define CAN1 ((Can *)0xF8010000U) /**< \brief (CAN1 ) Base Address */ +#define TC1 ((Tc *)0xF8014000U) /**< \brief (TC1 ) Base Address */ +#define ADC ((Adc *)0xF8018000U) /**< \brief (ADC ) Base Address */ +#define TWI2 ((Twi *)0xF801C000U) /**< \brief (TWI2 ) Base Address */ +#define USART2 ((Usart *)0xF8020000U) /**< \brief (USART2) Base Address */ +#define USART3 ((Usart *)0xF8024000U) /**< \brief (USART3) Base Address */ +#define UART1 ((Uart *)0xF8028000U) /**< \brief (UART1 ) Base Address */ +#define EMAC ((Emac *)0xF802C000U) /**< \brief (EMAC ) Base Address */ +#define UDPHS ((Udphs *)0xF8030000U) /**< \brief (UDPHS ) Base Address */ +#define SHA ((Sha *)0xF8034000U) /**< \brief (SHA ) Base Address */ +#define AES ((Aes *)0xF8038000U) /**< \brief (AES ) Base Address */ +#define TDES ((Tdes *)0xF803C000U) /**< \brief (TDES ) Base Address */ +#define TRNG ((Trng *)0xF8040000U) /**< \brief (TRNG ) Base Address */ +#define SMC ((Smc *)0xFFFFC000U) /**< \brief (SMC ) Base Address */ +#define FUSE ((Fuse *)0xFFFFE400U) /**< \brief (FUSE ) Base Address */ +#define DMAC0 ((Dmac *)0xFFFFE600U) /**< \brief (DMAC0 ) Base Address */ +#define DMAC1 ((Dmac *)0xFFFFE800U) /**< \brief (DMAC1 ) Base Address */ +#define MPDDRC ((Mpddrc *)0xFFFFEA00U) /**< \brief (MPDDRC) Base Address */ +#define MATRIX ((Matrix *)0xFFFFEC00U) /**< \brief (MATRIX) Base Address */ +#define DBGU ((Dbgu *)0xFFFFEE00U) /**< \brief (DBGU ) Base Address */ +#define AIC ((Aic *)0xFFFFF000U) /**< \brief (AIC ) Base Address */ +#define PIOA ((Pio *)0xFFFFF200U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0xFFFFF400U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0xFFFFF600U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0xFFFFF800U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0xFFFFFA00U) /**< \brief (PIOE ) Base Address */ +#define PMC ((Pmc *)0xFFFFFC00U) /**< \brief (PMC ) Base Address */ +#define RSTC ((Rstc *)0xFFFFFE00U) /**< \brief (RSTC ) Base Address */ +#define SHDWC ((Shdwc *)0xFFFFFE10U) /**< \brief (SHDWC ) Base Address */ +#define PIT ((Pit *)0xFFFFFE30U) /**< \brief (PIT ) Base Address */ +#define WDT ((Wdt *)0xFFFFFE40U) /**< \brief (WDT ) Base Address */ +#define SCKC ((Sckc *)0xFFFFFE50U) /**< \brief (SCKC ) Base Address */ +#define BSC ((Bsc *)0xFFFFFE54U) /**< \brief (BSC ) Base Address */ +#define GPBR ((Gpbr *)0xFFFFFE60U) /**< \brief (GPBR ) Base Address */ +#define RTC ((Rtc *)0xFFFFFEB0U) /**< \brief (RTC ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMA5D3x */ +/* ************************************************************************** */ +/** \addtogroup SAMA5D3x_pio Peripheral Pio Definitions */ +/*@{*/ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ +#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ +#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ +#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ +#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ +#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ +#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ +#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ +#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ +#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ +#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ +#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ +#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ +#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ +#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ +#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ +#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ +#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ +#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ +#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ +#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ +#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ +#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ +#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ +#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ +#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PD20A_AD0 (1u << 20) /**< \brief Adc signal: AD0 */ +#define PIO_PD21A_AD1 (1u << 21) /**< \brief Adc signal: AD1 */ +#define PIO_PD30A_AD10 (1u << 30) /**< \brief Adc signal: AD10 */ +#define PIO_PD31A_AD11 (1u << 31) /**< \brief Adc signal: AD11 */ +#define PIO_PD22A_AD2 (1u << 22) /**< \brief Adc signal: AD2 */ +#define PIO_PD23A_AD3 (1u << 23) /**< \brief Adc signal: AD3 */ +#define PIO_PD24A_AD4 (1u << 24) /**< \brief Adc signal: AD4 */ +#define PIO_PD25A_AD5 (1u << 25) /**< \brief Adc signal: AD5 */ +#define PIO_PD26A_AD6 (1u << 26) /**< \brief Adc signal: AD6 */ +#define PIO_PD27A_AD7 (1u << 27) /**< \brief Adc signal: AD7 */ +#define PIO_PD28A_AD8 (1u << 28) /**< \brief Adc signal: AD8 */ +#define PIO_PD29A_AD9 (1u << 29) /**< \brief Adc signal: AD9 */ +#define PIO_PD19A_ADTRG (1u << 19) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for AIC peripheral ========== */ +#define PIO_PC31A_FIQ (1u << 31) /**< \brief Aic signal: FIQ */ +#define PIO_PE31A_IRQ (1u << 31) /**< \brief Aic signal: IRQ */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PD14C_CANRX0 (1u << 14) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PD15C_CANTX0 (1u << 15) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB14B_CANRX1 (1u << 14) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB15B_CANTX1 (1u << 15) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DBGU peripheral ========== */ +#define PIO_PB30A_DRXD (1u << 30) /**< \brief Dbgu signal: DRXD */ +#define PIO_PB31A_DTXD (1u << 31) /**< \brief Dbgu signal: DTXD */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PE0A_A0 (1u << 0) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PE0A_NBS0 (1u << 0) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PE1A_A1 (1u << 1) /**< \brief Ebi signal: A1 */ +#define PIO_PE10A_A10 (1u << 10) /**< \brief Ebi signal: A10 */ +#define PIO_PE11A_A11 (1u << 11) /**< \brief Ebi signal: A11 */ +#define PIO_PE12A_A12 (1u << 12) /**< \brief Ebi signal: A12 */ +#define PIO_PE13A_A13 (1u << 13) /**< \brief Ebi signal: A13 */ +#define PIO_PE14A_A14 (1u << 14) /**< \brief Ebi signal: A14 */ +#define PIO_PE15A_A15 (1u << 15) /**< \brief Ebi signal: A15 */ +#define PIO_PE16A_A16 (1u << 16) /**< \brief Ebi signal: A16 */ +#define PIO_PE17A_A17 (1u << 17) /**< \brief Ebi signal: A17 */ +#define PIO_PE18A_A18 (1u << 18) /**< \brief Ebi signal: A18 */ +#define PIO_PE19A_A19 (1u << 19) /**< \brief Ebi signal: A19 */ +#define PIO_PE2A_A2 (1u << 2) /**< \brief Ebi signal: A2 */ +#define PIO_PE20A_A20 (1u << 20) /**< \brief Ebi signal: A20 */ +#define PIO_PE21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE23A_A23 (1u << 23) /**< \brief Ebi signal: A23 */ +#define PIO_PE24A_A24 (1u << 24) /**< \brief Ebi signal: A24 */ +#define PIO_PE25A_A25 (1u << 25) /**< \brief Ebi signal: A25 */ +#define PIO_PE3A_A3 (1u << 3) /**< \brief Ebi signal: A3 */ +#define PIO_PE4A_A4 (1u << 4) /**< \brief Ebi signal: A4 */ +#define PIO_PE5A_A5 (1u << 5) /**< \brief Ebi signal: A5 */ +#define PIO_PE6A_A6 (1u << 6) /**< \brief Ebi signal: A6 */ +#define PIO_PE7A_A7 (1u << 7) /**< \brief Ebi signal: A7 */ +#define PIO_PE8A_A8 (1u << 8) /**< \brief Ebi signal: A8 */ +#define PIO_PE9A_A9 (1u << 9) /**< \brief Ebi signal: A9 */ +#define PIO_PE26A_NCS0 (1u << 26) /**< \brief Ebi signal: NCS0 */ +#define PIO_PE27A_NCS1 (1u << 27) /**< \brief Ebi signal: NCS1 */ +#define PIO_PE28A_NCS2 (1u << 28) /**< \brief Ebi signal: NCS2 */ +#define PIO_PE30A_NWAIT (1u << 30) /**< \brief Ebi signal: NWAIT */ +#define PIO_PE29A_NWR1 (1u << 29) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PE29A_NBS1 (1u << 29) /**< \brief Ebi signal: NWR1/NBS1 */ +/* ========== Pio definition for EMAC peripheral ========== */ +#define PIO_PC5A_ECRSDV (1u << 5) /**< \brief Emac signal: ECRSDV */ +#define PIO_PC8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ +#define PIO_PC9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ +#define PIO_PC7A_EREFCK (1u << 7) /**< \brief Emac signal: EREFCK */ +#define PIO_PC2A_ERX0 (1u << 2) /**< \brief Emac signal: ERX0 */ +#define PIO_PC3A_ERX1 (1u << 3) /**< \brief Emac signal: ERX1 */ +#define PIO_PC6A_ERXER (1u << 6) /**< \brief Emac signal: ERXER */ +#define PIO_PC0A_ETX0 (1u << 0) /**< \brief Emac signal: ETX0 */ +#define PIO_PC1A_ETX1 (1u << 1) /**< \brief Emac signal: ETX1 */ +#define PIO_PC4A_ETXEN (1u << 4) /**< \brief Emac signal: ETXEN */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PB18A_G125CK (1u << 18) /**< \brief Gmac signal: G125CK */ +#define PIO_PB27B_G125CKO (1u << 27) /**< \brief Gmac signal: G125CKO */ +#define PIO_PB15A_GCOL (1u << 15) /**< \brief Gmac signal: GCOL */ +#define PIO_PB14A_GCRS (1u << 14) /**< \brief Gmac signal: GCRS */ +#define PIO_PB16A_GMDC (1u << 16) /**< \brief Gmac signal: GMDC */ +#define PIO_PB17A_GMDIO (1u << 17) /**< \brief Gmac signal: GMDIO */ +#define PIO_PB4A_GRX0 (1u << 4) /**< \brief Gmac signal: GRX0 */ +#define PIO_PB5A_GRX1 (1u << 5) /**< \brief Gmac signal: GRX1 */ +#define PIO_PB6A_GRX2 (1u << 6) /**< \brief Gmac signal: GRX2 */ +#define PIO_PB7A_GRX3 (1u << 7) /**< \brief Gmac signal: GRX3 */ +#define PIO_PB23B_GRX4 (1u << 23) /**< \brief Gmac signal: GRX4 */ +#define PIO_PB24B_GRX5 (1u << 24) /**< \brief Gmac signal: GRX5 */ +#define PIO_PB25B_GRX6 (1u << 25) /**< \brief Gmac signal: GRX6 */ +#define PIO_PB26B_GRX7 (1u << 26) /**< \brief Gmac signal: GRX7 */ +#define PIO_PB11A_GRXCK (1u << 11) /**< \brief Gmac signal: GRXCK */ +#define PIO_PB12A_GRXDV (1u << 12) /**< \brief Gmac signal: GRXDV */ +#define PIO_PB13A_GRXER (1u << 13) /**< \brief Gmac signal: GRXER */ +#define PIO_PB0A_GTX0 (1u << 0) /**< \brief Gmac signal: GTX0 */ +#define PIO_PB1A_GTX1 (1u << 1) /**< \brief Gmac signal: GTX1 */ +#define PIO_PB2A_GTX2 (1u << 2) /**< \brief Gmac signal: GTX2 */ +#define PIO_PB3A_GTX3 (1u << 3) /**< \brief Gmac signal: GTX3 */ +#define PIO_PB19B_GTX4 (1u << 19) /**< \brief Gmac signal: GTX4 */ +#define PIO_PB20B_GTX5 (1u << 20) /**< \brief Gmac signal: GTX5 */ +#define PIO_PB21B_GTX6 (1u << 21) /**< \brief Gmac signal: GTX6 */ +#define PIO_PB22B_GTX7 (1u << 22) /**< \brief Gmac signal: GTX7 */ +#define PIO_PB8A_GTXCK (1u << 8) /**< \brief Gmac signal: GTXCK */ +#define PIO_PB9A_GTXEN (1u << 9) /**< \brief Gmac signal: GTXEN */ +#define PIO_PB10A_GTXER (1u << 10) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI0 peripheral ========== */ +#define PIO_PD0A_MCI0_CDA (1u << 0) /**< \brief Hsmci0 signal: MCI0_CDA */ +#define PIO_PD9A_MCI0_CK (1u << 9) /**< \brief Hsmci0 signal: MCI0_CK */ +#define PIO_PD1A_MCI0_DA0 (1u << 1) /**< \brief Hsmci0 signal: MCI0_DA0 */ +#define PIO_PD2A_MCI0_DA1 (1u << 2) /**< \brief Hsmci0 signal: MCI0_DA1 */ +#define PIO_PD3A_MCI0_DA2 (1u << 3) /**< \brief Hsmci0 signal: MCI0_DA2 */ +#define PIO_PD4A_MCI0_DA3 (1u << 4) /**< \brief Hsmci0 signal: MCI0_DA3 */ +#define PIO_PD5A_MCI0_DA4 (1u << 5) /**< \brief Hsmci0 signal: MCI0_DA4 */ +#define PIO_PD6A_MCI0_DA5 (1u << 6) /**< \brief Hsmci0 signal: MCI0_DA5 */ +#define PIO_PD7A_MCI0_DA6 (1u << 7) /**< \brief Hsmci0 signal: MCI0_DA6 */ +#define PIO_PD8A_MCI0_DA7 (1u << 8) /**< \brief Hsmci0 signal: MCI0_DA7 */ +/* ========== Pio definition for HSMCI1 peripheral ========== */ +#define PIO_PB19A_MCI1_CDA (1u << 19) /**< \brief Hsmci1 signal: MCI1_CDA */ +#define PIO_PB24A_MCI1_CK (1u << 24) /**< \brief Hsmci1 signal: MCI1_CK */ +#define PIO_PB20A_MCI1_DA0 (1u << 20) /**< \brief Hsmci1 signal: MCI1_DA0 */ +#define PIO_PB21A_MCI1_DA1 (1u << 21) /**< \brief Hsmci1 signal: MCI1_DA1 */ +#define PIO_PB22A_MCI1_DA2 (1u << 22) /**< \brief Hsmci1 signal: MCI1_DA2 */ +#define PIO_PB23A_MCI1_DA3 (1u << 23) /**< \brief Hsmci1 signal: MCI1_DA3 */ +/* ========== Pio definition for HSMCI2 peripheral ========== */ +#define PIO_PC10A_MCI2_CDA (1u << 10) /**< \brief Hsmci2 signal: MCI2_CDA */ +#define PIO_PC15A_MCI2_CK (1u << 15) /**< \brief Hsmci2 signal: MCI2_CK */ +#define PIO_PC11A_MCI2_DA0 (1u << 11) /**< \brief Hsmci2 signal: MCI2_DA0 */ +#define PIO_PC12A_MCI2_DA1 (1u << 12) /**< \brief Hsmci2 signal: MCI2_DA1 */ +#define PIO_PC13A_MCI2_DA2 (1u << 13) /**< \brief Hsmci2 signal: MCI2_DA2 */ +#define PIO_PC14A_MCI2_DA3 (1u << 14) /**< \brief Hsmci2 signal: MCI2_DA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PA16C_ISI_D0 (1u << 16) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PA17C_ISI_D1 (1u << 17) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PC27C_ISI_D10 (1u << 27) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PC26C_ISI_D11 (1u << 26) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PA18C_ISI_D2 (1u << 18) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA19C_ISI_D3 (1u << 19) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA20C_ISI_D4 (1u << 20) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PA21C_ISI_D5 (1u << 21) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PA22C_ISI_D6 (1u << 22) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA23C_ISI_D7 (1u << 23) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PC29C_ISI_D8 (1u << 29) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PC28C_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PA31C_ISI_HSYNC (1u << 31) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PC30C_ISI_PCK (1u << 30) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PA30C_ISI_VSYNC (1u << 30) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for LCDC peripheral ========== */ +#define PIO_PA0A_LCDDAT0 (1u << 0) /**< \brief Lcdc signal: LCDDAT0 */ +#define PIO_PA1A_LCDDAT1 (1u << 1) /**< \brief Lcdc signal: LCDDAT1 */ +#define PIO_PA10A_LCDDAT10 (1u << 10) /**< \brief Lcdc signal: LCDDAT10 */ +#define PIO_PA11A_LCDDAT11 (1u << 11) /**< \brief Lcdc signal: LCDDAT11 */ +#define PIO_PA12A_LCDDAT12 (1u << 12) /**< \brief Lcdc signal: LCDDAT12 */ +#define PIO_PA13A_LCDDAT13 (1u << 13) /**< \brief Lcdc signal: LCDDAT13 */ +#define PIO_PA14A_LCDDAT14 (1u << 14) /**< \brief Lcdc signal: LCDDAT14 */ +#define PIO_PA15A_LCDDAT15 (1u << 15) /**< \brief Lcdc signal: LCDDAT15 */ +#define PIO_PA16A_LCDDAT16 (1u << 16) /**< \brief Lcdc signal: LCDDAT16 */ +#define PIO_PC14C_LCDDAT16 (1u << 14) /**< \brief Lcdc signal: LCDDAT16 */ +#define PIO_PA17A_LCDDAT17 (1u << 17) /**< \brief Lcdc signal: LCDDAT17 */ +#define PIO_PC13C_LCDDAT17 (1u << 13) /**< \brief Lcdc signal: LCDDAT17 */ +#define PIO_PA18A_LCDDAT18 (1u << 18) /**< \brief Lcdc signal: LCDDAT18 */ +#define PIO_PC12C_LCDDAT18 (1u << 12) /**< \brief Lcdc signal: LCDDAT18 */ +#define PIO_PA19A_LCDDAT19 (1u << 19) /**< \brief Lcdc signal: LCDDAT19 */ +#define PIO_PC11C_LCDDAT19 (1u << 11) /**< \brief Lcdc signal: LCDDAT19 */ +#define PIO_PA2A_LCDDAT2 (1u << 2) /**< \brief Lcdc signal: LCDDAT2 */ +#define PIO_PA20A_LCDDAT20 (1u << 20) /**< \brief Lcdc signal: LCDDAT20 */ +#define PIO_PC10C_LCDDAT20 (1u << 10) /**< \brief Lcdc signal: LCDDAT20 */ +#define PIO_PA21A_LCDDAT21 (1u << 21) /**< \brief Lcdc signal: LCDDAT21 */ +#define PIO_PC15C_LCDDAT21 (1u << 15) /**< \brief Lcdc signal: LCDDAT21 */ +#define PIO_PA22A_LCDDAT22 (1u << 22) /**< \brief Lcdc signal: LCDDAT22 */ +#define PIO_PE27C_LCDDAT22 (1u << 27) /**< \brief Lcdc signal: LCDDAT22 */ +#define PIO_PA23A_LCDDAT23 (1u << 23) /**< \brief Lcdc signal: LCDDAT23 */ +#define PIO_PE28C_LCDDAT23 (1u << 28) /**< \brief Lcdc signal: LCDDAT23 */ +#define PIO_PA3A_LCDDAT3 (1u << 3) /**< \brief Lcdc signal: LCDDAT3 */ +#define PIO_PA4A_LCDDAT4 (1u << 4) /**< \brief Lcdc signal: LCDDAT4 */ +#define PIO_PA5A_LCDDAT5 (1u << 5) /**< \brief Lcdc signal: LCDDAT5 */ +#define PIO_PA6A_LCDDAT6 (1u << 6) /**< \brief Lcdc signal: LCDDAT6 */ +#define PIO_PA7A_LCDDAT7 (1u << 7) /**< \brief Lcdc signal: LCDDAT7 */ +#define PIO_PA8A_LCDDAT8 (1u << 8) /**< \brief Lcdc signal: LCDDAT8 */ +#define PIO_PA9A_LCDDAT9 (1u << 9) /**< \brief Lcdc signal: LCDDAT9 */ +#define PIO_PA29A_LCDDEN (1u << 29) /**< \brief Lcdc signal: LCDDEN */ +#define PIO_PA25A_LCDDISP (1u << 25) /**< \brief Lcdc signal: LCDDISP */ +#define PIO_PA27A_LCDHSYNC (1u << 27) /**< \brief Lcdc signal: LCDHSYNC */ +#define PIO_PA28A_LCDPCK (1u << 28) /**< \brief Lcdc signal: LCDPCK */ +#define PIO_PA24A_LCDPWM (1u << 24) /**< \brief Lcdc signal: LCDPWM */ +#define PIO_PA26A_LCDVSYNC (1u << 26) /**< \brief Lcdc signal: LCDVSYNC */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PD30B_PCK0 (1u << 30) /**< \brief Pmc signal: PCK0 */ +#define PIO_PD31B_PCK1 (1u << 31) /**< \brief Pmc signal: PCK1 */ +#define PIO_PC15B_PCK2 (1u << 15) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PC28B_PWMFI0 (1u << 28) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PC31B_PWMFI1 (1u << 31) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PC29B_PWMFI2 (1u << 29) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PD16C_PWMFI3 (1u << 16) /**< \brief Pwm signal: PWMFI3 */ +#define PIO_PA20B_PWMH0 (1u << 20) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0B_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA22B_PWMH1 (1u << 22) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB4B_PWMH1 (1u << 4) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB27C_PWMH1 (1u << 27) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB8B_PWMH2 (1u << 8) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PD5C_PWMH2 (1u << 5) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB12B_PWMH3 (1u << 12) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PD7C_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB1B_PWML0 (1u << 1) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA23B_PWML1 (1u << 23) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB5B_PWML1 (1u << 5) /**< \brief Pwm signal: PWML1 */ +#define PIO_PE31B_PWML1 (1u << 31) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */ +#define PIO_PD6C_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13B_PWML3 (1u << 13) /**< \brief Pwm signal: PWML3 */ +#define PIO_PD8C_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD10A_SPI0_MISO (1u << 10) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD11A_SPI0_MOSI (1u << 11) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PD13A_SPI0_NPCS0 (1u << 13) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PD14B_SPI0_NPCS1 (1u << 14) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD15B_SPI0_NPCS2 (1u << 15) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD16B_SPI0_NPCS3 (1u << 16) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD12A_SPI0_SPCK (1u << 12) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC22A_SPI1_MISO (1u << 22) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC23A_SPI1_MOSI (1u << 23) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25A_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC26A_SPI1_NPCS1 (1u << 26) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC27A_SPI1_NPCS2 (1u << 27) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC28A_SPI1_NPCS3 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24A_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC0 peripheral ========== */ +#define PIO_PC21A_RD0 (1u << 21) /**< \brief Ssc0 signal: RD0 */ +#define PIO_PC20A_RF0 (1u << 20) /**< \brief Ssc0 signal: RF0 */ +#define PIO_PC19A_RK0 (1u << 19) /**< \brief Ssc0 signal: RK0 */ +#define PIO_PC18A_TD0 (1u << 18) /**< \brief Ssc0 signal: TD0 */ +#define PIO_PC17A_TF0 (1u << 17) /**< \brief Ssc0 signal: TF0 */ +#define PIO_PC16A_TK0 (1u << 16) /**< \brief Ssc0 signal: TK0 */ +/* ========== Pio definition for SSC1 peripheral ========== */ +#define PIO_PB11B_RD1 (1u << 11) /**< \brief Ssc1 signal: RD1 */ +#define PIO_PB10B_RF1 (1u << 10) /**< \brief Ssc1 signal: RF1 */ +#define PIO_PB7B_RK1 (1u << 7) /**< \brief Ssc1 signal: RK1 */ +#define PIO_PB6B_TD1 (1u << 6) /**< \brief Ssc1 signal: TD1 */ +#define PIO_PB3B_TF1 (1u << 3) /**< \brief Ssc1 signal: TF1 */ +#define PIO_PB2B_TK1 (1u << 2) /**< \brief Ssc1 signal: TK1 */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PD7B_TCLK0 (1u << 7) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PC14B_TCLK1 (1u << 14) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PE29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PD5B_TIOA0 (1u << 5) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PC12B_TIOA1 (1u << 12) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PE27B_TIOA2 (1u << 27) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PD6B_TIOB0 (1u << 6) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PC13B_TIOB1 (1u << 13) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PE28B_TIOB2 (1u << 28) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC2B_TCLK3 (1u << 2) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC5B_TCLK4 (1u << 5) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC8B_TCLK5 (1u << 8) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC3B_TIOA4 (1u << 3) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC6B_TIOA5 (1u << 6) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC4B_TIOB4 (1u << 4) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC7B_TIOB5 (1u << 7) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA31A_TWCK0 (1u << 31) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA30A_TWD0 (1u << 30) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PC27B_TWCK1 (1u << 27) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PC26B_TWD1 (1u << 26) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for TWI2 peripheral ========== */ +#define PIO_PA19B_TWCK2 (1u << 19) /**< \brief Twi2 signal: TWCK2 */ +#define PIO_PA18B_TWD2 (1u << 18) /**< \brief Twi2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PC29A_URXD0 (1u << 29) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PC30A_UTXD0 (1u << 30) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA30B_URXD1 (1u << 30) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA31B_UTXD1 (1u << 31) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PD15A_CTS0 (1u << 15) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD16A_RTS0 (1u << 16) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PD17A_RXD0 (1u << 17) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PD14A_SCK0 (1u << 14) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PD18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PB26A_CTS1 (1u << 26) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PB27A_RTS1 (1u << 27) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PB28A_RXD1 (1u << 28) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PB25A_SCK1 (1u << 25) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB29A_TXD1 (1u << 29) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PE23B_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PE24B_RTS2 (1u << 24) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PE25B_RXD2 (1u << 25) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PE20B_SCK2 (1u << 20) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PE26B_TXD2 (1u << 26) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PE16B_CTS3 (1u << 16) /**< \brief Usart3 signal: CTS3 */ +#define PIO_PE17B_RTS3 (1u << 17) /**< \brief Usart3 signal: RTS3 */ +#define PIO_PE18B_RXD3 (1u << 18) /**< \brief Usart3 signal: RXD3 */ +#define PIO_PE15B_SCK3 (1u << 15) /**< \brief Usart3 signal: SCK3 */ +#define PIO_PE19B_TXD3 (1u << 19) /**< \brief Usart3 signal: TXD3 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 +#define PIO_PE6_IDX 134 +#define PIO_PE7_IDX 135 +#define PIO_PE8_IDX 136 +#define PIO_PE9_IDX 137 +#define PIO_PE10_IDX 138 +#define PIO_PE11_IDX 139 +#define PIO_PE12_IDX 140 +#define PIO_PE13_IDX 141 +#define PIO_PE14_IDX 142 +#define PIO_PE15_IDX 143 +#define PIO_PE16_IDX 144 +#define PIO_PE17_IDX 145 +#define PIO_PE18_IDX 146 +#define PIO_PE19_IDX 147 +#define PIO_PE20_IDX 148 +#define PIO_PE21_IDX 149 +#define PIO_PE22_IDX 150 +#define PIO_PE23_IDX 151 +#define PIO_PE24_IDX 152 +#define PIO_PE25_IDX 153 +#define PIO_PE26_IDX 154 +#define PIO_PE27_IDX 155 +#define PIO_PE28_IDX 156 +#define PIO_PE29_IDX 157 +#define PIO_PE30_IDX 158 +#define PIO_PE31_IDX 159 +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMA5D3x */ +/* ************************************************************************** */ + +#define IRAM0_SIZE (0x10000u) +#define IRAM1_SIZE (0x10000u) +#define IROM_SIZE (0x20000u) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define EBI_CS0_ADDR (0x10000000u) /**< EBI Chip Select 0 base address */ +#define DDR_CS_ADDR (0x20000000u) /**< DDR Chip Select base address */ +#define EBI_CS1_ADDR (0x40000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x50000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x60000000u) /**< EBI Chip Select 3 base address */ +#define EBI_NF_ADDR (0x60000000u) /**< NAND Flash on EBI Chip Select 3 base address */ +#define NFC_ADDR (0x70000000u) /**< NAND Flash Controller Command base address */ +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x00300000u) /**< Internal RAM 0 base address */ +#if defined IRAM0_SIZE +#define IRAM1_ADDR (IRAM0_ADDR+IRAM0_SIZE) /**< Internal RAM 1 base address */ +#endif +#define SMD_ADDR (0x00400000u) /**< Software Modem Device base address */ +#define UDPHS_RAM_ADDR (0x00500000u) /**< USB High Speed Device Port RAM base address */ +#define UHP_OHCI_ADDR (0x00600000u) /**< USB Host Port OHCI base address */ +#define UHP_EHCI_ADDR (0x00700000u) /**< USB Host Port EHCI base address */ +#define AXIMX_ADDR (0x00800000u) /**< AXI Bus Matrix base address */ +#define DAP_ADDR (0x00900000u) /**< Debug Access Port base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMA5D3x */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMA5D3x_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/USBD_Config.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/USBD_Config.h new file mode 100644 index 000000000..5155d93dd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/USBD_Config.h @@ -0,0 +1,305 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * USB Device Framework configurations. + * + */ + +#ifndef USBD_CONFIG_H +#define USBD_CONFIG_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/** \addtogroup usbd_config + *@{ + */ +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_ids USBD Device IDs + * @{ + */ +#define USBD_VID_ATMEL 0x03EB /**< Vendor ID: Atmel */ + +#define USBD_PID_ENUM 0x0001 /**< Product ID: Enum (Core) */ +#define USBD_PID_CDCDSERIAL 0x6119 /**< Product ID: CDC Serial */ +#define USBD_PID_HIDKEYBOARD 0x6127 /**< Product ID: HID Keyboard */ +#define USBD_PID_AUDIO 0x6128 /**< Product ID: Audio devices */ +#define USBD_PID_MSD 0x6129 /**< Product ID: Massstorage */ +#define USBD_PID_CDCHID 0x6130 /**< Product ID: composite */ +#define USBD_PID_CDCAUDIO 0x6131 /**< Product ID: composite */ +#define USBD_PID_CDCMSD 0x6132 /**< Product ID: composite */ +#define USBD_PID_CDCCDC 0x6133 /**< Product ID: composite */ +#define USBD_PID_HIDAUDIO 0x6134 /**< Product ID: composite */ +#define USBD_PID_HIDMSD 0x6135 /**< Product ID: composite */ +#define USBD_PID_HIDMOUSE 0x6200 /**< Product ID: HID Mouse */ +#define USBD_PID_HIDTRANSFER 0x6201 /**< Product ID: HID Transfer */ +#define USBD_PID_CCID 0x6203 /**< Product ID: CCID */ + +#define USBD_RELEASE_1_00 0x0100 /**< Release: 1.00 */ +/** @}*/ + +/** \addtogroup usbd_general_config USBD General Configure + * @{ + * This page lists general configurations for all USB device drivers. + * - \ref USBD_BMATTRIBUTES + */ +/** default USB Device attributes configuration descriptor + * (bus or self powered, remote wakeup) */ +#define USBD_BMATTRIBUTES BOARD_USB_BMATTRIBUTES +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Mass storage + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_msdd_config USB MassStorage Configure + * @{ + * This page lists the defines used by the Mass Storage driver. + * + * \section msd_ep_addr Endpoint Addresses + * - \ref MSDDriverDescriptors_BULKOUT + * - \ref MSDDriverDescriptors_BULKIN + */ +/** Address of the Mass Storage bulk-out endpoint.*/ +#define MSDDriverDescriptors_BULKOUT 1 +/** Address of the Mass Storage bulk-in endpoint.*/ +#define MSDDriverDescriptors_BULKIN 2 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - CDC Serial + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_cdc_serial_config USB CDC Serial Configure + * @{ + * This page lists the defines used by the CDC Serial Device Driver. + * + * \section cdcd_ep_addr Endpoint Addresses + * - \ref CDCDSerialDriverDescriptors_DATAOUT + * - \ref CDCDSerialDriverDescriptors_DATAIN + * - \ref CDCDSerialDriverDescriptors_NOTIFICATION + */ +/** Data OUT endpoint number */ +#define CDCDSerialDriverDescriptors_DATAOUT 1 +/** Data IN endpoint number */ +#define CDCDSerialDriverDescriptors_DATAIN 2 +/** Notification endpoint number */ +#define CDCDSerialDriverDescriptors_NOTIFICATION 3 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Audio + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_audio_config USB Audio General Configure + * @{ + * This page lists definitions for USB Audio Devices Drivers. + * - \ref + */ +#if defined(at91sam7s) || defined(at91sam9xe) + /** Sample rate in Hz. */ + #define AUDDevice_SAMPLERATE 32000UL + /** Number of channels in audio stream. */ + #define AUDDevice_NUMCHANNELS 1 + /** Number of bytes in one sample. */ + #define AUDDevice_BYTESPERSAMPLE 2 +#else + /** Sample rate in Hz. */ + #define AUDDevice_SAMPLERATE 48000UL + /** Number of channels in audio stream. */ + #define AUDDevice_NUMCHANNELS 2 + /** Number of bytes in one sample. */ + #define AUDDevice_BYTESPERSAMPLE 2 +#endif +/** Number of bits in one sample. */ +#define AUDDevice_BITSPERSAMPLE (AUDDevice_BYTESPERSAMPLE * 8) +/** Number of bytes in one USB subframe. */ +#define AUDDevice_BYTESPERSUBFRAME (AUDDevice_NUMCHANNELS * \ + AUDDevice_BYTESPERSAMPLE) +/** Number of samples in one USB frame. */ +#define AUDDevice_SAMPLESPERFRAME (AUDDevice_SAMPLERATE / 1000 \ + * AUDDevice_NUMCHANNELS) +/** Number of bytes in one USB frame. */ +#define AUDDevice_BYTESPERFRAME (AUDDevice_SAMPLESPERFRAME * \ + AUDDevice_BYTESPERSAMPLE) +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Audio - Desktop Speaker + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_audio_speaker_config USB Speaker Configure + * @{ + * This page lists the definitions for USB Audio Speaker Device Driver. + * - \ref AUDDSpeakerDriverDescriptors_DATAOUT + * - \ref AUDDSpeakerDriverDescriptors_FS_INTERVAL + * - \ref AUDDSpeakerDriverDescriptors_HS_INTERVAL + * + * \note for UDP, uses IN EPs that support double buffer; for UDPHS, uses + * IN EPs that support DMA and High bandwidth. + */ +/** Data out endpoint number. */ +#define AUDDSpeakerDriverDescriptors_DATAOUT 0x04 +/** Endpoint polling interval 2^(x-1) * 125us */ +#define AUDDSpeakerDriverDescriptors_HS_INTERVAL 0x04 +/** Endpoint polling interval 2^(x-1) * ms */ +#define AUDDSpeakerDriverDescriptors_FS_INTERVAL 0x01 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Audio - Speaker Phone + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_audio_speakerphone_config USB Speaker Phone Configure + * @{ + * This page lists the definitions for USB Audio Speaker Phone Device Driver. + * - \ref AUDDSpeakerPhoneDriverDescriptors_DATAOUT + * - \ref AUDDSpeakerPhoneDriverDescriptors_DATAIN + * - \ref AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL + * - \ref AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL + */ + +#if defined(at91sam7s) || defined(at91sam9xe) + /** Data out endpoint number, size 64B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x01 + /** Data in endpoint number, size 64B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x02 +#elif defined(CHIP_USB_UDP) + /** Data out endpoint number, size 192B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x04 + /** Data in endpoint number, size 192B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x05 +#elif defined(at91sam9m10ek) + /** Data out endpoint number, size 192B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x01 + /** Data in endpoint number, size 192B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x06 +#else + /** Data out endpoint number, size 192B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x05 + /** Data in endpoint number, size 192B */ + #define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x06 +#endif +/** Endpoint polling interval 2^(x-1) * 125us */ +#define AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL 0x04 +/** Endpoint polling interval 2^(x-1) * ms */ +#define AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL 0x01 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - HID - Keyboard + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_hid_keyboard_config USB HID Keyboard Device Configure + * @{ + * This page lists the defines used by the HID Keyboard Device Driver. + * + * \section hidd_k_ep_addr Endpoint Addresses + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT + * \section hidd_k_ep_polling Endpoint Polling Rate + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING + */ +/** Interrupt IN endpoint number */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTIN 1 +/** Interrupt IN endpoint polling rate (in milliseconds) */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING 10 +/** Interrupt OUT endpoint number */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT 2 +/** Interrupt OUT endpoint polling rate (in milliseconds) */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING 10 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - HID - Mouse + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_hid_mouse_config USB HID Mouse Device Configure + * @{ + * This page lists the defines used by the HID Mouse Device Driver. + * + * \section hidd_m_ep_addr Endpoint Addresses + * - \ref HIDDMouseDriverDescriptors_INTERRUPTIN + * \section hidd_m_ep_polling Endpoint Polling Rate + * - \ref HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING + */ +/** Interrupt IN endpoint number */ +#define HIDDMouseDriverDescriptors_INTERRUPTIN 1 +/** Interrupt IN endpoint polling rate (in milliseconds) */ +#define HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING 10 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - HID - Transfer (Customize device) + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_hid_xfr_config USB HID Transfer Device Configure + * @{ + * This page lists the defines used by the HID Transfer Device Driver. + * + * \section hidd_t_ep_addr Endpoint Addresses + * - \ref HIDDTransferDriverDescriptors_INTERRUPTIN + * - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT + * \section hidd_t_ep_polling Endpoint Polling Rate + * - \ref HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING + * - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING + */ +/** Interrupt IN endpoint number. */ +#define HIDDTransferDriverDescriptors_INTERRUPTIN 1 +/** Polling rate in ms */ +#define HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING 50 +/** Interrupt IN endpoint polling rate (in milliseconds). */ +#define HIDDTransferDriverDescriptors_INTERRUPTOUT 2 +/** Polling rate in ms */ +#define HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING 50 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Composite + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_composite_config USB Composite Device Configure + * @{ + */ +/** @}*/ + +/**@}*/ +#endif //#ifndef USBD_CONFIG_H + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/USBD_LEDs.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/USBD_LEDs.h new file mode 100644 index 000000000..3772c96e0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/USBD_LEDs.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Collection of LEDs for using the USB device controller on AT91 + * microcontrollers. + */ + +#ifndef USBDLEDS_H +#define USBDLEDS_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/** \addtogroup usbd_hal + *@{ + */ +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_leds USB Device LEDs + * @{ + * This page lists the LEDs used in the USB %device driver. + * + * - USBD_LEDPOWER + * - USBD_LEDUSB + * - USBD_LEDOTHER + */ + +/** LED for indicating that the device is powered. */ +#define USBD_LEDPOWER 0 +/** LED for indicating USB activity. */ +#define USBD_LEDUSB 1 +/** LED for custom usage. */ +#define USBD_LEDOTHER 2 +/** @}*/ + +/**@}*/ + +#endif //#ifndef USBDLEDS_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/adc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/adc.h new file mode 100644 index 000000000..9ecce25d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/adc.h @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ADC. + * -# Initialize the ADC with ADC_Initialize(). + * -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming(). + * -# Select the active channel using ADC_EnableChannel(). + * -# Start the conversion with ADC_StartConversion(). + * -# Wait the end of the conversion by polling status with ADC_GetStatus(). + * -# Finally, get the converted data using ADC_GetConvertedData() or ADC_GetLastConvertedData(). + * +*/ +#ifndef _ADC_ +#define _ADC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* Max. ADC Clock Frequency (Hz) */ +#define ADC_CLOCK_MAX 20000000 + +/* Max. normal ADC startup time (us) */ +#define ADC_STARTUP_NORMAL_MAX 40 +/* Max. fast ADC startup time (us) */ +#define ADC_STARTUP_FAST_MAX 12 + +/* Definitions for ADC channels */ +#define ADC_CHANNEL_0 0 +#define ADC_CHANNEL_1 1 +#define ADC_CHANNEL_2 2 +#define ADC_CHANNEL_3 3 +#define ADC_CHANNEL_4 4 +#define ADC_CHANNEL_5 5 +#define ADC_CHANNEL_6 6 +#define ADC_CHANNEL_7 7 +#define ADC_CHANNEL_8 8 +#define ADC_CHANNEL_9 9 +#define ADC_CHANNEL_10 10 +#define ADC_CHANNEL_11 11 +#define ADC_CHANNEL_12 12 +#define ADC_CHANNEL_13 13 +#define ADC_CHANNEL_14 14 +#define ADC_CHANNEL_15 15 + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define ADC_GetModeReg( pAdc ) ((pAdc)->ADC_MR) + +#define ADC_StartConversion( pAdc ) ((pAdc)->ADC_CR = ADC_CR_START) + +#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL) + +#define ADC_EnableChannel( pAdc, dwChannel ) {\ + (pAdc)->ADC_CHER = (1 << (dwChannel));\ + } + +#define ADC_DisableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHDR = (1 << (dwChannel));\ + } + +#define ADC_EnableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IER = (dwMode);\ + } + +#define ADC_DisableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IDR = (dwMode);\ + } + +#define ADC_SetChannelGain(pAdc,dwMode) {\ + (pAdc)->ADC_CGR = dwMode;\ + } + +#define ADC_SetChannelOffset(pAdc,dwMode) {\ + (pAdc)->ADC_COR = dwMode;\ + } + +#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY) + +#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) + +#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk)) + +#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) + +#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) + +#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ADC_Initialize( Adc* pAdc, uint32_t dwId ); +extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwPres, uint32_t dwMck ); +extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling ); +extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel ); +extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis ); +extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 ); +extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh ); +extern void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ; +extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ; +extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ; +extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ; +extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ; +extern void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv); +extern uint32_t ADC_GetTsXPosition(Adc *pADC); +extern uint32_t ADC_GetTsYPosition(Adc *pADC); +extern uint32_t ADC_GetTsPressure(Adc *pADC); +extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime); +extern void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis); +extern void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs ); +extern void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs ); +extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod); +extern void ADC_SetTsMode(Adc* pADC, uint32_t dwMode); +extern void ADC_TsCalibration( Adc *pAdc ); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ADC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/aes.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/aes.h new file mode 100644 index 000000000..d67940b0d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/aes.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _AES_ +#define _AES_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define AES_MR_CIPHER_ENCRYPT 1 +#define AES_MR_CIPHER_DECRYPT 0 +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +extern void AES_Start(void); +extern void AES_SoftReset(void); +extern void AES_Recount(void); +extern void AES_Configure(uint32_t mode); +extern void AES_EnableIt(uint32_t sources); +extern void AES_DisableIt(uint32_t sources); +extern uint32_t AES_GetStatus(void); +extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength); +extern void AES_SetInput(uint32_t *data); +extern void AES_GetOutput(uint32_t *data); +extern void AES_SetVector(const uint32_t *pVector); +extern void AES_SetAadLen(uint32_t len); +extern void AES_SetDataLen(uint32_t len); +extern void AES_SetGcmHash(uint32_t * hash); +extern void AES_GetGcmTag(uint32_t * tag); +extern void AES_GetGcmCounter(uint32_t * counter); +extern void AES_GetGcmH(uint32_t *h); + + +#endif /* #ifndef _AES_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/async.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/async.h new file mode 100644 index 000000000..37d49b60c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/async.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Provide a routine for asynchronous transfer. + * + */ + +#ifndef _ASYNC_ +#define _ASYNC_ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +/** Transfer is still pending.*/ +#define ASYNC_STATUS_PENDING 0xFF + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +/** \brief Asynchronous transfer descriptor. */ +typedef struct _Async +{ + /** Asynchronous transfer status.*/ + volatile uint32_t status ; + /** Callback function to invoke when transfer completes or fails.*/ + void *callback ; + /** Driver storage area; do not use.*/ + uint8_t pStorage[9] ; +} Async ; + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ +extern uint32_t ASYNC_IsFinished( Async* pAsync ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ASYNC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/can.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/can.h new file mode 100644 index 000000000..b594dc049 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/can.h @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * Definitions and prototypes for Controller Area Network (CAN) + * peripheral operations. + */ + +/** \ingroup lib_chip + * \ingroup cand_module + * \addtogroup can_module Working with CAN + * + * \section Purpose + * Interface for Controller Area Network (CAN). + * + * \section Usage + * + * Before CAN operation, its peripheral clock should be enabled, see + * PMC_EnablePeripheral(). + * + * Modify CAN registers or register fields with API functions: + * - Modify CAN Mode register with CAN_ConfigureMode(). + * - Enable/Disable CAN with CAN_Enable(). + * - Change CAN interrupt settings with CAN_EnableIt(), CAN_DisableIt(), + * get interrupt mask by CAN_GetItMask(). + * - Get CAN status with CAN_GetStatus(). + * - Setup CAN baudrate via CAN_CalcBaudrate(). + * - Start several mailbox transmition through CAN_Command(). + * - The following functions setup mailboxes for message transfer: + * - CAN_ConfigureMessageMode() : setup _MMRx. + * - CAN_ConfigureMessageAcceptanceMask() : setup _MARx. + * - CAN_ConfigureMessageID() : setup _MIDx. + * - CAN_SetMessage() : setup _MDLx and _MDHx. + * - CAN_MessageControl() : setup _MCRx. + * - The following get status and data from mailbox: + * - CAN_GetMessage() : + * - CAN_GetMessageStatus() : + */ + +#ifndef _CAN_H_ +#define _CAN_H_ +/**@{*/ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** Number of mailboxes in a CAN controller */ +#define CAN_NUM_MAILBOX 8 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +void CAN_ConfigureMode(Can * pCan,uint32_t dwMr); +void CAN_Enable(Can * pCan,uint8_t bEnDis); +void CAN_EnableLowPower(Can * pCan,uint8_t bEnDis); +void CAN_EnableAutobaud(Can * pCan,uint8_t bEnDis); +void CAN_EnableOverloadFrame(Can * pCan,uint8_t bEnDis); +void CAN_EnableTimeStampEof(Can * pCan,uint8_t bEofSof); +void CAN_EnableTimeTriggerMode(Can * pCan,uint8_t bEnDis); +void CAN_EnableTimerFreeze(Can * pCan,uint8_t bEnDis); +void CAN_DisableRepeat(Can * pCan,uint8_t bDisEn); + +void CAN_EnableIt(Can * pCan,uint32_t dwSources); +void CAN_DisableIt(Can * pCan,uint32_t dwSources); +uint32_t CAN_GetItMask(Can * pCan); +uint32_t CAN_GetStatus(Can * pCan); + +uint8_t CAN_CalcBaudrate(Can * pCan, uint32_t dwBaud, uint32_t dwMck); +void CAN_ConfigureBaudrate(Can * pCan,uint32_t dwBr); +void CAN_SetSamplingMode(Can * pCan,uint8_t bAvg3); + +uint32_t CAN_GetTimer(Can * pCan); +uint32_t CAN_GetTimestamp(Can * pCan); + +uint32_t CAN_GetErrorCount(Can * pCan); +uint32_t CAN_GetRxErrorCount(Can * pCan); +uint32_t CAN_GetTxErrorCount(Can * pCan); + +void CAN_Command(Can * pCan,uint32_t dwRequests); +void CAN_ResetTimer(Can * pCan); +void CAN_Tx(Can * pCan,uint8_t bMb); + +void CAN_Abort(Can * pCan,uint32_t dwAborts); +void CAN_AbortMailbox(Can * pCan,uint8_t bMb); + +void CAN_ConfigureMessageMode(Can * pCan,uint8_t bMb,uint32_t dwMr); +uint32_t CAN_GetMessageMode(Can * pCan,uint8_t bMb); +void CAN_SetTimemark(Can * pCan,uint8_t bMb,uint8_t bTimemarks); +void CAN_SetPriority(Can * pCan,uint8_t bMb,uint8_t bPriority); +void CAN_SetObjectType(Can * pCan,uint8_t bMb,uint8_t bType); + +void CAN_ConfigureMessageAcceptanceMask(Can * pCan,uint8_t bMb,uint32_t dwMAM); +uint32_t CAN_GetMessageAcceptanceMask(Can * pCan,uint8_t bMb); +void CAN_ConfigureIdentifierMask(Can * pCan,uint8_t bMb,uint8_t bIdCfg); +void CAN_SetMIDvAMask(Can * pCan,uint8_t bMb,uint32_t dwIDvA); +void CAN_SetMIDvBMask(Can * pCan,uint8_t bMb,uint32_t dwIDvA); + +void CAN_ConfigureMessageID(Can * pCan,uint8_t bMb,uint32_t dwMID); +uint32_t CAN_GetMessageID(Can * pCan,uint8_t bMb); +void CAN_ConfigureIdVer(Can * pCan,uint8_t bMb,uint8_t bIdVer); +void CAN_SetMIDvA(Can * pCan,uint8_t bMb,uint32_t dwIDvA); +void CAN_SetMIDvB(Can * pCan,uint8_t bMb,uint32_t dwIDvA); + +uint32_t CAN_GetFamilyID(Can * pCan,uint8_t bMb); + +uint32_t CAN_GetMessageStatus(Can * pCan,uint8_t bMb); + +void CAN_SetMessageDataL(Can * pCan,uint8_t bMb,uint32_t dwL); +uint32_t CAN_GetMessageDataL(Can * pCan,uint8_t bMb); +void CAN_SetMessageDataH(Can * pCan,uint8_t bMb,uint32_t dwH); +uint32_t CAN_GetMessageDataH(Can * pCan,uint8_t bMb); +void CAN_SetMessage(Can * pCan,uint8_t bMb,uint32_t * pDwData); +void CAN_GetMessage(Can * pCan,uint8_t bMb,uint32_t * pDwData); +void CAN_SetMessageData64(Can * pCan,uint8_t bMb,uint64_t u64); +uint64_t CAN_GetMessageData64(Can * pCan,uint8_t bMb); + +void CAN_MessageControl(Can * pCan,uint8_t bMb,uint32_t dwCtrl); +void CAN_MessageRemote(Can * pCan,uint8_t bMb); +void CAN_MessageAbort(Can * pCan,uint8_t bMb); +void CAN_MessageTx(Can * pCan,uint8_t bMb,uint8_t bLen); +void CAN_MessageRx(Can * pCan,uint8_t bMb); + +/**@}*/ +#endif /* #ifndef _CAN_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_adc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_adc.h new file mode 100644 index 000000000..b3dc55751 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_adc.h @@ -0,0 +1,489 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_ADC_COMPONENT_ +#define _SAMA5_ADC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ +/* ============================================================================= */ +/** \addtogroup SAMA5_ADC Analog-to-digital Converter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Adc hardware registers */ +typedef struct { + WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */ + RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */ + WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + RoReg Reserved1[1]; + RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + RoReg Reserved2[2]; + RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + RoReg ADC_CDR[12]; /**< \brief (Adc Offset: 0x50) Channel Data Register */ + RoReg Reserved3[5]; + RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + RoReg Reserved4[6]; + RwReg ADC_TSMR; /**< \brief (Adc Offset: 0xB0) Touchscreen Mode Register */ + RoReg ADC_XPOSR; /**< \brief (Adc Offset: 0xB4) Touchscreen X Position Register */ + RoReg ADC_YPOSR; /**< \brief (Adc Offset: 0xB8) Touchscreen Y Position Register */ + RoReg ADC_PRESSR; /**< \brief (Adc Offset: 0xBC) Touchscreen Pressure Register */ + RwReg ADC_TRGR; /**< \brief (Adc Offset: 0xC0) Trigger Register */ + RoReg Reserved5[8]; + RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ +#define ADC_CR_TSCALIB (0x1u << 2) /**< \brief (ADC_CR) Touchscreen Calibration */ +#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGSEL_Pos 1 +#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) ADTRG */ +#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA0 */ +#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA1 */ +#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA2 */ +#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM event line 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM_even line 1 */ +#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */ +#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */ +#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ +#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */ +#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */ +#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */ +#define ADC_MR_PRESCAL_Pos 8 +#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) +#define ADC_MR_STARTUP_Pos 16 +#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */ +#define ADC_MR_SETTLING_Pos 20 +#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */ +#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */ +#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */ +#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */ +#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */ +#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */ +#define ADC_MR_TRACKTIM_Pos 24 +#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) +#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */ +#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */ +#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. */ +/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */ +#define ADC_SEQR1_USCH1_Pos 0 +#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */ +#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) +#define ADC_SEQR1_USCH2_Pos 4 +#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */ +#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) +#define ADC_SEQR1_USCH3_Pos 8 +#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */ +#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) +#define ADC_SEQR1_USCH4_Pos 12 +#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */ +#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) +#define ADC_SEQR1_USCH5_Pos 16 +#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */ +#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) +#define ADC_SEQR1_USCH6_Pos 20 +#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */ +#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) +#define ADC_SEQR1_USCH7_Pos 24 +#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */ +#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) +#define ADC_SEQR1_USCH8_Pos 28 +#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */ +#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos))) +/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */ +#define ADC_SEQR2_USCH9_Pos 0 +#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */ +#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos))) +#define ADC_SEQR2_USCH10_Pos 4 +#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */ +#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos))) +#define ADC_SEQR2_USCH11_Pos 8 +#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */ +#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos))) +#define ADC_SEQR2_USCH12_Pos 12 +#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */ +#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos))) +#define ADC_SEQR2_USCH13_Pos 16 +#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */ +#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos))) +#define ADC_SEQR2_USCH14_Pos 20 +#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */ +#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos))) +#define ADC_SEQR2_USCH15_Pos 24 +#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */ +#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos))) +#define ADC_SEQR2_USCH16_Pos 28 +#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */ +#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos))) +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA_Pos 0 +#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB_Pos 12 +#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_XRDY (0x1u << 20) /**< \brief (ADC_IER) Touchscreen Measure XPOS Ready Interrupt Enable */ +#define ADC_IER_YRDY (0x1u << 21) /**< \brief (ADC_IER) Touchscreen Measure YPOS Ready Interrupt Enable */ +#define ADC_IER_PRDY (0x1u << 22) /**< \brief (ADC_IER) Touchscreen Measure Pressure Ready Interrupt Enable */ +#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */ +#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_PEN (0x1u << 29) /**< \brief (ADC_IER) Pen Contact Interrupt Enable */ +#define ADC_IER_NOPEN (0x1u << 30) /**< \brief (ADC_IER) No Pen Contact Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_XRDY (0x1u << 20) /**< \brief (ADC_IDR) Touchscreen Measure XPOS Ready Interrupt Disable */ +#define ADC_IDR_YRDY (0x1u << 21) /**< \brief (ADC_IDR) Touchscreen Measure YPOS Ready Interrupt Disable */ +#define ADC_IDR_PRDY (0x1u << 22) /**< \brief (ADC_IDR) Touchscreen Measure Pressure Ready Interrupt Disable */ +#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */ +#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_PEN (0x1u << 29) /**< \brief (ADC_IDR) Pen Contact Interrupt Disable */ +#define ADC_IDR_NOPEN (0x1u << 30) /**< \brief (ADC_IDR) No Pen Contact Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_XRDY (0x1u << 20) /**< \brief (ADC_IMR) Touchscreen Measure XPOS Ready Interrupt Mask */ +#define ADC_IMR_YRDY (0x1u << 21) /**< \brief (ADC_IMR) Touchscreen Measure YPOS Ready Interrupt Mask */ +#define ADC_IMR_PRDY (0x1u << 22) /**< \brief (ADC_IMR) Touchscreen Measure Pressure Ready Interrupt Mask */ +#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */ +#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_PEN (0x1u << 29) /**< \brief (ADC_IMR) Pen Contact Interrupt Mask */ +#define ADC_IMR_NOPEN (0x1u << 30) /**< \brief (ADC_IMR) No Pen Contact Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_XRDY (0x1u << 20) /**< \brief (ADC_ISR) Touchscreen XPOS Measure Ready */ +#define ADC_ISR_YRDY (0x1u << 21) /**< \brief (ADC_ISR) Touchscreen YPOS Measure Ready */ +#define ADC_ISR_PRDY (0x1u << 22) /**< \brief (ADC_ISR) Touchscreen Pressure Measure Ready */ +#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */ +#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_PEN (0x1u << 29) /**< \brief (ADC_ISR) Pen contact */ +#define ADC_ISR_NOPEN (0x1u << 30) /**< \brief (ADC_ISR) No Pen contact */ +#define ADC_ISR_PENS (0x1u << 31) /**< \brief (ADC_ISR) Pen detect Status */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE_Pos 0 +#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */ +#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define ADC_EMR_CMPSEL_Pos 4 +#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) +#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_CMPFILTER_Pos 12 +#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */ +#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos))) +#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of the ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES_Pos 0 +#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) +#define ADC_CWR_HIGHTHRES_Pos 16 +#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */ +#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0_Pos 0 +#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */ +#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos))) +#define ADC_CGR_GAIN1_Pos 2 +#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */ +#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos))) +#define ADC_CGR_GAIN2_Pos 4 +#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */ +#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos))) +#define ADC_CGR_GAIN3_Pos 6 +#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */ +#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos))) +#define ADC_CGR_GAIN4_Pos 8 +#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */ +#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos))) +#define ADC_CGR_GAIN5_Pos 10 +#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */ +#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos))) +#define ADC_CGR_GAIN6_Pos 12 +#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */ +#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos))) +#define ADC_CGR_GAIN7_Pos 14 +#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */ +#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos))) +#define ADC_CGR_GAIN8_Pos 16 +#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */ +#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos))) +#define ADC_CGR_GAIN9_Pos 18 +#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */ +#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos))) +#define ADC_CGR_GAIN10_Pos 20 +#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */ +#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos))) +#define ADC_CGR_GAIN11_Pos 22 +#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */ +#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos))) +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +/* -------- ADC_CDR[12] : (ADC Offset: 0x50) Channel Data Register -------- */ +#define ADC_CDR_DATA_Pos 0 +#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[12]) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_PENDETSENS_Pos 0 +#define ADC_ACR_PENDETSENS_Msk (0x3u << ADC_ACR_PENDETSENS_Pos) /**< \brief (ADC_ACR) Pen Detection Sensitivity */ +#define ADC_ACR_PENDETSENS(value) ((ADC_ACR_PENDETSENS_Msk & ((value) << ADC_ACR_PENDETSENS_Pos))) +#define ADC_ACR_IBCTL_Pos 8 +#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */ +#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) +/* -------- ADC_TSMR : (ADC Offset: 0xB0) Touchscreen Mode Register -------- */ +#define ADC_TSMR_TSMODE_Pos 0 +#define ADC_TSMR_TSMODE_Msk (0x3u << ADC_TSMR_TSMODE_Pos) /**< \brief (ADC_TSMR) Touchscreen Mode */ +#define ADC_TSMR_TSMODE_NONE (0x0u << 0) /**< \brief (ADC_TSMR) No Touchscreen */ +#define ADC_TSMR_TSMODE_4_WIRE_NO_PM (0x1u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen without pressure measurement */ +#define ADC_TSMR_TSMODE_4_WIRE (0x2u << 0) /**< \brief (ADC_TSMR) 4-wire Touchscreen with pressure measurement */ +#define ADC_TSMR_TSMODE_5_WIRE (0x3u << 0) /**< \brief (ADC_TSMR) 5-wire Touchscreen */ +#define ADC_TSMR_TSAV_Pos 4 +#define ADC_TSMR_TSAV_Msk (0x3u << ADC_TSMR_TSAV_Pos) /**< \brief (ADC_TSMR) Touchscreen Average */ +#define ADC_TSMR_TSAV_NO_FILTER (0x0u << 4) /**< \brief (ADC_TSMR) No Filtering. Only one ADC conversion per measure */ +#define ADC_TSMR_TSAV_AVG2CONV (0x1u << 4) /**< \brief (ADC_TSMR) Averages 2 ADC conversions */ +#define ADC_TSMR_TSAV_AVG4CONV (0x2u << 4) /**< \brief (ADC_TSMR) Averages 4 ADC conversions */ +#define ADC_TSMR_TSAV_AVG8CONV (0x3u << 4) /**< \brief (ADC_TSMR) Averages 8 ADC conversions */ +#define ADC_TSMR_TSFREQ_Pos 8 +#define ADC_TSMR_TSFREQ_Msk (0xfu << ADC_TSMR_TSFREQ_Pos) /**< \brief (ADC_TSMR) Touchscreen Frequency */ +#define ADC_TSMR_TSFREQ(value) ((ADC_TSMR_TSFREQ_Msk & ((value) << ADC_TSMR_TSFREQ_Pos))) +#define ADC_TSMR_TSSCTIM_Pos 16 +#define ADC_TSMR_TSSCTIM_Msk (0xfu << ADC_TSMR_TSSCTIM_Pos) /**< \brief (ADC_TSMR) Touchscreen Switches Closure Time */ +#define ADC_TSMR_TSSCTIM(value) ((ADC_TSMR_TSSCTIM_Msk & ((value) << ADC_TSMR_TSSCTIM_Pos))) +#define ADC_TSMR_NOTSDMA (0x1u << 22) /**< \brief (ADC_TSMR) No TouchScreen DMA */ +#define ADC_TSMR_PENDET (0x1u << 24) /**< \brief (ADC_TSMR) Pen Contact Detection Enable */ +#define ADC_TSMR_PENDBC_Pos 28 +#define ADC_TSMR_PENDBC_Msk (0xfu << ADC_TSMR_PENDBC_Pos) /**< \brief (ADC_TSMR) Pen Detect Debouncing Period */ +#define ADC_TSMR_PENDBC(value) ((ADC_TSMR_PENDBC_Msk & ((value) << ADC_TSMR_PENDBC_Pos))) +/* -------- ADC_XPOSR : (ADC Offset: 0xB4) Touchscreen X Position Register -------- */ +#define ADC_XPOSR_XPOS_Pos 0 +#define ADC_XPOSR_XPOS_Msk (0xfffu << ADC_XPOSR_XPOS_Pos) /**< \brief (ADC_XPOSR) X Position */ +#define ADC_XPOSR_XSCALE_Pos 16 +#define ADC_XPOSR_XSCALE_Msk (0xfffu << ADC_XPOSR_XSCALE_Pos) /**< \brief (ADC_XPOSR) Scale of XPOS */ +/* -------- ADC_YPOSR : (ADC Offset: 0xB8) Touchscreen Y Position Register -------- */ +#define ADC_YPOSR_YPOS_Pos 0 +#define ADC_YPOSR_YPOS_Msk (0xfffu << ADC_YPOSR_YPOS_Pos) /**< \brief (ADC_YPOSR) Y Position */ +#define ADC_YPOSR_YSCALE_Pos 16 +#define ADC_YPOSR_YSCALE_Msk (0xfffu << ADC_YPOSR_YSCALE_Pos) /**< \brief (ADC_YPOSR) Scale of YPOS */ +/* -------- ADC_PRESSR : (ADC Offset: 0xBC) Touchscreen Pressure Register -------- */ +#define ADC_PRESSR_Z1_Pos 0 +#define ADC_PRESSR_Z1_Msk (0xfffu << ADC_PRESSR_Z1_Pos) /**< \brief (ADC_PRESSR) Data of Z1 Measurement */ +#define ADC_PRESSR_Z2_Pos 16 +#define ADC_PRESSR_Z2_Msk (0xfffu << ADC_PRESSR_Z2_Pos) /**< \brief (ADC_PRESSR) Data of Z2 Measurement */ +/* -------- ADC_TRGR : (ADC Offset: 0xC0) Trigger Register -------- */ +#define ADC_TRGR_TRGMOD_Pos 0 +#define ADC_TRGR_TRGMOD_Msk (0x7u << ADC_TRGR_TRGMOD_Pos) /**< \brief (ADC_TRGR) Trigger Mode */ +#define ADC_TRGR_TRGMOD_NO_TRIGGER (0x0u << 0) /**< \brief (ADC_TRGR) No trigger, only software trigger can start conversions */ +#define ADC_TRGR_TRGMOD_EXT_TRIG_RISE (0x1u << 0) /**< \brief (ADC_TRGR) External Trigger Rising Edge */ +#define ADC_TRGR_TRGMOD_EXT_TRIG_FALL (0x2u << 0) /**< \brief (ADC_TRGR) External Trigger Falling Edge */ +#define ADC_TRGR_TRGMOD_EXT_TRIG_ANY (0x3u << 0) /**< \brief (ADC_TRGR) External Trigger Any Edge */ +#define ADC_TRGR_TRGMOD_PEN_TRIG (0x4u << 0) /**< \brief (ADC_TRGR) Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) */ +#define ADC_TRGR_TRGMOD_PERIOD_TRIG (0x5u << 0) /**< \brief (ADC_TRGR) Periodic Trigger (TRGPER shall be initiated appropriately) */ +#define ADC_TRGR_TRGMOD_CONTINUOUS (0x6u << 0) /**< \brief (ADC_TRGR) Continuous Mode */ +#define ADC_TRGR_TRGPER_Pos 16 +#define ADC_TRGR_TRGPER_Msk (0xffffu << ADC_TRGR_TRGPER_Pos) /**< \brief (ADC_TRGR) Trigger Period */ +#define ADC_TRGR_TRGPER(value) ((ADC_TRGR_TRGPER_Msk & ((value) << ADC_TRGR_TRGPER_Pos))) +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY_Pos 8 +#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */ +#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC_Pos 8 +#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_ADC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aes.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aes.h new file mode 100644 index 000000000..60e5c3632 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aes.h @@ -0,0 +1,183 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AES_COMPONENT_ +#define _SAMA5_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMA5_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + WoReg AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + RwReg AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + RoReg Reserved1[2]; + WoReg AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + WoReg AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + RoReg AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + RoReg AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + WoReg AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + WoReg AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + RoReg AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + WoReg AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + WoReg AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + WoReg AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + WoReg AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + WoReg AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + WoReg AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + WoReg AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H World Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +#define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input BUFFer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */ +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx fields change. Any other values will abort the write operation in CMTYPx fields.Always reads as 0. */ +#define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */ +#define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled */ +#define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled */ +#define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */ +#define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled */ +#define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled */ +#define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */ +#define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled */ +#define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled */ +#define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */ +#define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled */ +#define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled */ +#define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */ +#define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled */ +#define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled */ +#define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) CounterMeasure Type 6 */ +#define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled */ +#define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access: */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD=0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) AAD Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H World Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_AES_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aic.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aic.h new file mode 100644 index 000000000..76322f808 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aic.h @@ -0,0 +1,270 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AIC_COMPONENT_ +#define _SAMA5_AIC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_AIC Advanced Interrupt Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aic hardware registers */ +typedef struct { + RwReg AIC_SSR; /**< \brief (Aic Offset: 0x00) Source Select Register */ + RwReg AIC_SMR; /**< \brief (Aic Offset: 0x04) Source Mode Register */ + RwReg AIC_SVR; /**< \brief (Aic Offset: 0x08) Source Vector Register */ + RoReg Reserved1[1]; + RoReg AIC_IVR; /**< \brief (Aic Offset: 0x10) Interrupt Vector Register */ + RoReg AIC_FVR; /**< \brief (Aic Offset: 0x14) FIQ Interrupt Vector Register */ + RoReg AIC_ISR; /**< \brief (Aic Offset: 0x18) Interrupt Status Register */ + RoReg Reserved2[1]; + RoReg AIC_IPR0; /**< \brief (Aic Offset: 0x20) Interrupt Pending Register 0 */ + RoReg AIC_IPR1; /**< \brief (Aic Offset: 0x24) Interrupt Pending Register 1 */ + RoReg AIC_IPR2; /**< \brief (Aic Offset: 0x28) Interrupt Pending Register 2 */ + RoReg AIC_IPR3; /**< \brief (Aic Offset: 0x2C) Interrupt Pending Register 3 */ + RoReg AIC_IMR; /**< \brief (Aic Offset: 0x30) Interrupt Mask Register */ + RoReg AIC_CISR; /**< \brief (Aic Offset: 0x34) Core Interrupt Status Register */ + WoReg AIC_EOICR; /**< \brief (Aic Offset: 0x38) End of Interrupt Command Register */ + RwReg AIC_SPU; /**< \brief (Aic Offset: 0x3C) Spurious Interrupt Vector Register */ + WoReg AIC_IECR; /**< \brief (Aic Offset: 0x40) Interrupt Enable Command Register */ + WoReg AIC_IDCR; /**< \brief (Aic Offset: 0x44) Interrupt Disable Command Register */ + WoReg AIC_ICCR; /**< \brief (Aic Offset: 0x48) Interrupt Clear Command Register */ + WoReg AIC_ISCR; /**< \brief (Aic Offset: 0x4C) Interrupt Set Command Register */ + WoReg AIC_FFER; /**< \brief (Aic Offset: 0x50) Fast Forcing Enable Register */ + WoReg AIC_FFDR; /**< \brief (Aic Offset: 0x54) Fast Forcing Disable Register */ + RoReg AIC_FFSR; /**< \brief (Aic Offset: 0x58) Fast Forcing Status Register */ + RoReg Reserved3[4]; + RwReg AIC_DCR; /**< \brief (Aic Offset: 0x6C) Debug Control Register */ + RoReg Reserved4[29]; + RwReg AIC_WPMR; /**< \brief (Aic Offset: 0xE4) Write Protect Mode Register */ + RoReg AIC_WPSR; /**< \brief (Aic Offset: 0xE8) Write Protect Status Register */ +} Aic; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AIC_SSR : (AIC Offset: 0x00) Source Select Register -------- */ +#define AIC_SSR_INTSEL_Pos 0 +#define AIC_SSR_INTSEL_Msk (0x7fu << AIC_SSR_INTSEL_Pos) /**< \brief (AIC_SSR) Interrupt line Selection */ +#define AIC_SSR_INTSEL(value) ((AIC_SSR_INTSEL_Msk & ((value) << AIC_SSR_INTSEL_Pos))) +/* -------- AIC_SMR : (AIC Offset: 0x04) Source Mode Register -------- */ +#define AIC_SMR_PRIOR_Pos 0 +#define AIC_SMR_PRIOR_Msk (0x7u << AIC_SMR_PRIOR_Pos) /**< \brief (AIC_SMR) Priority Level */ +#define AIC_SMR_PRIOR(value) ((AIC_SMR_PRIOR_Msk & ((value) << AIC_SMR_PRIOR_Pos))) +#define AIC_SMR_SRCTYPE_Pos 5 +#define AIC_SMR_SRCTYPE_Msk (0x3u << AIC_SMR_SRCTYPE_Pos) /**< \brief (AIC_SMR) Interrupt Source Type */ +#define AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceLow level Sensitive for external source */ +#define AIC_SMR_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourceNegative edge triggered for external source */ +#define AIC_SMR_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceHigh level Sensitive for external source */ +#define AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourcePositive edge triggered for external source */ +/* -------- AIC_SVR : (AIC Offset: 0x08) Source Vector Register -------- */ +#define AIC_SVR_VECTOR_Pos 0 +#define AIC_SVR_VECTOR_Msk (0xffffffffu << AIC_SVR_VECTOR_Pos) /**< \brief (AIC_SVR) Source Vector */ +#define AIC_SVR_VECTOR(value) ((AIC_SVR_VECTOR_Msk & ((value) << AIC_SVR_VECTOR_Pos))) +/* -------- AIC_IVR : (AIC Offset: 0x10) Interrupt Vector Register -------- */ +#define AIC_IVR_IRQV_Pos 0 +#define AIC_IVR_IRQV_Msk (0xffffffffu << AIC_IVR_IRQV_Pos) /**< \brief (AIC_IVR) Interrupt Vector Register */ +/* -------- AIC_FVR : (AIC Offset: 0x14) FIQ Interrupt Vector Register -------- */ +#define AIC_FVR_FIQV_Pos 0 +#define AIC_FVR_FIQV_Msk (0xffffffffu << AIC_FVR_FIQV_Pos) /**< \brief (AIC_FVR) FIQ Vector Register */ +/* -------- AIC_ISR : (AIC Offset: 0x18) Interrupt Status Register -------- */ +#define AIC_ISR_IRQID_Pos 0 +#define AIC_ISR_IRQID_Msk (0x7fu << AIC_ISR_IRQID_Pos) /**< \brief (AIC_ISR) Current Interrupt Identifier */ +/* -------- AIC_IPR0 : (AIC Offset: 0x20) Interrupt Pending Register 0 -------- */ +#define AIC_IPR0_FIQ (0x1u << 0) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_SYS (0x1u << 1) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID2 (0x1u << 2) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID3 (0x1u << 3) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID4 (0x1u << 4) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID5 (0x1u << 5) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID6 (0x1u << 6) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID7 (0x1u << 7) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID8 (0x1u << 8) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID9 (0x1u << 9) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID10 (0x1u << 10) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID11 (0x1u << 11) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID12 (0x1u << 12) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID13 (0x1u << 13) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID14 (0x1u << 14) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID15 (0x1u << 15) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID16 (0x1u << 16) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID17 (0x1u << 17) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID18 (0x1u << 18) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID19 (0x1u << 19) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID20 (0x1u << 20) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID21 (0x1u << 21) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID22 (0x1u << 22) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID23 (0x1u << 23) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID24 (0x1u << 24) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID25 (0x1u << 25) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID26 (0x1u << 26) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID27 (0x1u << 27) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID28 (0x1u << 28) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID29 (0x1u << 29) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID30 (0x1u << 30) /**< \brief (AIC_IPR0) Interrupt Pending */ +#define AIC_IPR0_PID31 (0x1u << 31) /**< \brief (AIC_IPR0) Interrupt Pending */ +/* -------- AIC_IPR1 : (AIC Offset: 0x24) Interrupt Pending Register 1 -------- */ +#define AIC_IPR1_PID32 (0x1u << 0) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID33 (0x1u << 1) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID34 (0x1u << 2) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID35 (0x1u << 3) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID36 (0x1u << 4) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID37 (0x1u << 5) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID38 (0x1u << 6) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID39 (0x1u << 7) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID40 (0x1u << 8) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID41 (0x1u << 9) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID42 (0x1u << 10) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID43 (0x1u << 11) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID44 (0x1u << 12) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID45 (0x1u << 13) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID46 (0x1u << 14) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID47 (0x1u << 15) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID48 (0x1u << 16) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID49 (0x1u << 17) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID50 (0x1u << 18) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID51 (0x1u << 19) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID52 (0x1u << 20) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID53 (0x1u << 21) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID54 (0x1u << 22) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID55 (0x1u << 23) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID56 (0x1u << 24) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID57 (0x1u << 25) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID58 (0x1u << 26) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID59 (0x1u << 27) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID60 (0x1u << 28) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID61 (0x1u << 29) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID62 (0x1u << 30) /**< \brief (AIC_IPR1) Interrupt Pending */ +#define AIC_IPR1_PID63 (0x1u << 31) /**< \brief (AIC_IPR1) Interrupt Pending */ +/* -------- AIC_IPR2 : (AIC Offset: 0x28) Interrupt Pending Register 2 -------- */ +#define AIC_IPR2_PID64 (0x1u << 0) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID65 (0x1u << 1) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID66 (0x1u << 2) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID67 (0x1u << 3) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID68 (0x1u << 4) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID69 (0x1u << 5) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID70 (0x1u << 6) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID71 (0x1u << 7) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID72 (0x1u << 8) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID73 (0x1u << 9) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID74 (0x1u << 10) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID75 (0x1u << 11) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID76 (0x1u << 12) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID77 (0x1u << 13) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID78 (0x1u << 14) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID79 (0x1u << 15) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID80 (0x1u << 16) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID81 (0x1u << 17) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID82 (0x1u << 18) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID83 (0x1u << 19) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID84 (0x1u << 20) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID85 (0x1u << 21) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID86 (0x1u << 22) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID87 (0x1u << 23) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID88 (0x1u << 24) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID89 (0x1u << 25) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID90 (0x1u << 26) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID91 (0x1u << 27) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID92 (0x1u << 28) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID93 (0x1u << 29) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID94 (0x1u << 30) /**< \brief (AIC_IPR2) Interrupt Pending */ +#define AIC_IPR2_PID95 (0x1u << 31) /**< \brief (AIC_IPR2) Interrupt Pending */ +/* -------- AIC_IPR3 : (AIC Offset: 0x2C) Interrupt Pending Register 3 -------- */ +#define AIC_IPR3_PID96 (0x1u << 0) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID97 (0x1u << 1) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID98 (0x1u << 2) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID99 (0x1u << 3) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID100 (0x1u << 4) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID101 (0x1u << 5) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID102 (0x1u << 6) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID103 (0x1u << 7) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID104 (0x1u << 8) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID105 (0x1u << 9) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID106 (0x1u << 10) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID107 (0x1u << 11) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID108 (0x1u << 12) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID109 (0x1u << 13) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID110 (0x1u << 14) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID111 (0x1u << 15) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID112 (0x1u << 16) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID113 (0x1u << 17) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID114 (0x1u << 18) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID115 (0x1u << 19) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID116 (0x1u << 20) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID117 (0x1u << 21) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID118 (0x1u << 22) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID119 (0x1u << 23) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID120 (0x1u << 24) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID121 (0x1u << 25) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID122 (0x1u << 26) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID123 (0x1u << 27) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID124 (0x1u << 28) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID125 (0x1u << 29) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID126 (0x1u << 30) /**< \brief (AIC_IPR3) Interrupt Pending */ +#define AIC_IPR3_PID127 (0x1u << 31) /**< \brief (AIC_IPR3) Interrupt Pending */ +/* -------- AIC_IMR : (AIC Offset: 0x30) Interrupt Mask Register -------- */ +#define AIC_IMR_INTM (0x1u << 0) /**< \brief (AIC_IMR) Interrupt Mask */ +/* -------- AIC_CISR : (AIC Offset: 0x34) Core Interrupt Status Register -------- */ +#define AIC_CISR_NFIQ (0x1u << 0) /**< \brief (AIC_CISR) NFIQ Status */ +#define AIC_CISR_NIRQ (0x1u << 1) /**< \brief (AIC_CISR) NIRQ Status */ +/* -------- AIC_SPU : (AIC Offset: 0x3C) Spurious Interrupt Vector Register -------- */ +#define AIC_SPU_SIVR_Pos 0 +#define AIC_SPU_SIVR_Msk (0xffffffffu << AIC_SPU_SIVR_Pos) /**< \brief (AIC_SPU) Spurious Interrupt Vector Register */ +#define AIC_SPU_SIVR(value) ((AIC_SPU_SIVR_Msk & ((value) << AIC_SPU_SIVR_Pos))) +/* -------- AIC_IECR : (AIC Offset: 0x40) Interrupt Enable Command Register -------- */ +#define AIC_IECR_INTEN (0x1u << 0) /**< \brief (AIC_IECR) Interrupt Enable */ +/* -------- AIC_IDCR : (AIC Offset: 0x44) Interrupt Disable Command Register -------- */ +#define AIC_IDCR_INTD (0x1u << 0) /**< \brief (AIC_IDCR) Interrupt Disable */ +/* -------- AIC_ICCR : (AIC Offset: 0x48) Interrupt Clear Command Register -------- */ +#define AIC_ICCR_INTCLR (0x1u << 0) /**< \brief (AIC_ICCR) Interrupt Clear */ +/* -------- AIC_ISCR : (AIC Offset: 0x4C) Interrupt Set Command Register -------- */ +#define AIC_ISCR_INTSET (0x1u << 0) /**< \brief (AIC_ISCR) Interrupt Set */ +/* -------- AIC_FFER : (AIC Offset: 0x50) Fast Forcing Enable Register -------- */ +#define AIC_FFER_FFEN (0x1u << 0) /**< \brief (AIC_FFER) Fast Forcing Enable */ +/* -------- AIC_FFDR : (AIC Offset: 0x54) Fast Forcing Disable Register -------- */ +#define AIC_FFDR_FFDIS (0x1u << 0) /**< \brief (AIC_FFDR) Fast Forcing Disable */ +/* -------- AIC_FFSR : (AIC Offset: 0x58) Fast Forcing Status Register -------- */ +#define AIC_FFSR_FFS (0x1u << 0) /**< \brief (AIC_FFSR) Fast Forcing Status */ +/* -------- AIC_DCR : (AIC Offset: 0x6C) Debug Control Register -------- */ +#define AIC_DCR_PROT (0x1u << 0) /**< \brief (AIC_DCR) Protection Mode */ +#define AIC_DCR_GMSK (0x1u << 1) /**< \brief (AIC_DCR) General Mask */ +/* -------- AIC_WPMR : (AIC Offset: 0xE4) Write Protect Mode Register -------- */ +#define AIC_WPMR_WPEN (0x1u << 0) /**< \brief (AIC_WPMR) Write Protect Enable */ +#define AIC_WPMR_WPKEY_Pos 8 +#define AIC_WPMR_WPKEY_Msk (0xffffffu << AIC_WPMR_WPKEY_Pos) /**< \brief (AIC_WPMR) Write Protect KEY */ +#define AIC_WPMR_WPKEY(value) ((AIC_WPMR_WPKEY_Msk & ((value) << AIC_WPMR_WPKEY_Pos))) +/* -------- AIC_WPSR : (AIC Offset: 0xE8) Write Protect Status Register -------- */ +#define AIC_WPSR_WPVS (0x1u << 0) /**< \brief (AIC_WPSR) Write Protect Violation Status */ +#define AIC_WPSR_WPVSRC_Pos 8 +#define AIC_WPSR_WPVSRC_Msk (0xffffu << AIC_WPSR_WPVSRC_Pos) /**< \brief (AIC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_AIC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aximx.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aximx.h new file mode 100644 index 000000000..c264368a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_aximx.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AXIMX_COMPONENT_ +#define _SAMA5_AXIMX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AXI MATRIX */ +/* ============================================================================= */ +/** \addtogroup SAMA5_AXIMX AXI MATRIX */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aximx hardware registers */ +typedef struct { + WoReg AXIMX_REMAP; /**< \brief (Aximx Offset: 0x00) Remap Register */ + RoReg Reserved1[2035]; + RoReg AXIMX_PERIPH_ID4; /**< \brief (Aximx Offset: 0x1FD0) Peripheral ID Register 4 */ + RoReg AXIMX_PERIPH_ID5; /**< \brief (Aximx Offset: 0x1FD4) Peripheral ID Register 5 */ + RoReg AXIMX_PERIPH_ID6; /**< \brief (Aximx Offset: 0x1FD8) Peripheral ID Register 6 */ + RoReg AXIMX_PERIPH_ID7; /**< \brief (Aximx Offset: 0x1FDC) Peripheral ID Register 7 */ + RoReg AXIMX_PERIPH_ID0; /**< \brief (Aximx Offset: 0x1FE0) Peripheral ID Register 0 */ + RoReg AXIMX_PERIPH_ID1; /**< \brief (Aximx Offset: 0x1FE4) Peripheral ID Register 1 */ + RoReg AXIMX_PERIPH_ID2; /**< \brief (Aximx Offset: 0x1FE8) Peripheral ID Register 2 */ + RoReg AXIMX_PERIPH_ID3; /**< \brief (Aximx Offset: 0x1FEC) Peripheral ID Register 3 */ + RoReg AXIMX_COMP_ID[4]; /**< \brief (Aximx Offset: 0x1FF0) Component ID Register */ + RoReg Reserved2[3074]; + RwReg AXIMX_AMIB3_FN_MOD_BM_ISS; /**< \brief (Aximx Offset: 0x5008) AMIB3 Bus Matrix Functionality Modification Register */ + RoReg Reserved3[6]; + RwReg AXIMX_AMIB3_FN_MOD2; /**< \brief (Aximx Offset: 0x5024) AMIB3 Bypass Merge */ + RoReg Reserved4[62518]; + RwReg AXIMX_ASIB0_READ_QOS; /**< \brief (Aximx Offset: 0x42100) ASIB0 Read Channel QoS Register */ + RwReg AXIMX_ASIB0_WRITE_QOS; /**< \brief (Aximx Offset: 0x42104) ASIB0 Write Channel QoS Register */ + RoReg Reserved5[968]; + RwReg AXIMX_ASIB1_FN_MOD_AHB; /**< \brief (Aximx Offset: 0x43028) ASIB1 AHB Functionality Modification Register */ + RoReg Reserved6[53]; + RwReg AXIMX_ASIB1_READ_QOS; /**< \brief (Aximx Offset: 0x43100) ASIB1 Read Channel QoS Register */ + RwReg AXIMX_ASIB1_WRITE_QOS; /**< \brief (Aximx Offset: 0x43104) ASIB1 Write Channel QoS Register */ + RwReg AXIMX_ASIB1_FN_MOD; /**< \brief (Aximx Offset: 0x43108) ASIB1 Issuing Functionality Modification Register */ +} Aximx; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AXIMX_REMAP : (AXIMX Offset: 0x00) Remap Register -------- */ +#define AXIMX_REMAP_REMAP0 (0x1u << 0) /**< \brief (AXIMX_REMAP) Remap State 0 */ +#define AXIMX_REMAP_REMAP1 (0x1u << 1) /**< \brief (AXIMX_REMAP) Remap State 1 */ +/* -------- AXIMX_PERIPH_ID4 : (AXIMX Offset: 0x1FD0) Peripheral ID Register 4 -------- */ +#define AXIMX_PERIPH_ID4_ID_Pos 0 +#define AXIMX_PERIPH_ID4_ID_Msk (0xffu << AXIMX_PERIPH_ID4_ID_Pos) /**< \brief (AXIMX_PERIPH_ID4) Peripheral ID */ +#define AXIMX_PERIPH_ID4_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID4) Part Number */ +#define AXIMX_PERIPH_ID4_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID4) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID4_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID4) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID4_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID4) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID5 : (AXIMX Offset: 0x1FD4) Peripheral ID Register 5 -------- */ +#define AXIMX_PERIPH_ID5_ID_Pos 0 +#define AXIMX_PERIPH_ID5_ID_Msk (0xffu << AXIMX_PERIPH_ID5_ID_Pos) /**< \brief (AXIMX_PERIPH_ID5) Peripheral ID */ +#define AXIMX_PERIPH_ID5_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID5) Part Number */ +#define AXIMX_PERIPH_ID5_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID5) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID5_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID5) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID5_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID5) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID6 : (AXIMX Offset: 0x1FD8) Peripheral ID Register 6 -------- */ +#define AXIMX_PERIPH_ID6_ID_Pos 0 +#define AXIMX_PERIPH_ID6_ID_Msk (0xffu << AXIMX_PERIPH_ID6_ID_Pos) /**< \brief (AXIMX_PERIPH_ID6) Peripheral ID */ +#define AXIMX_PERIPH_ID6_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID6) Part Number */ +#define AXIMX_PERIPH_ID6_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID6) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID6_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID6) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID6_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID6) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID7 : (AXIMX Offset: 0x1FDC) Peripheral ID Register 7 -------- */ +#define AXIMX_PERIPH_ID7_ID_Pos 0 +#define AXIMX_PERIPH_ID7_ID_Msk (0xffu << AXIMX_PERIPH_ID7_ID_Pos) /**< \brief (AXIMX_PERIPH_ID7) Peripheral ID */ +#define AXIMX_PERIPH_ID7_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID7) Part Number */ +#define AXIMX_PERIPH_ID7_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID7) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID7_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID7) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID7_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID7) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID0 : (AXIMX Offset: 0x1FE0) Peripheral ID Register 0 -------- */ +#define AXIMX_PERIPH_ID0_ID_Pos 0 +#define AXIMX_PERIPH_ID0_ID_Msk (0xffu << AXIMX_PERIPH_ID0_ID_Pos) /**< \brief (AXIMX_PERIPH_ID0) Peripheral ID */ +#define AXIMX_PERIPH_ID0_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID0) Part Number */ +#define AXIMX_PERIPH_ID0_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID0) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID0_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID0) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID0_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID0) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID1 : (AXIMX Offset: 0x1FE4) Peripheral ID Register 1 -------- */ +#define AXIMX_PERIPH_ID1_ID_Pos 0 +#define AXIMX_PERIPH_ID1_ID_Msk (0xffu << AXIMX_PERIPH_ID1_ID_Pos) /**< \brief (AXIMX_PERIPH_ID1) Peripheral ID */ +#define AXIMX_PERIPH_ID1_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID1) Part Number */ +#define AXIMX_PERIPH_ID1_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID1) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID1_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID1) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID1_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID1) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID2 : (AXIMX Offset: 0x1FE8) Peripheral ID Register 2 -------- */ +#define AXIMX_PERIPH_ID2_ID_Pos 0 +#define AXIMX_PERIPH_ID2_ID_Msk (0xffu << AXIMX_PERIPH_ID2_ID_Pos) /**< \brief (AXIMX_PERIPH_ID2) Peripheral ID */ +#define AXIMX_PERIPH_ID2_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID2) Part Number */ +#define AXIMX_PERIPH_ID2_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID2) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID2_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID2) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID2_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID2) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_PERIPH_ID3 : (AXIMX Offset: 0x1FEC) Peripheral ID Register 3 -------- */ +#define AXIMX_PERIPH_ID3_ID_Pos 0 +#define AXIMX_PERIPH_ID3_ID_Msk (0xffu << AXIMX_PERIPH_ID3_ID_Pos) /**< \brief (AXIMX_PERIPH_ID3) Peripheral ID */ +#define AXIMX_PERIPH_ID3_ID_ID0 (0x1u << 0) /**< \brief (AXIMX_PERIPH_ID3) Part Number */ +#define AXIMX_PERIPH_ID3_ID_ID4 (0x4u << 0) /**< \brief (AXIMX_PERIPH_ID3) 4KB count, JEP106 continuation code */ +#define AXIMX_PERIPH_ID3_ID_ID1 (0xB3u << 0) /**< \brief (AXIMX_PERIPH_ID3) JEP106[3:0, part number[11:8] */ +#define AXIMX_PERIPH_ID3_ID_ID2 (0xB6u << 0) /**< \brief (AXIMX_PERIPH_ID3) Revision, JEP106 code flag, JEP106[6:4] */ +/* -------- AXIMX_COMP_ID[4] : (AXIMX Offset: 0x1FF0) Component ID Register -------- */ +#define AXIMX_COMP_ID_ID_Pos 0 +#define AXIMX_COMP_ID_ID_Msk (0xffu << AXIMX_COMP_ID_ID_Pos) /**< \brief (AXIMX_COMP_ID[4]) Component ID */ +/* -------- AXIMX_AMIB3_FN_MOD_BM_ISS : (AXIMX Offset: 0x5008) AMIB3 Bus Matrix Functionality Modification Register -------- */ +#define AXIMX_AMIB3_FN_MOD_BM_ISS_RD_ISS (0x1u << 0) /**< \brief (AXIMX_AMIB3_FN_MOD_BM_ISS) Read Issuing */ +#define AXIMX_AMIB3_FN_MOD_BM_ISS_WR_ISS (0x1u << 1) /**< \brief (AXIMX_AMIB3_FN_MOD_BM_ISS) Write Issuing */ +/* -------- AXIMX_AMIB3_FN_MOD2 : (AXIMX Offset: 0x5024) AMIB3 Bypass Merge -------- */ +#define AXIMX_AMIB3_FN_MOD2_BP_MRG (0x1u << 0) /**< \brief (AXIMX_AMIB3_FN_MOD2) Bypass Merge */ +/* -------- AXIMX_ASIB0_READ_QOS : (AXIMX Offset: 0x42100) ASIB0 Read Channel QoS Register -------- */ +#define AXIMX_ASIB0_READ_QOS_RD_QOS_Pos 0 +#define AXIMX_ASIB0_READ_QOS_RD_QOS_Msk (0xfu << AXIMX_ASIB0_READ_QOS_RD_QOS_Pos) /**< \brief (AXIMX_ASIB0_READ_QOS) Read QoS */ +#define AXIMX_ASIB0_READ_QOS_RD_QOS(value) ((AXIMX_ASIB0_READ_QOS_RD_QOS_Msk & ((value) << AXIMX_ASIB0_READ_QOS_RD_QOS_Pos))) +/* -------- AXIMX_ASIB0_WRITE_QOS : (AXIMX Offset: 0x42104) ASIB0 Write Channel QoS Register -------- */ +#define AXIMX_ASIB0_WRITE_QOS_WR_QOS_Pos 0 +#define AXIMX_ASIB0_WRITE_QOS_WR_QOS_Msk (0xfu << AXIMX_ASIB0_WRITE_QOS_WR_QOS_Pos) /**< \brief (AXIMX_ASIB0_WRITE_QOS) Write QoS */ +#define AXIMX_ASIB0_WRITE_QOS_WR_QOS(value) ((AXIMX_ASIB0_WRITE_QOS_WR_QOS_Msk & ((value) << AXIMX_ASIB0_WRITE_QOS_WR_QOS_Pos))) +/* -------- AXIMX_ASIB1_FN_MOD_AHB : (AXIMX Offset: 0x43028) ASIB1 AHB Functionality Modification Register -------- */ +#define AXIMX_ASIB1_FN_MOD_AHB_RD_INCR_OVR (0x1u << 0) /**< \brief (AXIMX_ASIB1_FN_MOD_AHB) Read INCR Override */ +#define AXIMX_ASIB1_FN_MOD_AHB_WR_INCR_OVR (0x1u << 1) /**< \brief (AXIMX_ASIB1_FN_MOD_AHB) Write INCR override */ +#define AXIMX_ASIB1_FN_MOD_AHB_LOCK_OVR (0x1u << 2) /**< \brief (AXIMX_ASIB1_FN_MOD_AHB) Lock Override */ +/* -------- AXIMX_ASIB1_READ_QOS : (AXIMX Offset: 0x43100) ASIB1 Read Channel QoS Register -------- */ +#define AXIMX_ASIB1_READ_QOS_RD_QOS_Pos 0 +#define AXIMX_ASIB1_READ_QOS_RD_QOS_Msk (0xfu << AXIMX_ASIB1_READ_QOS_RD_QOS_Pos) /**< \brief (AXIMX_ASIB1_READ_QOS) Read QoS */ +#define AXIMX_ASIB1_READ_QOS_RD_QOS(value) ((AXIMX_ASIB1_READ_QOS_RD_QOS_Msk & ((value) << AXIMX_ASIB1_READ_QOS_RD_QOS_Pos))) +/* -------- AXIMX_ASIB1_WRITE_QOS : (AXIMX Offset: 0x43104) ASIB1 Write Channel QoS Register -------- */ +#define AXIMX_ASIB1_WRITE_QOS_WR_QOS_Pos 0 +#define AXIMX_ASIB1_WRITE_QOS_WR_QOS_Msk (0xfu << AXIMX_ASIB1_WRITE_QOS_WR_QOS_Pos) /**< \brief (AXIMX_ASIB1_WRITE_QOS) Write QoS */ +#define AXIMX_ASIB1_WRITE_QOS_WR_QOS(value) ((AXIMX_ASIB1_WRITE_QOS_WR_QOS_Msk & ((value) << AXIMX_ASIB1_WRITE_QOS_WR_QOS_Pos))) +/* -------- AXIMX_ASIB1_FN_MOD : (AXIMX Offset: 0x43108) ASIB1 Issuing Functionality Modification Register -------- */ +#define AXIMX_ASIB1_FN_MOD_RD_ISS (0x1u << 0) /**< \brief (AXIMX_ASIB1_FN_MOD) Read Issuing */ +#define AXIMX_ASIB1_FN_MOD_WR_ISS (0x1u << 1) /**< \brief (AXIMX_ASIB1_FN_MOD) Write Issuing */ + +/*@}*/ + + +#endif /* _SAMA5_AXIMX_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_bsc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_bsc.h new file mode 100644 index 000000000..817e017a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_bsc.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_BSC_COMPONENT_ +#define _SAMA5_BSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Boot Sequence Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_BSC Boot Sequence Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Bsc hardware registers */ +typedef struct { + RwReg BSC_CR; /**< \brief (Bsc Offset: 0x0) Boot Sequence Configuration Register */ +} Bsc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- BSC_CR : (BSC Offset: 0x0) Boot Sequence Configuration Register -------- */ +#define BSC_CR_BOOT_Pos 0 +#define BSC_CR_BOOT_Msk (0xffu << BSC_CR_BOOT_Pos) /**< \brief (BSC_CR) Boot media sequence */ +#define BSC_CR_BOOT(value) ((BSC_CR_BOOT_Msk & ((value) << BSC_CR_BOOT_Pos))) +#define BSC_CR_BOOTKEY_Pos 16 +#define BSC_CR_BOOTKEY_Msk (0xffffu << BSC_CR_BOOTKEY_Pos) /**< \brief (BSC_CR) */ +#define BSC_CR_BOOTKEY_BSC_KEY (0x6683u << 16) /**< \brief (BSC_CR) valid key to write BSC_CR register; it needs to be written at the same time as the BOOT field. */ + +/*@}*/ + + +#endif /* _SAMA5_BSC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_can.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_can.h new file mode 100644 index 000000000..503cae3a8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_can.h @@ -0,0 +1,292 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_CAN_COMPONENT_ +#define _SAMA5_CAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAMA5_CAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CanMb hardware registers */ +typedef struct { + RwReg CAN_MMR; /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */ + RwReg CAN_MAM; /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */ + RwReg CAN_MID; /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */ + RwReg CAN_MFID; /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */ + RwReg CAN_MSR; /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */ + RwReg CAN_MDL; /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */ + RwReg CAN_MDH; /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */ + RwReg CAN_MCR; /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */ +} CanMb; +/** \brief Can hardware registers */ +#define CANMB_NUMBER 8 +typedef struct { + RwReg CAN_MR; /**< \brief (Can Offset: 0x0000) Mode Register */ + WoReg CAN_IER; /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */ + WoReg CAN_IDR; /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */ + RoReg CAN_IMR; /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */ + RoReg CAN_SR; /**< \brief (Can Offset: 0x0010) Status Register */ + RwReg CAN_BR; /**< \brief (Can Offset: 0x0014) Baudrate Register */ + RoReg CAN_TIM; /**< \brief (Can Offset: 0x0018) Timer Register */ + RoReg CAN_TIMESTP; /**< \brief (Can Offset: 0x001C) Timestamp Register */ + RoReg CAN_ECR; /**< \brief (Can Offset: 0x0020) Error Counter Register */ + WoReg CAN_TCR; /**< \brief (Can Offset: 0x0024) Transfer Command Register */ + WoReg CAN_ACR; /**< \brief (Can Offset: 0x0028) Abort Command Register */ + RoReg Reserved1[46]; + RwReg CAN_WPMR; /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */ + RoReg CAN_WPSR; /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */ + RoReg Reserved2[69]; + CanMb CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */ +#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */ +#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */ +#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */ +#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */ +#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */ +#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */ +#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */ +#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */ +/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */ +#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */ +#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */ +#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */ +#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */ +#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */ +#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */ +#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */ +#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */ +#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */ +#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */ +#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */ +#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */ +#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */ +#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */ +#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */ +#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */ +#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */ +#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */ +#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */ +#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */ +#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */ +/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */ +#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */ +#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */ +#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */ +#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */ +#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */ +#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */ +#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */ +#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */ +#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */ +#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */ +#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */ +#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */ +#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */ +#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */ +#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */ +#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */ +#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */ +#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */ +#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */ +#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */ +#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */ +/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */ +#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */ +#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */ +#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */ +#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */ +#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */ +#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */ +#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */ +#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */ +#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */ +#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */ +#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */ +#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */ +#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */ +#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */ +#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */ +#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */ +#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */ +#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */ +#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */ +#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */ +#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */ +/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */ +#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */ +#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */ +#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */ +#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */ +#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */ +#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */ +#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */ +#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */ +#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */ +#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */ +#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */ +#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */ +#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */ +#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */ +#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */ +#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR) */ +#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */ +#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */ +#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */ +#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */ +#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */ +#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */ +#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */ +#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */ +/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */ +#define CAN_BR_PHASE2_Pos 0 +#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */ +#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos))) +#define CAN_BR_PHASE1_Pos 4 +#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */ +#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos))) +#define CAN_BR_PROPAG_Pos 8 +#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */ +#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos))) +#define CAN_BR_SJW_Pos 12 +#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */ +#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos))) +#define CAN_BR_BRP_Pos 16 +#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */ +#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos))) +#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */ +#define CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */ +#define CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */ +/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */ +#define CAN_TIM_TIMER_Pos 0 +#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */ +#define CAN_TIMESTP_MTIMESTAMP_Pos 0 +#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */ +/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */ +#define CAN_ECR_REC_Pos 0 +#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_TEC_Pos 16 +#define CAN_ECR_TEC_Msk (0x1ffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */ +#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */ +#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */ +#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */ +#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */ +#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */ +#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */ +#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */ +#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */ +#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */ +/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */ +#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */ +#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */ +#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */ +#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */ +#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */ +#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */ +#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */ +#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */ +/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */ +#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */ +#define CAN_WPMR_WPKEY_Pos 8 +#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */ +#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos))) +/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */ +#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */ +#define CAN_WPSR_WPVSRC_Pos 8 +#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */ +/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */ +#define CAN_MMR_MTIMEMARK_Pos 0 +#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */ +#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos))) +#define CAN_MMR_PRIOR_Pos 16 +#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */ +#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos))) +#define CAN_MMR_MOT_Pos 24 +#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */ +#define CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */ +#define CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */ +#define CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */ +#define CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */ +#define CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */ +#define CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */ +/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */ +#define CAN_MAM_MIDvB_Pos 0 +#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */ +#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos))) +#define CAN_MAM_MIDvA_Pos 18 +#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */ +#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos))) +#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */ +/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */ +#define CAN_MID_MIDvB_Pos 0 +#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */ +#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos))) +#define CAN_MID_MIDvA_Pos 18 +#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */ +#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos))) +#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */ +/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */ +#define CAN_MFID_MFID_Pos 0 +#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */ +/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */ +#define CAN_MSR_MTIMESTAMP_Pos 0 +#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */ +#define CAN_MSR_MDLC_Pos 16 +#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */ +#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */ +#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */ +#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */ +#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */ +#define CAN_MDL_MDL_Pos 0 +#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */ +#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos))) +/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */ +#define CAN_MDH_MDH_Pos 0 +#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */ +#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos))) +/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */ +#define CAN_MCR_MDLC_Pos 16 +#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */ +#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos))) +#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */ +#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */ +#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */ + +/*@}*/ + + +#endif /* _SAMA5_CAN_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_dbgu.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_dbgu.h new file mode 100644 index 000000000..337e259f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_dbgu.h @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DBGU_COMPONENT_ +#define _SAMA5_DBGU_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Debug Unit */ +/* ============================================================================= */ +/** \addtogroup SAMA5_DBGU Debug Unit */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dbgu hardware registers */ +typedef struct { + WoReg DBGU_CR; /**< \brief (Dbgu Offset: 0x0000) Control Register */ + RwReg DBGU_MR; /**< \brief (Dbgu Offset: 0x0004) Mode Register */ + WoReg DBGU_IER; /**< \brief (Dbgu Offset: 0x0008) Interrupt Enable Register */ + WoReg DBGU_IDR; /**< \brief (Dbgu Offset: 0x000C) Interrupt Disable Register */ + RoReg DBGU_IMR; /**< \brief (Dbgu Offset: 0x0010) Interrupt Mask Register */ + RoReg DBGU_SR; /**< \brief (Dbgu Offset: 0x0014) Status Register */ + RoReg DBGU_RHR; /**< \brief (Dbgu Offset: 0x0018) Receive Holding Register */ + WoReg DBGU_THR; /**< \brief (Dbgu Offset: 0x001C) Transmit Holding Register */ + RwReg DBGU_BRGR; /**< \brief (Dbgu Offset: 0x0020) Baud Rate Generator Register */ + RoReg Reserved1[7]; + RoReg DBGU_CIDR; /**< \brief (Dbgu Offset: 0x0040) Chip ID Register */ + RoReg DBGU_EXID; /**< \brief (Dbgu Offset: 0x0044) Chip ID Extension Register */ + RwReg DBGU_FNR; /**< \brief (Dbgu Offset: 0x0048) Force NTRST Register */ +} Dbgu; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DBGU_CR : (DBGU Offset: 0x0000) Control Register -------- */ +#define DBGU_CR_RSTRX (0x1u << 2) /**< \brief (DBGU_CR) Reset Receiver */ +#define DBGU_CR_RSTTX (0x1u << 3) /**< \brief (DBGU_CR) Reset Transmitter */ +#define DBGU_CR_RXEN (0x1u << 4) /**< \brief (DBGU_CR) Receiver Enable */ +#define DBGU_CR_RXDIS (0x1u << 5) /**< \brief (DBGU_CR) Receiver Disable */ +#define DBGU_CR_TXEN (0x1u << 6) /**< \brief (DBGU_CR) Transmitter Enable */ +#define DBGU_CR_TXDIS (0x1u << 7) /**< \brief (DBGU_CR) Transmitter Disable */ +#define DBGU_CR_RSTSTA (0x1u << 8) /**< \brief (DBGU_CR) Reset Status Bits */ +/* -------- DBGU_MR : (DBGU Offset: 0x0004) Mode Register -------- */ +#define DBGU_MR_PAR_Pos 9 +#define DBGU_MR_PAR_Msk (0x7u << DBGU_MR_PAR_Pos) /**< \brief (DBGU_MR) Parity Type */ +#define DBGU_MR_PAR_EVEN (0x0u << 9) /**< \brief (DBGU_MR) Even Parity */ +#define DBGU_MR_PAR_ODD (0x1u << 9) /**< \brief (DBGU_MR) Odd Parity */ +#define DBGU_MR_PAR_SPACE (0x2u << 9) /**< \brief (DBGU_MR) Space: Parity forced to 0 */ +#define DBGU_MR_PAR_MARK (0x3u << 9) /**< \brief (DBGU_MR) Mark: Parity forced to 1 */ +#define DBGU_MR_PAR_NONE (0x4u << 9) /**< \brief (DBGU_MR) No Parity */ +#define DBGU_MR_CHMODE_Pos 14 +#define DBGU_MR_CHMODE_Msk (0x3u << DBGU_MR_CHMODE_Pos) /**< \brief (DBGU_MR) Channel Mode */ +#define DBGU_MR_CHMODE_NORM (0x0u << 14) /**< \brief (DBGU_MR) Normal Mode */ +#define DBGU_MR_CHMODE_AUTO (0x1u << 14) /**< \brief (DBGU_MR) Automatic Echo */ +#define DBGU_MR_CHMODE_LOCLOOP (0x2u << 14) /**< \brief (DBGU_MR) Local Loopback */ +#define DBGU_MR_CHMODE_REMLOOP (0x3u << 14) /**< \brief (DBGU_MR) Remote Loopback */ +/* -------- DBGU_IER : (DBGU Offset: 0x0008) Interrupt Enable Register -------- */ +#define DBGU_IER_RXRDY (0x1u << 0) /**< \brief (DBGU_IER) Enable RXRDY Interrupt */ +#define DBGU_IER_TXRDY (0x1u << 1) /**< \brief (DBGU_IER) Enable TXRDY Interrupt */ +#define DBGU_IER_OVRE (0x1u << 5) /**< \brief (DBGU_IER) Enable Overrun Error Interrupt */ +#define DBGU_IER_FRAME (0x1u << 6) /**< \brief (DBGU_IER) Enable Framing Error Interrupt */ +#define DBGU_IER_PARE (0x1u << 7) /**< \brief (DBGU_IER) Enable Parity Error Interrupt */ +#define DBGU_IER_TXEMPTY (0x1u << 9) /**< \brief (DBGU_IER) Enable TXEMPTY Interrupt */ +#define DBGU_IER_COMMTX (0x1u << 30) /**< \brief (DBGU_IER) Enable COMMTX (from ARM) Interrupt */ +#define DBGU_IER_COMMRX (0x1u << 31) /**< \brief (DBGU_IER) Enable COMMRX (from ARM) Interrupt */ +/* -------- DBGU_IDR : (DBGU Offset: 0x000C) Interrupt Disable Register -------- */ +#define DBGU_IDR_RXRDY (0x1u << 0) /**< \brief (DBGU_IDR) Disable RXRDY Interrupt */ +#define DBGU_IDR_TXRDY (0x1u << 1) /**< \brief (DBGU_IDR) Disable TXRDY Interrupt */ +#define DBGU_IDR_OVRE (0x1u << 5) /**< \brief (DBGU_IDR) Disable Overrun Error Interrupt */ +#define DBGU_IDR_FRAME (0x1u << 6) /**< \brief (DBGU_IDR) Disable Framing Error Interrupt */ +#define DBGU_IDR_PARE (0x1u << 7) /**< \brief (DBGU_IDR) Disable Parity Error Interrupt */ +#define DBGU_IDR_TXEMPTY (0x1u << 9) /**< \brief (DBGU_IDR) Disable TXEMPTY Interrupt */ +#define DBGU_IDR_COMMTX (0x1u << 30) /**< \brief (DBGU_IDR) Disable COMMTX (from ARM) Interrupt */ +#define DBGU_IDR_COMMRX (0x1u << 31) /**< \brief (DBGU_IDR) Disable COMMRX (from ARM) Interrupt */ +/* -------- DBGU_IMR : (DBGU Offset: 0x0010) Interrupt Mask Register -------- */ +#define DBGU_IMR_RXRDY (0x1u << 0) /**< \brief (DBGU_IMR) Mask RXRDY Interrupt */ +#define DBGU_IMR_TXRDY (0x1u << 1) /**< \brief (DBGU_IMR) Disable TXRDY Interrupt */ +#define DBGU_IMR_OVRE (0x1u << 5) /**< \brief (DBGU_IMR) Mask Overrun Error Interrupt */ +#define DBGU_IMR_FRAME (0x1u << 6) /**< \brief (DBGU_IMR) Mask Framing Error Interrupt */ +#define DBGU_IMR_PARE (0x1u << 7) /**< \brief (DBGU_IMR) Mask Parity Error Interrupt */ +#define DBGU_IMR_TXEMPTY (0x1u << 9) /**< \brief (DBGU_IMR) Mask TXEMPTY Interrupt */ +#define DBGU_IMR_COMMTX (0x1u << 30) /**< \brief (DBGU_IMR) Mask COMMTX Interrupt */ +#define DBGU_IMR_COMMRX (0x1u << 31) /**< \brief (DBGU_IMR) Mask COMMRX Interrupt */ +/* -------- DBGU_SR : (DBGU Offset: 0x0014) Status Register -------- */ +#define DBGU_SR_RXRDY (0x1u << 0) /**< \brief (DBGU_SR) Receiver Ready */ +#define DBGU_SR_TXRDY (0x1u << 1) /**< \brief (DBGU_SR) Transmitter Ready */ +#define DBGU_SR_OVRE (0x1u << 5) /**< \brief (DBGU_SR) Overrun Error */ +#define DBGU_SR_FRAME (0x1u << 6) /**< \brief (DBGU_SR) Framing Error */ +#define DBGU_SR_PARE (0x1u << 7) /**< \brief (DBGU_SR) Parity Error */ +#define DBGU_SR_TXEMPTY (0x1u << 9) /**< \brief (DBGU_SR) Transmitter Empty */ +#define DBGU_SR_COMMTX (0x1u << 30) /**< \brief (DBGU_SR) Debug Communication Channel Write Status */ +#define DBGU_SR_COMMRX (0x1u << 31) /**< \brief (DBGU_SR) Debug Communication Channel Read Status */ +/* -------- DBGU_RHR : (DBGU Offset: 0x0018) Receive Holding Register -------- */ +#define DBGU_RHR_RXCHR_Pos 0 +#define DBGU_RHR_RXCHR_Msk (0xffu << DBGU_RHR_RXCHR_Pos) /**< \brief (DBGU_RHR) Received Character */ +/* -------- DBGU_THR : (DBGU Offset: 0x001C) Transmit Holding Register -------- */ +#define DBGU_THR_TXCHR_Pos 0 +#define DBGU_THR_TXCHR_Msk (0xffu << DBGU_THR_TXCHR_Pos) /**< \brief (DBGU_THR) Character to be Transmitted */ +#define DBGU_THR_TXCHR(value) ((DBGU_THR_TXCHR_Msk & ((value) << DBGU_THR_TXCHR_Pos))) +/* -------- DBGU_BRGR : (DBGU Offset: 0x0020) Baud Rate Generator Register -------- */ +#define DBGU_BRGR_CD_Pos 0 +#define DBGU_BRGR_CD_Msk (0xffffu << DBGU_BRGR_CD_Pos) /**< \brief (DBGU_BRGR) Clock Divisor */ +#define DBGU_BRGR_CD_DISABLED (0x0u << 0) /**< \brief (DBGU_BRGR) DBGU Disabled */ +#define DBGU_BRGR_CD_MCK (0x1u << 0) /**< \brief (DBGU_BRGR) MCK */ +/* -------- DBGU_CIDR : (DBGU Offset: 0x0040) Chip ID Register -------- */ +#define DBGU_CIDR_VERSION_Pos 0 +#define DBGU_CIDR_VERSION_Msk (0x1fu << DBGU_CIDR_VERSION_Pos) /**< \brief (DBGU_CIDR) Version of the Device */ +#define DBGU_CIDR_EPROC_Pos 5 +#define DBGU_CIDR_EPROC_Msk (0x7u << DBGU_CIDR_EPROC_Pos) /**< \brief (DBGU_CIDR) Embedded Processor */ +#define DBGU_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (DBGU_CIDR) ARM946ES */ +#define DBGU_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (DBGU_CIDR) ARM7TDMI */ +#define DBGU_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (DBGU_CIDR) Cortex-M3 */ +#define DBGU_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (DBGU_CIDR) ARM920T */ +#define DBGU_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (DBGU_CIDR) ARM926EJS */ +#define DBGU_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (DBGU_CIDR) Cortex-A5 */ +#define DBGU_CIDR_NVPSIZ_Pos 8 +#define DBGU_CIDR_NVPSIZ_Msk (0xfu << DBGU_CIDR_NVPSIZ_Pos) /**< \brief (DBGU_CIDR) Nonvolatile Program Memory Size */ +#define DBGU_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (DBGU_CIDR) None */ +#define DBGU_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (DBGU_CIDR) 8K bytes */ +#define DBGU_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (DBGU_CIDR) 16K bytes */ +#define DBGU_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (DBGU_CIDR) 32K bytes */ +#define DBGU_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (DBGU_CIDR) 64K bytes */ +#define DBGU_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (DBGU_CIDR) 128K bytes */ +#define DBGU_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (DBGU_CIDR) 256K bytes */ +#define DBGU_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (DBGU_CIDR) 512K bytes */ +#define DBGU_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (DBGU_CIDR) 1024K bytes */ +#define DBGU_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (DBGU_CIDR) 2048K bytes */ +#define DBGU_CIDR_NVPSIZ2_Pos 12 +#define DBGU_CIDR_NVPSIZ2_Msk (0xfu << DBGU_CIDR_NVPSIZ2_Pos) /**< \brief (DBGU_CIDR) */ +#define DBGU_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (DBGU_CIDR) None */ +#define DBGU_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (DBGU_CIDR) 8K bytes */ +#define DBGU_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (DBGU_CIDR) 16K bytes */ +#define DBGU_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (DBGU_CIDR) 32K bytes */ +#define DBGU_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (DBGU_CIDR) 64K bytes */ +#define DBGU_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (DBGU_CIDR) 128K bytes */ +#define DBGU_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (DBGU_CIDR) 256K bytes */ +#define DBGU_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (DBGU_CIDR) 512K bytes */ +#define DBGU_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (DBGU_CIDR) 1024K bytes */ +#define DBGU_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (DBGU_CIDR) 2048K bytes */ +#define DBGU_CIDR_SRAMSIZ_Pos 16 +#define DBGU_CIDR_SRAMSIZ_Msk (0xfu << DBGU_CIDR_SRAMSIZ_Pos) /**< \brief (DBGU_CIDR) Internal SRAM Size */ +#define DBGU_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (DBGU_CIDR) 1K bytes */ +#define DBGU_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (DBGU_CIDR) 2K bytes */ +#define DBGU_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (DBGU_CIDR) 6K bytes */ +#define DBGU_CIDR_SRAMSIZ_112K (0x4u << 16) /**< \brief (DBGU_CIDR) 112K bytes */ +#define DBGU_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (DBGU_CIDR) 4K bytes */ +#define DBGU_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (DBGU_CIDR) 80K bytes */ +#define DBGU_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (DBGU_CIDR) 160K bytes */ +#define DBGU_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (DBGU_CIDR) 8K bytes */ +#define DBGU_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (DBGU_CIDR) 16K bytes */ +#define DBGU_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (DBGU_CIDR) 32K bytes */ +#define DBGU_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (DBGU_CIDR) 64K bytes */ +#define DBGU_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (DBGU_CIDR) 128K bytes */ +#define DBGU_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (DBGU_CIDR) 256K bytes */ +#define DBGU_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (DBGU_CIDR) 96K bytes */ +#define DBGU_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (DBGU_CIDR) 512K bytes */ +#define DBGU_CIDR_ARCH_Pos 20 +#define DBGU_CIDR_ARCH_Msk (0xffu << DBGU_CIDR_ARCH_Pos) /**< \brief (DBGU_CIDR) Architecture Identifier */ +#define DBGU_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (DBGU_CIDR) AT91SAM9xx Series */ +#define DBGU_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (DBGU_CIDR) AT91SAM9XExx Series */ +#define DBGU_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (DBGU_CIDR) AT91x34 Series */ +#define DBGU_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (DBGU_CIDR) CAP7 Series */ +#define DBGU_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (DBGU_CIDR) CAP9 Series */ +#define DBGU_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (DBGU_CIDR) CAP11 Series */ +#define DBGU_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (DBGU_CIDR) AT91x40 Series */ +#define DBGU_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (DBGU_CIDR) AT91x42 Series */ +#define DBGU_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (DBGU_CIDR) AT91x55 Series */ +#define DBGU_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Axx Series */ +#define DBGU_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (DBGU_CIDR) AT91SAM7AQxx Series */ +#define DBGU_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (DBGU_CIDR) AT91x63 Series */ +#define DBGU_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Sxx Series */ +#define DBGU_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (DBGU_CIDR) AT91SAM7XCxx Series */ +#define DBGU_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (DBGU_CIDR) AT91SAM7SExx Series */ +#define DBGU_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Lxx Series */ +#define DBGU_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (DBGU_CIDR) AT91SAM7Xxx Series */ +#define DBGU_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (DBGU_CIDR) AT91SAM7SLxx Series */ +#define DBGU_CIDR_ARCH_ATSAM3UxC (0x80u << 20) /**< \brief (DBGU_CIDR) ATSAM3UxC Series (100-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3UxE (0x81u << 20) /**< \brief (DBGU_CIDR) ATSAM3UxE Series (144-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3AxC (0x83u << 20) /**< \brief (DBGU_CIDR) ATSAM3AxC Series (100-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3XxC (0x84u << 20) /**< \brief (DBGU_CIDR) ATSAM3XxC Series (100-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3XxE (0x85u << 20) /**< \brief (DBGU_CIDR) ATSAM3XxE Series (144-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3XxG (0x86u << 20) /**< \brief (DBGU_CIDR) ATSAM3XxG Series (208/217-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3SxA (0x88u << 20) /**< \brief (DBGU_CIDR) ATSAM3SxA Series (48-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3SxB (0x89u << 20) /**< \brief (DBGU_CIDR) ATSAM3SxB Series (64-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3SxC (0x8Au << 20) /**< \brief (DBGU_CIDR) ATSAM3SxC Series (100-pin version) */ +#define DBGU_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (DBGU_CIDR) AT91x92 Series */ +#define DBGU_CIDR_ARCH_ATSAM3NxA (0x93u << 20) /**< \brief (DBGU_CIDR) ATSAM3NxA Series (48-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3NxB (0x94u << 20) /**< \brief (DBGU_CIDR) ATSAM3NxB Series (64-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3NxC (0x95u << 20) /**< \brief (DBGU_CIDR) ATSAM3NxC Series (100-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3SDxA (0x98u << 20) /**< \brief (DBGU_CIDR) ATSAM3SDxA Series (48-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3SDxB (0x99u << 20) /**< \brief (DBGU_CIDR) ATSAM3SDxB Series (64-pin version) */ +#define DBGU_CIDR_ARCH_ATSAM3SDxC (0x9Au << 20) /**< \brief (DBGU_CIDR) ATSAM3SDxC Series (100-pin version) */ +#define DBGU_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (DBGU_CIDR) AT75Cxx Series */ +#define DBGU_CIDR_NVPTYP_Pos 28 +#define DBGU_CIDR_NVPTYP_Msk (0x7u << DBGU_CIDR_NVPTYP_Pos) /**< \brief (DBGU_CIDR) Nonvolatile Program Memory Type */ +#define DBGU_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (DBGU_CIDR) ROM */ +#define DBGU_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (DBGU_CIDR) ROMless or on-chip Flash */ +#define DBGU_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (DBGU_CIDR) Embedded Flash Memory */ +#define DBGU_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (DBGU_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */ +#define DBGU_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (DBGU_CIDR) SRAM emulating ROM */ +#define DBGU_CIDR_EXT (0x1u << 31) /**< \brief (DBGU_CIDR) Extension Flag */ +/* -------- DBGU_EXID : (DBGU Offset: 0x0044) Chip ID Extension Register -------- */ +#define DBGU_EXID_EXID_Pos 0 +#define DBGU_EXID_EXID_Msk (0xffffffffu << DBGU_EXID_EXID_Pos) /**< \brief (DBGU_EXID) Chip ID Extension */ +/* -------- DBGU_FNR : (DBGU Offset: 0x0048) Force NTRST Register -------- */ +#define DBGU_FNR_FNTRST (0x1u << 0) /**< \brief (DBGU_FNR) Force NTRST */ + +/*@}*/ + + +#endif /* _SAMA5_DBGU_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_dmac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_dmac.h new file mode 100644 index 000000000..a7aeecf46 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_dmac.h @@ -0,0 +1,508 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DMAC_COMPONENT_ +#define _SAMA5_DMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_DMAC DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DmacCh_num hardware registers */ +typedef struct { + RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */ + RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */ + RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */ + RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */ + RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */ + RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */ + RwReg DMAC_SPIP; /**< \brief (DmacCh_num Offset: 0x18) DMAC Channel Source Picture-in-Picture Configuration Register */ + RwReg DMAC_DPIP; /**< \brief (DmacCh_num Offset: 0x1C) DMAC Channel Destination Picture-in-Picture Configuration Register */ + RoReg Reserved1[2]; +} DmacCh_num; +/** \brief Dmac hardware registers */ +#define DMACCH_NUM_NUMBER 8 +typedef struct { + RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */ + RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */ + RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */ + RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */ + RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */ + RoReg Reserved1[1]; + WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ + WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ + RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ + RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ + WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */ + WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */ + RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */ + RoReg Reserved2[2]; + DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 7 */ + RoReg Reserved3[26]; + RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */ + RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */ +} Dmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */ +#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */ +#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */ +#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */ +#define DMAC_GCFG_DICEN (0x1u << 8) /**< \brief (DMAC_GCFG) Descriptor Integrity Check */ +/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */ +#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */ +/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */ +#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ6 (0x1u << 12) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ6 (0x1u << 13) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ7 (0x1u << 14) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ7 (0x1u << 15) /**< \brief (DMAC_SREQ) Destination Request */ +/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */ +#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ6 (0x1u << 12) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ6 (0x1u << 13) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ7 (0x1u << 14) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ7 (0x1u << 15) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */ +#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST6 (0x1u << 12) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST6 (0x1u << 13) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST7 (0x1u << 14) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST7 (0x1u << 15) /**< \brief (DMAC_LAST) Destination Last */ +/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */ +#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCIER) Access Error [7:0] */ +#define DMAC_EBCIER_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIER_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCIER) Descriptor Integrity Check Error [7:0] */ +/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */ +#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCIDR) Access Error [7:0] */ +#define DMAC_EBCIDR_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIDR_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCIDR) Descriptor Integrity Check Error [7:0] */ +/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */ +#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCIMR) Access Error [7:0] */ +#define DMAC_EBCIMR_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCIMR_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCIMR) Descriptor Integrity Check Error [7:0] */ +/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */ +#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC6 (0x1u << 6) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_BTC7 (0x1u << 7) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC6 (0x1u << 14) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_CBTC7 (0x1u << 15) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [7:0] */ +#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR6 (0x1u << 22) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_ERR7 (0x1u << 23) /**< \brief (DMAC_EBCISR) Access Error [7:0] */ +#define DMAC_EBCISR_DICERR0 (0x1u << 24) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR1 (0x1u << 25) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR2 (0x1u << 26) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR3 (0x1u << 27) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR4 (0x1u << 28) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR5 (0x1u << 29) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR6 (0x1u << 30) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +#define DMAC_EBCISR_DICERR7 (0x1u << 31) /**< \brief (DMAC_EBCISR) Descriptor Integrity Check Error [7:0] */ +/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */ +#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA6 (0x1u << 6) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_ENA7 (0x1u << 7) /**< \brief (DMAC_CHER) Enable [7:0] */ +#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP6 (0x1u << 14) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_SUSP7 (0x1u << 15) /**< \brief (DMAC_CHER) Suspend [7:0] */ +#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP6 (0x1u << 30) /**< \brief (DMAC_CHER) Keep on [7:0] */ +#define DMAC_CHER_KEEP7 (0x1u << 31) /**< \brief (DMAC_CHER) Keep on [7:0] */ +/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */ +#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS6 (0x1u << 6) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_DIS7 (0x1u << 7) /**< \brief (DMAC_CHDR) Disable [7:0] */ +#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES6 (0x1u << 14) /**< \brief (DMAC_CHDR) Resume [7:0] */ +#define DMAC_CHDR_RES7 (0x1u << 15) /**< \brief (DMAC_CHDR) Resume [7:0] */ +/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */ +#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA6 (0x1u << 6) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_ENA7 (0x1u << 7) /**< \brief (DMAC_CHSR) Enable [7:0] */ +#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP6 (0x1u << 14) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_SUSP7 (0x1u << 15) /**< \brief (DMAC_CHSR) Suspend [7:0] */ +#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT6 (0x1u << 22) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_EMPT7 (0x1u << 23) /**< \brief (DMAC_CHSR) Empty [7:0] */ +#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL6 (0x1u << 30) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +#define DMAC_CHSR_STAL7 (0x1u << 31) /**< \brief (DMAC_CHSR) Stalled [7:0] */ +/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */ +#define DMAC_SADDR_SADDR_Pos 0 +#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */ +#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos))) +/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */ +#define DMAC_DADDR_DADDR_Pos 0 +#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */ +#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos))) +/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */ +#define DMAC_DSCR_DSCR_IF_Pos 0 +#define DMAC_DSCR_DSCR_IF_Msk (0x3u << DMAC_DSCR_DSCR_IF_Pos) /**< \brief (DMAC_DSCR) */ +#define DMAC_DSCR_DSCR_IF_AHB_IF0 (0x0u << 0) /**< \brief (DMAC_DSCR) The buffer transfer descriptor is fetched via AHB-Lite Interface 0 */ +#define DMAC_DSCR_DSCR_IF_AHB_IF1 (0x1u << 0) /**< \brief (DMAC_DSCR) The buffer transfer descriptor is fetched via AHB-Lite Interface 1 */ +#define DMAC_DSCR_DSCR_IF_AHB_IF2 (0x2u << 0) /**< \brief (DMAC_DSCR) The buffer transfer descriptor is fetched via AHB-Lite Interface 2 */ +#define DMAC_DSCR_DSCR_Pos 2 +#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */ +#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos))) +/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */ +#define DMAC_CTRLA_BTSIZE_Pos 0 +#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */ +#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos))) +#define DMAC_CTRLA_SCSIZE_Pos 16 +#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */ +#define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */ +#define DMAC_CTRLA_DCSIZE_Pos 20 +#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */ +#define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */ +#define DMAC_CTRLA_SRC_WIDTH_Pos 24 +#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */ +#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ +#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ +#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ +#define DMAC_CTRLA_SRC_WIDTH_DWORD (0x3u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 64-bit width */ +#define DMAC_CTRLA_DST_WIDTH_Pos 28 +#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */ +#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ +#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ +#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ +#define DMAC_CTRLA_DST_WIDTH_DWORD (0x3u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 64-bit width */ +#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */ +/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */ +#define DMAC_CTRLB_SIF_Pos 0 +#define DMAC_CTRLB_SIF_Msk (0x3u << DMAC_CTRLB_SIF_Pos) /**< \brief (DMAC_CTRLB) Source Interface Selection Field */ +#define DMAC_CTRLB_SIF_AHB_IF0 (0x0u << 0) /**< \brief (DMAC_CTRLB) The source transfer is done via AHB-Lite Interface 0 */ +#define DMAC_CTRLB_SIF_AHB_IF1 (0x1u << 0) /**< \brief (DMAC_CTRLB) The source transfer is done via AHB-Lite Interface 1 */ +#define DMAC_CTRLB_SIF_AHB_IF2 (0x2u << 0) /**< \brief (DMAC_CTRLB) The source transfer is done via AHB-Lite Interface 2 */ +#define DMAC_CTRLB_DIF_Pos 4 +#define DMAC_CTRLB_DIF_Msk (0x3u << DMAC_CTRLB_DIF_Pos) /**< \brief (DMAC_CTRLB) Destination Interface Selection Field */ +#define DMAC_CTRLB_DIF_AHB_IF0 (0x0u << 4) /**< \brief (DMAC_CTRLB) The destination transfer is done via AHB-Lite Interface 0 */ +#define DMAC_CTRLB_DIF_AHB_IF1 (0x1u << 4) /**< \brief (DMAC_CTRLB) The destination transfer is done via AHB-Lite Interface 1 */ +#define DMAC_CTRLB_DIF_AHB_IF2 (0x2u << 4) /**< \brief (DMAC_CTRLB) The destination transfer is done via AHB-Lite Interface 2 */ +#define DMAC_CTRLB_SRC_PIP (0x1u << 8) /**< \brief (DMAC_CTRLB) Source Picture-in-Picture Mode */ +#define DMAC_CTRLB_SRC_PIP_DISABLE (0x0u << 8) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is disabled. The source data area is contiguous. */ +#define DMAC_CTRLB_SRC_PIP_ENABLE (0x1u << 8) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount. */ +#define DMAC_CTRLB_DST_PIP (0x1u << 12) /**< \brief (DMAC_CTRLB) Destination Picture-in-Picture Mode */ +#define DMAC_CTRLB_DST_PIP_DISABLE (0x0u << 12) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is disabled. The Destination data area is contiguous. */ +#define DMAC_CTRLB_DST_PIP_ENABLE (0x1u << 12) /**< \brief (DMAC_CTRLB) Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount. */ +#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */ +#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */ +#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */ +#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */ +#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */ +#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */ +#define DMAC_CTRLB_FC_Pos 21 +#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */ +#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */ +#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */ +#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */ +#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */ +#define DMAC_CTRLB_SRC_INCR_Pos 24 +#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */ +#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */ +#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */ +#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */ +#define DMAC_CTRLB_DST_INCR_Pos 28 +#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */ +#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */ +#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */ +#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */ +#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */ +#define DMAC_CTRLB_AUTO (0x1u << 31) /**< \brief (DMAC_CTRLB) Automatic Multiple Buffer Transfer */ +#define DMAC_CTRLB_AUTO_DISABLE (0x0u << 31) /**< \brief (DMAC_CTRLB) Automatic multiple buffer transfer is disabled. */ +#define DMAC_CTRLB_AUTO_ENABLE (0x1u << 31) /**< \brief (DMAC_CTRLB) Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred. */ +/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */ +#define DMAC_CFG_SRC_PER_Pos 0 +#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */ +#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos))) +#define DMAC_CFG_DST_PER_Pos 4 +#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */ +#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos))) +#define DMAC_CFG_SRC_REP (0x1u << 8) /**< \brief (DMAC_CFG) Source Reloaded from Previous */ +#define DMAC_CFG_SRC_REP_CONTIGUOUS_ADDR (0x0u << 8) /**< \brief (DMAC_CFG) When automatic mode is activated, source address is contiguous between two buffers. */ +#define DMAC_CFG_SRC_REP_RELOAD_ADDR (0x1u << 8) /**< \brief (DMAC_CFG) When automatic mode is activated, the source address and the control register are reloaded from previous transfer. */ +#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */ +#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_SRC_PER_MSB_Pos 10 +#define DMAC_CFG_SRC_PER_MSB_Msk (0x3u << DMAC_CFG_SRC_PER_MSB_Pos) /**< \brief (DMAC_CFG) SRC_PER Most Significant Bits */ +#define DMAC_CFG_SRC_PER_MSB(value) ((DMAC_CFG_SRC_PER_MSB_Msk & ((value) << DMAC_CFG_SRC_PER_MSB_Pos))) +#define DMAC_CFG_DST_REP (0x1u << 12) /**< \brief (DMAC_CFG) Destination Reloaded from Previous */ +#define DMAC_CFG_DST_REP_CONTIGUOUS_ADDR (0x0u << 12) /**< \brief (DMAC_CFG) When automatic mode is activated, destination address is contiguous between two buffers. */ +#define DMAC_CFG_DST_REP_RELOAD_ADDR (0x1u << 12) /**< \brief (DMAC_CFG) When automatic mode is activated, the destination and the control register are reloaded from the pre-vious transfer. */ +#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */ +#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_DST_PER_MSB_Pos 14 +#define DMAC_CFG_DST_PER_MSB_Msk (0x3u << DMAC_CFG_DST_PER_MSB_Pos) /**< \brief (DMAC_CFG) DST_PER Most Significant Bits */ +#define DMAC_CFG_DST_PER_MSB(value) ((DMAC_CFG_DST_PER_MSB_Msk & ((value) << DMAC_CFG_DST_PER_MSB_Pos))) +#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */ +#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */ +#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */ +#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */ +#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */ +#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */ +#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */ +#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */ +#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */ +#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */ +#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */ +#define DMAC_CFG_AHB_PROT_Pos 24 +#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */ +#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos))) +#define DMAC_CFG_FIFOCFG_Pos 28 +#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */ +#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */ +#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */ +#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */ +/* -------- DMAC_SPIP : (DMAC Offset: N/A) DMAC Channel Source Picture-in-Picture Configuration Register -------- */ +#define DMAC_SPIP_SPIP_HOLE_Pos 0 +#define DMAC_SPIP_SPIP_HOLE_Msk (0xffffu << DMAC_SPIP_SPIP_HOLE_Pos) /**< \brief (DMAC_SPIP) Source Picture-in-Picture Hole */ +#define DMAC_SPIP_SPIP_HOLE(value) ((DMAC_SPIP_SPIP_HOLE_Msk & ((value) << DMAC_SPIP_SPIP_HOLE_Pos))) +#define DMAC_SPIP_SPIP_BOUNDARY_Pos 16 +#define DMAC_SPIP_SPIP_BOUNDARY_Msk (0x3ffu << DMAC_SPIP_SPIP_BOUNDARY_Pos) /**< \brief (DMAC_SPIP) Source Picture-in-Picture Boundary */ +#define DMAC_SPIP_SPIP_BOUNDARY(value) ((DMAC_SPIP_SPIP_BOUNDARY_Msk & ((value) << DMAC_SPIP_SPIP_BOUNDARY_Pos))) +/* -------- DMAC_DPIP : (DMAC Offset: N/A) DMAC Channel Destination Picture-in-Picture Configuration Register -------- */ +#define DMAC_DPIP_DPIP_HOLE_Pos 0 +#define DMAC_DPIP_DPIP_HOLE_Msk (0xffffu << DMAC_DPIP_DPIP_HOLE_Pos) /**< \brief (DMAC_DPIP) Destination Picture-in-Picture Hole */ +#define DMAC_DPIP_DPIP_HOLE(value) ((DMAC_DPIP_DPIP_HOLE_Msk & ((value) << DMAC_DPIP_DPIP_HOLE_Pos))) +#define DMAC_DPIP_DPIP_BOUNDARY_Pos 16 +#define DMAC_DPIP_DPIP_BOUNDARY_Msk (0x3ffu << DMAC_DPIP_DPIP_BOUNDARY_Pos) /**< \brief (DMAC_DPIP) Destination Picture-in-Picture Boundary */ +#define DMAC_DPIP_DPIP_BOUNDARY(value) ((DMAC_DPIP_DPIP_BOUNDARY_Msk & ((value) << DMAC_DPIP_DPIP_BOUNDARY_Pos))) +/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */ +#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */ +#define DMAC_WPMR_WPKEY_Pos 8 +#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */ +#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos))) +/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */ +#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */ +#define DMAC_WPSR_WPVSRC_Pos 8 +#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_DMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_emac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_emac.h new file mode 100644 index 000000000..4f3f27f09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_emac.h @@ -0,0 +1,348 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_EMAC_COMPONENT_ +#define _SAMA5_EMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ============================================================================= */ +/** \addtogroup SAMA5_EMAC Ethernet MAC 10/100 */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief EmacSa hardware registers */ +typedef struct { + RwReg EMAC_SAxB; /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + RwReg EMAC_SAxT; /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */ +} EmacSa; +/** \brief Emac hardware registers */ +#define EMACSA_NUMBER 4 +typedef struct { + RwReg EMAC_NCR; /**< \brief (Emac Offset: 0x00) Network Control Register */ + RwReg EMAC_NCFGR; /**< \brief (Emac Offset: 0x04) Network Configuration Register */ + RoReg EMAC_NSR; /**< \brief (Emac Offset: 0x08) Network Status Register */ + RoReg Reserved1[2]; + RwReg EMAC_TSR; /**< \brief (Emac Offset: 0x14) Transmit Status Register */ + RwReg EMAC_RBQP; /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */ + RwReg EMAC_TBQP; /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */ + RwReg EMAC_RSR; /**< \brief (Emac Offset: 0x20) Receive Status Register */ + RwReg EMAC_ISR; /**< \brief (Emac Offset: 0x24) Interrupt Status Register */ + WoReg EMAC_IER; /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */ + WoReg EMAC_IDR; /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */ + RoReg EMAC_IMR; /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */ + RwReg EMAC_MAN; /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */ + RwReg EMAC_PTR; /**< \brief (Emac Offset: 0x38) Pause Time Register */ + RwReg EMAC_PFR; /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */ + RwReg EMAC_FTO; /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */ + RwReg EMAC_SCF; /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */ + RwReg EMAC_MCF; /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */ + RwReg EMAC_FRO; /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */ + RwReg EMAC_FCSE; /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */ + RwReg EMAC_ALE; /**< \brief (Emac Offset: 0x54) Alignment Errors Register */ + RwReg EMAC_DTF; /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */ + RwReg EMAC_LCOL; /**< \brief (Emac Offset: 0x5C) Late Collisions Register */ + RwReg EMAC_ECOL; /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */ + RwReg EMAC_TUND; /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */ + RwReg EMAC_CSE; /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */ + RwReg EMAC_RRE; /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */ + RwReg EMAC_ROV; /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */ + RwReg EMAC_RSE; /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */ + RwReg EMAC_ELE; /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */ + RwReg EMAC_RJA; /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */ + RwReg EMAC_USF; /**< \brief (Emac Offset: 0x80) Undersize Frames Register */ + RwReg EMAC_STE; /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */ + RwReg EMAC_RLE; /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */ + RoReg Reserved2[1]; + RwReg EMAC_HRB; /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */ + RwReg EMAC_HRT; /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */ + EmacSa EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */ + RwReg EMAC_TID; /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */ + RoReg Reserved3[1]; + RwReg EMAC_USRIO; /**< \brief (Emac Offset: 0xC0) User Input/Output Register */ + RwReg EMAC_WOL; /**< \brief (Emac Offset: 0xC4) Wake on LAN Register */ +} Emac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */ +#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */ +#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */ +#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */ +#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */ +#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */ +#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */ +#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */ +#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */ +#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */ +#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */ +#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */ +#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */ +#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */ +#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */ +#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */ +#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */ +#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */ +#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */ +#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */ +#define EMAC_NCFGR_CLK_Pos 10 +#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */ +#define EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */ +#define EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */ +#define EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */ +#define EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */ +#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */ +#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */ +#define EMAC_NCFGR_RBOF_Pos 14 +#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */ +#define EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */ +#define EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */ +#define EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */ +#define EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */ +#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */ +#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */ +#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR) */ +#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */ +#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR) */ +#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */ +#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */ +#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */ +#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */ +#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */ +#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */ +#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */ +/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */ +#define EMAC_RBQP_ADDR_Pos 2 +#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */ +#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos))) +/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */ +#define EMAC_TBQP_ADDR_Pos 2 +#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */ +#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos))) +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */ +#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */ +#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */ +#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */ +#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */ +#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */ +#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */ +#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */ +#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */ +#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */ +#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */ +#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */ +#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */ +#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */ +#define EMAC_ISR_WOL (0x1u << 14) /**< \brief (EMAC_ISR) Wake On LAN */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */ +#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */ +#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */ +#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */ +#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */ +#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */ +#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER) */ +#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */ +#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */ +#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */ +#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */ +#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */ +#define EMAC_IER_WOL (0x1u << 14) /**< \brief (EMAC_IER) Wake On LAN */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */ +#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */ +#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */ +#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */ +#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */ +#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */ +#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */ +#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR) */ +#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */ +#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */ +#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */ +#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */ +#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */ +#define EMAC_IDR_WOL (0x1u << 14) /**< \brief (EMAC_IDR) Wake On LAN */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */ +#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */ +#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */ +#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */ +#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */ +#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */ +#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR) */ +#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */ +#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */ +#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */ +#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */ +#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */ +#define EMAC_IMR_WOL (0x1u << 14) /**< \brief (EMAC_IMR) Wake On LAN */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */ +#define EMAC_MAN_DATA_Pos 0 +#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN) */ +#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos))) +#define EMAC_MAN_CODE_Pos 16 +#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN) */ +#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos))) +#define EMAC_MAN_REGA_Pos 18 +#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */ +#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos))) +#define EMAC_MAN_PHYA_Pos 23 +#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */ +#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos))) +#define EMAC_MAN_RW_Pos 28 +#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */ +#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos))) +#define EMAC_MAN_SOF_Pos 30 +#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */ +#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos))) +/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */ +#define EMAC_PTR_PTIME_Pos 0 +#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */ +#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos))) +/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */ +#define EMAC_PFR_FROK_Pos 0 +#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */ +#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos))) +/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */ +#define EMAC_FTO_FTOK_Pos 0 +#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */ +#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos))) +/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */ +#define EMAC_SCF_SCF_Pos 0 +#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */ +#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos))) +/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */ +#define EMAC_MCF_MCF_Pos 0 +#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */ +#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos))) +/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */ +#define EMAC_FRO_FROK_Pos 0 +#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */ +#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos))) +/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */ +#define EMAC_FCSE_FCSE_Pos 0 +#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */ +#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos))) +/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */ +#define EMAC_ALE_ALE_Pos 0 +#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */ +#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos))) +/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */ +#define EMAC_DTF_DTF_Pos 0 +#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */ +#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos))) +/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */ +#define EMAC_LCOL_LCOL_Pos 0 +#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */ +#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos))) +/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */ +#define EMAC_ECOL_EXCOL_Pos 0 +#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */ +#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos))) +/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */ +#define EMAC_TUND_TUND_Pos 0 +#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */ +#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos))) +/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */ +#define EMAC_CSE_CSE_Pos 0 +#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */ +#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos))) +/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */ +#define EMAC_RRE_RRE_Pos 0 +#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */ +#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos))) +/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */ +#define EMAC_ROV_ROVR_Pos 0 +#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */ +#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos))) +/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */ +#define EMAC_RSE_RSE_Pos 0 +#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */ +#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos))) +/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */ +#define EMAC_ELE_EXL_Pos 0 +#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */ +#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos))) +/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */ +#define EMAC_RJA_RJB_Pos 0 +#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */ +#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos))) +/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */ +#define EMAC_USF_USF_Pos 0 +#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */ +#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos))) +/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */ +#define EMAC_STE_SQER_Pos 0 +#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */ +#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos))) +/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */ +#define EMAC_RLE_RLFM_Pos 0 +#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */ +#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos))) +/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */ +#define EMAC_HRB_ADDR_Pos 0 +#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB) */ +#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos))) +/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */ +#define EMAC_HRT_ADDR_Pos 0 +#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT) */ +#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos))) +/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define EMAC_SAxB_ADDR_Pos 0 +#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB) */ +#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos))) +/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define EMAC_SAxT_ADDR_Pos 0 +#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT) */ +#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos))) +/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */ +#define EMAC_TID_TID_Pos 0 +#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */ +#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos))) +/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */ +#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */ +#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */ +/* -------- EMAC_WOL : (EMAC Offset: 0xC4) Wake on LAN Register -------- */ +#define EMAC_WOL_IP_Pos 0 +#define EMAC_WOL_IP_Msk (0xffffu << EMAC_WOL_IP_Pos) /**< \brief (EMAC_WOL) ARP request IP address */ +#define EMAC_WOL_IP(value) ((EMAC_WOL_IP_Msk & ((value) << EMAC_WOL_IP_Pos))) +#define EMAC_WOL_MAG (0x1u << 16) /**< \brief (EMAC_WOL) Magic packet event enable */ +#define EMAC_WOL_ARP (0x1u << 17) /**< \brief (EMAC_WOL) ARP request IP address */ +#define EMAC_WOL_SA1 (0x1u << 18) /**< \brief (EMAC_WOL) Specific address register 1 event enable */ +#define EMAC_WOL_MTI (0x1u << 19) /**< \brief (EMAC_WOL) Multicast hash event enable */ + +/*@}*/ + + +#endif /* _SAMA5_EMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_fuse.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_fuse.h new file mode 100644 index 000000000..40e06c1ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_fuse.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_FUSE_COMPONENT_ +#define _SAMA5_FUSE_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Fuse Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_FUSE Fuse Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Fuse hardware registers */ +typedef struct { + WoReg FUSE_CR; /**< \brief (Fuse Offset: 0x00) Fuse Control Register */ + WoReg FUSE_MR; /**< \brief (Fuse Offset: 0x04) Fuse Mode Register */ + RwReg FUSE_IR; /**< \brief (Fuse Offset: 0x08) Fuse Index Register */ + RwReg FUSE_DR; /**< \brief (Fuse Offset: 0x0C) Fuse Data Register */ + RoReg FUSE_SR[8]; /**< \brief (Fuse Offset: 0x10) Fuse Status Register */ +} Fuse; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- FUSE_CR : (FUSE Offset: 0x00) Fuse Control Register -------- */ +#define FUSE_CR_WRQ (0x1u << 0) /**< \brief (FUSE_CR) Write Request */ +#define FUSE_CR_RRQ (0x1u << 1) /**< \brief (FUSE_CR) Read Request */ +#define FUSE_CR_KEY_Pos 8 +#define FUSE_CR_KEY_Msk (0xffu << FUSE_CR_KEY_Pos) /**< \brief (FUSE_CR) Key code */ +#define FUSE_CR_KEY_VALID (0xFBu << 8) /**< \brief (FUSE_CR) valid key. */ +/* -------- FUSE_MR : (FUSE Offset: 0x04) Fuse Mode Register -------- */ +#define FUSE_MR_MSK (0x1u << 0) /**< \brief (FUSE_MR) Mask Fuse Status Registers */ +/* -------- FUSE_IR : (FUSE Offset: 0x08) Fuse Index Register -------- */ +#define FUSE_IR_WS (0x1u << 0) /**< \brief (FUSE_IR) Write Status */ +#define FUSE_IR_RS (0x1u << 1) /**< \brief (FUSE_IR) Read Status */ +#define FUSE_IR_WSEL_Pos 8 +#define FUSE_IR_WSEL_Msk (0xfu << FUSE_IR_WSEL_Pos) /**< \brief (FUSE_IR) Word Selection */ +#define FUSE_IR_WSEL(value) ((FUSE_IR_WSEL_Msk & ((value) << FUSE_IR_WSEL_Pos))) +/* -------- FUSE_DR : (FUSE Offset: 0x0C) Fuse Data Register -------- */ +#define FUSE_DR_DATA_Pos 0 +#define FUSE_DR_DATA_Msk (0xffffffffu << FUSE_DR_DATA_Pos) /**< \brief (FUSE_DR) Data to Program */ +#define FUSE_DR_DATA(value) ((FUSE_DR_DATA_Msk & ((value) << FUSE_DR_DATA_Pos))) +/* -------- FUSE_SR[8] : (FUSE Offset: 0x10) Fuse Status Register -------- */ +#define FUSE_SR_FUSE_Pos 0 +#define FUSE_SR_FUSE_Msk (0xffffffffu << FUSE_SR_FUSE_Pos) /**< \brief (FUSE_SR[8]) Fuse Status */ + +/*@}*/ + + +#endif /* _SAMA5_FUSE_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_gmac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_gmac.h new file mode 100644 index 000000000..89a6a6837 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_gmac.h @@ -0,0 +1,734 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_GMAC_COMPONENT_ +#define _SAMA5_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAMA5_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + RwReg GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom [31:0] Register */ + RwReg GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top [47:32] Register */ +} GmacSa; +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +typedef struct { + RwReg GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + RwReg GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + RoReg GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + RwReg GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + RwReg GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + RwReg GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + RwReg GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address */ + RwReg GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address */ + RwReg GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + RoReg GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + WoReg GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + WoReg GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + RoReg GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + RwReg GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + RoReg GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + RwReg GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + RwReg GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + RwReg GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + RoReg Reserved1[14]; + RwReg GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom [31:0] */ + RwReg GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top [63:32] */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + RwReg GMAC_TIDM[4]; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + RwReg GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + RwReg GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + RwReg GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + RwReg GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + RwReg GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register */ + RwReg GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register */ + RoReg Reserved2[12]; + RoReg GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */ + RoReg GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */ + RoReg GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + RoReg GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + RoReg GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + RoReg GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + RoReg GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + RoReg GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + RoReg GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + RoReg GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Under Runs Register */ + RoReg GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + RoReg GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + RoReg GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + RoReg GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + RoReg GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + RoReg GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register */ + RoReg GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received [31:0] Received */ + RoReg GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received [47:32] Received */ + RoReg GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + RoReg GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + RoReg GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + RoReg GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + RoReg GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + RoReg GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + RoReg GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + RoReg GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511Byte Frames Received Register */ + RoReg GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + RoReg GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + RoReg GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + RoReg GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + RoReg GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + RoReg GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + RoReg GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + RoReg GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + RoReg GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + RoReg GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + RoReg GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + RoReg GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + RoReg GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + RoReg GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + RoReg GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + RoReg Reserved3[5]; + RwReg GMAC_TSSS; /**< \brief (Gmac Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register */ + RwReg GMAC_TSSN; /**< \brief (Gmac Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register */ + RwReg GMAC_TS; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Register */ + RwReg GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + WoReg GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + RwReg GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + RoReg GMAC_EFTS; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds */ + RoReg GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds */ + RoReg GMAC_EFRS; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds */ + RoReg GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds */ + RoReg GMAC_PEFTS; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds */ + RoReg GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds */ + RoReg GMAC_PEFRS; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds */ + RoReg GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds */ + RoReg Reserved4[128]; + RoReg GMAC_ISRPQ[7]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue */ + RoReg Reserved5[9]; + RwReg GMAC_TBQBAPQ[7]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue */ + RoReg Reserved6[9]; + RwReg GMAC_RBQBAPQ[7]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Priority Queue */ + RoReg Reserved7[1]; + RwReg GMAC_RBSRPQ[7]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue */ + RoReg Reserved8[17]; + RwReg GMAC_ST1RPQ[16]; /**< \brief (Gmac Offset: 0x500) Screening Type1 Register Priority Queue */ + RwReg GMAC_ST2RPQ[16]; /**< \brief (Gmac Offset: 0x540) Screening Type2 Register Priority Queue */ + RoReg Reserved9[32]; + WoReg GMAC_IERPQ[7]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue */ + RoReg Reserved10[1]; + WoReg GMAC_IDRPQ[7]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue */ + RoReg Reserved11[1]; + RwReg GMAC_IMRPQ[7]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LB (0x1u << 0) /**< \brief (GMAC_NCR) Loop Back */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_RDS (0x1u << 14) /**< \brief (GMAC_NCR) Read Snapshot */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_GBE (0x1u << 10) /**< \brief (GMAC_NCFGR) Gigabit Mode Enable */ +#define GMAC_NCFGR_PIS (0x1u << 11) /**< \brief (GMAC_NCFGR) Physical Interface Select */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_CLK_MCK_128 (0x6u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 128 (MCK up to 320 MHz) */ +#define GMAC_NCFGR_CLK_MCK_224 (0x7u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 224 (MCK up to 540 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW_DBW32 (0x0u << 21) /**< \brief (GMAC_NCFGR) 32-bit data bus width */ +#define GMAC_NCFGR_DBW_DBW64 (0x1u << 21) /**< \brief (GMAC_NCFGR) 64-bit data bus width */ +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG rx_er */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RGMII (0x1u << 0) /**< \brief (GMAC_UR) RGMII Mode */ +#define GMAC_UR_HDFC (0x1u << 6) /**< \brief (GMAC_UR) Half Duplex Flow Control */ +#define GMAC_UR_BPDG (0x1u << 7) /**< \brief (GMAC_UR) BPDG Bypass Deglitchers */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 1 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 8 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption due to AHB error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_UND (0x1u << 6) /**< \brief (GMAC_TSR) Transmit Under Run */ +#define GMAC_TSR_LCO (0x1u << 7) /**< \brief (GMAC_TSR) Late Collision Occurred */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive buffer queue base address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Under Run */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption due to AHB error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_EXINT (0x1u << 15) /**< \brief (GMAC_ISR) External Interrupt */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Under Run */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption due to AHB error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Under Run */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption due to AHB error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IDR) Wake On LAN */ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Under Run */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption due to AHB error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) tx_pbuf_addr-1:0 */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) rx_pbuf_addr-1:0 */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom [31:0] -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top [63:32] -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB1 : (GMAC Offset: 0x088) Specific Address 1 Bottom [31:0] Register -------- */ +#define GMAC_SAB1_ADDR_Pos 0 +#define GMAC_SAB1_ADDR_Msk (0xffffffffu << GMAC_SAB1_ADDR_Pos) /**< \brief (GMAC_SAB1) Specific Address 1 */ +#define GMAC_SAB1_ADDR(value) ((GMAC_SAB1_ADDR_Msk & ((value) << GMAC_SAB1_ADDR_Pos))) +/* -------- GMAC_SAT1 : (GMAC Offset: 0x08C) Specific Address 1 Top [47:32] Register -------- */ +#define GMAC_SAT1_ADDR_Pos 0 +#define GMAC_SAT1_ADDR_Msk (0xffffu << GMAC_SAT1_ADDR_Pos) /**< \brief (GMAC_SAT1) Specific Address 1 */ +#define GMAC_SAT1_ADDR(value) ((GMAC_SAT1_ADDR_Msk & ((value) << GMAC_SAT1_ADDR_Pos))) +/* -------- GMAC_SAB2 : (GMAC Offset: 0x090) Specific Address 2 Bottom [31:0] Register -------- */ +#define GMAC_SAB2_ADDR_Pos 0 +#define GMAC_SAB2_ADDR_Msk (0xffffffffu << GMAC_SAB2_ADDR_Pos) /**< \brief (GMAC_SAB2) Specific Address 2 */ +#define GMAC_SAB2_ADDR(value) ((GMAC_SAB2_ADDR_Msk & ((value) << GMAC_SAB2_ADDR_Pos))) +/* -------- GMAC_SAT2 : (GMAC Offset: 0x094) Specific Address 2 Top [47:32] Register -------- */ +#define GMAC_SAT2_ADDR_Pos 0 +#define GMAC_SAT2_ADDR_Msk (0xffffu << GMAC_SAT2_ADDR_Pos) /**< \brief (GMAC_SAT2) Specific Address 2 */ +#define GMAC_SAT2_ADDR(value) ((GMAC_SAT2_ADDR_Msk & ((value) << GMAC_SAT2_ADDR_Pos))) +/* -------- GMAC_SAB3 : (GMAC Offset: 0x098) Specific Address 3 Bottom [31:0] Register -------- */ +#define GMAC_SAB3_ADDR_Pos 0 +#define GMAC_SAB3_ADDR_Msk (0xffffffffu << GMAC_SAB3_ADDR_Pos) /**< \brief (GMAC_SAB3) Specific Address 3 */ +#define GMAC_SAB3_ADDR(value) ((GMAC_SAB3_ADDR_Msk & ((value) << GMAC_SAB3_ADDR_Pos))) +/* -------- GMAC_SAT3 : (GMAC Offset: 0x09C) Specific Address 3 Top [47:32] Register -------- */ +#define GMAC_SAT3_ADDR_Pos 0 +#define GMAC_SAT3_ADDR_Msk (0xffffu << GMAC_SAT3_ADDR_Pos) /**< \brief (GMAC_SAT3) Specific Address 3 */ +#define GMAC_SAT3_ADDR(value) ((GMAC_SAT3_ADDR_Msk & ((value) << GMAC_SAT3_ADDR_Pos))) +/* -------- GMAC_SAB4 : (GMAC Offset: 0x0A0) Specific Address 4 Bottom [31:0] Register -------- */ +#define GMAC_SAB4_ADDR_Pos 0 +#define GMAC_SAB4_ADDR_Msk (0xffffffffu << GMAC_SAB4_ADDR_Pos) /**< \brief (GMAC_SAB4) Specific Address 4 */ +#define GMAC_SAB4_ADDR(value) ((GMAC_SAB4_ADDR_Msk & ((value) << GMAC_SAB4_ADDR_Pos))) +/* -------- GMAC_SAT4 : (GMAC Offset: 0x0A4) Specific Address 4 Top [47:32] Register -------- */ +#define GMAC_SAT4_ADDR_Pos 0 +#define GMAC_SAT4_ADDR_Msk (0xffffu << GMAC_SAT4_ADDR_Pos) /**< \brief (GMAC_SAT4) Specific Address 4 */ +#define GMAC_SAT4_ADDR(value) ((GMAC_SAT4_ADDR_Msk & ((value) << GMAC_SAT4_ADDR_Pos))) +/* -------- GMAC_TIDM[4] : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM_TID_Pos 0 +#define GMAC_TIDM_TID_Msk (0xffffu << GMAC_TIDM_TID_Pos) /**< \brief (GMAC_TIDM[4]) Type ID Match 1 */ +#define GMAC_TIDM_TID(value) ((GMAC_TIDM_TID_Msk & ((value) << GMAC_TIDM_TID_Pos))) +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom [31:0] Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top [47:32] Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted [31:0] Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted [47:32] Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Under Runs Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Under Runs */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received [31:0] Received -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received [47:32] Received -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TSSS : (GMAC Offset: 0x1C8) 1588 Timer Sync Strobe Seconds Register -------- */ +#define GMAC_TSSS_VTS_Pos 0 +#define GMAC_TSSS_VTS_Msk (0xffffffffu << GMAC_TSSS_VTS_Pos) /**< \brief (GMAC_TSSS) Value of Timer Seconds Register Capture */ +#define GMAC_TSSS_VTS(value) ((GMAC_TSSS_VTS_Msk & ((value) << GMAC_TSSS_VTS_Pos))) +/* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) 1588 Timer Sync Strobe Nanoseconds Register -------- */ +#define GMAC_TSSN_VTN_Pos 0 +#define GMAC_TSSN_VTN_Msk (0x3fffffffu << GMAC_TSSN_VTN_Pos) /**< \brief (GMAC_TSSN) Value Timer Nanoseconds Register Capture */ +#define GMAC_TSSN_VTN(value) ((GMAC_TSSN_VTN_Msk & ((value) << GMAC_TSSN_VTN_Pos))) +/* -------- GMAC_TS : (GMAC Offset: 0x1D0) 1588 Timer Seconds Register -------- */ +#define GMAC_TS_TCS_Pos 0 +#define GMAC_TS_TCS_Msk (0xffffffffu << GMAC_TS_TCS_Pos) /**< \brief (GMAC_TS) Timer Count in Seconds */ +#define GMAC_TS_TCS(value) ((GMAC_TS_TCS_Msk & ((value) << GMAC_TS_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTS : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds -------- */ +#define GMAC_EFTS_RUD_Pos 0 +#define GMAC_EFTS_RUD_Msk (0xffffffffu << GMAC_EFTS_RUD_Pos) /**< \brief (GMAC_EFTS) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRS : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds -------- */ +#define GMAC_EFRS_RUD_Pos 0 +#define GMAC_EFRS_RUD_Msk (0xffffffffu << GMAC_EFRS_RUD_Pos) /**< \brief (GMAC_EFRS) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTS : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds -------- */ +#define GMAC_PEFTS_RUD_Pos 0 +#define GMAC_PEFTS_RUD_Msk (0xffffffffu << GMAC_PEFTS_RUD_Pos) /**< \brief (GMAC_PEFTS) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRS : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds -------- */ +#define GMAC_PEFRS_RUD_Pos 0 +#define GMAC_PEFRS_RUD_Msk (0xffffffffu << GMAC_PEFRS_RUD_Pos) /**< \brief (GMAC_PEFRS) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[7] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[7]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[7]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[7]) Transmit Frame Corruption due to AHB error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[7]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[7]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[7]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[7] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Priority Queue -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[7]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[7] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Priority Queue -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[7]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[7] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[7]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_ST1RPQ[16] : (GMAC Offset: 0x500) Screening Type1 Register Priority Queue -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0xfu << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[16]) Que Number (0->7) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[16]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[16]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[16] : (GMAC Offset: 0x540) Screening Type2 Register Priority Queue -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0xfu << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[16]) Que Number (0->7) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0xfu << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[16]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[16]) VLAN Enable */ +/* -------- GMAC_IERPQ[7] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[7]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[7]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[7]) Transmit Frame Corruption due to AHB error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[7]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[7]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[7]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[7] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[7]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[7]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[7]) Transmit Frame Corruption due to AHB error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[7]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[7]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[7]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[7] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[7]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[7]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[7]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[7]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[7]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[7]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[7]) HRESP Not OK */ + +/*@}*/ + + +#endif /* _SAMA5_GMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_gpbr.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_gpbr.h new file mode 100644 index 000000000..4068f5790 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_GPBR_COMPONENT_ +#define _SAMA5_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ +/* ============================================================================= */ +/** \addtogroup SAMA5_GPBR General Purpose Backup Register */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + RwReg SYS_GPBR[4]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[4] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[4]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_GPBR_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_hsmci.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_hsmci.h new file mode 100644 index 000000000..60b79ef04 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_hsmci.h @@ -0,0 +1,339 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI_COMPONENT_ +#define _SAMA5_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMA5_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + RoReg Reserved1[2]; + RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + RoReg Reserved2[35]; + RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + RoReg Reserved3[69]; + RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 1: Value 0 corresponds to an infinite block transfer. */ +#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */ +#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_OFFSET_Pos 0 +#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */ +#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos))) +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x2u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x3u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_CHKSIZE_32 (0x4u << 4) /**< \brief (HSMCI_DMA) 32 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_Pos 8 +#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS_Pos 0 +#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ +#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ +#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ +#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ +#define HSMCI_WPSR_WP_VSRC_Pos 8 +#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_HSMCI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_isi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_isi.h new file mode 100644 index 000000000..5acfe69a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_isi.h @@ -0,0 +1,271 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_ISI_COMPONENT_ +#define _SAMA5_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMA5_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + RwReg ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + RwReg ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + RwReg ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + RwReg ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + RwReg ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI CSC YCrCb To RGB Set 0 Register */ + RwReg ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI CSC YCrCb To RGB Set 1 Register */ + RwReg ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI CSC RGB To YCrCb Set 0 Register */ + RwReg ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI CSC RGB To YCrCb Set 1 Register */ + RwReg ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI CSC RGB To YCrCb Set 2 Register */ + WoReg ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + RoReg ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + WoReg ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + WoReg ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + RoReg ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + WoReg ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + WoReg ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + RoReg ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + RwReg ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + RwReg ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + RwReg ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + RwReg ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + RwReg ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + RwReg ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + RoReg Reserved1[34]; + RwReg ISI_WPCR; /**< \brief (Isi Offset: 0xE4) Write Protection Control Register */ + RoReg ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047]: */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode: */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) Defines the YCC Image Data */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) Defines RGB Pattern when RGB_MODE is set to 1 */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI CSC YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI CSC YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI CSC RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI CSC RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI CSC RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request (this bit is a status bit) */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated. */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated. */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress (this is a status bit) */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Interrupt */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Interrupt */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) FIFO Preview Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) FIFO Codec Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address. (This address is word aligned.) */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Field */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Field */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) (This field is only updated in the memory.) */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address (This address is word aligned.) */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address (This address is word aligned.) */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Field */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Field */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done flag control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) (This field is only updated in the memory.) */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address (This address is word aligned.) */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPCR : (ISI Offset: 0xE4) Write Protection Control Register -------- */ +#define ISI_WPCR_WP_EN (0x1u << 0) /**< \brief (ISI_WPCR) Write Protection Enable */ +#define ISI_WPCR_WP_KEY_Pos 8 +#define ISI_WPCR_WP_KEY_Msk (0xffffffu << ISI_WPCR_WP_KEY_Pos) /**< \brief (ISI_WPCR) Write Protection KEY Password */ +#define ISI_WPCR_WP_KEY(value) ((ISI_WPCR_WP_KEY_Msk & ((value) << ISI_WPCR_WP_KEY_Pos))) +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WP_VS_Pos 0 +#define ISI_WPSR_WP_VS_Msk (0xfu << ISI_WPSR_WP_VS_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WP_VSRC_Pos 8 +#define ISI_WPSR_WP_VSRC_Msk (0xffffu << ISI_WPSR_WP_VSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_ISI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_lcdc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_lcdc.h new file mode 100644 index 000000000..1e0c84ea0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_lcdc.h @@ -0,0 +1,1648 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_LCDC_COMPONENT_ +#define _SAMA5_LCDC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR LCD Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_LCDC LCD Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Lcdc hardware registers */ +typedef struct { + RwReg LCDC_LCDCFG0; /**< \brief (Lcdc Offset: 0x00000000) LCD Controller Configuration Register 0 */ + RwReg LCDC_LCDCFG1; /**< \brief (Lcdc Offset: 0x00000004) LCD Controller Configuration Register 1 */ + RwReg LCDC_LCDCFG2; /**< \brief (Lcdc Offset: 0x00000008) LCD Controller Configuration Register 2 */ + RwReg LCDC_LCDCFG3; /**< \brief (Lcdc Offset: 0x0000000C) LCD Controller Configuration Register 3 */ + RwReg LCDC_LCDCFG4; /**< \brief (Lcdc Offset: 0x00000010) LCD Controller Configuration Register 4 */ + RwReg LCDC_LCDCFG5; /**< \brief (Lcdc Offset: 0x00000014) LCD Controller Configuration Register 5 */ + RwReg LCDC_LCDCFG6; /**< \brief (Lcdc Offset: 0x00000018) LCD Controller Configuration Register 6 */ + RoReg Reserved1[1]; + WoReg LCDC_LCDEN; /**< \brief (Lcdc Offset: 0x00000020) LCD Controller Enable Register */ + WoReg LCDC_LCDDIS; /**< \brief (Lcdc Offset: 0x00000024) LCD Controller Disable Register */ + RoReg LCDC_LCDSR; /**< \brief (Lcdc Offset: 0x00000028) LCD Controller Status Register */ + WoReg LCDC_LCDIER; /**< \brief (Lcdc Offset: 0x0000002C) LCD Controller Interrupt Enable Register */ + WoReg LCDC_LCDIDR; /**< \brief (Lcdc Offset: 0x00000030) LCD Controller Interrupt Disable Register */ + RoReg LCDC_LCDIMR; /**< \brief (Lcdc Offset: 0x00000034) LCD Controller Interrupt Mask Register */ + RoReg LCDC_LCDISR; /**< \brief (Lcdc Offset: 0x00000038) LCD Controller Interrupt Status Register */ + RoReg Reserved2[1]; + WoReg LCDC_BASECHER; /**< \brief (Lcdc Offset: 0x00000040) Base Layer Channel Enable Register */ + WoReg LCDC_BASECHDR; /**< \brief (Lcdc Offset: 0x00000044) Base Layer Channel Disable Register */ + RoReg LCDC_BASECHSR; /**< \brief (Lcdc Offset: 0x00000048) Base Layer Channel Status Register */ + WoReg LCDC_BASEIER; /**< \brief (Lcdc Offset: 0x0000004C) Base Layer Interrupt Enable Register */ + WoReg LCDC_BASEIDR; /**< \brief (Lcdc Offset: 0x00000050) Base Layer Interrupt Disabled Register */ + RoReg LCDC_BASEIMR; /**< \brief (Lcdc Offset: 0x00000054) Base Layer Interrupt Mask Register */ + RoReg LCDC_BASEISR; /**< \brief (Lcdc Offset: 0x00000058) Base Layer Interrupt status Register */ + RwReg LCDC_BASEHEAD; /**< \brief (Lcdc Offset: 0x0000005C) Base DMA Head Register */ + RwReg LCDC_BASEADDR; /**< \brief (Lcdc Offset: 0x00000060) Base DMA Address Register */ + RwReg LCDC_BASECTRL; /**< \brief (Lcdc Offset: 0x00000064) Base DMA Control Register */ + RwReg LCDC_BASENEXT; /**< \brief (Lcdc Offset: 0x00000068) Base DMA Next Register */ + RwReg LCDC_BASECFG0; /**< \brief (Lcdc Offset: 0x0000006C) Base Configuration register 0 */ + RwReg LCDC_BASECFG1; /**< \brief (Lcdc Offset: 0x00000070) Base Configuration register 1 */ + RwReg LCDC_BASECFG2; /**< \brief (Lcdc Offset: 0x00000074) Base Configuration register 2 */ + RwReg LCDC_BASECFG3; /**< \brief (Lcdc Offset: 0x00000078) Base Configuration register 3 */ + RwReg LCDC_BASECFG4; /**< \brief (Lcdc Offset: 0x0000007C) Base Configuration register 4 */ + RwReg LCDC_BASECFG5; /**< \brief (Lcdc Offset: 0x00000080) Base Configuration register 5 */ + RwReg LCDC_BASECFG6; /**< \brief (Lcdc Offset: 0x00000084) Base Configuration register 6 */ + RoReg Reserved3[46]; + WoReg LCDC_OVR1CHER; /**< \brief (Lcdc Offset: 0x00000140) Overlay 1 Channel Enable Register */ + WoReg LCDC_OVR1CHDR; /**< \brief (Lcdc Offset: 0x00000144) Overlay 1 Channel Disable Register */ + RoReg LCDC_OVR1CHSR; /**< \brief (Lcdc Offset: 0x00000148) Overlay 1 Channel Status Register */ + WoReg LCDC_OVR1IER; /**< \brief (Lcdc Offset: 0x0000014C) Overlay 1 Interrupt Enable Register */ + WoReg LCDC_OVR1IDR; /**< \brief (Lcdc Offset: 0x00000150) Overlay 1 Interrupt Disable Register */ + RoReg LCDC_OVR1IMR; /**< \brief (Lcdc Offset: 0x00000154) Overlay 1 Interrupt Mask Register */ + RoReg LCDC_OVR1ISR; /**< \brief (Lcdc Offset: 0x00000158) Overlay 1 Interrupt Status Register */ + RwReg LCDC_OVR1HEAD; /**< \brief (Lcdc Offset: 0x0000015C) Overlay 1 DMA Head Register */ + RwReg LCDC_OVR1ADDR; /**< \brief (Lcdc Offset: 0x00000160) Overlay 1 DMA Address Register */ + RwReg LCDC_OVR1CTRL; /**< \brief (Lcdc Offset: 0x00000164) Overlay1 DMA Control Register */ + RwReg LCDC_OVR1NEXT; /**< \brief (Lcdc Offset: 0x00000168) Overlay1 DMA Next Register */ + RwReg LCDC_OVR1CFG0; /**< \brief (Lcdc Offset: 0x0000016C) Overlay 1 Configuration 0 Register */ + RwReg LCDC_OVR1CFG1; /**< \brief (Lcdc Offset: 0x00000170) Overlay 1 Configuration 1 Register */ + RwReg LCDC_OVR1CFG2; /**< \brief (Lcdc Offset: 0x00000174) Overlay 1 Configuration 2 Register */ + RwReg LCDC_OVR1CFG3; /**< \brief (Lcdc Offset: 0x00000178) Overlay 1 Configuration 3 Register */ + RwReg LCDC_OVR1CFG4; /**< \brief (Lcdc Offset: 0x0000017C) Overlay 1 Configuration 4 Register */ + RwReg LCDC_OVR1CFG5; /**< \brief (Lcdc Offset: 0x00000180) Overlay 1 Configuration 5 Register */ + RwReg LCDC_OVR1CFG6; /**< \brief (Lcdc Offset: 0x00000184) Overlay 1 Configuration 6 Register */ + RwReg LCDC_OVR1CFG7; /**< \brief (Lcdc Offset: 0x00000188) Overlay 1 Configuration 7 Register */ + RwReg LCDC_OVR1CFG8; /**< \brief (Lcdc Offset: 0x0000018C) Overlay 1 Configuration 8Register */ + RwReg LCDC_OVR1CFG9; /**< \brief (Lcdc Offset: 0x00000190) Overlay 1 Configuration 9 Register */ + RoReg Reserved4[43]; + WoReg LCDC_OVR2CHER; /**< \brief (Lcdc Offset: 0x00000240) Overlay 2 Channel Enable Register */ + WoReg LCDC_OVR2CHDR; /**< \brief (Lcdc Offset: 0x00000244) Overlay 2 Channel Disable Register */ + RoReg LCDC_OVR2CHSR; /**< \brief (Lcdc Offset: 0x00000248) Overlay 2 Channel Status Register */ + WoReg LCDC_OVR2IER; /**< \brief (Lcdc Offset: 0x0000024C) Overlay 2 Interrupt Enable Register */ + WoReg LCDC_OVR2IDR; /**< \brief (Lcdc Offset: 0x00000250) Overlay 2 Interrupt Disable Register */ + RoReg LCDC_OVR2IMR; /**< \brief (Lcdc Offset: 0x00000254) Overlay 2 Interrupt Mask Register */ + RoReg LCDC_OVR2ISR; /**< \brief (Lcdc Offset: 0x00000258) Overlay 2 Interrupt status Register */ + RwReg LCDC_OVR2HEAD; /**< \brief (Lcdc Offset: 0x0000025C) Overlay 2 DMA Head Register */ + RwReg LCDC_OVR2ADDR; /**< \brief (Lcdc Offset: 0x00000260) Overlay 2 DMA Address Register */ + RwReg LCDC_OVR2CTRL; /**< \brief (Lcdc Offset: 0x00000264) Overlay 2 DMA Control Register */ + RwReg LCDC_OVR2NEXT; /**< \brief (Lcdc Offset: 0x00000268) Overlay 2 DMA Next Register */ + RwReg LCDC_OVR2CFG0; /**< \brief (Lcdc Offset: 0x0000026C) Overlay 2 Configuration 0 Register */ + RwReg LCDC_OVR2CFG1; /**< \brief (Lcdc Offset: 0x00000270) Overlay 2 Configuration 1 Register */ + RwReg LCDC_OVR2CFG2; /**< \brief (Lcdc Offset: 0x00000274) Overlay 2 Configuration 2 Register */ + RwReg LCDC_OVR2CFG3; /**< \brief (Lcdc Offset: 0x00000278) Overlay 2 Configuration 3 Register */ + RwReg LCDC_OVR2CFG4; /**< \brief (Lcdc Offset: 0x0000027C) Overlay 2 Configuration 4 Register */ + RwReg LCDC_OVR2CFG5; /**< \brief (Lcdc Offset: 0x00000280) Overlay 2 Configuration 5 Register */ + RwReg LCDC_OVR2CFG6; /**< \brief (Lcdc Offset: 0x00000284) Overlay 2 Configuration 6 Register */ + RwReg LCDC_OVR2CFG7; /**< \brief (Lcdc Offset: 0x00000288) Overlay 2 Configuration 7 Register */ + RwReg LCDC_OVR2CFG8; /**< \brief (Lcdc Offset: 0x0000028C) Overlay 2 Configuration 8 Register */ + RwReg LCDC_OVR2CFG9; /**< \brief (Lcdc Offset: 0x00000290) Overlay 2 Configuration 9 Register */ + RoReg Reserved5[43]; + WoReg LCDC_HEOCHER; /**< \brief (Lcdc Offset: 0x00000340) High-End Overlay Channel Enable Register */ + WoReg LCDC_HEOCHDR; /**< \brief (Lcdc Offset: 0x00000344) High-End Overlay Channel Disable Register */ + RoReg LCDC_HEOCHSR; /**< \brief (Lcdc Offset: 0x00000348) High-End Overlay Channel Status Register */ + WoReg LCDC_HEOIER; /**< \brief (Lcdc Offset: 0x0000034C) High-End Overlay Interrupt Enable Register */ + WoReg LCDC_HEOIDR; /**< \brief (Lcdc Offset: 0x00000350) High-End Overlay Interrupt Disable Register */ + RoReg LCDC_HEOIMR; /**< \brief (Lcdc Offset: 0x00000354) High-End Overlay Interrupt Mask Register */ + RoReg LCDC_HEOISR; /**< \brief (Lcdc Offset: 0x00000358) High-End Overlay Interrupt Status Register */ + RwReg LCDC_HEOHEAD; /**< \brief (Lcdc Offset: 0x0000035C) High-End Overlay DMA Head Register */ + RwReg LCDC_HEOADDR; /**< \brief (Lcdc Offset: 0x00000360) High-End Overlay DMA Address Register */ + RwReg LCDC_HEOCTRL; /**< \brief (Lcdc Offset: 0x00000364) High-End Overlay DMA Control Register */ + RwReg LCDC_HEONEXT; /**< \brief (Lcdc Offset: 0x00000368) High-End Overlay DMA Next Register */ + RwReg LCDC_HEOUHEAD; /**< \brief (Lcdc Offset: 0x0000036C) High-End Overlay U DMA Head Register */ + RwReg LCDC_HEOUADDR; /**< \brief (Lcdc Offset: 0x00000370) High-End Overlay U DMA Address Register */ + RwReg LCDC_HEOUCTRL; /**< \brief (Lcdc Offset: 0x00000374) High-End Overlay U DMA control Register */ + RwReg LCDC_HEOUNEXT; /**< \brief (Lcdc Offset: 0x00000378) High-End Overlay U DMA Next Register */ + RwReg LCDC_HEOVHEAD; /**< \brief (Lcdc Offset: 0x0000037C) High-End Overlay V DMA Head Register */ + RwReg LCDC_HEOVADDR; /**< \brief (Lcdc Offset: 0x00000380) High-End Overlay V DMA Address Register */ + RwReg LCDC_HEOVCTRL; /**< \brief (Lcdc Offset: 0x00000384) High-End Overlay V DMA control Register */ + RwReg LCDC_HEOVNEXT; /**< \brief (Lcdc Offset: 0x00000388) High-End Overlay VDMA Next Register */ + RwReg LCDC_HEOCFG0; /**< \brief (Lcdc Offset: 0x0000038C) High-End Overlay Configuration Register 0 */ + RwReg LCDC_HEOCFG1; /**< \brief (Lcdc Offset: 0x00000390) High-End Overlay Configuration Register 1 */ + RwReg LCDC_HEOCFG2; /**< \brief (Lcdc Offset: 0x00000394) High-End Overlay Configuration Register 2 */ + RwReg LCDC_HEOCFG3; /**< \brief (Lcdc Offset: 0x00000398) High-End Overlay Configuration Register 3 */ + RwReg LCDC_HEOCFG4; /**< \brief (Lcdc Offset: 0x0000039C) High-End Overlay Configuration Register 4 */ + RwReg LCDC_HEOCFG5; /**< \brief (Lcdc Offset: 0x000003A0) High-End Overlay Configuration Register 5 */ + RwReg LCDC_HEOCFG6; /**< \brief (Lcdc Offset: 0x000003A4) High-End Overlay Configuration Register 6 */ + RwReg LCDC_HEOCFG7; /**< \brief (Lcdc Offset: 0x000003A8) High-End Overlay Configuration Register 7 */ + RwReg LCDC_HEOCFG8; /**< \brief (Lcdc Offset: 0x000003AC) High-End Overlay Configuration Register 8 */ + RwReg LCDC_HEOCFG9; /**< \brief (Lcdc Offset: 0x000003B0) High-End Overlay Configuration Register 9 */ + RwReg LCDC_HEOCFG10; /**< \brief (Lcdc Offset: 0x000003B4) High-End Overlay Configuration Register 10 */ + RwReg LCDC_HEOCFG11; /**< \brief (Lcdc Offset: 0x000003B8) High-End Overlay Configuration Register 11 */ + RwReg LCDC_HEOCFG12; /**< \brief (Lcdc Offset: 0x000003BC) High-End Overlay Configuration Register 12 */ + RwReg LCDC_HEOCFG13; /**< \brief (Lcdc Offset: 0x000003C0) High-End Overlay Configuration Register 13 */ + RwReg LCDC_HEOCFG14; /**< \brief (Lcdc Offset: 0x000003C4) High-End Overlay Configuration Register 14 */ + RwReg LCDC_HEOCFG15; /**< \brief (Lcdc Offset: 0x000003C8) High-End Overlay Configuration Register 15 */ + RwReg LCDC_HEOCFG16; /**< \brief (Lcdc Offset: 0x000003CC) High-End Overlay Configuration Register 16 */ + RwReg LCDC_HEOCFG17; /**< \brief (Lcdc Offset: 0x000003D0) High-End Overlay Configuration Register 17 */ + RwReg LCDC_HEOCFG18; /**< \brief (Lcdc Offset: 0x000003D4) High-End Overlay Configuration Register 18 */ + RwReg LCDC_HEOCFG19; /**< \brief (Lcdc Offset: 0x000003D8) High-End Overlay Configuration Register 19 */ + RwReg LCDC_HEOCFG20; /**< \brief (Lcdc Offset: 0x000003DC) High-End Overlay Configuration Register 20 */ + RwReg LCDC_HEOCFG21; /**< \brief (Lcdc Offset: 0x000003E0) High-End Overlay Configuration Register 21 */ + RwReg LCDC_HEOCFG22; /**< \brief (Lcdc Offset: 0x000003E4) High-End Overlay Configuration Register 22 */ + RwReg LCDC_HEOCFG23; /**< \brief (Lcdc Offset: 0x000003E8) High-End Overlay Configuration Register 23 */ + RwReg LCDC_HEOCFG24; /**< \brief (Lcdc Offset: 0x000003EC) High-End Overlay Configuration Register 24 */ + RwReg LCDC_HEOCFG25; /**< \brief (Lcdc Offset: 0x000003F0) High-End Overlay Configuration Register 25 */ + RwReg LCDC_HEOCFG26; /**< \brief (Lcdc Offset: 0x000003F4) High-End Overlay Configuration Register 26 */ + RwReg LCDC_HEOCFG27; /**< \brief (Lcdc Offset: 0x000003F8) High-End Overlay Configuration Register 27 */ + RwReg LCDC_HEOCFG28; /**< \brief (Lcdc Offset: 0x000003FC) High-End Overlay Configuration Register 28 */ + RwReg LCDC_HEOCFG29; /**< \brief (Lcdc Offset: 0x00000400) High-End Overlay Configuration Register 29 */ + RwReg LCDC_HEOCFG30; /**< \brief (Lcdc Offset: 0x00000404) High-End Overlay Configuration Register 30 */ + RwReg LCDC_HEOCFG31; /**< \brief (Lcdc Offset: 0x00000408) High-End Overlay Configuration Register 31 */ + RwReg LCDC_HEOCFG32; /**< \brief (Lcdc Offset: 0x0000040C) High-End Overlay Configuration Register 32 */ + RwReg LCDC_HEOCFG33; /**< \brief (Lcdc Offset: 0x00000410) High-End Overlay Configuration Register 33 */ + RwReg LCDC_HEOCFG34; /**< \brief (Lcdc Offset: 0x00000414) High-End Overlay Configuration Register 34 */ + RwReg LCDC_HEOCFG35; /**< \brief (Lcdc Offset: 0x00000418) High-End Overlay Configuration Register 35 */ + RwReg LCDC_HEOCFG36; /**< \brief (Lcdc Offset: 0x0000041C) High-End Overlay Configuration Register 36 */ + RwReg LCDC_HEOCFG37; /**< \brief (Lcdc Offset: 0x00000420) High-End Overlay Configuration Register 37 */ + RwReg LCDC_HEOCFG38; /**< \brief (Lcdc Offset: 0x00000424) High-End Overlay Configuration Register 38 */ + RwReg LCDC_HEOCFG39; /**< \brief (Lcdc Offset: 0x00000428) High-End Overlay Configuration Register 39 */ + RwReg LCDC_HEOCFG40; /**< \brief (Lcdc Offset: 0x0000042C) High-End Overlay Configuration Register 40 */ + RwReg LCDC_HEOCFG41; /**< \brief (Lcdc Offset: 0x00000430) High-End Overlay Configuration Register 41 */ + RoReg Reserved6[3]; + WoReg LCDC_HCRCHER; /**< \brief (Lcdc Offset: 0x00000440) Hardware Cursor Channel Enable Register */ + WoReg LCDC_HCRCHDR; /**< \brief (Lcdc Offset: 0x00000444) Hardware Cursor Channel disable Register */ + RoReg LCDC_HCRCHSR; /**< \brief (Lcdc Offset: 0x00000448) Hardware Cursor Channel Status Register */ + WoReg LCDC_HCRIER; /**< \brief (Lcdc Offset: 0x0000044C) Hardware Cursor Interrupt Enable Register */ + WoReg LCDC_HCRIDR; /**< \brief (Lcdc Offset: 0x00000450) Hardware Cursor Interrupt Disable Register */ + RoReg LCDC_HCRIMR; /**< \brief (Lcdc Offset: 0x00000454) Hardware Cursor Interrupt Mask Register */ + RoReg LCDC_HCRISR; /**< \brief (Lcdc Offset: 0x00000458) Hardware Cursor Interrupt Status Register */ + RwReg LCDC_HCRHEAD; /**< \brief (Lcdc Offset: 0x0000045C) Hardware Cursor DMA Head Register */ + RwReg LCDC_HCRADDR; /**< \brief (Lcdc Offset: 0x00000460) Hardware cursor DMA Address Register */ + RwReg LCDC_HCRCTRL; /**< \brief (Lcdc Offset: 0x00000464) Hardware Cursor DMA Control Register */ + RwReg LCDC_HCRNEXT; /**< \brief (Lcdc Offset: 0x00000468) Hardware Cursor DMA NExt Register */ + RwReg LCDC_HCRCFG0; /**< \brief (Lcdc Offset: 0x0000046C) Hardware Cursor Configuration 0 Register */ + RwReg LCDC_HCRCFG1; /**< \brief (Lcdc Offset: 0x00000470) Hardware Cursor Configuration 1 Register */ + RwReg LCDC_HCRCFG2; /**< \brief (Lcdc Offset: 0x00000474) Hardware Cursor Configuration 2 Register */ + RwReg LCDC_HCRCFG3; /**< \brief (Lcdc Offset: 0x00000478) Hardware Cursor Configuration 3 Register */ + RwReg LCDC_HCRCFG4; /**< \brief (Lcdc Offset: 0x0000047C) Hardware Cursor Configuration 4 Register */ + RoReg Reserved7[1]; + RwReg LCDC_HCRCFG6; /**< \brief (Lcdc Offset: 0x00000484) Hardware Cursor Configuration 6 Register */ + RwReg LCDC_HCRCFG7; /**< \brief (Lcdc Offset: 0x00000488) Hardware Cursor Configuration 7 Register */ + RwReg LCDC_HCRCFG8; /**< \brief (Lcdc Offset: 0x0000048C) Hardware Cursor Configuration 8 Register */ + RwReg LCDC_HCRCFG9; /**< \brief (Lcdc Offset: 0x00000490) Hardware Cursor Configuration 9 Register */ + RoReg Reserved8[43]; + WoReg LCDC_PPCHER; /**< \brief (Lcdc Offset: 0x00000540) Post Processing Channel Enable Register */ + WoReg LCDC_PPCHDR; /**< \brief (Lcdc Offset: 0x00000544) Post Processing Channel Disable Register */ + RoReg LCDC_PPCHSR; /**< \brief (Lcdc Offset: 0x00000548) Post Processing Channel Status Register */ + WoReg LCDC_PPIER; /**< \brief (Lcdc Offset: 0x0000054C) Post Processing Interrupt Enable Register */ + WoReg LCDC_PPIDR; /**< \brief (Lcdc Offset: 0x00000550) Post Processing Interrupt Disable Register */ + RoReg LCDC_PPIMR; /**< \brief (Lcdc Offset: 0x00000554) Post Processing Interrupt Mask Register */ + RoReg LCDC_PPISR; /**< \brief (Lcdc Offset: 0x00000558) Post Processing Interrupt Status Register */ + RwReg LCDC_PPHEAD; /**< \brief (Lcdc Offset: 0x0000055C) Post Processing Head Register */ + RwReg LCDC_PPADDR; /**< \brief (Lcdc Offset: 0x00000560) Post Processing Address Register */ + RwReg LCDC_PPCTRL; /**< \brief (Lcdc Offset: 0x00000564) Post Processing Control Register */ + RwReg LCDC_PPNEXT; /**< \brief (Lcdc Offset: 0x00000568) Post Processing Next Register */ + RwReg LCDC_PPCFG0; /**< \brief (Lcdc Offset: 0x0000056C) Post Processing Configuration Register 0 */ + RwReg LCDC_PPCFG1; /**< \brief (Lcdc Offset: 0x00000570) Post Processing Configuration Register 1 */ + RwReg LCDC_PPCFG2; /**< \brief (Lcdc Offset: 0x00000574) Post Processing Configuration Register 2 */ + RwReg LCDC_PPCFG3; /**< \brief (Lcdc Offset: 0x00000578) Post Processing Configuration Register 3 */ + RwReg LCDC_PPCFG4; /**< \brief (Lcdc Offset: 0x0000057C) Post Processing Configuration Register 4 */ + RwReg LCDC_PPCFG5; /**< \brief (Lcdc Offset: 0x00000580) Post Processing Configuration Register 5 */ + RoReg Reserved9[31]; + RwReg LCDC_BASECLUT[256]; /**< \brief (Lcdc Offset: 0x600) Base CLUT Register */ + RwReg LCDC_OVR1CLUT[256]; /**< \brief (Lcdc Offset: 0xA00) Overlay 1 CLUT Register */ + RwReg LCDC_OVR2CLUT[256]; /**< \brief (Lcdc Offset: 0xE00) Overlay 2 CLUT Register */ + RwReg LCDC_HEOCLUT[256]; /**< \brief (Lcdc Offset: 0x1200) High End Overlay CLUT Register */ + RwReg LCDC_HCRCLUT[256]; /**< \brief (Lcdc Offset: 0x1600) Hardware Cursor CLUT Register */ +} Lcdc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- LCDC_LCDCFG0 : (LCDC Offset: 0x00000000) LCD Controller Configuration Register 0 -------- */ +#define LCDC_LCDCFG0_CLKPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Polarity */ +#define LCDC_LCDCFG0_CLKSEL (0x1u << 2) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Source Selection */ +#define LCDC_LCDCFG0_CLKPWMSEL (0x1u << 3) /**< \brief (LCDC_LCDCFG0) LCD Controller PWM Clock Source Selection */ +#define LCDC_LCDCFG0_CGDISBASE (0x1u << 8) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Base Layer */ +#define LCDC_LCDCFG0_CGDISOVR1 (0x1u << 9) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 1 Layer */ +#define LCDC_LCDCFG0_CGDISOVR2 (0x1u << 10) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Overlay 2 Layer */ +#define LCDC_LCDCFG0_CGDISHEO (0x1u << 11) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the High End Overlay */ +#define LCDC_LCDCFG0_CGDISHCR (0x1u << 12) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Hardware Cursor Layer */ +#define LCDC_LCDCFG0_CGDISPP (0x1u << 13) /**< \brief (LCDC_LCDCFG0) Clock Gating Disable Control for the Post Processing Layer */ +#define LCDC_LCDCFG0_CLKDIV_Pos 16 +#define LCDC_LCDCFG0_CLKDIV_Msk (0xffu << LCDC_LCDCFG0_CLKDIV_Pos) /**< \brief (LCDC_LCDCFG0) LCD Controller Clock Divider */ +#define LCDC_LCDCFG0_CLKDIV(value) ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos))) +/* -------- LCDC_LCDCFG1 : (LCDC Offset: 0x00000004) LCD Controller Configuration Register 1 -------- */ +#define LCDC_LCDCFG1_HSPW_Pos 0 +#define LCDC_LCDCFG1_HSPW_Msk (0x3fu << LCDC_LCDCFG1_HSPW_Pos) /**< \brief (LCDC_LCDCFG1) Horizontal Synchronization Pulse Width */ +#define LCDC_LCDCFG1_HSPW(value) ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos))) +#define LCDC_LCDCFG1_VSPW_Pos 16 +#define LCDC_LCDCFG1_VSPW_Msk (0x3fu << LCDC_LCDCFG1_VSPW_Pos) /**< \brief (LCDC_LCDCFG1) Vertical Synchronization Pulse Width */ +#define LCDC_LCDCFG1_VSPW(value) ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos))) +/* -------- LCDC_LCDCFG2 : (LCDC Offset: 0x00000008) LCD Controller Configuration Register 2 -------- */ +#define LCDC_LCDCFG2_VFPW_Pos 0 +#define LCDC_LCDCFG2_VFPW_Msk (0x3fu << LCDC_LCDCFG2_VFPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Front Porch Width */ +#define LCDC_LCDCFG2_VFPW(value) ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos))) +#define LCDC_LCDCFG2_VBPW_Pos 16 +#define LCDC_LCDCFG2_VBPW_Msk (0x3fu << LCDC_LCDCFG2_VBPW_Pos) /**< \brief (LCDC_LCDCFG2) Vertical Back Porch Width */ +#define LCDC_LCDCFG2_VBPW(value) ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos))) +/* -------- LCDC_LCDCFG3 : (LCDC Offset: 0x0000000C) LCD Controller Configuration Register 3 -------- */ +#define LCDC_LCDCFG3_HFPW_Pos 0 +#define LCDC_LCDCFG3_HFPW_Msk (0x1ffu << LCDC_LCDCFG3_HFPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Front Porch Width */ +#define LCDC_LCDCFG3_HFPW(value) ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos))) +#define LCDC_LCDCFG3_HBPW_Pos 16 +#define LCDC_LCDCFG3_HBPW_Msk (0x1ffu << LCDC_LCDCFG3_HBPW_Pos) /**< \brief (LCDC_LCDCFG3) Horizontal Back Porch Width */ +#define LCDC_LCDCFG3_HBPW(value) ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos))) +/* -------- LCDC_LCDCFG4 : (LCDC Offset: 0x00000010) LCD Controller Configuration Register 4 -------- */ +#define LCDC_LCDCFG4_PPL_Pos 0 +#define LCDC_LCDCFG4_PPL_Msk (0x7ffu << LCDC_LCDCFG4_PPL_Pos) /**< \brief (LCDC_LCDCFG4) Number of Pixels Per Line */ +#define LCDC_LCDCFG4_PPL(value) ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos))) +#define LCDC_LCDCFG4_RPF_Pos 16 +#define LCDC_LCDCFG4_RPF_Msk (0x7ffu << LCDC_LCDCFG4_RPF_Pos) /**< \brief (LCDC_LCDCFG4) Number of Active Row Per Frame */ +#define LCDC_LCDCFG4_RPF(value) ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos))) +/* -------- LCDC_LCDCFG5 : (LCDC Offset: 0x00000014) LCD Controller Configuration Register 5 -------- */ +#define LCDC_LCDCFG5_HSPOL (0x1u << 0) /**< \brief (LCDC_LCDCFG5) Horizontal Synchronization Pulse Polarity */ +#define LCDC_LCDCFG5_VSPOL (0x1u << 1) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Polarity */ +#define LCDC_LCDCFG5_VSPDLYS (0x1u << 2) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse Start */ +#define LCDC_LCDCFG5_VSPDLYE (0x1u << 3) /**< \brief (LCDC_LCDCFG5) Vertical Synchronization Pulse End */ +#define LCDC_LCDCFG5_DISPPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG5) Display Signal Polarity */ +#define LCDC_LCDCFG5_DITHER (0x1u << 6) /**< \brief (LCDC_LCDCFG5) LCD Controller Dithering */ +#define LCDC_LCDCFG5_DISPDLY (0x1u << 7) /**< \brief (LCDC_LCDCFG5) LCD Controller Display Power Signal Synchronization */ +#define LCDC_LCDCFG5_MODE_Pos 8 +#define LCDC_LCDCFG5_MODE_Msk (0x3u << LCDC_LCDCFG5_MODE_Pos) /**< \brief (LCDC_LCDCFG5) LCD Controller Output Mode */ +#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 12 bits per pixel */ +#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 16 bits per pixel */ +#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 18 bits per pixel */ +#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3u << 8) /**< \brief (LCDC_LCDCFG5) LCD output mode is set to 24 bits per pixel */ +#define LCDC_LCDCFG5_PP (0x1u << 10) /**< \brief (LCDC_LCDCFG5) Post Processing Enable */ +#define LCDC_LCDCFG5_VSPSU (0x1u << 12) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Setup Configuration */ +#define LCDC_LCDCFG5_VSPHO (0x1u << 13) /**< \brief (LCDC_LCDCFG5) LCD Controller Vertical synchronization Pulse Hold Configuration */ +#define LCDC_LCDCFG5_GUARDTIME_Pos 16 +#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1fu << LCDC_LCDCFG5_GUARDTIME_Pos) /**< \brief (LCDC_LCDCFG5) LCD DISPLAY Guard Time */ +#define LCDC_LCDCFG5_GUARDTIME(value) ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos))) +/* -------- LCDC_LCDCFG6 : (LCDC Offset: 0x00000018) LCD Controller Configuration Register 6 -------- */ +#define LCDC_LCDCFG6_PWMPS_Pos 0 +#define LCDC_LCDCFG6_PWMPS_Msk (0x7u << LCDC_LCDCFG6_PWMPS_Pos) /**< \brief (LCDC_LCDCFG6) PWM Clock Prescaler */ +#define LCDC_LCDCFG6_PWMPS(value) ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos))) +#define LCDC_LCDCFG6_PWMPOL (0x1u << 4) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Signal Polarity */ +#define LCDC_LCDCFG6_PWMCVAL_Pos 8 +#define LCDC_LCDCFG6_PWMCVAL_Msk (0xffu << LCDC_LCDCFG6_PWMCVAL_Pos) /**< \brief (LCDC_LCDCFG6) LCD Controller PWM Compare Value */ +#define LCDC_LCDCFG6_PWMCVAL(value) ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos))) +/* -------- LCDC_LCDEN : (LCDC Offset: 0x00000020) LCD Controller Enable Register -------- */ +#define LCDC_LCDEN_CLKEN (0x1u << 0) /**< \brief (LCDC_LCDEN) LCD Controller Pixel Clock Enable */ +#define LCDC_LCDEN_SYNCEN (0x1u << 1) /**< \brief (LCDC_LCDEN) LCD Controller Horizontal and Vertical Synchronization Enable */ +#define LCDC_LCDEN_DISPEN (0x1u << 2) /**< \brief (LCDC_LCDEN) LCD Controller DISP Signal Enable */ +#define LCDC_LCDEN_PWMEN (0x1u << 3) /**< \brief (LCDC_LCDEN) LCD Controller Pulse Width Modulation Enable */ +/* -------- LCDC_LCDDIS : (LCDC Offset: 0x00000024) LCD Controller Disable Register -------- */ +#define LCDC_LCDDIS_CLKDIS (0x1u << 0) /**< \brief (LCDC_LCDDIS) LCD Controller Pixel Clock Disable */ +#define LCDC_LCDDIS_SYNCDIS (0x1u << 1) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Disable */ +#define LCDC_LCDDIS_DISPDIS (0x1u << 2) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Disable */ +#define LCDC_LCDDIS_PWMDIS (0x1u << 3) /**< \brief (LCDC_LCDDIS) LCD Controller Pulse Width Modulation Disable */ +#define LCDC_LCDDIS_CLKRST (0x1u << 8) /**< \brief (LCDC_LCDDIS) LCD Controller Clock Reset */ +#define LCDC_LCDDIS_SYNCRST (0x1u << 9) /**< \brief (LCDC_LCDDIS) LCD Controller Horizontal and Vertical Synchronization Reset */ +#define LCDC_LCDDIS_DISPRST (0x1u << 10) /**< \brief (LCDC_LCDDIS) LCD Controller DISP Signal Reset */ +#define LCDC_LCDDIS_PWMRST (0x1u << 11) /**< \brief (LCDC_LCDDIS) LCD Controller PWM Reset */ +/* -------- LCDC_LCDSR : (LCDC Offset: 0x00000028) LCD Controller Status Register -------- */ +#define LCDC_LCDSR_CLKSTS (0x1u << 0) /**< \brief (LCDC_LCDSR) Clock Status */ +#define LCDC_LCDSR_LCDSTS (0x1u << 1) /**< \brief (LCDC_LCDSR) LCD Controller Synchronization status */ +#define LCDC_LCDSR_DISPSTS (0x1u << 2) /**< \brief (LCDC_LCDSR) LCD Controller DISP Signal Status */ +#define LCDC_LCDSR_PWMSTS (0x1u << 3) /**< \brief (LCDC_LCDSR) LCD Controller PWM Signal Status */ +#define LCDC_LCDSR_SIPSTS (0x1u << 4) /**< \brief (LCDC_LCDSR) Synchronization In Progress */ +/* -------- LCDC_LCDIER : (LCDC Offset: 0x0000002C) LCD Controller Interrupt Enable Register -------- */ +#define LCDC_LCDIER_SOFIE (0x1u << 0) /**< \brief (LCDC_LCDIER) Start of Frame Interrupt Enable Register */ +#define LCDC_LCDIER_DISIE (0x1u << 1) /**< \brief (LCDC_LCDIER) LCD Disable Interrupt Enable Register */ +#define LCDC_LCDIER_DISPIE (0x1u << 2) /**< \brief (LCDC_LCDIER) Power UP/Down Sequence Terminated Interrupt Enable Register */ +#define LCDC_LCDIER_FIFOERRIE (0x1u << 4) /**< \brief (LCDC_LCDIER) Output FIFO Error Interrupt Enable Register */ +#define LCDC_LCDIER_BASEIE (0x1u << 8) /**< \brief (LCDC_LCDIER) Base Layer Interrupt Enable Register */ +#define LCDC_LCDIER_OVR1IE (0x1u << 9) /**< \brief (LCDC_LCDIER) Overlay 1 Interrupt Enable Register */ +#define LCDC_LCDIER_OVR2IE (0x1u << 10) /**< \brief (LCDC_LCDIER) Overlay 2 Interrupt Enable Register */ +#define LCDC_LCDIER_HEOIE (0x1u << 11) /**< \brief (LCDC_LCDIER) High End Overlay Interrupt Enable Register */ +#define LCDC_LCDIER_HCRIE (0x1u << 12) /**< \brief (LCDC_LCDIER) Hardware Cursor Interrupt Enable Register */ +#define LCDC_LCDIER_PPIE (0x1u << 13) /**< \brief (LCDC_LCDIER) Post Processing Interrupt Enable Register */ +/* -------- LCDC_LCDIDR : (LCDC Offset: 0x00000030) LCD Controller Interrupt Disable Register -------- */ +#define LCDC_LCDIDR_SOFID (0x1u << 0) /**< \brief (LCDC_LCDIDR) Start of Frame Interrupt Disable Register */ +#define LCDC_LCDIDR_DISID (0x1u << 1) /**< \brief (LCDC_LCDIDR) LCD Disable Interrupt Disable Register */ +#define LCDC_LCDIDR_DISPID (0x1u << 2) /**< \brief (LCDC_LCDIDR) Power UP/Down Sequence Terminated Interrupt Disable Register */ +#define LCDC_LCDIDR_FIFOERRID (0x1u << 4) /**< \brief (LCDC_LCDIDR) Output FIFO Error Interrupt Disable Register */ +#define LCDC_LCDIDR_BASEID (0x1u << 8) /**< \brief (LCDC_LCDIDR) Base Layer Interrupt Disable Register */ +#define LCDC_LCDIDR_OVR1ID (0x1u << 9) /**< \brief (LCDC_LCDIDR) Overlay 1 Interrupt Disable Register */ +#define LCDC_LCDIDR_OVR2ID (0x1u << 10) /**< \brief (LCDC_LCDIDR) Overlay 2 Interrupt Disable Register */ +#define LCDC_LCDIDR_HEOID (0x1u << 11) /**< \brief (LCDC_LCDIDR) High End Overlay Interrupt Disable Register */ +#define LCDC_LCDIDR_HCRID (0x1u << 12) /**< \brief (LCDC_LCDIDR) Hardware Cursor Interrupt Disable Register */ +#define LCDC_LCDIDR_PPID (0x1u << 13) /**< \brief (LCDC_LCDIDR) Post Processing Interrupt Disable Register */ +/* -------- LCDC_LCDIMR : (LCDC Offset: 0x00000034) LCD Controller Interrupt Mask Register -------- */ +#define LCDC_LCDIMR_SOFIM (0x1u << 0) /**< \brief (LCDC_LCDIMR) Start of Frame Interrupt Mask Register */ +#define LCDC_LCDIMR_DISIM (0x1u << 1) /**< \brief (LCDC_LCDIMR) LCD Disable Interrupt Mask Register */ +#define LCDC_LCDIMR_DISPIM (0x1u << 2) /**< \brief (LCDC_LCDIMR) Power UP/Down Sequence Terminated Interrupt Mask Register */ +#define LCDC_LCDIMR_FIFOERRIM (0x1u << 4) /**< \brief (LCDC_LCDIMR) Output FIFO Error Interrupt Mask Register */ +#define LCDC_LCDIMR_BASEIM (0x1u << 8) /**< \brief (LCDC_LCDIMR) Base Layer Interrupt Mask Register */ +#define LCDC_LCDIMR_OVR1IM (0x1u << 9) /**< \brief (LCDC_LCDIMR) Overlay 1 Interrupt Mask Register */ +#define LCDC_LCDIMR_OVR2IM (0x1u << 10) /**< \brief (LCDC_LCDIMR) Overlay 2 Interrupt Mask Register */ +#define LCDC_LCDIMR_HEOIM (0x1u << 11) /**< \brief (LCDC_LCDIMR) High End Overlay Interrupt Mask Register */ +#define LCDC_LCDIMR_HCRIM (0x1u << 12) /**< \brief (LCDC_LCDIMR) Hardware Cursor Interrupt Mask Register */ +#define LCDC_LCDIMR_PPIM (0x1u << 13) /**< \brief (LCDC_LCDIMR) Post Processing Interrupt Mask Register */ +/* -------- LCDC_LCDISR : (LCDC Offset: 0x00000038) LCD Controller Interrupt Status Register -------- */ +#define LCDC_LCDISR_SOF (0x1u << 0) /**< \brief (LCDC_LCDISR) Start of Frame Interrupt Status Register */ +#define LCDC_LCDISR_DIS (0x1u << 1) /**< \brief (LCDC_LCDISR) LCD Disable Interrupt Status Register */ +#define LCDC_LCDISR_DISP (0x1u << 2) /**< \brief (LCDC_LCDISR) Power-up/Power-down Sequence Terminated Interrupt Status Register */ +#define LCDC_LCDISR_FIFOERR (0x1u << 4) /**< \brief (LCDC_LCDISR) Output FIFO Error */ +#define LCDC_LCDISR_BASE (0x1u << 8) /**< \brief (LCDC_LCDISR) Base Layer Raw Interrupt Status Register */ +#define LCDC_LCDISR_OVR1 (0x1u << 9) /**< \brief (LCDC_LCDISR) Overlay 1 Raw Interrupt Status Register */ +#define LCDC_LCDISR_OVR2 (0x1u << 10) /**< \brief (LCDC_LCDISR) Overlay 2 Raw Interrupt Status Register */ +#define LCDC_LCDISR_HEO (0x1u << 11) /**< \brief (LCDC_LCDISR) High End Overlay Raw Interrupt Status Register */ +#define LCDC_LCDISR_HCR (0x1u << 12) /**< \brief (LCDC_LCDISR) Hardware Cursor Raw Interrupt Status Register */ +#define LCDC_LCDISR_PP (0x1u << 13) /**< \brief (LCDC_LCDISR) Post Processing Raw Interrupt Status Register */ +/* -------- LCDC_BASECHER : (LCDC Offset: 0x00000040) Base Layer Channel Enable Register -------- */ +#define LCDC_BASECHER_CHEN (0x1u << 0) /**< \brief (LCDC_BASECHER) Channel Enable Register */ +#define LCDC_BASECHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_BASECHER) Update Overlay Attributes Enable Register */ +#define LCDC_BASECHER_A2QEN (0x1u << 2) /**< \brief (LCDC_BASECHER) Add Head Pointer Enable Register */ +/* -------- LCDC_BASECHDR : (LCDC Offset: 0x00000044) Base Layer Channel Disable Register -------- */ +#define LCDC_BASECHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_BASECHDR) Channel Disable Register */ +#define LCDC_BASECHDR_CHRST (0x1u << 8) /**< \brief (LCDC_BASECHDR) Channel Reset Register */ +/* -------- LCDC_BASECHSR : (LCDC Offset: 0x00000048) Base Layer Channel Status Register -------- */ +#define LCDC_BASECHSR_CHSR (0x1u << 0) /**< \brief (LCDC_BASECHSR) Channel Status Register */ +#define LCDC_BASECHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_BASECHSR) Update Overlay Attributes In Progress */ +#define LCDC_BASECHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_BASECHSR) Add To Queue Pending Register */ +/* -------- LCDC_BASEIER : (LCDC Offset: 0x0000004C) Base Layer Interrupt Enable Register -------- */ +#define LCDC_BASEIER_DMA (0x1u << 2) /**< \brief (LCDC_BASEIER) End of DMA Transfer Interrupt Enable Register */ +#define LCDC_BASEIER_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIER) Descriptor Loaded Interrupt Enable Register */ +#define LCDC_BASEIER_ADD (0x1u << 4) /**< \brief (LCDC_BASEIER) Head Descriptor Loaded Interrupt Enable Register */ +#define LCDC_BASEIER_DONE (0x1u << 5) /**< \brief (LCDC_BASEIER) End of List Interrupt Enable Register */ +#define LCDC_BASEIER_OVR (0x1u << 6) /**< \brief (LCDC_BASEIER) Overflow Interrupt Enable Register */ +/* -------- LCDC_BASEIDR : (LCDC Offset: 0x00000050) Base Layer Interrupt Disabled Register -------- */ +#define LCDC_BASEIDR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIDR) End of DMA Transfer Interrupt Disable Register */ +#define LCDC_BASEIDR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIDR) Descriptor Loaded Interrupt Disable Register */ +#define LCDC_BASEIDR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIDR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_BASEIDR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIDR) End of List Interrupt Disable Register */ +#define LCDC_BASEIDR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIDR) Overflow Interrupt Disable Register */ +/* -------- LCDC_BASEIMR : (LCDC Offset: 0x00000054) Base Layer Interrupt Mask Register -------- */ +#define LCDC_BASEIMR_DMA (0x1u << 2) /**< \brief (LCDC_BASEIMR) End of DMA Transfer Interrupt Mask Register */ +#define LCDC_BASEIMR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEIMR) Descriptor Loaded Interrupt Mask Register */ +#define LCDC_BASEIMR_ADD (0x1u << 4) /**< \brief (LCDC_BASEIMR) Head Descriptor Loaded Interrupt Mask Register */ +#define LCDC_BASEIMR_DONE (0x1u << 5) /**< \brief (LCDC_BASEIMR) End of List Interrupt Mask Register */ +#define LCDC_BASEIMR_OVR (0x1u << 6) /**< \brief (LCDC_BASEIMR) Overflow Interrupt Mask Register */ +/* -------- LCDC_BASEISR : (LCDC Offset: 0x00000058) Base Layer Interrupt status Register -------- */ +#define LCDC_BASEISR_DMA (0x1u << 2) /**< \brief (LCDC_BASEISR) End of DMA Transfer */ +#define LCDC_BASEISR_DSCR (0x1u << 3) /**< \brief (LCDC_BASEISR) DMA Descriptor Loaded */ +#define LCDC_BASEISR_ADD (0x1u << 4) /**< \brief (LCDC_BASEISR) Head Descriptor Loaded */ +#define LCDC_BASEISR_DONE (0x1u << 5) /**< \brief (LCDC_BASEISR) End of List Detected */ +#define LCDC_BASEISR_OVR (0x1u << 6) /**< \brief (LCDC_BASEISR) Overflow Detected */ +/* -------- LCDC_BASEHEAD : (LCDC Offset: 0x0000005C) Base DMA Head Register -------- */ +#define LCDC_BASEHEAD_HEAD_Pos 2 +#define LCDC_BASEHEAD_HEAD_Msk (0x3fffffffu << LCDC_BASEHEAD_HEAD_Pos) /**< \brief (LCDC_BASEHEAD) DMA Head Pointer */ +#define LCDC_BASEHEAD_HEAD(value) ((LCDC_BASEHEAD_HEAD_Msk & ((value) << LCDC_BASEHEAD_HEAD_Pos))) +/* -------- LCDC_BASEADDR : (LCDC Offset: 0x00000060) Base DMA Address Register -------- */ +#define LCDC_BASEADDR_ADDR_Pos 0 +#define LCDC_BASEADDR_ADDR_Msk (0xffffffffu << LCDC_BASEADDR_ADDR_Pos) /**< \brief (LCDC_BASEADDR) DMA Transfer Start Address */ +#define LCDC_BASEADDR_ADDR(value) ((LCDC_BASEADDR_ADDR_Msk & ((value) << LCDC_BASEADDR_ADDR_Pos))) +/* -------- LCDC_BASECTRL : (LCDC Offset: 0x00000064) Base DMA Control Register -------- */ +#define LCDC_BASECTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_BASECTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_BASECTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_BASECTRL) Lookup Table Fetch Enable */ +#define LCDC_BASECTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_BASECTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_BASECTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_BASECTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_BASECTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_BASECTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_BASECTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_BASECTRL) End of List Interrupt Enable */ +/* -------- LCDC_BASENEXT : (LCDC Offset: 0x00000068) Base DMA Next Register -------- */ +#define LCDC_BASENEXT_NEXT_Pos 0 +#define LCDC_BASENEXT_NEXT_Msk (0xffffffffu << LCDC_BASENEXT_NEXT_Pos) /**< \brief (LCDC_BASENEXT) DMA Descriptor Next Address */ +#define LCDC_BASENEXT_NEXT(value) ((LCDC_BASENEXT_NEXT_Msk & ((value) << LCDC_BASENEXT_NEXT_Pos))) +/* -------- LCDC_BASECFG0 : (LCDC Offset: 0x0000006C) Base Configuration register 0 -------- */ +#define LCDC_BASECFG0_SIF (0x1u << 0) /**< \brief (LCDC_BASECFG0) Source Interface */ +#define LCDC_BASECFG0_BLEN_Pos 4 +#define LCDC_BASECFG0_BLEN_Msk (0x3u << LCDC_BASECFG0_BLEN_Pos) /**< \brief (LCDC_BASECFG0) AHB Burst Length */ +#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_BASECFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_BASECFG0_DLBO (0x1u << 8) /**< \brief (LCDC_BASECFG0) Defined Length Burst Only For Channel Bus Transaction. */ +/* -------- LCDC_BASECFG1 : (LCDC Offset: 0x00000070) Base Configuration register 1 -------- */ +#define LCDC_BASECFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_BASECFG1) Color Lookup Table Enable */ +#define LCDC_BASECFG1_RGBMODE_Pos 4 +#define LCDC_BASECFG1_RGBMODE_Msk (0xfu << LCDC_BASECFG1_RGBMODE_Pos) /**< \brief (LCDC_BASECFG1) RGB Input Mode Selection */ +#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_BASECFG1) 12 bpp RGB 444 */ +#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp ARGB 4444 */ +#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGBA 4444 */ +#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp RGB 565 */ +#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_BASECFG1) 16 bpp TRGB 1555 */ +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 */ +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_BASECFG1) 18 bpp RGB 666 PACKED */ +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 */ +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_BASECFG1) 19 bpp TRGB 1666 PACKED */ +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 */ +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_BASECFG1) 24 bpp RGB 888 PACKED */ +#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_BASECFG1) 25 bpp TRGB 1888 */ +#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp ARGB 8888 */ +#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_BASECFG1) 32 bpp RGBA 8888 */ +#define LCDC_BASECFG1_CLUTMODE_Pos 8 +#define LCDC_BASECFG1_CLUTMODE_Msk (0x3u << LCDC_BASECFG1_CLUTMODE_Pos) /**< \brief (LCDC_BASECFG1) Color Lookup Table Input Mode Selection */ +#define LCDC_BASECFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 1 bit per pixel */ +#define LCDC_BASECFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 2 bits per pixel */ +#define LCDC_BASECFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 4 bits per pixel */ +#define LCDC_BASECFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_BASECFG1) color lookup table mode set to 8 bits per pixel */ +/* -------- LCDC_BASECFG2 : (LCDC Offset: 0x00000074) Base Configuration register 2 -------- */ +#define LCDC_BASECFG2_XSTRIDE_Pos 0 +#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffffu << LCDC_BASECFG2_XSTRIDE_Pos) /**< \brief (LCDC_BASECFG2) Horizontal Stride */ +#define LCDC_BASECFG2_XSTRIDE(value) ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos))) +/* -------- LCDC_BASECFG3 : (LCDC Offset: 0x00000078) Base Configuration register 3 -------- */ +#define LCDC_BASECFG3_BDEF_Pos 0 +#define LCDC_BASECFG3_BDEF_Msk (0xffu << LCDC_BASECFG3_BDEF_Pos) /**< \brief (LCDC_BASECFG3) Blue Default */ +#define LCDC_BASECFG3_BDEF(value) ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos))) +#define LCDC_BASECFG3_GDEF_Pos 8 +#define LCDC_BASECFG3_GDEF_Msk (0xffu << LCDC_BASECFG3_GDEF_Pos) /**< \brief (LCDC_BASECFG3) Green Default */ +#define LCDC_BASECFG3_GDEF(value) ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos))) +#define LCDC_BASECFG3_RDEF_Pos 16 +#define LCDC_BASECFG3_RDEF_Msk (0xffu << LCDC_BASECFG3_RDEF_Pos) /**< \brief (LCDC_BASECFG3) Red Default */ +#define LCDC_BASECFG3_RDEF(value) ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos))) +/* -------- LCDC_BASECFG4 : (LCDC Offset: 0x0000007C) Base Configuration register 4 -------- */ +#define LCDC_BASECFG4_DMA (0x1u << 8) /**< \brief (LCDC_BASECFG4) Use DMA Data Path */ +#define LCDC_BASECFG4_REP (0x1u << 9) /**< \brief (LCDC_BASECFG4) Use Replication logic to expand RGB color to 24 bits */ +#define LCDC_BASECFG4_DISCEN (0x1u << 11) /**< \brief (LCDC_BASECFG4) Discard Area Enable */ +/* -------- LCDC_BASECFG5 : (LCDC Offset: 0x00000080) Base Configuration register 5 -------- */ +#define LCDC_BASECFG5_DISCXPOS_Pos 0 +#define LCDC_BASECFG5_DISCXPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCXPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area horizontal coordinate */ +#define LCDC_BASECFG5_DISCXPOS(value) ((LCDC_BASECFG5_DISCXPOS_Msk & ((value) << LCDC_BASECFG5_DISCXPOS_Pos))) +#define LCDC_BASECFG5_DISCYPOS_Pos 16 +#define LCDC_BASECFG5_DISCYPOS_Msk (0x7ffu << LCDC_BASECFG5_DISCYPOS_Pos) /**< \brief (LCDC_BASECFG5) Discard Area Vertical coordinate */ +#define LCDC_BASECFG5_DISCYPOS(value) ((LCDC_BASECFG5_DISCYPOS_Msk & ((value) << LCDC_BASECFG5_DISCYPOS_Pos))) +/* -------- LCDC_BASECFG6 : (LCDC Offset: 0x00000084) Base Configuration register 6 -------- */ +#define LCDC_BASECFG6_DISCXSIZE_Pos 0 +#define LCDC_BASECFG6_DISCXSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCXSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Horizontal Size */ +#define LCDC_BASECFG6_DISCXSIZE(value) ((LCDC_BASECFG6_DISCXSIZE_Msk & ((value) << LCDC_BASECFG6_DISCXSIZE_Pos))) +#define LCDC_BASECFG6_DISCYSIZE_Pos 16 +#define LCDC_BASECFG6_DISCYSIZE_Msk (0x7ffu << LCDC_BASECFG6_DISCYSIZE_Pos) /**< \brief (LCDC_BASECFG6) Discard Area Vertical Size */ +#define LCDC_BASECFG6_DISCYSIZE(value) ((LCDC_BASECFG6_DISCYSIZE_Msk & ((value) << LCDC_BASECFG6_DISCYSIZE_Pos))) +/* -------- LCDC_OVR1CHER : (LCDC Offset: 0x00000140) Overlay 1 Channel Enable Register -------- */ +#define LCDC_OVR1CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR1CHER) Channel Enable Register */ +#define LCDC_OVR1CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR1CHER) Update Overlay Attributes Enable Register */ +#define LCDC_OVR1CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR1CHER) Add Head Pointer Enable Register */ +/* -------- LCDC_OVR1CHDR : (LCDC Offset: 0x00000144) Overlay 1 Channel Disable Register -------- */ +#define LCDC_OVR1CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR1CHDR) Channel Disable Register */ +#define LCDC_OVR1CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR1CHDR) Channel Reset Register */ +/* -------- LCDC_OVR1CHSR : (LCDC Offset: 0x00000148) Overlay 1 Channel Status Register -------- */ +#define LCDC_OVR1CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR1CHSR) Channel Status Register */ +#define LCDC_OVR1CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR1CHSR) Update Overlay Attributes In Progress */ +#define LCDC_OVR1CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR1CHSR) Add to Queue Pending Register */ +/* -------- LCDC_OVR1IER : (LCDC Offset: 0x0000014C) Overlay 1 Interrupt Enable Register -------- */ +#define LCDC_OVR1IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IER) End of DMA Transfer Interrupt Enable Register */ +#define LCDC_OVR1IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IER) Descriptor Loaded Interrupt Enable Register */ +#define LCDC_OVR1IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IER) Head Descriptor Loaded Interrupt Enable Register */ +#define LCDC_OVR1IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IER) End of List Interrupt Enable Register */ +#define LCDC_OVR1IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IER) Overflow Interrupt Enable Register */ +/* -------- LCDC_OVR1IDR : (LCDC Offset: 0x00000150) Overlay 1 Interrupt Disable Register -------- */ +#define LCDC_OVR1IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IDR) End of DMA Transfer Interrupt Disable Register */ +#define LCDC_OVR1IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IDR) Descriptor Loaded Interrupt Disable Register */ +#define LCDC_OVR1IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IDR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_OVR1IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IDR) End of List Interrupt Disable Register */ +#define LCDC_OVR1IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IDR) Overflow Interrupt Disable Register */ +/* -------- LCDC_OVR1IMR : (LCDC Offset: 0x00000154) Overlay 1 Interrupt Mask Register -------- */ +#define LCDC_OVR1IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1IMR) End of DMA Transfer Interrupt Mask Register */ +#define LCDC_OVR1IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1IMR) Descriptor Loaded Interrupt Mask Register */ +#define LCDC_OVR1IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1IMR) Head Descriptor Loaded Interrupt Mask Register */ +#define LCDC_OVR1IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1IMR) End of List Interrupt Mask Register */ +#define LCDC_OVR1IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1IMR) Overflow Interrupt Mask Register */ +/* -------- LCDC_OVR1ISR : (LCDC Offset: 0x00000158) Overlay 1 Interrupt Status Register -------- */ +#define LCDC_OVR1ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR1ISR) End of DMA Transfer */ +#define LCDC_OVR1ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR1ISR) DMA Descriptor Loaded */ +#define LCDC_OVR1ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR1ISR) Head Descriptor Loaded */ +#define LCDC_OVR1ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR1ISR) End of List Detected Register */ +#define LCDC_OVR1ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR1ISR) Overflow Detected */ +/* -------- LCDC_OVR1HEAD : (LCDC Offset: 0x0000015C) Overlay 1 DMA Head Register -------- */ +#define LCDC_OVR1HEAD_HEAD_Pos 2 +#define LCDC_OVR1HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR1HEAD_HEAD_Pos) /**< \brief (LCDC_OVR1HEAD) DMA Head Pointer */ +#define LCDC_OVR1HEAD_HEAD(value) ((LCDC_OVR1HEAD_HEAD_Msk & ((value) << LCDC_OVR1HEAD_HEAD_Pos))) +/* -------- LCDC_OVR1ADDR : (LCDC Offset: 0x00000160) Overlay 1 DMA Address Register -------- */ +#define LCDC_OVR1ADDR_ADDR_Pos 0 +#define LCDC_OVR1ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR1ADDR_ADDR_Pos) /**< \brief (LCDC_OVR1ADDR) DMA Transfer Overlay 1 Address */ +#define LCDC_OVR1ADDR_ADDR(value) ((LCDC_OVR1ADDR_ADDR_Msk & ((value) << LCDC_OVR1ADDR_ADDR_Pos))) +/* -------- LCDC_OVR1CTRL : (LCDC Offset: 0x00000164) Overlay1 DMA Control Register -------- */ +#define LCDC_OVR1CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR1CTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_OVR1CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR1CTRL) Lookup Table Fetch Enable */ +#define LCDC_OVR1CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR1CTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_OVR1CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR1CTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_OVR1CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR1CTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_OVR1CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR1CTRL) End of List Interrupt Enable */ +/* -------- LCDC_OVR1NEXT : (LCDC Offset: 0x00000168) Overlay1 DMA Next Register -------- */ +#define LCDC_OVR1NEXT_NEXT_Pos 0 +#define LCDC_OVR1NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR1NEXT_NEXT_Pos) /**< \brief (LCDC_OVR1NEXT) DMA Descriptor Next Address */ +#define LCDC_OVR1NEXT_NEXT(value) ((LCDC_OVR1NEXT_NEXT_Msk & ((value) << LCDC_OVR1NEXT_NEXT_Pos))) +/* -------- LCDC_OVR1CFG0 : (LCDC Offset: 0x0000016C) Overlay 1 Configuration 0 Register -------- */ +#define LCDC_OVR1CFG0_SIF (0x1u << 0) /**< \brief (LCDC_OVR1CFG0) Source Interface */ +#define LCDC_OVR1CFG0_BLEN_Pos 4 +#define LCDC_OVR1CFG0_BLEN_Msk (0x3u << LCDC_OVR1CFG0_BLEN_Pos) /**< \brief (LCDC_OVR1CFG0) AHB Burst Length */ +#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR1CFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR1CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR1CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR1CFG0) Defined Length Burst Only for Channel Bus Transaction. */ +#define LCDC_OVR1CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Optimization Disable */ +#define LCDC_OVR1CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR1CFG0) Hardware Rotation Lock Disable */ +/* -------- LCDC_OVR1CFG1 : (LCDC Offset: 0x00000170) Overlay 1 Configuration 1 Register -------- */ +#define LCDC_OVR1CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR1CFG1) Color Lookup Table Enable */ +#define LCDC_OVR1CFG1_RGBMODE_Pos 4 +#define LCDC_OVR1CFG1_RGBMODE_Msk (0xfu << LCDC_OVR1CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR1CFG1) RGB Input Mode Selection */ +#define LCDC_OVR1CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR1CFG1) 12 bpp RGB 444 */ +#define LCDC_OVR1CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp ARGB 4444 */ +#define LCDC_OVR1CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGBA 4444 */ +#define LCDC_OVR1CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp RGB 565 */ +#define LCDC_OVR1CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR1CFG1) 16 bpp TRGB 1555 */ +#define LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 */ +#define LCDC_OVR1CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR1CFG1) 18 bpp RGB 666 PACKED */ +#define LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 */ +#define LCDC_OVR1CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR1CFG1) 19 bpp TRGB 1666 PACKED */ +#define LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 */ +#define LCDC_OVR1CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR1CFG1) 24 bpp RGB 888 PACKED */ +#define LCDC_OVR1CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR1CFG1) 25 bpp TRGB 1888 */ +#define LCDC_OVR1CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp ARGB 8888 */ +#define LCDC_OVR1CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR1CFG1) 32 bpp RGBA 8888 */ +#define LCDC_OVR1CFG1_CLUTMODE_Pos 8 +#define LCDC_OVR1CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR1CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR1CFG1) Color Lookup table input mode selection */ +#define LCDC_OVR1CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 1 bit per pixel */ +#define LCDC_OVR1CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 2 bits per pixel */ +#define LCDC_OVR1CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 4 bits per pixel */ +#define LCDC_OVR1CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR1CFG1) color lookup table mode set to 8 bits per pixel */ +/* -------- LCDC_OVR1CFG2 : (LCDC Offset: 0x00000174) Overlay 1 Configuration 2 Register -------- */ +#define LCDC_OVR1CFG2_XPOS_Pos 0 +#define LCDC_OVR1CFG2_XPOS_Msk (0x7ffu << LCDC_OVR1CFG2_XPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Horizontal Window Position */ +#define LCDC_OVR1CFG2_XPOS(value) ((LCDC_OVR1CFG2_XPOS_Msk & ((value) << LCDC_OVR1CFG2_XPOS_Pos))) +#define LCDC_OVR1CFG2_YPOS_Pos 16 +#define LCDC_OVR1CFG2_YPOS_Msk (0x7ffu << LCDC_OVR1CFG2_YPOS_Pos) /**< \brief (LCDC_OVR1CFG2) Vertical Window Position */ +#define LCDC_OVR1CFG2_YPOS(value) ((LCDC_OVR1CFG2_YPOS_Msk & ((value) << LCDC_OVR1CFG2_YPOS_Pos))) +/* -------- LCDC_OVR1CFG3 : (LCDC Offset: 0x00000178) Overlay 1 Configuration 3 Register -------- */ +#define LCDC_OVR1CFG3_XSIZE_Pos 0 +#define LCDC_OVR1CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Horizontal Window Size */ +#define LCDC_OVR1CFG3_XSIZE(value) ((LCDC_OVR1CFG3_XSIZE_Msk & ((value) << LCDC_OVR1CFG3_XSIZE_Pos))) +#define LCDC_OVR1CFG3_YSIZE_Pos 16 +#define LCDC_OVR1CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR1CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR1CFG3) Vertical Window Size */ +#define LCDC_OVR1CFG3_YSIZE(value) ((LCDC_OVR1CFG3_YSIZE_Msk & ((value) << LCDC_OVR1CFG3_YSIZE_Pos))) +/* -------- LCDC_OVR1CFG4 : (LCDC Offset: 0x0000017C) Overlay 1 Configuration 4 Register -------- */ +#define LCDC_OVR1CFG4_XSTRIDE_Pos 0 +#define LCDC_OVR1CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG4) Horizontal Stride */ +#define LCDC_OVR1CFG4_XSTRIDE(value) ((LCDC_OVR1CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR1CFG4_XSTRIDE_Pos))) +/* -------- LCDC_OVR1CFG5 : (LCDC Offset: 0x00000180) Overlay 1 Configuration 5 Register -------- */ +#define LCDC_OVR1CFG5_PSTRIDE_Pos 0 +#define LCDC_OVR1CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR1CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR1CFG5) Pixel Stride */ +#define LCDC_OVR1CFG5_PSTRIDE(value) ((LCDC_OVR1CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR1CFG5_PSTRIDE_Pos))) +/* -------- LCDC_OVR1CFG6 : (LCDC Offset: 0x00000184) Overlay 1 Configuration 6 Register -------- */ +#define LCDC_OVR1CFG6_BDEF_Pos 0 +#define LCDC_OVR1CFG6_BDEF_Msk (0xffu << LCDC_OVR1CFG6_BDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Blue Default */ +#define LCDC_OVR1CFG6_BDEF(value) ((LCDC_OVR1CFG6_BDEF_Msk & ((value) << LCDC_OVR1CFG6_BDEF_Pos))) +#define LCDC_OVR1CFG6_GDEF_Pos 8 +#define LCDC_OVR1CFG6_GDEF_Msk (0xffu << LCDC_OVR1CFG6_GDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Green Default */ +#define LCDC_OVR1CFG6_GDEF(value) ((LCDC_OVR1CFG6_GDEF_Msk & ((value) << LCDC_OVR1CFG6_GDEF_Pos))) +#define LCDC_OVR1CFG6_RDEF_Pos 16 +#define LCDC_OVR1CFG6_RDEF_Msk (0xffu << LCDC_OVR1CFG6_RDEF_Pos) /**< \brief (LCDC_OVR1CFG6) Red Default */ +#define LCDC_OVR1CFG6_RDEF(value) ((LCDC_OVR1CFG6_RDEF_Msk & ((value) << LCDC_OVR1CFG6_RDEF_Pos))) +/* -------- LCDC_OVR1CFG7 : (LCDC Offset: 0x00000188) Overlay 1 Configuration 7 Register -------- */ +#define LCDC_OVR1CFG7_BKEY_Pos 0 +#define LCDC_OVR1CFG7_BKEY_Msk (0xffu << LCDC_OVR1CFG7_BKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Blue Color Component Chroma Key */ +#define LCDC_OVR1CFG7_BKEY(value) ((LCDC_OVR1CFG7_BKEY_Msk & ((value) << LCDC_OVR1CFG7_BKEY_Pos))) +#define LCDC_OVR1CFG7_GKEY_Pos 8 +#define LCDC_OVR1CFG7_GKEY_Msk (0xffu << LCDC_OVR1CFG7_GKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Green Color Component Chroma Key */ +#define LCDC_OVR1CFG7_GKEY(value) ((LCDC_OVR1CFG7_GKEY_Msk & ((value) << LCDC_OVR1CFG7_GKEY_Pos))) +#define LCDC_OVR1CFG7_RKEY_Pos 16 +#define LCDC_OVR1CFG7_RKEY_Msk (0xffu << LCDC_OVR1CFG7_RKEY_Pos) /**< \brief (LCDC_OVR1CFG7) Red Color Component Chroma Key */ +#define LCDC_OVR1CFG7_RKEY(value) ((LCDC_OVR1CFG7_RKEY_Msk & ((value) << LCDC_OVR1CFG7_RKEY_Pos))) +/* -------- LCDC_OVR1CFG8 : (LCDC Offset: 0x0000018C) Overlay 1 Configuration 8Register -------- */ +#define LCDC_OVR1CFG8_BMASK_Pos 0 +#define LCDC_OVR1CFG8_BMASK_Msk (0xffu << LCDC_OVR1CFG8_BMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Blue Color Component Chroma Key Mask */ +#define LCDC_OVR1CFG8_BMASK(value) ((LCDC_OVR1CFG8_BMASK_Msk & ((value) << LCDC_OVR1CFG8_BMASK_Pos))) +#define LCDC_OVR1CFG8_GMASK_Pos 8 +#define LCDC_OVR1CFG8_GMASK_Msk (0xffu << LCDC_OVR1CFG8_GMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Green Color Component Chroma Key Mask */ +#define LCDC_OVR1CFG8_GMASK(value) ((LCDC_OVR1CFG8_GMASK_Msk & ((value) << LCDC_OVR1CFG8_GMASK_Pos))) +#define LCDC_OVR1CFG8_RMASK_Pos 16 +#define LCDC_OVR1CFG8_RMASK_Msk (0xffu << LCDC_OVR1CFG8_RMASK_Pos) /**< \brief (LCDC_OVR1CFG8) Red Color Component Chroma Key Mask */ +#define LCDC_OVR1CFG8_RMASK(value) ((LCDC_OVR1CFG8_RMASK_Msk & ((value) << LCDC_OVR1CFG8_RMASK_Pos))) +/* -------- LCDC_OVR1CFG9 : (LCDC Offset: 0x00000190) Overlay 1 Configuration 9 Register -------- */ +#define LCDC_OVR1CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR1CFG9) Blender Chroma Key Enable */ +#define LCDC_OVR1CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR1CFG9) Blender Inverted Blender Output Enable */ +#define LCDC_OVR1CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR1CFG9) Blender Iterated Color Enable */ +#define LCDC_OVR1CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR1CFG9) Blender Use Iterated Color */ +#define LCDC_OVR1CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR1CFG9) Blender Reverse Alpha */ +#define LCDC_OVR1CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha Enable */ +#define LCDC_OVR1CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR1CFG9) Blender Local Alpha Enable */ +#define LCDC_OVR1CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR1CFG9) Blender Overlay Layer Enable */ +#define LCDC_OVR1CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR1CFG9) Blender DMA Layer Enable */ +#define LCDC_OVR1CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR1CFG9) Use Replication logic to expand RGB color to 24 bits */ +#define LCDC_OVR1CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR1CFG9) Destination Chroma Keying */ +#define LCDC_OVR1CFG9_GA_Pos 16 +#define LCDC_OVR1CFG9_GA_Msk (0xffu << LCDC_OVR1CFG9_GA_Pos) /**< \brief (LCDC_OVR1CFG9) Blender Global Alpha */ +#define LCDC_OVR1CFG9_GA(value) ((LCDC_OVR1CFG9_GA_Msk & ((value) << LCDC_OVR1CFG9_GA_Pos))) +/* -------- LCDC_OVR2CHER : (LCDC Offset: 0x00000240) Overlay 2 Channel Enable Register -------- */ +#define LCDC_OVR2CHER_CHEN (0x1u << 0) /**< \brief (LCDC_OVR2CHER) Channel Enable Register */ +#define LCDC_OVR2CHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_OVR2CHER) Update Overlay Attributes Enable Register */ +#define LCDC_OVR2CHER_A2QEN (0x1u << 2) /**< \brief (LCDC_OVR2CHER) Add Head Pointer Enable Register */ +/* -------- LCDC_OVR2CHDR : (LCDC Offset: 0x00000244) Overlay 2 Channel Disable Register -------- */ +#define LCDC_OVR2CHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_OVR2CHDR) Channel Disable Register */ +#define LCDC_OVR2CHDR_CHRST (0x1u << 8) /**< \brief (LCDC_OVR2CHDR) Channel Reset Register */ +/* -------- LCDC_OVR2CHSR : (LCDC Offset: 0x00000248) Overlay 2 Channel Status Register -------- */ +#define LCDC_OVR2CHSR_CHSR (0x1u << 0) /**< \brief (LCDC_OVR2CHSR) Channel Status Register */ +#define LCDC_OVR2CHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_OVR2CHSR) Update Overlay Attributes In Progress */ +#define LCDC_OVR2CHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_OVR2CHSR) Add To Queue Pending Register */ +/* -------- LCDC_OVR2IER : (LCDC Offset: 0x0000024C) Overlay 2 Interrupt Enable Register -------- */ +#define LCDC_OVR2IER_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IER) End of DMA Transfer Interrupt Enable Register */ +#define LCDC_OVR2IER_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IER) Descriptor Loaded Interrupt Enable Register */ +#define LCDC_OVR2IER_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IER) Head Descriptor Loaded Interrupt Enable Register */ +#define LCDC_OVR2IER_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IER) End of List Interrupt Enable Register */ +#define LCDC_OVR2IER_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IER) Overflow Interrupt Enable Register */ +/* -------- LCDC_OVR2IDR : (LCDC Offset: 0x00000250) Overlay 2 Interrupt Disable Register -------- */ +#define LCDC_OVR2IDR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IDR) End of DMA Transfer Interrupt Disable Register */ +#define LCDC_OVR2IDR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IDR) Descriptor Loaded Interrupt Disable Register */ +#define LCDC_OVR2IDR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IDR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_OVR2IDR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IDR) End of List Interrupt Disable Register */ +#define LCDC_OVR2IDR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IDR) Overflow Interrupt Disable Register */ +/* -------- LCDC_OVR2IMR : (LCDC Offset: 0x00000254) Overlay 2 Interrupt Mask Register -------- */ +#define LCDC_OVR2IMR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2IMR) End of DMA Transfer Interrupt Mask Register */ +#define LCDC_OVR2IMR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2IMR) Descriptor Loaded Interrupt Mask Register */ +#define LCDC_OVR2IMR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2IMR) Head Descriptor Loaded Interrupt Mask Register */ +#define LCDC_OVR2IMR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2IMR) End of List Interrupt Mask Register */ +#define LCDC_OVR2IMR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2IMR) Overflow Interrupt Mask Register */ +/* -------- LCDC_OVR2ISR : (LCDC Offset: 0x00000258) Overlay 2 Interrupt status Register -------- */ +#define LCDC_OVR2ISR_DMA (0x1u << 2) /**< \brief (LCDC_OVR2ISR) End of DMA Transfer */ +#define LCDC_OVR2ISR_DSCR (0x1u << 3) /**< \brief (LCDC_OVR2ISR) DMA Descriptor Loaded */ +#define LCDC_OVR2ISR_ADD (0x1u << 4) /**< \brief (LCDC_OVR2ISR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_OVR2ISR_DONE (0x1u << 5) /**< \brief (LCDC_OVR2ISR) End Of List Interrupt Disable Register */ +#define LCDC_OVR2ISR_OVR (0x1u << 6) /**< \brief (LCDC_OVR2ISR) Overflow Detected */ +/* -------- LCDC_OVR2HEAD : (LCDC Offset: 0x0000025C) Overlay 2 DMA Head Register -------- */ +#define LCDC_OVR2HEAD_HEAD_Pos 2 +#define LCDC_OVR2HEAD_HEAD_Msk (0x3fffffffu << LCDC_OVR2HEAD_HEAD_Pos) /**< \brief (LCDC_OVR2HEAD) DMA Head Pointer */ +#define LCDC_OVR2HEAD_HEAD(value) ((LCDC_OVR2HEAD_HEAD_Msk & ((value) << LCDC_OVR2HEAD_HEAD_Pos))) +/* -------- LCDC_OVR2ADDR : (LCDC Offset: 0x00000260) Overlay 2 DMA Address Register -------- */ +#define LCDC_OVR2ADDR_ADDR_Pos 0 +#define LCDC_OVR2ADDR_ADDR_Msk (0xffffffffu << LCDC_OVR2ADDR_ADDR_Pos) /**< \brief (LCDC_OVR2ADDR) DMA Transfer Overlay 2 Address */ +#define LCDC_OVR2ADDR_ADDR(value) ((LCDC_OVR2ADDR_ADDR_Msk & ((value) << LCDC_OVR2ADDR_ADDR_Pos))) +/* -------- LCDC_OVR2CTRL : (LCDC Offset: 0x00000264) Overlay 2 DMA Control Register -------- */ +#define LCDC_OVR2CTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_OVR2CTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_OVR2CTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_OVR2CTRL) Lookup Table Fetch Enable */ +#define LCDC_OVR2CTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_OVR2CTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_OVR2CTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_OVR2CTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_OVR2CTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_OVR2CTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_OVR2CTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_OVR2CTRL) End of List Interrupt Enable */ +/* -------- LCDC_OVR2NEXT : (LCDC Offset: 0x00000268) Overlay 2 DMA Next Register -------- */ +#define LCDC_OVR2NEXT_NEXT_Pos 0 +#define LCDC_OVR2NEXT_NEXT_Msk (0xffffffffu << LCDC_OVR2NEXT_NEXT_Pos) /**< \brief (LCDC_OVR2NEXT) DMA Descriptor Next Address */ +#define LCDC_OVR2NEXT_NEXT(value) ((LCDC_OVR2NEXT_NEXT_Msk & ((value) << LCDC_OVR2NEXT_NEXT_Pos))) +/* -------- LCDC_OVR2CFG0 : (LCDC Offset: 0x0000026C) Overlay 2 Configuration 0 Register -------- */ +#define LCDC_OVR2CFG0_BLEN_Pos 4 +#define LCDC_OVR2CFG0_BLEN_Msk (0x3u << LCDC_OVR2CFG0_BLEN_Pos) /**< \brief (LCDC_OVR2CFG0) AHB Burst Length */ +#define LCDC_OVR2CFG0_BLEN_AHB_SINGLE (0x0u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR2CFG0_BLEN_AHB_INCR4 (0x1u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR2CFG0_BLEN_AHB_INCR8 (0x2u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR2CFG0_BLEN_AHB_INCR16 (0x3u << 4) /**< \brief (LCDC_OVR2CFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_OVR2CFG0_DLBO (0x1u << 8) /**< \brief (LCDC_OVR2CFG0) Defined Length Burst Only For Channel Bus Transaction. */ +#define LCDC_OVR2CFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Optimization Disable */ +#define LCDC_OVR2CFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_OVR2CFG0) Hardware Rotation Lock Disable */ +/* -------- LCDC_OVR2CFG1 : (LCDC Offset: 0x00000270) Overlay 2 Configuration 1 Register -------- */ +#define LCDC_OVR2CFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_OVR2CFG1) Color Lookup Table Enable */ +#define LCDC_OVR2CFG1_RGBMODE_Pos 4 +#define LCDC_OVR2CFG1_RGBMODE_Msk (0xfu << LCDC_OVR2CFG1_RGBMODE_Pos) /**< \brief (LCDC_OVR2CFG1) RGB Input Mode Selection */ +#define LCDC_OVR2CFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_OVR2CFG1) 12 bpp RGB 444 */ +#define LCDC_OVR2CFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp ARGB 4444 */ +#define LCDC_OVR2CFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGBA 4444 */ +#define LCDC_OVR2CFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp RGB 565 */ +#define LCDC_OVR2CFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_OVR2CFG1) 16 bpp TRGB 1555 */ +#define LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 */ +#define LCDC_OVR2CFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_OVR2CFG1) 18 bpp RGB 666 PACKED */ +#define LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 */ +#define LCDC_OVR2CFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_OVR2CFG1) 19 bpp TRGB 1666 PACKED */ +#define LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 */ +#define LCDC_OVR2CFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_OVR2CFG1) 24 bpp RGB 888 PACKED */ +#define LCDC_OVR2CFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_OVR2CFG1) 25 bpp TRGB 1888 */ +#define LCDC_OVR2CFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp ARGB 8888 */ +#define LCDC_OVR2CFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_OVR2CFG1) 32 bpp RGBA 8888 */ +#define LCDC_OVR2CFG1_CLUTMODE_Pos 8 +#define LCDC_OVR2CFG1_CLUTMODE_Msk (0x3u << LCDC_OVR2CFG1_CLUTMODE_Pos) /**< \brief (LCDC_OVR2CFG1) Color Lookup table input mode selection */ +#define LCDC_OVR2CFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 1 bit per pixel */ +#define LCDC_OVR2CFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 2 bits per pixel */ +#define LCDC_OVR2CFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 4 bits per pixel */ +#define LCDC_OVR2CFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_OVR2CFG1) color lookup table mode set to 8 bits per pixel */ +/* -------- LCDC_OVR2CFG2 : (LCDC Offset: 0x00000274) Overlay 2 Configuration 2 Register -------- */ +#define LCDC_OVR2CFG2_XPOS_Pos 0 +#define LCDC_OVR2CFG2_XPOS_Msk (0x7ffu << LCDC_OVR2CFG2_XPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Horizontal Window Position */ +#define LCDC_OVR2CFG2_XPOS(value) ((LCDC_OVR2CFG2_XPOS_Msk & ((value) << LCDC_OVR2CFG2_XPOS_Pos))) +#define LCDC_OVR2CFG2_YPOS_Pos 16 +#define LCDC_OVR2CFG2_YPOS_Msk (0x7ffu << LCDC_OVR2CFG2_YPOS_Pos) /**< \brief (LCDC_OVR2CFG2) Vertical Window Position */ +#define LCDC_OVR2CFG2_YPOS(value) ((LCDC_OVR2CFG2_YPOS_Msk & ((value) << LCDC_OVR2CFG2_YPOS_Pos))) +/* -------- LCDC_OVR2CFG3 : (LCDC Offset: 0x00000278) Overlay 2 Configuration 3 Register -------- */ +#define LCDC_OVR2CFG3_XSIZE_Pos 0 +#define LCDC_OVR2CFG3_XSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_XSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Horizontal Window Size */ +#define LCDC_OVR2CFG3_XSIZE(value) ((LCDC_OVR2CFG3_XSIZE_Msk & ((value) << LCDC_OVR2CFG3_XSIZE_Pos))) +#define LCDC_OVR2CFG3_YSIZE_Pos 16 +#define LCDC_OVR2CFG3_YSIZE_Msk (0x7ffu << LCDC_OVR2CFG3_YSIZE_Pos) /**< \brief (LCDC_OVR2CFG3) Vertical Window Size */ +#define LCDC_OVR2CFG3_YSIZE(value) ((LCDC_OVR2CFG3_YSIZE_Msk & ((value) << LCDC_OVR2CFG3_YSIZE_Pos))) +/* -------- LCDC_OVR2CFG4 : (LCDC Offset: 0x0000027C) Overlay 2 Configuration 4 Register -------- */ +#define LCDC_OVR2CFG4_XSTRIDE_Pos 0 +#define LCDC_OVR2CFG4_XSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG4_XSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG4) Horizontal Stride */ +#define LCDC_OVR2CFG4_XSTRIDE(value) ((LCDC_OVR2CFG4_XSTRIDE_Msk & ((value) << LCDC_OVR2CFG4_XSTRIDE_Pos))) +/* -------- LCDC_OVR2CFG5 : (LCDC Offset: 0x00000280) Overlay 2 Configuration 5 Register -------- */ +#define LCDC_OVR2CFG5_PSTRIDE_Pos 0 +#define LCDC_OVR2CFG5_PSTRIDE_Msk (0xffffffffu << LCDC_OVR2CFG5_PSTRIDE_Pos) /**< \brief (LCDC_OVR2CFG5) Pixel Stride */ +#define LCDC_OVR2CFG5_PSTRIDE(value) ((LCDC_OVR2CFG5_PSTRIDE_Msk & ((value) << LCDC_OVR2CFG5_PSTRIDE_Pos))) +/* -------- LCDC_OVR2CFG6 : (LCDC Offset: 0x00000284) Overlay 2 Configuration 6 Register -------- */ +#define LCDC_OVR2CFG6_BDEF_Pos 0 +#define LCDC_OVR2CFG6_BDEF_Msk (0xffu << LCDC_OVR2CFG6_BDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Blue Default */ +#define LCDC_OVR2CFG6_BDEF(value) ((LCDC_OVR2CFG6_BDEF_Msk & ((value) << LCDC_OVR2CFG6_BDEF_Pos))) +#define LCDC_OVR2CFG6_GDEF_Pos 8 +#define LCDC_OVR2CFG6_GDEF_Msk (0xffu << LCDC_OVR2CFG6_GDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Green Default */ +#define LCDC_OVR2CFG6_GDEF(value) ((LCDC_OVR2CFG6_GDEF_Msk & ((value) << LCDC_OVR2CFG6_GDEF_Pos))) +#define LCDC_OVR2CFG6_RDEF_Pos 16 +#define LCDC_OVR2CFG6_RDEF_Msk (0xffu << LCDC_OVR2CFG6_RDEF_Pos) /**< \brief (LCDC_OVR2CFG6) Red Default */ +#define LCDC_OVR2CFG6_RDEF(value) ((LCDC_OVR2CFG6_RDEF_Msk & ((value) << LCDC_OVR2CFG6_RDEF_Pos))) +/* -------- LCDC_OVR2CFG7 : (LCDC Offset: 0x00000288) Overlay 2 Configuration 7 Register -------- */ +#define LCDC_OVR2CFG7_BKEY_Pos 0 +#define LCDC_OVR2CFG7_BKEY_Msk (0xffu << LCDC_OVR2CFG7_BKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Blue Color Component Chroma Key */ +#define LCDC_OVR2CFG7_BKEY(value) ((LCDC_OVR2CFG7_BKEY_Msk & ((value) << LCDC_OVR2CFG7_BKEY_Pos))) +#define LCDC_OVR2CFG7_GKEY_Pos 8 +#define LCDC_OVR2CFG7_GKEY_Msk (0xffu << LCDC_OVR2CFG7_GKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Green Color Component Chroma Key */ +#define LCDC_OVR2CFG7_GKEY(value) ((LCDC_OVR2CFG7_GKEY_Msk & ((value) << LCDC_OVR2CFG7_GKEY_Pos))) +#define LCDC_OVR2CFG7_RKEY_Pos 16 +#define LCDC_OVR2CFG7_RKEY_Msk (0xffu << LCDC_OVR2CFG7_RKEY_Pos) /**< \brief (LCDC_OVR2CFG7) Red Color Component Chroma Key */ +#define LCDC_OVR2CFG7_RKEY(value) ((LCDC_OVR2CFG7_RKEY_Msk & ((value) << LCDC_OVR2CFG7_RKEY_Pos))) +/* -------- LCDC_OVR2CFG8 : (LCDC Offset: 0x0000028C) Overlay 2 Configuration 8 Register -------- */ +#define LCDC_OVR2CFG8_BMASK_Pos 0 +#define LCDC_OVR2CFG8_BMASK_Msk (0xffu << LCDC_OVR2CFG8_BMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Blue Color Component Chroma Key Mask */ +#define LCDC_OVR2CFG8_BMASK(value) ((LCDC_OVR2CFG8_BMASK_Msk & ((value) << LCDC_OVR2CFG8_BMASK_Pos))) +#define LCDC_OVR2CFG8_GMASK_Pos 8 +#define LCDC_OVR2CFG8_GMASK_Msk (0xffu << LCDC_OVR2CFG8_GMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Green Color Component Chroma Key Mask */ +#define LCDC_OVR2CFG8_GMASK(value) ((LCDC_OVR2CFG8_GMASK_Msk & ((value) << LCDC_OVR2CFG8_GMASK_Pos))) +#define LCDC_OVR2CFG8_RMASK_Pos 16 +#define LCDC_OVR2CFG8_RMASK_Msk (0xffu << LCDC_OVR2CFG8_RMASK_Pos) /**< \brief (LCDC_OVR2CFG8) Red Color Component Chroma Key Mask */ +#define LCDC_OVR2CFG8_RMASK(value) ((LCDC_OVR2CFG8_RMASK_Msk & ((value) << LCDC_OVR2CFG8_RMASK_Pos))) +/* -------- LCDC_OVR2CFG9 : (LCDC Offset: 0x00000290) Overlay 2 Configuration 9 Register -------- */ +#define LCDC_OVR2CFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_OVR2CFG9) Blender Chroma Key Enable */ +#define LCDC_OVR2CFG9_INV (0x1u << 1) /**< \brief (LCDC_OVR2CFG9) Blender Inverted Blender Output Enable */ +#define LCDC_OVR2CFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_OVR2CFG9) Blender Iterated Color Enable */ +#define LCDC_OVR2CFG9_ITER (0x1u << 3) /**< \brief (LCDC_OVR2CFG9) Blender Use Iterated Color */ +#define LCDC_OVR2CFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_OVR2CFG9) Blender Reverse Alpha */ +#define LCDC_OVR2CFG9_GAEN (0x1u << 5) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha Enable */ +#define LCDC_OVR2CFG9_LAEN (0x1u << 6) /**< \brief (LCDC_OVR2CFG9) Blender Local Alpha Enable */ +#define LCDC_OVR2CFG9_OVR (0x1u << 7) /**< \brief (LCDC_OVR2CFG9) Blender Overlay Layer Enable */ +#define LCDC_OVR2CFG9_DMA (0x1u << 8) /**< \brief (LCDC_OVR2CFG9) Blender DMA Layer Enable */ +#define LCDC_OVR2CFG9_REP (0x1u << 9) /**< \brief (LCDC_OVR2CFG9) Use Replication logic to expand RGB color to 24 bits */ +#define LCDC_OVR2CFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_OVR2CFG9) Destination Chroma Keying */ +#define LCDC_OVR2CFG9_GA_Pos 16 +#define LCDC_OVR2CFG9_GA_Msk (0xffu << LCDC_OVR2CFG9_GA_Pos) /**< \brief (LCDC_OVR2CFG9) Blender Global Alpha */ +#define LCDC_OVR2CFG9_GA(value) ((LCDC_OVR2CFG9_GA_Msk & ((value) << LCDC_OVR2CFG9_GA_Pos))) +/* -------- LCDC_HEOCHER : (LCDC Offset: 0x00000340) High-End Overlay Channel Enable Register -------- */ +#define LCDC_HEOCHER_CHEN (0x1u << 0) /**< \brief (LCDC_HEOCHER) Channel Enable Register */ +#define LCDC_HEOCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_HEOCHER) Update Overlay Attributes Enable Register */ +#define LCDC_HEOCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_HEOCHER) Add Head Pointer Enable Register */ +/* -------- LCDC_HEOCHDR : (LCDC Offset: 0x00000344) High-End Overlay Channel Disable Register -------- */ +#define LCDC_HEOCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_HEOCHDR) Channel Disable Register */ +#define LCDC_HEOCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_HEOCHDR) Channel Reset Register */ +/* -------- LCDC_HEOCHSR : (LCDC Offset: 0x00000348) High-End Overlay Channel Status Register -------- */ +#define LCDC_HEOCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_HEOCHSR) Channel Status Register */ +#define LCDC_HEOCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_HEOCHSR) Update Overlay Attributes In Progress */ +#define LCDC_HEOCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_HEOCHSR) Add To Queue Pending Register */ +/* -------- LCDC_HEOIER : (LCDC Offset: 0x0000034C) High-End Overlay Interrupt Enable Register -------- */ +#define LCDC_HEOIER_DMA (0x1u << 2) /**< \brief (LCDC_HEOIER) End of DMA Transfer Interrupt Enable Register */ +#define LCDC_HEOIER_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIER) Descriptor Loaded Interrupt Enable Register */ +#define LCDC_HEOIER_ADD (0x1u << 4) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded Interrupt Enable Register */ +#define LCDC_HEOIER_DONE (0x1u << 5) /**< \brief (LCDC_HEOIER) End of List Interrupt Enable Register */ +#define LCDC_HEOIER_OVR (0x1u << 6) /**< \brief (LCDC_HEOIER) Overflow Interrupt Enable Register */ +#define LCDC_HEOIER_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIER) End of DMA Transfer for U or UV Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIER) Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_UADD (0x1u << 12) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIER) End of List for U or UV Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIER) Overflow for U or UV Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIER) End of DMA for V Chrominance Transfer Interrupt Enable Register */ +#define LCDC_HEOIER_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIER) Descriptor Loaded for V Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_VADD (0x1u << 20) /**< \brief (LCDC_HEOIER) Head Descriptor Loaded for V Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIER) End of List for V Chrominance Interrupt Enable Register */ +#define LCDC_HEOIER_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIER) Overflow for V Chrominance Interrupt Enable Register */ +/* -------- LCDC_HEOIDR : (LCDC Offset: 0x00000350) High-End Overlay Interrupt Disable Register -------- */ +#define LCDC_HEOIDR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIDR) End of DMA Transfer Interrupt Disable Register */ +#define LCDC_HEOIDR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIDR) Descriptor Loaded Interrupt Disable Register */ +#define LCDC_HEOIDR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_HEOIDR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIDR) End of List Interrupt Disable Register */ +#define LCDC_HEOIDR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIDR) Overflow Interrupt Disable Register */ +#define LCDC_HEOIDR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIDR) End of List Interrupt for U or UV Chrominance Component Disable Register */ +#define LCDC_HEOIDR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIDR) Overflow Interrupt for U or UV Chrominance Component Disable Register */ +#define LCDC_HEOIDR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIDR) End of DMA Transfer for V Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIDR) Descriptor Loaded for V Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIDR) Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIDR) End of List for V Chrominance Component Interrupt Disable Register */ +#define LCDC_HEOIDR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIDR) Overflow for V Chrominance Component Interrupt Disable Register */ +/* -------- LCDC_HEOIMR : (LCDC Offset: 0x00000354) High-End Overlay Interrupt Mask Register -------- */ +#define LCDC_HEOIMR_DMA (0x1u << 2) /**< \brief (LCDC_HEOIMR) End of DMA Transfer Interrupt Mask Register */ +#define LCDC_HEOIMR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOIMR) Descriptor Loaded Interrupt Mask Register */ +#define LCDC_HEOIMR_ADD (0x1u << 4) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded Interrupt Mask Register */ +#define LCDC_HEOIMR_DONE (0x1u << 5) /**< \brief (LCDC_HEOIMR) End of List Interrupt Mask Register */ +#define LCDC_HEOIMR_OVR (0x1u << 6) /**< \brief (LCDC_HEOIMR) Overflow Interrupt Mask Register */ +#define LCDC_HEOIMR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register */ +#define LCDC_HEOIMR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register */ +#define LCDC_HEOIMR_UADD (0x1u << 12) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for U or UV Chrominance Component Mask Register */ +#define LCDC_HEOIMR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOIMR) End of List for U or UV Chrominance Component Mask Register */ +#define LCDC_HEOIMR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOIMR) Overflow for U Chrominance Interrupt Mask Register */ +#define LCDC_HEOIMR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOIMR) End of DMA Transfer for V Chrominance Component Interrupt Mask Register */ +#define LCDC_HEOIMR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOIMR) Descriptor Loaded for V Chrominance Component Interrupt Mask Register */ +#define LCDC_HEOIMR_VADD (0x1u << 20) /**< \brief (LCDC_HEOIMR) Head Descriptor Loaded for V Chrominance Component Mask Register */ +#define LCDC_HEOIMR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOIMR) End of List for V Chrominance Component Mask Register */ +#define LCDC_HEOIMR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOIMR) Overflow for V Chrominance Interrupt Mask Register */ +/* -------- LCDC_HEOISR : (LCDC Offset: 0x00000358) High-End Overlay Interrupt Status Register -------- */ +#define LCDC_HEOISR_DMA (0x1u << 2) /**< \brief (LCDC_HEOISR) End of DMA Transfer */ +#define LCDC_HEOISR_DSCR (0x1u << 3) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded */ +#define LCDC_HEOISR_ADD (0x1u << 4) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded */ +#define LCDC_HEOISR_DONE (0x1u << 5) /**< \brief (LCDC_HEOISR) End of List Detected */ +#define LCDC_HEOISR_OVR (0x1u << 6) /**< \brief (LCDC_HEOISR) Overflow Detected */ +#define LCDC_HEOISR_UDMA (0x1u << 10) /**< \brief (LCDC_HEOISR) End of DMA Transfer for U component */ +#define LCDC_HEOISR_UDSCR (0x1u << 11) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for U component */ +#define LCDC_HEOISR_UADD (0x1u << 12) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for U component */ +#define LCDC_HEOISR_UDONE (0x1u << 13) /**< \brief (LCDC_HEOISR) End of List Detected for U component */ +#define LCDC_HEOISR_UOVR (0x1u << 14) /**< \brief (LCDC_HEOISR) Overflow Detected for U component */ +#define LCDC_HEOISR_VDMA (0x1u << 18) /**< \brief (LCDC_HEOISR) End of DMA Transfer for V component */ +#define LCDC_HEOISR_VDSCR (0x1u << 19) /**< \brief (LCDC_HEOISR) DMA Descriptor Loaded for V component */ +#define LCDC_HEOISR_VADD (0x1u << 20) /**< \brief (LCDC_HEOISR) Head Descriptor Loaded for V component */ +#define LCDC_HEOISR_VDONE (0x1u << 21) /**< \brief (LCDC_HEOISR) End of List Detected for V component */ +#define LCDC_HEOISR_VOVR (0x1u << 22) /**< \brief (LCDC_HEOISR) Overflow Detected for V component */ +/* -------- LCDC_HEOHEAD : (LCDC Offset: 0x0000035C) High-End Overlay DMA Head Register -------- */ +#define LCDC_HEOHEAD_HEAD_Pos 2 +#define LCDC_HEOHEAD_HEAD_Msk (0x3fffffffu << LCDC_HEOHEAD_HEAD_Pos) /**< \brief (LCDC_HEOHEAD) DMA Head Pointer */ +#define LCDC_HEOHEAD_HEAD(value) ((LCDC_HEOHEAD_HEAD_Msk & ((value) << LCDC_HEOHEAD_HEAD_Pos))) +/* -------- LCDC_HEOADDR : (LCDC Offset: 0x00000360) High-End Overlay DMA Address Register -------- */ +#define LCDC_HEOADDR_ADDR_Pos 0 +#define LCDC_HEOADDR_ADDR_Msk (0xffffffffu << LCDC_HEOADDR_ADDR_Pos) /**< \brief (LCDC_HEOADDR) DMA Transfer start Address */ +#define LCDC_HEOADDR_ADDR(value) ((LCDC_HEOADDR_ADDR_Msk & ((value) << LCDC_HEOADDR_ADDR_Pos))) +/* -------- LCDC_HEOCTRL : (LCDC Offset: 0x00000364) High-End Overlay DMA Control Register -------- */ +#define LCDC_HEOCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_HEOCTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_HEOCTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_HEOCTRL) Lookup Table Fetch Enable */ +#define LCDC_HEOCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_HEOCTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_HEOCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOCTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_HEOCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_HEOCTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_HEOCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_HEOCTRL) End of List Interrupt Enable */ +/* -------- LCDC_HEONEXT : (LCDC Offset: 0x00000368) High-End Overlay DMA Next Register -------- */ +#define LCDC_HEONEXT_NEXT_Pos 0 +#define LCDC_HEONEXT_NEXT_Msk (0xffffffffu << LCDC_HEONEXT_NEXT_Pos) /**< \brief (LCDC_HEONEXT) DMA Descriptor Next Address */ +#define LCDC_HEONEXT_NEXT(value) ((LCDC_HEONEXT_NEXT_Msk & ((value) << LCDC_HEONEXT_NEXT_Pos))) +/* -------- LCDC_HEOUHEAD : (LCDC Offset: 0x0000036C) High-End Overlay U DMA Head Register -------- */ +#define LCDC_HEOUHEAD_UHEAD_Pos 0 +#define LCDC_HEOUHEAD_UHEAD_Msk (0xffffffffu << LCDC_HEOUHEAD_UHEAD_Pos) /**< \brief (LCDC_HEOUHEAD) DMA Head Pointer */ +#define LCDC_HEOUHEAD_UHEAD(value) ((LCDC_HEOUHEAD_UHEAD_Msk & ((value) << LCDC_HEOUHEAD_UHEAD_Pos))) +/* -------- LCDC_HEOUADDR : (LCDC Offset: 0x00000370) High-End Overlay U DMA Address Register -------- */ +#define LCDC_HEOUADDR_UADDR_Pos 0 +#define LCDC_HEOUADDR_UADDR_Msk (0xffffffffu << LCDC_HEOUADDR_UADDR_Pos) /**< \brief (LCDC_HEOUADDR) DMA Transfer Start Address for U or UV Chrominance */ +#define LCDC_HEOUADDR_UADDR(value) ((LCDC_HEOUADDR_UADDR_Msk & ((value) << LCDC_HEOUADDR_UADDR_Pos))) +/* -------- LCDC_HEOUCTRL : (LCDC Offset: 0x00000374) High-End Overlay U DMA control Register -------- */ +#define LCDC_HEOUCTRL_UDFETCH (0x1u << 0) /**< \brief (LCDC_HEOUCTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_HEOUCTRL_UDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOUCTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_HEOUCTRL_UDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOUCTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_HEOUCTRL_UADDIEN (0x1u << 4) /**< \brief (LCDC_HEOUCTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_HEOUCTRL_UDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOUCTRL) End of List Interrupt Enable */ +/* -------- LCDC_HEOUNEXT : (LCDC Offset: 0x00000378) High-End Overlay U DMA Next Register -------- */ +#define LCDC_HEOUNEXT_UNEXT_Pos 0 +#define LCDC_HEOUNEXT_UNEXT_Msk (0xffffffffu << LCDC_HEOUNEXT_UNEXT_Pos) /**< \brief (LCDC_HEOUNEXT) DMA Descriptor Next Address */ +#define LCDC_HEOUNEXT_UNEXT(value) ((LCDC_HEOUNEXT_UNEXT_Msk & ((value) << LCDC_HEOUNEXT_UNEXT_Pos))) +/* -------- LCDC_HEOVHEAD : (LCDC Offset: 0x0000037C) High-End Overlay V DMA Head Register -------- */ +#define LCDC_HEOVHEAD_VHEAD_Pos 0 +#define LCDC_HEOVHEAD_VHEAD_Msk (0xffffffffu << LCDC_HEOVHEAD_VHEAD_Pos) /**< \brief (LCDC_HEOVHEAD) DMA Head Pointer */ +#define LCDC_HEOVHEAD_VHEAD(value) ((LCDC_HEOVHEAD_VHEAD_Msk & ((value) << LCDC_HEOVHEAD_VHEAD_Pos))) +/* -------- LCDC_HEOVADDR : (LCDC Offset: 0x00000380) High-End Overlay V DMA Address Register -------- */ +#define LCDC_HEOVADDR_VADDR_Pos 0 +#define LCDC_HEOVADDR_VADDR_Msk (0xffffffffu << LCDC_HEOVADDR_VADDR_Pos) /**< \brief (LCDC_HEOVADDR) DMA Transfer Start Address for V Chrominance */ +#define LCDC_HEOVADDR_VADDR(value) ((LCDC_HEOVADDR_VADDR_Msk & ((value) << LCDC_HEOVADDR_VADDR_Pos))) +/* -------- LCDC_HEOVCTRL : (LCDC Offset: 0x00000384) High-End Overlay V DMA control Register -------- */ +#define LCDC_HEOVCTRL_VDFETCH (0x1u << 0) /**< \brief (LCDC_HEOVCTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_HEOVCTRL_VDMAIEN (0x1u << 2) /**< \brief (LCDC_HEOVCTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_HEOVCTRL_VDSCRIEN (0x1u << 3) /**< \brief (LCDC_HEOVCTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_HEOVCTRL_VADDIEN (0x1u << 4) /**< \brief (LCDC_HEOVCTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_HEOVCTRL_VDONEIEN (0x1u << 5) /**< \brief (LCDC_HEOVCTRL) End of List Interrupt Enable */ +/* -------- LCDC_HEOVNEXT : (LCDC Offset: 0x00000388) High-End Overlay VDMA Next Register -------- */ +#define LCDC_HEOVNEXT_VNEXT_Pos 0 +#define LCDC_HEOVNEXT_VNEXT_Msk (0xffffffffu << LCDC_HEOVNEXT_VNEXT_Pos) /**< \brief (LCDC_HEOVNEXT) DMA Descriptor Next Address */ +#define LCDC_HEOVNEXT_VNEXT(value) ((LCDC_HEOVNEXT_VNEXT_Msk & ((value) << LCDC_HEOVNEXT_VNEXT_Pos))) +/* -------- LCDC_HEOCFG0 : (LCDC Offset: 0x0000038C) High-End Overlay Configuration Register 0 -------- */ +#define LCDC_HEOCFG0_SIF (0x1u << 0) /**< \brief (LCDC_HEOCFG0) Source Interface */ +#define LCDC_HEOCFG0_BLEN_Pos 4 +#define LCDC_HEOCFG0_BLEN_Msk (0x3u << LCDC_HEOCFG0_BLEN_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length */ +#define LCDC_HEOCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLENUV_Pos 6 +#define LCDC_HEOCFG0_BLENUV_Msk (0x3u << LCDC_HEOCFG0_BLENUV_Pos) /**< \brief (LCDC_HEOCFG0) AHB Burst Length for U-V channel */ +#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3u << 6) /**< \brief (LCDC_HEOCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HEOCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_HEOCFG0) Defined Length Burst Only For Channel Bus Transaction. */ +#define LCDC_HEOCFG0_ROTDIS (0x1u << 12) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Optimization Disable */ +#define LCDC_HEOCFG0_LOCKDIS (0x1u << 13) /**< \brief (LCDC_HEOCFG0) Hardware Rotation Lock Disable */ +/* -------- LCDC_HEOCFG1 : (LCDC Offset: 0x00000390) High-End Overlay Configuration Register 1 -------- */ +#define LCDC_HEOCFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_HEOCFG1) Color Lookup Table Enable */ +#define LCDC_HEOCFG1_YUVEN (0x1u << 1) /**< \brief (LCDC_HEOCFG1) YUV Color Space Enable */ +#define LCDC_HEOCFG1_RGBMODE_Pos 4 +#define LCDC_HEOCFG1_RGBMODE_Msk (0xfu << LCDC_HEOCFG1_RGBMODE_Pos) /**< \brief (LCDC_HEOCFG1) RGB input mode selection */ +#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_HEOCFG1) 12 bpp RGB 444 */ +#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp ARGB 4444 */ +#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGBA 4444 */ +#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp RGB 565 */ +#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_HEOCFG1) 16 bpp TRGB 1555 */ +#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 */ +#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_HEOCFG1) 18 bpp RGB 666 PACKED */ +#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 */ +#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_HEOCFG1) 19 bpp TRGB 1666 PACKED */ +#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 */ +#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_HEOCFG1) 24 bpp RGB 888 PACKED */ +#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_HEOCFG1) 25 bpp TRGB 1888 */ +#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp ARGB 8888 */ +#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_HEOCFG1) 32 bpp RGBA 8888 */ +#define LCDC_HEOCFG1_CLUTMODE_Pos 8 +#define LCDC_HEOCFG1_CLUTMODE_Msk (0x3u << LCDC_HEOCFG1_CLUTMODE_Pos) /**< \brief (LCDC_HEOCFG1) Color Lookup table input mode selection */ +#define LCDC_HEOCFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 1 bit per pixel */ +#define LCDC_HEOCFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 2 bits per pixel */ +#define LCDC_HEOCFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 4 bits per pixel */ +#define LCDC_HEOCFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_HEOCFG1) color lookup table mode set to 8 bits per pixel */ +#define LCDC_HEOCFG1_YUVMODE_Pos 12 +#define LCDC_HEOCFG1_YUVMODE_Msk (0xfu << LCDC_HEOCFG1_YUVMODE_Pos) /**< \brief (LCDC_HEOCFG1) YUV input mode selection */ +#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0u << 12) /**< \brief (LCDC_HEOCFG1) 32 bpp AYCbCr 444 */ +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 */ +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 */ +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 */ +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 */ +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Semiplanar 422 YCbCr */ +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6u << 12) /**< \brief (LCDC_HEOCFG1) 16 bpp Planar 422 YCbCr */ +#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Semiplanar 420 YCbCr */ +#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8u << 12) /**< \brief (LCDC_HEOCFG1) 12 bpp Planar 420 YCbCr */ +#define LCDC_HEOCFG1_YUV422ROT (0x1u << 16) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 Rotation */ +#define LCDC_HEOCFG1_YUV422SWP (0x1u << 17) /**< \brief (LCDC_HEOCFG1) YUV 4:2:2 SWAP */ +#define LCDC_HEOCFG1_DSCALEOPT (0x1u << 20) /**< \brief (LCDC_HEOCFG1) Down Scaling Bandwidth Optimization */ +/* -------- LCDC_HEOCFG2 : (LCDC Offset: 0x00000394) High-End Overlay Configuration Register 2 -------- */ +#define LCDC_HEOCFG2_XPOS_Pos 0 +#define LCDC_HEOCFG2_XPOS_Msk (0x7ffu << LCDC_HEOCFG2_XPOS_Pos) /**< \brief (LCDC_HEOCFG2) Horizontal Window Position */ +#define LCDC_HEOCFG2_XPOS(value) ((LCDC_HEOCFG2_XPOS_Msk & ((value) << LCDC_HEOCFG2_XPOS_Pos))) +#define LCDC_HEOCFG2_YPOS_Pos 16 +#define LCDC_HEOCFG2_YPOS_Msk (0x7ffu << LCDC_HEOCFG2_YPOS_Pos) /**< \brief (LCDC_HEOCFG2) Vertical Window Position */ +#define LCDC_HEOCFG2_YPOS(value) ((LCDC_HEOCFG2_YPOS_Msk & ((value) << LCDC_HEOCFG2_YPOS_Pos))) +/* -------- LCDC_HEOCFG3 : (LCDC Offset: 0x00000398) High-End Overlay Configuration Register 3 -------- */ +#define LCDC_HEOCFG3_XSIZE_Pos 0 +#define LCDC_HEOCFG3_XSIZE_Msk (0x7ffu << LCDC_HEOCFG3_XSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Horizontal Window Size */ +#define LCDC_HEOCFG3_XSIZE(value) ((LCDC_HEOCFG3_XSIZE_Msk & ((value) << LCDC_HEOCFG3_XSIZE_Pos))) +#define LCDC_HEOCFG3_YSIZE_Pos 16 +#define LCDC_HEOCFG3_YSIZE_Msk (0x7ffu << LCDC_HEOCFG3_YSIZE_Pos) /**< \brief (LCDC_HEOCFG3) Vertical Window Size */ +#define LCDC_HEOCFG3_YSIZE(value) ((LCDC_HEOCFG3_YSIZE_Msk & ((value) << LCDC_HEOCFG3_YSIZE_Pos))) +/* -------- LCDC_HEOCFG4 : (LCDC Offset: 0x0000039C) High-End Overlay Configuration Register 4 -------- */ +#define LCDC_HEOCFG4_XMEM_SIZE_Pos 0 +#define LCDC_HEOCFG4_XMEM_SIZE_Msk (0x7ffu << LCDC_HEOCFG4_XMEM_SIZE_Pos) /**< \brief (LCDC_HEOCFG4) Horizontal image Size in Memory */ +#define LCDC_HEOCFG4_XMEM_SIZE(value) ((LCDC_HEOCFG4_XMEM_SIZE_Msk & ((value) << LCDC_HEOCFG4_XMEM_SIZE_Pos))) +#define LCDC_HEOCFG4_YMEM_SIZE_Pos 16 +#define LCDC_HEOCFG4_YMEM_SIZE_Msk (0x7ffu << LCDC_HEOCFG4_YMEM_SIZE_Pos) /**< \brief (LCDC_HEOCFG4) Vertical image Size in Memory */ +#define LCDC_HEOCFG4_YMEM_SIZE(value) ((LCDC_HEOCFG4_YMEM_SIZE_Msk & ((value) << LCDC_HEOCFG4_YMEM_SIZE_Pos))) +/* -------- LCDC_HEOCFG5 : (LCDC Offset: 0x000003A0) High-End Overlay Configuration Register 5 -------- */ +#define LCDC_HEOCFG5_XSTRIDE_Pos 0 +#define LCDC_HEOCFG5_XSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG5_XSTRIDE_Pos) /**< \brief (LCDC_HEOCFG5) Horizontal Stride */ +#define LCDC_HEOCFG5_XSTRIDE(value) ((LCDC_HEOCFG5_XSTRIDE_Msk & ((value) << LCDC_HEOCFG5_XSTRIDE_Pos))) +/* -------- LCDC_HEOCFG6 : (LCDC Offset: 0x000003A4) High-End Overlay Configuration Register 6 -------- */ +#define LCDC_HEOCFG6_PSTRIDE_Pos 0 +#define LCDC_HEOCFG6_PSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG6_PSTRIDE_Pos) /**< \brief (LCDC_HEOCFG6) Pixel Stride */ +#define LCDC_HEOCFG6_PSTRIDE(value) ((LCDC_HEOCFG6_PSTRIDE_Msk & ((value) << LCDC_HEOCFG6_PSTRIDE_Pos))) +/* -------- LCDC_HEOCFG7 : (LCDC Offset: 0x000003A8) High-End Overlay Configuration Register 7 -------- */ +#define LCDC_HEOCFG7_UVXSTRIDE_Pos 0 +#define LCDC_HEOCFG7_UVXSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG7_UVXSTRIDE_Pos) /**< \brief (LCDC_HEOCFG7) UV Horizontal Stride */ +#define LCDC_HEOCFG7_UVXSTRIDE(value) ((LCDC_HEOCFG7_UVXSTRIDE_Msk & ((value) << LCDC_HEOCFG7_UVXSTRIDE_Pos))) +/* -------- LCDC_HEOCFG8 : (LCDC Offset: 0x000003AC) High-End Overlay Configuration Register 8 -------- */ +#define LCDC_HEOCFG8_UVPSTRIDE_Pos 0 +#define LCDC_HEOCFG8_UVPSTRIDE_Msk (0xffffffffu << LCDC_HEOCFG8_UVPSTRIDE_Pos) /**< \brief (LCDC_HEOCFG8) UV Pixel Stride */ +#define LCDC_HEOCFG8_UVPSTRIDE(value) ((LCDC_HEOCFG8_UVPSTRIDE_Msk & ((value) << LCDC_HEOCFG8_UVPSTRIDE_Pos))) +/* -------- LCDC_HEOCFG9 : (LCDC Offset: 0x000003B0) High-End Overlay Configuration Register 9 -------- */ +#define LCDC_HEOCFG9_BDEF_Pos 0 +#define LCDC_HEOCFG9_BDEF_Msk (0xffu << LCDC_HEOCFG9_BDEF_Pos) /**< \brief (LCDC_HEOCFG9) Blue Default */ +#define LCDC_HEOCFG9_BDEF(value) ((LCDC_HEOCFG9_BDEF_Msk & ((value) << LCDC_HEOCFG9_BDEF_Pos))) +#define LCDC_HEOCFG9_GDEF_Pos 8 +#define LCDC_HEOCFG9_GDEF_Msk (0xffu << LCDC_HEOCFG9_GDEF_Pos) /**< \brief (LCDC_HEOCFG9) Green Default */ +#define LCDC_HEOCFG9_GDEF(value) ((LCDC_HEOCFG9_GDEF_Msk & ((value) << LCDC_HEOCFG9_GDEF_Pos))) +#define LCDC_HEOCFG9_RDEF_Pos 16 +#define LCDC_HEOCFG9_RDEF_Msk (0xffu << LCDC_HEOCFG9_RDEF_Pos) /**< \brief (LCDC_HEOCFG9) Red Default */ +#define LCDC_HEOCFG9_RDEF(value) ((LCDC_HEOCFG9_RDEF_Msk & ((value) << LCDC_HEOCFG9_RDEF_Pos))) +/* -------- LCDC_HEOCFG10 : (LCDC Offset: 0x000003B4) High-End Overlay Configuration Register 10 -------- */ +#define LCDC_HEOCFG10_BKEY_Pos 0 +#define LCDC_HEOCFG10_BKEY_Msk (0xffu << LCDC_HEOCFG10_BKEY_Pos) /**< \brief (LCDC_HEOCFG10) Blue Color Component Chroma Key */ +#define LCDC_HEOCFG10_BKEY(value) ((LCDC_HEOCFG10_BKEY_Msk & ((value) << LCDC_HEOCFG10_BKEY_Pos))) +#define LCDC_HEOCFG10_GKEY_Pos 8 +#define LCDC_HEOCFG10_GKEY_Msk (0xffu << LCDC_HEOCFG10_GKEY_Pos) /**< \brief (LCDC_HEOCFG10) Green Color Component Chroma Key */ +#define LCDC_HEOCFG10_GKEY(value) ((LCDC_HEOCFG10_GKEY_Msk & ((value) << LCDC_HEOCFG10_GKEY_Pos))) +#define LCDC_HEOCFG10_RKEY_Pos 16 +#define LCDC_HEOCFG10_RKEY_Msk (0xffu << LCDC_HEOCFG10_RKEY_Pos) /**< \brief (LCDC_HEOCFG10) Red Color Component Chroma Key */ +#define LCDC_HEOCFG10_RKEY(value) ((LCDC_HEOCFG10_RKEY_Msk & ((value) << LCDC_HEOCFG10_RKEY_Pos))) +/* -------- LCDC_HEOCFG11 : (LCDC Offset: 0x000003B8) High-End Overlay Configuration Register 11 -------- */ +#define LCDC_HEOCFG11_BMASK_Pos 0 +#define LCDC_HEOCFG11_BMASK_Msk (0xffu << LCDC_HEOCFG11_BMASK_Pos) /**< \brief (LCDC_HEOCFG11) Blue Color Component Chroma Key Mask */ +#define LCDC_HEOCFG11_BMASK(value) ((LCDC_HEOCFG11_BMASK_Msk & ((value) << LCDC_HEOCFG11_BMASK_Pos))) +#define LCDC_HEOCFG11_GMASK_Pos 8 +#define LCDC_HEOCFG11_GMASK_Msk (0xffu << LCDC_HEOCFG11_GMASK_Pos) /**< \brief (LCDC_HEOCFG11) Green Color Component Chroma Key Mask */ +#define LCDC_HEOCFG11_GMASK(value) ((LCDC_HEOCFG11_GMASK_Msk & ((value) << LCDC_HEOCFG11_GMASK_Pos))) +#define LCDC_HEOCFG11_RMASK_Pos 16 +#define LCDC_HEOCFG11_RMASK_Msk (0xffu << LCDC_HEOCFG11_RMASK_Pos) /**< \brief (LCDC_HEOCFG11) Red Color Component Chroma Key Mask */ +#define LCDC_HEOCFG11_RMASK(value) ((LCDC_HEOCFG11_RMASK_Msk & ((value) << LCDC_HEOCFG11_RMASK_Pos))) +/* -------- LCDC_HEOCFG12 : (LCDC Offset: 0x000003BC) High-End Overlay Configuration Register 12 -------- */ +#define LCDC_HEOCFG12_CRKEY (0x1u << 0) /**< \brief (LCDC_HEOCFG12) Blender Chroma Key Enable */ +#define LCDC_HEOCFG12_INV (0x1u << 1) /**< \brief (LCDC_HEOCFG12) Blender Inverted Blender Output Enable */ +#define LCDC_HEOCFG12_ITER2BL (0x1u << 2) /**< \brief (LCDC_HEOCFG12) Blender Iterated Color Enable */ +#define LCDC_HEOCFG12_ITER (0x1u << 3) /**< \brief (LCDC_HEOCFG12) Blender Use Iterated Color */ +#define LCDC_HEOCFG12_REVALPHA (0x1u << 4) /**< \brief (LCDC_HEOCFG12) Blender Reverse Alpha */ +#define LCDC_HEOCFG12_GAEN (0x1u << 5) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha Enable */ +#define LCDC_HEOCFG12_LAEN (0x1u << 6) /**< \brief (LCDC_HEOCFG12) Blender Local Alpha Enable */ +#define LCDC_HEOCFG12_OVR (0x1u << 7) /**< \brief (LCDC_HEOCFG12) Blender Overlay Layer Enable */ +#define LCDC_HEOCFG12_DMA (0x1u << 8) /**< \brief (LCDC_HEOCFG12) Blender DMA Layer Enable */ +#define LCDC_HEOCFG12_REP (0x1u << 9) /**< \brief (LCDC_HEOCFG12) Use Replication logic to expand RGB color to 24 bits */ +#define LCDC_HEOCFG12_DSTKEY (0x1u << 10) /**< \brief (LCDC_HEOCFG12) Destination Chroma Keying */ +#define LCDC_HEOCFG12_VIDPRI (0x1u << 12) /**< \brief (LCDC_HEOCFG12) Video Priority */ +#define LCDC_HEOCFG12_GA_Pos 16 +#define LCDC_HEOCFG12_GA_Msk (0xffu << LCDC_HEOCFG12_GA_Pos) /**< \brief (LCDC_HEOCFG12) Blender Global Alpha */ +#define LCDC_HEOCFG12_GA(value) ((LCDC_HEOCFG12_GA_Msk & ((value) << LCDC_HEOCFG12_GA_Pos))) +/* -------- LCDC_HEOCFG13 : (LCDC Offset: 0x000003C0) High-End Overlay Configuration Register 13 -------- */ +#define LCDC_HEOCFG13_XFACTOR_Pos 0 +#define LCDC_HEOCFG13_XFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_XFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Horizontal Scaling Factor */ +#define LCDC_HEOCFG13_XFACTOR(value) ((LCDC_HEOCFG13_XFACTOR_Msk & ((value) << LCDC_HEOCFG13_XFACTOR_Pos))) +#define LCDC_HEOCFG13_YFACTOR_Pos 16 +#define LCDC_HEOCFG13_YFACTOR_Msk (0x3fffu << LCDC_HEOCFG13_YFACTOR_Pos) /**< \brief (LCDC_HEOCFG13) Vertical Scaling Factor */ +#define LCDC_HEOCFG13_YFACTOR(value) ((LCDC_HEOCFG13_YFACTOR_Msk & ((value) << LCDC_HEOCFG13_YFACTOR_Pos))) +#define LCDC_HEOCFG13_SCALEN (0x1u << 31) /**< \brief (LCDC_HEOCFG13) Hardware Scaler Enable */ +/* -------- LCDC_HEOCFG14 : (LCDC Offset: 0x000003C4) High-End Overlay Configuration Register 14 -------- */ +#define LCDC_HEOCFG14_CSCRY_Pos 0 +#define LCDC_HEOCFG14_CSCRY_Msk (0x3ffu << LCDC_HEOCFG14_CSCRY_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Y coefficient for Red Component 1:2:7 format */ +#define LCDC_HEOCFG14_CSCRY(value) ((LCDC_HEOCFG14_CSCRY_Msk & ((value) << LCDC_HEOCFG14_CSCRY_Pos))) +#define LCDC_HEOCFG14_CSCRU_Pos 10 +#define LCDC_HEOCFG14_CSCRU_Msk (0x3ffu << LCDC_HEOCFG14_CSCRU_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion U coefficient for Red Component 1:2:7 format */ +#define LCDC_HEOCFG14_CSCRU(value) ((LCDC_HEOCFG14_CSCRU_Msk & ((value) << LCDC_HEOCFG14_CSCRU_Pos))) +#define LCDC_HEOCFG14_CSCRV_Pos 20 +#define LCDC_HEOCFG14_CSCRV_Msk (0x3ffu << LCDC_HEOCFG14_CSCRV_Pos) /**< \brief (LCDC_HEOCFG14) Color Space Conversion V coefficient for Red Component 1:2:7 format */ +#define LCDC_HEOCFG14_CSCRV(value) ((LCDC_HEOCFG14_CSCRV_Msk & ((value) << LCDC_HEOCFG14_CSCRV_Pos))) +#define LCDC_HEOCFG14_CSCYOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG14) Color Space Conversion Offset */ +/* -------- LCDC_HEOCFG15 : (LCDC Offset: 0x000003C8) High-End Overlay Configuration Register 15 -------- */ +#define LCDC_HEOCFG15_CSCGY_Pos 0 +#define LCDC_HEOCFG15_CSCGY_Msk (0x3ffu << LCDC_HEOCFG15_CSCGY_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Y coefficient for Green Component 1:2:7 format */ +#define LCDC_HEOCFG15_CSCGY(value) ((LCDC_HEOCFG15_CSCGY_Msk & ((value) << LCDC_HEOCFG15_CSCGY_Pos))) +#define LCDC_HEOCFG15_CSCGU_Pos 10 +#define LCDC_HEOCFG15_CSCGU_Msk (0x3ffu << LCDC_HEOCFG15_CSCGU_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion U coefficient for Green Component 1:2:7 format */ +#define LCDC_HEOCFG15_CSCGU(value) ((LCDC_HEOCFG15_CSCGU_Msk & ((value) << LCDC_HEOCFG15_CSCGU_Pos))) +#define LCDC_HEOCFG15_CSCGV_Pos 20 +#define LCDC_HEOCFG15_CSCGV_Msk (0x3ffu << LCDC_HEOCFG15_CSCGV_Pos) /**< \brief (LCDC_HEOCFG15) Color Space Conversion V coefficient for Green Component 1:2:7 format */ +#define LCDC_HEOCFG15_CSCGV(value) ((LCDC_HEOCFG15_CSCGV_Msk & ((value) << LCDC_HEOCFG15_CSCGV_Pos))) +#define LCDC_HEOCFG15_CSCUOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG15) Color Space Conversion Offset */ +/* -------- LCDC_HEOCFG16 : (LCDC Offset: 0x000003CC) High-End Overlay Configuration Register 16 -------- */ +#define LCDC_HEOCFG16_CSCBY_Pos 0 +#define LCDC_HEOCFG16_CSCBY_Msk (0x3ffu << LCDC_HEOCFG16_CSCBY_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Y coefficient for Blue Component 1:2:7 format */ +#define LCDC_HEOCFG16_CSCBY(value) ((LCDC_HEOCFG16_CSCBY_Msk & ((value) << LCDC_HEOCFG16_CSCBY_Pos))) +#define LCDC_HEOCFG16_CSCBU_Pos 10 +#define LCDC_HEOCFG16_CSCBU_Msk (0x3ffu << LCDC_HEOCFG16_CSCBU_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion U coefficient for Blue Component 1:2:7 format */ +#define LCDC_HEOCFG16_CSCBU(value) ((LCDC_HEOCFG16_CSCBU_Msk & ((value) << LCDC_HEOCFG16_CSCBU_Pos))) +#define LCDC_HEOCFG16_CSCBV_Pos 20 +#define LCDC_HEOCFG16_CSCBV_Msk (0x3ffu << LCDC_HEOCFG16_CSCBV_Pos) /**< \brief (LCDC_HEOCFG16) Color Space Conversion V coefficient for Blue Component 1:2:7 format */ +#define LCDC_HEOCFG16_CSCBV(value) ((LCDC_HEOCFG16_CSCBV_Msk & ((value) << LCDC_HEOCFG16_CSCBV_Pos))) +#define LCDC_HEOCFG16_CSCVOFF (0x1u << 30) /**< \brief (LCDC_HEOCFG16) Color Space Conversion Offset */ +/* -------- LCDC_HEOCFG17 : (LCDC Offset: 0x000003D0) High-End Overlay Configuration Register 17 -------- */ +#define LCDC_HEOCFG17_XPHI0COEFF0_Pos 0 +#define LCDC_HEOCFG17_XPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 0 */ +#define LCDC_HEOCFG17_XPHI0COEFF0(value) ((LCDC_HEOCFG17_XPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF0_Pos))) +#define LCDC_HEOCFG17_XPHI0COEFF1_Pos 8 +#define LCDC_HEOCFG17_XPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 1 */ +#define LCDC_HEOCFG17_XPHI0COEFF1(value) ((LCDC_HEOCFG17_XPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF1_Pos))) +#define LCDC_HEOCFG17_XPHI0COEFF2_Pos 16 +#define LCDC_HEOCFG17_XPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 2 */ +#define LCDC_HEOCFG17_XPHI0COEFF2(value) ((LCDC_HEOCFG17_XPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF2_Pos))) +#define LCDC_HEOCFG17_XPHI0COEFF3_Pos 24 +#define LCDC_HEOCFG17_XPHI0COEFF3_Msk (0xffu << LCDC_HEOCFG17_XPHI0COEFF3_Pos) /**< \brief (LCDC_HEOCFG17) Horizontal Coefficient for phase 0 tap 3 */ +#define LCDC_HEOCFG17_XPHI0COEFF3(value) ((LCDC_HEOCFG17_XPHI0COEFF3_Msk & ((value) << LCDC_HEOCFG17_XPHI0COEFF3_Pos))) +/* -------- LCDC_HEOCFG18 : (LCDC Offset: 0x000003D4) High-End Overlay Configuration Register 18 -------- */ +#define LCDC_HEOCFG18_XPHI0COEFF4_Pos 0 +#define LCDC_HEOCFG18_XPHI0COEFF4_Msk (0xffu << LCDC_HEOCFG18_XPHI0COEFF4_Pos) /**< \brief (LCDC_HEOCFG18) Horizontal Coefficient for phase 0 tap 4 */ +#define LCDC_HEOCFG18_XPHI0COEFF4(value) ((LCDC_HEOCFG18_XPHI0COEFF4_Msk & ((value) << LCDC_HEOCFG18_XPHI0COEFF4_Pos))) +/* -------- LCDC_HEOCFG19 : (LCDC Offset: 0x000003D8) High-End Overlay Configuration Register 19 -------- */ +#define LCDC_HEOCFG19_XPHI1COEFF0_Pos 0 +#define LCDC_HEOCFG19_XPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 0 */ +#define LCDC_HEOCFG19_XPHI1COEFF0(value) ((LCDC_HEOCFG19_XPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF0_Pos))) +#define LCDC_HEOCFG19_XPHI1COEFF1_Pos 8 +#define LCDC_HEOCFG19_XPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 1 */ +#define LCDC_HEOCFG19_XPHI1COEFF1(value) ((LCDC_HEOCFG19_XPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF1_Pos))) +#define LCDC_HEOCFG19_XPHI1COEFF2_Pos 16 +#define LCDC_HEOCFG19_XPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 2 */ +#define LCDC_HEOCFG19_XPHI1COEFF2(value) ((LCDC_HEOCFG19_XPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF2_Pos))) +#define LCDC_HEOCFG19_XPHI1COEFF3_Pos 24 +#define LCDC_HEOCFG19_XPHI1COEFF3_Msk (0xffu << LCDC_HEOCFG19_XPHI1COEFF3_Pos) /**< \brief (LCDC_HEOCFG19) Horizontal Coefficient for phase 1 tap 3 */ +#define LCDC_HEOCFG19_XPHI1COEFF3(value) ((LCDC_HEOCFG19_XPHI1COEFF3_Msk & ((value) << LCDC_HEOCFG19_XPHI1COEFF3_Pos))) +/* -------- LCDC_HEOCFG20 : (LCDC Offset: 0x000003DC) High-End Overlay Configuration Register 20 -------- */ +#define LCDC_HEOCFG20_XPHI1COEFF4_Pos 0 +#define LCDC_HEOCFG20_XPHI1COEFF4_Msk (0xffu << LCDC_HEOCFG20_XPHI1COEFF4_Pos) /**< \brief (LCDC_HEOCFG20) Horizontal Coefficient for phase 1 tap 4 */ +#define LCDC_HEOCFG20_XPHI1COEFF4(value) ((LCDC_HEOCFG20_XPHI1COEFF4_Msk & ((value) << LCDC_HEOCFG20_XPHI1COEFF4_Pos))) +/* -------- LCDC_HEOCFG21 : (LCDC Offset: 0x000003E0) High-End Overlay Configuration Register 21 -------- */ +#define LCDC_HEOCFG21_XPHI2COEFF0_Pos 0 +#define LCDC_HEOCFG21_XPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 0 */ +#define LCDC_HEOCFG21_XPHI2COEFF0(value) ((LCDC_HEOCFG21_XPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF0_Pos))) +#define LCDC_HEOCFG21_XPHI2COEFF1_Pos 8 +#define LCDC_HEOCFG21_XPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 1 */ +#define LCDC_HEOCFG21_XPHI2COEFF1(value) ((LCDC_HEOCFG21_XPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF1_Pos))) +#define LCDC_HEOCFG21_XPHI2COEFF2_Pos 16 +#define LCDC_HEOCFG21_XPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 2 */ +#define LCDC_HEOCFG21_XPHI2COEFF2(value) ((LCDC_HEOCFG21_XPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF2_Pos))) +#define LCDC_HEOCFG21_XPHI2COEFF3_Pos 24 +#define LCDC_HEOCFG21_XPHI2COEFF3_Msk (0xffu << LCDC_HEOCFG21_XPHI2COEFF3_Pos) /**< \brief (LCDC_HEOCFG21) Horizontal Coefficient for phase 2 tap 3 */ +#define LCDC_HEOCFG21_XPHI2COEFF3(value) ((LCDC_HEOCFG21_XPHI2COEFF3_Msk & ((value) << LCDC_HEOCFG21_XPHI2COEFF3_Pos))) +/* -------- LCDC_HEOCFG22 : (LCDC Offset: 0x000003E4) High-End Overlay Configuration Register 22 -------- */ +#define LCDC_HEOCFG22_XPHI2COEFF4_Pos 0 +#define LCDC_HEOCFG22_XPHI2COEFF4_Msk (0xffu << LCDC_HEOCFG22_XPHI2COEFF4_Pos) /**< \brief (LCDC_HEOCFG22) Horizontal Coefficient for phase 2 tap 4 */ +#define LCDC_HEOCFG22_XPHI2COEFF4(value) ((LCDC_HEOCFG22_XPHI2COEFF4_Msk & ((value) << LCDC_HEOCFG22_XPHI2COEFF4_Pos))) +/* -------- LCDC_HEOCFG23 : (LCDC Offset: 0x000003E8) High-End Overlay Configuration Register 23 -------- */ +#define LCDC_HEOCFG23_XPHI3COEFF0_Pos 0 +#define LCDC_HEOCFG23_XPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 0 */ +#define LCDC_HEOCFG23_XPHI3COEFF0(value) ((LCDC_HEOCFG23_XPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF0_Pos))) +#define LCDC_HEOCFG23_XPHI3COEFF1_Pos 8 +#define LCDC_HEOCFG23_XPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 1 */ +#define LCDC_HEOCFG23_XPHI3COEFF1(value) ((LCDC_HEOCFG23_XPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF1_Pos))) +#define LCDC_HEOCFG23_XPHI3COEFF2_Pos 16 +#define LCDC_HEOCFG23_XPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 2 */ +#define LCDC_HEOCFG23_XPHI3COEFF2(value) ((LCDC_HEOCFG23_XPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF2_Pos))) +#define LCDC_HEOCFG23_XPHI3COEFF3_Pos 24 +#define LCDC_HEOCFG23_XPHI3COEFF3_Msk (0xffu << LCDC_HEOCFG23_XPHI3COEFF3_Pos) /**< \brief (LCDC_HEOCFG23) Horizontal Coefficient for phase 3 tap 3 */ +#define LCDC_HEOCFG23_XPHI3COEFF3(value) ((LCDC_HEOCFG23_XPHI3COEFF3_Msk & ((value) << LCDC_HEOCFG23_XPHI3COEFF3_Pos))) +/* -------- LCDC_HEOCFG24 : (LCDC Offset: 0x000003EC) High-End Overlay Configuration Register 24 -------- */ +#define LCDC_HEOCFG24_XPHI3COEFF4_Pos 0 +#define LCDC_HEOCFG24_XPHI3COEFF4_Msk (0xffu << LCDC_HEOCFG24_XPHI3COEFF4_Pos) /**< \brief (LCDC_HEOCFG24) Horizontal Coefficient for phase 3 tap 4 */ +#define LCDC_HEOCFG24_XPHI3COEFF4(value) ((LCDC_HEOCFG24_XPHI3COEFF4_Msk & ((value) << LCDC_HEOCFG24_XPHI3COEFF4_Pos))) +/* -------- LCDC_HEOCFG25 : (LCDC Offset: 0x000003F0) High-End Overlay Configuration Register 25 -------- */ +#define LCDC_HEOCFG25_XPHI4COEFF0_Pos 0 +#define LCDC_HEOCFG25_XPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 0 */ +#define LCDC_HEOCFG25_XPHI4COEFF0(value) ((LCDC_HEOCFG25_XPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF0_Pos))) +#define LCDC_HEOCFG25_XPHI4COEFF1_Pos 8 +#define LCDC_HEOCFG25_XPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 1 */ +#define LCDC_HEOCFG25_XPHI4COEFF1(value) ((LCDC_HEOCFG25_XPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF1_Pos))) +#define LCDC_HEOCFG25_XPHI4COEFF2_Pos 16 +#define LCDC_HEOCFG25_XPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 2 */ +#define LCDC_HEOCFG25_XPHI4COEFF2(value) ((LCDC_HEOCFG25_XPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF2_Pos))) +#define LCDC_HEOCFG25_XPHI4COEFF3_Pos 24 +#define LCDC_HEOCFG25_XPHI4COEFF3_Msk (0xffu << LCDC_HEOCFG25_XPHI4COEFF3_Pos) /**< \brief (LCDC_HEOCFG25) Horizontal Coefficient for phase 4 tap 3 */ +#define LCDC_HEOCFG25_XPHI4COEFF3(value) ((LCDC_HEOCFG25_XPHI4COEFF3_Msk & ((value) << LCDC_HEOCFG25_XPHI4COEFF3_Pos))) +/* -------- LCDC_HEOCFG26 : (LCDC Offset: 0x000003F4) High-End Overlay Configuration Register 26 -------- */ +#define LCDC_HEOCFG26_XPHI4COEFF4_Pos 0 +#define LCDC_HEOCFG26_XPHI4COEFF4_Msk (0xffu << LCDC_HEOCFG26_XPHI4COEFF4_Pos) /**< \brief (LCDC_HEOCFG26) Horizontal Coefficient for phase 4 tap 4 */ +#define LCDC_HEOCFG26_XPHI4COEFF4(value) ((LCDC_HEOCFG26_XPHI4COEFF4_Msk & ((value) << LCDC_HEOCFG26_XPHI4COEFF4_Pos))) +/* -------- LCDC_HEOCFG27 : (LCDC Offset: 0x000003F8) High-End Overlay Configuration Register 27 -------- */ +#define LCDC_HEOCFG27_XPHI5COEFF0_Pos 0 +#define LCDC_HEOCFG27_XPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 0 */ +#define LCDC_HEOCFG27_XPHI5COEFF0(value) ((LCDC_HEOCFG27_XPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF0_Pos))) +#define LCDC_HEOCFG27_XPHI5COEFF1_Pos 8 +#define LCDC_HEOCFG27_XPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 1 */ +#define LCDC_HEOCFG27_XPHI5COEFF1(value) ((LCDC_HEOCFG27_XPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF1_Pos))) +#define LCDC_HEOCFG27_XPHI5COEFF2_Pos 16 +#define LCDC_HEOCFG27_XPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 2 */ +#define LCDC_HEOCFG27_XPHI5COEFF2(value) ((LCDC_HEOCFG27_XPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF2_Pos))) +#define LCDC_HEOCFG27_XPHI5COEFF3_Pos 24 +#define LCDC_HEOCFG27_XPHI5COEFF3_Msk (0xffu << LCDC_HEOCFG27_XPHI5COEFF3_Pos) /**< \brief (LCDC_HEOCFG27) Horizontal Coefficient for phase 5 tap 3 */ +#define LCDC_HEOCFG27_XPHI5COEFF3(value) ((LCDC_HEOCFG27_XPHI5COEFF3_Msk & ((value) << LCDC_HEOCFG27_XPHI5COEFF3_Pos))) +/* -------- LCDC_HEOCFG28 : (LCDC Offset: 0x000003FC) High-End Overlay Configuration Register 28 -------- */ +#define LCDC_HEOCFG28_XPHI5COEFF4_Pos 0 +#define LCDC_HEOCFG28_XPHI5COEFF4_Msk (0xffu << LCDC_HEOCFG28_XPHI5COEFF4_Pos) /**< \brief (LCDC_HEOCFG28) Horizontal Coefficient for phase 5 tap 4 */ +#define LCDC_HEOCFG28_XPHI5COEFF4(value) ((LCDC_HEOCFG28_XPHI5COEFF4_Msk & ((value) << LCDC_HEOCFG28_XPHI5COEFF4_Pos))) +/* -------- LCDC_HEOCFG29 : (LCDC Offset: 0x00000400) High-End Overlay Configuration Register 29 -------- */ +#define LCDC_HEOCFG29_XPHI6COEFF0_Pos 0 +#define LCDC_HEOCFG29_XPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 0 */ +#define LCDC_HEOCFG29_XPHI6COEFF0(value) ((LCDC_HEOCFG29_XPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF0_Pos))) +#define LCDC_HEOCFG29_XPHI6COEFF1_Pos 8 +#define LCDC_HEOCFG29_XPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 1 */ +#define LCDC_HEOCFG29_XPHI6COEFF1(value) ((LCDC_HEOCFG29_XPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF1_Pos))) +#define LCDC_HEOCFG29_XPHI6COEFF2_Pos 16 +#define LCDC_HEOCFG29_XPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 2 */ +#define LCDC_HEOCFG29_XPHI6COEFF2(value) ((LCDC_HEOCFG29_XPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF2_Pos))) +#define LCDC_HEOCFG29_XPHI6COEFF3_Pos 24 +#define LCDC_HEOCFG29_XPHI6COEFF3_Msk (0xffu << LCDC_HEOCFG29_XPHI6COEFF3_Pos) /**< \brief (LCDC_HEOCFG29) Horizontal Coefficient for phase 6 tap 3 */ +#define LCDC_HEOCFG29_XPHI6COEFF3(value) ((LCDC_HEOCFG29_XPHI6COEFF3_Msk & ((value) << LCDC_HEOCFG29_XPHI6COEFF3_Pos))) +/* -------- LCDC_HEOCFG30 : (LCDC Offset: 0x00000404) High-End Overlay Configuration Register 30 -------- */ +#define LCDC_HEOCFG30_XPHI6COEFF4_Pos 0 +#define LCDC_HEOCFG30_XPHI6COEFF4_Msk (0xffu << LCDC_HEOCFG30_XPHI6COEFF4_Pos) /**< \brief (LCDC_HEOCFG30) Horizontal Coefficient for phase 6 tap 4 */ +#define LCDC_HEOCFG30_XPHI6COEFF4(value) ((LCDC_HEOCFG30_XPHI6COEFF4_Msk & ((value) << LCDC_HEOCFG30_XPHI6COEFF4_Pos))) +/* -------- LCDC_HEOCFG31 : (LCDC Offset: 0x00000408) High-End Overlay Configuration Register 31 -------- */ +#define LCDC_HEOCFG31_XPHI7COEFF0_Pos 0 +#define LCDC_HEOCFG31_XPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 0 */ +#define LCDC_HEOCFG31_XPHI7COEFF0(value) ((LCDC_HEOCFG31_XPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF0_Pos))) +#define LCDC_HEOCFG31_XPHI7COEFF1_Pos 8 +#define LCDC_HEOCFG31_XPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 1 */ +#define LCDC_HEOCFG31_XPHI7COEFF1(value) ((LCDC_HEOCFG31_XPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF1_Pos))) +#define LCDC_HEOCFG31_XPHI7COEFF2_Pos 16 +#define LCDC_HEOCFG31_XPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 2 */ +#define LCDC_HEOCFG31_XPHI7COEFF2(value) ((LCDC_HEOCFG31_XPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF2_Pos))) +#define LCDC_HEOCFG31_XPHI7COEFF3_Pos 24 +#define LCDC_HEOCFG31_XPHI7COEFF3_Msk (0xffu << LCDC_HEOCFG31_XPHI7COEFF3_Pos) /**< \brief (LCDC_HEOCFG31) Horizontal Coefficient for phase 7 tap 3 */ +#define LCDC_HEOCFG31_XPHI7COEFF3(value) ((LCDC_HEOCFG31_XPHI7COEFF3_Msk & ((value) << LCDC_HEOCFG31_XPHI7COEFF3_Pos))) +/* -------- LCDC_HEOCFG32 : (LCDC Offset: 0x0000040C) High-End Overlay Configuration Register 32 -------- */ +#define LCDC_HEOCFG32_XPHI7COEFF4_Pos 0 +#define LCDC_HEOCFG32_XPHI7COEFF4_Msk (0xffu << LCDC_HEOCFG32_XPHI7COEFF4_Pos) /**< \brief (LCDC_HEOCFG32) Horizontal Coefficient for phase 7 tap 4 */ +#define LCDC_HEOCFG32_XPHI7COEFF4(value) ((LCDC_HEOCFG32_XPHI7COEFF4_Msk & ((value) << LCDC_HEOCFG32_XPHI7COEFF4_Pos))) +/* -------- LCDC_HEOCFG33 : (LCDC Offset: 0x00000410) High-End Overlay Configuration Register 33 -------- */ +#define LCDC_HEOCFG33_YPHI0COEFF0_Pos 0 +#define LCDC_HEOCFG33_YPHI0COEFF0_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF0_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 0 */ +#define LCDC_HEOCFG33_YPHI0COEFF0(value) ((LCDC_HEOCFG33_YPHI0COEFF0_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF0_Pos))) +#define LCDC_HEOCFG33_YPHI0COEFF1_Pos 8 +#define LCDC_HEOCFG33_YPHI0COEFF1_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF1_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 1 */ +#define LCDC_HEOCFG33_YPHI0COEFF1(value) ((LCDC_HEOCFG33_YPHI0COEFF1_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF1_Pos))) +#define LCDC_HEOCFG33_YPHI0COEFF2_Pos 16 +#define LCDC_HEOCFG33_YPHI0COEFF2_Msk (0xffu << LCDC_HEOCFG33_YPHI0COEFF2_Pos) /**< \brief (LCDC_HEOCFG33) Vertical Coefficient for phase 0 tap 2 */ +#define LCDC_HEOCFG33_YPHI0COEFF2(value) ((LCDC_HEOCFG33_YPHI0COEFF2_Msk & ((value) << LCDC_HEOCFG33_YPHI0COEFF2_Pos))) +/* -------- LCDC_HEOCFG34 : (LCDC Offset: 0x00000414) High-End Overlay Configuration Register 34 -------- */ +#define LCDC_HEOCFG34_YPHI1COEFF0_Pos 0 +#define LCDC_HEOCFG34_YPHI1COEFF0_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF0_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 0 */ +#define LCDC_HEOCFG34_YPHI1COEFF0(value) ((LCDC_HEOCFG34_YPHI1COEFF0_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF0_Pos))) +#define LCDC_HEOCFG34_YPHI1COEFF1_Pos 8 +#define LCDC_HEOCFG34_YPHI1COEFF1_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF1_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 1 */ +#define LCDC_HEOCFG34_YPHI1COEFF1(value) ((LCDC_HEOCFG34_YPHI1COEFF1_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF1_Pos))) +#define LCDC_HEOCFG34_YPHI1COEFF2_Pos 16 +#define LCDC_HEOCFG34_YPHI1COEFF2_Msk (0xffu << LCDC_HEOCFG34_YPHI1COEFF2_Pos) /**< \brief (LCDC_HEOCFG34) Vertical Coefficient for phase 1 tap 2 */ +#define LCDC_HEOCFG34_YPHI1COEFF2(value) ((LCDC_HEOCFG34_YPHI1COEFF2_Msk & ((value) << LCDC_HEOCFG34_YPHI1COEFF2_Pos))) +/* -------- LCDC_HEOCFG35 : (LCDC Offset: 0x00000418) High-End Overlay Configuration Register 35 -------- */ +#define LCDC_HEOCFG35_YPHI2COEFF0_Pos 0 +#define LCDC_HEOCFG35_YPHI2COEFF0_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF0_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 0 */ +#define LCDC_HEOCFG35_YPHI2COEFF0(value) ((LCDC_HEOCFG35_YPHI2COEFF0_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF0_Pos))) +#define LCDC_HEOCFG35_YPHI2COEFF1_Pos 8 +#define LCDC_HEOCFG35_YPHI2COEFF1_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF1_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 1 */ +#define LCDC_HEOCFG35_YPHI2COEFF1(value) ((LCDC_HEOCFG35_YPHI2COEFF1_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF1_Pos))) +#define LCDC_HEOCFG35_YPHI2COEFF2_Pos 16 +#define LCDC_HEOCFG35_YPHI2COEFF2_Msk (0xffu << LCDC_HEOCFG35_YPHI2COEFF2_Pos) /**< \brief (LCDC_HEOCFG35) Vertical Coefficient for phase 2 tap 2 */ +#define LCDC_HEOCFG35_YPHI2COEFF2(value) ((LCDC_HEOCFG35_YPHI2COEFF2_Msk & ((value) << LCDC_HEOCFG35_YPHI2COEFF2_Pos))) +/* -------- LCDC_HEOCFG36 : (LCDC Offset: 0x0000041C) High-End Overlay Configuration Register 36 -------- */ +#define LCDC_HEOCFG36_YPHI3COEFF0_Pos 0 +#define LCDC_HEOCFG36_YPHI3COEFF0_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF0_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 0 */ +#define LCDC_HEOCFG36_YPHI3COEFF0(value) ((LCDC_HEOCFG36_YPHI3COEFF0_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF0_Pos))) +#define LCDC_HEOCFG36_YPHI3COEFF1_Pos 8 +#define LCDC_HEOCFG36_YPHI3COEFF1_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF1_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 1 */ +#define LCDC_HEOCFG36_YPHI3COEFF1(value) ((LCDC_HEOCFG36_YPHI3COEFF1_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF1_Pos))) +#define LCDC_HEOCFG36_YPHI3COEFF2_Pos 16 +#define LCDC_HEOCFG36_YPHI3COEFF2_Msk (0xffu << LCDC_HEOCFG36_YPHI3COEFF2_Pos) /**< \brief (LCDC_HEOCFG36) Vertical Coefficient for phase 3 tap 2 */ +#define LCDC_HEOCFG36_YPHI3COEFF2(value) ((LCDC_HEOCFG36_YPHI3COEFF2_Msk & ((value) << LCDC_HEOCFG36_YPHI3COEFF2_Pos))) +/* -------- LCDC_HEOCFG37 : (LCDC Offset: 0x00000420) High-End Overlay Configuration Register 37 -------- */ +#define LCDC_HEOCFG37_YPHI4COEFF0_Pos 0 +#define LCDC_HEOCFG37_YPHI4COEFF0_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF0_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 0 */ +#define LCDC_HEOCFG37_YPHI4COEFF0(value) ((LCDC_HEOCFG37_YPHI4COEFF0_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF0_Pos))) +#define LCDC_HEOCFG37_YPHI4COEFF1_Pos 8 +#define LCDC_HEOCFG37_YPHI4COEFF1_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF1_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 1 */ +#define LCDC_HEOCFG37_YPHI4COEFF1(value) ((LCDC_HEOCFG37_YPHI4COEFF1_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF1_Pos))) +#define LCDC_HEOCFG37_YPHI4COEFF2_Pos 16 +#define LCDC_HEOCFG37_YPHI4COEFF2_Msk (0xffu << LCDC_HEOCFG37_YPHI4COEFF2_Pos) /**< \brief (LCDC_HEOCFG37) Vertical Coefficient for phase 4 tap 2 */ +#define LCDC_HEOCFG37_YPHI4COEFF2(value) ((LCDC_HEOCFG37_YPHI4COEFF2_Msk & ((value) << LCDC_HEOCFG37_YPHI4COEFF2_Pos))) +/* -------- LCDC_HEOCFG38 : (LCDC Offset: 0x00000424) High-End Overlay Configuration Register 38 -------- */ +#define LCDC_HEOCFG38_YPHI5COEFF0_Pos 0 +#define LCDC_HEOCFG38_YPHI5COEFF0_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF0_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 0 */ +#define LCDC_HEOCFG38_YPHI5COEFF0(value) ((LCDC_HEOCFG38_YPHI5COEFF0_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF0_Pos))) +#define LCDC_HEOCFG38_YPHI5COEFF1_Pos 8 +#define LCDC_HEOCFG38_YPHI5COEFF1_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF1_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 1 */ +#define LCDC_HEOCFG38_YPHI5COEFF1(value) ((LCDC_HEOCFG38_YPHI5COEFF1_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF1_Pos))) +#define LCDC_HEOCFG38_YPHI5COEFF2_Pos 16 +#define LCDC_HEOCFG38_YPHI5COEFF2_Msk (0xffu << LCDC_HEOCFG38_YPHI5COEFF2_Pos) /**< \brief (LCDC_HEOCFG38) Vertical Coefficient for phase 5 tap 2 */ +#define LCDC_HEOCFG38_YPHI5COEFF2(value) ((LCDC_HEOCFG38_YPHI5COEFF2_Msk & ((value) << LCDC_HEOCFG38_YPHI5COEFF2_Pos))) +/* -------- LCDC_HEOCFG39 : (LCDC Offset: 0x00000428) High-End Overlay Configuration Register 39 -------- */ +#define LCDC_HEOCFG39_YPHI6COEFF0_Pos 0 +#define LCDC_HEOCFG39_YPHI6COEFF0_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF0_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 0 */ +#define LCDC_HEOCFG39_YPHI6COEFF0(value) ((LCDC_HEOCFG39_YPHI6COEFF0_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF0_Pos))) +#define LCDC_HEOCFG39_YPHI6COEFF1_Pos 8 +#define LCDC_HEOCFG39_YPHI6COEFF1_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF1_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 1 */ +#define LCDC_HEOCFG39_YPHI6COEFF1(value) ((LCDC_HEOCFG39_YPHI6COEFF1_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF1_Pos))) +#define LCDC_HEOCFG39_YPHI6COEFF2_Pos 16 +#define LCDC_HEOCFG39_YPHI6COEFF2_Msk (0xffu << LCDC_HEOCFG39_YPHI6COEFF2_Pos) /**< \brief (LCDC_HEOCFG39) Vertical Coefficient for phase 6 tap 2 */ +#define LCDC_HEOCFG39_YPHI6COEFF2(value) ((LCDC_HEOCFG39_YPHI6COEFF2_Msk & ((value) << LCDC_HEOCFG39_YPHI6COEFF2_Pos))) +/* -------- LCDC_HEOCFG40 : (LCDC Offset: 0x0000042C) High-End Overlay Configuration Register 40 -------- */ +#define LCDC_HEOCFG40_YPHI7COEFF0_Pos 0 +#define LCDC_HEOCFG40_YPHI7COEFF0_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF0_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 0 */ +#define LCDC_HEOCFG40_YPHI7COEFF0(value) ((LCDC_HEOCFG40_YPHI7COEFF0_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF0_Pos))) +#define LCDC_HEOCFG40_YPHI7COEFF1_Pos 8 +#define LCDC_HEOCFG40_YPHI7COEFF1_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF1_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 1 */ +#define LCDC_HEOCFG40_YPHI7COEFF1(value) ((LCDC_HEOCFG40_YPHI7COEFF1_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF1_Pos))) +#define LCDC_HEOCFG40_YPHI7COEFF2_Pos 16 +#define LCDC_HEOCFG40_YPHI7COEFF2_Msk (0xffu << LCDC_HEOCFG40_YPHI7COEFF2_Pos) /**< \brief (LCDC_HEOCFG40) Vertical Coefficient for phase 7 tap 2 */ +#define LCDC_HEOCFG40_YPHI7COEFF2(value) ((LCDC_HEOCFG40_YPHI7COEFF2_Msk & ((value) << LCDC_HEOCFG40_YPHI7COEFF2_Pos))) +/* -------- LCDC_HEOCFG41 : (LCDC Offset: 0x00000430) High-End Overlay Configuration Register 41 -------- */ +#define LCDC_HEOCFG41_XPHIDEF_Pos 0 +#define LCDC_HEOCFG41_XPHIDEF_Msk (0x7u << LCDC_HEOCFG41_XPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Horizontal Filter Phase Offset */ +#define LCDC_HEOCFG41_XPHIDEF(value) ((LCDC_HEOCFG41_XPHIDEF_Msk & ((value) << LCDC_HEOCFG41_XPHIDEF_Pos))) +#define LCDC_HEOCFG41_YPHIDEF_Pos 16 +#define LCDC_HEOCFG41_YPHIDEF_Msk (0x7u << LCDC_HEOCFG41_YPHIDEF_Pos) /**< \brief (LCDC_HEOCFG41) Vertical Filter Phase Offset */ +#define LCDC_HEOCFG41_YPHIDEF(value) ((LCDC_HEOCFG41_YPHIDEF_Msk & ((value) << LCDC_HEOCFG41_YPHIDEF_Pos))) +/* -------- LCDC_HCRCHER : (LCDC Offset: 0x00000440) Hardware Cursor Channel Enable Register -------- */ +#define LCDC_HCRCHER_CHEN (0x1u << 0) /**< \brief (LCDC_HCRCHER) Channel Enable Register */ +#define LCDC_HCRCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_HCRCHER) Update Overlay Attributes Enable Register */ +#define LCDC_HCRCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_HCRCHER) Add Head Pointer Enable Register */ +/* -------- LCDC_HCRCHDR : (LCDC Offset: 0x00000444) Hardware Cursor Channel disable Register -------- */ +#define LCDC_HCRCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_HCRCHDR) Channel Disable Register */ +#define LCDC_HCRCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_HCRCHDR) Channel Reset Register */ +/* -------- LCDC_HCRCHSR : (LCDC Offset: 0x00000448) Hardware Cursor Channel Status Register -------- */ +#define LCDC_HCRCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_HCRCHSR) Channel Status Register */ +#define LCDC_HCRCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_HCRCHSR) Update Overlay Attributes In Progress */ +#define LCDC_HCRCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_HCRCHSR) Add To Queue Pending Register */ +/* -------- LCDC_HCRIER : (LCDC Offset: 0x0000044C) Hardware Cursor Interrupt Enable Register -------- */ +#define LCDC_HCRIER_DMA (0x1u << 2) /**< \brief (LCDC_HCRIER) End of DMA Transfer Interrupt Enable Register */ +#define LCDC_HCRIER_DSCR (0x1u << 3) /**< \brief (LCDC_HCRIER) Descriptor Loaded Interrupt Enable Register */ +#define LCDC_HCRIER_ADD (0x1u << 4) /**< \brief (LCDC_HCRIER) Head Descriptor Loaded Interrupt Enable Register */ +#define LCDC_HCRIER_DONE (0x1u << 5) /**< \brief (LCDC_HCRIER) End of List Interrupt Enable Register */ +#define LCDC_HCRIER_OVR (0x1u << 6) /**< \brief (LCDC_HCRIER) Overflow Interrupt Enable Register */ +/* -------- LCDC_HCRIDR : (LCDC Offset: 0x00000450) Hardware Cursor Interrupt Disable Register -------- */ +#define LCDC_HCRIDR_DMA (0x1u << 2) /**< \brief (LCDC_HCRIDR) End of DMA Transfer Interrupt Disable Register */ +#define LCDC_HCRIDR_DSCR (0x1u << 3) /**< \brief (LCDC_HCRIDR) Descriptor Loaded Interrupt Disable Register */ +#define LCDC_HCRIDR_ADD (0x1u << 4) /**< \brief (LCDC_HCRIDR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_HCRIDR_DONE (0x1u << 5) /**< \brief (LCDC_HCRIDR) End of List Interrupt Disable Register */ +#define LCDC_HCRIDR_OVR (0x1u << 6) /**< \brief (LCDC_HCRIDR) Overflow Interrupt Disable Register */ +/* -------- LCDC_HCRIMR : (LCDC Offset: 0x00000454) Hardware Cursor Interrupt Mask Register -------- */ +#define LCDC_HCRIMR_DMA (0x1u << 2) /**< \brief (LCDC_HCRIMR) End of DMA Transfer Interrupt Mask Register */ +#define LCDC_HCRIMR_DSCR (0x1u << 3) /**< \brief (LCDC_HCRIMR) Descriptor Loaded Interrupt Mask Register */ +#define LCDC_HCRIMR_ADD (0x1u << 4) /**< \brief (LCDC_HCRIMR) Head Descriptor Loaded Interrupt Mask Register */ +#define LCDC_HCRIMR_DONE (0x1u << 5) /**< \brief (LCDC_HCRIMR) End of List Interrupt Mask Register */ +#define LCDC_HCRIMR_OVR (0x1u << 6) /**< \brief (LCDC_HCRIMR) Overflow Interrupt Mask Register */ +/* -------- LCDC_HCRISR : (LCDC Offset: 0x00000458) Hardware Cursor Interrupt Status Register -------- */ +#define LCDC_HCRISR_DMA (0x1u << 2) /**< \brief (LCDC_HCRISR) End of DMA Transfer */ +#define LCDC_HCRISR_DSCR (0x1u << 3) /**< \brief (LCDC_HCRISR) DMA Descriptor Loaded */ +#define LCDC_HCRISR_ADD (0x1u << 4) /**< \brief (LCDC_HCRISR) Head Descriptor Loaded */ +#define LCDC_HCRISR_DONE (0x1u << 5) /**< \brief (LCDC_HCRISR) End of List Detected */ +#define LCDC_HCRISR_OVR (0x1u << 6) /**< \brief (LCDC_HCRISR) Overflow Detected */ +/* -------- LCDC_HCRHEAD : (LCDC Offset: 0x0000045C) Hardware Cursor DMA Head Register -------- */ +#define LCDC_HCRHEAD_HEAD_Pos 2 +#define LCDC_HCRHEAD_HEAD_Msk (0x3fffffffu << LCDC_HCRHEAD_HEAD_Pos) /**< \brief (LCDC_HCRHEAD) DMA Head Pointer */ +#define LCDC_HCRHEAD_HEAD(value) ((LCDC_HCRHEAD_HEAD_Msk & ((value) << LCDC_HCRHEAD_HEAD_Pos))) +/* -------- LCDC_HCRADDR : (LCDC Offset: 0x00000460) Hardware cursor DMA Address Register -------- */ +#define LCDC_HCRADDR_ADDR_Pos 0 +#define LCDC_HCRADDR_ADDR_Msk (0xffffffffu << LCDC_HCRADDR_ADDR_Pos) /**< \brief (LCDC_HCRADDR) DMA Transfer start address */ +#define LCDC_HCRADDR_ADDR(value) ((LCDC_HCRADDR_ADDR_Msk & ((value) << LCDC_HCRADDR_ADDR_Pos))) +/* -------- LCDC_HCRCTRL : (LCDC Offset: 0x00000464) Hardware Cursor DMA Control Register -------- */ +#define LCDC_HCRCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_HCRCTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_HCRCTRL_LFETCH (0x1u << 1) /**< \brief (LCDC_HCRCTRL) Lookup Table Fetch Enable */ +#define LCDC_HCRCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_HCRCTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_HCRCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_HCRCTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_HCRCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_HCRCTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_HCRCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_HCRCTRL) End of List Interrupt Enable */ +/* -------- LCDC_HCRNEXT : (LCDC Offset: 0x00000468) Hardware Cursor DMA NExt Register -------- */ +#define LCDC_HCRNEXT_NEXT_Pos 0 +#define LCDC_HCRNEXT_NEXT_Msk (0xffffffffu << LCDC_HCRNEXT_NEXT_Pos) /**< \brief (LCDC_HCRNEXT) DMA Descriptor Next Address */ +#define LCDC_HCRNEXT_NEXT(value) ((LCDC_HCRNEXT_NEXT_Msk & ((value) << LCDC_HCRNEXT_NEXT_Pos))) +/* -------- LCDC_HCRCFG0 : (LCDC Offset: 0x0000046C) Hardware Cursor Configuration 0 Register -------- */ +#define LCDC_HCRCFG0_SIF (0x1u << 0) /**< \brief (LCDC_HCRCFG0) Source Interface */ +#define LCDC_HCRCFG0_BLEN_Pos 4 +#define LCDC_HCRCFG0_BLEN_Msk (0x3u << LCDC_HCRCFG0_BLEN_Pos) /**< \brief (LCDC_HCRCFG0) AHB Burst Length */ +#define LCDC_HCRCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HCRCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_HCRCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_HCRCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_HCRCFG0) Defined Length Burst Only for Channel Bus Transaction. */ +/* -------- LCDC_HCRCFG1 : (LCDC Offset: 0x00000470) Hardware Cursor Configuration 1 Register -------- */ +#define LCDC_HCRCFG1_CLUTEN (0x1u << 0) /**< \brief (LCDC_HCRCFG1) Color Lookup Table Enable */ +#define LCDC_HCRCFG1_RGBMODE_Pos 4 +#define LCDC_HCRCFG1_RGBMODE_Msk (0xfu << LCDC_HCRCFG1_RGBMODE_Pos) /**< \brief (LCDC_HCRCFG1) RGB input mode selection */ +#define LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0u << 4) /**< \brief (LCDC_HCRCFG1) 12 bpp RGB 444 */ +#define LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp ARGB 4444 */ +#define LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp RGBA 4444 */ +#define LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp RGB 565 */ +#define LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4u << 4) /**< \brief (LCDC_HCRCFG1) 16 bpp TRGB 1555 */ +#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5u << 4) /**< \brief (LCDC_HCRCFG1) 18 bpp RGB 666 */ +#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666PACKED (0x6u << 4) /**< \brief (LCDC_HCRCFG1) 18 bpp RGB 666 PACKED */ +#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7u << 4) /**< \brief (LCDC_HCRCFG1) 19 bpp TRGB 1666 */ +#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8u << 4) /**< \brief (LCDC_HCRCFG1) 19 bpp TRGB 1666 PACKED */ +#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9u << 4) /**< \brief (LCDC_HCRCFG1) 24 bpp RGB 888 */ +#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xAu << 4) /**< \brief (LCDC_HCRCFG1) 24 bpp RGB 888 PACKED */ +#define LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xBu << 4) /**< \brief (LCDC_HCRCFG1) 25 bpp TRGB 1888 */ +#define LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xCu << 4) /**< \brief (LCDC_HCRCFG1) 32 bpp ARGB 8888 */ +#define LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xDu << 4) /**< \brief (LCDC_HCRCFG1) 32 bpp RGBA 8888 */ +#define LCDC_HCRCFG1_CLUTMODE_Pos 8 +#define LCDC_HCRCFG1_CLUTMODE_Msk (0x3u << LCDC_HCRCFG1_CLUTMODE_Pos) /**< \brief (LCDC_HCRCFG1) Color Lookup table input mode selection */ +#define LCDC_HCRCFG1_CLUTMODE_CLUT_1BPP (0x0u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 1 bit per pixel */ +#define LCDC_HCRCFG1_CLUTMODE_CLUT_2BPP (0x1u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 2 bits per pixel */ +#define LCDC_HCRCFG1_CLUTMODE_CLUT_4BPP (0x2u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 4 bits per pixel */ +#define LCDC_HCRCFG1_CLUTMODE_CLUT_8BPP (0x3u << 8) /**< \brief (LCDC_HCRCFG1) color lookup table mode set to 8 bits per pixel */ +/* -------- LCDC_HCRCFG2 : (LCDC Offset: 0x00000474) Hardware Cursor Configuration 2 Register -------- */ +#define LCDC_HCRCFG2_XPOS_Pos 0 +#define LCDC_HCRCFG2_XPOS_Msk (0x7ffu << LCDC_HCRCFG2_XPOS_Pos) /**< \brief (LCDC_HCRCFG2) Horizontal Window Position */ +#define LCDC_HCRCFG2_XPOS(value) ((LCDC_HCRCFG2_XPOS_Msk & ((value) << LCDC_HCRCFG2_XPOS_Pos))) +#define LCDC_HCRCFG2_YPOS_Pos 16 +#define LCDC_HCRCFG2_YPOS_Msk (0x7ffu << LCDC_HCRCFG2_YPOS_Pos) /**< \brief (LCDC_HCRCFG2) Vertical Window Position */ +#define LCDC_HCRCFG2_YPOS(value) ((LCDC_HCRCFG2_YPOS_Msk & ((value) << LCDC_HCRCFG2_YPOS_Pos))) +/* -------- LCDC_HCRCFG3 : (LCDC Offset: 0x00000478) Hardware Cursor Configuration 3 Register -------- */ +#define LCDC_HCRCFG3_XSIZE_Pos 0 +#define LCDC_HCRCFG3_XSIZE_Msk (0x7ffu << LCDC_HCRCFG3_XSIZE_Pos) /**< \brief (LCDC_HCRCFG3) Horizontal Window Size */ +#define LCDC_HCRCFG3_XSIZE(value) ((LCDC_HCRCFG3_XSIZE_Msk & ((value) << LCDC_HCRCFG3_XSIZE_Pos))) +#define LCDC_HCRCFG3_YSIZE_Pos 16 +#define LCDC_HCRCFG3_YSIZE_Msk (0x7ffu << LCDC_HCRCFG3_YSIZE_Pos) /**< \brief (LCDC_HCRCFG3) Vertical Window Size */ +#define LCDC_HCRCFG3_YSIZE(value) ((LCDC_HCRCFG3_YSIZE_Msk & ((value) << LCDC_HCRCFG3_YSIZE_Pos))) +/* -------- LCDC_HCRCFG4 : (LCDC Offset: 0x0000047C) Hardware Cursor Configuration 4 Register -------- */ +#define LCDC_HCRCFG4_XSTRIDE_Pos 0 +#define LCDC_HCRCFG4_XSTRIDE_Msk (0xffffffffu << LCDC_HCRCFG4_XSTRIDE_Pos) /**< \brief (LCDC_HCRCFG4) Horizontal Stride */ +#define LCDC_HCRCFG4_XSTRIDE(value) ((LCDC_HCRCFG4_XSTRIDE_Msk & ((value) << LCDC_HCRCFG4_XSTRIDE_Pos))) +/* -------- LCDC_HCRCFG6 : (LCDC Offset: 0x00000484) Hardware Cursor Configuration 6 Register -------- */ +#define LCDC_HCRCFG6_BDEF_Pos 0 +#define LCDC_HCRCFG6_BDEF_Msk (0xffu << LCDC_HCRCFG6_BDEF_Pos) /**< \brief (LCDC_HCRCFG6) Blue Default */ +#define LCDC_HCRCFG6_BDEF(value) ((LCDC_HCRCFG6_BDEF_Msk & ((value) << LCDC_HCRCFG6_BDEF_Pos))) +#define LCDC_HCRCFG6_GDEF_Pos 8 +#define LCDC_HCRCFG6_GDEF_Msk (0xffu << LCDC_HCRCFG6_GDEF_Pos) /**< \brief (LCDC_HCRCFG6) Green Default */ +#define LCDC_HCRCFG6_GDEF(value) ((LCDC_HCRCFG6_GDEF_Msk & ((value) << LCDC_HCRCFG6_GDEF_Pos))) +#define LCDC_HCRCFG6_RDEF_Pos 16 +#define LCDC_HCRCFG6_RDEF_Msk (0xffu << LCDC_HCRCFG6_RDEF_Pos) /**< \brief (LCDC_HCRCFG6) Red Default */ +#define LCDC_HCRCFG6_RDEF(value) ((LCDC_HCRCFG6_RDEF_Msk & ((value) << LCDC_HCRCFG6_RDEF_Pos))) +/* -------- LCDC_HCRCFG7 : (LCDC Offset: 0x00000488) Hardware Cursor Configuration 7 Register -------- */ +#define LCDC_HCRCFG7_BKEY_Pos 0 +#define LCDC_HCRCFG7_BKEY_Msk (0xffu << LCDC_HCRCFG7_BKEY_Pos) /**< \brief (LCDC_HCRCFG7) Blue Color Component Chroma Key */ +#define LCDC_HCRCFG7_BKEY(value) ((LCDC_HCRCFG7_BKEY_Msk & ((value) << LCDC_HCRCFG7_BKEY_Pos))) +#define LCDC_HCRCFG7_GKEY_Pos 8 +#define LCDC_HCRCFG7_GKEY_Msk (0xffu << LCDC_HCRCFG7_GKEY_Pos) /**< \brief (LCDC_HCRCFG7) Green Color Component Chroma Key */ +#define LCDC_HCRCFG7_GKEY(value) ((LCDC_HCRCFG7_GKEY_Msk & ((value) << LCDC_HCRCFG7_GKEY_Pos))) +#define LCDC_HCRCFG7_RKEY_Pos 16 +#define LCDC_HCRCFG7_RKEY_Msk (0xffu << LCDC_HCRCFG7_RKEY_Pos) /**< \brief (LCDC_HCRCFG7) Red Color Component Chroma Key */ +#define LCDC_HCRCFG7_RKEY(value) ((LCDC_HCRCFG7_RKEY_Msk & ((value) << LCDC_HCRCFG7_RKEY_Pos))) +/* -------- LCDC_HCRCFG8 : (LCDC Offset: 0x0000048C) Hardware Cursor Configuration 8 Register -------- */ +#define LCDC_HCRCFG8_BMASK_Pos 0 +#define LCDC_HCRCFG8_BMASK_Msk (0xffu << LCDC_HCRCFG8_BMASK_Pos) /**< \brief (LCDC_HCRCFG8) Blue Color Component Chroma Key Mask */ +#define LCDC_HCRCFG8_BMASK(value) ((LCDC_HCRCFG8_BMASK_Msk & ((value) << LCDC_HCRCFG8_BMASK_Pos))) +#define LCDC_HCRCFG8_GMASK_Pos 8 +#define LCDC_HCRCFG8_GMASK_Msk (0xffu << LCDC_HCRCFG8_GMASK_Pos) /**< \brief (LCDC_HCRCFG8) Green Color Component Chroma Key Mask */ +#define LCDC_HCRCFG8_GMASK(value) ((LCDC_HCRCFG8_GMASK_Msk & ((value) << LCDC_HCRCFG8_GMASK_Pos))) +#define LCDC_HCRCFG8_RMASK_Pos 16 +#define LCDC_HCRCFG8_RMASK_Msk (0xffu << LCDC_HCRCFG8_RMASK_Pos) /**< \brief (LCDC_HCRCFG8) Red Color Component Chroma Key Mask */ +#define LCDC_HCRCFG8_RMASK(value) ((LCDC_HCRCFG8_RMASK_Msk & ((value) << LCDC_HCRCFG8_RMASK_Pos))) +/* -------- LCDC_HCRCFG9 : (LCDC Offset: 0x00000490) Hardware Cursor Configuration 9 Register -------- */ +#define LCDC_HCRCFG9_CRKEY (0x1u << 0) /**< \brief (LCDC_HCRCFG9) Blender Chroma Key Enable */ +#define LCDC_HCRCFG9_INV (0x1u << 1) /**< \brief (LCDC_HCRCFG9) Blender Inverted Blender Output Enable */ +#define LCDC_HCRCFG9_ITER2BL (0x1u << 2) /**< \brief (LCDC_HCRCFG9) Blender Iterated Color Enable */ +#define LCDC_HCRCFG9_ITER (0x1u << 3) /**< \brief (LCDC_HCRCFG9) Blender Use Iterated Color */ +#define LCDC_HCRCFG9_REVALPHA (0x1u << 4) /**< \brief (LCDC_HCRCFG9) Blender Reverse Alpha */ +#define LCDC_HCRCFG9_GAEN (0x1u << 5) /**< \brief (LCDC_HCRCFG9) Blender Global Alpha Enable */ +#define LCDC_HCRCFG9_LAEN (0x1u << 6) /**< \brief (LCDC_HCRCFG9) Blender Local Alpha Enable */ +#define LCDC_HCRCFG9_OVR (0x1u << 7) /**< \brief (LCDC_HCRCFG9) Blender Overlay Layer Enable */ +#define LCDC_HCRCFG9_DMA (0x1u << 8) /**< \brief (LCDC_HCRCFG9) Blender DMA Layer Enable */ +#define LCDC_HCRCFG9_REP (0x1u << 9) /**< \brief (LCDC_HCRCFG9) Use Replication logic to expand RGB color to 24 bits */ +#define LCDC_HCRCFG9_DSTKEY (0x1u << 10) /**< \brief (LCDC_HCRCFG9) Destination Chroma Keying */ +#define LCDC_HCRCFG9_GA_Pos 16 +#define LCDC_HCRCFG9_GA_Msk (0xffu << LCDC_HCRCFG9_GA_Pos) /**< \brief (LCDC_HCRCFG9) Blender Global Alpha */ +#define LCDC_HCRCFG9_GA(value) ((LCDC_HCRCFG9_GA_Msk & ((value) << LCDC_HCRCFG9_GA_Pos))) +/* -------- LCDC_PPCHER : (LCDC Offset: 0x00000540) Post Processing Channel Enable Register -------- */ +#define LCDC_PPCHER_CHEN (0x1u << 0) /**< \brief (LCDC_PPCHER) Channel Enable Register */ +#define LCDC_PPCHER_UPDATEEN (0x1u << 1) /**< \brief (LCDC_PPCHER) Update Overlay Attributes Enable Register */ +#define LCDC_PPCHER_A2QEN (0x1u << 2) /**< \brief (LCDC_PPCHER) Add Head Pointer Enable Register */ +/* -------- LCDC_PPCHDR : (LCDC Offset: 0x00000544) Post Processing Channel Disable Register -------- */ +#define LCDC_PPCHDR_CHDIS (0x1u << 0) /**< \brief (LCDC_PPCHDR) Channel Disable Register */ +#define LCDC_PPCHDR_CHRST (0x1u << 8) /**< \brief (LCDC_PPCHDR) Channel Reset Register */ +/* -------- LCDC_PPCHSR : (LCDC Offset: 0x00000548) Post Processing Channel Status Register -------- */ +#define LCDC_PPCHSR_CHSR (0x1u << 0) /**< \brief (LCDC_PPCHSR) Channel Status Register */ +#define LCDC_PPCHSR_UPDATESR (0x1u << 1) /**< \brief (LCDC_PPCHSR) Update Overlay Attributes In Progress */ +#define LCDC_PPCHSR_A2QSR (0x1u << 2) /**< \brief (LCDC_PPCHSR) Add To Queue Pending Register */ +/* -------- LCDC_PPIER : (LCDC Offset: 0x0000054C) Post Processing Interrupt Enable Register -------- */ +#define LCDC_PPIER_DMA (0x1u << 2) /**< \brief (LCDC_PPIER) End of DMA Transfer Interrupt Enable Register */ +#define LCDC_PPIER_DSCR (0x1u << 3) /**< \brief (LCDC_PPIER) Descriptor Loaded Interrupt Enable Register */ +#define LCDC_PPIER_ADD (0x1u << 4) /**< \brief (LCDC_PPIER) Head Descriptor Loaded Interrupt Enable Register */ +#define LCDC_PPIER_DONE (0x1u << 5) /**< \brief (LCDC_PPIER) End of List Interrupt Enable Register */ +/* -------- LCDC_PPIDR : (LCDC Offset: 0x00000550) Post Processing Interrupt Disable Register -------- */ +#define LCDC_PPIDR_DMA (0x1u << 2) /**< \brief (LCDC_PPIDR) End of DMA Transfer Interrupt Disable Register */ +#define LCDC_PPIDR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIDR) Descriptor Loaded Interrupt Disable Register */ +#define LCDC_PPIDR_ADD (0x1u << 4) /**< \brief (LCDC_PPIDR) Head Descriptor Loaded Interrupt Disable Register */ +#define LCDC_PPIDR_DONE (0x1u << 5) /**< \brief (LCDC_PPIDR) End of List Interrupt Disable Register */ +/* -------- LCDC_PPIMR : (LCDC Offset: 0x00000554) Post Processing Interrupt Mask Register -------- */ +#define LCDC_PPIMR_DMA (0x1u << 2) /**< \brief (LCDC_PPIMR) End of DMA Transfer Interrupt Mask Register */ +#define LCDC_PPIMR_DSCR (0x1u << 3) /**< \brief (LCDC_PPIMR) Descriptor Loaded Interrupt Mask Register */ +#define LCDC_PPIMR_ADD (0x1u << 4) /**< \brief (LCDC_PPIMR) Head Descriptor Loaded Interrupt Mask Register */ +#define LCDC_PPIMR_DONE (0x1u << 5) /**< \brief (LCDC_PPIMR) End of List Interrupt Mask Register */ +/* -------- LCDC_PPISR : (LCDC Offset: 0x00000558) Post Processing Interrupt Status Register -------- */ +#define LCDC_PPISR_DMA (0x1u << 2) /**< \brief (LCDC_PPISR) End of DMA Transfer */ +#define LCDC_PPISR_DSCR (0x1u << 3) /**< \brief (LCDC_PPISR) DMA Descriptor Loaded */ +#define LCDC_PPISR_ADD (0x1u << 4) /**< \brief (LCDC_PPISR) Head Descriptor Loaded */ +#define LCDC_PPISR_DONE (0x1u << 5) /**< \brief (LCDC_PPISR) End Of List Detected */ +/* -------- LCDC_PPHEAD : (LCDC Offset: 0x0000055C) Post Processing Head Register -------- */ +#define LCDC_PPHEAD_HEAD_Pos 2 +#define LCDC_PPHEAD_HEAD_Msk (0x3fffffffu << LCDC_PPHEAD_HEAD_Pos) /**< \brief (LCDC_PPHEAD) DMA Head Pointer */ +#define LCDC_PPHEAD_HEAD(value) ((LCDC_PPHEAD_HEAD_Msk & ((value) << LCDC_PPHEAD_HEAD_Pos))) +/* -------- LCDC_PPADDR : (LCDC Offset: 0x00000560) Post Processing Address Register -------- */ +#define LCDC_PPADDR_ADDR_Pos 0 +#define LCDC_PPADDR_ADDR_Msk (0xffffffffu << LCDC_PPADDR_ADDR_Pos) /**< \brief (LCDC_PPADDR) DMA Transfer start address */ +#define LCDC_PPADDR_ADDR(value) ((LCDC_PPADDR_ADDR_Msk & ((value) << LCDC_PPADDR_ADDR_Pos))) +/* -------- LCDC_PPCTRL : (LCDC Offset: 0x00000564) Post Processing Control Register -------- */ +#define LCDC_PPCTRL_DFETCH (0x1u << 0) /**< \brief (LCDC_PPCTRL) Transfer Descriptor Fetch Enable */ +#define LCDC_PPCTRL_DMAIEN (0x1u << 2) /**< \brief (LCDC_PPCTRL) End of DMA Transfer Interrupt Enable */ +#define LCDC_PPCTRL_DSCRIEN (0x1u << 3) /**< \brief (LCDC_PPCTRL) Descriptor Loaded Interrupt Enable */ +#define LCDC_PPCTRL_ADDIEN (0x1u << 4) /**< \brief (LCDC_PPCTRL) Add Head Descriptor to Queue Interrupt Enable */ +#define LCDC_PPCTRL_DONEIEN (0x1u << 5) /**< \brief (LCDC_PPCTRL) End of List Interrupt Enable */ +/* -------- LCDC_PPNEXT : (LCDC Offset: 0x00000568) Post Processing Next Register -------- */ +#define LCDC_PPNEXT_NEXT_Pos 0 +#define LCDC_PPNEXT_NEXT_Msk (0xffffffffu << LCDC_PPNEXT_NEXT_Pos) /**< \brief (LCDC_PPNEXT) DMA Descriptor Next Address */ +#define LCDC_PPNEXT_NEXT(value) ((LCDC_PPNEXT_NEXT_Msk & ((value) << LCDC_PPNEXT_NEXT_Pos))) +/* -------- LCDC_PPCFG0 : (LCDC Offset: 0x0000056C) Post Processing Configuration Register 0 -------- */ +#define LCDC_PPCFG0_SIF (0x1u << 0) /**< \brief (LCDC_PPCFG0) Source Interface */ +#define LCDC_PPCFG0_BLEN_Pos 4 +#define LCDC_PPCFG0_BLEN_Msk (0x3u << LCDC_PPCFG0_BLEN_Pos) /**< \brief (LCDC_PPCFG0) AHB Burst Length */ +#define LCDC_PPCFG0_BLEN_AHB_BLEN_SINGLE (0x0u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_PPCFG0_BLEN_AHB_BLEN_INCR4 (0x1u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_PPCFG0_BLEN_AHB_BLEN_INCR8 (0x2u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_PPCFG0_BLEN_AHB_BLEN_INCR16 (0x3u << 4) /**< \brief (LCDC_PPCFG0) AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. */ +#define LCDC_PPCFG0_DLBO (0x1u << 8) /**< \brief (LCDC_PPCFG0) Defined Length Burst Only For Channel Bus Transaction. */ +/* -------- LCDC_PPCFG1 : (LCDC Offset: 0x00000570) Post Processing Configuration Register 1 -------- */ +#define LCDC_PPCFG1_PPMODE_Pos 0 +#define LCDC_PPCFG1_PPMODE_Msk (0x7u << LCDC_PPCFG1_PPMODE_Pos) /**< \brief (LCDC_PPCFG1) Post Processing Output Format selection */ +#define LCDC_PPCFG1_PPMODE_PPMODE_RGB_16BPP (0x0u << 0) /**< \brief (LCDC_PPCFG1) RGB 16 bpp */ +#define LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_PACKED (0x1u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp PACKED */ +#define LCDC_PPCFG1_PPMODE_PPMODE_RGB_24BPP_UNPACKED (0x2u << 0) /**< \brief (LCDC_PPCFG1) RGB 24 bpp UNPACKED */ +#define LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE0 (0x3u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 0) */ +#define LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE1 (0x4u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 1) */ +#define LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE2 (0x5u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 2) */ +#define LCDC_PPCFG1_PPMODE_PPMODE_YCbCr_422_MODE3 (0x6u << 0) /**< \brief (LCDC_PPCFG1) YCbCr 422 16 bpp (Mode 3) */ +#define LCDC_PPCFG1_ITUBT601 (0x1u << 4) /**< \brief (LCDC_PPCFG1) Color Space Conversion Luminance */ +/* -------- LCDC_PPCFG2 : (LCDC Offset: 0x00000574) Post Processing Configuration Register 2 -------- */ +#define LCDC_PPCFG2_XSTRIDE_Pos 0 +#define LCDC_PPCFG2_XSTRIDE_Msk (0xffffffffu << LCDC_PPCFG2_XSTRIDE_Pos) /**< \brief (LCDC_PPCFG2) Horizontal Stride */ +#define LCDC_PPCFG2_XSTRIDE(value) ((LCDC_PPCFG2_XSTRIDE_Msk & ((value) << LCDC_PPCFG2_XSTRIDE_Pos))) +/* -------- LCDC_PPCFG3 : (LCDC Offset: 0x00000578) Post Processing Configuration Register 3 -------- */ +#define LCDC_PPCFG3_CSCYR_Pos 0 +#define LCDC_PPCFG3_CSCYR_Msk (0x3ffu << LCDC_PPCFG3_CSCYR_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 */ +#define LCDC_PPCFG3_CSCYR(value) ((LCDC_PPCFG3_CSCYR_Msk & ((value) << LCDC_PPCFG3_CSCYR_Pos))) +#define LCDC_PPCFG3_CSCYG_Pos 10 +#define LCDC_PPCFG3_CSCYG_Msk (0x3ffu << LCDC_PPCFG3_CSCYG_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 */ +#define LCDC_PPCFG3_CSCYG(value) ((LCDC_PPCFG3_CSCYG_Msk & ((value) << LCDC_PPCFG3_CSCYG_Pos))) +#define LCDC_PPCFG3_CSCYB_Pos 20 +#define LCDC_PPCFG3_CSCYB_Msk (0x3ffu << LCDC_PPCFG3_CSCYB_Pos) /**< \brief (LCDC_PPCFG3) Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 */ +#define LCDC_PPCFG3_CSCYB(value) ((LCDC_PPCFG3_CSCYB_Msk & ((value) << LCDC_PPCFG3_CSCYB_Pos))) +#define LCDC_PPCFG3_CSCYOFF (0x1u << 30) /**< \brief (LCDC_PPCFG3) Color Space Conversion Luminance Offset */ +/* -------- LCDC_PPCFG4 : (LCDC Offset: 0x0000057C) Post Processing Configuration Register 4 -------- */ +#define LCDC_PPCFG4_CSCUR_Pos 0 +#define LCDC_PPCFG4_CSCUR_Msk (0x3ffu << LCDC_PPCFG4_CSCUR_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) */ +#define LCDC_PPCFG4_CSCUR(value) ((LCDC_PPCFG4_CSCUR_Msk & ((value) << LCDC_PPCFG4_CSCUR_Pos))) +#define LCDC_PPCFG4_CSCUG_Pos 10 +#define LCDC_PPCFG4_CSCUG_Msk (0x3ffu << LCDC_PPCFG4_CSCUG_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) */ +#define LCDC_PPCFG4_CSCUG(value) ((LCDC_PPCFG4_CSCUG_Msk & ((value) << LCDC_PPCFG4_CSCUG_Pos))) +#define LCDC_PPCFG4_CSCUB_Pos 20 +#define LCDC_PPCFG4_CSCUB_Msk (0x3ffu << LCDC_PPCFG4_CSCUB_Pos) /**< \brief (LCDC_PPCFG4) Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) */ +#define LCDC_PPCFG4_CSCUB(value) ((LCDC_PPCFG4_CSCUB_Msk & ((value) << LCDC_PPCFG4_CSCUB_Pos))) +#define LCDC_PPCFG4_CSCUOFF (0x1u << 30) /**< \brief (LCDC_PPCFG4) Color Space Conversion Chrominance B Offset */ +/* -------- LCDC_PPCFG5 : (LCDC Offset: 0x00000580) Post Processing Configuration Register 5 -------- */ +#define LCDC_PPCFG5_CSCVR_Pos 0 +#define LCDC_PPCFG5_CSCVR_Msk (0x3ffu << LCDC_PPCFG5_CSCVR_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) */ +#define LCDC_PPCFG5_CSCVR(value) ((LCDC_PPCFG5_CSCVR_Msk & ((value) << LCDC_PPCFG5_CSCVR_Pos))) +#define LCDC_PPCFG5_CSCVG_Pos 10 +#define LCDC_PPCFG5_CSCVG_Msk (0x3ffu << LCDC_PPCFG5_CSCVG_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) */ +#define LCDC_PPCFG5_CSCVG(value) ((LCDC_PPCFG5_CSCVG_Msk & ((value) << LCDC_PPCFG5_CSCVG_Pos))) +#define LCDC_PPCFG5_CSCVB_Pos 20 +#define LCDC_PPCFG5_CSCVB_Msk (0x3ffu << LCDC_PPCFG5_CSCVB_Pos) /**< \brief (LCDC_PPCFG5) Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) */ +#define LCDC_PPCFG5_CSCVB(value) ((LCDC_PPCFG5_CSCVB_Msk & ((value) << LCDC_PPCFG5_CSCVB_Pos))) +#define LCDC_PPCFG5_CSCVOFF (0x1u << 30) /**< \brief (LCDC_PPCFG5) Color Space Conversion Chrominance R Offset */ +/* -------- LCDC_BASECLUT[256] : (LCDC Offset: 0x600) Base CLUT Register -------- */ +#define LCDC_BASECLUT_BCLUT_Pos 0 +#define LCDC_BASECLUT_BCLUT_Msk (0xffu << LCDC_BASECLUT_BCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Blue Color entry */ +#define LCDC_BASECLUT_BCLUT(value) ((LCDC_BASECLUT_BCLUT_Msk & ((value) << LCDC_BASECLUT_BCLUT_Pos))) +#define LCDC_BASECLUT_GCLUT_Pos 8 +#define LCDC_BASECLUT_GCLUT_Msk (0xffu << LCDC_BASECLUT_GCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Green Color entry */ +#define LCDC_BASECLUT_GCLUT(value) ((LCDC_BASECLUT_GCLUT_Msk & ((value) << LCDC_BASECLUT_GCLUT_Pos))) +#define LCDC_BASECLUT_RCLUT_Pos 16 +#define LCDC_BASECLUT_RCLUT_Msk (0xffu << LCDC_BASECLUT_RCLUT_Pos) /**< \brief (LCDC_BASECLUT[256]) Red Color entry */ +#define LCDC_BASECLUT_RCLUT(value) ((LCDC_BASECLUT_RCLUT_Msk & ((value) << LCDC_BASECLUT_RCLUT_Pos))) +/* -------- LCDC_OVR1CLUT[256] : (LCDC Offset: 0xA00) Overlay 1 CLUT Register -------- */ +#define LCDC_OVR1CLUT_BCLUT_Pos 0 +#define LCDC_OVR1CLUT_BCLUT_Msk (0xffu << LCDC_OVR1CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Blue Color entry */ +#define LCDC_OVR1CLUT_BCLUT(value) ((LCDC_OVR1CLUT_BCLUT_Msk & ((value) << LCDC_OVR1CLUT_BCLUT_Pos))) +#define LCDC_OVR1CLUT_GCLUT_Pos 8 +#define LCDC_OVR1CLUT_GCLUT_Msk (0xffu << LCDC_OVR1CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Green Color entry */ +#define LCDC_OVR1CLUT_GCLUT(value) ((LCDC_OVR1CLUT_GCLUT_Msk & ((value) << LCDC_OVR1CLUT_GCLUT_Pos))) +#define LCDC_OVR1CLUT_RCLUT_Pos 16 +#define LCDC_OVR1CLUT_RCLUT_Msk (0xffu << LCDC_OVR1CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Red Color entry */ +#define LCDC_OVR1CLUT_RCLUT(value) ((LCDC_OVR1CLUT_RCLUT_Msk & ((value) << LCDC_OVR1CLUT_RCLUT_Pos))) +#define LCDC_OVR1CLUT_ACLUT_Pos 24 +#define LCDC_OVR1CLUT_ACLUT_Msk (0xffu << LCDC_OVR1CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR1CLUT[256]) Alpha Color entry */ +#define LCDC_OVR1CLUT_ACLUT(value) ((LCDC_OVR1CLUT_ACLUT_Msk & ((value) << LCDC_OVR1CLUT_ACLUT_Pos))) +/* -------- LCDC_OVR2CLUT[256] : (LCDC Offset: 0xE00) Overlay 2 CLUT Register -------- */ +#define LCDC_OVR2CLUT_BCLUT_Pos 0 +#define LCDC_OVR2CLUT_BCLUT_Msk (0xffu << LCDC_OVR2CLUT_BCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Blue Color entry */ +#define LCDC_OVR2CLUT_BCLUT(value) ((LCDC_OVR2CLUT_BCLUT_Msk & ((value) << LCDC_OVR2CLUT_BCLUT_Pos))) +#define LCDC_OVR2CLUT_GCLUT_Pos 8 +#define LCDC_OVR2CLUT_GCLUT_Msk (0xffu << LCDC_OVR2CLUT_GCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Green Color entry */ +#define LCDC_OVR2CLUT_GCLUT(value) ((LCDC_OVR2CLUT_GCLUT_Msk & ((value) << LCDC_OVR2CLUT_GCLUT_Pos))) +#define LCDC_OVR2CLUT_RCLUT_Pos 16 +#define LCDC_OVR2CLUT_RCLUT_Msk (0xffu << LCDC_OVR2CLUT_RCLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Red Color entry */ +#define LCDC_OVR2CLUT_RCLUT(value) ((LCDC_OVR2CLUT_RCLUT_Msk & ((value) << LCDC_OVR2CLUT_RCLUT_Pos))) +#define LCDC_OVR2CLUT_ACLUT_Pos 24 +#define LCDC_OVR2CLUT_ACLUT_Msk (0xffu << LCDC_OVR2CLUT_ACLUT_Pos) /**< \brief (LCDC_OVR2CLUT[256]) Alpha Color entry */ +#define LCDC_OVR2CLUT_ACLUT(value) ((LCDC_OVR2CLUT_ACLUT_Msk & ((value) << LCDC_OVR2CLUT_ACLUT_Pos))) +/* -------- LCDC_HEOCLUT[256] : (LCDC Offset: 0x1200) High End Overlay CLUT Register -------- */ +#define LCDC_HEOCLUT_BCLUT_Pos 0 +#define LCDC_HEOCLUT_BCLUT_Msk (0xffu << LCDC_HEOCLUT_BCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Blue Color entry */ +#define LCDC_HEOCLUT_BCLUT(value) ((LCDC_HEOCLUT_BCLUT_Msk & ((value) << LCDC_HEOCLUT_BCLUT_Pos))) +#define LCDC_HEOCLUT_GCLUT_Pos 8 +#define LCDC_HEOCLUT_GCLUT_Msk (0xffu << LCDC_HEOCLUT_GCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Green Color entry */ +#define LCDC_HEOCLUT_GCLUT(value) ((LCDC_HEOCLUT_GCLUT_Msk & ((value) << LCDC_HEOCLUT_GCLUT_Pos))) +#define LCDC_HEOCLUT_RCLUT_Pos 16 +#define LCDC_HEOCLUT_RCLUT_Msk (0xffu << LCDC_HEOCLUT_RCLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Red Color entry */ +#define LCDC_HEOCLUT_RCLUT(value) ((LCDC_HEOCLUT_RCLUT_Msk & ((value) << LCDC_HEOCLUT_RCLUT_Pos))) +#define LCDC_HEOCLUT_ACLUT_Pos 24 +#define LCDC_HEOCLUT_ACLUT_Msk (0xffu << LCDC_HEOCLUT_ACLUT_Pos) /**< \brief (LCDC_HEOCLUT[256]) Alpha Color entry */ +#define LCDC_HEOCLUT_ACLUT(value) ((LCDC_HEOCLUT_ACLUT_Msk & ((value) << LCDC_HEOCLUT_ACLUT_Pos))) +/* -------- LCDC_HCRCLUT[256] : (LCDC Offset: 0x1600) Hardware Cursor CLUT Register -------- */ +#define LCDC_HCRCLUT_BCLUT_Pos 0 +#define LCDC_HCRCLUT_BCLUT_Msk (0xffu << LCDC_HCRCLUT_BCLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Blue Color entry */ +#define LCDC_HCRCLUT_BCLUT(value) ((LCDC_HCRCLUT_BCLUT_Msk & ((value) << LCDC_HCRCLUT_BCLUT_Pos))) +#define LCDC_HCRCLUT_GCLUT_Pos 8 +#define LCDC_HCRCLUT_GCLUT_Msk (0xffu << LCDC_HCRCLUT_GCLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Green Color entry */ +#define LCDC_HCRCLUT_GCLUT(value) ((LCDC_HCRCLUT_GCLUT_Msk & ((value) << LCDC_HCRCLUT_GCLUT_Pos))) +#define LCDC_HCRCLUT_RCLUT_Pos 16 +#define LCDC_HCRCLUT_RCLUT_Msk (0xffu << LCDC_HCRCLUT_RCLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Red Color entry */ +#define LCDC_HCRCLUT_RCLUT(value) ((LCDC_HCRCLUT_RCLUT_Msk & ((value) << LCDC_HCRCLUT_RCLUT_Pos))) +#define LCDC_HCRCLUT_ACLUT_Pos 24 +#define LCDC_HCRCLUT_ACLUT_Msk (0xffu << LCDC_HCRCLUT_ACLUT_Pos) /**< \brief (LCDC_HCRCLUT[256]) Alpha Color entry */ +#define LCDC_HCRCLUT_ACLUT(value) ((LCDC_HCRCLUT_ACLUT_Msk & ((value) << LCDC_HCRCLUT_ACLUT_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_LCDC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_matrix.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_matrix.h new file mode 100644 index 000000000..7bbef80c5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_matrix.h @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_MATRIX_COMPONENT_ +#define _SAMA5_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMA5_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + RwReg MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + RwReg MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 16 +typedef struct { + RwReg MATRIX_MCFG[16]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + RwReg MATRIX_SCFG[16]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 15 */ + RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + RoReg Reserved1[3]; + RwReg MATRIX_SFR[16]; /**< \brief (Matrix Offset: 0x0110) Special Function Register */ + RoReg Reserved2[37]; + RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protect Mode Register */ + RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protect Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[16] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[16]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +/* -------- MATRIX_SCFG[16] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[16]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[16]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[16]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +#define MATRIX_PRAS_M7PR_Pos 28 +#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */ +#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +#define MATRIX_PRBS_M12PR_Pos 16 +#define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) /**< \brief (MATRIX_PRBS) Master 12 Priority */ +#define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos))) +#define MATRIX_PRBS_M13PR_Pos 20 +#define MATRIX_PRBS_M13PR_Msk (0x3u << MATRIX_PRBS_M13PR_Pos) /**< \brief (MATRIX_PRBS) Master 13 Priority */ +#define MATRIX_PRBS_M13PR(value) ((MATRIX_PRBS_M13PR_Msk & ((value) << MATRIX_PRBS_M13PR_Pos))) +#define MATRIX_PRBS_M14PR_Pos 24 +#define MATRIX_PRBS_M14PR_Msk (0x3u << MATRIX_PRBS_M14PR_Pos) /**< \brief (MATRIX_PRBS) Master 14 Priority */ +#define MATRIX_PRBS_M14PR(value) ((MATRIX_PRBS_M14PR_Msk & ((value) << MATRIX_PRBS_M14PR_Pos))) +#define MATRIX_PRBS_M15PR_Pos 28 +#define MATRIX_PRBS_M15PR_Msk (0x3u << MATRIX_PRBS_M15PR_Pos) /**< \brief (MATRIX_PRBS) Master 15 Priority */ +#define MATRIX_PRBS_M15PR(value) ((MATRIX_PRBS_M15PR_Msk & ((value) << MATRIX_PRBS_M15PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB12 (0x1u << 12) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB13 (0x1u << 13) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB14 (0x1u << 14) /**< \brief (MATRIX_MRCR) */ +#define MATRIX_MRCR_RCB15 (0x1u << 15) /**< \brief (MATRIX_MRCR) */ +/* -------- MATRIX_SFR[16] : (MATRIX Offset: 0x0110) Special Function Register -------- */ +#define MATRIX_SFR_SFR_Pos 0 +#define MATRIX_SFR_SFR_Msk (0xffffffffu << MATRIX_SFR_SFR_Pos) /**< \brief (MATRIX_SFR[16]) Special Function Register Fields */ +#define MATRIX_SFR_SFR(value) ((MATRIX_SFR_SFR_Msk & ((value) << MATRIX_SFR_SFR_Pos))) +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_MATRIX_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_mpddrc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_mpddrc.h new file mode 100644 index 000000000..538ec0e09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_mpddrc.h @@ -0,0 +1,362 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_MPDDRC_COMPONENT_ +#define _SAMA5_MPDDRC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Multi-port DDR-SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_MPDDRC AHB Multi-port DDR-SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mpddrc hardware registers */ +typedef struct { + RwReg MPDDRC_MR; /**< \brief (Mpddrc Offset: 0x00) MPDDRC Mode Register */ + RwReg MPDDRC_RTR; /**< \brief (Mpddrc Offset: 0x04) MPDDRC Refresh Timer Register */ + RwReg MPDDRC_CR; /**< \brief (Mpddrc Offset: 0x08) MPDDRC Configuration Register */ + RwReg MPDDRC_TPR0; /**< \brief (Mpddrc Offset: 0x0C) MPDDRC Timing Parameter 0 Register */ + RwReg MPDDRC_TPR1; /**< \brief (Mpddrc Offset: 0x10) MPDDRC Timing Parameter 1 Register */ + RwReg MPDDRC_TPR2; /**< \brief (Mpddrc Offset: 0x14) MPDDRC Timing Parameter 2 Register */ + RoReg Reserved1[1]; + RwReg MPDDRC_LPR; /**< \brief (Mpddrc Offset: 0x1C) MPDDRC Low-power Register */ + RwReg MPDDRC_MD; /**< \brief (Mpddrc Offset: 0x20) MPDDRC Memory Device Register */ + RoReg Reserved2[1]; + RwReg MPDDRC_LPDDR2_LPR; /**< \brief (Mpddrc Offset: 0x28) MPDDRC LPDDR2 Low-power Register */ + RwReg MPDDRC_LPDDR2_CAL_MR4; /**< \brief (Mpddrc Offset: 0x2C) MPDDRC LPDDR2 Calibration and MR4 Register */ + RwReg MPDDRC_LPDDR2_TIM_CAL; /**< \brief (Mpddrc Offset: 0x30) MPDDRC LPDDR2 Timing Calibration Register */ + RwReg MPDDRC_IO_CALIBR; /**< \brief (Mpddrc Offset: 0x34) MPDDRC IO Calibration */ + RwReg MPDDRC_OCMS; /**< \brief (Mpddrc Offset: 0x38) MPDDRC OCMS Register */ + WoReg MPDDRC_OCMS_KEY1; /**< \brief (Mpddrc Offset: 0x3C) MPDDRC OCMS KEY1 Register */ + WoReg MPDDRC_OCMS_KEY2; /**< \brief (Mpddrc Offset: 0x40) MPDDRC OCMS KEY2 Register */ + RoReg Reserved3[12]; + RwReg MPDDRC_DLL_MOR; /**< \brief (Mpddrc Offset: 0x74) MPDDRC DLL Master Offset Register */ + RwReg MPDDRC_DLL_SOR; /**< \brief (Mpddrc Offset: 0x78) MPDDRC DLL Slave Offset Register */ + RoReg MPDDRC_DLL_MSR; /**< \brief (Mpddrc Offset: 0x7C) MPDDRC DLL Master Status Register */ + RoReg MPDDRC_DLL_SxSR[4]; /**< \brief (Mpddrc Offset: 0x80) MPDDRC DLL Slave 0 Status Register */ + RoReg Reserved4[21]; + RwReg MPDDRC_WPCR; /**< \brief (Mpddrc Offset: 0xE4) MPDDRC Write Protect Control Register */ + RoReg MPDDRC_WPSR; /**< \brief (Mpddrc Offset: 0xE8) MPDDRC Write Protect Status Register */ +} Mpddrc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MPDDRC_MR : (MPDDRC Offset: 0x00) MPDDRC Mode Register -------- */ +#define MPDDRC_MR_MODE_Pos 0 +#define MPDDRC_MR_MODE_Msk (0x7u << MPDDRC_MR_MODE_Pos) /**< \brief (MPDDRC_MR) MPDDRC Command Mode */ +#define MPDDRC_MR_MODE_NORMAL_CMD (0x0u << 0) /**< \brief (MPDDRC_MR) Normal Mode. Any access to the MPDDRC will be decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */ +#define MPDDRC_MR_MODE_NOP_CMD (0x1u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */ +#define MPDDRC_MR_MODE_PRCGALL_CMD (0x2u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "All Banks Precharge" command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define MPDDRC_MR_MODE_LMR_CMD (0x3u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues a "Load Mode Register" command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */ +#define MPDDRC_MR_MODE_RFSH_CMD (0x4u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "Auto-Refresh" Command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. */ +#define MPDDRC_MR_MODE_EXT_LMR_CMD (0x5u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. */ +#define MPDDRC_MR_MODE_DEEP_CMD (0x6u << 0) /**< \brief (MPDDRC_MR) Deep power mode: Access to deep power-down mode */ +#define MPDDRC_MR_MODE_LPDDR2_CMD (0x7u << 0) /**< \brief (MPDDRC_MR) The MPDDRC issues an "LPDDR2 Mode Register" command when the Low-power DDR2-SDRAM device is accessed regardless of the cycle. To activate this mode, the "Mode Register" command must be followed by a write to the Low-power DDR2-SDRAM. */ +#define MPDDRC_MR_MRS_Pos 8 +#define MPDDRC_MR_MRS_Msk (0xffu << MPDDRC_MR_MRS_Pos) /**< \brief (MPDDRC_MR) Mode Register Select LPDDR2 */ +#define MPDDRC_MR_MRS(value) ((MPDDRC_MR_MRS_Msk & ((value) << MPDDRC_MR_MRS_Pos))) +/* -------- MPDDRC_RTR : (MPDDRC Offset: 0x04) MPDDRC Refresh Timer Register -------- */ +#define MPDDRC_RTR_COUNT_Pos 0 +#define MPDDRC_RTR_COUNT_Msk (0xfffu << MPDDRC_RTR_COUNT_Pos) /**< \brief (MPDDRC_RTR) MPDDRC Refresh Timer Count */ +#define MPDDRC_RTR_COUNT(value) ((MPDDRC_RTR_COUNT_Msk & ((value) << MPDDRC_RTR_COUNT_Pos))) +#define MPDDRC_RTR_ADJ_REF (0x1u << 16) /**< \brief (MPDDRC_RTR) Adjust Refresh Rate */ +#define MPDDRC_RTR_REF_PB (0x1u << 17) /**< \brief (MPDDRC_RTR) Refresh Per Bank */ +#define MPDDRC_RTR_MR4_VALUE_Pos 20 +#define MPDDRC_RTR_MR4_VALUE_Msk (0x7u << MPDDRC_RTR_MR4_VALUE_Pos) /**< \brief (MPDDRC_RTR) Content of MR4 Register */ +#define MPDDRC_RTR_MR4_VALUE(value) ((MPDDRC_RTR_MR4_VALUE_Msk & ((value) << MPDDRC_RTR_MR4_VALUE_Pos))) +/* -------- MPDDRC_CR : (MPDDRC Offset: 0x08) MPDDRC Configuration Register -------- */ +#define MPDDRC_CR_NC_Pos 0 +#define MPDDRC_CR_NC_Msk (0x3u << MPDDRC_CR_NC_Pos) /**< \brief (MPDDRC_CR) Number of Column Bits. */ +#define MPDDRC_CR_NC_9 (0x0u << 0) /**< \brief (MPDDRC_CR) 9 DDR column bits */ +#define MPDDRC_CR_NC_10 (0x1u << 0) /**< \brief (MPDDRC_CR) 10 DDR column bits */ +#define MPDDRC_CR_NC_11 (0x2u << 0) /**< \brief (MPDDRC_CR) 11 DDR column bits */ +#define MPDDRC_CR_NC_12 (0x3u << 0) /**< \brief (MPDDRC_CR) 12 DDR column bits */ +#define MPDDRC_CR_NR_Pos 2 +#define MPDDRC_CR_NR_Msk (0x3u << MPDDRC_CR_NR_Pos) /**< \brief (MPDDRC_CR) Number of Row Bits */ +#define MPDDRC_CR_NR_11 (0x0u << 2) /**< \brief (MPDDRC_CR) 11 row bits */ +#define MPDDRC_CR_NR_12 (0x1u << 2) /**< \brief (MPDDRC_CR) 12 row bits */ +#define MPDDRC_CR_NR_13 (0x2u << 2) /**< \brief (MPDDRC_CR) 13 row bits */ +#define MPDDRC_CR_NR_14 (0x3u << 2) /**< \brief (MPDDRC_CR) 14 row bits */ +#define MPDDRC_CR_CAS_Pos 4 +#define MPDDRC_CR_CAS_Msk (0x7u << MPDDRC_CR_CAS_Pos) /**< \brief (MPDDRC_CR) CAS Latency */ +#define MPDDRC_CR_CAS_3_DDR2 (0x3u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 3 */ +#define MPDDRC_CR_CAS_3_LPDDR2 (0x3u << 4) /**< \brief (MPDDRC_CR) LPDDR2 CAS Latency 3 */ +#define MPDDRC_CR_CAS_4_DDR2 (0x4u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 4 */ +#define MPDDRC_CR_CAS_4_LPDDR2 (0x4u << 4) /**< \brief (MPDDRC_CR) LPDDR2 CAS Latency 4 */ +#define MPDDRC_CR_CAS_5_DDR2 (0x5u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 5 */ +#define MPDDRC_CR_CAS_5_LPDDR2 (0x5u << 4) /**< \brief (MPDDRC_CR) LPDDR2 CAS Latency 5 */ +#define MPDDRC_CR_CAS_6_DDR2 (0x6u << 4) /**< \brief (MPDDRC_CR) DDR2 CAS Latency 6 */ +#define MPDDRC_CR_DLL (0x1u << 7) /**< \brief (MPDDRC_CR) Reset DLL */ +#define MPDDRC_CR_DLL_RESET_DISABLED (0x0u << 7) /**< \brief (MPDDRC_CR) Disable DLL reset. */ +#define MPDDRC_CR_DLL_RESET_ENABLED (0x1u << 7) /**< \brief (MPDDRC_CR) Enable DLL reset. */ +#define MPDDRC_CR_DIC_DS (0x1u << 8) /**< \brief (MPDDRC_CR) Output Driver Impedance Control (Drive Strength) */ +#define MPDDRC_CR_DIS_DLL (0x1u << 9) /**< \brief (MPDDRC_CR) DISABLE DLL */ +#define MPDDRC_CR_ZQ_Pos 10 +#define MPDDRC_CR_ZQ_Msk (0x3u << MPDDRC_CR_ZQ_Pos) /**< \brief (MPDDRC_CR) ZQ Calibration */ +#define MPDDRC_CR_ZQ_INIT (0x0u << 10) /**< \brief (MPDDRC_CR) Calibration command after initialization */ +#define MPDDRC_CR_ZQ_LONG (0x1u << 10) /**< \brief (MPDDRC_CR) Long calibration */ +#define MPDDRC_CR_ZQ_SHORT (0x2u << 10) /**< \brief (MPDDRC_CR) Short calibration */ +#define MPDDRC_CR_ZQ_RESET (0x3u << 10) /**< \brief (MPDDRC_CR) ZQ Reset */ +#define MPDDRC_CR_OCD_Pos 12 +#define MPDDRC_CR_OCD_Msk (0x7u << MPDDRC_CR_OCD_Pos) /**< \brief (MPDDRC_CR) Off-chip Driver */ +#define MPDDRC_CR_OCD(value) ((MPDDRC_CR_OCD_Msk & ((value) << MPDDRC_CR_OCD_Pos))) +#define MPDDRC_CR_DQMS (0x1u << 16) /**< \brief (MPDDRC_CR) Mask Data is Shared */ +#define MPDDRC_CR_DQMS_NOT_SHARED (0x0u << 16) /**< \brief (MPDDRC_CR) DQM is not shared with another controller. */ +#define MPDDRC_CR_DQMS_SHARED (0x1u << 16) /**< \brief (MPDDRC_CR) DQM is shared with another controller. */ +#define MPDDRC_CR_ENRDM (0x1u << 17) /**< \brief (MPDDRC_CR) Enable Read Measure */ +#define MPDDRC_CR_ENRDM_OFF (0x0u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is disabled. */ +#define MPDDRC_CR_ENRDM_ON (0x1u << 17) /**< \brief (MPDDRC_CR) DQS/DDR_DATA phase error correction is enabled. */ +#define MPDDRC_CR_NB (0x1u << 20) /**< \brief (MPDDRC_CR) Number of Banks. */ +#define MPDDRC_CR_NB_4 (0x0u << 20) /**< \brief (MPDDRC_CR) 4 banks */ +#define MPDDRC_CR_NB_8 (0x1u << 20) /**< \brief (MPDDRC_CR) 8 banks */ +#define MPDDRC_CR_NDQS (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS: */ +#define MPDDRC_CR_NDQS_ENABLED (0x0u << 21) /**< \brief (MPDDRC_CR) Not DQS is enabled. */ +#define MPDDRC_CR_NDQS_DISABLED (0x1u << 21) /**< \brief (MPDDRC_CR) Not DQS is disabled. */ +#define MPDDRC_CR_DECOD (0x1u << 22) /**< \brief (MPDDRC_CR) Type of Decoding */ +#define MPDDRC_CR_UNAL (0x1u << 23) /**< \brief (MPDDRC_CR) Support Unaligned Access */ +#define MPDDRC_CR_UNAL_UNSUPPORTED (0x0u << 23) /**< \brief (MPDDRC_CR) Unaligned access is not supported. */ +#define MPDDRC_CR_UNAL_SUPPORTED (0x1u << 23) /**< \brief (MPDDRC_CR) Unaligned access is supported. */ +/* -------- MPDDRC_TPR0 : (MPDDRC Offset: 0x0C) MPDDRC Timing Parameter 0 Register -------- */ +#define MPDDRC_TPR0_TRAS_Pos 0 +#define MPDDRC_TPR0_TRAS_Msk (0xfu << MPDDRC_TPR0_TRAS_Pos) /**< \brief (MPDDRC_TPR0) Active to Precharge Delay */ +#define MPDDRC_TPR0_TRAS(value) ((MPDDRC_TPR0_TRAS_Msk & ((value) << MPDDRC_TPR0_TRAS_Pos))) +#define MPDDRC_TPR0_TRCD_Pos 4 +#define MPDDRC_TPR0_TRCD_Msk (0xfu << MPDDRC_TPR0_TRCD_Pos) /**< \brief (MPDDRC_TPR0) Row to Column Delay */ +#define MPDDRC_TPR0_TRCD(value) ((MPDDRC_TPR0_TRCD_Msk & ((value) << MPDDRC_TPR0_TRCD_Pos))) +#define MPDDRC_TPR0_TWR_Pos 8 +#define MPDDRC_TPR0_TWR_Msk (0xfu << MPDDRC_TPR0_TWR_Pos) /**< \brief (MPDDRC_TPR0) Write Recovery Delay */ +#define MPDDRC_TPR0_TWR(value) ((MPDDRC_TPR0_TWR_Msk & ((value) << MPDDRC_TPR0_TWR_Pos))) +#define MPDDRC_TPR0_TRC_Pos 12 +#define MPDDRC_TPR0_TRC_Msk (0xfu << MPDDRC_TPR0_TRC_Pos) /**< \brief (MPDDRC_TPR0) Row Cycle Delay */ +#define MPDDRC_TPR0_TRC(value) ((MPDDRC_TPR0_TRC_Msk & ((value) << MPDDRC_TPR0_TRC_Pos))) +#define MPDDRC_TPR0_TRP_Pos 16 +#define MPDDRC_TPR0_TRP_Msk (0xfu << MPDDRC_TPR0_TRP_Pos) /**< \brief (MPDDRC_TPR0) Row Precharge Delay */ +#define MPDDRC_TPR0_TRP(value) ((MPDDRC_TPR0_TRP_Msk & ((value) << MPDDRC_TPR0_TRP_Pos))) +#define MPDDRC_TPR0_TRRD_Pos 20 +#define MPDDRC_TPR0_TRRD_Msk (0xfu << MPDDRC_TPR0_TRRD_Pos) /**< \brief (MPDDRC_TPR0) Active BankA to Active BankB */ +#define MPDDRC_TPR0_TRRD(value) ((MPDDRC_TPR0_TRRD_Msk & ((value) << MPDDRC_TPR0_TRRD_Pos))) +#define MPDDRC_TPR0_TWTR_Pos 24 +#define MPDDRC_TPR0_TWTR_Msk (0xfu << MPDDRC_TPR0_TWTR_Pos) /**< \brief (MPDDRC_TPR0) Internal Write to Read Delay */ +#define MPDDRC_TPR0_TWTR(value) ((MPDDRC_TPR0_TWTR_Msk & ((value) << MPDDRC_TPR0_TWTR_Pos))) +#define MPDDRC_TPR0_TMRD_Pos 28 +#define MPDDRC_TPR0_TMRD_Msk (0xfu << MPDDRC_TPR0_TMRD_Pos) /**< \brief (MPDDRC_TPR0) Load Mode Register Command to Activate or Refresh Command */ +#define MPDDRC_TPR0_TMRD(value) ((MPDDRC_TPR0_TMRD_Msk & ((value) << MPDDRC_TPR0_TMRD_Pos))) +/* -------- MPDDRC_TPR1 : (MPDDRC Offset: 0x10) MPDDRC Timing Parameter 1 Register -------- */ +#define MPDDRC_TPR1_TRFC_Pos 0 +#define MPDDRC_TPR1_TRFC_Msk (0x1fu << MPDDRC_TPR1_TRFC_Pos) /**< \brief (MPDDRC_TPR1) Row Cycle Delay */ +#define MPDDRC_TPR1_TRFC(value) ((MPDDRC_TPR1_TRFC_Msk & ((value) << MPDDRC_TPR1_TRFC_Pos))) +#define MPDDRC_TPR1_TXSNR_Pos 8 +#define MPDDRC_TPR1_TXSNR_Msk (0xffu << MPDDRC_TPR1_TXSNR_Pos) /**< \brief (MPDDRC_TPR1) Exit Self Refresh Delay to Non Read Command */ +#define MPDDRC_TPR1_TXSNR(value) ((MPDDRC_TPR1_TXSNR_Msk & ((value) << MPDDRC_TPR1_TXSNR_Pos))) +#define MPDDRC_TPR1_TXSRD_Pos 16 +#define MPDDRC_TPR1_TXSRD_Msk (0xffu << MPDDRC_TPR1_TXSRD_Pos) /**< \brief (MPDDRC_TPR1) Exit Self Refresh Delay to Read Command */ +#define MPDDRC_TPR1_TXSRD(value) ((MPDDRC_TPR1_TXSRD_Msk & ((value) << MPDDRC_TPR1_TXSRD_Pos))) +#define MPDDRC_TPR1_TXP_Pos 24 +#define MPDDRC_TPR1_TXP_Msk (0xfu << MPDDRC_TPR1_TXP_Pos) /**< \brief (MPDDRC_TPR1) Exit Power-down Delay to First Command */ +#define MPDDRC_TPR1_TXP(value) ((MPDDRC_TPR1_TXP_Msk & ((value) << MPDDRC_TPR1_TXP_Pos))) +/* -------- MPDDRC_TPR2 : (MPDDRC Offset: 0x14) MPDDRC Timing Parameter 2 Register -------- */ +#define MPDDRC_TPR2_TXARD_Pos 0 +#define MPDDRC_TPR2_TXARD_Msk (0xfu << MPDDRC_TPR2_TXARD_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Fast Exit". */ +#define MPDDRC_TPR2_TXARD(value) ((MPDDRC_TPR2_TXARD_Msk & ((value) << MPDDRC_TPR2_TXARD_Pos))) +#define MPDDRC_TPR2_TXARDS_Pos 4 +#define MPDDRC_TPR2_TXARDS_Msk (0xfu << MPDDRC_TPR2_TXARDS_Pos) /**< \brief (MPDDRC_TPR2) Exit Active Power Down Delay to Read Command in Mode "Slow Exit". */ +#define MPDDRC_TPR2_TXARDS(value) ((MPDDRC_TPR2_TXARDS_Msk & ((value) << MPDDRC_TPR2_TXARDS_Pos))) +#define MPDDRC_TPR2_TRPA_Pos 8 +#define MPDDRC_TPR2_TRPA_Msk (0xfu << MPDDRC_TPR2_TRPA_Pos) /**< \brief (MPDDRC_TPR2) Row Precharge All Delay */ +#define MPDDRC_TPR2_TRPA(value) ((MPDDRC_TPR2_TRPA_Msk & ((value) << MPDDRC_TPR2_TRPA_Pos))) +#define MPDDRC_TPR2_TRTP_Pos 12 +#define MPDDRC_TPR2_TRTP_Msk (0x7u << MPDDRC_TPR2_TRTP_Pos) /**< \brief (MPDDRC_TPR2) Read to Precharge */ +#define MPDDRC_TPR2_TRTP(value) ((MPDDRC_TPR2_TRTP_Msk & ((value) << MPDDRC_TPR2_TRTP_Pos))) +#define MPDDRC_TPR2_TFAW_Pos 16 +#define MPDDRC_TPR2_TFAW_Msk (0xfu << MPDDRC_TPR2_TFAW_Pos) /**< \brief (MPDDRC_TPR2) Four Active Windows */ +#define MPDDRC_TPR2_TFAW(value) ((MPDDRC_TPR2_TFAW_Msk & ((value) << MPDDRC_TPR2_TFAW_Pos))) +/* -------- MPDDRC_LPR : (MPDDRC Offset: 0x1C) MPDDRC Low-power Register -------- */ +#define MPDDRC_LPR_LPCB_Pos 0 +#define MPDDRC_LPR_LPCB_Msk (0x3u << MPDDRC_LPR_LPCB_Pos) /**< \brief (MPDDRC_LPR) Low-power Command Bit */ +#define MPDDRC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (MPDDRC_LPR) Low-power Feature is inhibited. No power-down, self refresh and deep-power modes are issued to the DDR-SDRAM device. */ +#define MPDDRC_LPR_LPCB_SELFREFRESH (0x1u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Self Refresh command to the DDR-SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The DDR-SDRAM device leaves the self refresh mode when accessed and reenters it after the access. */ +#define MPDDRC_LPR_LPCB_POWERDOWN (0x2u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Power-down Command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the power-down mode when accessed and reenters it after the access. */ +#define MPDDRC_LPR_LPCB_DEEP_PWD (0x3u << 0) /**< \brief (MPDDRC_LPR) The MPDDRC issues a Deep Power-down command to the Low-power DDR-SDRAM device. */ +#define MPDDRC_LPR_CLK_FR (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock Frozen Command Bit */ +#define MPDDRC_LPR_CLK_FR_DISABLED (0x0u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are not frozen. */ +#define MPDDRC_LPR_CLK_FR_ENABLED (0x1u << 2) /**< \brief (MPDDRC_LPR) Clock(s) is/are frozen. */ +#define MPDDRC_LPR_LPDDR2_PWOFF (0x1u << 3) /**< \brief (MPDDRC_LPR) LPDDR2 Power Off Bit */ +#define MPDDRC_LPR_LPDDR2_PWOFF_DISABLED (0x0u << 3) /**< \brief (MPDDRC_LPR) No power off sequence applied to LPDDR2. */ +#define MPDDRC_LPR_LPDDR2_PWOFF_ENABLED (0x1u << 3) /**< \brief (MPDDRC_LPR) A power off sequence is applied to the LPDDR2 device. CKE is forced low. */ +#define MPDDRC_LPR_PASR_Pos 4 +#define MPDDRC_LPR_PASR_Msk (0x7u << MPDDRC_LPR_PASR_Pos) /**< \brief (MPDDRC_LPR) Partial Array Self Refresh */ +#define MPDDRC_LPR_PASR(value) ((MPDDRC_LPR_PASR_Msk & ((value) << MPDDRC_LPR_PASR_Pos))) +#define MPDDRC_LPR_DS_Pos 8 +#define MPDDRC_LPR_DS_Msk (0x7u << MPDDRC_LPR_DS_Pos) /**< \brief (MPDDRC_LPR) Drive Strength */ +#define MPDDRC_LPR_DS(value) ((MPDDRC_LPR_DS_Msk & ((value) << MPDDRC_LPR_DS_Pos))) +#define MPDDRC_LPR_TIMEOUT_Pos 12 +#define MPDDRC_LPR_TIMEOUT_Msk (0x3u << MPDDRC_LPR_TIMEOUT_Pos) /**< \brief (MPDDRC_LPR) Enter Low-power Mode */ +#define MPDDRC_LPR_TIMEOUT_0 (0x0u << 12) /**< \brief (MPDDRC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define MPDDRC_LPR_TIMEOUT_64 (0x1u << 12) /**< \brief (MPDDRC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define MPDDRC_LPR_TIMEOUT_128 (0x2u << 12) /**< \brief (MPDDRC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +#define MPDDRC_LPR_APDE (0x1u << 16) /**< \brief (MPDDRC_LPR) Active Power Down Exit Time */ +#define MPDDRC_LPR_APDE_FAST (0x0u << 16) /**< \brief (MPDDRC_LPR) Fast Exit. */ +#define MPDDRC_LPR_APDE_SLOW (0x1u << 16) /**< \brief (MPDDRC_LPR) Low Exit. */ +#define MPDDRC_LPR_UPD_MR_Pos 20 +#define MPDDRC_LPR_UPD_MR_Msk (0x3u << MPDDRC_LPR_UPD_MR_Pos) /**< \brief (MPDDRC_LPR) Update Load Mode Register and Extended Mode Register */ +#define MPDDRC_LPR_UPD_MR(value) ((MPDDRC_LPR_UPD_MR_Msk & ((value) << MPDDRC_LPR_UPD_MR_Pos))) +/* -------- MPDDRC_MD : (MPDDRC Offset: 0x20) MPDDRC Memory Device Register -------- */ +#define MPDDRC_MD_MD_Pos 0 +#define MPDDRC_MD_MD_Msk (0x7u << MPDDRC_MD_MD_Pos) /**< \brief (MPDDRC_MD) Memory Device */ +#define MPDDRC_MD_MD_LPDDR_SDRAM (0x3u << 0) /**< \brief (MPDDRC_MD) Low-power DDR1-SDRAM */ +#define MPDDRC_MD_MD_DDR2_SDRAM (0x6u << 0) /**< \brief (MPDDRC_MD) DDR2-SDRAM */ +#define MPDDRC_MD_MD_LPDDR2_SDRAM (0x7u << 0) /**< \brief (MPDDRC_MD) Low-Power DDR2-SDRAM */ +#define MPDDRC_MD_DBW (0x1u << 4) /**< \brief (MPDDRC_MD) Data Bus Width */ +#define MPDDRC_MD_DBW_32_BITS (0x0u << 4) /**< \brief (MPDDRC_MD) Data bus width is 32 bits. */ +#define MPDDRC_MD_DBW_16_BITS (0x1u << 4) /**< \brief (MPDDRC_MD) Data bus width is 16 bits. */ +/* -------- MPDDRC_LPDDR2_LPR : (MPDDRC Offset: 0x28) MPDDRC LPDDR2 Low-power Register -------- */ +#define MPDDRC_LPDDR2_LPR_BK_MASK_Pos 0 +#define MPDDRC_LPDDR2_LPR_BK_MASK_Msk (0xffu << MPDDRC_LPDDR2_LPR_BK_MASK_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) */ +#define MPDDRC_LPDDR2_LPR_BK_MASK(value) ((MPDDRC_LPDDR2_LPR_BK_MASK_Msk & ((value) << MPDDRC_LPDDR2_LPR_BK_MASK_Pos))) +#define MPDDRC_LPDDR2_LPR_SEG_MASK_Pos 8 +#define MPDDRC_LPDDR2_LPR_SEG_MASK_Msk (0xffffu << MPDDRC_LPDDR2_LPR_SEG_MASK_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Segment Mask Bit */ +#define MPDDRC_LPDDR2_LPR_SEG_MASK(value) ((MPDDRC_LPDDR2_LPR_SEG_MASK_Msk & ((value) << MPDDRC_LPDDR2_LPR_SEG_MASK_Pos))) +#define MPDDRC_LPDDR2_LPR_DS_Pos 24 +#define MPDDRC_LPDDR2_LPR_DS_Msk (0xfu << MPDDRC_LPDDR2_LPR_DS_Pos) /**< \brief (MPDDRC_LPDDR2_LPR) Drive strength */ +#define MPDDRC_LPDDR2_LPR_DS(value) ((MPDDRC_LPDDR2_LPR_DS_Msk & ((value) << MPDDRC_LPDDR2_LPR_DS_Pos))) +/* -------- MPDDRC_LPDDR2_CAL_MR4 : (MPDDRC Offset: 0x2C) MPDDRC LPDDR2 Calibration and MR4 Register -------- */ +#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos 0 +#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Msk (0xffffu << MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos) /**< \brief (MPDDRC_LPDDR2_CAL_MR4) LPDDR2 Calibration Timer Count */ +#define MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL(value) ((MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Msk & ((value) << MPDDRC_LPDDR2_CAL_MR4_COUNT_CAL_Pos))) +#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos 16 +#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Msk (0xffffu << MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos) /**< \brief (MPDDRC_LPDDR2_CAL_MR4) Mode Register 4 Read Interval */ +#define MPDDRC_LPDDR2_CAL_MR4_MR4_READ(value) ((MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Msk & ((value) << MPDDRC_LPDDR2_CAL_MR4_MR4_READ_Pos))) +/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) MPDDRC LPDDR2 Timing Calibration Register -------- */ +#define MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos 0 +#define MPDDRC_LPDDR2_TIM_CAL_ZQCS_Msk (0xffu << MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos) /**< \brief (MPDDRC_LPDDR2_TIM_CAL) ZQ Calibration Short */ +#define MPDDRC_LPDDR2_TIM_CAL_ZQCS(value) ((MPDDRC_LPDDR2_TIM_CAL_ZQCS_Msk & ((value) << MPDDRC_LPDDR2_TIM_CAL_ZQCS_Pos))) +/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) MPDDRC IO Calibration -------- */ +#define MPDDRC_IO_CALIBR_RDIV_Pos 0 +#define MPDDRC_IO_CALIBR_RDIV_Msk (0x7u << MPDDRC_IO_CALIBR_RDIV_Pos) /**< \brief (MPDDRC_IO_CALIBR) Resistor Divider, output driver impedance */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_34 (0x1u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 34,3 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_40 (0x2u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 40 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_333 (0x2u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 33,3 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_48 (0x3u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ =48 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_60 (0x4u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ =60 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_50 (0x4u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ =50 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_80 (0x6u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 80 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_667 (0x6u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 66,7 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_120 (0x7u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 120 Ohm */ +#define MPDDRC_IO_CALIBR_RDIV_RZQ_100 (0x7u << 0) /**< \brief (MPDDRC_IO_CALIBR) RZQ = 100 Ohm */ +#define MPDDRC_IO_CALIBR_TZQIO_Pos 8 +#define MPDDRC_IO_CALIBR_TZQIO_Msk (0x7u << MPDDRC_IO_CALIBR_TZQIO_Pos) /**< \brief (MPDDRC_IO_CALIBR) IO Calibration */ +#define MPDDRC_IO_CALIBR_TZQIO(value) ((MPDDRC_IO_CALIBR_TZQIO_Msk & ((value) << MPDDRC_IO_CALIBR_TZQIO_Pos))) +#define MPDDRC_IO_CALIBR_CALCODEP_Pos 16 +#define MPDDRC_IO_CALIBR_CALCODEP_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEP_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor P */ +#define MPDDRC_IO_CALIBR_CALCODEP(value) ((MPDDRC_IO_CALIBR_CALCODEP_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEP_Pos))) +#define MPDDRC_IO_CALIBR_CALCODEN_Pos 20 +#define MPDDRC_IO_CALIBR_CALCODEN_Msk (0xfu << MPDDRC_IO_CALIBR_CALCODEN_Pos) /**< \brief (MPDDRC_IO_CALIBR) Number of Transistor N */ +#define MPDDRC_IO_CALIBR_CALCODEN(value) ((MPDDRC_IO_CALIBR_CALCODEN_Msk & ((value) << MPDDRC_IO_CALIBR_CALCODEN_Pos))) +/* -------- MPDDRC_OCMS : (MPDDRC Offset: 0x38) MPDDRC OCMS Register -------- */ +#define MPDDRC_OCMS_SCR_EN (0x1u << 0) /**< \brief (MPDDRC_OCMS) Scrambling enable */ +/* -------- MPDDRC_OCMS_KEY1 : (MPDDRC Offset: 0x3C) MPDDRC OCMS KEY1 Register -------- */ +#define MPDDRC_OCMS_KEY1_KEY1_Pos 0 +#define MPDDRC_OCMS_KEY1_KEY1_Msk (0xffffffffu << MPDDRC_OCMS_KEY1_KEY1_Pos) /**< \brief (MPDDRC_OCMS_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define MPDDRC_OCMS_KEY1_KEY1(value) ((MPDDRC_OCMS_KEY1_KEY1_Msk & ((value) << MPDDRC_OCMS_KEY1_KEY1_Pos))) +/* -------- MPDDRC_OCMS_KEY2 : (MPDDRC Offset: 0x40) MPDDRC OCMS KEY2 Register -------- */ +#define MPDDRC_OCMS_KEY2_KEY2_Pos 0 +#define MPDDRC_OCMS_KEY2_KEY2_Msk (0xffffffffu << MPDDRC_OCMS_KEY2_KEY2_Pos) /**< \brief (MPDDRC_OCMS_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define MPDDRC_OCMS_KEY2_KEY2(value) ((MPDDRC_OCMS_KEY2_KEY2_Msk & ((value) << MPDDRC_OCMS_KEY2_KEY2_Pos))) +/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) MPDDRC DLL Master Offset Register -------- */ +#define MPDDRC_DLL_MOR_MOFF_Pos 0 +#define MPDDRC_DLL_MOR_MOFF_Msk (0xfu << MPDDRC_DLL_MOR_MOFF_Pos) /**< \brief (MPDDRC_DLL_MOR) DLL Master Delay Line Offset */ +#define MPDDRC_DLL_MOR_MOFF(value) ((MPDDRC_DLL_MOR_MOFF_Msk & ((value) << MPDDRC_DLL_MOR_MOFF_Pos))) +#define MPDDRC_DLL_MOR_CLK90OFF_Pos 8 +#define MPDDRC_DLL_MOR_CLK90OFF_Msk (0x1fu << MPDDRC_DLL_MOR_CLK90OFF_Pos) /**< \brief (MPDDRC_DLL_MOR) DLL CLK90 Delay Line Offset */ +#define MPDDRC_DLL_MOR_CLK90OFF(value) ((MPDDRC_DLL_MOR_CLK90OFF_Msk & ((value) << MPDDRC_DLL_MOR_CLK90OFF_Pos))) +#define MPDDRC_DLL_MOR_SELOFF (0x1u << 16) /**< \brief (MPDDRC_DLL_MOR) DLL Offset Selection */ +/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) MPDDRC DLL Slave Offset Register -------- */ +#define MPDDRC_DLL_SOR_S0OFF_Pos 0 +#define MPDDRC_DLL_SOR_S0OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S0OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 0 Delay Line Offset ([x=0..3]) */ +#define MPDDRC_DLL_SOR_S0OFF(value) ((MPDDRC_DLL_SOR_S0OFF_Msk & ((value) << MPDDRC_DLL_SOR_S0OFF_Pos))) +#define MPDDRC_DLL_SOR_S1OFF_Pos 8 +#define MPDDRC_DLL_SOR_S1OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S1OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 1 Delay Line Offset ([x=0..3]) */ +#define MPDDRC_DLL_SOR_S1OFF(value) ((MPDDRC_DLL_SOR_S1OFF_Msk & ((value) << MPDDRC_DLL_SOR_S1OFF_Pos))) +#define MPDDRC_DLL_SOR_S2OFF_Pos 16 +#define MPDDRC_DLL_SOR_S2OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S2OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 2 Delay Line Offset ([x=0..3]) */ +#define MPDDRC_DLL_SOR_S2OFF(value) ((MPDDRC_DLL_SOR_S2OFF_Msk & ((value) << MPDDRC_DLL_SOR_S2OFF_Pos))) +#define MPDDRC_DLL_SOR_S3OFF_Pos 24 +#define MPDDRC_DLL_SOR_S3OFF_Msk (0x1fu << MPDDRC_DLL_SOR_S3OFF_Pos) /**< \brief (MPDDRC_DLL_SOR) DLL Slave 3 Delay Line Offset ([x=0..3]) */ +#define MPDDRC_DLL_SOR_S3OFF(value) ((MPDDRC_DLL_SOR_S3OFF_Msk & ((value) << MPDDRC_DLL_SOR_S3OFF_Pos))) +/* -------- MPDDRC_DLL_MSR : (MPDDRC Offset: 0x7C) MPDDRC DLL Master Status Register -------- */ +#define MPDDRC_DLL_MSR_MDINC (0x1u << 0) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Increment */ +#define MPDDRC_DLL_MSR_MDDEC (0x1u << 1) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Decrement */ +#define MPDDRC_DLL_MSR_MDOVF (0x1u << 2) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Overflow Flag */ +#define MPDDRC_DLL_MSR_MDVAL_Pos 8 +#define MPDDRC_DLL_MSR_MDVAL_Msk (0xffu << MPDDRC_DLL_MSR_MDVAL_Pos) /**< \brief (MPDDRC_DLL_MSR) DLL Master Delay Value */ +/* -------- MPDDRC_DLL_S0SR : (MPDDRC Offset: 0x80) MPDDRC DLL Slave 0 Status Register -------- */ +#define MPDDRC_DLL_S0SR_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Overflow Flag */ +#define MPDDRC_DLL_S0SR_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Underflow Flag */ +#define MPDDRC_DLL_S0SR_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Error Flag */ +#define MPDDRC_DLL_S0SR_SDVAL_Pos 8 +#define MPDDRC_DLL_S0SR_SDVAL_Msk (0xffu << MPDDRC_DLL_S0SR_SDVAL_Pos) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Value */ +#define MPDDRC_DLL_S0SR_SDCVAL_Pos 16 +#define MPDDRC_DLL_S0SR_SDCVAL_Msk (0xffu << MPDDRC_DLL_S0SR_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_S0SR) DLL Slave x Delay Correction Value */ +/* -------- MPDDRC_DLL_S1SR : (MPDDRC Offset: 0x84) MPDDRC DLL Slave 1 Status Register -------- */ +#define MPDDRC_DLL_S1SR_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Overflow Flag */ +#define MPDDRC_DLL_S1SR_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Underflow Flag */ +#define MPDDRC_DLL_S1SR_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Error Flag */ +#define MPDDRC_DLL_S1SR_SDVAL_Pos 8 +#define MPDDRC_DLL_S1SR_SDVAL_Msk (0xffu << MPDDRC_DLL_S1SR_SDVAL_Pos) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Value */ +#define MPDDRC_DLL_S1SR_SDCVAL_Pos 16 +#define MPDDRC_DLL_S1SR_SDCVAL_Msk (0xffu << MPDDRC_DLL_S1SR_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_S1SR) DLL Slave x Delay Correction Value */ +/* -------- MPDDRC_DLL_S2SR : (MPDDRC Offset: 0x88) MPDDRC DLL Slave 2 Status Register -------- */ +#define MPDDRC_DLL_S2SR_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_S2SR) DLL Slave x Delay Correction Overflow Flag */ +#define MPDDRC_DLL_S2SR_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_S2SR) DLL Slave x Delay Correction Underflow Flag */ +#define MPDDRC_DLL_S2SR_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_S2SR) DLL Slave x Delay Correction Error Flag */ +#define MPDDRC_DLL_S2SR_SDVAL_Pos 8 +#define MPDDRC_DLL_S2SR_SDVAL_Msk (0xffu << MPDDRC_DLL_S2SR_SDVAL_Pos) /**< \brief (MPDDRC_DLL_S2SR) DLL Slave x Delay Value */ +#define MPDDRC_DLL_S2SR_SDCVAL_Pos 16 +#define MPDDRC_DLL_S2SR_SDCVAL_Msk (0xffu << MPDDRC_DLL_S2SR_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_S2SR) DLL Slave x Delay Correction Value */ +/* -------- MPDDRC_DLL_S3SR : (MPDDRC Offset: 0x8C) MPDDRC DLL Slave 3 Status Register -------- */ +#define MPDDRC_DLL_S3SR_SDCOVF (0x1u << 0) /**< \brief (MPDDRC_DLL_S3SR) DLL Slave x Delay Correction Overflow Flag */ +#define MPDDRC_DLL_S3SR_SDCUDF (0x1u << 1) /**< \brief (MPDDRC_DLL_S3SR) DLL Slave x Delay Correction Underflow Flag */ +#define MPDDRC_DLL_S3SR_SDERF (0x1u << 2) /**< \brief (MPDDRC_DLL_S3SR) DLL Slave x Delay Correction Error Flag */ +#define MPDDRC_DLL_S3SR_SDVAL_Pos 8 +#define MPDDRC_DLL_S3SR_SDVAL_Msk (0xffu << MPDDRC_DLL_S3SR_SDVAL_Pos) /**< \brief (MPDDRC_DLL_S3SR) DLL Slave x Delay Value */ +#define MPDDRC_DLL_S3SR_SDCVAL_Pos 16 +#define MPDDRC_DLL_S3SR_SDCVAL_Msk (0xffu << MPDDRC_DLL_S3SR_SDCVAL_Pos) /**< \brief (MPDDRC_DLL_S3SR) DLL Slave x Delay Correction Value */ +/* -------- MPDDRC_WPCR : (MPDDRC Offset: 0xE4) MPDDRC Write Protect Control Register -------- */ +#define MPDDRC_WPCR_WPEN (0x1u << 0) /**< \brief (MPDDRC_WPCR) Write Protection Enable */ +#define MPDDRC_WPCR_WPKEY_Pos 8 +#define MPDDRC_WPCR_WPKEY_Msk (0xffffffu << MPDDRC_WPCR_WPKEY_Pos) /**< \brief (MPDDRC_WPCR) Write Protection KEY */ +#define MPDDRC_WPCR_WPKEY(value) ((MPDDRC_WPCR_WPKEY_Msk & ((value) << MPDDRC_WPCR_WPKEY_Pos))) +/* -------- MPDDRC_WPSR : (MPDDRC Offset: 0xE8) MPDDRC Write Protect Status Register -------- */ +#define MPDDRC_WPSR_WPVS (0x1u << 0) /**< \brief (MPDDRC_WPSR) Write Protection Enable */ +#define MPDDRC_WPSR_WPVSRC_Pos 8 +#define MPDDRC_WPSR_WPVSRC_Msk (0xffffu << MPDDRC_WPSR_WPVSRC_Pos) /**< \brief (MPDDRC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_MPDDRC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pio.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pio.h new file mode 100644 index 000000000..c201b0dd3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pio.h @@ -0,0 +1,1737 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIO_COMPONENT_ +#define _SAMA5_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + RoReg Reserved1[1]; + WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + RoReg Reserved2[1]; + WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + RoReg Reserved3[1]; + WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + RoReg Reserved4[1]; + WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + RoReg Reserved5[1]; + RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + RoReg Reserved6[2]; + WoReg PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + WoReg PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + RoReg PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + RoReg Reserved7[1]; + WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + RoReg Reserved8[1]; + WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + RoReg Reserved9[1]; + WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + RoReg Reserved10[1]; + WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + RoReg Reserved11[1]; + RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ + RoReg Reserved12[5]; + RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + RoReg Reserved13[5]; + RwReg PIO_DRIVER1; /**< \brief (Pio Offset: 0x0118) I/O Drive Register 1 */ + RwReg PIO_DRIVER2; /**< \brief (Pio Offset: 0x011C) I/O Drive Register 2 */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */ +/* -------- PIO_DRIVER1 : (PIO Offset: 0x0118) I/O Drive Register 1 -------- */ +#define PIO_DRIVER1_LINE0_Pos 0 +#define PIO_DRIVER1_LINE0_Msk (0x3u << PIO_DRIVER1_LINE0_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 0 */ +#define PIO_DRIVER1_LINE0_LO_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE0_ME_DRIVE (0x2u << 0) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE0_HI_DRIVE (0x3u << 0) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE1_Pos 2 +#define PIO_DRIVER1_LINE1_Msk (0x3u << PIO_DRIVER1_LINE1_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 1 */ +#define PIO_DRIVER1_LINE1_LO_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE1_ME_DRIVE (0x2u << 2) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE1_HI_DRIVE (0x3u << 2) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE2_Pos 4 +#define PIO_DRIVER1_LINE2_Msk (0x3u << PIO_DRIVER1_LINE2_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 2 */ +#define PIO_DRIVER1_LINE2_LO_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE2_ME_DRIVE (0x2u << 4) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE2_HI_DRIVE (0x3u << 4) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE3_Pos 6 +#define PIO_DRIVER1_LINE3_Msk (0x3u << PIO_DRIVER1_LINE3_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 3 */ +#define PIO_DRIVER1_LINE3_LO_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE3_ME_DRIVE (0x2u << 6) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE3_HI_DRIVE (0x3u << 6) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE4_Pos 8 +#define PIO_DRIVER1_LINE4_Msk (0x3u << PIO_DRIVER1_LINE4_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 4 */ +#define PIO_DRIVER1_LINE4_LO_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE4_ME_DRIVE (0x2u << 8) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE4_HI_DRIVE (0x3u << 8) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE5_Pos 10 +#define PIO_DRIVER1_LINE5_Msk (0x3u << PIO_DRIVER1_LINE5_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 5 */ +#define PIO_DRIVER1_LINE5_LO_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE5_ME_DRIVE (0x2u << 10) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE5_HI_DRIVE (0x3u << 10) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE6_Pos 12 +#define PIO_DRIVER1_LINE6_Msk (0x3u << PIO_DRIVER1_LINE6_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 6 */ +#define PIO_DRIVER1_LINE6_LO_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE6_ME_DRIVE (0x2u << 12) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE6_HI_DRIVE (0x3u << 12) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE7_Pos 14 +#define PIO_DRIVER1_LINE7_Msk (0x3u << PIO_DRIVER1_LINE7_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 7 */ +#define PIO_DRIVER1_LINE7_LO_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE7_ME_DRIVE (0x2u << 14) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE7_HI_DRIVE (0x3u << 14) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE8_Pos 16 +#define PIO_DRIVER1_LINE8_Msk (0x3u << PIO_DRIVER1_LINE8_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 8 */ +#define PIO_DRIVER1_LINE8_LO_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE8_ME_DRIVE (0x2u << 16) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE8_HI_DRIVE (0x3u << 16) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE9_Pos 18 +#define PIO_DRIVER1_LINE9_Msk (0x3u << PIO_DRIVER1_LINE9_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 9 */ +#define PIO_DRIVER1_LINE9_LO_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE9_ME_DRIVE (0x2u << 18) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE9_HI_DRIVE (0x3u << 18) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE10_Pos 20 +#define PIO_DRIVER1_LINE10_Msk (0x3u << PIO_DRIVER1_LINE10_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 10 */ +#define PIO_DRIVER1_LINE10_LO_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE10_ME_DRIVE (0x2u << 20) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE10_HI_DRIVE (0x3u << 20) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE11_Pos 22 +#define PIO_DRIVER1_LINE11_Msk (0x3u << PIO_DRIVER1_LINE11_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 11 */ +#define PIO_DRIVER1_LINE11_LO_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE11_ME_DRIVE (0x2u << 22) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE11_HI_DRIVE (0x3u << 22) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE12_Pos 24 +#define PIO_DRIVER1_LINE12_Msk (0x3u << PIO_DRIVER1_LINE12_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 12 */ +#define PIO_DRIVER1_LINE12_LO_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE12_ME_DRIVE (0x2u << 24) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE12_HI_DRIVE (0x3u << 24) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE13_Pos 26 +#define PIO_DRIVER1_LINE13_Msk (0x3u << PIO_DRIVER1_LINE13_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 13 */ +#define PIO_DRIVER1_LINE13_LO_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE13_ME_DRIVE (0x2u << 26) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE13_HI_DRIVE (0x3u << 26) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE14_Pos 28 +#define PIO_DRIVER1_LINE14_Msk (0x3u << PIO_DRIVER1_LINE14_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 14 */ +#define PIO_DRIVER1_LINE14_LO_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE14_ME_DRIVE (0x2u << 28) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE14_HI_DRIVE (0x3u << 28) /**< \brief (PIO_DRIVER1) High drive */ +#define PIO_DRIVER1_LINE15_Pos 30 +#define PIO_DRIVER1_LINE15_Msk (0x3u << PIO_DRIVER1_LINE15_Pos) /**< \brief (PIO_DRIVER1) Drive of PIO line 15 */ +#define PIO_DRIVER1_LINE15_LO_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER1) Low drive */ +#define PIO_DRIVER1_LINE15_ME_DRIVE (0x2u << 30) /**< \brief (PIO_DRIVER1) Medium drive */ +#define PIO_DRIVER1_LINE15_HI_DRIVE (0x3u << 30) /**< \brief (PIO_DRIVER1) High drive */ +/* -------- PIO_DRIVER2 : (PIO Offset: 0x011C) I/O Drive Register 2 -------- */ +#define PIO_DRIVER2_LINE16_Pos 0 +#define PIO_DRIVER2_LINE16_Msk (0x3u << PIO_DRIVER2_LINE16_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 16 */ +#define PIO_DRIVER2_LINE16_LO_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE16_ME_DRIVE (0x2u << 0) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE16_HI_DRIVE (0x3u << 0) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE17_Pos 2 +#define PIO_DRIVER2_LINE17_Msk (0x3u << PIO_DRIVER2_LINE17_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 17 */ +#define PIO_DRIVER2_LINE17_LO_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE17_ME_DRIVE (0x2u << 2) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE17_HI_DRIVE (0x3u << 2) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE18_Pos 4 +#define PIO_DRIVER2_LINE18_Msk (0x3u << PIO_DRIVER2_LINE18_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 18 */ +#define PIO_DRIVER2_LINE18_LO_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE18_ME_DRIVE (0x2u << 4) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE18_HI_DRIVE (0x3u << 4) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE19_Pos 6 +#define PIO_DRIVER2_LINE19_Msk (0x3u << PIO_DRIVER2_LINE19_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 19 */ +#define PIO_DRIVER2_LINE19_LO_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE19_ME_DRIVE (0x2u << 6) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE19_HI_DRIVE (0x3u << 6) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE20_Pos 8 +#define PIO_DRIVER2_LINE20_Msk (0x3u << PIO_DRIVER2_LINE20_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 20 */ +#define PIO_DRIVER2_LINE20_LO_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE20_ME_DRIVE (0x2u << 8) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE20_HI_DRIVE (0x3u << 8) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE21_Pos 10 +#define PIO_DRIVER2_LINE21_Msk (0x3u << PIO_DRIVER2_LINE21_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 21 */ +#define PIO_DRIVER2_LINE21_LO_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE21_ME_DRIVE (0x2u << 10) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE21_HI_DRIVE (0x3u << 10) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE22_Pos 12 +#define PIO_DRIVER2_LINE22_Msk (0x3u << PIO_DRIVER2_LINE22_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 22 */ +#define PIO_DRIVER2_LINE22_LO_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE22_ME_DRIVE (0x2u << 12) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE22_HI_DRIVE (0x3u << 12) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE23_Pos 14 +#define PIO_DRIVER2_LINE23_Msk (0x3u << PIO_DRIVER2_LINE23_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 23 */ +#define PIO_DRIVER2_LINE23_LO_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE23_ME_DRIVE (0x2u << 14) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE23_HI_DRIVE (0x3u << 14) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE24_Pos 16 +#define PIO_DRIVER2_LINE24_Msk (0x3u << PIO_DRIVER2_LINE24_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 24 */ +#define PIO_DRIVER2_LINE24_LO_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE24_ME_DRIVE (0x2u << 16) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE24_HI_DRIVE (0x3u << 16) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE25_Pos 18 +#define PIO_DRIVER2_LINE25_Msk (0x3u << PIO_DRIVER2_LINE25_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 25 */ +#define PIO_DRIVER2_LINE25_LO_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE25_ME_DRIVE (0x2u << 18) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE25_HI_DRIVE (0x3u << 18) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE26_Pos 20 +#define PIO_DRIVER2_LINE26_Msk (0x3u << PIO_DRIVER2_LINE26_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 26 */ +#define PIO_DRIVER2_LINE26_LO_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE26_ME_DRIVE (0x2u << 20) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE26_HI_DRIVE (0x3u << 20) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE27_Pos 22 +#define PIO_DRIVER2_LINE27_Msk (0x3u << PIO_DRIVER2_LINE27_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 27 */ +#define PIO_DRIVER2_LINE27_LO_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE27_ME_DRIVE (0x2u << 22) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE27_HI_DRIVE (0x3u << 22) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE28_Pos 24 +#define PIO_DRIVER2_LINE28_Msk (0x3u << PIO_DRIVER2_LINE28_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 28 */ +#define PIO_DRIVER2_LINE28_LO_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE28_ME_DRIVE (0x2u << 24) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE28_HI_DRIVE (0x3u << 24) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE29_Pos 26 +#define PIO_DRIVER2_LINE29_Msk (0x3u << PIO_DRIVER2_LINE29_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 29 */ +#define PIO_DRIVER2_LINE29_LO_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE29_ME_DRIVE (0x2u << 26) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE29_HI_DRIVE (0x3u << 26) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE30_Pos 28 +#define PIO_DRIVER2_LINE30_Msk (0x3u << PIO_DRIVER2_LINE30_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 30 */ +#define PIO_DRIVER2_LINE30_LO_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE30_ME_DRIVE (0x2u << 28) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE30_HI_DRIVE (0x3u << 28) /**< \brief (PIO_DRIVER2) High drive */ +#define PIO_DRIVER2_LINE31_Pos 30 +#define PIO_DRIVER2_LINE31_Msk (0x3u << PIO_DRIVER2_LINE31_Pos) /**< \brief (PIO_DRIVER2) Drive of PIO line 31 */ +#define PIO_DRIVER2_LINE31_LO_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER2) Low drive */ +#define PIO_DRIVER2_LINE31_ME_DRIVE (0x2u << 30) /**< \brief (PIO_DRIVER2) Medium drive */ +#define PIO_DRIVER2_LINE31_HI_DRIVE (0x3u << 30) /**< \brief (PIO_DRIVER2) High drive */ + +/*@}*/ + + +#endif /* _SAMA5_PIO_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pit.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pit.h new file mode 100644 index 000000000..947745d5a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pit.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIT_COMPONENT_ +#define _SAMA5_PIT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Periodic Interval Timer */ +/* ============================================================================= */ +/** \addtogroup SAMA5_PIT Periodic Interval Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pit hardware registers */ +typedef struct { + RwReg PIT_MR; /**< \brief (Pit Offset: 0x00) Mode Register */ + RoReg PIT_SR; /**< \brief (Pit Offset: 0x04) Status Register */ + RoReg PIT_PIVR; /**< \brief (Pit Offset: 0x08) Periodic Interval Value Register */ + RoReg PIT_PIIR; /**< \brief (Pit Offset: 0x0C) Periodic Interval Image Register */ +} Pit; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIT_MR : (PIT Offset: 0x00) Mode Register -------- */ +#define PIT_MR_PIV_Pos 0 +#define PIT_MR_PIV_Msk (0xfffffu << PIT_MR_PIV_Pos) /**< \brief (PIT_MR) Periodic Interval Value */ +#define PIT_MR_PIV(value) ((PIT_MR_PIV_Msk & ((value) << PIT_MR_PIV_Pos))) +#define PIT_MR_PITEN (0x1u << 24) /**< \brief (PIT_MR) Period Interval Timer Enabled */ +#define PIT_MR_PITIEN (0x1u << 25) /**< \brief (PIT_MR) Periodic Interval Timer Interrupt Enable */ +/* -------- PIT_SR : (PIT Offset: 0x04) Status Register -------- */ +#define PIT_SR_PITS (0x1u << 0) /**< \brief (PIT_SR) Periodic Interval Timer Status */ +/* -------- PIT_PIVR : (PIT Offset: 0x08) Periodic Interval Value Register -------- */ +#define PIT_PIVR_CPIV_Pos 0 +#define PIT_PIVR_CPIV_Msk (0xfffffu << PIT_PIVR_CPIV_Pos) /**< \brief (PIT_PIVR) Current Periodic Interval Value */ +#define PIT_PIVR_PICNT_Pos 20 +#define PIT_PIVR_PICNT_Msk (0xfffu << PIT_PIVR_PICNT_Pos) /**< \brief (PIT_PIVR) Periodic Interval Counter */ +/* -------- PIT_PIIR : (PIT Offset: 0x0C) Periodic Interval Image Register -------- */ +#define PIT_PIIR_CPIV_Pos 0 +#define PIT_PIIR_CPIV_Msk (0xfffffu << PIT_PIIR_CPIV_Pos) /**< \brief (PIT_PIIR) Current Periodic Interval Value */ +#define PIT_PIIR_PICNT_Pos 20 +#define PIT_PIIR_PICNT_Msk (0xfffu << PIT_PIIR_PICNT_Pos) /**< \brief (PIT_PIIR) Periodic Interval Counter */ + +/*@}*/ + + +#endif /* _SAMA5_PIT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pmc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pmc.h new file mode 100644 index 000000000..8cd6c077d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pmc.h @@ -0,0 +1,456 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PMC_COMPONENT_ +#define _SAMA5_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + RoReg Reserved1[1]; + WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + RoReg Reserved2[1]; + RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + RoReg Reserved3[1]; + RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + RwReg PMC_SMD; /**< \brief (Pmc Offset: 0x003C) Soft Modem Clock Register */ + RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + RoReg Reserved4[5]; + WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + RoReg Reserved5[4]; + WoReg PMC_PLLICPR; /**< \brief (Pmc Offset: 0x0080) PLL Charge Pump Current Register */ + RoReg Reserved6[24]; + RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + RoReg Reserved7[5]; + WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x00100) Peripheral Clock Enable Register 1 */ + WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x00104) Peripheral Clock Disable Register 1 */ + RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x00108) Peripheral Clock Status Register 1 */ + RwReg PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_DDRCK (0x1u << 2) /**< \brief (PMC_SCER) DDR Clock Enable */ +#define PMC_SCER_SMDCK (0x1u << 4) /**< \brief (PMC_SCER) SMD Clock Enable */ +#define PMC_SCER_UHP (0x1u << 6) /**< \brief (PMC_SCER) USB Host OHCI Clocks Enable */ +#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Clock Enable */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_PCK (0x1u << 0) /**< \brief (PMC_SCDR) Processor Clock Disable */ +#define PMC_SCDR_DDRCK (0x1u << 2) /**< \brief (PMC_SCDR) DDR Clock Disable */ +#define PMC_SCDR_SMDCK (0x1u << 4) /**< \brief (PMC_SCDR) SMD Clock Disable */ +#define PMC_SCDR_UHP (0x1u << 6) /**< \brief (PMC_SCDR) USB Host OHCI Clock Disable */ +#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Clock Enable */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_PCK (0x1u << 0) /**< \brief (PMC_SCSR) Processor Clock Status */ +#define PMC_SCSR_DDRCK (0x1u << 2) /**< \brief (PMC_SCSR) DDR Clock Status */ +#define PMC_SCSR_SMDCK (0x1u << 4) /**< \brief (PMC_SCSR) SMD Clock Status */ +#define PMC_SCSR_UHP (0x1u << 6) /**< \brief (PMC_SCSR) USB Host Port Clock Status */ +#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ +#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ +#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ +#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ +#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ +#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ +#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ +#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ +#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ +#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ +#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ +#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ +#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +#define CKGR_UCKR_BIASEN (0x1u << 24) /**< \brief (CKGR_UCKR) UTMI BIAS Enable */ +#define CKGR_UCKR_BIASCOUNT_Pos 28 +#define CKGR_UCKR_BIASCOUNT_Msk (0xfu << CKGR_UCKR_BIASCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI BIAS Start-up Time */ +#define CKGR_UCKR_BIASCOUNT(value) ((CKGR_UCKR_BIASCOUNT_Msk & ((value) << CKGR_UCKR_BIASCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider A */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_OUTA_Pos 14 +#define CKGR_PLLAR_OUTA_Msk (0x3u << CKGR_PLLAR_OUTA_Pos) /**< \brief (CKGR_PLLAR) PLLA Clock Frequency Range */ +#define CKGR_PLLAR_OUTA(value) ((CKGR_PLLAR_OUTA_Msk & ((value) << CKGR_PLLAR_OUTA_Pos))) +#define CKGR_PLLAR_MULA_Pos 18 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLAR) */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Source Selection */ +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLACK/PLLADIV2 is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Master/Processor Clock Prescaler */ +#define PMC_MCKR_PRES_CLOCK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLOCK_DIV2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLOCK_DIV4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLOCK_DIV8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLOCK_DIV16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLOCK_DIV32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLOCK_DIV64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1.Warning: SysClk DDR and DDRCK are not available. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3.SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. */ +#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA divisor by 2 */ +#define PMC_MCKR_PLLADIV2_NOT_DIV2 (0x0u << 12) /**< \brief (PMC_MCKR) PLLA clock frequency is divided by 1. */ +#define PMC_MCKR_PLLADIV2_DIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA clock frequency is divided by 2. */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB OHCI Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB OHCI Clock. */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_SMD : (PMC Offset: 0x003C) Soft Modem Clock Register -------- */ +#define PMC_SMD_SMDS (0x1u << 0) /**< \brief (PMC_SMD) SMD input clock selection */ +#define PMC_SMD_SMDDIV_Pos 8 +#define PMC_SMD_SMDDIV_Msk (0x1fu << PMC_SMD_SMDDIV_Pos) /**< \brief (PMC_SMD) Divider for SMD Clock. */ +#define PMC_SMD_SMDDIV(value) ((PMC_SMD_SMDDIV_Msk & ((value) << PMC_SMD_SMDDIV_Pos))) +/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLACK/PLLADIV2 is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK_CLK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES_CLOCK (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLOCK_DIV2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLOCK_DIV4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLOCK_DIV8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLOCK_DIV16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLOCK_DIV32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLOCK_DIV64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Enable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UPLL Clock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_PLLICPR : (PMC Offset: 0x0080) PLL Charge Pump Current Register -------- */ +#define PMC_PLLICPR_ICPLLA (0x1u << 0) /**< \brief (PMC_PLLICPR) Charge Pump Current */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x00100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID53_Pos 20 +#define PMC_PCER1_PID53_Msk (0x3u << PMC_PCER1_PID53_Pos) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID53(value) ((PMC_PCER1_PID53_Msk & ((value) << PMC_PCER1_PID53_Pos))) +#define PMC_PCER1_PID54 (0x1u << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ +#define PMC_PCER1_PID55 (0x1u << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +#define PMC_PCER1_PID61 (0x1u << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ +#define PMC_PCER1_PID62 (0x1u << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ +#define PMC_PCER1_PID63 (0x1u << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x00104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID53_Pos 20 +#define PMC_PCDR1_PID53_Msk (0x3u << PMC_PCDR1_PID53_Pos) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID53(value) ((PMC_PCDR1_PID53_Msk & ((value) << PMC_PCDR1_PID53_Pos))) +#define PMC_PCDR1_PID54 (0x1u << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ +#define PMC_PCDR1_PID55 (0x1u << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +#define PMC_PCDR1_PID61 (0x1u << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ +#define PMC_PCDR1_PID62 (0x1u << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ +#define PMC_PCDR1_PID63 (0x1u << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x00108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID53_Pos 20 +#define PMC_PCSR1_PID53_Msk (0x3u << PMC_PCSR1_PID53_Pos) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID54 (0x1u << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ +#define PMC_PCSR1_PID55 (0x1u << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +#define PMC_PCSR1_PID61 (0x1u << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ +#define PMC_PCSR1_PID62 (0x1u << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ +#define PMC_PCSR1_PID63 (0x1u << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_DIV_Pos 16 +#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */ +#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */ +#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */ +#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */ +#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ + +/*@}*/ + + +#endif /* _SAMA5_PMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pwm.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pwm.h new file mode 100644 index 000000000..a09dc823a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_pwm.h @@ -0,0 +1,524 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PWM_COMPONENT_ +#define _SAMA5_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + RoReg Reserved1[1]; + RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + RwReg PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + RoReg Reserved2[3]; + RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + RoReg Reserved3[15]; + RwReg PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + RoReg Reserved4[8]; + WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + RoReg Reserved5[17]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + RoReg Reserved6[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + RoReg Reserved7[96]; + WoReg PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + RoReg Reserved8[7]; + WoReg PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + RoReg Reserved9[7]; + WoReg PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + RoReg Reserved10[7]; + WoReg PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to ) */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to ) */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to ) */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to ) */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to ) */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to ) */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to ) */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to ) */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to ) */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to ) */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ + +/*@}*/ + + +#endif /* _SAMA5_PWM_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_rstc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_rstc.h new file mode 100644 index 000000000..3da95f8e0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_rstc.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_RSTC_COMPONENT_ +#define _SAMA5_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_RSTC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_rtc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_rtc.h new file mode 100644 index 000000000..77253a1af --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_rtc.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_RTC_COMPONENT_ +#define _SAMA5_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMA5_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + + +#endif /* _SAMA5_RTC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sckc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sckc.h new file mode 100644 index 000000000..ee3815232 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sckc.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SCKC_COMPONENT_ +#define _SAMA5_SCKC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Slow Clock Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SCKC Slow Clock Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sckc hardware registers */ +typedef struct { + RwReg SCKC_CR; /**< \brief (Sckc Offset: 0x0) Slow Clock Configuration Register */ +} Sckc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SCKC_CR : (SCKC Offset: 0x0) Slow Clock Configuration Register -------- */ +#define SCKC_CR_RCEN (0x1u << 0) /**< \brief (SCKC_CR) Internal 32 kHz RC Oscillator */ +#define SCKC_CR_OSC32EN (0x1u << 1) /**< \brief (SCKC_CR) 32,768 Hz Oscillator */ +#define SCKC_CR_OSC32BYP (0x1u << 2) /**< \brief (SCKC_CR) 32,768Hz Oscillator Bypass */ +#define SCKC_CR_OSCSEL (0x1u << 3) /**< \brief (SCKC_CR) Slow Clock Selector */ +#define SCKC_CR_OSCSEL_RC (0x0u << 3) /**< \brief (SCKC_CR) Slow clock is internal 32 kHz RC oscillator. */ +#define SCKC_CR_OSCSEL_XTAL (0x1u << 3) /**< \brief (SCKC_CR) Slow clock is 32,768 Hz oscillator. */ + +/*@}*/ + + +#endif /* _SAMA5_SCKC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sfr.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sfr.h new file mode 100644 index 000000000..1e4f3614f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sfr.h @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SFR_COMPONENT_ +#define _SAMA5_SFR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Special Function Registers */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SFR Special Function Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sfr hardware registers */ +typedef struct { + RoReg Reserved1[4]; + RwReg SFR_OHCIICR; /**< \brief (Sfr Offset: 0x10) OHCI Interrupt Configuration Register */ + RoReg SFR_OHCIISR; /**< \brief (Sfr Offset: 0x14) OHCI Interrupt Status Register */ + RoReg Reserved2[2]; + RwReg SFR_AHB; /**< \brief (Sfr Offset: 0x20) AHB Configuration Register */ + RwReg SFR_BRIDGE; /**< \brief (Sfr Offset: 0x24) Bridge Configuration Register */ + RwReg SFR_SECURE; /**< \brief (Sfr Offset: 0x28) Security Configuration Register */ + RoReg Reserved3[1]; + RwReg SFR_UTMICKTRIM; /**< \brief (Sfr Offset: 0x30) UTMI Clock Trimming Register */ + RwReg SFR_UTMIHSTRIM; /**< \brief (Sfr Offset: 0x34) UTMI High Speed Trimming Register */ + RwReg SFR_UTMIFSTRIM; /**< \brief (Sfr Offset: 0x38) UTMI Full Speed Trimming Register */ + RwReg SFR_UTMISWAP; /**< \brief (Sfr Offset: 0x3C) UTMI DP/DM Pin Swapping Register */ + RwReg SFR_EBICFG; /**< \brief (Sfr Offset: 0x40) EBI Configuration Register */ +} Sfr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SFR_OHCIICR : (SFR Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define SFR_OHCIICR_RES0 (0x1u << 0) /**< \brief (SFR_OHCIICR) USB PORTx RESET */ +#define SFR_OHCIICR_RES1 (0x1u << 1) /**< \brief (SFR_OHCIICR) USB PORTx RESET */ +#define SFR_OHCIICR_RES2 (0x1u << 2) /**< \brief (SFR_OHCIICR) USB PORTx RESET */ +#define SFR_OHCIICR_ARIE (0x1u << 4) /**< \brief (SFR_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define SFR_OHCIICR_APPSTART (0x1u << 5) /**< \brief (SFR_OHCIICR) Reserved */ +#define SFR_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (SFR_OHCIICR) OHCI USB DEVICE PULL-UP DISABLE */ +/* -------- SFR_OHCIISR : (SFR Offset: 0x14) OHCI Interrupt Status Register -------- */ +#define SFR_OHCIISR_RIS0 (0x1u << 0) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 0 */ +#define SFR_OHCIISR_RIS1 (0x1u << 1) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 1 */ +#define SFR_OHCIISR_RIS2 (0x1u << 2) /**< \brief (SFR_OHCIISR) OHCI Resume Interrupt Status Port 2 */ +/* -------- SFR_AHB : (SFR Offset: 0x20) AHB Configuration Register -------- */ +#define SFR_AHB_PFETCH10 (0x1u << 10) /**< \brief (SFR_AHB) AHB MASTERx 10 Converter Prefetch */ +#define SFR_AHB_PFETCH10_INCR4 (0x0u << 10) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */ +#define SFR_AHB_PFETCH10_INCR8 (0x1u << 10) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */ +#define SFR_AHB_PFETCH11 (0x1u << 11) /**< \brief (SFR_AHB) AHB MASTERx 11 Converter Prefetch */ +#define SFR_AHB_PFETCH11_INCR4 (0x0u << 11) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */ +#define SFR_AHB_PFETCH11_INCR8 (0x1u << 11) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */ +#define SFR_AHB_PFETCH12 (0x1u << 12) /**< \brief (SFR_AHB) AHB MASTERx 12 Converter Prefetch */ +#define SFR_AHB_PFETCH12_INCR4 (0x0u << 12) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */ +#define SFR_AHB_PFETCH12_INCR8 (0x1u << 12) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */ +#define SFR_AHB_PFETCH13 (0x1u << 13) /**< \brief (SFR_AHB) AHB MASTERx 13 Converter Prefetch */ +#define SFR_AHB_PFETCH13_INCR4 (0x0u << 13) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */ +#define SFR_AHB_PFETCH13_INCR8 (0x1u << 13) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */ +#define SFR_AHB_PFETCH14 (0x1u << 14) /**< \brief (SFR_AHB) AHB MASTERx 14 Converter Prefetch */ +#define SFR_AHB_PFETCH14_INCR4 (0x0u << 14) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 4 beats. */ +#define SFR_AHB_PFETCH14_INCR8 (0x1u << 14) /**< \brief (SFR_AHB) INCR undefined burst converted to burst of 8 beats. */ +#define SFR_AHB_DLBOPT10 (0x1u << 26) /**< \brief (SFR_AHB) AHB MASTERx 10 Converter Define Length Burst Optimization */ +#define SFR_AHB_DLBOPT11 (0x1u << 27) /**< \brief (SFR_AHB) AHB MASTERx 11 Converter Define Length Burst Optimization */ +#define SFR_AHB_DLBOPT12 (0x1u << 28) /**< \brief (SFR_AHB) AHB MASTERx 12 Converter Define Length Burst Optimization */ +#define SFR_AHB_DLBOPT13 (0x1u << 29) /**< \brief (SFR_AHB) AHB MASTERx 13 Converter Define Length Burst Optimization */ +#define SFR_AHB_DLBOPT14 (0x1u << 30) /**< \brief (SFR_AHB) AHB MASTERx 14 Converter Define Length Burst Optimization */ +/* -------- SFR_BRIDGE : (SFR Offset: 0x24) Bridge Configuration Register -------- */ +#define SFR_BRIDGE_APBTURBO (0x1u << 0) /**< \brief (SFR_BRIDGE) AHB to APB Bridge mode */ +#define SFR_BRIDGE_AXI2AHBSEL (0x1u << 8) /**< \brief (SFR_BRIDGE) AXI to AHB bridge for DDR controller selection */ +#define SFR_BRIDGE_AXI2AHBSEL_SINGLE (0x0u << 8) /**< \brief (SFR_BRIDGE) use single port bridge. */ +#define SFR_BRIDGE_AXI2AHBSEL_DUAL (0x1u << 8) /**< \brief (SFR_BRIDGE) use dual port bridge. */ +/* -------- SFR_SECURE : (SFR Offset: 0x28) Security Configuration Register -------- */ +#define SFR_SECURE_ROM (0x1u << 0) /**< \brief (SFR_SECURE) Disable Access to ROM Code */ +#define SFR_SECURE_FUSE (0x1u << 8) /**< \brief (SFR_SECURE) Disable Access to Fuse Controller */ +/* -------- SFR_UTMICKTRIM : (SFR Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define SFR_UTMICKTRIM_FREQ_Pos 0 +#define SFR_UTMICKTRIM_FREQ_Msk (0x3u << SFR_UTMICKTRIM_FREQ_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Reference Clock Frequency */ +#define SFR_UTMICKTRIM_FREQ_12 (0x0u << 0) /**< \brief (SFR_UTMICKTRIM) 12 MHz reference clock */ +#define SFR_UTMICKTRIM_FREQ_16 (0x1u << 0) /**< \brief (SFR_UTMICKTRIM) 16 MHz reference clock */ +#define SFR_UTMICKTRIM_FREQ_24 (0x2u << 0) /**< \brief (SFR_UTMICKTRIM) 24 MHz reference clock */ +#define SFR_UTMICKTRIM_FREQ_48 (0x3u << 0) /**< \brief (SFR_UTMICKTRIM) 48 MHz reference clock */ +#define SFR_UTMICKTRIM_VBG_Pos 16 +#define SFR_UTMICKTRIM_VBG_Msk (0xfu << SFR_UTMICKTRIM_VBG_Pos) /**< \brief (SFR_UTMICKTRIM) UTMI Band Gap Voltage Trimming */ +#define SFR_UTMICKTRIM_VBG(value) ((SFR_UTMICKTRIM_VBG_Msk & ((value) << SFR_UTMICKTRIM_VBG_Pos))) +/* -------- SFR_UTMIHSTRIM : (SFR Offset: 0x34) UTMI High Speed Trimming Register -------- */ +#define SFR_UTMIHSTRIM_SQUELCH_Pos 0 +#define SFR_UTMIHSTRIM_SQUELCH_Msk (0x7u << SFR_UTMIHSTRIM_SQUELCH_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS SQUELCH Voltage Trimming */ +#define SFR_UTMIHSTRIM_SQUELCH(value) ((SFR_UTMIHSTRIM_SQUELCH_Msk & ((value) << SFR_UTMIHSTRIM_SQUELCH_Pos))) +#define SFR_UTMIHSTRIM_DISC_Pos 4 +#define SFR_UTMIHSTRIM_DISC_Msk (0x7u << SFR_UTMIHSTRIM_DISC_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI Disconnect Voltage Trimming */ +#define SFR_UTMIHSTRIM_DISC(value) ((SFR_UTMIHSTRIM_DISC_Msk & ((value) << SFR_UTMIHSTRIM_DISC_Pos))) +#define SFR_UTMIHSTRIM_SLOPE0_Pos 8 +#define SFR_UTMIHSTRIM_SLOPE0_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE0_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */ +#define SFR_UTMIHSTRIM_SLOPE0(value) ((SFR_UTMIHSTRIM_SLOPE0_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE0_Pos))) +#define SFR_UTMIHSTRIM_SLOPE1_Pos 12 +#define SFR_UTMIHSTRIM_SLOPE1_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE1_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */ +#define SFR_UTMIHSTRIM_SLOPE1(value) ((SFR_UTMIHSTRIM_SLOPE1_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE1_Pos))) +#define SFR_UTMIHSTRIM_SLOPE2_Pos 16 +#define SFR_UTMIHSTRIM_SLOPE2_Msk (0x7u << SFR_UTMIHSTRIM_SLOPE2_Pos) /**< \brief (SFR_UTMIHSTRIM) UTMI HS PORTx Transceiver Slope Trimming */ +#define SFR_UTMIHSTRIM_SLOPE2(value) ((SFR_UTMIHSTRIM_SLOPE2_Msk & ((value) << SFR_UTMIHSTRIM_SLOPE2_Pos))) +/* -------- SFR_UTMIFSTRIM : (SFR Offset: 0x38) UTMI Full Speed Trimming Register -------- */ +#define SFR_UTMIFSTRIM_RISE_Pos 0 +#define SFR_UTMIFSTRIM_RISE_Msk (0x7u << SFR_UTMIFSTRIM_RISE_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver output rising slope trimming */ +#define SFR_UTMIFSTRIM_RISE(value) ((SFR_UTMIFSTRIM_RISE_Msk & ((value) << SFR_UTMIFSTRIM_RISE_Pos))) +#define SFR_UTMIFSTRIM_FALL_Pos 4 +#define SFR_UTMIFSTRIM_FALL_Msk (0x7u << SFR_UTMIFSTRIM_FALL_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver output falling slope trimming */ +#define SFR_UTMIFSTRIM_FALL(value) ((SFR_UTMIFSTRIM_FALL_Msk & ((value) << SFR_UTMIFSTRIM_FALL_Pos))) +#define SFR_UTMIFSTRIM_XCVR_Pos 8 +#define SFR_UTMIFSTRIM_XCVR_Msk (0x3u << SFR_UTMIFSTRIM_XCVR_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver crossover voltage trimming */ +#define SFR_UTMIFSTRIM_XCVR(value) ((SFR_UTMIFSTRIM_XCVR_Msk & ((value) << SFR_UTMIFSTRIM_XCVR_Pos))) +#define SFR_UTMIFSTRIM_ZN_Pos 16 +#define SFR_UTMIFSTRIM_ZN_Msk (0x7u << SFR_UTMIFSTRIM_ZN_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver NMOS impedance trimming */ +#define SFR_UTMIFSTRIM_ZN(value) ((SFR_UTMIFSTRIM_ZN_Msk & ((value) << SFR_UTMIFSTRIM_ZN_Pos))) +#define SFR_UTMIFSTRIM_ZP_Pos 20 +#define SFR_UTMIFSTRIM_ZP_Msk (0x7u << SFR_UTMIFSTRIM_ZP_Pos) /**< \brief (SFR_UTMIFSTRIM) FS Transceiver PMOS impedance trimming */ +#define SFR_UTMIFSTRIM_ZP(value) ((SFR_UTMIFSTRIM_ZP_Msk & ((value) << SFR_UTMIFSTRIM_ZP_Pos))) +/* -------- SFR_UTMISWAP : (SFR Offset: 0x3C) UTMI DP/DM Pin Swapping Register -------- */ +#define SFR_UTMISWAP_PORT0 (0x1u << 0) /**< \brief (SFR_UTMISWAP) PORT 0 DP/DM Pin Swapping */ +#define SFR_UTMISWAP_PORT0_NORMAL (0x0u << 0) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */ +#define SFR_UTMISWAP_PORT0_SWAPPED (0x1u << 0) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */ +#define SFR_UTMISWAP_PORT1 (0x1u << 1) /**< \brief (SFR_UTMISWAP) PORT 1 DP/DM Pin Swapping */ +#define SFR_UTMISWAP_PORT1_NORMAL (0x0u << 1) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */ +#define SFR_UTMISWAP_PORT1_SWAPPED (0x1u << 1) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */ +#define SFR_UTMISWAP_PORT2 (0x1u << 2) /**< \brief (SFR_UTMISWAP) PORT 2 DP/DM Pin Swapping */ +#define SFR_UTMISWAP_PORT2_NORMAL (0x0u << 2) /**< \brief (SFR_UTMISWAP) DP/DM normal pinout. */ +#define SFR_UTMISWAP_PORT2_SWAPPED (0x1u << 2) /**< \brief (SFR_UTMISWAP) DP/DM swapped pinout. */ +/* -------- SFR_EBICFG : (SFR Offset: 0x40) EBI Configuration Register -------- */ +#define SFR_EBICFG_DRIVE0_Pos 0 +#define SFR_EBICFG_DRIVE0_Msk (0x3u << SFR_EBICFG_DRIVE0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */ +#define SFR_EBICFG_DRIVE0_LOW (0x0u << 0) /**< \brief (SFR_EBICFG) Low drive level */ +#define SFR_EBICFG_DRIVE0_MEDIUM (0x2u << 0) /**< \brief (SFR_EBICFG) Medium drive level */ +#define SFR_EBICFG_DRIVE0_HIGH (0x3u << 0) /**< \brief (SFR_EBICFG) High drive level */ +#define SFR_EBICFG_PULL0_Pos 2 +#define SFR_EBICFG_PULL0_Msk (0x3u << SFR_EBICFG_PULL0_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */ +#define SFR_EBICFG_PULL0_UP (0x0u << 2) /**< \brief (SFR_EBICFG) Pull-up */ +#define SFR_EBICFG_PULL0_NONE (0x1u << 2) /**< \brief (SFR_EBICFG) No Pull */ +#define SFR_EBICFG_PULL0_DOWN (0x3u << 2) /**< \brief (SFR_EBICFG) Pull-down */ +#define SFR_EBICFG_SCH0 (0x1u << 4) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */ +#define SFR_EBICFG_DRIVE1_Pos 8 +#define SFR_EBICFG_DRIVE1_Msk (0x3u << SFR_EBICFG_DRIVE1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Drive Level */ +#define SFR_EBICFG_DRIVE1_LOW (0x0u << 8) /**< \brief (SFR_EBICFG) Low drive level */ +#define SFR_EBICFG_DRIVE1_MEDIUM (0x2u << 8) /**< \brief (SFR_EBICFG) Medium drive level */ +#define SFR_EBICFG_DRIVE1_HIGH (0x3u << 8) /**< \brief (SFR_EBICFG) High drive level */ +#define SFR_EBICFG_PULL1_Pos 10 +#define SFR_EBICFG_PULL1_Msk (0x3u << SFR_EBICFG_PULL1_Pos) /**< \brief (SFR_EBICFG) EBI Pins Pull Value */ +#define SFR_EBICFG_PULL1_UP (0x0u << 10) /**< \brief (SFR_EBICFG) Pull-up */ +#define SFR_EBICFG_PULL1_NONE (0x1u << 10) /**< \brief (SFR_EBICFG) No Pull */ +#define SFR_EBICFG_PULL1_DOWN (0x3u << 10) /**< \brief (SFR_EBICFG) Pull-down */ +#define SFR_EBICFG_SCH1 (0x1u << 12) /**< \brief (SFR_EBICFG) EBI Pins Schmitt Trigger */ +#define SFR_EBICFG_BMS (0x1u << 16) /**< \brief (SFR_EBICFG) BMS Sampled Value (Read Only) */ +#define SFR_EBICFG_BMS_ROM (0x0u << 16) /**< \brief (SFR_EBICFG) Boot on ROM. */ +#define SFR_EBICFG_BMS_EBI (0x1u << 16) /**< \brief (SFR_EBICFG) Boot on EBI. */ + +/*@}*/ + + +#endif /* _SAMA5_SFR_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sha.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sha.h new file mode 100644 index 000000000..e00ca4a75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_sha.h @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SHA_COMPONENT_ +#define _SAMA5_SHA_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Secure Hash Algorithm */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SHA Secure Hash Algorithm */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sha hardware registers */ +typedef struct { + WoReg SHA_CR; /**< \brief (Sha Offset: 0x00) Control Register */ + RwReg SHA_MR; /**< \brief (Sha Offset: 0x04) Mode Register */ + RoReg Reserved1[2]; + WoReg SHA_IER; /**< \brief (Sha Offset: 0x10) Interrupt Enable Register */ + WoReg SHA_IDR; /**< \brief (Sha Offset: 0x14) Interrupt Disable Register */ + RoReg SHA_IMR; /**< \brief (Sha Offset: 0x18) Interrupt Mask Register */ + RoReg SHA_ISR; /**< \brief (Sha Offset: 0x1C) Interrupt Status Register */ + RoReg Reserved2[8]; + WoReg SHA_IDATAR[16]; /**< \brief (Sha Offset: 0x40) Input Data 0 Register */ + RwReg SHA_IODATAR[16]; /**< \brief (Sha Offset: 0x80) Input/Output Data 0 Register */ +} Sha; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SHA_CR : (SHA Offset: 0x00) Control Register -------- */ +#define SHA_CR_START (0x1u << 0) /**< \brief (SHA_CR) Start Processing */ +#define SHA_CR_FIRST (0x1u << 4) /**< \brief (SHA_CR) First Block of a Message */ +#define SHA_CR_SWRST (0x1u << 8) /**< \brief (SHA_CR) Software Reset */ +/* -------- SHA_MR : (SHA Offset: 0x04) Mode Register -------- */ +#define SHA_MR_SMOD_Pos 0 +#define SHA_MR_SMOD_Msk (0x3u << SHA_MR_SMOD_Pos) /**< \brief (SHA_MR) Start Mode */ +#define SHA_MR_SMOD_MANUAL_START (0x0u << 0) /**< \brief (SHA_MR) Manual Mode */ +#define SHA_MR_SMOD_AUTO_START (0x1u << 0) /**< \brief (SHA_MR) Auto Mode */ +#define SHA_MR_SMOD_IDATAR0_START (0x2u << 0) /**< \brief (SHA_MR) SHA_IDATAR0 access only Auto Mode */ +#define SHA_MR_PROCDLY (0x1u << 4) /**< \brief (SHA_MR) Processing Delay */ +#define SHA_MR_PROCDLY_SHORTEST (0x0u << 4) /**< \brief (SHA_MR) SHA processing runtime is the shortest one */ +#define SHA_MR_PROCDLY_LONGEST (0x1u << 4) /**< \brief (SHA_MR) SHA processing runtime is the longest one */ +#define SHA_MR_ALGO_Pos 8 +#define SHA_MR_ALGO_Msk (0x7u << SHA_MR_ALGO_Pos) /**< \brief (SHA_MR) SHA Algorithm. */ +#define SHA_MR_ALGO_SHA1 (0x0u << 8) /**< \brief (SHA_MR) SHA1 algorithm processed */ +#define SHA_MR_ALGO_SHA256 (0x1u << 8) /**< \brief (SHA_MR) SHA256 algorithm processed */ +#define SHA_MR_ALGO_SHA384 (0x2u << 8) /**< \brief (SHA_MR) SHA384 algorithm processed */ +#define SHA_MR_ALGO_SHA512 (0x3u << 8) /**< \brief (SHA_MR) SHA512 algorithm processed */ +#define SHA_MR_ALGO_SHA224 (0x4u << 8) /**< \brief (SHA_MR) SHA224 algorithm processed */ +#define SHA_MR_DUALBUFF (0x1u << 16) /**< \brief (SHA_MR) Dual Input BUFFer */ +#define SHA_MR_DUALBUFF_INACTIVE (0x0u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. */ +#define SHA_MR_DUALBUFF_ACTIVE (0x1u << 16) /**< \brief (SHA_MR) SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD=0x2. It speeds up the overall runtime of large files. */ +/* -------- SHA_IER : (SHA Offset: 0x10) Interrupt Enable Register -------- */ +#define SHA_IER_DATRDY (0x1u << 0) /**< \brief (SHA_IER) Data Ready Interrupt Enable */ +#define SHA_IER_URAD (0x1u << 8) /**< \brief (SHA_IER) Unspecified Register Access Detection Interrupt Enable */ +/* -------- SHA_IDR : (SHA Offset: 0x14) Interrupt Disable Register -------- */ +#define SHA_IDR_DATRDY (0x1u << 0) /**< \brief (SHA_IDR) Data Ready Interrupt Disable */ +#define SHA_IDR_URAD (0x1u << 8) /**< \brief (SHA_IDR) Unspecified Register Access Detection Interrupt Disable */ +/* -------- SHA_IMR : (SHA Offset: 0x18) Interrupt Mask Register -------- */ +#define SHA_IMR_DATRDY (0x1u << 0) /**< \brief (SHA_IMR) Data Ready Interrupt Mask */ +#define SHA_IMR_URAD (0x1u << 8) /**< \brief (SHA_IMR) Unspecified Register Access Detection Interrupt Mask */ +/* -------- SHA_ISR : (SHA Offset: 0x1C) Interrupt Status Register -------- */ +#define SHA_ISR_DATRDY (0x1u << 0) /**< \brief (SHA_ISR) Data Ready */ +#define SHA_ISR_URAD (0x1u << 8) /**< \brief (SHA_ISR) Unspecified Register Access Detection Status */ +#define SHA_ISR_URAT_Pos 12 +#define SHA_ISR_URAT_Msk (0x7u << SHA_ISR_URAT_Pos) /**< \brief (SHA_ISR) Unspecified Register Access Type */ +/* -------- SHA_IDATAR[16] : (SHA Offset: 0x40) Input Data 0 Register -------- */ +#define SHA_IDATAR_IDATA_Pos 0 +#define SHA_IDATAR_IDATA_Msk (0xffffffffu << SHA_IDATAR_IDATA_Pos) /**< \brief (SHA_IDATAR[16]) Input Data */ +#define SHA_IDATAR_IDATA(value) ((SHA_IDATAR_IDATA_Msk & ((value) << SHA_IDATAR_IDATA_Pos))) +/* -------- SHA_IODATAR[16] : (SHA Offset: 0x80) Input/Output Data 0 Register -------- */ +#define SHA_IODATAR_IODATA_Pos 0 +#define SHA_IODATAR_IODATA_Msk (0xffffffffu << SHA_IODATAR_IODATA_Pos) /**< \brief (SHA_IODATAR[16]) Input/Output Data */ +#define SHA_IODATAR_IODATA(value) ((SHA_IODATAR_IODATA_Msk & ((value) << SHA_IODATAR_IODATA_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_SHA_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_shdwc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_shdwc.h new file mode 100644 index 000000000..491b4e9ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_shdwc.h @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SHDWC_COMPONENT_ +#define _SAMA5_SHDWC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Shutdown Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SHDWC Shutdown Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Shdwc hardware registers */ +typedef struct { + WoReg SHDW_CR; /**< \brief (Shdwc Offset: 0x00) Shutdown Control Register */ + RwReg SHDW_MR; /**< \brief (Shdwc Offset: 0x04) Shutdown Mode Register */ + RoReg SHDW_SR; /**< \brief (Shdwc Offset: 0x08) Shutdown Status Register */ +} Shdwc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SHDW_CR : (SHDWC Offset: 0x00) Shutdown Control Register -------- */ +#define SHDW_CR_SHDW (0x1u << 0) /**< \brief (SHDW_CR) Shutdown Command */ +#define SHDW_CR_KEY_Pos 24 +#define SHDW_CR_KEY_Msk (0xffu << SHDW_CR_KEY_Pos) /**< \brief (SHDW_CR) Password */ +#define SHDW_CR_KEY(value) ((SHDW_CR_KEY_Msk & ((value) << SHDW_CR_KEY_Pos))) +/* -------- SHDW_MR : (SHDWC Offset: 0x04) Shutdown Mode Register -------- */ +#define SHDW_MR_WKMODE0_Pos 0 +#define SHDW_MR_WKMODE0_Msk (0x3u << SHDW_MR_WKMODE0_Pos) /**< \brief (SHDW_MR) Wake-up Mode 0 */ +#define SHDW_MR_WKMODE0(value) ((SHDW_MR_WKMODE0_Msk & ((value) << SHDW_MR_WKMODE0_Pos))) +#define SHDW_MR_CPTWK0_Pos 4 +#define SHDW_MR_CPTWK0_Msk (0xfu << SHDW_MR_CPTWK0_Pos) /**< \brief (SHDW_MR) Counter on Wake-up 0 */ +#define SHDW_MR_CPTWK0(value) ((SHDW_MR_CPTWK0_Msk & ((value) << SHDW_MR_CPTWK0_Pos))) +#define SHDW_MR_RTCWKEN (0x1u << 17) /**< \brief (SHDW_MR) Real-time Clock Wake-up Enable */ +/* -------- SHDW_SR : (SHDWC Offset: 0x08) Shutdown Status Register -------- */ +#define SHDW_SR_WAKEUP0 (0x1u << 0) /**< \brief (SHDW_SR) Wake-up 0 Status */ +#define SHDW_SR_RTCWK (0x1u << 17) /**< \brief (SHDW_SR) Real-time Clock Wake-up */ + +/*@}*/ + + +#endif /* _SAMA5_SHDWC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_smc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_smc.h new file mode 100644 index 000000000..1d7e11e83 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_smc.h @@ -0,0 +1,738 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SMC_COMPONENT_ +#define _SAMA5_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */ + RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */ +} SmcCs_number; +/** \brief SmcPmecc hardware registers */ +typedef struct { + RwReg SMC_PMECC[11]; /**< \brief (SmcPmecc Offset: 0x0) PMECC Redundancy x Register */ + RoReg Reserved1[5]; +} SmcPmecc; +/** \brief SmcRem hardware registers */ +typedef struct { + RwReg SMC_REM[12]; /**< \brief (SmcRem Offset: 0x0) PMECC Remainder x Register */ + RoReg Reserved2[4]; +} SmcRem; +/** \brief Smc hardware registers */ +#define SMCPMECC_NUMBER 8 +#define SMCREM_NUMBER 8 +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */ + WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */ + RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */ + WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */ + WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */ + RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */ + RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */ + RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */ + WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */ + RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */ + RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */ + RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */ + RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */ + RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */ + RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */ + RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */ + RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */ + RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */ + RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */ + RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */ + RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */ + RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */ + RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */ + RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */ + RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */ + RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */ + RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */ + RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */ + RwReg SMC_PMECCFG; /**< \brief (Smc Offset: 0x70) PMECC Configuration Register */ + RwReg SMC_PMECCSAREA; /**< \brief (Smc Offset: 0x74) PMECC Spare Area Size Register */ + RwReg SMC_PMECCSADDR; /**< \brief (Smc Offset: 0x78) PMECC Start Address Register */ + RwReg SMC_PMECCEADDR; /**< \brief (Smc Offset: 0x7C) PMECC End Address Register */ + RoReg Reserved1[1]; + WoReg SMC_PMECCTRL; /**< \brief (Smc Offset: 0x84) PMECC Control Register */ + RoReg SMC_PMECCSR; /**< \brief (Smc Offset: 0x88) PMECC Status Register */ + WoReg SMC_PMECCIER; /**< \brief (Smc Offset: 0x8C) PMECC Interrupt Enable register */ + WoReg SMC_PMECCIDR; /**< \brief (Smc Offset: 0x90) PMECC Interrupt Disable Register */ + RoReg SMC_PMECCIMR; /**< \brief (Smc Offset: 0x94) PMECC Interrupt Mask Register */ + RoReg SMC_PMECCISR; /**< \brief (Smc Offset: 0x98) PMECC Interrupt Status Register */ + RoReg Reserved2[5]; + SmcPmecc SMC_PMECC[SMCPMECC_NUMBER]; /**< \brief (Smc Offset: 0xB0) sec_num = 0 .. 7 */ + SmcRem SMC_REM[SMCREM_NUMBER]; /**< \brief (Smc Offset: 0x2B0) sec_num = 0 .. 7 */ + RoReg Reserved3[20]; + RwReg SMC_ELCFG; /**< \brief (Smc Offset: 0x500) PMECC Error Location Configuration Register */ + RoReg SMC_ELPRIM; /**< \brief (Smc Offset: 0x504) PMECC Error Location Primitive Register */ + WoReg SMC_ELEN; /**< \brief (Smc Offset: 0x508) PMECC Error Location Enable Register */ + WoReg SMC_ELDIS; /**< \brief (Smc Offset: 0x50C) PMECC Error Location Disable Register */ + RoReg SMC_ELSR; /**< \brief (Smc Offset: 0x510) PMECC Error Location Status Register */ + WoReg SMC_ELIER; /**< \brief (Smc Offset: 0x514) PMECC Error Location Interrupt Enable register */ + WoReg SMC_ELIDR; /**< \brief (Smc Offset: 0x518) PMECC Error Location Interrupt Disable Register */ + RoReg SMC_ELIMR; /**< \brief (Smc Offset: 0x51C) PMECC Error Location Interrupt Mask Register */ + RoReg SMC_ELISR; /**< \brief (Smc Offset: 0x520) PMECC Error Location Interrupt Status Register */ + RoReg Reserved4[1]; + RwReg SMC_SIGMA0; /**< \brief (Smc Offset: 0x528) PMECC Error Location SIGMA 0 Register */ + RwReg SMC_SIGMA1; /**< \brief (Smc Offset: 0x52C) PMECC Error Location SIGMA 1 Register */ + RwReg SMC_SIGMA2; /**< \brief (Smc Offset: 0x530) PMECC Error Location SIGMA 2 Register */ + RwReg SMC_SIGMA3; /**< \brief (Smc Offset: 0x534) PMECC Error Location SIGMA 3 Register */ + RwReg SMC_SIGMA4; /**< \brief (Smc Offset: 0x538) PMECC Error Location SIGMA 4 Register */ + RwReg SMC_SIGMA5; /**< \brief (Smc Offset: 0x53C) PMECC Error Location SIGMA 5 Register */ + RwReg SMC_SIGMA6; /**< \brief (Smc Offset: 0x540) PMECC Error Location SIGMA 6 Register */ + RwReg SMC_SIGMA7; /**< \brief (Smc Offset: 0x544) PMECC Error Location SIGMA 7 Register */ + RwReg SMC_SIGMA8; /**< \brief (Smc Offset: 0x548) PMECC Error Location SIGMA 8 Register */ + RwReg SMC_SIGMA9; /**< \brief (Smc Offset: 0x54C) PMECC Error Location SIGMA 9 Register */ + RwReg SMC_SIGMA10; /**< \brief (Smc Offset: 0x550) PMECC Error Location SIGMA 10 Register */ + RwReg SMC_SIGMA11; /**< \brief (Smc Offset: 0x554) PMECC Error Location SIGMA 11 Register */ + RwReg SMC_SIGMA12; /**< \brief (Smc Offset: 0x558) PMECC Error Location SIGMA 12 Register */ + RwReg SMC_SIGMA13; /**< \brief (Smc Offset: 0x55C) PMECC Error Location SIGMA 13 Register */ + RwReg SMC_SIGMA14; /**< \brief (Smc Offset: 0x560) PMECC Error Location SIGMA 14 Register */ + RwReg SMC_SIGMA15; /**< \brief (Smc Offset: 0x564) PMECC Error Location SIGMA 15 Register */ + RwReg SMC_SIGMA16; /**< \brief (Smc Offset: 0x568) PMECC Error Location SIGMA 16 Register */ + RwReg SMC_SIGMA17; /**< \brief (Smc Offset: 0x56C) PMECC Error Location SIGMA 17 Register */ + RwReg SMC_SIGMA18; /**< \brief (Smc Offset: 0x570) PMECC Error Location SIGMA 18 Register */ + RwReg SMC_SIGMA19; /**< \brief (Smc Offset: 0x574) PMECC Error Location SIGMA 19 Register */ + RwReg SMC_SIGMA20; /**< \brief (Smc Offset: 0x578) PMECC Error Location SIGMA 20 Register */ + RwReg SMC_SIGMA21; /**< \brief (Smc Offset: 0x57C) PMECC Error Location SIGMA 21 Register */ + RwReg SMC_SIGMA22; /**< \brief (Smc Offset: 0x580) PMECC Error Location SIGMA 22 Register */ + RwReg SMC_SIGMA23; /**< \brief (Smc Offset: 0x584) PMECC Error Location SIGMA 23 Register */ + RwReg SMC_SIGMA24; /**< \brief (Smc Offset: 0x588) PMECC Error Location SIGMA 24 Register */ + RoReg SMC_ERRLOC[24]; /**< \brief (Smc Offset: 0x58C) PMECC Error Location 0 Register */ + RoReg Reserved5[5]; + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x600) CS_number = 0 .. 3 */ + RoReg Reserved6[20]; + RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x6A0) SMC OCMS Register */ + WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x6A4) SMC OCMS KEY1 Register */ + WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x6A8) SMC OCMS KEY2 Register */ + RoReg Reserved7[14]; + WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x6E4) SMC Write Protection Control Register */ + RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x6E8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */ +#define SMC_CFG_PAGESIZE_Pos 0 +#define SMC_CFG_PAGESIZE_Msk (0x7u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */ +#define SMC_CFG_PAGESIZE_PS512 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes */ +#define SMC_CFG_PAGESIZE_PS1024 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes */ +#define SMC_CFG_PAGESIZE_PS2048 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes */ +#define SMC_CFG_PAGESIZE_PS4096 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes */ +#define SMC_CFG_PAGESIZE_PS8192 (0x4u << 0) /**< \brief (SMC_CFG) Main area 8192 Bytes */ +#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */ +#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */ +#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */ +#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */ +#define SMC_CFG_DTOCYC_Pos 16 +#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */ +#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos))) +#define SMC_CFG_DTOMUL_Pos 20 +#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */ +#define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */ +#define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */ +#define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */ +#define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */ +#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */ +#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */ +#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */ +#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */ +#define SMC_CFG_NFCSPARESIZE_Pos 24 +#define SMC_CFG_NFCSPARESIZE_Msk (0x7fu << SMC_CFG_NFCSPARESIZE_Pos) /**< \brief (SMC_CFG) NAND Flash Spare Area Size Retrieved by the Host Controller */ +#define SMC_CFG_NFCSPARESIZE(value) ((SMC_CFG_NFCSPARESIZE_Msk & ((value) << SMC_CFG_NFCSPARESIZE_Pos))) +/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */ +#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */ +#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */ +/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */ +#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller Status (this field cannot be reset) */ +#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */ +#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */ +#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */ +#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */ +#define SMC_SR_NFCSID_Pos 12 +#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */ +#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */ +#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */ +#define SMC_SR_ECCRDY (0x1u << 18) /**< \brief (SMC_SR) Hamming ECC Ready */ +#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */ +#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */ +#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */ +#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */ +#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */ +/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */ +#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */ +#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */ +#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */ +#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */ +#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */ +#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */ +#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */ +#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */ +#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */ +/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */ +#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */ +#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */ +#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */ +#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */ +#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */ +#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */ +#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */ +#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */ +#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */ +/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */ +#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */ +#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */ +#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */ +#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */ +#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */ +#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */ +#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */ +#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */ +#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */ +/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */ +#define SMC_ADDR_ADDR_CYCLE0_Pos 0 +#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address Cycle 0 */ +#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos))) +/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */ +#define SMC_BANK_BANK (0x1u << 0) /**< \brief (SMC_BANK) Bank Identifier */ +/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */ +#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */ +#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */ +/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */ +#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0 +#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS512 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Words */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS1024 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Words */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS2048 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Words */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS4096 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Words */ +#define SMC_ECC_MD_TYPCORREC_Pos 4 +#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */ +#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */ +#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */ +#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */ +#define SMC_ECC_MD_HAMMING (0x1u << 8) /**< \brief (SMC_ECC_MD) Hamming Error Correcting Code Selected */ +/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */ +#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */ +#define SMC_ECC_SR1_ECCERR0 (0x1u << 1) /**< \brief (SMC_ECC_SR1) ECC Error */ +#define SMC_ECC_SR1_MULERR0 (0x1u << 2) /**< \brief (SMC_ECC_SR1) Multiple Error */ +#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th Bytes or the 512nd and the 1023rd Bytes */ +#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th Bytes or between the 512nd and the 1023rd Bytes */ +#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th Bytes or between the 512nd and the 1023rd Bytes */ +#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th Bytes or between the 1024th and the 1535th Bytes */ +#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th Bytes or between the 1024th and the 1535th Bytes */ +#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th Bytes or between the 1024th and the 1535th Bytes */ +#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd Bytes or between the 1536th and the 2047th Bytes */ +#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd Bytes or between the 1536th and the 2047th Bytes */ +#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd Bytes or between the 1536th and the 2047th Bytes */ +#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th Bytes or between the 2048th and the 2559th Bytes */ +#define SMC_ECC_SR1_ECCERR4 (0x1u << 17) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th Bytes or between the 2048th and the 2559th Bytes */ +#define SMC_ECC_SR1_MULERR4 (0x1u << 18) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 1024th and the 1279th Bytes or between the 2048th and the 2559th Bytes */ +#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th Bytes or between the 2560th and the 3071st Bytes */ +#define SMC_ECC_SR1_ECCERR5 (0x1u << 21) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th Bytes or between the 2560th and the 3071st Bytes */ +#define SMC_ECC_SR1_MULERR5 (0x1u << 22) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 1280th and the 1535th Bytes or between the 2560th and the 3071st Bytes */ +#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st Bytes or between the 3072nd and the 3583rd Bytes */ +#define SMC_ECC_SR1_ECCERR6 (0x1u << 25) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st Bytes or between the 3072nd and the 3583rd Bytes */ +#define SMC_ECC_SR1_MULERR6 (0x1u << 26) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 1536th and the 1791st Bytes or between the 3072nd and the 3583rd Bytes */ +#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th Bytes or between the 3584th and the 4095th Bytes */ +#define SMC_ECC_SR1_ECCERR7 (0x1u << 29) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th Bytes or between the 3584th and the 4095th Bytes */ +#define SMC_ECC_SR1_MULERR7 (0x1u << 30) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 1792nd and the 2047th Bytes or between the 3584th and the 4095th Bytes */ +/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */ +#define SMC_ECC_PR0_BITADDR_Pos 0 +#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */ +#define SMC_ECC_PR0_WORDADDR_Pos 4 +#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */ +#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0 +#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3 +#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_NPARITY_Pos 12 +#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */ +#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0 +#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */ +/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */ +#define SMC_ECC_PR1_NPARITY_Pos 0 +#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */ +#define SMC_ECC_PR1_BITADDR_Pos 0 +#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR1_WORDADDR_Pos 3 +#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12 +#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */ +#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */ +/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */ +#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd Bytes */ +#define SMC_ECC_SR2_ECCERR8 (0x1u << 1) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd Bytes */ +#define SMC_ECC_SR2_MULERR8 (0x1u << 2) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2048th and the 2303rd Bytes */ +#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th Bytes */ +#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th Bytes */ +#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th Bytes */ +#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th Bytes */ +#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th Bytes */ +#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th Bytes */ +#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st Bytes */ +#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st Bytes */ +#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st Bytes */ +#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th Bytes */ +#define SMC_ECC_SR2_ECCERR12 (0x1u << 17) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th Bytes */ +#define SMC_ECC_SR2_MULERR12 (0x1u << 18) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 3072nd and the 3327th Bytes */ +#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd Bytes */ +#define SMC_ECC_SR2_ECCERR13 (0x1u << 21) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd Bytes */ +#define SMC_ECC_SR2_MULERR13 (0x1u << 22) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 3328th and the 3583rd Bytes */ +#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th Bytes */ +#define SMC_ECC_SR2_ECCERR14 (0x1u << 25) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th Bytes */ +#define SMC_ECC_SR2_MULERR14 (0x1u << 26) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 3584th and the 3839th Bytes */ +#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th Bytes */ +#define SMC_ECC_SR2_ECCERR15 (0x1u << 29) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th Bytes */ +#define SMC_ECC_SR2_MULERR15 (0x1u << 30) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 3840th and the 4095th Bytes */ +/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */ +#define SMC_ECC_PR2_BITADDR_Pos 0 +#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR2_WORDADDR_Pos 3 +#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR2_NPARITY_Pos 12 +#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */ +#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */ +/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */ +#define SMC_ECC_PR3_BITADDR_Pos 0 +#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR3_WORDADDR_Pos 3 +#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR3_NPARITY_Pos 12 +#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */ +#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */ +/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */ +#define SMC_ECC_PR4_BITADDR_Pos 0 +#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR4_WORDADDR_Pos 3 +#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR4_NPARITY_Pos 12 +#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */ +#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */ +/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */ +#define SMC_ECC_PR5_BITADDR_Pos 0 +#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR5_WORDADDR_Pos 3 +#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR5_NPARITY_Pos 12 +#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */ +#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */ +/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */ +#define SMC_ECC_PR6_BITADDR_Pos 0 +#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR6_WORDADDR_Pos 3 +#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR6_NPARITY_Pos 12 +#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */ +#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */ +/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */ +#define SMC_ECC_PR7_BITADDR_Pos 0 +#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR7_WORDADDR_Pos 3 +#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR7_NPARITY_Pos 12 +#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */ +#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */ +/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */ +#define SMC_ECC_PR8_BITADDR_Pos 0 +#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR8_WORDADDR_Pos 3 +#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR8_NPARITY_Pos 12 +#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */ +/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */ +#define SMC_ECC_PR9_BITADDR_Pos 0 +#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR9_WORDADDR_Pos 3 +#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR9_NPARITY_Pos 12 +#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */ +/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */ +#define SMC_ECC_PR10_BITADDR_Pos 0 +#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR10_WORDADDR_Pos 3 +#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR10_NPARITY_Pos 12 +#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */ +/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */ +#define SMC_ECC_PR11_BITADDR_Pos 0 +#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR11_WORDADDR_Pos 3 +#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR11_NPARITY_Pos 12 +#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */ +/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */ +#define SMC_ECC_PR12_BITADDR_Pos 0 +#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR12_WORDADDR_Pos 3 +#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR12_NPARITY_Pos 12 +#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */ +/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */ +#define SMC_ECC_PR13_BITADDR_Pos 0 +#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR13_WORDADDR_Pos 3 +#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR13_NPARITY_Pos 12 +#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */ +/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */ +#define SMC_ECC_PR14_BITADDR_Pos 0 +#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR14_WORDADDR_Pos 3 +#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR14_NPARITY_Pos 12 +#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */ +/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */ +#define SMC_ECC_PR15_BITADDR_Pos 0 +#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR15_WORDADDR_Pos 3 +#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR15_NPARITY_Pos 12 +#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */ +/* -------- SMC_PMECCFG : (SMC Offset: 0x70) PMECC Configuration Register -------- */ +#define SMC_PMECCFG_BCH_ERR_Pos 0 +#define SMC_PMECCFG_BCH_ERR_Msk (0x7u << SMC_PMECCFG_BCH_ERR_Pos) /**< \brief (SMC_PMECCFG) Error Correcting Capability */ +#define SMC_PMECCFG_BCH_ERR_BCH_ERR2 (0x0u << 0) /**< \brief (SMC_PMECCFG) 2 errors */ +#define SMC_PMECCFG_BCH_ERR_BCH_ERR4 (0x1u << 0) /**< \brief (SMC_PMECCFG) 4 errors */ +#define SMC_PMECCFG_BCH_ERR_BCH_ERR8 (0x2u << 0) /**< \brief (SMC_PMECCFG) 8 errors */ +#define SMC_PMECCFG_BCH_ERR_BCH_ERR12 (0x3u << 0) /**< \brief (SMC_PMECCFG) 12 errors */ +#define SMC_PMECCFG_BCH_ERR_BCH_ERR24 (0x4u << 0) /**< \brief (SMC_PMECCFG) 24 errors */ +#define SMC_PMECCFG_SECTORSZ (0x1u << 4) /**< \brief (SMC_PMECCFG) Sector Size */ +#define SMC_PMECCFG_PAGESIZE_Pos 8 +#define SMC_PMECCFG_PAGESIZE_Msk (0x3u << SMC_PMECCFG_PAGESIZE_Pos) /**< \brief (SMC_PMECCFG) Number of Sectors in the Page */ +#define SMC_PMECCFG_PAGESIZE_PAGESIZE_1SEC (0x0u << 8) /**< \brief (SMC_PMECCFG) 1 sector for main area (512 or 1024 Bytes) */ +#define SMC_PMECCFG_PAGESIZE_PAGESIZE_2SEC (0x1u << 8) /**< \brief (SMC_PMECCFG) 2 sectors for main area (1024 or 2048 Bytes) */ +#define SMC_PMECCFG_PAGESIZE_PAGESIZE_4SEC (0x2u << 8) /**< \brief (SMC_PMECCFG) 4 sectors for main area (2048 or 4096 Bytes) */ +#define SMC_PMECCFG_PAGESIZE_PAGESIZE_8SEC (0x3u << 8) /**< \brief (SMC_PMECCFG) 8 sectors for main area (4096 or 8192 Bytes) */ +#define SMC_PMECCFG_NANDWR (0x1u << 12) /**< \brief (SMC_PMECCFG) NAND Write Access */ +#define SMC_PMECCFG_SPAREEN (0x1u << 16) /**< \brief (SMC_PMECCFG) Spare Enable */ +#define SMC_PMECCFG_AUTO (0x1u << 20) /**< \brief (SMC_PMECCFG) Automatic Mode Enable */ +/* -------- SMC_PMECCSAREA : (SMC Offset: 0x74) PMECC Spare Area Size Register -------- */ +#define SMC_PMECCSAREA_SPARESIZE_Pos 0 +#define SMC_PMECCSAREA_SPARESIZE_Msk (0x1ffu << SMC_PMECCSAREA_SPARESIZE_Pos) /**< \brief (SMC_PMECCSAREA) Spare Area Size */ +#define SMC_PMECCSAREA_SPARESIZE(value) ((SMC_PMECCSAREA_SPARESIZE_Msk & ((value) << SMC_PMECCSAREA_SPARESIZE_Pos))) +/* -------- SMC_PMECCSADDR : (SMC Offset: 0x78) PMECC Start Address Register -------- */ +#define SMC_PMECCSADDR_STARTADDR_Pos 0 +#define SMC_PMECCSADDR_STARTADDR_Msk (0x1ffu << SMC_PMECCSADDR_STARTADDR_Pos) /**< \brief (SMC_PMECCSADDR) ECC Area Start Address */ +#define SMC_PMECCSADDR_STARTADDR(value) ((SMC_PMECCSADDR_STARTADDR_Msk & ((value) << SMC_PMECCSADDR_STARTADDR_Pos))) +/* -------- SMC_PMECCEADDR : (SMC Offset: 0x7C) PMECC End Address Register -------- */ +#define SMC_PMECCEADDR_ENDADDR_Pos 0 +#define SMC_PMECCEADDR_ENDADDR_Msk (0x1ffu << SMC_PMECCEADDR_ENDADDR_Pos) /**< \brief (SMC_PMECCEADDR) ECC Area End Address */ +#define SMC_PMECCEADDR_ENDADDR(value) ((SMC_PMECCEADDR_ENDADDR_Msk & ((value) << SMC_PMECCEADDR_ENDADDR_Pos))) +/* -------- SMC_PMECCTRL : (SMC Offset: 0x84) PMECC Control Register -------- */ +#define SMC_PMECCTRL_RST (0x1u << 0) /**< \brief (SMC_PMECCTRL) Reset the PMECC Module */ +#define SMC_PMECCTRL_DATA (0x1u << 1) /**< \brief (SMC_PMECCTRL) Start a Data Phase */ +#define SMC_PMECCTRL_USER (0x1u << 2) /**< \brief (SMC_PMECCTRL) Start a User Mode Phase */ +#define SMC_PMECCTRL_ENABLE (0x1u << 4) /**< \brief (SMC_PMECCTRL) PMECC Enable */ +#define SMC_PMECCTRL_DISABLE (0x1u << 5) /**< \brief (SMC_PMECCTRL) PMECC Enable */ +/* -------- SMC_PMECCSR : (SMC Offset: 0x88) PMECC Status Register -------- */ +#define SMC_PMECCSR_BUSY (0x1u << 0) /**< \brief (SMC_PMECCSR) The kernel of the PMECC is busy */ +#define SMC_PMECCSR_ENABLE (0x1u << 4) /**< \brief (SMC_PMECCSR) PMECC Enable bit */ +/* -------- SMC_PMECCIER : (SMC Offset: 0x8C) PMECC Interrupt Enable register -------- */ +#define SMC_PMECCIER_ERRIE (0x1u << 0) /**< \brief (SMC_PMECCIER) Error Interrupt Enable */ +/* -------- SMC_PMECCIDR : (SMC Offset: 0x90) PMECC Interrupt Disable Register -------- */ +#define SMC_PMECCIDR_ERRID (0x1u << 0) /**< \brief (SMC_PMECCIDR) Error Interrupt Disable */ +/* -------- SMC_PMECCIMR : (SMC Offset: 0x94) PMECC Interrupt Mask Register -------- */ +#define SMC_PMECCIMR_ERRIM (0x1u << 0) /**< \brief (SMC_PMECCIMR) Error Interrupt Mask */ +/* -------- SMC_PMECCISR : (SMC Offset: 0x98) PMECC Interrupt Status Register -------- */ +#define SMC_PMECCISR_ERRIS_Pos 0 +#define SMC_PMECCISR_ERRIS_Msk (0xffu << SMC_PMECCISR_ERRIS_Pos) /**< \brief (SMC_PMECCISR) Error Interrupt Status Register */ +/* -------- SMC_PMECC[11] : (SMC Offset: N/A) PMECC Redundancy x Register -------- */ +#define SMC_PMECC_ECC_Pos 0 +#define SMC_PMECC_ECC_Msk (0xffffffffu << SMC_PMECC_ECC_Pos) /**< \brief (SMC_PMECC[11]) BCH Redundancy */ +/* -------- SMC_REM[12] : (SMC Offset: N/A) PMECC Remainder x Register -------- */ +#define SMC_REM_REM2NP1_Pos 0 +#define SMC_REM_REM2NP1_Msk (0x3fffu << SMC_REM_REM2NP1_Pos) /**< \brief (SMC_REM[12]) BCH Remainder 2 * N + 1 */ +#define SMC_REM_REM2NP3_Pos 16 +#define SMC_REM_REM2NP3_Msk (0x3fffu << SMC_REM_REM2NP3_Pos) /**< \brief (SMC_REM[12]) BCH Remainder 2 * N + 3 */ +/* -------- SMC_ELCFG : (SMC Offset: 0x500) PMECC Error Location Configuration Register -------- */ +#define SMC_ELCFG_SECTORSZ (0x1u << 0) /**< \brief (SMC_ELCFG) Sector Size */ +#define SMC_ELCFG_ERRNUM_Pos 16 +#define SMC_ELCFG_ERRNUM_Msk (0x1fu << SMC_ELCFG_ERRNUM_Pos) /**< \brief (SMC_ELCFG) Number of Errors */ +#define SMC_ELCFG_ERRNUM(value) ((SMC_ELCFG_ERRNUM_Msk & ((value) << SMC_ELCFG_ERRNUM_Pos))) +/* -------- SMC_ELPRIM : (SMC Offset: 0x504) PMECC Error Location Primitive Register -------- */ +#define SMC_ELPRIM_PRIMITIV_Pos 0 +#define SMC_ELPRIM_PRIMITIV_Msk (0xffffu << SMC_ELPRIM_PRIMITIV_Pos) /**< \brief (SMC_ELPRIM) Primitive Polynomial */ +/* -------- SMC_ELEN : (SMC Offset: 0x508) PMECC Error Location Enable Register -------- */ +#define SMC_ELEN_ENINIT_Pos 0 +#define SMC_ELEN_ENINIT_Msk (0x3fffu << SMC_ELEN_ENINIT_Pos) /**< \brief (SMC_ELEN) Error Location Enable */ +#define SMC_ELEN_ENINIT(value) ((SMC_ELEN_ENINIT_Msk & ((value) << SMC_ELEN_ENINIT_Pos))) +/* -------- SMC_ELDIS : (SMC Offset: 0x50C) PMECC Error Location Disable Register -------- */ +#define SMC_ELDIS_DIS (0x1u << 0) /**< \brief (SMC_ELDIS) Disable Error Location Engine */ +/* -------- SMC_ELSR : (SMC Offset: 0x510) PMECC Error Location Status Register -------- */ +#define SMC_ELSR_BUSY (0x1u << 0) /**< \brief (SMC_ELSR) Error Location Engine Busy */ +/* -------- SMC_ELIER : (SMC Offset: 0x514) PMECC Error Location Interrupt Enable register -------- */ +#define SMC_ELIER_DONE (0x1u << 0) /**< \brief (SMC_ELIER) Computation Terminated Interrupt Enable */ +/* -------- SMC_ELIDR : (SMC Offset: 0x518) PMECC Error Location Interrupt Disable Register -------- */ +#define SMC_ELIDR_DONE (0x1u << 0) /**< \brief (SMC_ELIDR) Computation Terminated Interrupt Disable */ +/* -------- SMC_ELIMR : (SMC Offset: 0x51C) PMECC Error Location Interrupt Mask Register -------- */ +#define SMC_ELIMR_DONE (0x1u << 0) /**< \brief (SMC_ELIMR) Computation Terminated Interrupt Mask */ +/* -------- SMC_ELISR : (SMC Offset: 0x520) PMECC Error Location Interrupt Status Register -------- */ +#define SMC_ELISR_DONE (0x1u << 0) /**< \brief (SMC_ELISR) Computation Terminated Interrupt Status */ +#define SMC_ELISR_ERR_CNT_Pos 8 +#define SMC_ELISR_ERR_CNT_Msk (0x1fu << SMC_ELISR_ERR_CNT_Pos) /**< \brief (SMC_ELISR) Error Counter value */ +/* -------- SMC_SIGMA0 : (SMC Offset: 0x528) PMECC Error Location SIGMA 0 Register -------- */ +#define SMC_SIGMA0_SIGMA0_Pos 0 +#define SMC_SIGMA0_SIGMA0_Msk (0x3fffu << SMC_SIGMA0_SIGMA0_Pos) /**< \brief (SMC_SIGMA0) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA0_SIGMA0(value) ((SMC_SIGMA0_SIGMA0_Msk & ((value) << SMC_SIGMA0_SIGMA0_Pos))) +/* -------- SMC_SIGMA1 : (SMC Offset: 0x52C) PMECC Error Location SIGMA 1 Register -------- */ +#define SMC_SIGMA1_SIGMA1_Pos 0 +#define SMC_SIGMA1_SIGMA1_Msk (0x3fffu << SMC_SIGMA1_SIGMA1_Pos) /**< \brief (SMC_SIGMA1) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA1_SIGMA1(value) ((SMC_SIGMA1_SIGMA1_Msk & ((value) << SMC_SIGMA1_SIGMA1_Pos))) +/* -------- SMC_SIGMA2 : (SMC Offset: 0x530) PMECC Error Location SIGMA 2 Register -------- */ +#define SMC_SIGMA2_SIGMA2_Pos 0 +#define SMC_SIGMA2_SIGMA2_Msk (0x3fffu << SMC_SIGMA2_SIGMA2_Pos) /**< \brief (SMC_SIGMA2) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA2_SIGMA2(value) ((SMC_SIGMA2_SIGMA2_Msk & ((value) << SMC_SIGMA2_SIGMA2_Pos))) +/* -------- SMC_SIGMA3 : (SMC Offset: 0x534) PMECC Error Location SIGMA 3 Register -------- */ +#define SMC_SIGMA3_SIGMA3_Pos 0 +#define SMC_SIGMA3_SIGMA3_Msk (0x3fffu << SMC_SIGMA3_SIGMA3_Pos) /**< \brief (SMC_SIGMA3) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA3_SIGMA3(value) ((SMC_SIGMA3_SIGMA3_Msk & ((value) << SMC_SIGMA3_SIGMA3_Pos))) +/* -------- SMC_SIGMA4 : (SMC Offset: 0x538) PMECC Error Location SIGMA 4 Register -------- */ +#define SMC_SIGMA4_SIGMA4_Pos 0 +#define SMC_SIGMA4_SIGMA4_Msk (0x3fffu << SMC_SIGMA4_SIGMA4_Pos) /**< \brief (SMC_SIGMA4) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA4_SIGMA4(value) ((SMC_SIGMA4_SIGMA4_Msk & ((value) << SMC_SIGMA4_SIGMA4_Pos))) +/* -------- SMC_SIGMA5 : (SMC Offset: 0x53C) PMECC Error Location SIGMA 5 Register -------- */ +#define SMC_SIGMA5_SIGMA5_Pos 0 +#define SMC_SIGMA5_SIGMA5_Msk (0x3fffu << SMC_SIGMA5_SIGMA5_Pos) /**< \brief (SMC_SIGMA5) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA5_SIGMA5(value) ((SMC_SIGMA5_SIGMA5_Msk & ((value) << SMC_SIGMA5_SIGMA5_Pos))) +/* -------- SMC_SIGMA6 : (SMC Offset: 0x540) PMECC Error Location SIGMA 6 Register -------- */ +#define SMC_SIGMA6_SIGMA6_Pos 0 +#define SMC_SIGMA6_SIGMA6_Msk (0x3fffu << SMC_SIGMA6_SIGMA6_Pos) /**< \brief (SMC_SIGMA6) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA6_SIGMA6(value) ((SMC_SIGMA6_SIGMA6_Msk & ((value) << SMC_SIGMA6_SIGMA6_Pos))) +/* -------- SMC_SIGMA7 : (SMC Offset: 0x544) PMECC Error Location SIGMA 7 Register -------- */ +#define SMC_SIGMA7_SIGMA7_Pos 0 +#define SMC_SIGMA7_SIGMA7_Msk (0x3fffu << SMC_SIGMA7_SIGMA7_Pos) /**< \brief (SMC_SIGMA7) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA7_SIGMA7(value) ((SMC_SIGMA7_SIGMA7_Msk & ((value) << SMC_SIGMA7_SIGMA7_Pos))) +/* -------- SMC_SIGMA8 : (SMC Offset: 0x548) PMECC Error Location SIGMA 8 Register -------- */ +#define SMC_SIGMA8_SIGMA8_Pos 0 +#define SMC_SIGMA8_SIGMA8_Msk (0x3fffu << SMC_SIGMA8_SIGMA8_Pos) /**< \brief (SMC_SIGMA8) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA8_SIGMA8(value) ((SMC_SIGMA8_SIGMA8_Msk & ((value) << SMC_SIGMA8_SIGMA8_Pos))) +/* -------- SMC_SIGMA9 : (SMC Offset: 0x54C) PMECC Error Location SIGMA 9 Register -------- */ +#define SMC_SIGMA9_SIGMA9_Pos 0 +#define SMC_SIGMA9_SIGMA9_Msk (0x3fffu << SMC_SIGMA9_SIGMA9_Pos) /**< \brief (SMC_SIGMA9) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA9_SIGMA9(value) ((SMC_SIGMA9_SIGMA9_Msk & ((value) << SMC_SIGMA9_SIGMA9_Pos))) +/* -------- SMC_SIGMA10 : (SMC Offset: 0x550) PMECC Error Location SIGMA 10 Register -------- */ +#define SMC_SIGMA10_SIGMA10_Pos 0 +#define SMC_SIGMA10_SIGMA10_Msk (0x3fffu << SMC_SIGMA10_SIGMA10_Pos) /**< \brief (SMC_SIGMA10) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA10_SIGMA10(value) ((SMC_SIGMA10_SIGMA10_Msk & ((value) << SMC_SIGMA10_SIGMA10_Pos))) +/* -------- SMC_SIGMA11 : (SMC Offset: 0x554) PMECC Error Location SIGMA 11 Register -------- */ +#define SMC_SIGMA11_SIGMA11_Pos 0 +#define SMC_SIGMA11_SIGMA11_Msk (0x3fffu << SMC_SIGMA11_SIGMA11_Pos) /**< \brief (SMC_SIGMA11) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA11_SIGMA11(value) ((SMC_SIGMA11_SIGMA11_Msk & ((value) << SMC_SIGMA11_SIGMA11_Pos))) +/* -------- SMC_SIGMA12 : (SMC Offset: 0x558) PMECC Error Location SIGMA 12 Register -------- */ +#define SMC_SIGMA12_SIGMA12_Pos 0 +#define SMC_SIGMA12_SIGMA12_Msk (0x3fffu << SMC_SIGMA12_SIGMA12_Pos) /**< \brief (SMC_SIGMA12) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA12_SIGMA12(value) ((SMC_SIGMA12_SIGMA12_Msk & ((value) << SMC_SIGMA12_SIGMA12_Pos))) +/* -------- SMC_SIGMA13 : (SMC Offset: 0x55C) PMECC Error Location SIGMA 13 Register -------- */ +#define SMC_SIGMA13_SIGMA13_Pos 0 +#define SMC_SIGMA13_SIGMA13_Msk (0x3fffu << SMC_SIGMA13_SIGMA13_Pos) /**< \brief (SMC_SIGMA13) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA13_SIGMA13(value) ((SMC_SIGMA13_SIGMA13_Msk & ((value) << SMC_SIGMA13_SIGMA13_Pos))) +/* -------- SMC_SIGMA14 : (SMC Offset: 0x560) PMECC Error Location SIGMA 14 Register -------- */ +#define SMC_SIGMA14_SIGMA14_Pos 0 +#define SMC_SIGMA14_SIGMA14_Msk (0x3fffu << SMC_SIGMA14_SIGMA14_Pos) /**< \brief (SMC_SIGMA14) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA14_SIGMA14(value) ((SMC_SIGMA14_SIGMA14_Msk & ((value) << SMC_SIGMA14_SIGMA14_Pos))) +/* -------- SMC_SIGMA15 : (SMC Offset: 0x564) PMECC Error Location SIGMA 15 Register -------- */ +#define SMC_SIGMA15_SIGMA15_Pos 0 +#define SMC_SIGMA15_SIGMA15_Msk (0x3fffu << SMC_SIGMA15_SIGMA15_Pos) /**< \brief (SMC_SIGMA15) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA15_SIGMA15(value) ((SMC_SIGMA15_SIGMA15_Msk & ((value) << SMC_SIGMA15_SIGMA15_Pos))) +/* -------- SMC_SIGMA16 : (SMC Offset: 0x568) PMECC Error Location SIGMA 16 Register -------- */ +#define SMC_SIGMA16_SIGMA16_Pos 0 +#define SMC_SIGMA16_SIGMA16_Msk (0x3fffu << SMC_SIGMA16_SIGMA16_Pos) /**< \brief (SMC_SIGMA16) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA16_SIGMA16(value) ((SMC_SIGMA16_SIGMA16_Msk & ((value) << SMC_SIGMA16_SIGMA16_Pos))) +/* -------- SMC_SIGMA17 : (SMC Offset: 0x56C) PMECC Error Location SIGMA 17 Register -------- */ +#define SMC_SIGMA17_SIGMA17_Pos 0 +#define SMC_SIGMA17_SIGMA17_Msk (0x3fffu << SMC_SIGMA17_SIGMA17_Pos) /**< \brief (SMC_SIGMA17) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA17_SIGMA17(value) ((SMC_SIGMA17_SIGMA17_Msk & ((value) << SMC_SIGMA17_SIGMA17_Pos))) +/* -------- SMC_SIGMA18 : (SMC Offset: 0x570) PMECC Error Location SIGMA 18 Register -------- */ +#define SMC_SIGMA18_SIGMA18_Pos 0 +#define SMC_SIGMA18_SIGMA18_Msk (0x3fffu << SMC_SIGMA18_SIGMA18_Pos) /**< \brief (SMC_SIGMA18) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA18_SIGMA18(value) ((SMC_SIGMA18_SIGMA18_Msk & ((value) << SMC_SIGMA18_SIGMA18_Pos))) +/* -------- SMC_SIGMA19 : (SMC Offset: 0x574) PMECC Error Location SIGMA 19 Register -------- */ +#define SMC_SIGMA19_SIGMA19_Pos 0 +#define SMC_SIGMA19_SIGMA19_Msk (0x3fffu << SMC_SIGMA19_SIGMA19_Pos) /**< \brief (SMC_SIGMA19) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA19_SIGMA19(value) ((SMC_SIGMA19_SIGMA19_Msk & ((value) << SMC_SIGMA19_SIGMA19_Pos))) +/* -------- SMC_SIGMA20 : (SMC Offset: 0x578) PMECC Error Location SIGMA 20 Register -------- */ +#define SMC_SIGMA20_SIGMA20_Pos 0 +#define SMC_SIGMA20_SIGMA20_Msk (0x3fffu << SMC_SIGMA20_SIGMA20_Pos) /**< \brief (SMC_SIGMA20) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA20_SIGMA20(value) ((SMC_SIGMA20_SIGMA20_Msk & ((value) << SMC_SIGMA20_SIGMA20_Pos))) +/* -------- SMC_SIGMA21 : (SMC Offset: 0x57C) PMECC Error Location SIGMA 21 Register -------- */ +#define SMC_SIGMA21_SIGMA21_Pos 0 +#define SMC_SIGMA21_SIGMA21_Msk (0x3fffu << SMC_SIGMA21_SIGMA21_Pos) /**< \brief (SMC_SIGMA21) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA21_SIGMA21(value) ((SMC_SIGMA21_SIGMA21_Msk & ((value) << SMC_SIGMA21_SIGMA21_Pos))) +/* -------- SMC_SIGMA22 : (SMC Offset: 0x580) PMECC Error Location SIGMA 22 Register -------- */ +#define SMC_SIGMA22_SIGMA22_Pos 0 +#define SMC_SIGMA22_SIGMA22_Msk (0x3fffu << SMC_SIGMA22_SIGMA22_Pos) /**< \brief (SMC_SIGMA22) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA22_SIGMA22(value) ((SMC_SIGMA22_SIGMA22_Msk & ((value) << SMC_SIGMA22_SIGMA22_Pos))) +/* -------- SMC_SIGMA23 : (SMC Offset: 0x584) PMECC Error Location SIGMA 23 Register -------- */ +#define SMC_SIGMA23_SIGMA23_Pos 0 +#define SMC_SIGMA23_SIGMA23_Msk (0x3fffu << SMC_SIGMA23_SIGMA23_Pos) /**< \brief (SMC_SIGMA23) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA23_SIGMA23(value) ((SMC_SIGMA23_SIGMA23_Msk & ((value) << SMC_SIGMA23_SIGMA23_Pos))) +/* -------- SMC_SIGMA24 : (SMC Offset: 0x588) PMECC Error Location SIGMA 24 Register -------- */ +#define SMC_SIGMA24_SIGMA24_Pos 0 +#define SMC_SIGMA24_SIGMA24_Msk (0x3fffu << SMC_SIGMA24_SIGMA24_Pos) /**< \brief (SMC_SIGMA24) Coefficient of degree x in the SIGMA polynomial. */ +#define SMC_SIGMA24_SIGMA24(value) ((SMC_SIGMA24_SIGMA24_Msk & ((value) << SMC_SIGMA24_SIGMA24_Pos))) +/* -------- SMC_ERRLOC[24] : (SMC Offset: 0x58C) PMECC Error Location 0 Register -------- */ +#define SMC_ERRLOC_ERRLOCN_Pos 0 +#define SMC_ERRLOC_ERRLOCN_Msk (0x3fffu << SMC_ERRLOC_ERRLOCN_Pos) /**< \brief (SMC_ERRLOC[24]) Error Position within the Set {sector area, spare area} */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */ +#define SMC_TIMINGS_TCLR_Pos 0 +#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */ +#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos))) +#define SMC_TIMINGS_TADL_Pos 4 +#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */ +#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos))) +#define SMC_TIMINGS_TAR_Pos 8 +#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */ +#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos))) +#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */ +#define SMC_TIMINGS_TRR_Pos 16 +#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */ +#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos))) +#define SMC_TIMINGS_TWB_Pos 24 +#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */ +#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos))) +#define SMC_TIMINGS_RBNSEL_Pos 28 +#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */ +#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos))) +#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */ +/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */ +#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */ +#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */ +#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */ +#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */ +#define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +/* -------- SMC_OCMS : (SMC Offset: 0x6A0) SMC OCMS Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x6A4) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x6A8) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPCR : (SMC Offset: 0x6E4) SMC Write Protection Control Register -------- */ +#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */ +#define SMC_WPCR_WP_KEY_Pos 8 +#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */ +#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos))) +/* -------- SMC_WPSR : (SMC Offset: 0x6E8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WP_VS_Pos 0 +#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WP_VSRC_Pos 8 +#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_SMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_spi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_spi.h new file mode 100644 index 000000000..b1c420949 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_spi.h @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SPI_COMPONENT_ +#define _SAMA5_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + RoReg Reserved1[4]; + RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + RoReg Reserved2[41]; + RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) */ +#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) */ +#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) */ +#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) */ +#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) */ +#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) */ +#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) */ +#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) */ +#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) */ +#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) */ +#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) */ +#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) */ +#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_SPI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_ssc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_ssc.h new file mode 100644 index 000000000..e3b12a686 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_ssc.h @@ -0,0 +1,270 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SSC_COMPONENT_ +#define _SAMA5_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMA5_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + RoReg Reserved1[2]; + RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + RoReg Reserved2[2]; + RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + RoReg Reserved3[37]; + RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */ +#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */ +#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_SSC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_tc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_tc.h new file mode 100644 index 000000000..e2a87e52d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_tc.h @@ -0,0 +1,257 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TC_COMPONENT_ +#define _SAMA5_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMA5_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + RoReg Reserved1[1]; + RwReg TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + RoReg Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ + +/*@}*/ + + +#endif /* _SAMA5_TC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_tdes.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_tdes.h new file mode 100644 index 000000000..011830471 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_tdes.h @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TDES_COMPONENT_ +#define _SAMA5_TDES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMA5_TDES Triple Data Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Tdes hardware registers */ +typedef struct { + WoReg TDES_CR; /**< \brief (Tdes Offset: 0x00) Control Register */ + RwReg TDES_MR; /**< \brief (Tdes Offset: 0x04) Mode Register */ + RoReg Reserved1[2]; + WoReg TDES_IER; /**< \brief (Tdes Offset: 0x10) Interrupt Enable Register */ + WoReg TDES_IDR; /**< \brief (Tdes Offset: 0x14) Interrupt Disable Register */ + RoReg TDES_IMR; /**< \brief (Tdes Offset: 0x18) Interrupt Mask Register */ + RoReg TDES_ISR; /**< \brief (Tdes Offset: 0x1C) Interrupt Status Register */ + WoReg TDES_KEY1WR[2]; /**< \brief (Tdes Offset: 0x20) Key 1 Word Register */ + WoReg TDES_KEY2WR[2]; /**< \brief (Tdes Offset: 0x28) Key 2 Word Register */ + WoReg TDES_KEY3WR[2]; /**< \brief (Tdes Offset: 0x30) Key 3 Word Register */ + RoReg Reserved2[2]; + WoReg TDES_IDATAR[2]; /**< \brief (Tdes Offset: 0x40) Input Data Register */ + RoReg Reserved3[2]; + RoReg TDES_ODATAR[2]; /**< \brief (Tdes Offset: 0x50) Output Data Register */ + RoReg Reserved4[2]; + WoReg TDES_IVR[2]; /**< \brief (Tdes Offset: 0x60) Initialization Vector Register */ + RoReg Reserved5[2]; + RwReg TDES_XTEARNDR; /**< \brief (Tdes Offset: 0x70) XTEA Rounds Register */ +} Tdes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TDES_CR : (TDES Offset: 0x00) Control Register -------- */ +#define TDES_CR_START (0x1u << 0) /**< \brief (TDES_CR) Start Processing */ +#define TDES_CR_SWRST (0x1u << 8) /**< \brief (TDES_CR) Software Reset */ +#define TDES_CR_LOADSEED (0x1u << 16) /**< \brief (TDES_CR) Load Seed */ +/* -------- TDES_MR : (TDES Offset: 0x04) Mode Register -------- */ +#define TDES_MR_CIPHER (0x1u << 0) /**< \brief (TDES_MR) Processing Mode */ +#define TDES_MR_CIPHER_DECRYPT (0x0u << 0) /**< \brief (TDES_MR) Decrypts data. */ +#define TDES_MR_CIPHER_ENCRYPT (0x1u << 0) /**< \brief (TDES_MR) Encrypts data. */ +#define TDES_MR_TDESMOD_Pos 1 +#define TDES_MR_TDESMOD_Msk (0x3u << TDES_MR_TDESMOD_Pos) /**< \brief (TDES_MR) ALGORITHM mode */ +#define TDES_MR_TDESMOD(value) ((TDES_MR_TDESMOD_Msk & ((value) << TDES_MR_TDESMOD_Pos))) +#define TDES_MR_KEYMOD (0x1u << 4) /**< \brief (TDES_MR) Key Mode */ +#define TDES_MR_SMOD_Pos 8 +#define TDES_MR_SMOD_Msk (0x3u << TDES_MR_SMOD_Pos) /**< \brief (TDES_MR) Start Mode */ +#define TDES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (TDES_MR) Manual Mode */ +#define TDES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (TDES_MR) Auto Mode */ +#define TDES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (TDES_MR) TDES_IDATAR0 access only Auto Mode */ +#define TDES_MR_OPMOD_Pos 12 +#define TDES_MR_OPMOD_Msk (0x3u << TDES_MR_OPMOD_Pos) /**< \brief (TDES_MR) Operation Mode */ +#define TDES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (TDES_MR) ECB: Electronic Code Book mode */ +#define TDES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (TDES_MR) CBC: Cipher Block Chaining mode */ +#define TDES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (TDES_MR) OFB: Output Feedback mode */ +#define TDES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (TDES_MR) CFB: Cipher Feedback mode */ +#define TDES_MR_LOD (0x1u << 15) /**< \brief (TDES_MR) Last Output Data Mode */ +#define TDES_MR_CFBS_Pos 16 +#define TDES_MR_CFBS_Msk (0x3u << TDES_MR_CFBS_Pos) /**< \brief (TDES_MR) Cipher Feedback Data Size */ +#define TDES_MR_CFBS_SIZE_64BIT (0x0u << 16) /**< \brief (TDES_MR) 64-bit */ +#define TDES_MR_CFBS_SIZE_32BIT (0x1u << 16) /**< \brief (TDES_MR) 32-bit */ +#define TDES_MR_CFBS_SIZE_16BIT (0x2u << 16) /**< \brief (TDES_MR) 16-bit */ +#define TDES_MR_CFBS_SIZE_8BIT (0x3u << 16) /**< \brief (TDES_MR) 8-bit */ +#define TDES_MR_CKEY_Pos 20 +#define TDES_MR_CKEY_Msk (0xfu << TDES_MR_CKEY_Pos) /**< \brief (TDES_MR) Countermeasure Key */ +#define TDES_MR_CKEY(value) ((TDES_MR_CKEY_Msk & ((value) << TDES_MR_CKEY_Pos))) +#define TDES_MR_CMTYP1 (0x1u << 24) /**< \brief (TDES_MR) CounterMeasure Type 1 */ +#define TDES_MR_CMTYP1_NO_PAUSE (0x0u << 24) /**< \brief (TDES_MR) Counter-Measure type 1 is disabled */ +#define TDES_MR_CMTYP1_PAUSE (0x1u << 24) /**< \brief (TDES_MR) Counter-Measure type 1 is enabled */ +#define TDES_MR_CMTYP2 (0x1u << 25) /**< \brief (TDES_MR) CounterMeasure Type 2 */ +#define TDES_MR_CMTYP2_NO_DUMMY (0x0u << 25) /**< \brief (TDES_MR) Counter-Measure type 2 is disabled */ +#define TDES_MR_CMTYP2_DUMMY (0x1u << 25) /**< \brief (TDES_MR) Counter-Measure type 2 is enabled */ +#define TDES_MR_CMTYP3 (0x1u << 26) /**< \brief (TDES_MR) CounterMeasure Type 3 */ +#define TDES_MR_CMTYP3_NO_RESTART (0x0u << 26) /**< \brief (TDES_MR) Counter-Measure type 3 is disabled */ +#define TDES_MR_CMTYP3_RESTART (0x1u << 26) /**< \brief (TDES_MR) Counter-Measure type 3 is enabled */ +#define TDES_MR_CMTYP4 (0x1u << 27) /**< \brief (TDES_MR) CounterMeasure Type 4 */ +#define TDES_MR_CMTYP4_NO_IDLECURRENT (0x0u << 27) /**< \brief (TDES_MR) Counter-Measure type 4 is disabled */ +#define TDES_MR_CMTYP4_IDLECURRENT (0x1u << 27) /**< \brief (TDES_MR) Counter-Measure type 4 is enabled */ +#define TDES_MR_CMTYP5 (0x1u << 28) /**< \brief (TDES_MR) CounterMeasure Type 5 */ +#define TDES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (TDES_MR) Counter-Measure type 5 is disabled */ +#define TDES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (TDES_MR) Counter-Measure type 5 is enabled */ +/* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */ +#define TDES_IER_DATRDY (0x1u << 0) /**< \brief (TDES_IER) Data Ready Interrupt Enable */ +#define TDES_IER_URAD (0x1u << 8) /**< \brief (TDES_IER) Unspecified Register Access Detection Interrupt Enable */ +/* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */ +#define TDES_IDR_DATRDY (0x1u << 0) /**< \brief (TDES_IDR) Data Ready Interrupt Disable */ +#define TDES_IDR_URAD (0x1u << 8) /**< \brief (TDES_IDR) Unspecified Register Access Detection Interrupt Disable */ +/* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */ +#define TDES_IMR_DATRDY (0x1u << 0) /**< \brief (TDES_IMR) Data Ready Interrupt Mask */ +#define TDES_IMR_URAD (0x1u << 8) /**< \brief (TDES_IMR) Unspecified Register Access Detection Interrupt Mask */ +/* -------- TDES_ISR : (TDES Offset: 0x1C) Interrupt Status Register -------- */ +#define TDES_ISR_DATRDY (0x1u << 0) /**< \brief (TDES_ISR) Data Ready */ +#define TDES_ISR_URAD (0x1u << 8) /**< \brief (TDES_ISR) Unspecified Register Access Detection Status */ +#define TDES_ISR_URAT_Pos 12 +#define TDES_ISR_URAT_Msk (0x3u << TDES_ISR_URAT_Pos) /**< \brief (TDES_ISR) Unspecified Register Access */ +#define TDES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (TDES_ISR) Input Data Register written during the data processing when SMOD=0x2 mode. */ +#define TDES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (TDES_ISR) Output Data Register read during the data processing. */ +#define TDES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (TDES_ISR) Mode Register written during the data processing. */ +#define TDES_ISR_URAT_WOR_RD_ACCESS (0x3u << 12) /**< \brief (TDES_ISR) Write-only register read access. */ +/* -------- TDES_KEY1WR[2] : (TDES Offset: 0x20) Key 1 Word Register -------- */ +#define TDES_KEY1WR_KEY1W_Pos 0 +#define TDES_KEY1WR_KEY1W_Msk (0xffffffffu << TDES_KEY1WR_KEY1W_Pos) /**< \brief (TDES_KEY1WR[2]) Key 1 Word */ +#define TDES_KEY1WR_KEY1W(value) ((TDES_KEY1WR_KEY1W_Msk & ((value) << TDES_KEY1WR_KEY1W_Pos))) +/* -------- TDES_KEY2WR[2] : (TDES Offset: 0x28) Key 2 Word Register -------- */ +#define TDES_KEY2WR_KEY2W_Pos 0 +#define TDES_KEY2WR_KEY2W_Msk (0xffffffffu << TDES_KEY2WR_KEY2W_Pos) /**< \brief (TDES_KEY2WR[2]) Key 2 Word */ +#define TDES_KEY2WR_KEY2W(value) ((TDES_KEY2WR_KEY2W_Msk & ((value) << TDES_KEY2WR_KEY2W_Pos))) +/* -------- TDES_KEY3WR[2] : (TDES Offset: 0x30) Key 3 Word Register -------- */ +#define TDES_KEY3WR_KEY3W_Pos 0 +#define TDES_KEY3WR_KEY3W_Msk (0xffffffffu << TDES_KEY3WR_KEY3W_Pos) /**< \brief (TDES_KEY3WR[2]) Key 3 Word */ +#define TDES_KEY3WR_KEY3W(value) ((TDES_KEY3WR_KEY3W_Msk & ((value) << TDES_KEY3WR_KEY3W_Pos))) +/* -------- TDES_IDATAR[2] : (TDES Offset: 0x40) Input Data Register -------- */ +#define TDES_IDATAR_IDATA_Pos 0 +#define TDES_IDATAR_IDATA_Msk (0xffffffffu << TDES_IDATAR_IDATA_Pos) /**< \brief (TDES_IDATAR[2]) Input Data */ +#define TDES_IDATAR_IDATA(value) ((TDES_IDATAR_IDATA_Msk & ((value) << TDES_IDATAR_IDATA_Pos))) +/* -------- TDES_ODATAR[2] : (TDES Offset: 0x50) Output Data Register -------- */ +#define TDES_ODATAR_ODATA_Pos 0 +#define TDES_ODATAR_ODATA_Msk (0xffffffffu << TDES_ODATAR_ODATA_Pos) /**< \brief (TDES_ODATAR[2]) Output Data */ +/* -------- TDES_IVR[2] : (TDES Offset: 0x60) Initialization Vector Register -------- */ +#define TDES_IVR_IV_Pos 0 +#define TDES_IVR_IV_Msk (0xffffffffu << TDES_IVR_IV_Pos) /**< \brief (TDES_IVR[2]) Initialization Vector */ +#define TDES_IVR_IV(value) ((TDES_IVR_IV_Msk & ((value) << TDES_IVR_IV_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_TDES_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_trng.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_trng.h new file mode 100644 index 000000000..636e9244b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_trng.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TRNG_COMPONENT_ +#define _SAMA5_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMA5_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + WoReg TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + RoReg Reserved1[3]; + WoReg TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + WoReg TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + RoReg TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + RoReg TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + RoReg Reserved2[12]; + RoReg TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAMA5_TRNG_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_twi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_twi.h new file mode 100644 index 000000000..3f7f40f1e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_twi.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI_COMPONENT_ +#define _SAMA5_TWI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup SAMA5_TWI Two-wire Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twi hardware registers */ +typedef struct { + WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + RoReg Reserved1[3]; + RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + RoReg Reserved2[43]; + RwReg TWI_WPROT_MODE; /**< \brief (Twi Offset: 0xE4) Protection Mode Register */ + RoReg TWI_WPROT_STATUS; /**< \brief (Twi Offset: 0xE8) Protection Status Register */ +} Twi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) +/* -------- TWI_WPROT_MODE : (TWI Offset: 0xE4) Protection Mode Register -------- */ +#define TWI_WPROT_MODE_WPROT (0x1u << 0) /**< \brief (TWI_WPROT_MODE) Write protection bit */ +#define TWI_WPROT_MODE_SECURITY_CODE_Pos 8 +#define TWI_WPROT_MODE_SECURITY_CODE_Msk (0xffffffu << TWI_WPROT_MODE_SECURITY_CODE_Pos) /**< \brief (TWI_WPROT_MODE) Write protection mode security code */ +#define TWI_WPROT_MODE_SECURITY_CODE(value) ((TWI_WPROT_MODE_SECURITY_CODE_Msk & ((value) << TWI_WPROT_MODE_SECURITY_CODE_Pos))) +/* -------- TWI_WPROT_STATUS : (TWI Offset: 0xE8) Protection Status Register -------- */ +#define TWI_WPROT_STATUS_WPROTERR (0x1u << 0) /**< \brief (TWI_WPROT_STATUS) Write Protection Error */ +#define TWI_WPROT_STATUS_WPROTADDR_Pos 8 +#define TWI_WPROT_STATUS_WPROTADDR_Msk (0xffffffu << TWI_WPROT_STATUS_WPROTADDR_Pos) /**< \brief (TWI_WPROT_STATUS) Write Protection Error Address */ + +/*@}*/ + + +#endif /* _SAMA5_TWI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_uart.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_uart.h new file mode 100644 index 000000000..84f6d8504 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_uart.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UART_COMPONENT_ +#define _SAMA5_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMA5_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_UART_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_udphs.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_udphs.h new file mode 100644 index 000000000..2045fdf8e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_udphs.h @@ -0,0 +1,403 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UDPHS_COMPONENT_ +#define _SAMA5_UDPHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */ +/* ============================================================================= */ +/** \addtogroup SAMA5_UDPHS USB High Speed Device Port */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UdphsDma hardware registers */ +typedef struct { + RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */ + RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */ + RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */ + RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */ +} UdphsDma; +/** \brief UdphsEpt hardware registers */ +typedef struct { + RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */ + RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */ + RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */ + RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */ + RoReg Reserved1[1]; + RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */ + RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */ + RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */ +} UdphsEpt; +/** \brief Udphs hardware registers */ +#define UDPHSEPT_NUMBER 16 +#define UDPHSDMA_NUMBER 7 +typedef struct { + RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */ + RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */ + RoReg Reserved1[2]; + RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */ + RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */ + WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */ + WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */ + RoReg Reserved2[48]; + RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */ + RoReg Reserved3[3]; + RoReg UDPHS_IPNAME1; /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */ + RoReg UDPHS_IPNAME2; /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */ + RoReg UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */ + RoReg Reserved4[1]; + UdphsEpt UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 15 */ + UdphsDma UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 6 */ +} Udphs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */ +#define UDPHS_CTRL_DEV_ADDR_Pos 0 +#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */ +#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos))) +#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */ +#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */ +#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */ +#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */ +#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */ +/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */ +#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0 +#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */ +#define UDPHS_FNUM_FRAME_NUMBER_Pos 3 +#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */ +#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */ +/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */ +#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */ +#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */ +#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */ +#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */ +#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */ +#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */ +#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */ +#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */ +#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */ +#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */ +#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */ +#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */ +#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */ +#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */ +#define UDPHS_IEN_EPT_7 (0x1u << 15) /**< \brief (UDPHS_IEN) Endpoint 7 Interrupt Enable */ +#define UDPHS_IEN_EPT_8 (0x1u << 16) /**< \brief (UDPHS_IEN) Endpoint 8 Interrupt Enable */ +#define UDPHS_IEN_EPT_9 (0x1u << 17) /**< \brief (UDPHS_IEN) Endpoint 9 Interrupt Enable */ +#define UDPHS_IEN_EPT_10 (0x1u << 18) /**< \brief (UDPHS_IEN) Endpoint 10 Interrupt Enable */ +#define UDPHS_IEN_EPT_11 (0x1u << 19) /**< \brief (UDPHS_IEN) Endpoint 11 Interrupt Enable */ +#define UDPHS_IEN_EPT_12 (0x1u << 20) /**< \brief (UDPHS_IEN) Endpoint 12 Interrupt Enable */ +#define UDPHS_IEN_EPT_13 (0x1u << 21) /**< \brief (UDPHS_IEN) Endpoint 13 Interrupt Enable */ +#define UDPHS_IEN_EPT_14 (0x1u << 22) /**< \brief (UDPHS_IEN) Endpoint 14 Interrupt Enable */ +#define UDPHS_IEN_EPT_15 (0x1u << 23) /**< \brief (UDPHS_IEN) Endpoint 15 Interrupt Enable */ +#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */ +#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */ +#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */ +#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */ +#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */ +#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */ +#define UDPHS_IEN_DMA_7 (0x1u << 31) /**< \brief (UDPHS_IEN) DMA Channel 7 Interrupt Enable */ +/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */ +#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */ +#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */ +#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */ +#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */ +#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */ +#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */ +#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */ +#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */ +#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */ +#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */ +#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */ +#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */ +#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */ +#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */ +#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */ +#define UDPHS_INTSTA_EPT_7 (0x1u << 15) /**< \brief (UDPHS_INTSTA) Endpoint 7 Interrupt */ +#define UDPHS_INTSTA_EPT_8 (0x1u << 16) /**< \brief (UDPHS_INTSTA) Endpoint 8 Interrupt */ +#define UDPHS_INTSTA_EPT_9 (0x1u << 17) /**< \brief (UDPHS_INTSTA) Endpoint 9 Interrupt */ +#define UDPHS_INTSTA_EPT_10 (0x1u << 18) /**< \brief (UDPHS_INTSTA) Endpoint 10 Interrupt */ +#define UDPHS_INTSTA_EPT_11 (0x1u << 19) /**< \brief (UDPHS_INTSTA) Endpoint 11 Interrupt */ +#define UDPHS_INTSTA_EPT_12 (0x1u << 20) /**< \brief (UDPHS_INTSTA) Endpoint 12 Interrupt */ +#define UDPHS_INTSTA_EPT_13 (0x1u << 21) /**< \brief (UDPHS_INTSTA) Endpoint 13 Interrupt */ +#define UDPHS_INTSTA_EPT_14 (0x1u << 22) /**< \brief (UDPHS_INTSTA) Endpoint 14 Interrupt */ +#define UDPHS_INTSTA_EPT_15 (0x1u << 23) /**< \brief (UDPHS_INTSTA) Endpoint 15 Interrupt */ +#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */ +#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */ +#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */ +#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */ +#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */ +#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */ +#define UDPHS_INTSTA_DMA_7 (0x1u << 31) /**< \brief (UDPHS_INTSTA) DMA Channel 7 Interrupt */ +/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */ +#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */ +#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */ +#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */ +#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */ +#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */ +#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */ +#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */ +/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */ +#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */ +#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */ +#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */ +#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */ +#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */ +#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */ +#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */ +#define UDPHS_EPTRST_EPT_7 (0x1u << 7) /**< \brief (UDPHS_EPTRST) Endpoint 7 Reset */ +#define UDPHS_EPTRST_EPT_8 (0x1u << 8) /**< \brief (UDPHS_EPTRST) Endpoint 8 Reset */ +#define UDPHS_EPTRST_EPT_9 (0x1u << 9) /**< \brief (UDPHS_EPTRST) Endpoint 9 Reset */ +#define UDPHS_EPTRST_EPT_10 (0x1u << 10) /**< \brief (UDPHS_EPTRST) Endpoint 10 Reset */ +#define UDPHS_EPTRST_EPT_11 (0x1u << 11) /**< \brief (UDPHS_EPTRST) Endpoint 11 Reset */ +#define UDPHS_EPTRST_EPT_12 (0x1u << 12) /**< \brief (UDPHS_EPTRST) Endpoint 12 Reset */ +#define UDPHS_EPTRST_EPT_13 (0x1u << 13) /**< \brief (UDPHS_EPTRST) Endpoint 13 Reset */ +#define UDPHS_EPTRST_EPT_14 (0x1u << 14) /**< \brief (UDPHS_EPTRST) Endpoint 14 Reset */ +#define UDPHS_EPTRST_EPT_15 (0x1u << 15) /**< \brief (UDPHS_EPTRST) Endpoint 15 Reset */ +/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */ +#define UDPHS_TST_SPEED_CFG_Pos 0 +#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */ +#define UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */ +#define UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */ +#define UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */ +#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */ +#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */ +#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */ +#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */ +/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */ +#define UDPHS_IPNAME1_IP_NAME1_Pos 0 +#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) /**< \brief (UDPHS_IPNAME1) */ +/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */ +#define UDPHS_IPNAME2_IP_NAME2_Pos 0 +#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) /**< \brief (UDPHS_IPNAME2) */ +/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */ +#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0 +#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */ +#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4 +#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */ +#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */ +#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8 +#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */ +#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12 +#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */ +#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */ +#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */ +#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ +/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */ +#define UDPHS_EPTCFG_EPT_SIZE_Pos 0 +#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */ +#define UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */ +#define UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */ +#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */ +#define UDPHS_EPTCFG_EPT_TYPE_Pos 4 +#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */ +#define UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */ +#define UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */ +#define UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */ +#define UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */ +#define UDPHS_EPTCFG_BK_NUMBER_Pos 6 +#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */ +#define UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */ +#define UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */ +#define UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */ +#define UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */ +#define UDPHS_EPTCFG_NB_TRANS_Pos 8 +#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */ +#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos))) +#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */ +/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */ +#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */ +#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */ +#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */ +#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */ +#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ +#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ +#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */ +#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */ +#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */ +#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */ +#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */ +#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */ +#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */ +#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */ +/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */ +#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */ +#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */ +#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */ +#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */ +#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ +#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ +#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */ +#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */ +#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */ +#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */ +#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */ +#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */ +#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */ +#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */ +/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */ +#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */ +#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ +#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */ +#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */ +#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ +#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ +#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */ +#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */ +#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */ +#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */ +#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */ +#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */ +#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */ +#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ +#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ +#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ +#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */ +#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */ +#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */ +#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */ +#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */ +/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */ +#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */ +#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */ +#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */ +/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */ +#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */ +#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */ +#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */ +#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */ +#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */ +#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */ +#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */ +#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */ +#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */ +#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */ +#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */ +/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */ +#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */ +#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6 +#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */ +#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */ +#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */ +#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Data2 (only for High Bandwidth Isochronous Endpoint) */ +#define UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) MData (only for High Bandwidth Isochronous Endpoint) */ +#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */ +#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */ +#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */ +#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */ +#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */ +#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */ +#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */ +#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */ +#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */ +#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */ +#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */ +#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */ +#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */ +#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */ +#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16 +#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */ +#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16 +#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */ +#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18 +#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */ +#define UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */ +#define UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */ +#define UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */ +#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20 +#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */ +#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */ +/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */ +#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC) */ +#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */ +#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0 +#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS) */ +#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos))) +/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */ +#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL) */ +#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */ +#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */ +#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */ +#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */ +#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */ +#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */ +#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16 +#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */ +#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */ +#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */ +#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */ +#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */ +#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */ +#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */ +#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16 +#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */ +#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos))) + +/*@}*/ + + +#endif /* _SAMA5_UDPHS_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_usart.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_usart.h new file mode 100644 index 000000000..7788f649a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_usart.h @@ -0,0 +1,270 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART_COMPONENT_ +#define _SAMA5_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMA5_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + RoReg Reserved1[5]; + RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + RoReg Reserved2[1]; + RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + RoReg Reserved3[36]; + RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ + RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */ +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=(DIV=8)) is selected */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error or Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error or Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error or Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error or */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */ +/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMA5_USART_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_wdt.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_wdt.h new file mode 100644 index 000000000..454aade0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_WDT_COMPONENT_ +#define _SAMA5_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMA5_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + + +#endif /* _SAMA5_WDT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/dmac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/dmac.h new file mode 100644 index 000000000..60001e800 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/dmac.h @@ -0,0 +1,245 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup dmac_module Working with DMAC + * + * \section Usage + *
    + *
  • Enable or disable the a DMAC controller with DMAC_Enable() and or DMAC_Disable().
    • + *
  • Enable or disable %Dma interrupt using DMAC_EnableIt()or DMAC_DisableIt().
    • + *
  • Get %Dma interrupt status by DMAC_GetStatus() and DMAC_GetInterruptMask().
    • + *
  • Enable or disable specified %Dma channel with DMAC_EnableChannel() or DMAC_DisableChannel().
    • + *
  • Get %Dma channel status by DMAC_GetChannelStatus().
    • + *
  • ControlA and ControlB register is set by DMAC_SetControlA() and DMAC_SetControlB().
    • + *
  • Configure source and/or destination start address with DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().
    • + *
  • Set %Dma descriptor address using DMAC_SetDescriptorAddr().
    • + *
  • Set source transfer buffer size with DMAC_SetBufferSize().
    • + *
  • Configure source and/or destination Picture-In-Picutre mode with DMAC_SetSourcePip() and/or DMAC_SetDestPip().
    • + *
+ * + * For more accurate information, please look at the DMAC section of the + * Datasheet. + * + * \sa \ref dmad_module + * + * Related files :\n + * \ref dmac.c\n + * \ref dmac.h.\n + * + */ + +#ifndef DMAC_H +#define DMAC_H +/**@{*/ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup dmac_defines DMAC Definitions + * @{ + */ +/** Number of DMA channels */ +#define DMAC_CHANNEL_NUM 8 +/** Max DMA single transfer size */ +#define DMAC_MAX_BT_SIZE 0xFFFF +/** @}*/ + +/*------------------------------------------------------------------------------ + * Data structs + *----------------------------------------------------------------------------*/ + +/** \addtogroup dmac_struct DMAC Data Structs + * @{ + */ +/** DMA Transfer Descriptor as well as Linked List Item */ +typedef struct _DmaTransferDescriptor { + uint32_t dwSrcAddr; /**< Source buffer address */ + uint32_t dwDstAddr; /**< Destination buffer address */ + uint32_t dwCtrlA; /**< Control A register settings */ + uint32_t dwCtrlB; /**< Control B register settings */ + uint32_t dwDscAddr; /**< Next descriptor address */ +} sDmaTransferDescriptor; + +/** DMA channel control A */ +typedef struct _DmaCtrlA { + uint32_t btSize:16, /**< Buffer Transfer size */ + scSize:3, /**< Source Chunk Transfer size */ + reserve1:1, + dcSize:3, /**< Destination Chunk Transfer size */ + reserve2:1, + srcWidth:2, /**< Source width */ + reserve3:2, + dstWidth:2, /**< Destination width */ + reserve4:1, + done:1; /**< The transfer is done */ +} sDmaCtrlA; + +/** DMA channel control B */ +typedef struct _DmaCtrlB { + uint32_t sIf:2, /**< Source Interface Selection Field */ + reserve1:2, + dIf:2, /**< Destination Interface Selection Field */ + reserve2:2, + srcPip:1, /**< Source Picture-in-picture mode enable */ + reserve3:3, + dstPip:1, /**< Destination Picture-in-picture mode enable */ + reserve4:3, + srcDscr:1, /**< Source Descriptor disabled */ + reserve5:3, + dstDscr:1, /**< Destination Descriptor disabled */ + fc:3, /**< Flow Controller */ + srcIncr:2, /**< Source Fixed/Dec/Inc setting */ + reserve6, + dstIncr:2, /**< Destination Fixed/Dec/Inc setting */ + iEn:1, /**< Active low to enable interrupt */ + autoEn:1; /**< Automatic multiple buffer transfer */ +} sDmaCtrlB; + +/** DMA channel Picture-In-Picture */ +typedef struct _DmaPip { + uint32_t pipHole:16, /**< Hole size */ + pipBoundary:10,/**< Number of transfers to perform before + hole increse */ + reserve:6; +} sDmaPIP; +/** @}*/ + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ +/** \addtogroup dmac_functions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void DMAC_Modified_Arbiter( Dmac *pDmac); +extern void DMAC_Enable( Dmac *pDmac ); +extern void DMAC_Disable( Dmac *pDmac ); +extern void DMAC_EnableIt (Dmac *pDmac, uint32_t dwInteruptMask ); +extern void DMAC_DisableIt (Dmac *pDmac, uint32_t dwInteruptMask ); +extern uint32_t DMAC_GetInterruptMask( Dmac *pDmac ); +extern uint32_t DMAC_GetStatus( Dmac *pDmac ); +extern uint32_t DMAC_GetMaskedStatus( Dmac *pDmac ); +extern void DMAC_EnableChannel( Dmac *pDmac, uint8_t channel ); +extern void DMAC_EnableChannels( Dmac *pDmac, uint8_t bmChannels ); +extern void DMAC_DisableChannel( Dmac *pDmac, uint8_t channel ); +extern void DMAC_DisableChannels( Dmac *pDmac, uint8_t bmChannels ); +extern void DMAC_SuspendChannel( Dmac *pDmac, uint8_t channel ); +extern void DMAC_KeepChannel( Dmac *pDmac, uint8_t channel ); +extern void DMAC_RestoreChannel( Dmac *pDmac, uint8_t channel ); +extern uint32_t DMAC_GetChannelStatus( Dmac *pDmac ); +extern void DMAC_SetSourceAddr( Dmac *pDmac, + uint8_t channel, + uint32_t saddr ); +extern uint32_t DMAC_GetSourceAddr( Dmac * pDmac, + uint8_t channel ); +extern void DMAC_SetDestinationAddr( Dmac *pDmac, + uint8_t channel, + uint32_t daddr ); +extern uint32_t DMAC_GetDestinationAddr( Dmac * pDmac, + uint8_t channel ); +extern void DMAC_SetDescriptorAddr( Dmac *pDmac, + uint8_t channel, + uint32_t descr, + uint8_t descrif ); +extern void DMAC_SetControlA( Dmac *pDmac, + uint8_t channel, + uint32_t controlA ); +extern void DMAC_SetBufferSize( Dmac *pDmac, + uint8_t channel, + uint16_t bsize); +extern void DMAC_SetSingleTransferSize ( Dmac *pDmac, + uint8_t channel, + uint8_t srcWidth, + uint8_t dstWidth ); +extern void DMAC_SetChunkTransferSize ( Dmac *pDmac, + uint8_t channel, + uint8_t scSize, + uint8_t dcSize); +extern void DMAC_SetControlB( Dmac *pDmac, + uint8_t channel, + uint32_t controlB ); +extern void DMAC_EnableAutoMode( Dmac *pDmac, uint8_t channel ); +extern void DMAC_DisableAutoMode( Dmac *pDmac, uint8_t channel ); +extern void DMAC_SelectAHBInterface( Dmac *pDmac, + uint8_t channel, + uint8_t srcIf, + uint8_t dstIf ); +extern void DMAC_SetPipMode( Dmac *pDmac, + uint8_t channel, + uint8_t srcPip, + uint8_t dstPip ); +extern void DMAC_SetDescFetchMode( Dmac *pDmac, + uint8_t channel, + uint8_t srcDscr, + uint8_t dstDscr ); +extern void DMAC_SetFlowControl( Dmac *pDmac, + uint8_t channel, + uint8_t flowControl ); +extern void DMAC_SetCFG( Dmac *pDmac, + uint8_t channel, + uint32_t configuration ); +extern void DMAC_SetReloadMode( Dmac *pDmac, + uint8_t channel, + uint8_t srcRep, + uint8_t dstRep ); +extern void DMAC_SethandshakeInterface( Dmac *pDmac, + uint8_t channel, + uint8_t srcH2sel, + uint8_t dstH2sel ); +extern void DMAC_SetSourcePip( Dmac *pDmac, + uint8_t channel, + uint16_t pipHole, + uint16_t pipBoundary); +extern void DMAC_SetDestPip( Dmac *pDmac, + uint8_t channel, + uint16_t pipHole, + uint16_t pipBoundary); +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef DMAC_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/emac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/emac.h new file mode 100644 index 000000000..151f85976 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/emac.h @@ -0,0 +1,302 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup emac_module + * @{ + * Provides the interface to configure and use the EMAC peripheral. + * + * \section emac_usage Usage + * - Configure Emac::EMAC_NCFG with EMAC_Configure(), some of related controls + * are also available, such as: + * - EMAC_SetSpeed(): Setup EMAC working clock. + * - EMAC_FullDuplexEnable(): Working in full duplex or not. + * - EMAC_CpyAllEnable(): Copying all valid frames (\ref EMAC_NCFG_CAF). + * - ... + * - Setup Emac::EMAC_NCR with EMAC_NetworkControl(), more related controls + * can modify with: + * - EMAC_ReceiveEnable(): Enable/Disable Rx. + * - EMAC_TransmitEnable(): Enable/Disable Tx. + * - EMAC_BroadcastDisable(): Enable/Disable broadcast receiving. + * - ... + * - Manage EMAC interrupts with EMAC_EnableIt(), EMAC_DisableIt(), + * EMAC_GetItMask() and EMAC_GetItStatus(). + * - Manage EMAC Tx/Rx status with EMAC_GetTxStatus(), EMAC_GetRxStatus() + * EMAC_ClearTxStatus() and EMAC_ClearRxStatus(). + * - Manage EMAC Queue with EMAC_SetTxQueue(), EMAC_GetTxQueue(), + * EMAC_SetRxQueue() and EMAC_GetRxQueue(), the queue descriptor can define + * by \ref sEmacRxDescriptor and \ref sEmacTxDescriptor. + * - Manage PHY through EMAC is performed by + * - EMAC_ManagementEnable(): Enable/Disable PHY management. + * - EMAC_PHYMaintain(): Execute PHY management commands. + * - EMAC_PHYData(): Return PHY management data. + * - EMAC_IsIdle(): Check if PHY is idle. + * - Setup EMAC parameters with following functions: + * - EMAC_SetHash(): Set Hash value. + * - EMAC_SetAddress(): Set MAC address. + * - Enable/Disable EMAC transceiver clock via EMAC_TransceiverClockEnable() + * - Switch EMAC MII/RMII mode through EMAC_RMIIEnable() + * + * For more accurate information, please look at the EMAC section of the + * Datasheet. + * + * \sa \ref emacd_module + * + * Related files:\n + * emac.c\n + * emac.h.\n + * + * \defgroup emac_defines EMAC Defines + * \defgroup emac_structs EMAC Data Structs + * \defgroup emac_functions EMAC Functions + */ +/**@}*/ + +#ifndef _EMAC_H +#define _EMAC_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ +/** \addtogroup emac_defines + @{*/ + +/** The buffer addresses written into the descriptors must be aligned so the + last few bits are zero. These bits have special meaning for the EMAC + peripheral and cannot be used as part of the address. */ +#define EMAC_RXD_ADDR_MASK 0xFFFFFFFC +#define EMAC_RXD_bmWRAP (1ul << 1) /**< Wrap bit */ +#define EMAC_RXD_bmOWNERSHIP (1ul << 0) /**< Ownership bit */ + +#define EMAC_RXD_bmBROADCAST (1ul << 31) /**< Broadcast detected */ +#define EMAC_RXD_bmMULTIHASH (1ul << 30) /**< Multicast hash match */ +#define EMAC_RXD_bmUNIHASH (1ul << 29) /**< Unicast hash match */ +#define EMAC_RXD_bmEXTADDR (1ul << 28) /**< External address match */ +#define EMAC_RXD_bmADDR1 (1ul << 26) /**< Address 1 match */ +#define EMAC_RXD_bmADDR2 (1ul << 25) /**< Address 2 match */ +#define EMAC_RXD_bmADDR3 (1ul << 24) /**< Address 3 match */ +#define EMAC_RXD_bmADDR4 (1ul << 23) /**< Address 4 match */ +#define EMAC_RXD_bmTYPE (1ul << 22) /**< Type ID match */ +#define EMAC_RXD_bmVLAN (1ul << 21) /**< VLAN tag detected */ +#define EMAC_RXD_bmPRIORITY (1ul << 20) /**< Prority tag detected */ +#define EMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN prority */ +#define EMAC_RXD_bmCFI (1ul << 16) /**< Concatenation Format Indicator + only if bit 21 is set */ +#define EMAC_RXD_bmEOF (1ul << 15) /**< End of frame */ +#define EMAC_RXD_bmSOF (1ul << 14) /**< Start of frame */ +#define EMAC_RXD_OFFSET_MASK /**< Receive buffer offset */ +#define EMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS + (if selected) */ +#define EMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */ + +#define EMAC_TXD_bmUSED (1ul << 31) /**< Frame is transmitted */ +#define EMAC_TXD_bmWRAP (1ul << 30) /**< Last descriptor */ +#define EMAC_TXD_bmERROR (1ul << 29) /**< Retry limit exceed, error */ +#define EMAC_TXD_bmUNDERRUN (1ul << 28) /**< Transmit underrun */ +#define EMAC_TXD_bmEXHAUSTED (1ul << 27) /**< Buffer exhausted */ +#define EMAC_TXD_bmNOCRC (1ul << 16) /**< No CRC */ +#define EMAC_TXD_bmLAST (1ul << 15) /**< Last buffer in frame */ +#define EMAC_TXD_LEN_MASK (0x7FF) /**< Length of buffer */ + + +/** The MAC can support frame lengths up to 1536 bytes. */ +#define EMAC_FRAME_LENTGH_MAX 1536 + +/** @}*/ +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup emac_structs + @{*/ +#ifdef __ICCARM__ // IAR +#define PACKED_ATTR +#elif defined ( __GNUC__ ) /* GCC CS3 */ +#define PACKED_ATTR __attribute__((packed, aligned(8))) +#endif + +/** Receive buffer descriptor struct */ +typedef struct _EmacRxDescriptor { + union _EmacRxAddr { + uint32_t val; + struct _EmacRxAddrBM { + uint32_t bOwnership:1, /**< User clear, EMAC set this to one once + it has successfully written a frame to + memory */ + bWrap:1, /**< Marks last descriptor in receive buffer */ + addrDW:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union _EmacRxStatus { + uint32_t val; + struct _EmacRxStatusBM { + uint32_t len:12, /** Length of frame including FCS */ + offset:2, /** Receive buffer offset, + bits 13:12 of frame length for jumbo + frame */ + bSof:1, /** Start of frame */ + bEof:1, /** End of frame */ + bCFI:1, /** Concatenation Format Indicator */ + vlanPriority:3, /** VLAN priority (if VLAN detected) */ + bPriorityDetected:1, /** Priority tag detected */ + bVlanDetected:1, /**< VLAN tag detected */ + bTypeIDMatch:1, /**< Type ID match */ + bAddr4Match:1, /**< Address register 4 match */ + bAddr3Match:1, /**< Address register 3 match */ + bAddr2Match:1, /**< Address register 2 match */ + bAddr1Match:1, /**< Address register 1 match */ + reserved:1, + bExtAddrMatch:1, /**< External address match */ + bUniHashMatch:1, /**< Unicast hash match */ + bMultiHashMatch:1, /**< Multicast hash match */ + bBroadcastDetected:1; /**< Global all ones broadcast + address detected */ + } bm; + } status; +}PACKED_ATTR sEmacRxDescriptor; /* GCC */ + +/** Transmit buffer descriptor struct */ +typedef struct _EmacTxDescriptor { + uint32_t addr; + union _EmacTxStatus { + uint32_t val; + struct _EmacTxStatusBM { + uint32_t len:11, /**< Length of buffer */ + reserved:4, + bLastBuffer:1, /**< Last buffer (in the current frame) */ + bNoCRC:1, /**< No CRC */ + reserved1:10, + bExhausted:1, /**< Buffer exhausted in mid frame */ + bUnderrun:1, /**< Transmit underrun */ + bError:1, /**< Retry limit exceeded, error detected */ + bWrap:1, /**< Marks last descriptor in TD list */ + bUsed:1; /**< User clear, EMAC sets this once a frame + has been successfully transmitted */ + } bm; + } status; +} PACKED_ATTR sEmacTxDescriptor; /* GCC */ + +/** @}*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** \addtogroup emac_functions + @{*/ +extern void EMAC_NetworkControl(Emac *pEmac, uint32_t bmNCR); +extern uint32_t EMAC_GetNetworkControl(Emac * pEmac); +extern void EMAC_ReceiveEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_TransmitEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_ManagementEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_ClearStatistics(Emac * pEmac); +extern void EMAC_IncreaseStatistics(Emac * pEmac); +extern void EMAC_StatisticsWriteEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_BackPressureEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_TransmissionStart(Emac * pEmac); +extern void EMAC_TransmissionHalt(Emac * pEmac); + +extern void EMAC_Configure(Emac * pEmac,uint32_t dwCfg); +extern uint32_t EMAC_GetConfigure(Emac * pEmac); +extern void EMAC_SetSpeed(Emac * pEmac,uint8_t bSpeed); +extern void EMAC_FullDuplexEnable(Emac * pEmac,uint8_t bFD); +extern void EMAC_CpyAllEnable(Emac * pEmac,uint8_t bCAF); +extern void EMAC_JumboFrameEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_BroadcastDisable(Emac * pEmac,uint8_t bDisEna); +extern void EMAC_MulticastHashEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_BigFrameEnable(Emac * pEmac,uint8_t bEnaDis); +extern uint8_t EMAC_SetClock(Emac * pEmac,uint32_t dwMck); +extern void EMAC_RetryTestEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_PauseFrameEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_SetRxBufferOffset(Emac * pEmac,uint8_t bOffset); +extern void EMAC_RxLenthCheckEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_DiscardFCSEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_EFRHD(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_IRXFCS(Emac * pEmac,uint8_t bEnaDis); + +extern uint32_t EMAC_GetStatus(Emac * pEmac); +extern uint8_t EMAC_GetMDIO(Emac * pEmac); +extern uint8_t EMAC_IsIdle(Emac * pEmac); + +extern uint32_t EMAC_GetTxStatus(Emac * pEmac); +extern void EMAC_ClearTxStatus(Emac * pEmac,uint32_t dwStatus); + +extern uint32_t EMAC_GetRxStatus(Emac * pEmac); +extern void EMAC_ClearRxStatus(Emac * pEmac,uint32_t dwStatus); + +extern void EMAC_SetTxQueue(Emac * pEmac,uint32_t dwAddr); +extern uint32_t EMAC_GetTxQueue(Emac * pEmac); + +extern void EMAC_SetRxQueue(Emac * pEmac,uint32_t dwAddr); +extern uint32_t EMAC_GetRxQueue(Emac * pEmac); + +extern void EMAC_EnableIt(Emac * pEmac,uint32_t dwSources); +extern void EMAC_DisableIt(Emac * pEmac,uint32_t dwSources); +extern uint32_t EMAC_GetItMask(Emac * pEmac); +extern uint32_t EMAC_GetItStatus(Emac * pEmac); + +extern void EMAC_PHYMaintain(Emac * pEmac, + uint8_t bPhyAddr, uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData); +extern uint16_t EMAC_PHYData(Emac * pEmac); + +extern void EMAC_SetPauseTime(Emac * pEmac,uint16_t wPTime); + +extern void EMAC_SetHash(Emac * pEmac,uint32_t dwHashTop,uint32_t dwHashBottom); +extern void EMAC_SetHash64(Emac * pEmac,uint64_t ddwHash); + +extern void EMAC_SetAddress(Emac * pEmac,uint8_t bIndex,uint8_t * pMacAddr); +extern void EMAC_SetAddress32(Emac * pEmac,uint8_t bIndex, + uint32_t dwMacT,uint32_t dwMacB); +extern void EMAC_SetAddress64(Emac * pEmac,uint8_t bIndex,uint64_t ddwMac); + +extern void EMAC_SetTypeID(Emac * pEmac,uint16_t wTID); +extern uint16_t EMAC_GetTypeID(Emac * pEmac); + +extern void EMAC_RMIIEnable(Emac * pEmac,uint8_t bEnaDis); +extern void EMAC_TransceiverClockEnable(Emac * pEmac,uint8_t bEnaDis); +/** @}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _EMAC_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/fuse.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/fuse.h new file mode 100644 index 000000000..aca9906a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/fuse.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Synchronous Serial (SSC) controller. + * + */ + +#ifndef _FUSE_ +#define _FUSE_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t FUSE_Read (uint8_t wordPosition ); +extern void FUSE_Write (uint32_t data, uint8_t wordPosition ); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _FUSE_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/gmac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/gmac.h new file mode 100644 index 000000000..7b6472313 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/gmac.h @@ -0,0 +1,238 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmac_module + * @{ + * Provides the interface to configure and use the GMAC peripheral. + * + * \section gmac_usage Usage + * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls + * are also available, such as: + * - GMAC_SetSpeed(): Setup GMAC working clock. + * - GMAC_FullDuplexEnable(): Working in full duplex or not. + * - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF). + * - ... + * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls + * can modify with: + * - GMAC_ReceiveEnable(): Enable/Disable Rx. + * - GMAC_TransmitEnable(): Enable/Disable Tx. + * - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving. + * - ... + * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(), + * GMAC_GetItMask() and GMAC_GetItStatus(). + * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus() + * GMAC_ClearTxStatus() and GMAC_ClearRxStatus(). + * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(), + * GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define + * by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor. + * - Manage PHY through GMAC is performed by + * - GMAC_ManagementEnable(): Enable/Disable PHY management. + * - GMAC_PHYMaintain(): Execute PHY management commands. + * - GMAC_PHYData(): Return PHY management data. + * - GMAC_IsIdle(): Check if PHY is idle. + * - Setup GMAC parameters with following functions: + * - GMAC_SetHash(): Set Hash value. + * - GMAC_SetAddress(): Set MAC address. + * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable() + * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable() + * + * For more accurate information, please look at the GMAC section of the + * Datasheet. + * + * \sa \ref gmacd_module + * + * Related files:\n + * gmac.c\n + * gmac.h.\n + * + * \defgroup gmac_defines GMAC Defines + * \defgroup gmac_structs GMAC Data Structs + * \defgroup gmac_functions GMAC Functions + */ +/**@}*/ + +#ifndef _GMAC_H +#define _GMAC_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_defines + @{*/ + +/// Board GMAC base address + +/// Number of buffer for RX, be carreful: MUST be 2^n +#define GRX_BUFFERS 16 +/// Number of buffer for TX, be carreful: MUST be 2^n +#define GTX_BUFFERS 8 + +/// Buffer Size +#define GMAC_RX_UNITSIZE 128 /// Fixed size for RX buffer +#define GMAC_TX_UNITSIZE 1518 /// Size for ETH frame length + +// The MAC can support frame lengths up to 1536 bytes. +#define GMAC_FRAME_LENTGH_MAX 1536 + +// +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +// +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 +#define GMAC_SPEED_1000M 2 +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_structs + @{*/ +/** Receive buffer descriptor struct */ +typedef struct _GmacRxDescriptor { + union _GmacRxAddr { + uint32_t val; + struct _GmacRxAddrBM { + uint32_t bOwnership:1, /**< User clear, GMAC set this to one once + it has successfully written a frame to + memory */ + bWrap:1, /**< Marks last descriptor in receive buffer */ + addrDW:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union _GmacRxStatus { + uint32_t val; + struct _GmacRxStatusBM { + uint32_t len:12, /** Length of frame including FCS */ + offset:2, /** Receive buffer offset, + bits 13:12 of frame length for jumbo + frame */ + bSof:1, /** Start of frame */ + bEof:1, /** End of frame */ + bCFI:1, /** Concatenation Format Indicator */ + vlanPriority:3, /** VLAN priority (if VLAN detected) */ + bPriorityDetected:1, /** Priority tag detected */ + bVlanDetected:1, /**< VLAN tag detected */ + bTypeIDMatch:1, /**< Type ID match */ + bAddr4Match:1, /**< Address register 4 match */ + bAddr3Match:1, /**< Address register 3 match */ + bAddr2Match:1, /**< Address register 2 match */ + bAddr1Match:1, /**< Address register 1 match */ + reserved:1, + bExtAddrMatch:1, /**< External address match */ + bUniHashMatch:1, /**< Unicast hash match */ + bMultiHashMatch:1, /**< Multicast hash match */ + bBroadcastDetected:1; /**< Global all ones broadcast + address detected */ + } bm; + } status; +} sGmacRxDescriptor; /* GCC */ + +/** Transmit buffer descriptor struct */ +typedef struct _GmacTxDescriptor { + uint32_t addr; + union _GmacTxStatus { + uint32_t val; + struct _GmacTxStatusBM { + uint32_t len:11, /**< Length of buffer */ + reserved:4, + bLastBuffer:1, /**< Last buffer (in the current frame) */ + bNoCRC:1, /**< No CRC */ + reserved1:10, + bExhausted:1, /**< Buffer exhausted in mid frame */ + bUnderrun:1, /**< Transmit underrun */ + bError:1, /**< Retry limit exceeded, error detected */ + bWrap:1, /**< Marks last descriptor in TD list */ + bUsed:1; /**< User clear, GMAC sets this once a frame + has been successfully transmitted */ + } bm; + } status; +} sGmacTxDescriptor; /* GCC */ + +/** @}*/ + +//----------------------------------------------------------------------------- +// PHY Exported functions +//----------------------------------------------------------------------------- +extern uint8_t GMAC_IsIdle(Gmac *pGmac); +extern void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData); +extern uint16_t GMAC_PHYData(Gmac *pGmac); +extern void GMAC_ClearStatistics(Gmac *pGmac); +extern void GMAC_IncreaseStatistics(Gmac *pGmac); +extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck ); +extern void GMAC_EnableMdio(Gmac *pGmac ); +extern void GMAC_DisableMdio(Gmac *pGmac ); +extern void GMAC_EnableMII(Gmac *pGmac ); +extern void GMAC_EnableRMII(Gmac *pGmac ); +extern void GMAC_EnableGMII( Gmac *pGmac ); +extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex); +extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources); +extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources); +extern uint32_t GMAC_GetItStatus(Gmac *pGmac); +extern uint32_t GMAC_GetItMask(Gmac *pGmac); +extern uint32_t GMAC_GetTxStatus(Gmac *pGmac); +extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus); +extern uint32_t GMAC_GetRxStatus(Gmac *pGmac); +extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus); +extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis); +extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis); +extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr); +extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac); +extern uint32_t GMAC_GetRxQueue(Gmac *pGmac); +extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr); +extern uint32_t GMAC_GetTxQueue(Gmac *pGmac); +extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR); +extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac); +extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr); +extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB); +extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac); +extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg); +extern uint32_t GMAC_GetConfigure(Gmac *pGmac); +extern void GMAC_TransmissionStart(Gmac *pGmac); +extern void GMAC_TransmissionHalt(Gmac *pGmac); +extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed); +#endif // #ifndef GMAC_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/hsmci.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/hsmci.h new file mode 100644 index 000000000..43c420686 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/hsmci.h @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup hsmci_module Working with HSMCI + * \ingroup mcid_module + * + * \section Purpose + * + * The HSMCI driver provides the interface to configure and use the HSMCI + * peripheral. + * + * \section Usage + * + * -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface. + * -# HSMCI_Reset(): Reset HSMCI interface. + * -# HSMCI_Select(): HSMCI slot and buswidth selection + * (\ref Hsmci::HSMCI_SDCR). + * -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register + * (\ref Hsmci::HSMCI_MR). + * -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus() + * HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR, + * \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR). + * -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer + * (\ref Hsmci::HSMCI_BLKR). + * -# HSMCI_SendCmd(): Send SD/MMC command with argument + * (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR). + * -# HSMCI_GetResponse(): Get SD/MMC response after command finished + * (\ref Hsmci::HSMCI_RSPR). + * -# HSMCI_ConfigureDma(): Configure MCI DMA transfer + * (\ref Hsmci::HSMCI_DMA). + * -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG). + * -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control. + * + * For more accurate information, please look at the HSMCI section of the + * Datasheet. + * + * \sa \ref mcid_module + * + * Related files :\n + * \ref hsmci.h\n + * \ref hsmci.c.\n + */ + +#ifndef HSMCID_H +#define HSMCID_H +/** \addtogroup hsmci_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup hsmci_functions HSMCI Functions + * @{ + */ + +extern void HSMCI_Enable(Hsmci* pRMci); +extern void HSMCI_Disable(Hsmci* pRMci); +extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup); + +extern void HSMCI_Select(Hsmci * pRMci,uint8_t bSlot,uint8_t bBusWidth); +extern void HSMCI_SetSlot(Hsmci * pRMci,uint8_t bSlot); +extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth); +extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci); + +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode); +extern uint32_t HSMCI_GetMode(Hsmci *pRMci); +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof); +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv); +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn); +extern uint8_t HSMCI_IsFByteEnabled(Hsmci * pRMci); +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv); + +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources); +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources); +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci); + +extern void HSMCI_ConfigureTransfer(Hsmci * pRMci,uint16_t wBlkLen,uint16_t wCnt); +extern void HSMCI_SetBlockLen(Hsmci * pRMci,uint16_t wBlkSize); +extern void HSMCI_SetBlockCount(Hsmci * pRMci,uint16_t wBlkCnt); + +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure); + +extern void HSMCI_SendCmd(Hsmci * pRMci,uint32_t dwCmd,uint32_t dwArg); +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci); +extern uint32_t HSMCI_Read(Hsmci *pRMci); +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData); +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); + +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci); + +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_EnableDma(Hsmci * pRMci,uint8_t bEnable); +extern void HSMCI_SetDmaOffset(Hsmci * pRMci,uint8_t bOffset); + +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable); +extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci); + +extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth); +extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot); +extern uint8_t HSMCI_GetSlot(Hsmci *pRMci); + +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure); +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci); + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_adc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_adc.h new file mode 100644 index 000000000..850e8c08a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_adc.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_ADC_INSTANCE_ +#define _SAMA5_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CR (0xF8018000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (0xF8018004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (0xF8018008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (0xF801800CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (0xF8018010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (0xF8018014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (0xF8018018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (0xF8018020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (0xF8018024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (0xF8018028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (0xF801802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (0xF8018030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (0xF801803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (0xF8018040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (0xF8018044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (0xF8018048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (0xF801804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (0xF8018050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (0xF8018094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_TSMR (0xF80180B0U) /**< \brief (ADC) Touchscreen Mode Register */ +#define REG_ADC_XPOSR (0xF80180B4U) /**< \brief (ADC) Touchscreen X Position Register */ +#define REG_ADC_YPOSR (0xF80180B8U) /**< \brief (ADC) Touchscreen Y Position Register */ +#define REG_ADC_PRESSR (0xF80180BCU) /**< \brief (ADC) Touchscreen Pressure Register */ +#define REG_ADC_TRGR (0xF80180C0U) /**< \brief (ADC) Trigger Register */ +#define REG_ADC_WPMR (0xF80180E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (0xF80180E8U) /**< \brief (ADC) Write Protect Status Register */ +#else +#define REG_ADC_CR (*(WoReg*)0xF8018000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (*(RwReg*)0xF8018004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (*(RwReg*)0xF8018008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (*(RwReg*)0xF801800CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (*(WoReg*)0xF8018010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (*(WoReg*)0xF8018014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (*(RoReg*)0xF8018018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (*(RoReg*)0xF8018020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (*(WoReg*)0xF8018024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (*(WoReg*)0xF8018028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (*(RoReg*)0xF801802CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (*(RoReg*)0xF8018030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (*(RoReg*)0xF801803CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (*(RwReg*)0xF8018040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (*(RwReg*)0xF8018044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (*(RwReg*)0xF8018048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (*(RwReg*)0xF801804CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (*(RoReg*)0xF8018050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (*(RwReg*)0xF8018094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_TSMR (*(RwReg*)0xF80180B0U) /**< \brief (ADC) Touchscreen Mode Register */ +#define REG_ADC_XPOSR (*(RoReg*)0xF80180B4U) /**< \brief (ADC) Touchscreen X Position Register */ +#define REG_ADC_YPOSR (*(RoReg*)0xF80180B8U) /**< \brief (ADC) Touchscreen Y Position Register */ +#define REG_ADC_PRESSR (*(RoReg*)0xF80180BCU) /**< \brief (ADC) Touchscreen Pressure Register */ +#define REG_ADC_TRGR (*(RwReg*)0xF80180C0U) /**< \brief (ADC) Trigger Register */ +#define REG_ADC_WPMR (*(RwReg*)0xF80180E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (*(RoReg*)0xF80180E8U) /**< \brief (ADC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_ADC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aes.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aes.h new file mode 100644 index 000000000..0f6100665 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aes.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AES_INSTANCE_ +#define _SAMA5_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AES_CR (0xF8038000U) /**< \brief (AES) Control Register */ +#define REG_AES_MR (0xF8038004U) /**< \brief (AES) Mode Register */ +#define REG_AES_IER (0xF8038010U) /**< \brief (AES) Interrupt Enable Register */ +#define REG_AES_IDR (0xF8038014U) /**< \brief (AES) Interrupt Disable Register */ +#define REG_AES_IMR (0xF8038018U) /**< \brief (AES) Interrupt Mask Register */ +#define REG_AES_ISR (0xF803801CU) /**< \brief (AES) Interrupt Status Register */ +#define REG_AES_KEYWR (0xF8038020U) /**< \brief (AES) Key Word Register */ +#define REG_AES_IDATAR (0xF8038040U) /**< \brief (AES) Input Data Register */ +#define REG_AES_ODATAR (0xF8038050U) /**< \brief (AES) Output Data Register */ +#define REG_AES_IVR (0xF8038060U) /**< \brief (AES) Initialization Vector Register */ +#else +#define REG_AES_CR (*(WoReg*)0xF8038000U) /**< \brief (AES) Control Register */ +#define REG_AES_MR (*(RwReg*)0xF8038004U) /**< \brief (AES) Mode Register */ +#define REG_AES_IER (*(WoReg*)0xF8038010U) /**< \brief (AES) Interrupt Enable Register */ +#define REG_AES_IDR (*(WoReg*)0xF8038014U) /**< \brief (AES) Interrupt Disable Register */ +#define REG_AES_IMR (*(RoReg*)0xF8038018U) /**< \brief (AES) Interrupt Mask Register */ +#define REG_AES_ISR (*(RoReg*)0xF803801CU) /**< \brief (AES) Interrupt Status Register */ +#define REG_AES_KEYWR (*(WoReg*)0xF8038020U) /**< \brief (AES) Key Word Register */ +#define REG_AES_IDATAR (*(WoReg*)0xF8038040U) /**< \brief (AES) Input Data Register */ +#define REG_AES_ODATAR (*(RoReg*)0xF8038050U) /**< \brief (AES) Output Data Register */ +#define REG_AES_IVR (*(WoReg*)0xF8038060U) /**< \brief (AES) Initialization Vector Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_AES_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aic.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aic.h new file mode 100644 index 000000000..cc0344370 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aic.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AIC_INSTANCE_ +#define _SAMA5_AIC_INSTANCE_ + +/* ========== Register definition for AIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AIC_SSR (0xFFFFF000U) /**< \brief (AIC) Source Select Register */ +#define REG_AIC_SMR (0xFFFFF004U) /**< \brief (AIC) Source Mode Register */ +#define REG_AIC_SVR (0xFFFFF008U) /**< \brief (AIC) Source Vector Register */ +#define REG_AIC_IVR (0xFFFFF010U) /**< \brief (AIC) Interrupt Vector Register */ +#define REG_AIC_FVR (0xFFFFF014U) /**< \brief (AIC) FIQ Interrupt Vector Register */ +#define REG_AIC_ISR (0xFFFFF018U) /**< \brief (AIC) Interrupt Status Register */ +#define REG_AIC_IPR0 (0xFFFFF020U) /**< \brief (AIC) Interrupt Pending Register 0 */ +#define REG_AIC_IPR1 (0xFFFFF024U) /**< \brief (AIC) Interrupt Pending Register 1 */ +#define REG_AIC_IPR2 (0xFFFFF028U) /**< \brief (AIC) Interrupt Pending Register 2 */ +#define REG_AIC_IPR3 (0xFFFFF02CU) /**< \brief (AIC) Interrupt Pending Register 3 */ +#define REG_AIC_IMR (0xFFFFF030U) /**< \brief (AIC) Interrupt Mask Register */ +#define REG_AIC_CISR (0xFFFFF034U) /**< \brief (AIC) Core Interrupt Status Register */ +#define REG_AIC_EOICR (0xFFFFF038U) /**< \brief (AIC) End of Interrupt Command Register */ +#define REG_AIC_SPU (0xFFFFF03CU) /**< \brief (AIC) Spurious Interrupt Vector Register */ +#define REG_AIC_IECR (0xFFFFF040U) /**< \brief (AIC) Interrupt Enable Command Register */ +#define REG_AIC_IDCR (0xFFFFF044U) /**< \brief (AIC) Interrupt Disable Command Register */ +#define REG_AIC_ICCR (0xFFFFF048U) /**< \brief (AIC) Interrupt Clear Command Register */ +#define REG_AIC_ISCR (0xFFFFF04CU) /**< \brief (AIC) Interrupt Set Command Register */ +#define REG_AIC_FFER (0xFFFFF050U) /**< \brief (AIC) Fast Forcing Enable Register */ +#define REG_AIC_FFDR (0xFFFFF054U) /**< \brief (AIC) Fast Forcing Disable Register */ +#define REG_AIC_FFSR (0xFFFFF058U) /**< \brief (AIC) Fast Forcing Status Register */ +#define REG_AIC_DCR (0xFFFFF06CU) /**< \brief (AIC) Debug Control Register */ +#define REG_AIC_WPMR (0xFFFFF0E4U) /**< \brief (AIC) Write Protect Mode Register */ +#define REG_AIC_WPSR (0xFFFFF0E8U) /**< \brief (AIC) Write Protect Status Register */ +#else +#define REG_AIC_SSR (*(RwReg*)0xFFFFF000U) /**< \brief (AIC) Source Select Register */ +#define REG_AIC_SMR (*(RwReg*)0xFFFFF004U) /**< \brief (AIC) Source Mode Register */ +#define REG_AIC_SVR (*(RwReg*)0xFFFFF008U) /**< \brief (AIC) Source Vector Register */ +#define REG_AIC_IVR (*(RoReg*)0xFFFFF010U) /**< \brief (AIC) Interrupt Vector Register */ +#define REG_AIC_FVR (*(RoReg*)0xFFFFF014U) /**< \brief (AIC) FIQ Interrupt Vector Register */ +#define REG_AIC_ISR (*(RoReg*)0xFFFFF018U) /**< \brief (AIC) Interrupt Status Register */ +#define REG_AIC_IPR0 (*(RoReg*)0xFFFFF020U) /**< \brief (AIC) Interrupt Pending Register 0 */ +#define REG_AIC_IPR1 (*(RoReg*)0xFFFFF024U) /**< \brief (AIC) Interrupt Pending Register 1 */ +#define REG_AIC_IPR2 (*(RoReg*)0xFFFFF028U) /**< \brief (AIC) Interrupt Pending Register 2 */ +#define REG_AIC_IPR3 (*(RoReg*)0xFFFFF02CU) /**< \brief (AIC) Interrupt Pending Register 3 */ +#define REG_AIC_IMR (*(RoReg*)0xFFFFF030U) /**< \brief (AIC) Interrupt Mask Register */ +#define REG_AIC_CISR (*(RoReg*)0xFFFFF034U) /**< \brief (AIC) Core Interrupt Status Register */ +#define REG_AIC_EOICR (*(WoReg*)0xFFFFF038U) /**< \brief (AIC) End of Interrupt Command Register */ +#define REG_AIC_SPU (*(RwReg*)0xFFFFF03CU) /**< \brief (AIC) Spurious Interrupt Vector Register */ +#define REG_AIC_IECR (*(WoReg*)0xFFFFF040U) /**< \brief (AIC) Interrupt Enable Command Register */ +#define REG_AIC_IDCR (*(WoReg*)0xFFFFF044U) /**< \brief (AIC) Interrupt Disable Command Register */ +#define REG_AIC_ICCR (*(WoReg*)0xFFFFF048U) /**< \brief (AIC) Interrupt Clear Command Register */ +#define REG_AIC_ISCR (*(WoReg*)0xFFFFF04CU) /**< \brief (AIC) Interrupt Set Command Register */ +#define REG_AIC_FFER (*(WoReg*)0xFFFFF050U) /**< \brief (AIC) Fast Forcing Enable Register */ +#define REG_AIC_FFDR (*(WoReg*)0xFFFFF054U) /**< \brief (AIC) Fast Forcing Disable Register */ +#define REG_AIC_FFSR (*(RoReg*)0xFFFFF058U) /**< \brief (AIC) Fast Forcing Status Register */ +#define REG_AIC_DCR (*(RwReg*)0xFFFFF06CU) /**< \brief (AIC) Debug Control Register */ +#define REG_AIC_WPMR (*(RwReg*)0xFFFFF0E4U) /**< \brief (AIC) Write Protect Mode Register */ +#define REG_AIC_WPSR (*(RoReg*)0xFFFFF0E8U) /**< \brief (AIC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_AIC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aximx.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aximx.h new file mode 100644 index 000000000..00b6ef9df --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_aximx.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_AXIMX_INSTANCE_ +#define _SAMA5_AXIMX_INSTANCE_ + +/* ========== Register definition for AXIMX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AXIMX_REMAP (0x00800000U) /**< \brief (AXIMX) Remap Register */ +#define REG_AXIMX_PERIPH_ID4 (0x00801FD0U) /**< \brief (AXIMX) Peripheral ID Register 4 */ +#define REG_AXIMX_PERIPH_ID5 (0x00801FD4U) /**< \brief (AXIMX) Peripheral ID Register 5 */ +#define REG_AXIMX_PERIPH_ID6 (0x00801FD8U) /**< \brief (AXIMX) Peripheral ID Register 6 */ +#define REG_AXIMX_PERIPH_ID7 (0x00801FDCU) /**< \brief (AXIMX) Peripheral ID Register 7 */ +#define REG_AXIMX_PERIPH_ID0 (0x00801FE0U) /**< \brief (AXIMX) Peripheral ID Register 0 */ +#define REG_AXIMX_PERIPH_ID1 (0x00801FE4U) /**< \brief (AXIMX) Peripheral ID Register 1 */ +#define REG_AXIMX_PERIPH_ID2 (0x00801FE8U) /**< \brief (AXIMX) Peripheral ID Register 2 */ +#define REG_AXIMX_PERIPH_ID3 (0x00801FECU) /**< \brief (AXIMX) Peripheral ID Register 3 */ +#define REG_AXIMX_COMP_ID (0x00801FF0U) /**< \brief (AXIMX) Component ID Register */ +#define REG_AXIMX_AMIB3_FN_MOD_BM_ISS (0x00805008U) /**< \brief (AXIMX) AMIB3 Bus Matrix Functionality Modification Register */ +#define REG_AXIMX_AMIB3_FN_MOD2 (0x00805024U) /**< \brief (AXIMX) AMIB3 Bypass Merge */ +#define REG_AXIMX_ASIB0_READ_QOS (0x00842100U) /**< \brief (AXIMX) ASIB0 Read Channel QoS Register */ +#define REG_AXIMX_ASIB0_WRITE_QOS (0x00842104U) /**< \brief (AXIMX) ASIB0 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD_AHB (0x00843028U) /**< \brief (AXIMX) ASIB1 AHB Functionality Modification Register */ +#define REG_AXIMX_ASIB1_READ_QOS (0x00843100U) /**< \brief (AXIMX) ASIB1 Read Channel QoS Register */ +#define REG_AXIMX_ASIB1_WRITE_QOS (0x00843104U) /**< \brief (AXIMX) ASIB1 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD (0x00843108U) /**< \brief (AXIMX) ASIB1 Issuing Functionality Modification Register */ +#else +#define REG_AXIMX_REMAP (*(WoReg*)0x00800000U) /**< \brief (AXIMX) Remap Register */ +#define REG_AXIMX_PERIPH_ID4 (*(RoReg*)0x00801FD0U) /**< \brief (AXIMX) Peripheral ID Register 4 */ +#define REG_AXIMX_PERIPH_ID5 (*(RoReg*)0x00801FD4U) /**< \brief (AXIMX) Peripheral ID Register 5 */ +#define REG_AXIMX_PERIPH_ID6 (*(RoReg*)0x00801FD8U) /**< \brief (AXIMX) Peripheral ID Register 6 */ +#define REG_AXIMX_PERIPH_ID7 (*(RoReg*)0x00801FDCU) /**< \brief (AXIMX) Peripheral ID Register 7 */ +#define REG_AXIMX_PERIPH_ID0 (*(RoReg*)0x00801FE0U) /**< \brief (AXIMX) Peripheral ID Register 0 */ +#define REG_AXIMX_PERIPH_ID1 (*(RoReg*)0x00801FE4U) /**< \brief (AXIMX) Peripheral ID Register 1 */ +#define REG_AXIMX_PERIPH_ID2 (*(RoReg*)0x00801FE8U) /**< \brief (AXIMX) Peripheral ID Register 2 */ +#define REG_AXIMX_PERIPH_ID3 (*(RoReg*)0x00801FECU) /**< \brief (AXIMX) Peripheral ID Register 3 */ +#define REG_AXIMX_COMP_ID (*(RoReg*)0x00801FF0U) /**< \brief (AXIMX) Component ID Register */ +#define REG_AXIMX_AMIB3_FN_MOD_BM_ISS (*(RwReg*)0x00805008U) /**< \brief (AXIMX) AMIB3 Bus Matrix Functionality Modification Register */ +#define REG_AXIMX_AMIB3_FN_MOD2 (*(RwReg*)0x00805024U) /**< \brief (AXIMX) AMIB3 Bypass Merge */ +#define REG_AXIMX_ASIB0_READ_QOS (*(RwReg*)0x00842100U) /**< \brief (AXIMX) ASIB0 Read Channel QoS Register */ +#define REG_AXIMX_ASIB0_WRITE_QOS (*(RwReg*)0x00842104U) /**< \brief (AXIMX) ASIB0 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD_AHB (*(RwReg*)0x00843028U) /**< \brief (AXIMX) ASIB1 AHB Functionality Modification Register */ +#define REG_AXIMX_ASIB1_READ_QOS (*(RwReg*)0x00843100U) /**< \brief (AXIMX) ASIB1 Read Channel QoS Register */ +#define REG_AXIMX_ASIB1_WRITE_QOS (*(RwReg*)0x00843104U) /**< \brief (AXIMX) ASIB1 Write Channel QoS Register */ +#define REG_AXIMX_ASIB1_FN_MOD (*(RwReg*)0x00843108U) /**< \brief (AXIMX) ASIB1 Issuing Functionality Modification Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_AXIMX_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_bsc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_bsc.h new file mode 100644 index 000000000..d79cc1f38 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_bsc.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_BSC_INSTANCE_ +#define _SAMA5_BSC_INSTANCE_ + +/* ========== Register definition for BSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_BSC_CR (0xFFFFFE54U) /**< \brief (BSC) Boot Sequence Configuration Register */ +#else +#define REG_BSC_CR (*(RwReg*)0xFFFFFE54U) /**< \brief (BSC) Boot Sequence Configuration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_BSC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can0.h new file mode 100644 index 000000000..69e79ffeb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can0.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_CAN0_INSTANCE_ +#define _SAMA5_CAN0_INSTANCE_ + +/* ========== Register definition for CAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN0_MR (0xF000C000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (0xF000C004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (0xF000C008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (0xF000C00CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (0xF000C010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (0xF000C014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (0xF000C018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (0xF000C01CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (0xF000C020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (0xF000C024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (0xF000C028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (0xF000C0E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (0xF000C0E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (0xF000C200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (0xF000C204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (0xF000C208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (0xF000C20CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (0xF000C210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (0xF000C214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (0xF000C218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (0xF000C21CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (0xF000C220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (0xF000C224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (0xF000C228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (0xF000C22CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (0xF000C230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (0xF000C234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (0xF000C238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (0xF000C23CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (0xF000C240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (0xF000C244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (0xF000C248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (0xF000C24CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (0xF000C250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (0xF000C254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (0xF000C258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (0xF000C25CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (0xF000C260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (0xF000C264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (0xF000C268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (0xF000C26CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (0xF000C270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (0xF000C274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (0xF000C278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (0xF000C27CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (0xF000C280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (0xF000C284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (0xF000C288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (0xF000C28CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (0xF000C290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (0xF000C294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (0xF000C298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (0xF000C29CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (0xF000C2A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (0xF000C2A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (0xF000C2A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (0xF000C2ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (0xF000C2B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (0xF000C2B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (0xF000C2B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (0xF000C2BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (0xF000C2C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (0xF000C2C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (0xF000C2C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (0xF000C2CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (0xF000C2D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (0xF000C2D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (0xF000C2D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (0xF000C2DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (0xF000C2E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (0xF000C2E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (0xF000C2E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (0xF000C2ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (0xF000C2F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (0xF000C2F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (0xF000C2F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (0xF000C2FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN0_MR (*(RwReg*)0xF000C000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (*(WoReg*)0xF000C004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (*(WoReg*)0xF000C008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (*(RoReg*)0xF000C00CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (*(RoReg*)0xF000C010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (*(RwReg*)0xF000C014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (*(RoReg*)0xF000C018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (*(RoReg*)0xF000C01CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (*(RoReg*)0xF000C020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (*(WoReg*)0xF000C024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (*(WoReg*)0xF000C028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (*(RwReg*)0xF000C0E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (*(RoReg*)0xF000C0E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (*(RwReg*)0xF000C200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (*(RwReg*)0xF000C204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (*(RwReg*)0xF000C208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (*(RoReg*)0xF000C20CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (*(RoReg*)0xF000C210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (*(RwReg*)0xF000C214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (*(RwReg*)0xF000C218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (*(WoReg*)0xF000C21CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (*(RwReg*)0xF000C220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (*(RwReg*)0xF000C224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (*(RwReg*)0xF000C228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (*(RoReg*)0xF000C22CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (*(RoReg*)0xF000C230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (*(RwReg*)0xF000C234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (*(RwReg*)0xF000C238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (*(WoReg*)0xF000C23CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (*(RwReg*)0xF000C240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (*(RwReg*)0xF000C244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (*(RwReg*)0xF000C248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (*(RoReg*)0xF000C24CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (*(RoReg*)0xF000C250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (*(RwReg*)0xF000C254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (*(RwReg*)0xF000C258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (*(WoReg*)0xF000C25CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (*(RwReg*)0xF000C260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (*(RwReg*)0xF000C264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (*(RwReg*)0xF000C268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (*(RoReg*)0xF000C26CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (*(RoReg*)0xF000C270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (*(RwReg*)0xF000C274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (*(RwReg*)0xF000C278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (*(WoReg*)0xF000C27CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (*(RwReg*)0xF000C280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (*(RwReg*)0xF000C284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (*(RwReg*)0xF000C288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (*(RoReg*)0xF000C28CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (*(RoReg*)0xF000C290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (*(RwReg*)0xF000C294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (*(RwReg*)0xF000C298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (*(WoReg*)0xF000C29CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (*(RwReg*)0xF000C2A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (*(RwReg*)0xF000C2A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (*(RwReg*)0xF000C2A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (*(RoReg*)0xF000C2ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (*(RoReg*)0xF000C2B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (*(RwReg*)0xF000C2B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (*(RwReg*)0xF000C2B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (*(WoReg*)0xF000C2BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (*(RwReg*)0xF000C2C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (*(RwReg*)0xF000C2C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (*(RwReg*)0xF000C2C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (*(RoReg*)0xF000C2CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (*(RoReg*)0xF000C2D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (*(RwReg*)0xF000C2D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (*(RwReg*)0xF000C2D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (*(WoReg*)0xF000C2DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (*(RwReg*)0xF000C2E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (*(RwReg*)0xF000C2E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (*(RwReg*)0xF000C2E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (*(RoReg*)0xF000C2ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (*(RoReg*)0xF000C2F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (*(RwReg*)0xF000C2F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (*(RwReg*)0xF000C2F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (*(WoReg*)0xF000C2FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_CAN0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can1.h new file mode 100644 index 000000000..1c6f460f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_can1.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_CAN1_INSTANCE_ +#define _SAMA5_CAN1_INSTANCE_ + +/* ========== Register definition for CAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN1_MR (0xF8010000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (0xF8010004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (0xF8010008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (0xF801000CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (0xF8010010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (0xF8010014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (0xF8010018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (0xF801001CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (0xF8010020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (0xF8010024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (0xF8010028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (0xF80100E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (0xF80100E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (0xF8010200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (0xF8010204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (0xF8010208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (0xF801020CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (0xF8010210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (0xF8010214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (0xF8010218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (0xF801021CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (0xF8010220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (0xF8010224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (0xF8010228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (0xF801022CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (0xF8010230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (0xF8010234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (0xF8010238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (0xF801023CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (0xF8010240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (0xF8010244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (0xF8010248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (0xF801024CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (0xF8010250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (0xF8010254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (0xF8010258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (0xF801025CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (0xF8010260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (0xF8010264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (0xF8010268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (0xF801026CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (0xF8010270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (0xF8010274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (0xF8010278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (0xF801027CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (0xF8010280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (0xF8010284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (0xF8010288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (0xF801028CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (0xF8010290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (0xF8010294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (0xF8010298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (0xF801029CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (0xF80102A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (0xF80102A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (0xF80102A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (0xF80102ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (0xF80102B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (0xF80102B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (0xF80102B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (0xF80102BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (0xF80102C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (0xF80102C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (0xF80102C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (0xF80102CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (0xF80102D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (0xF80102D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (0xF80102D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (0xF80102DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (0xF80102E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (0xF80102E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (0xF80102E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (0xF80102ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (0xF80102F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (0xF80102F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (0xF80102F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (0xF80102FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN1_MR (*(RwReg*)0xF8010000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (*(WoReg*)0xF8010004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (*(WoReg*)0xF8010008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (*(RoReg*)0xF801000CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (*(RoReg*)0xF8010010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (*(RwReg*)0xF8010014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (*(RoReg*)0xF8010018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (*(RoReg*)0xF801001CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (*(RoReg*)0xF8010020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (*(WoReg*)0xF8010024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (*(WoReg*)0xF8010028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (*(RwReg*)0xF80100E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (*(RoReg*)0xF80100E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (*(RwReg*)0xF8010200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (*(RwReg*)0xF8010204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (*(RwReg*)0xF8010208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (*(RoReg*)0xF801020CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (*(RoReg*)0xF8010210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (*(RwReg*)0xF8010214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (*(RwReg*)0xF8010218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (*(WoReg*)0xF801021CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (*(RwReg*)0xF8010220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (*(RwReg*)0xF8010224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (*(RwReg*)0xF8010228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (*(RoReg*)0xF801022CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (*(RoReg*)0xF8010230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (*(RwReg*)0xF8010234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (*(RwReg*)0xF8010238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (*(WoReg*)0xF801023CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (*(RwReg*)0xF8010240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (*(RwReg*)0xF8010244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (*(RwReg*)0xF8010248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (*(RoReg*)0xF801024CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (*(RoReg*)0xF8010250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (*(RwReg*)0xF8010254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (*(RwReg*)0xF8010258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (*(WoReg*)0xF801025CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (*(RwReg*)0xF8010260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (*(RwReg*)0xF8010264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (*(RwReg*)0xF8010268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (*(RoReg*)0xF801026CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (*(RoReg*)0xF8010270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (*(RwReg*)0xF8010274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (*(RwReg*)0xF8010278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (*(WoReg*)0xF801027CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (*(RwReg*)0xF8010280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (*(RwReg*)0xF8010284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (*(RwReg*)0xF8010288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (*(RoReg*)0xF801028CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (*(RoReg*)0xF8010290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (*(RwReg*)0xF8010294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (*(RwReg*)0xF8010298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (*(WoReg*)0xF801029CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (*(RwReg*)0xF80102A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (*(RwReg*)0xF80102A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (*(RwReg*)0xF80102A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (*(RoReg*)0xF80102ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (*(RoReg*)0xF80102B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (*(RwReg*)0xF80102B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (*(RwReg*)0xF80102B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (*(WoReg*)0xF80102BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (*(RwReg*)0xF80102C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (*(RwReg*)0xF80102C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (*(RwReg*)0xF80102C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (*(RoReg*)0xF80102CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (*(RoReg*)0xF80102D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (*(RwReg*)0xF80102D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (*(RwReg*)0xF80102D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (*(WoReg*)0xF80102DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (*(RwReg*)0xF80102E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (*(RwReg*)0xF80102E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (*(RwReg*)0xF80102E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (*(RoReg*)0xF80102ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (*(RoReg*)0xF80102F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (*(RwReg*)0xF80102F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (*(RwReg*)0xF80102F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (*(WoReg*)0xF80102FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_CAN1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dbgu.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dbgu.h new file mode 100644 index 000000000..475fb2418 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dbgu.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DBGU_INSTANCE_ +#define _SAMA5_DBGU_INSTANCE_ + +/* ========== Register definition for DBGU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DBGU_CR (0xFFFFEE00U) /**< \brief (DBGU) Control Register */ +#define REG_DBGU_MR (0xFFFFEE04U) /**< \brief (DBGU) Mode Register */ +#define REG_DBGU_IER (0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */ +#define REG_DBGU_IDR (0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */ +#define REG_DBGU_IMR (0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */ +#define REG_DBGU_SR (0xFFFFEE14U) /**< \brief (DBGU) Status Register */ +#define REG_DBGU_RHR (0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */ +#define REG_DBGU_THR (0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */ +#define REG_DBGU_BRGR (0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */ +#define REG_DBGU_CIDR (0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */ +#define REG_DBGU_EXID (0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */ +#define REG_DBGU_FNR (0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */ +#else +#define REG_DBGU_CR (*(WoReg*)0xFFFFEE00U) /**< \brief (DBGU) Control Register */ +#define REG_DBGU_MR (*(RwReg*)0xFFFFEE04U) /**< \brief (DBGU) Mode Register */ +#define REG_DBGU_IER (*(WoReg*)0xFFFFEE08U) /**< \brief (DBGU) Interrupt Enable Register */ +#define REG_DBGU_IDR (*(WoReg*)0xFFFFEE0CU) /**< \brief (DBGU) Interrupt Disable Register */ +#define REG_DBGU_IMR (*(RoReg*)0xFFFFEE10U) /**< \brief (DBGU) Interrupt Mask Register */ +#define REG_DBGU_SR (*(RoReg*)0xFFFFEE14U) /**< \brief (DBGU) Status Register */ +#define REG_DBGU_RHR (*(RoReg*)0xFFFFEE18U) /**< \brief (DBGU) Receive Holding Register */ +#define REG_DBGU_THR (*(WoReg*)0xFFFFEE1CU) /**< \brief (DBGU) Transmit Holding Register */ +#define REG_DBGU_BRGR (*(RwReg*)0xFFFFEE20U) /**< \brief (DBGU) Baud Rate Generator Register */ +#define REG_DBGU_CIDR (*(RoReg*)0xFFFFEE40U) /**< \brief (DBGU) Chip ID Register */ +#define REG_DBGU_EXID (*(RoReg*)0xFFFFEE44U) /**< \brief (DBGU) Chip ID Extension Register */ +#define REG_DBGU_FNR (*(RwReg*)0xFFFFEE48U) /**< \brief (DBGU) Force NTRST Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_DBGU_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac0.h new file mode 100644 index 000000000..97e910399 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac0.h @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DMAC0_INSTANCE_ +#define _SAMA5_DMAC0_INSTANCE_ + +/* ========== Register definition for DMAC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC0_GCFG (0xFFFFE600U) /**< \brief (DMAC0) DMAC Global Configuration Register */ +#define REG_DMAC0_EN (0xFFFFE604U) /**< \brief (DMAC0) DMAC Enable Register */ +#define REG_DMAC0_SREQ (0xFFFFE608U) /**< \brief (DMAC0) DMAC Software Single Request Register */ +#define REG_DMAC0_CREQ (0xFFFFE60CU) /**< \brief (DMAC0) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC0_LAST (0xFFFFE610U) /**< \brief (DMAC0) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC0_EBCIER (0xFFFFE618U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC0_EBCIDR (0xFFFFE61CU) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC0_EBCIMR (0xFFFFE620U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC0_EBCISR (0xFFFFE624U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC0_CHER (0xFFFFE628U) /**< \brief (DMAC0) DMAC Channel Handler Enable Register */ +#define REG_DMAC0_CHDR (0xFFFFE62CU) /**< \brief (DMAC0) DMAC Channel Handler Disable Register */ +#define REG_DMAC0_CHSR (0xFFFFE630U) /**< \brief (DMAC0) DMAC Channel Handler Status Register */ +#define REG_DMAC0_SADDR0 (0xFFFFE63CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC0_DADDR0 (0xFFFFE640U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC0_DSCR0 (0xFFFFE644U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC0_CTRLA0 (0xFFFFE648U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC0_CTRLB0 (0xFFFFE64CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC0_CFG0 (0xFFFFE650U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SPIP0 (0xFFFFE654U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_DPIP0 (0xFFFFE658U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SADDR1 (0xFFFFE664U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC0_DADDR1 (0xFFFFE668U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC0_DSCR1 (0xFFFFE66CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC0_CTRLA1 (0xFFFFE670U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC0_CTRLB1 (0xFFFFE674U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC0_CFG1 (0xFFFFE678U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SPIP1 (0xFFFFE67CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_DPIP1 (0xFFFFE680U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SADDR2 (0xFFFFE68CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC0_DADDR2 (0xFFFFE690U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC0_DSCR2 (0xFFFFE694U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC0_CTRLA2 (0xFFFFE698U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC0_CTRLB2 (0xFFFFE69CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC0_CFG2 (0xFFFFE6A0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SPIP2 (0xFFFFE6A4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_DPIP2 (0xFFFFE6A8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SADDR3 (0xFFFFE6B4U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC0_DADDR3 (0xFFFFE6B8U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC0_DSCR3 (0xFFFFE6BCU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC0_CTRLA3 (0xFFFFE6C0U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC0_CTRLB3 (0xFFFFE6C4U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC0_CFG3 (0xFFFFE6C8U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SPIP3 (0xFFFFE6CCU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_DPIP3 (0xFFFFE6D0U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SADDR4 (0xFFFFE6DCU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC0_DADDR4 (0xFFFFE6E0U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC0_DSCR4 (0xFFFFE6E4U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC0_CTRLA4 (0xFFFFE6E8U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC0_CTRLB4 (0xFFFFE6ECU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC0_CFG4 (0xFFFFE6F0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SPIP4 (0xFFFFE6F4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_DPIP4 (0xFFFFE6F8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SADDR5 (0xFFFFE704U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC0_DADDR5 (0xFFFFE708U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC0_DSCR5 (0xFFFFE70CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC0_CTRLA5 (0xFFFFE710U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC0_CTRLB5 (0xFFFFE714U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC0_CFG5 (0xFFFFE718U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SPIP5 (0xFFFFE71CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_DPIP5 (0xFFFFE720U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SADDR6 (0xFFFFE72CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC0_DADDR6 (0xFFFFE730U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC0_DSCR6 (0xFFFFE734U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC0_CTRLA6 (0xFFFFE738U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC0_CTRLB6 (0xFFFFE73CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC0_CFG6 (0xFFFFE740U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SPIP6 (0xFFFFE744U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_DPIP6 (0xFFFFE748U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SADDR7 (0xFFFFE754U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC0_DADDR7 (0xFFFFE758U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC0_DSCR7 (0xFFFFE75CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC0_CTRLA7 (0xFFFFE760U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC0_CTRLB7 (0xFFFFE764U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC0_CFG7 (0xFFFFE768U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC0_SPIP7 (0xFFFFE76CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_DPIP7 (0xFFFFE770U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_WPMR (0xFFFFE7E4U) /**< \brief (DMAC0) DMAC Write Protect Mode Register */ +#define REG_DMAC0_WPSR (0xFFFFE7E8U) /**< \brief (DMAC0) DMAC Write Protect Status Register */ +#else +#define REG_DMAC0_GCFG (*(RwReg*)0xFFFFE600U) /**< \brief (DMAC0) DMAC Global Configuration Register */ +#define REG_DMAC0_EN (*(RwReg*)0xFFFFE604U) /**< \brief (DMAC0) DMAC Enable Register */ +#define REG_DMAC0_SREQ (*(RwReg*)0xFFFFE608U) /**< \brief (DMAC0) DMAC Software Single Request Register */ +#define REG_DMAC0_CREQ (*(RwReg*)0xFFFFE60CU) /**< \brief (DMAC0) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC0_LAST (*(RwReg*)0xFFFFE610U) /**< \brief (DMAC0) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC0_EBCIER (*(WoReg*)0xFFFFE618U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC0_EBCIDR (*(WoReg*)0xFFFFE61CU) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC0_EBCIMR (*(RoReg*)0xFFFFE620U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC0_EBCISR (*(RoReg*)0xFFFFE624U) /**< \brief (DMAC0) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC0_CHER (*(WoReg*)0xFFFFE628U) /**< \brief (DMAC0) DMAC Channel Handler Enable Register */ +#define REG_DMAC0_CHDR (*(WoReg*)0xFFFFE62CU) /**< \brief (DMAC0) DMAC Channel Handler Disable Register */ +#define REG_DMAC0_CHSR (*(RoReg*)0xFFFFE630U) /**< \brief (DMAC0) DMAC Channel Handler Status Register */ +#define REG_DMAC0_SADDR0 (*(RwReg*)0xFFFFE63CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC0_DADDR0 (*(RwReg*)0xFFFFE640U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC0_DSCR0 (*(RwReg*)0xFFFFE644U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC0_CTRLA0 (*(RwReg*)0xFFFFE648U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC0_CTRLB0 (*(RwReg*)0xFFFFE64CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC0_CFG0 (*(RwReg*)0xFFFFE650U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SPIP0 (*(RwReg*)0xFFFFE654U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_DPIP0 (*(RwReg*)0xFFFFE658U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC0_SADDR1 (*(RwReg*)0xFFFFE664U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC0_DADDR1 (*(RwReg*)0xFFFFE668U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC0_DSCR1 (*(RwReg*)0xFFFFE66CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC0_CTRLA1 (*(RwReg*)0xFFFFE670U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC0_CTRLB1 (*(RwReg*)0xFFFFE674U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC0_CFG1 (*(RwReg*)0xFFFFE678U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SPIP1 (*(RwReg*)0xFFFFE67CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_DPIP1 (*(RwReg*)0xFFFFE680U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC0_SADDR2 (*(RwReg*)0xFFFFE68CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC0_DADDR2 (*(RwReg*)0xFFFFE690U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC0_DSCR2 (*(RwReg*)0xFFFFE694U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC0_CTRLA2 (*(RwReg*)0xFFFFE698U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC0_CTRLB2 (*(RwReg*)0xFFFFE69CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC0_CFG2 (*(RwReg*)0xFFFFE6A0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SPIP2 (*(RwReg*)0xFFFFE6A4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_DPIP2 (*(RwReg*)0xFFFFE6A8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC0_SADDR3 (*(RwReg*)0xFFFFE6B4U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC0_DADDR3 (*(RwReg*)0xFFFFE6B8U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC0_DSCR3 (*(RwReg*)0xFFFFE6BCU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC0_CTRLA3 (*(RwReg*)0xFFFFE6C0U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC0_CTRLB3 (*(RwReg*)0xFFFFE6C4U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC0_CFG3 (*(RwReg*)0xFFFFE6C8U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SPIP3 (*(RwReg*)0xFFFFE6CCU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_DPIP3 (*(RwReg*)0xFFFFE6D0U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC0_SADDR4 (*(RwReg*)0xFFFFE6DCU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC0_DADDR4 (*(RwReg*)0xFFFFE6E0U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC0_DSCR4 (*(RwReg*)0xFFFFE6E4U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC0_CTRLA4 (*(RwReg*)0xFFFFE6E8U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC0_CTRLB4 (*(RwReg*)0xFFFFE6ECU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC0_CFG4 (*(RwReg*)0xFFFFE6F0U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SPIP4 (*(RwReg*)0xFFFFE6F4U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_DPIP4 (*(RwReg*)0xFFFFE6F8U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC0_SADDR5 (*(RwReg*)0xFFFFE704U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC0_DADDR5 (*(RwReg*)0xFFFFE708U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC0_DSCR5 (*(RwReg*)0xFFFFE70CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC0_CTRLA5 (*(RwReg*)0xFFFFE710U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC0_CTRLB5 (*(RwReg*)0xFFFFE714U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC0_CFG5 (*(RwReg*)0xFFFFE718U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SPIP5 (*(RwReg*)0xFFFFE71CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_DPIP5 (*(RwReg*)0xFFFFE720U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC0_SADDR6 (*(RwReg*)0xFFFFE72CU) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC0_DADDR6 (*(RwReg*)0xFFFFE730U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC0_DSCR6 (*(RwReg*)0xFFFFE734U) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC0_CTRLA6 (*(RwReg*)0xFFFFE738U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC0_CTRLB6 (*(RwReg*)0xFFFFE73CU) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC0_CFG6 (*(RwReg*)0xFFFFE740U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SPIP6 (*(RwReg*)0xFFFFE744U) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_DPIP6 (*(RwReg*)0xFFFFE748U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC0_SADDR7 (*(RwReg*)0xFFFFE754U) /**< \brief (DMAC0) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC0_DADDR7 (*(RwReg*)0xFFFFE758U) /**< \brief (DMAC0) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC0_DSCR7 (*(RwReg*)0xFFFFE75CU) /**< \brief (DMAC0) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC0_CTRLA7 (*(RwReg*)0xFFFFE760U) /**< \brief (DMAC0) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC0_CTRLB7 (*(RwReg*)0xFFFFE764U) /**< \brief (DMAC0) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC0_CFG7 (*(RwReg*)0xFFFFE768U) /**< \brief (DMAC0) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC0_SPIP7 (*(RwReg*)0xFFFFE76CU) /**< \brief (DMAC0) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_DPIP7 (*(RwReg*)0xFFFFE770U) /**< \brief (DMAC0) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC0_WPMR (*(RwReg*)0xFFFFE7E4U) /**< \brief (DMAC0) DMAC Write Protect Mode Register */ +#define REG_DMAC0_WPSR (*(RoReg*)0xFFFFE7E8U) /**< \brief (DMAC0) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_DMAC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac1.h new file mode 100644 index 000000000..881dd566e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_dmac1.h @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_DMAC1_INSTANCE_ +#define _SAMA5_DMAC1_INSTANCE_ + +/* ========== Register definition for DMAC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC1_GCFG (0xFFFFE800U) /**< \brief (DMAC1) DMAC Global Configuration Register */ +#define REG_DMAC1_EN (0xFFFFE804U) /**< \brief (DMAC1) DMAC Enable Register */ +#define REG_DMAC1_SREQ (0xFFFFE808U) /**< \brief (DMAC1) DMAC Software Single Request Register */ +#define REG_DMAC1_CREQ (0xFFFFE80CU) /**< \brief (DMAC1) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC1_LAST (0xFFFFE810U) /**< \brief (DMAC1) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC1_EBCIER (0xFFFFE818U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC1_EBCIDR (0xFFFFE81CU) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC1_EBCIMR (0xFFFFE820U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC1_EBCISR (0xFFFFE824U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC1_CHER (0xFFFFE828U) /**< \brief (DMAC1) DMAC Channel Handler Enable Register */ +#define REG_DMAC1_CHDR (0xFFFFE82CU) /**< \brief (DMAC1) DMAC Channel Handler Disable Register */ +#define REG_DMAC1_CHSR (0xFFFFE830U) /**< \brief (DMAC1) DMAC Channel Handler Status Register */ +#define REG_DMAC1_SADDR0 (0xFFFFE83CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC1_DADDR0 (0xFFFFE840U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC1_DSCR0 (0xFFFFE844U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC1_CTRLA0 (0xFFFFE848U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC1_CTRLB0 (0xFFFFE84CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC1_CFG0 (0xFFFFE850U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SPIP0 (0xFFFFE854U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_DPIP0 (0xFFFFE858U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SADDR1 (0xFFFFE864U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC1_DADDR1 (0xFFFFE868U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC1_DSCR1 (0xFFFFE86CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC1_CTRLA1 (0xFFFFE870U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC1_CTRLB1 (0xFFFFE874U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC1_CFG1 (0xFFFFE878U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SPIP1 (0xFFFFE87CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_DPIP1 (0xFFFFE880U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SADDR2 (0xFFFFE88CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC1_DADDR2 (0xFFFFE890U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC1_DSCR2 (0xFFFFE894U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC1_CTRLA2 (0xFFFFE898U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC1_CTRLB2 (0xFFFFE89CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC1_CFG2 (0xFFFFE8A0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SPIP2 (0xFFFFE8A4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_DPIP2 (0xFFFFE8A8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SADDR3 (0xFFFFE8B4U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC1_DADDR3 (0xFFFFE8B8U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC1_DSCR3 (0xFFFFE8BCU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC1_CTRLA3 (0xFFFFE8C0U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC1_CTRLB3 (0xFFFFE8C4U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC1_CFG3 (0xFFFFE8C8U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SPIP3 (0xFFFFE8CCU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_DPIP3 (0xFFFFE8D0U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SADDR4 (0xFFFFE8DCU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC1_DADDR4 (0xFFFFE8E0U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC1_DSCR4 (0xFFFFE8E4U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC1_CTRLA4 (0xFFFFE8E8U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC1_CTRLB4 (0xFFFFE8ECU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC1_CFG4 (0xFFFFE8F0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SPIP4 (0xFFFFE8F4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_DPIP4 (0xFFFFE8F8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SADDR5 (0xFFFFE904U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC1_DADDR5 (0xFFFFE908U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC1_DSCR5 (0xFFFFE90CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC1_CTRLA5 (0xFFFFE910U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC1_CTRLB5 (0xFFFFE914U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC1_CFG5 (0xFFFFE918U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SPIP5 (0xFFFFE91CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_DPIP5 (0xFFFFE920U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SADDR6 (0xFFFFE92CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC1_DADDR6 (0xFFFFE930U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC1_DSCR6 (0xFFFFE934U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC1_CTRLA6 (0xFFFFE938U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC1_CTRLB6 (0xFFFFE93CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC1_CFG6 (0xFFFFE940U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SPIP6 (0xFFFFE944U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_DPIP6 (0xFFFFE948U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SADDR7 (0xFFFFE954U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC1_DADDR7 (0xFFFFE958U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC1_DSCR7 (0xFFFFE95CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC1_CTRLA7 (0xFFFFE960U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC1_CTRLB7 (0xFFFFE964U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC1_CFG7 (0xFFFFE968U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC1_SPIP7 (0xFFFFE96CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_DPIP7 (0xFFFFE970U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_WPMR (0xFFFFE9E4U) /**< \brief (DMAC1) DMAC Write Protect Mode Register */ +#define REG_DMAC1_WPSR (0xFFFFE9E8U) /**< \brief (DMAC1) DMAC Write Protect Status Register */ +#else +#define REG_DMAC1_GCFG (*(RwReg*)0xFFFFE800U) /**< \brief (DMAC1) DMAC Global Configuration Register */ +#define REG_DMAC1_EN (*(RwReg*)0xFFFFE804U) /**< \brief (DMAC1) DMAC Enable Register */ +#define REG_DMAC1_SREQ (*(RwReg*)0xFFFFE808U) /**< \brief (DMAC1) DMAC Software Single Request Register */ +#define REG_DMAC1_CREQ (*(RwReg*)0xFFFFE80CU) /**< \brief (DMAC1) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC1_LAST (*(RwReg*)0xFFFFE810U) /**< \brief (DMAC1) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC1_EBCIER (*(WoReg*)0xFFFFE818U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC1_EBCIDR (*(WoReg*)0xFFFFE81CU) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC1_EBCIMR (*(RoReg*)0xFFFFE820U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC1_EBCISR (*(RoReg*)0xFFFFE824U) /**< \brief (DMAC1) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC1_CHER (*(WoReg*)0xFFFFE828U) /**< \brief (DMAC1) DMAC Channel Handler Enable Register */ +#define REG_DMAC1_CHDR (*(WoReg*)0xFFFFE82CU) /**< \brief (DMAC1) DMAC Channel Handler Disable Register */ +#define REG_DMAC1_CHSR (*(RoReg*)0xFFFFE830U) /**< \brief (DMAC1) DMAC Channel Handler Status Register */ +#define REG_DMAC1_SADDR0 (*(RwReg*)0xFFFFE83CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC1_DADDR0 (*(RwReg*)0xFFFFE840U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC1_DSCR0 (*(RwReg*)0xFFFFE844U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC1_CTRLA0 (*(RwReg*)0xFFFFE848U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC1_CTRLB0 (*(RwReg*)0xFFFFE84CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC1_CFG0 (*(RwReg*)0xFFFFE850U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SPIP0 (*(RwReg*)0xFFFFE854U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_DPIP0 (*(RwReg*)0xFFFFE858U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 0) */ +#define REG_DMAC1_SADDR1 (*(RwReg*)0xFFFFE864U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC1_DADDR1 (*(RwReg*)0xFFFFE868U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC1_DSCR1 (*(RwReg*)0xFFFFE86CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC1_CTRLA1 (*(RwReg*)0xFFFFE870U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC1_CTRLB1 (*(RwReg*)0xFFFFE874U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC1_CFG1 (*(RwReg*)0xFFFFE878U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SPIP1 (*(RwReg*)0xFFFFE87CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_DPIP1 (*(RwReg*)0xFFFFE880U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 1) */ +#define REG_DMAC1_SADDR2 (*(RwReg*)0xFFFFE88CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC1_DADDR2 (*(RwReg*)0xFFFFE890U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC1_DSCR2 (*(RwReg*)0xFFFFE894U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC1_CTRLA2 (*(RwReg*)0xFFFFE898U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC1_CTRLB2 (*(RwReg*)0xFFFFE89CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC1_CFG2 (*(RwReg*)0xFFFFE8A0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SPIP2 (*(RwReg*)0xFFFFE8A4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_DPIP2 (*(RwReg*)0xFFFFE8A8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 2) */ +#define REG_DMAC1_SADDR3 (*(RwReg*)0xFFFFE8B4U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC1_DADDR3 (*(RwReg*)0xFFFFE8B8U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC1_DSCR3 (*(RwReg*)0xFFFFE8BCU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC1_CTRLA3 (*(RwReg*)0xFFFFE8C0U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC1_CTRLB3 (*(RwReg*)0xFFFFE8C4U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC1_CFG3 (*(RwReg*)0xFFFFE8C8U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SPIP3 (*(RwReg*)0xFFFFE8CCU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_DPIP3 (*(RwReg*)0xFFFFE8D0U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 3) */ +#define REG_DMAC1_SADDR4 (*(RwReg*)0xFFFFE8DCU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC1_DADDR4 (*(RwReg*)0xFFFFE8E0U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC1_DSCR4 (*(RwReg*)0xFFFFE8E4U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC1_CTRLA4 (*(RwReg*)0xFFFFE8E8U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC1_CTRLB4 (*(RwReg*)0xFFFFE8ECU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC1_CFG4 (*(RwReg*)0xFFFFE8F0U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SPIP4 (*(RwReg*)0xFFFFE8F4U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_DPIP4 (*(RwReg*)0xFFFFE8F8U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 4) */ +#define REG_DMAC1_SADDR5 (*(RwReg*)0xFFFFE904U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC1_DADDR5 (*(RwReg*)0xFFFFE908U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC1_DSCR5 (*(RwReg*)0xFFFFE90CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC1_CTRLA5 (*(RwReg*)0xFFFFE910U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC1_CTRLB5 (*(RwReg*)0xFFFFE914U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC1_CFG5 (*(RwReg*)0xFFFFE918U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SPIP5 (*(RwReg*)0xFFFFE91CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_DPIP5 (*(RwReg*)0xFFFFE920U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 5) */ +#define REG_DMAC1_SADDR6 (*(RwReg*)0xFFFFE92CU) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 6) */ +#define REG_DMAC1_DADDR6 (*(RwReg*)0xFFFFE930U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 6) */ +#define REG_DMAC1_DSCR6 (*(RwReg*)0xFFFFE934U) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 6) */ +#define REG_DMAC1_CTRLA6 (*(RwReg*)0xFFFFE938U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 6) */ +#define REG_DMAC1_CTRLB6 (*(RwReg*)0xFFFFE93CU) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 6) */ +#define REG_DMAC1_CFG6 (*(RwReg*)0xFFFFE940U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SPIP6 (*(RwReg*)0xFFFFE944U) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_DPIP6 (*(RwReg*)0xFFFFE948U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 6) */ +#define REG_DMAC1_SADDR7 (*(RwReg*)0xFFFFE954U) /**< \brief (DMAC1) DMAC Channel Source Address Register (ch_num = 7) */ +#define REG_DMAC1_DADDR7 (*(RwReg*)0xFFFFE958U) /**< \brief (DMAC1) DMAC Channel Destination Address Register (ch_num = 7) */ +#define REG_DMAC1_DSCR7 (*(RwReg*)0xFFFFE95CU) /**< \brief (DMAC1) DMAC Channel Descriptor Address Register (ch_num = 7) */ +#define REG_DMAC1_CTRLA7 (*(RwReg*)0xFFFFE960U) /**< \brief (DMAC1) DMAC Channel Control A Register (ch_num = 7) */ +#define REG_DMAC1_CTRLB7 (*(RwReg*)0xFFFFE964U) /**< \brief (DMAC1) DMAC Channel Control B Register (ch_num = 7) */ +#define REG_DMAC1_CFG7 (*(RwReg*)0xFFFFE968U) /**< \brief (DMAC1) DMAC Channel Configuration Register (ch_num = 7) */ +#define REG_DMAC1_SPIP7 (*(RwReg*)0xFFFFE96CU) /**< \brief (DMAC1) DMAC Channel Source Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_DPIP7 (*(RwReg*)0xFFFFE970U) /**< \brief (DMAC1) DMAC Channel Destination Picture-in-Picture Configuration Register (ch_num = 7) */ +#define REG_DMAC1_WPMR (*(RwReg*)0xFFFFE9E4U) /**< \brief (DMAC1) DMAC Write Protect Mode Register */ +#define REG_DMAC1_WPSR (*(RoReg*)0xFFFFE9E8U) /**< \brief (DMAC1) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_DMAC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_emac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_emac.h new file mode 100644 index 000000000..7520b4a13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_emac.h @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_EMAC_INSTANCE_ +#define _SAMA5_EMAC_INSTANCE_ + +/* ========== Register definition for EMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EMAC_NCR (0xF802C000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (0xF802C004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (0xF802C008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (0xF802C014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (0xF802C018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (0xF802C01CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (0xF802C020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (0xF802C024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (0xF802C028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (0xF802C02CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (0xF802C030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (0xF802C034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (0xF802C038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (0xF802C03CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (0xF802C040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (0xF802C044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (0xF802C048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (0xF802C04CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (0xF802C050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (0xF802C054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (0xF802C058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (0xF802C05CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (0xF802C060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (0xF802C064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (0xF802C068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (0xF802C06CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (0xF802C070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (0xF802C074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (0xF802C078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (0xF802C07CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (0xF802C080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (0xF802C084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (0xF802C088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (0xF802C090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (0xF802C094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (0xF802C098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (0xF802C09CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (0xF802C0A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (0xF802C0A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (0xF802C0A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (0xF802C0ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (0xF802C0B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (0xF802C0B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (0xF802C0B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (0xF802C0C0U) /**< \brief (EMAC) User Input/Output Register */ +#define REG_EMAC_WOL (0xF802C0C4U) /**< \brief (EMAC) Wake on LAN Register */ +#else +#define REG_EMAC_NCR (*(RwReg*)0xF802C000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (*(RwReg*)0xF802C004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (*(RoReg*)0xF802C008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (*(RwReg*)0xF802C014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (*(RwReg*)0xF802C018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (*(RwReg*)0xF802C01CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (*(RwReg*)0xF802C020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (*(RwReg*)0xF802C024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (*(WoReg*)0xF802C028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (*(WoReg*)0xF802C02CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (*(RoReg*)0xF802C030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (*(RwReg*)0xF802C034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (*(RwReg*)0xF802C038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (*(RwReg*)0xF802C03CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (*(RwReg*)0xF802C040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (*(RwReg*)0xF802C044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (*(RwReg*)0xF802C048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (*(RwReg*)0xF802C04CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (*(RwReg*)0xF802C050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (*(RwReg*)0xF802C054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (*(RwReg*)0xF802C058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (*(RwReg*)0xF802C05CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (*(RwReg*)0xF802C060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (*(RwReg*)0xF802C064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (*(RwReg*)0xF802C068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (*(RwReg*)0xF802C06CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (*(RwReg*)0xF802C070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (*(RwReg*)0xF802C074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (*(RwReg*)0xF802C078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (*(RwReg*)0xF802C07CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (*(RwReg*)0xF802C080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (*(RwReg*)0xF802C084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (*(RwReg*)0xF802C088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (*(RwReg*)0xF802C090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (*(RwReg*)0xF802C094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (*(RwReg*)0xF802C098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (*(RwReg*)0xF802C09CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (*(RwReg*)0xF802C0A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (*(RwReg*)0xF802C0A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (*(RwReg*)0xF802C0A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (*(RwReg*)0xF802C0ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (*(RwReg*)0xF802C0B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (*(RwReg*)0xF802C0B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (*(RwReg*)0xF802C0B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (*(RwReg*)0xF802C0C0U) /**< \brief (EMAC) User Input/Output Register */ +#define REG_EMAC_WOL (*(RwReg*)0xF802C0C4U) /**< \brief (EMAC) Wake on LAN Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_EMAC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_fuse.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_fuse.h new file mode 100644 index 000000000..3d556eff0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_fuse.h @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_FUSE_INSTANCE_ +#define _SAMA5_FUSE_INSTANCE_ + +/* ========== Register definition for FUSE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_FUSE_CR (0xFFFFE400U) /**< \brief (FUSE) Fuse Control Register */ +#define REG_FUSE_MR (0xFFFFE404U) /**< \brief (FUSE) Fuse Mode Register */ +#define REG_FUSE_IR (0xFFFFE408U) /**< \brief (FUSE) Fuse Index Register */ +#define REG_FUSE_DR (0xFFFFE40CU) /**< \brief (FUSE) Fuse Data Register */ +#define REG_FUSE_SR (0xFFFFE410U) /**< \brief (FUSE) Fuse Status Register */ +#else +#define REG_FUSE_CR (*(WoReg*)0xFFFFE400U) /**< \brief (FUSE) Fuse Control Register */ +#define REG_FUSE_MR (*(WoReg*)0xFFFFE404U) /**< \brief (FUSE) Fuse Mode Register */ +#define REG_FUSE_IR (*(RwReg*)0xFFFFE408U) /**< \brief (FUSE) Fuse Index Register */ +#define REG_FUSE_DR (*(RwReg*)0xFFFFE40CU) /**< \brief (FUSE) Fuse Data Register */ +#define REG_FUSE_SR (*(RoReg*)0xFFFFE410U) /**< \brief (FUSE) Fuse Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_FUSE_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gmac.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gmac.h new file mode 100644 index 000000000..77852b1d2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gmac.h @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_GMAC_INSTANCE_ +#define _SAMA5_GMAC_INSTANCE_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GMAC_NCR (0xF0028000U) /**< \brief (GMAC) Network Control Register */ +#define REG_GMAC_NCFGR (0xF0028004U) /**< \brief (GMAC) Network Configuration Register */ +#define REG_GMAC_NSR (0xF0028008U) /**< \brief (GMAC) Network Status Register */ +#define REG_GMAC_UR (0xF002800CU) /**< \brief (GMAC) User Register */ +#define REG_GMAC_DCFGR (0xF0028010U) /**< \brief (GMAC) DMA Configuration Register */ +#define REG_GMAC_TSR (0xF0028014U) /**< \brief (GMAC) Transmit Status Register */ +#define REG_GMAC_RBQB (0xF0028018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */ +#define REG_GMAC_TBQB (0xF002801CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */ +#define REG_GMAC_RSR (0xF0028020U) /**< \brief (GMAC) Receive Status Register */ +#define REG_GMAC_ISR (0xF0028024U) /**< \brief (GMAC) Interrupt Status Register */ +#define REG_GMAC_IER (0xF0028028U) /**< \brief (GMAC) Interrupt Enable Register */ +#define REG_GMAC_IDR (0xF002802CU) /**< \brief (GMAC) Interrupt Disable Register */ +#define REG_GMAC_IMR (0xF0028030U) /**< \brief (GMAC) Interrupt Mask Register */ +#define REG_GMAC_MAN (0xF0028034U) /**< \brief (GMAC) PHY Maintenance Register */ +#define REG_GMAC_RPQ (0xF0028038U) /**< \brief (GMAC) Received Pause Quantum Register */ +#define REG_GMAC_TPQ (0xF002803CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ +#define REG_GMAC_TPSF (0xF0028040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ +#define REG_GMAC_RPSF (0xF0028044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ +#define REG_GMAC_HRB (0xF0028080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */ +#define REG_GMAC_HRT (0xF0028084U) /**< \brief (GMAC) Hash Register Top [63:32] */ +#define REG_GMAC_SAB1 (0xF0028088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */ +#define REG_GMAC_SAT1 (0xF002808CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */ +#define REG_GMAC_SAB2 (0xF0028090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */ +#define REG_GMAC_SAT2 (0xF0028094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */ +#define REG_GMAC_SAB3 (0xF0028098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */ +#define REG_GMAC_SAT3 (0xF002809CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */ +#define REG_GMAC_SAB4 (0xF00280A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */ +#define REG_GMAC_SAT4 (0xF00280A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */ +#define REG_GMAC_TIDM (0xF00280A8U) /**< \brief (GMAC) Type ID Match 1 Register */ +#define REG_GMAC_WOL (0xF00280B8U) /**< \brief (GMAC) Wake on LAN Register */ +#define REG_GMAC_IPGS (0xF00280BCU) /**< \brief (GMAC) IPG Stretch Register */ +#define REG_GMAC_SVLAN (0xF00280C0U) /**< \brief (GMAC) Stacked VLAN Register */ +#define REG_GMAC_TPFCP (0xF00280C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ +#define REG_GMAC_SAMB1 (0xF00280C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */ +#define REG_GMAC_SAMT1 (0xF00280CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */ +#define REG_GMAC_OTLO (0xF0028100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */ +#define REG_GMAC_OTHI (0xF0028104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */ +#define REG_GMAC_FT (0xF0028108U) /**< \brief (GMAC) Frames Transmitted Register */ +#define REG_GMAC_BCFT (0xF002810CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ +#define REG_GMAC_MFT (0xF0028110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ +#define REG_GMAC_PFT (0xF0028114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ +#define REG_GMAC_BFT64 (0xF0028118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT127 (0xF002811CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT255 (0xF0028120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT511 (0xF0028124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1023 (0xF0028128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1518 (0xF002812CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_GTBFT1518 (0xF0028130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_TUR (0xF0028134U) /**< \brief (GMAC) Transmit Under Runs Register */ +#define REG_GMAC_SCF (0xF0028138U) /**< \brief (GMAC) Single Collision Frames Register */ +#define REG_GMAC_MCF (0xF002813CU) /**< \brief (GMAC) Multiple Collision Frames Register */ +#define REG_GMAC_EC (0xF0028140U) /**< \brief (GMAC) Excessive Collisions Register */ +#define REG_GMAC_LC (0xF0028144U) /**< \brief (GMAC) Late Collisions Register */ +#define REG_GMAC_DTF (0xF0028148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ +#define REG_GMAC_CSE (0xF002814CU) /**< \brief (GMAC) Carrier Sense Errors Register */ +#define REG_GMAC_ORLO (0xF0028150U) /**< \brief (GMAC) Octets Received [31:0] Received */ +#define REG_GMAC_ORHI (0xF0028154U) /**< \brief (GMAC) Octets Received [47:32] Received */ +#define REG_GMAC_FR (0xF0028158U) /**< \brief (GMAC) Frames Received Register */ +#define REG_GMAC_BCFR (0xF002815CU) /**< \brief (GMAC) Broadcast Frames Received Register */ +#define REG_GMAC_MFR (0xF0028160U) /**< \brief (GMAC) Multicast Frames Received Register */ +#define REG_GMAC_PFR (0xF0028164U) /**< \brief (GMAC) Pause Frames Received Register */ +#define REG_GMAC_BFR64 (0xF0028168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ +#define REG_GMAC_TBFR127 (0xF002816CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ +#define REG_GMAC_TBFR255 (0xF0028170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ +#define REG_GMAC_TBFR511 (0xF0028174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */ +#define REG_GMAC_TBFR1023 (0xF0028178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ +#define REG_GMAC_TBFR1518 (0xF002817CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ +#define REG_GMAC_TMXBFR (0xF0028180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ +#define REG_GMAC_UFR (0xF0028184U) /**< \brief (GMAC) Undersize Frames Received Register */ +#define REG_GMAC_OFR (0xF0028188U) /**< \brief (GMAC) Oversize Frames Received Register */ +#define REG_GMAC_JR (0xF002818CU) /**< \brief (GMAC) Jabbers Received Register */ +#define REG_GMAC_FCSE (0xF0028190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ +#define REG_GMAC_LFFE (0xF0028194U) /**< \brief (GMAC) Length Field Frame Errors Register */ +#define REG_GMAC_RSE (0xF0028198U) /**< \brief (GMAC) Receive Symbol Errors Register */ +#define REG_GMAC_AE (0xF002819CU) /**< \brief (GMAC) Alignment Errors Register */ +#define REG_GMAC_RRE (0xF00281A0U) /**< \brief (GMAC) Receive Resource Errors Register */ +#define REG_GMAC_ROE (0xF00281A4U) /**< \brief (GMAC) Receive Overrun Register */ +#define REG_GMAC_IHCE (0xF00281A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ +#define REG_GMAC_TCE (0xF00281ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ +#define REG_GMAC_UCE (0xF00281B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ +#define REG_GMAC_TSSS (0xF00281C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */ +#define REG_GMAC_TSSN (0xF00281CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */ +#define REG_GMAC_TS (0xF00281D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */ +#define REG_GMAC_TN (0xF00281D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ +#define REG_GMAC_TA (0xF00281D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ +#define REG_GMAC_TI (0xF00281DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ +#define REG_GMAC_EFTS (0xF00281E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */ +#define REG_GMAC_EFTN (0xF00281E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_EFRS (0xF00281E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */ +#define REG_GMAC_EFRN (0xF00281ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */ +#define REG_GMAC_PEFTS (0xF00281F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */ +#define REG_GMAC_PEFTN (0xF00281F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_PEFRS (0xF00281F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */ +#define REG_GMAC_PEFRN (0xF00281FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */ +#define REG_GMAC_ISRPQ (0xF0028400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */ +#define REG_GMAC_TBQBAPQ (0xF0028440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBQBAPQ (0xF0028480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBSRPQ (0xF00284A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */ +#define REG_GMAC_ST1RPQ (0xF0028500U) /**< \brief (GMAC) Screening Type1 Register Priority Queue */ +#define REG_GMAC_ST2RPQ (0xF0028540U) /**< \brief (GMAC) Screening Type2 Register Priority Queue */ +#define REG_GMAC_IERPQ (0xF0028600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */ +#define REG_GMAC_IDRPQ (0xF0028620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */ +#define REG_GMAC_IMRPQ (0xF0028640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */ +#else +#define REG_GMAC_NCR (*(RwReg*)0xF0028000U) /**< \brief (GMAC) Network Control Register */ +#define REG_GMAC_NCFGR (*(RwReg*)0xF0028004U) /**< \brief (GMAC) Network Configuration Register */ +#define REG_GMAC_NSR (*(RoReg*)0xF0028008U) /**< \brief (GMAC) Network Status Register */ +#define REG_GMAC_UR (*(RwReg*)0xF002800CU) /**< \brief (GMAC) User Register */ +#define REG_GMAC_DCFGR (*(RwReg*)0xF0028010U) /**< \brief (GMAC) DMA Configuration Register */ +#define REG_GMAC_TSR (*(RwReg*)0xF0028014U) /**< \brief (GMAC) Transmit Status Register */ +#define REG_GMAC_RBQB (*(RwReg*)0xF0028018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */ +#define REG_GMAC_TBQB (*(RwReg*)0xF002801CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */ +#define REG_GMAC_RSR (*(RwReg*)0xF0028020U) /**< \brief (GMAC) Receive Status Register */ +#define REG_GMAC_ISR (*(RoReg*)0xF0028024U) /**< \brief (GMAC) Interrupt Status Register */ +#define REG_GMAC_IER (*(WoReg*)0xF0028028U) /**< \brief (GMAC) Interrupt Enable Register */ +#define REG_GMAC_IDR (*(WoReg*)0xF002802CU) /**< \brief (GMAC) Interrupt Disable Register */ +#define REG_GMAC_IMR (*(RoReg*)0xF0028030U) /**< \brief (GMAC) Interrupt Mask Register */ +#define REG_GMAC_MAN (*(RwReg*)0xF0028034U) /**< \brief (GMAC) PHY Maintenance Register */ +#define REG_GMAC_RPQ (*(RoReg*)0xF0028038U) /**< \brief (GMAC) Received Pause Quantum Register */ +#define REG_GMAC_TPQ (*(RwReg*)0xF002803CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ +#define REG_GMAC_TPSF (*(RwReg*)0xF0028040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ +#define REG_GMAC_RPSF (*(RwReg*)0xF0028044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ +#define REG_GMAC_HRB (*(RwReg*)0xF0028080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */ +#define REG_GMAC_HRT (*(RwReg*)0xF0028084U) /**< \brief (GMAC) Hash Register Top [63:32] */ +#define REG_GMAC_SAB1 (*(RwReg*)0xF0028088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */ +#define REG_GMAC_SAT1 (*(RwReg*)0xF002808CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */ +#define REG_GMAC_SAB2 (*(RwReg*)0xF0028090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */ +#define REG_GMAC_SAT2 (*(RwReg*)0xF0028094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */ +#define REG_GMAC_SAB3 (*(RwReg*)0xF0028098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */ +#define REG_GMAC_SAT3 (*(RwReg*)0xF002809CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */ +#define REG_GMAC_SAB4 (*(RwReg*)0xF00280A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */ +#define REG_GMAC_SAT4 (*(RwReg*)0xF00280A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */ +#define REG_GMAC_TIDM (*(RwReg*)0xF00280A8U) /**< \brief (GMAC) Type ID Match 1 Register */ +#define REG_GMAC_WOL (*(RwReg*)0xF00280B8U) /**< \brief (GMAC) Wake on LAN Register */ +#define REG_GMAC_IPGS (*(RwReg*)0xF00280BCU) /**< \brief (GMAC) IPG Stretch Register */ +#define REG_GMAC_SVLAN (*(RwReg*)0xF00280C0U) /**< \brief (GMAC) Stacked VLAN Register */ +#define REG_GMAC_TPFCP (*(RwReg*)0xF00280C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ +#define REG_GMAC_SAMB1 (*(RwReg*)0xF00280C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */ +#define REG_GMAC_SAMT1 (*(RwReg*)0xF00280CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */ +#define REG_GMAC_OTLO (*(RoReg*)0xF0028100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */ +#define REG_GMAC_OTHI (*(RoReg*)0xF0028104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */ +#define REG_GMAC_FT (*(RoReg*)0xF0028108U) /**< \brief (GMAC) Frames Transmitted Register */ +#define REG_GMAC_BCFT (*(RoReg*)0xF002810CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ +#define REG_GMAC_MFT (*(RoReg*)0xF0028110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ +#define REG_GMAC_PFT (*(RoReg*)0xF0028114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ +#define REG_GMAC_BFT64 (*(RoReg*)0xF0028118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT127 (*(RoReg*)0xF002811CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT255 (*(RoReg*)0xF0028120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT511 (*(RoReg*)0xF0028124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1023 (*(RoReg*)0xF0028128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ +#define REG_GMAC_TBFT1518 (*(RoReg*)0xF002812CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_GTBFT1518 (*(RoReg*)0xF0028130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ +#define REG_GMAC_TUR (*(RoReg*)0xF0028134U) /**< \brief (GMAC) Transmit Under Runs Register */ +#define REG_GMAC_SCF (*(RoReg*)0xF0028138U) /**< \brief (GMAC) Single Collision Frames Register */ +#define REG_GMAC_MCF (*(RoReg*)0xF002813CU) /**< \brief (GMAC) Multiple Collision Frames Register */ +#define REG_GMAC_EC (*(RoReg*)0xF0028140U) /**< \brief (GMAC) Excessive Collisions Register */ +#define REG_GMAC_LC (*(RoReg*)0xF0028144U) /**< \brief (GMAC) Late Collisions Register */ +#define REG_GMAC_DTF (*(RoReg*)0xF0028148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ +#define REG_GMAC_CSE (*(RoReg*)0xF002814CU) /**< \brief (GMAC) Carrier Sense Errors Register */ +#define REG_GMAC_ORLO (*(RoReg*)0xF0028150U) /**< \brief (GMAC) Octets Received [31:0] Received */ +#define REG_GMAC_ORHI (*(RoReg*)0xF0028154U) /**< \brief (GMAC) Octets Received [47:32] Received */ +#define REG_GMAC_FR (*(RoReg*)0xF0028158U) /**< \brief (GMAC) Frames Received Register */ +#define REG_GMAC_BCFR (*(RoReg*)0xF002815CU) /**< \brief (GMAC) Broadcast Frames Received Register */ +#define REG_GMAC_MFR (*(RoReg*)0xF0028160U) /**< \brief (GMAC) Multicast Frames Received Register */ +#define REG_GMAC_PFR (*(RoReg*)0xF0028164U) /**< \brief (GMAC) Pause Frames Received Register */ +#define REG_GMAC_BFR64 (*(RoReg*)0xF0028168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ +#define REG_GMAC_TBFR127 (*(RoReg*)0xF002816CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ +#define REG_GMAC_TBFR255 (*(RoReg*)0xF0028170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ +#define REG_GMAC_TBFR511 (*(RoReg*)0xF0028174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */ +#define REG_GMAC_TBFR1023 (*(RoReg*)0xF0028178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ +#define REG_GMAC_TBFR1518 (*(RoReg*)0xF002817CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ +#define REG_GMAC_TMXBFR (*(RoReg*)0xF0028180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ +#define REG_GMAC_UFR (*(RoReg*)0xF0028184U) /**< \brief (GMAC) Undersize Frames Received Register */ +#define REG_GMAC_OFR (*(RoReg*)0xF0028188U) /**< \brief (GMAC) Oversize Frames Received Register */ +#define REG_GMAC_JR (*(RoReg*)0xF002818CU) /**< \brief (GMAC) Jabbers Received Register */ +#define REG_GMAC_FCSE (*(RoReg*)0xF0028190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ +#define REG_GMAC_LFFE (*(RoReg*)0xF0028194U) /**< \brief (GMAC) Length Field Frame Errors Register */ +#define REG_GMAC_RSE (*(RoReg*)0xF0028198U) /**< \brief (GMAC) Receive Symbol Errors Register */ +#define REG_GMAC_AE (*(RoReg*)0xF002819CU) /**< \brief (GMAC) Alignment Errors Register */ +#define REG_GMAC_RRE (*(RoReg*)0xF00281A0U) /**< \brief (GMAC) Receive Resource Errors Register */ +#define REG_GMAC_ROE (*(RoReg*)0xF00281A4U) /**< \brief (GMAC) Receive Overrun Register */ +#define REG_GMAC_IHCE (*(RoReg*)0xF00281A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ +#define REG_GMAC_TCE (*(RoReg*)0xF00281ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ +#define REG_GMAC_UCE (*(RoReg*)0xF00281B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ +#define REG_GMAC_TSSS (*(RwReg*)0xF00281C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */ +#define REG_GMAC_TSSN (*(RwReg*)0xF00281CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */ +#define REG_GMAC_TS (*(RwReg*)0xF00281D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */ +#define REG_GMAC_TN (*(RwReg*)0xF00281D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ +#define REG_GMAC_TA (*(WoReg*)0xF00281D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ +#define REG_GMAC_TI (*(RwReg*)0xF00281DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ +#define REG_GMAC_EFTS (*(RoReg*)0xF00281E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */ +#define REG_GMAC_EFTN (*(RoReg*)0xF00281E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_EFRS (*(RoReg*)0xF00281E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */ +#define REG_GMAC_EFRN (*(RoReg*)0xF00281ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */ +#define REG_GMAC_PEFTS (*(RoReg*)0xF00281F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */ +#define REG_GMAC_PEFTN (*(RoReg*)0xF00281F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */ +#define REG_GMAC_PEFRS (*(RoReg*)0xF00281F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */ +#define REG_GMAC_PEFRN (*(RoReg*)0xF00281FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */ +#define REG_GMAC_ISRPQ (*(RoReg*)0xF0028400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue */ +#define REG_GMAC_TBQBAPQ (*(RwReg*)0xF0028440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBQBAPQ (*(RwReg*)0xF0028480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Priority Queue */ +#define REG_GMAC_RBSRPQ (*(RwReg*)0xF00284A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue */ +#define REG_GMAC_ST1RPQ (*(RwReg*)0xF0028500U) /**< \brief (GMAC) Screening Type1 Register Priority Queue */ +#define REG_GMAC_ST2RPQ (*(RwReg*)0xF0028540U) /**< \brief (GMAC) Screening Type2 Register Priority Queue */ +#define REG_GMAC_IERPQ (*(WoReg*)0xF0028600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue */ +#define REG_GMAC_IDRPQ (*(WoReg*)0xF0028620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue */ +#define REG_GMAC_IMRPQ (*(RwReg*)0xF0028640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_GMAC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gpbr.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gpbr.h new file mode 100644 index 000000000..7ca1237f5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_gpbr.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_GPBR_INSTANCE_ +#define _SAMA5_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GPBR_GPBR (0xFFFFFE60U) /**< \brief (GPBR) General Purpose Backup Register */ +#else +#define REG_GPBR_GPBR (*(RwReg*)0xFFFFFE60U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_GPBR_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci0.h new file mode 100644 index 000000000..ac66fadac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci0.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI0_INSTANCE_ +#define _SAMA5_HSMCI0_INSTANCE_ + +/* ========== Register definition for HSMCI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI0_CR (0xF0000000U) /**< \brief (HSMCI0) Control Register */ +#define REG_HSMCI0_MR (0xF0000004U) /**< \brief (HSMCI0) Mode Register */ +#define REG_HSMCI0_DTOR (0xF0000008U) /**< \brief (HSMCI0) Data Timeout Register */ +#define REG_HSMCI0_SDCR (0xF000000CU) /**< \brief (HSMCI0) SD/SDIO Card Register */ +#define REG_HSMCI0_ARGR (0xF0000010U) /**< \brief (HSMCI0) Argument Register */ +#define REG_HSMCI0_CMDR (0xF0000014U) /**< \brief (HSMCI0) Command Register */ +#define REG_HSMCI0_BLKR (0xF0000018U) /**< \brief (HSMCI0) Block Register */ +#define REG_HSMCI0_CSTOR (0xF000001CU) /**< \brief (HSMCI0) Completion Signal Timeout Register */ +#define REG_HSMCI0_RSPR (0xF0000020U) /**< \brief (HSMCI0) Response Register */ +#define REG_HSMCI0_RDR (0xF0000030U) /**< \brief (HSMCI0) Receive Data Register */ +#define REG_HSMCI0_TDR (0xF0000034U) /**< \brief (HSMCI0) Transmit Data Register */ +#define REG_HSMCI0_SR (0xF0000040U) /**< \brief (HSMCI0) Status Register */ +#define REG_HSMCI0_IER (0xF0000044U) /**< \brief (HSMCI0) Interrupt Enable Register */ +#define REG_HSMCI0_IDR (0xF0000048U) /**< \brief (HSMCI0) Interrupt Disable Register */ +#define REG_HSMCI0_IMR (0xF000004CU) /**< \brief (HSMCI0) Interrupt Mask Register */ +#define REG_HSMCI0_DMA (0xF0000050U) /**< \brief (HSMCI0) DMA Configuration Register */ +#define REG_HSMCI0_CFG (0xF0000054U) /**< \brief (HSMCI0) Configuration Register */ +#define REG_HSMCI0_WPMR (0xF00000E4U) /**< \brief (HSMCI0) Write Protection Mode Register */ +#define REG_HSMCI0_WPSR (0xF00000E8U) /**< \brief (HSMCI0) Write Protection Status Register */ +#define REG_HSMCI0_FIFO (0xF0000200U) /**< \brief (HSMCI0) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI0_CR (*(WoReg*)0xF0000000U) /**< \brief (HSMCI0) Control Register */ +#define REG_HSMCI0_MR (*(RwReg*)0xF0000004U) /**< \brief (HSMCI0) Mode Register */ +#define REG_HSMCI0_DTOR (*(RwReg*)0xF0000008U) /**< \brief (HSMCI0) Data Timeout Register */ +#define REG_HSMCI0_SDCR (*(RwReg*)0xF000000CU) /**< \brief (HSMCI0) SD/SDIO Card Register */ +#define REG_HSMCI0_ARGR (*(RwReg*)0xF0000010U) /**< \brief (HSMCI0) Argument Register */ +#define REG_HSMCI0_CMDR (*(WoReg*)0xF0000014U) /**< \brief (HSMCI0) Command Register */ +#define REG_HSMCI0_BLKR (*(RwReg*)0xF0000018U) /**< \brief (HSMCI0) Block Register */ +#define REG_HSMCI0_CSTOR (*(RwReg*)0xF000001CU) /**< \brief (HSMCI0) Completion Signal Timeout Register */ +#define REG_HSMCI0_RSPR (*(RoReg*)0xF0000020U) /**< \brief (HSMCI0) Response Register */ +#define REG_HSMCI0_RDR (*(RoReg*)0xF0000030U) /**< \brief (HSMCI0) Receive Data Register */ +#define REG_HSMCI0_TDR (*(WoReg*)0xF0000034U) /**< \brief (HSMCI0) Transmit Data Register */ +#define REG_HSMCI0_SR (*(RoReg*)0xF0000040U) /**< \brief (HSMCI0) Status Register */ +#define REG_HSMCI0_IER (*(WoReg*)0xF0000044U) /**< \brief (HSMCI0) Interrupt Enable Register */ +#define REG_HSMCI0_IDR (*(WoReg*)0xF0000048U) /**< \brief (HSMCI0) Interrupt Disable Register */ +#define REG_HSMCI0_IMR (*(RoReg*)0xF000004CU) /**< \brief (HSMCI0) Interrupt Mask Register */ +#define REG_HSMCI0_DMA (*(RwReg*)0xF0000050U) /**< \brief (HSMCI0) DMA Configuration Register */ +#define REG_HSMCI0_CFG (*(RwReg*)0xF0000054U) /**< \brief (HSMCI0) Configuration Register */ +#define REG_HSMCI0_WPMR (*(RwReg*)0xF00000E4U) /**< \brief (HSMCI0) Write Protection Mode Register */ +#define REG_HSMCI0_WPSR (*(RoReg*)0xF00000E8U) /**< \brief (HSMCI0) Write Protection Status Register */ +#define REG_HSMCI0_FIFO (*(RwReg*)0xF0000200U) /**< \brief (HSMCI0) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_HSMCI0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci1.h new file mode 100644 index 000000000..133832d3b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci1.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI1_INSTANCE_ +#define _SAMA5_HSMCI1_INSTANCE_ + +/* ========== Register definition for HSMCI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI1_CR (0xF8000000U) /**< \brief (HSMCI1) Control Register */ +#define REG_HSMCI1_MR (0xF8000004U) /**< \brief (HSMCI1) Mode Register */ +#define REG_HSMCI1_DTOR (0xF8000008U) /**< \brief (HSMCI1) Data Timeout Register */ +#define REG_HSMCI1_SDCR (0xF800000CU) /**< \brief (HSMCI1) SD/SDIO Card Register */ +#define REG_HSMCI1_ARGR (0xF8000010U) /**< \brief (HSMCI1) Argument Register */ +#define REG_HSMCI1_CMDR (0xF8000014U) /**< \brief (HSMCI1) Command Register */ +#define REG_HSMCI1_BLKR (0xF8000018U) /**< \brief (HSMCI1) Block Register */ +#define REG_HSMCI1_CSTOR (0xF800001CU) /**< \brief (HSMCI1) Completion Signal Timeout Register */ +#define REG_HSMCI1_RSPR (0xF8000020U) /**< \brief (HSMCI1) Response Register */ +#define REG_HSMCI1_RDR (0xF8000030U) /**< \brief (HSMCI1) Receive Data Register */ +#define REG_HSMCI1_TDR (0xF8000034U) /**< \brief (HSMCI1) Transmit Data Register */ +#define REG_HSMCI1_SR (0xF8000040U) /**< \brief (HSMCI1) Status Register */ +#define REG_HSMCI1_IER (0xF8000044U) /**< \brief (HSMCI1) Interrupt Enable Register */ +#define REG_HSMCI1_IDR (0xF8000048U) /**< \brief (HSMCI1) Interrupt Disable Register */ +#define REG_HSMCI1_IMR (0xF800004CU) /**< \brief (HSMCI1) Interrupt Mask Register */ +#define REG_HSMCI1_DMA (0xF8000050U) /**< \brief (HSMCI1) DMA Configuration Register */ +#define REG_HSMCI1_CFG (0xF8000054U) /**< \brief (HSMCI1) Configuration Register */ +#define REG_HSMCI1_WPMR (0xF80000E4U) /**< \brief (HSMCI1) Write Protection Mode Register */ +#define REG_HSMCI1_WPSR (0xF80000E8U) /**< \brief (HSMCI1) Write Protection Status Register */ +#define REG_HSMCI1_FIFO (0xF8000200U) /**< \brief (HSMCI1) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI1_CR (*(WoReg*)0xF8000000U) /**< \brief (HSMCI1) Control Register */ +#define REG_HSMCI1_MR (*(RwReg*)0xF8000004U) /**< \brief (HSMCI1) Mode Register */ +#define REG_HSMCI1_DTOR (*(RwReg*)0xF8000008U) /**< \brief (HSMCI1) Data Timeout Register */ +#define REG_HSMCI1_SDCR (*(RwReg*)0xF800000CU) /**< \brief (HSMCI1) SD/SDIO Card Register */ +#define REG_HSMCI1_ARGR (*(RwReg*)0xF8000010U) /**< \brief (HSMCI1) Argument Register */ +#define REG_HSMCI1_CMDR (*(WoReg*)0xF8000014U) /**< \brief (HSMCI1) Command Register */ +#define REG_HSMCI1_BLKR (*(RwReg*)0xF8000018U) /**< \brief (HSMCI1) Block Register */ +#define REG_HSMCI1_CSTOR (*(RwReg*)0xF800001CU) /**< \brief (HSMCI1) Completion Signal Timeout Register */ +#define REG_HSMCI1_RSPR (*(RoReg*)0xF8000020U) /**< \brief (HSMCI1) Response Register */ +#define REG_HSMCI1_RDR (*(RoReg*)0xF8000030U) /**< \brief (HSMCI1) Receive Data Register */ +#define REG_HSMCI1_TDR (*(WoReg*)0xF8000034U) /**< \brief (HSMCI1) Transmit Data Register */ +#define REG_HSMCI1_SR (*(RoReg*)0xF8000040U) /**< \brief (HSMCI1) Status Register */ +#define REG_HSMCI1_IER (*(WoReg*)0xF8000044U) /**< \brief (HSMCI1) Interrupt Enable Register */ +#define REG_HSMCI1_IDR (*(WoReg*)0xF8000048U) /**< \brief (HSMCI1) Interrupt Disable Register */ +#define REG_HSMCI1_IMR (*(RoReg*)0xF800004CU) /**< \brief (HSMCI1) Interrupt Mask Register */ +#define REG_HSMCI1_DMA (*(RwReg*)0xF8000050U) /**< \brief (HSMCI1) DMA Configuration Register */ +#define REG_HSMCI1_CFG (*(RwReg*)0xF8000054U) /**< \brief (HSMCI1) Configuration Register */ +#define REG_HSMCI1_WPMR (*(RwReg*)0xF80000E4U) /**< \brief (HSMCI1) Write Protection Mode Register */ +#define REG_HSMCI1_WPSR (*(RoReg*)0xF80000E8U) /**< \brief (HSMCI1) Write Protection Status Register */ +#define REG_HSMCI1_FIFO (*(RwReg*)0xF8000200U) /**< \brief (HSMCI1) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_HSMCI1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci2.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci2.h new file mode 100644 index 000000000..0e9d95752 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_hsmci2.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_HSMCI2_INSTANCE_ +#define _SAMA5_HSMCI2_INSTANCE_ + +/* ========== Register definition for HSMCI2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI2_CR (0xF8004000U) /**< \brief (HSMCI2) Control Register */ +#define REG_HSMCI2_MR (0xF8004004U) /**< \brief (HSMCI2) Mode Register */ +#define REG_HSMCI2_DTOR (0xF8004008U) /**< \brief (HSMCI2) Data Timeout Register */ +#define REG_HSMCI2_SDCR (0xF800400CU) /**< \brief (HSMCI2) SD/SDIO Card Register */ +#define REG_HSMCI2_ARGR (0xF8004010U) /**< \brief (HSMCI2) Argument Register */ +#define REG_HSMCI2_CMDR (0xF8004014U) /**< \brief (HSMCI2) Command Register */ +#define REG_HSMCI2_BLKR (0xF8004018U) /**< \brief (HSMCI2) Block Register */ +#define REG_HSMCI2_CSTOR (0xF800401CU) /**< \brief (HSMCI2) Completion Signal Timeout Register */ +#define REG_HSMCI2_RSPR (0xF8004020U) /**< \brief (HSMCI2) Response Register */ +#define REG_HSMCI2_RDR (0xF8004030U) /**< \brief (HSMCI2) Receive Data Register */ +#define REG_HSMCI2_TDR (0xF8004034U) /**< \brief (HSMCI2) Transmit Data Register */ +#define REG_HSMCI2_SR (0xF8004040U) /**< \brief (HSMCI2) Status Register */ +#define REG_HSMCI2_IER (0xF8004044U) /**< \brief (HSMCI2) Interrupt Enable Register */ +#define REG_HSMCI2_IDR (0xF8004048U) /**< \brief (HSMCI2) Interrupt Disable Register */ +#define REG_HSMCI2_IMR (0xF800404CU) /**< \brief (HSMCI2) Interrupt Mask Register */ +#define REG_HSMCI2_DMA (0xF8004050U) /**< \brief (HSMCI2) DMA Configuration Register */ +#define REG_HSMCI2_CFG (0xF8004054U) /**< \brief (HSMCI2) Configuration Register */ +#define REG_HSMCI2_WPMR (0xF80040E4U) /**< \brief (HSMCI2) Write Protection Mode Register */ +#define REG_HSMCI2_WPSR (0xF80040E8U) /**< \brief (HSMCI2) Write Protection Status Register */ +#define REG_HSMCI2_FIFO (0xF8004200U) /**< \brief (HSMCI2) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI2_CR (*(WoReg*)0xF8004000U) /**< \brief (HSMCI2) Control Register */ +#define REG_HSMCI2_MR (*(RwReg*)0xF8004004U) /**< \brief (HSMCI2) Mode Register */ +#define REG_HSMCI2_DTOR (*(RwReg*)0xF8004008U) /**< \brief (HSMCI2) Data Timeout Register */ +#define REG_HSMCI2_SDCR (*(RwReg*)0xF800400CU) /**< \brief (HSMCI2) SD/SDIO Card Register */ +#define REG_HSMCI2_ARGR (*(RwReg*)0xF8004010U) /**< \brief (HSMCI2) Argument Register */ +#define REG_HSMCI2_CMDR (*(WoReg*)0xF8004014U) /**< \brief (HSMCI2) Command Register */ +#define REG_HSMCI2_BLKR (*(RwReg*)0xF8004018U) /**< \brief (HSMCI2) Block Register */ +#define REG_HSMCI2_CSTOR (*(RwReg*)0xF800401CU) /**< \brief (HSMCI2) Completion Signal Timeout Register */ +#define REG_HSMCI2_RSPR (*(RoReg*)0xF8004020U) /**< \brief (HSMCI2) Response Register */ +#define REG_HSMCI2_RDR (*(RoReg*)0xF8004030U) /**< \brief (HSMCI2) Receive Data Register */ +#define REG_HSMCI2_TDR (*(WoReg*)0xF8004034U) /**< \brief (HSMCI2) Transmit Data Register */ +#define REG_HSMCI2_SR (*(RoReg*)0xF8004040U) /**< \brief (HSMCI2) Status Register */ +#define REG_HSMCI2_IER (*(WoReg*)0xF8004044U) /**< \brief (HSMCI2) Interrupt Enable Register */ +#define REG_HSMCI2_IDR (*(WoReg*)0xF8004048U) /**< \brief (HSMCI2) Interrupt Disable Register */ +#define REG_HSMCI2_IMR (*(RoReg*)0xF800404CU) /**< \brief (HSMCI2) Interrupt Mask Register */ +#define REG_HSMCI2_DMA (*(RwReg*)0xF8004050U) /**< \brief (HSMCI2) DMA Configuration Register */ +#define REG_HSMCI2_CFG (*(RwReg*)0xF8004054U) /**< \brief (HSMCI2) Configuration Register */ +#define REG_HSMCI2_WPMR (*(RwReg*)0xF80040E4U) /**< \brief (HSMCI2) Write Protection Mode Register */ +#define REG_HSMCI2_WPSR (*(RoReg*)0xF80040E8U) /**< \brief (HSMCI2) Write Protection Status Register */ +#define REG_HSMCI2_FIFO (*(RwReg*)0xF8004200U) /**< \brief (HSMCI2) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_HSMCI2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_isi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_isi.h new file mode 100644 index 000000000..14c6671b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_isi.h @@ -0,0 +1,88 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_ISI_INSTANCE_ +#define _SAMA5_ISI_INSTANCE_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ISI_CFG1 (0xF0034000U) /**< \brief (ISI) ISI Configuration 1 Register */ +#define REG_ISI_CFG2 (0xF0034004U) /**< \brief (ISI) ISI Configuration 2 Register */ +#define REG_ISI_PSIZE (0xF0034008U) /**< \brief (ISI) ISI Preview Size Register */ +#define REG_ISI_PDECF (0xF003400CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ +#define REG_ISI_Y2R_SET0 (0xF0034010U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 0 Register */ +#define REG_ISI_Y2R_SET1 (0xF0034014U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 1 Register */ +#define REG_ISI_R2Y_SET0 (0xF0034018U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 0 Register */ +#define REG_ISI_R2Y_SET1 (0xF003401CU) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 1 Register */ +#define REG_ISI_R2Y_SET2 (0xF0034020U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 2 Register */ +#define REG_ISI_CR (0xF0034024U) /**< \brief (ISI) ISI Control Register */ +#define REG_ISI_SR (0xF0034028U) /**< \brief (ISI) ISI Status Register */ +#define REG_ISI_IER (0xF003402CU) /**< \brief (ISI) ISI Interrupt Enable Register */ +#define REG_ISI_IDR (0xF0034030U) /**< \brief (ISI) ISI Interrupt Disable Register */ +#define REG_ISI_IMR (0xF0034034U) /**< \brief (ISI) ISI Interrupt Mask Register */ +#define REG_ISI_DMA_CHER (0xF0034038U) /**< \brief (ISI) DMA Channel Enable Register */ +#define REG_ISI_DMA_CHDR (0xF003403CU) /**< \brief (ISI) DMA Channel Disable Register */ +#define REG_ISI_DMA_CHSR (0xF0034040U) /**< \brief (ISI) DMA Channel Status Register */ +#define REG_ISI_DMA_P_ADDR (0xF0034044U) /**< \brief (ISI) DMA Preview Base Address Register */ +#define REG_ISI_DMA_P_CTRL (0xF0034048U) /**< \brief (ISI) DMA Preview Control Register */ +#define REG_ISI_DMA_P_DSCR (0xF003404CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ +#define REG_ISI_DMA_C_ADDR (0xF0034050U) /**< \brief (ISI) DMA Codec Base Address Register */ +#define REG_ISI_DMA_C_CTRL (0xF0034054U) /**< \brief (ISI) DMA Codec Control Register */ +#define REG_ISI_DMA_C_DSCR (0xF0034058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ +#define REG_ISI_WPCR (0xF00340E4U) /**< \brief (ISI) Write Protection Control Register */ +#define REG_ISI_WPSR (0xF00340E8U) /**< \brief (ISI) Write Protection Status Register */ +#else +#define REG_ISI_CFG1 (*(RwReg*)0xF0034000U) /**< \brief (ISI) ISI Configuration 1 Register */ +#define REG_ISI_CFG2 (*(RwReg*)0xF0034004U) /**< \brief (ISI) ISI Configuration 2 Register */ +#define REG_ISI_PSIZE (*(RwReg*)0xF0034008U) /**< \brief (ISI) ISI Preview Size Register */ +#define REG_ISI_PDECF (*(RwReg*)0xF003400CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ +#define REG_ISI_Y2R_SET0 (*(RwReg*)0xF0034010U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 0 Register */ +#define REG_ISI_Y2R_SET1 (*(RwReg*)0xF0034014U) /**< \brief (ISI) ISI CSC YCrCb To RGB Set 1 Register */ +#define REG_ISI_R2Y_SET0 (*(RwReg*)0xF0034018U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 0 Register */ +#define REG_ISI_R2Y_SET1 (*(RwReg*)0xF003401CU) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 1 Register */ +#define REG_ISI_R2Y_SET2 (*(RwReg*)0xF0034020U) /**< \brief (ISI) ISI CSC RGB To YCrCb Set 2 Register */ +#define REG_ISI_CR (*(WoReg*)0xF0034024U) /**< \brief (ISI) ISI Control Register */ +#define REG_ISI_SR (*(RoReg*)0xF0034028U) /**< \brief (ISI) ISI Status Register */ +#define REG_ISI_IER (*(WoReg*)0xF003402CU) /**< \brief (ISI) ISI Interrupt Enable Register */ +#define REG_ISI_IDR (*(WoReg*)0xF0034030U) /**< \brief (ISI) ISI Interrupt Disable Register */ +#define REG_ISI_IMR (*(RoReg*)0xF0034034U) /**< \brief (ISI) ISI Interrupt Mask Register */ +#define REG_ISI_DMA_CHER (*(WoReg*)0xF0034038U) /**< \brief (ISI) DMA Channel Enable Register */ +#define REG_ISI_DMA_CHDR (*(WoReg*)0xF003403CU) /**< \brief (ISI) DMA Channel Disable Register */ +#define REG_ISI_DMA_CHSR (*(RoReg*)0xF0034040U) /**< \brief (ISI) DMA Channel Status Register */ +#define REG_ISI_DMA_P_ADDR (*(RwReg*)0xF0034044U) /**< \brief (ISI) DMA Preview Base Address Register */ +#define REG_ISI_DMA_P_CTRL (*(RwReg*)0xF0034048U) /**< \brief (ISI) DMA Preview Control Register */ +#define REG_ISI_DMA_P_DSCR (*(RwReg*)0xF003404CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ +#define REG_ISI_DMA_C_ADDR (*(RwReg*)0xF0034050U) /**< \brief (ISI) DMA Codec Base Address Register */ +#define REG_ISI_DMA_C_CTRL (*(RwReg*)0xF0034054U) /**< \brief (ISI) DMA Codec Control Register */ +#define REG_ISI_DMA_C_DSCR (*(RwReg*)0xF0034058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ +#define REG_ISI_WPCR (*(RwReg*)0xF00340E4U) /**< \brief (ISI) Write Protection Control Register */ +#define REG_ISI_WPSR (*(RoReg*)0xF00340E8U) /**< \brief (ISI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_ISI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_lcdc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_lcdc.h new file mode 100644 index 000000000..85a599943 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_lcdc.h @@ -0,0 +1,392 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_LCDC_INSTANCE_ +#define _SAMA5_LCDC_INSTANCE_ + +/* ========== Register definition for LCDC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_LCDC_LCDCFG0 (0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */ +#define REG_LCDC_LCDCFG1 (0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */ +#define REG_LCDC_LCDCFG2 (0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */ +#define REG_LCDC_LCDCFG3 (0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */ +#define REG_LCDC_LCDCFG4 (0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */ +#define REG_LCDC_LCDCFG5 (0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */ +#define REG_LCDC_LCDCFG6 (0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */ +#define REG_LCDC_LCDEN (0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */ +#define REG_LCDC_LCDDIS (0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */ +#define REG_LCDC_LCDSR (0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */ +#define REG_LCDC_LCDIER (0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */ +#define REG_LCDC_LCDIDR (0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */ +#define REG_LCDC_LCDIMR (0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */ +#define REG_LCDC_LCDISR (0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */ +#define REG_LCDC_BASECHER (0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */ +#define REG_LCDC_BASECHDR (0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */ +#define REG_LCDC_BASECHSR (0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */ +#define REG_LCDC_BASEIER (0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */ +#define REG_LCDC_BASEIDR (0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */ +#define REG_LCDC_BASEIMR (0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */ +#define REG_LCDC_BASEISR (0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */ +#define REG_LCDC_BASEHEAD (0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */ +#define REG_LCDC_BASEADDR (0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */ +#define REG_LCDC_BASECTRL (0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */ +#define REG_LCDC_BASENEXT (0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */ +#define REG_LCDC_BASECFG0 (0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */ +#define REG_LCDC_BASECFG1 (0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */ +#define REG_LCDC_BASECFG2 (0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */ +#define REG_LCDC_BASECFG3 (0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */ +#define REG_LCDC_BASECFG4 (0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */ +#define REG_LCDC_BASECFG5 (0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */ +#define REG_LCDC_BASECFG6 (0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */ +#define REG_LCDC_OVR1CHER (0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */ +#define REG_LCDC_OVR1CHDR (0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */ +#define REG_LCDC_OVR1CHSR (0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */ +#define REG_LCDC_OVR1IER (0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */ +#define REG_LCDC_OVR1IDR (0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */ +#define REG_LCDC_OVR1IMR (0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */ +#define REG_LCDC_OVR1ISR (0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */ +#define REG_LCDC_OVR1HEAD (0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */ +#define REG_LCDC_OVR1ADDR (0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */ +#define REG_LCDC_OVR1CTRL (0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */ +#define REG_LCDC_OVR1NEXT (0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */ +#define REG_LCDC_OVR1CFG0 (0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */ +#define REG_LCDC_OVR1CFG1 (0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */ +#define REG_LCDC_OVR1CFG2 (0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */ +#define REG_LCDC_OVR1CFG3 (0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */ +#define REG_LCDC_OVR1CFG4 (0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */ +#define REG_LCDC_OVR1CFG5 (0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */ +#define REG_LCDC_OVR1CFG6 (0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */ +#define REG_LCDC_OVR1CFG7 (0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */ +#define REG_LCDC_OVR1CFG8 (0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */ +#define REG_LCDC_OVR1CFG9 (0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */ +#define REG_LCDC_OVR2CHER (0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */ +#define REG_LCDC_OVR2CHDR (0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */ +#define REG_LCDC_OVR2CHSR (0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */ +#define REG_LCDC_OVR2IER (0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */ +#define REG_LCDC_OVR2IDR (0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */ +#define REG_LCDC_OVR2IMR (0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */ +#define REG_LCDC_OVR2ISR (0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */ +#define REG_LCDC_OVR2HEAD (0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */ +#define REG_LCDC_OVR2ADDR (0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */ +#define REG_LCDC_OVR2CTRL (0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */ +#define REG_LCDC_OVR2NEXT (0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */ +#define REG_LCDC_OVR2CFG0 (0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */ +#define REG_LCDC_OVR2CFG1 (0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */ +#define REG_LCDC_OVR2CFG2 (0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */ +#define REG_LCDC_OVR2CFG3 (0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */ +#define REG_LCDC_OVR2CFG4 (0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */ +#define REG_LCDC_OVR2CFG5 (0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */ +#define REG_LCDC_OVR2CFG6 (0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */ +#define REG_LCDC_OVR2CFG7 (0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */ +#define REG_LCDC_OVR2CFG8 (0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */ +#define REG_LCDC_OVR2CFG9 (0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */ +#define REG_LCDC_HEOCHER (0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */ +#define REG_LCDC_HEOCHDR (0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */ +#define REG_LCDC_HEOCHSR (0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */ +#define REG_LCDC_HEOIER (0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */ +#define REG_LCDC_HEOIDR (0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */ +#define REG_LCDC_HEOIMR (0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */ +#define REG_LCDC_HEOISR (0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */ +#define REG_LCDC_HEOHEAD (0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */ +#define REG_LCDC_HEOADDR (0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */ +#define REG_LCDC_HEOCTRL (0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */ +#define REG_LCDC_HEONEXT (0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */ +#define REG_LCDC_HEOUHEAD (0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */ +#define REG_LCDC_HEOUADDR (0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */ +#define REG_LCDC_HEOUCTRL (0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */ +#define REG_LCDC_HEOUNEXT (0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */ +#define REG_LCDC_HEOVHEAD (0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */ +#define REG_LCDC_HEOVADDR (0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */ +#define REG_LCDC_HEOVCTRL (0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */ +#define REG_LCDC_HEOVNEXT (0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */ +#define REG_LCDC_HEOCFG0 (0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */ +#define REG_LCDC_HEOCFG1 (0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */ +#define REG_LCDC_HEOCFG2 (0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */ +#define REG_LCDC_HEOCFG3 (0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */ +#define REG_LCDC_HEOCFG4 (0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */ +#define REG_LCDC_HEOCFG5 (0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */ +#define REG_LCDC_HEOCFG6 (0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */ +#define REG_LCDC_HEOCFG7 (0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */ +#define REG_LCDC_HEOCFG8 (0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */ +#define REG_LCDC_HEOCFG9 (0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */ +#define REG_LCDC_HEOCFG10 (0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */ +#define REG_LCDC_HEOCFG11 (0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */ +#define REG_LCDC_HEOCFG12 (0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */ +#define REG_LCDC_HEOCFG13 (0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */ +#define REG_LCDC_HEOCFG14 (0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */ +#define REG_LCDC_HEOCFG15 (0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */ +#define REG_LCDC_HEOCFG16 (0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */ +#define REG_LCDC_HEOCFG17 (0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */ +#define REG_LCDC_HEOCFG18 (0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */ +#define REG_LCDC_HEOCFG19 (0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */ +#define REG_LCDC_HEOCFG20 (0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */ +#define REG_LCDC_HEOCFG21 (0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */ +#define REG_LCDC_HEOCFG22 (0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */ +#define REG_LCDC_HEOCFG23 (0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */ +#define REG_LCDC_HEOCFG24 (0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */ +#define REG_LCDC_HEOCFG25 (0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */ +#define REG_LCDC_HEOCFG26 (0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */ +#define REG_LCDC_HEOCFG27 (0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */ +#define REG_LCDC_HEOCFG28 (0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */ +#define REG_LCDC_HEOCFG29 (0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */ +#define REG_LCDC_HEOCFG30 (0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */ +#define REG_LCDC_HEOCFG31 (0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */ +#define REG_LCDC_HEOCFG32 (0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */ +#define REG_LCDC_HEOCFG33 (0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */ +#define REG_LCDC_HEOCFG34 (0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */ +#define REG_LCDC_HEOCFG35 (0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */ +#define REG_LCDC_HEOCFG36 (0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */ +#define REG_LCDC_HEOCFG37 (0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */ +#define REG_LCDC_HEOCFG38 (0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */ +#define REG_LCDC_HEOCFG39 (0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */ +#define REG_LCDC_HEOCFG40 (0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */ +#define REG_LCDC_HEOCFG41 (0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */ +#define REG_LCDC_HCRCHER (0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */ +#define REG_LCDC_HCRCHDR (0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */ +#define REG_LCDC_HCRCHSR (0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */ +#define REG_LCDC_HCRIER (0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */ +#define REG_LCDC_HCRIDR (0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */ +#define REG_LCDC_HCRIMR (0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */ +#define REG_LCDC_HCRISR (0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */ +#define REG_LCDC_HCRHEAD (0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */ +#define REG_LCDC_HCRADDR (0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */ +#define REG_LCDC_HCRCTRL (0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */ +#define REG_LCDC_HCRNEXT (0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */ +#define REG_LCDC_HCRCFG0 (0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */ +#define REG_LCDC_HCRCFG1 (0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */ +#define REG_LCDC_HCRCFG2 (0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */ +#define REG_LCDC_HCRCFG3 (0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */ +#define REG_LCDC_HCRCFG4 (0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */ +#define REG_LCDC_HCRCFG6 (0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */ +#define REG_LCDC_HCRCFG7 (0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */ +#define REG_LCDC_HCRCFG8 (0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */ +#define REG_LCDC_HCRCFG9 (0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */ +#define REG_LCDC_PPCHER (0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */ +#define REG_LCDC_PPCHDR (0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */ +#define REG_LCDC_PPCHSR (0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */ +#define REG_LCDC_PPIER (0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */ +#define REG_LCDC_PPIDR (0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */ +#define REG_LCDC_PPIMR (0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */ +#define REG_LCDC_PPISR (0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */ +#define REG_LCDC_PPHEAD (0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */ +#define REG_LCDC_PPADDR (0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */ +#define REG_LCDC_PPCTRL (0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */ +#define REG_LCDC_PPNEXT (0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */ +#define REG_LCDC_PPCFG0 (0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */ +#define REG_LCDC_PPCFG1 (0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */ +#define REG_LCDC_PPCFG2 (0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */ +#define REG_LCDC_PPCFG3 (0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */ +#define REG_LCDC_PPCFG4 (0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */ +#define REG_LCDC_PPCFG5 (0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */ +#define REG_LCDC_BASECLUT (0xF0030600U) /**< \brief (LCDC) Base CLUT Register */ +#define REG_LCDC_OVR1CLUT (0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */ +#define REG_LCDC_OVR2CLUT (0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */ +#define REG_LCDC_HEOCLUT (0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */ +#define REG_LCDC_HCRCLUT (0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */ +#else +#define REG_LCDC_LCDCFG0 (*(RwReg*)0xF0030000U) /**< \brief (LCDC) LCD Controller Configuration Register 0 */ +#define REG_LCDC_LCDCFG1 (*(RwReg*)0xF0030004U) /**< \brief (LCDC) LCD Controller Configuration Register 1 */ +#define REG_LCDC_LCDCFG2 (*(RwReg*)0xF0030008U) /**< \brief (LCDC) LCD Controller Configuration Register 2 */ +#define REG_LCDC_LCDCFG3 (*(RwReg*)0xF003000CU) /**< \brief (LCDC) LCD Controller Configuration Register 3 */ +#define REG_LCDC_LCDCFG4 (*(RwReg*)0xF0030010U) /**< \brief (LCDC) LCD Controller Configuration Register 4 */ +#define REG_LCDC_LCDCFG5 (*(RwReg*)0xF0030014U) /**< \brief (LCDC) LCD Controller Configuration Register 5 */ +#define REG_LCDC_LCDCFG6 (*(RwReg*)0xF0030018U) /**< \brief (LCDC) LCD Controller Configuration Register 6 */ +#define REG_LCDC_LCDEN (*(WoReg*)0xF0030020U) /**< \brief (LCDC) LCD Controller Enable Register */ +#define REG_LCDC_LCDDIS (*(WoReg*)0xF0030024U) /**< \brief (LCDC) LCD Controller Disable Register */ +#define REG_LCDC_LCDSR (*(RoReg*)0xF0030028U) /**< \brief (LCDC) LCD Controller Status Register */ +#define REG_LCDC_LCDIER (*(WoReg*)0xF003002CU) /**< \brief (LCDC) LCD Controller Interrupt Enable Register */ +#define REG_LCDC_LCDIDR (*(WoReg*)0xF0030030U) /**< \brief (LCDC) LCD Controller Interrupt Disable Register */ +#define REG_LCDC_LCDIMR (*(RoReg*)0xF0030034U) /**< \brief (LCDC) LCD Controller Interrupt Mask Register */ +#define REG_LCDC_LCDISR (*(RoReg*)0xF0030038U) /**< \brief (LCDC) LCD Controller Interrupt Status Register */ +#define REG_LCDC_BASECHER (*(WoReg*)0xF0030040U) /**< \brief (LCDC) Base Layer Channel Enable Register */ +#define REG_LCDC_BASECHDR (*(WoReg*)0xF0030044U) /**< \brief (LCDC) Base Layer Channel Disable Register */ +#define REG_LCDC_BASECHSR (*(RoReg*)0xF0030048U) /**< \brief (LCDC) Base Layer Channel Status Register */ +#define REG_LCDC_BASEIER (*(WoReg*)0xF003004CU) /**< \brief (LCDC) Base Layer Interrupt Enable Register */ +#define REG_LCDC_BASEIDR (*(WoReg*)0xF0030050U) /**< \brief (LCDC) Base Layer Interrupt Disabled Register */ +#define REG_LCDC_BASEIMR (*(RoReg*)0xF0030054U) /**< \brief (LCDC) Base Layer Interrupt Mask Register */ +#define REG_LCDC_BASEISR (*(RoReg*)0xF0030058U) /**< \brief (LCDC) Base Layer Interrupt status Register */ +#define REG_LCDC_BASEHEAD (*(RwReg*)0xF003005CU) /**< \brief (LCDC) Base DMA Head Register */ +#define REG_LCDC_BASEADDR (*(RwReg*)0xF0030060U) /**< \brief (LCDC) Base DMA Address Register */ +#define REG_LCDC_BASECTRL (*(RwReg*)0xF0030064U) /**< \brief (LCDC) Base DMA Control Register */ +#define REG_LCDC_BASENEXT (*(RwReg*)0xF0030068U) /**< \brief (LCDC) Base DMA Next Register */ +#define REG_LCDC_BASECFG0 (*(RwReg*)0xF003006CU) /**< \brief (LCDC) Base Configuration register 0 */ +#define REG_LCDC_BASECFG1 (*(RwReg*)0xF0030070U) /**< \brief (LCDC) Base Configuration register 1 */ +#define REG_LCDC_BASECFG2 (*(RwReg*)0xF0030074U) /**< \brief (LCDC) Base Configuration register 2 */ +#define REG_LCDC_BASECFG3 (*(RwReg*)0xF0030078U) /**< \brief (LCDC) Base Configuration register 3 */ +#define REG_LCDC_BASECFG4 (*(RwReg*)0xF003007CU) /**< \brief (LCDC) Base Configuration register 4 */ +#define REG_LCDC_BASECFG5 (*(RwReg*)0xF0030080U) /**< \brief (LCDC) Base Configuration register 5 */ +#define REG_LCDC_BASECFG6 (*(RwReg*)0xF0030084U) /**< \brief (LCDC) Base Configuration register 6 */ +#define REG_LCDC_OVR1CHER (*(WoReg*)0xF0030140U) /**< \brief (LCDC) Overlay 1 Channel Enable Register */ +#define REG_LCDC_OVR1CHDR (*(WoReg*)0xF0030144U) /**< \brief (LCDC) Overlay 1 Channel Disable Register */ +#define REG_LCDC_OVR1CHSR (*(RoReg*)0xF0030148U) /**< \brief (LCDC) Overlay 1 Channel Status Register */ +#define REG_LCDC_OVR1IER (*(WoReg*)0xF003014CU) /**< \brief (LCDC) Overlay 1 Interrupt Enable Register */ +#define REG_LCDC_OVR1IDR (*(WoReg*)0xF0030150U) /**< \brief (LCDC) Overlay 1 Interrupt Disable Register */ +#define REG_LCDC_OVR1IMR (*(RoReg*)0xF0030154U) /**< \brief (LCDC) Overlay 1 Interrupt Mask Register */ +#define REG_LCDC_OVR1ISR (*(RoReg*)0xF0030158U) /**< \brief (LCDC) Overlay 1 Interrupt Status Register */ +#define REG_LCDC_OVR1HEAD (*(RwReg*)0xF003015CU) /**< \brief (LCDC) Overlay 1 DMA Head Register */ +#define REG_LCDC_OVR1ADDR (*(RwReg*)0xF0030160U) /**< \brief (LCDC) Overlay 1 DMA Address Register */ +#define REG_LCDC_OVR1CTRL (*(RwReg*)0xF0030164U) /**< \brief (LCDC) Overlay1 DMA Control Register */ +#define REG_LCDC_OVR1NEXT (*(RwReg*)0xF0030168U) /**< \brief (LCDC) Overlay1 DMA Next Register */ +#define REG_LCDC_OVR1CFG0 (*(RwReg*)0xF003016CU) /**< \brief (LCDC) Overlay 1 Configuration 0 Register */ +#define REG_LCDC_OVR1CFG1 (*(RwReg*)0xF0030170U) /**< \brief (LCDC) Overlay 1 Configuration 1 Register */ +#define REG_LCDC_OVR1CFG2 (*(RwReg*)0xF0030174U) /**< \brief (LCDC) Overlay 1 Configuration 2 Register */ +#define REG_LCDC_OVR1CFG3 (*(RwReg*)0xF0030178U) /**< \brief (LCDC) Overlay 1 Configuration 3 Register */ +#define REG_LCDC_OVR1CFG4 (*(RwReg*)0xF003017CU) /**< \brief (LCDC) Overlay 1 Configuration 4 Register */ +#define REG_LCDC_OVR1CFG5 (*(RwReg*)0xF0030180U) /**< \brief (LCDC) Overlay 1 Configuration 5 Register */ +#define REG_LCDC_OVR1CFG6 (*(RwReg*)0xF0030184U) /**< \brief (LCDC) Overlay 1 Configuration 6 Register */ +#define REG_LCDC_OVR1CFG7 (*(RwReg*)0xF0030188U) /**< \brief (LCDC) Overlay 1 Configuration 7 Register */ +#define REG_LCDC_OVR1CFG8 (*(RwReg*)0xF003018CU) /**< \brief (LCDC) Overlay 1 Configuration 8Register */ +#define REG_LCDC_OVR1CFG9 (*(RwReg*)0xF0030190U) /**< \brief (LCDC) Overlay 1 Configuration 9 Register */ +#define REG_LCDC_OVR2CHER (*(WoReg*)0xF0030240U) /**< \brief (LCDC) Overlay 2 Channel Enable Register */ +#define REG_LCDC_OVR2CHDR (*(WoReg*)0xF0030244U) /**< \brief (LCDC) Overlay 2 Channel Disable Register */ +#define REG_LCDC_OVR2CHSR (*(RoReg*)0xF0030248U) /**< \brief (LCDC) Overlay 2 Channel Status Register */ +#define REG_LCDC_OVR2IER (*(WoReg*)0xF003024CU) /**< \brief (LCDC) Overlay 2 Interrupt Enable Register */ +#define REG_LCDC_OVR2IDR (*(WoReg*)0xF0030250U) /**< \brief (LCDC) Overlay 2 Interrupt Disable Register */ +#define REG_LCDC_OVR2IMR (*(RoReg*)0xF0030254U) /**< \brief (LCDC) Overlay 2 Interrupt Mask Register */ +#define REG_LCDC_OVR2ISR (*(RoReg*)0xF0030258U) /**< \brief (LCDC) Overlay 2 Interrupt status Register */ +#define REG_LCDC_OVR2HEAD (*(RwReg*)0xF003025CU) /**< \brief (LCDC) Overlay 2 DMA Head Register */ +#define REG_LCDC_OVR2ADDR (*(RwReg*)0xF0030260U) /**< \brief (LCDC) Overlay 2 DMA Address Register */ +#define REG_LCDC_OVR2CTRL (*(RwReg*)0xF0030264U) /**< \brief (LCDC) Overlay 2 DMA Control Register */ +#define REG_LCDC_OVR2NEXT (*(RwReg*)0xF0030268U) /**< \brief (LCDC) Overlay 2 DMA Next Register */ +#define REG_LCDC_OVR2CFG0 (*(RwReg*)0xF003026CU) /**< \brief (LCDC) Overlay 2 Configuration 0 Register */ +#define REG_LCDC_OVR2CFG1 (*(RwReg*)0xF0030270U) /**< \brief (LCDC) Overlay 2 Configuration 1 Register */ +#define REG_LCDC_OVR2CFG2 (*(RwReg*)0xF0030274U) /**< \brief (LCDC) Overlay 2 Configuration 2 Register */ +#define REG_LCDC_OVR2CFG3 (*(RwReg*)0xF0030278U) /**< \brief (LCDC) Overlay 2 Configuration 3 Register */ +#define REG_LCDC_OVR2CFG4 (*(RwReg*)0xF003027CU) /**< \brief (LCDC) Overlay 2 Configuration 4 Register */ +#define REG_LCDC_OVR2CFG5 (*(RwReg*)0xF0030280U) /**< \brief (LCDC) Overlay 2 Configuration 5 Register */ +#define REG_LCDC_OVR2CFG6 (*(RwReg*)0xF0030284U) /**< \brief (LCDC) Overlay 2 Configuration 6 Register */ +#define REG_LCDC_OVR2CFG7 (*(RwReg*)0xF0030288U) /**< \brief (LCDC) Overlay 2 Configuration 7 Register */ +#define REG_LCDC_OVR2CFG8 (*(RwReg*)0xF003028CU) /**< \brief (LCDC) Overlay 2 Configuration 8 Register */ +#define REG_LCDC_OVR2CFG9 (*(RwReg*)0xF0030290U) /**< \brief (LCDC) Overlay 2 Configuration 9 Register */ +#define REG_LCDC_HEOCHER (*(WoReg*)0xF0030340U) /**< \brief (LCDC) High-End Overlay Channel Enable Register */ +#define REG_LCDC_HEOCHDR (*(WoReg*)0xF0030344U) /**< \brief (LCDC) High-End Overlay Channel Disable Register */ +#define REG_LCDC_HEOCHSR (*(RoReg*)0xF0030348U) /**< \brief (LCDC) High-End Overlay Channel Status Register */ +#define REG_LCDC_HEOIER (*(WoReg*)0xF003034CU) /**< \brief (LCDC) High-End Overlay Interrupt Enable Register */ +#define REG_LCDC_HEOIDR (*(WoReg*)0xF0030350U) /**< \brief (LCDC) High-End Overlay Interrupt Disable Register */ +#define REG_LCDC_HEOIMR (*(RoReg*)0xF0030354U) /**< \brief (LCDC) High-End Overlay Interrupt Mask Register */ +#define REG_LCDC_HEOISR (*(RoReg*)0xF0030358U) /**< \brief (LCDC) High-End Overlay Interrupt Status Register */ +#define REG_LCDC_HEOHEAD (*(RwReg*)0xF003035CU) /**< \brief (LCDC) High-End Overlay DMA Head Register */ +#define REG_LCDC_HEOADDR (*(RwReg*)0xF0030360U) /**< \brief (LCDC) High-End Overlay DMA Address Register */ +#define REG_LCDC_HEOCTRL (*(RwReg*)0xF0030364U) /**< \brief (LCDC) High-End Overlay DMA Control Register */ +#define REG_LCDC_HEONEXT (*(RwReg*)0xF0030368U) /**< \brief (LCDC) High-End Overlay DMA Next Register */ +#define REG_LCDC_HEOUHEAD (*(RwReg*)0xF003036CU) /**< \brief (LCDC) High-End Overlay U DMA Head Register */ +#define REG_LCDC_HEOUADDR (*(RwReg*)0xF0030370U) /**< \brief (LCDC) High-End Overlay U DMA Address Register */ +#define REG_LCDC_HEOUCTRL (*(RwReg*)0xF0030374U) /**< \brief (LCDC) High-End Overlay U DMA control Register */ +#define REG_LCDC_HEOUNEXT (*(RwReg*)0xF0030378U) /**< \brief (LCDC) High-End Overlay U DMA Next Register */ +#define REG_LCDC_HEOVHEAD (*(RwReg*)0xF003037CU) /**< \brief (LCDC) High-End Overlay V DMA Head Register */ +#define REG_LCDC_HEOVADDR (*(RwReg*)0xF0030380U) /**< \brief (LCDC) High-End Overlay V DMA Address Register */ +#define REG_LCDC_HEOVCTRL (*(RwReg*)0xF0030384U) /**< \brief (LCDC) High-End Overlay V DMA control Register */ +#define REG_LCDC_HEOVNEXT (*(RwReg*)0xF0030388U) /**< \brief (LCDC) High-End Overlay VDMA Next Register */ +#define REG_LCDC_HEOCFG0 (*(RwReg*)0xF003038CU) /**< \brief (LCDC) High-End Overlay Configuration Register 0 */ +#define REG_LCDC_HEOCFG1 (*(RwReg*)0xF0030390U) /**< \brief (LCDC) High-End Overlay Configuration Register 1 */ +#define REG_LCDC_HEOCFG2 (*(RwReg*)0xF0030394U) /**< \brief (LCDC) High-End Overlay Configuration Register 2 */ +#define REG_LCDC_HEOCFG3 (*(RwReg*)0xF0030398U) /**< \brief (LCDC) High-End Overlay Configuration Register 3 */ +#define REG_LCDC_HEOCFG4 (*(RwReg*)0xF003039CU) /**< \brief (LCDC) High-End Overlay Configuration Register 4 */ +#define REG_LCDC_HEOCFG5 (*(RwReg*)0xF00303A0U) /**< \brief (LCDC) High-End Overlay Configuration Register 5 */ +#define REG_LCDC_HEOCFG6 (*(RwReg*)0xF00303A4U) /**< \brief (LCDC) High-End Overlay Configuration Register 6 */ +#define REG_LCDC_HEOCFG7 (*(RwReg*)0xF00303A8U) /**< \brief (LCDC) High-End Overlay Configuration Register 7 */ +#define REG_LCDC_HEOCFG8 (*(RwReg*)0xF00303ACU) /**< \brief (LCDC) High-End Overlay Configuration Register 8 */ +#define REG_LCDC_HEOCFG9 (*(RwReg*)0xF00303B0U) /**< \brief (LCDC) High-End Overlay Configuration Register 9 */ +#define REG_LCDC_HEOCFG10 (*(RwReg*)0xF00303B4U) /**< \brief (LCDC) High-End Overlay Configuration Register 10 */ +#define REG_LCDC_HEOCFG11 (*(RwReg*)0xF00303B8U) /**< \brief (LCDC) High-End Overlay Configuration Register 11 */ +#define REG_LCDC_HEOCFG12 (*(RwReg*)0xF00303BCU) /**< \brief (LCDC) High-End Overlay Configuration Register 12 */ +#define REG_LCDC_HEOCFG13 (*(RwReg*)0xF00303C0U) /**< \brief (LCDC) High-End Overlay Configuration Register 13 */ +#define REG_LCDC_HEOCFG14 (*(RwReg*)0xF00303C4U) /**< \brief (LCDC) High-End Overlay Configuration Register 14 */ +#define REG_LCDC_HEOCFG15 (*(RwReg*)0xF00303C8U) /**< \brief (LCDC) High-End Overlay Configuration Register 15 */ +#define REG_LCDC_HEOCFG16 (*(RwReg*)0xF00303CCU) /**< \brief (LCDC) High-End Overlay Configuration Register 16 */ +#define REG_LCDC_HEOCFG17 (*(RwReg*)0xF00303D0U) /**< \brief (LCDC) High-End Overlay Configuration Register 17 */ +#define REG_LCDC_HEOCFG18 (*(RwReg*)0xF00303D4U) /**< \brief (LCDC) High-End Overlay Configuration Register 18 */ +#define REG_LCDC_HEOCFG19 (*(RwReg*)0xF00303D8U) /**< \brief (LCDC) High-End Overlay Configuration Register 19 */ +#define REG_LCDC_HEOCFG20 (*(RwReg*)0xF00303DCU) /**< \brief (LCDC) High-End Overlay Configuration Register 20 */ +#define REG_LCDC_HEOCFG21 (*(RwReg*)0xF00303E0U) /**< \brief (LCDC) High-End Overlay Configuration Register 21 */ +#define REG_LCDC_HEOCFG22 (*(RwReg*)0xF00303E4U) /**< \brief (LCDC) High-End Overlay Configuration Register 22 */ +#define REG_LCDC_HEOCFG23 (*(RwReg*)0xF00303E8U) /**< \brief (LCDC) High-End Overlay Configuration Register 23 */ +#define REG_LCDC_HEOCFG24 (*(RwReg*)0xF00303ECU) /**< \brief (LCDC) High-End Overlay Configuration Register 24 */ +#define REG_LCDC_HEOCFG25 (*(RwReg*)0xF00303F0U) /**< \brief (LCDC) High-End Overlay Configuration Register 25 */ +#define REG_LCDC_HEOCFG26 (*(RwReg*)0xF00303F4U) /**< \brief (LCDC) High-End Overlay Configuration Register 26 */ +#define REG_LCDC_HEOCFG27 (*(RwReg*)0xF00303F8U) /**< \brief (LCDC) High-End Overlay Configuration Register 27 */ +#define REG_LCDC_HEOCFG28 (*(RwReg*)0xF00303FCU) /**< \brief (LCDC) High-End Overlay Configuration Register 28 */ +#define REG_LCDC_HEOCFG29 (*(RwReg*)0xF0030400U) /**< \brief (LCDC) High-End Overlay Configuration Register 29 */ +#define REG_LCDC_HEOCFG30 (*(RwReg*)0xF0030404U) /**< \brief (LCDC) High-End Overlay Configuration Register 30 */ +#define REG_LCDC_HEOCFG31 (*(RwReg*)0xF0030408U) /**< \brief (LCDC) High-End Overlay Configuration Register 31 */ +#define REG_LCDC_HEOCFG32 (*(RwReg*)0xF003040CU) /**< \brief (LCDC) High-End Overlay Configuration Register 32 */ +#define REG_LCDC_HEOCFG33 (*(RwReg*)0xF0030410U) /**< \brief (LCDC) High-End Overlay Configuration Register 33 */ +#define REG_LCDC_HEOCFG34 (*(RwReg*)0xF0030414U) /**< \brief (LCDC) High-End Overlay Configuration Register 34 */ +#define REG_LCDC_HEOCFG35 (*(RwReg*)0xF0030418U) /**< \brief (LCDC) High-End Overlay Configuration Register 35 */ +#define REG_LCDC_HEOCFG36 (*(RwReg*)0xF003041CU) /**< \brief (LCDC) High-End Overlay Configuration Register 36 */ +#define REG_LCDC_HEOCFG37 (*(RwReg*)0xF0030420U) /**< \brief (LCDC) High-End Overlay Configuration Register 37 */ +#define REG_LCDC_HEOCFG38 (*(RwReg*)0xF0030424U) /**< \brief (LCDC) High-End Overlay Configuration Register 38 */ +#define REG_LCDC_HEOCFG39 (*(RwReg*)0xF0030428U) /**< \brief (LCDC) High-End Overlay Configuration Register 39 */ +#define REG_LCDC_HEOCFG40 (*(RwReg*)0xF003042CU) /**< \brief (LCDC) High-End Overlay Configuration Register 40 */ +#define REG_LCDC_HEOCFG41 (*(RwReg*)0xF0030430U) /**< \brief (LCDC) High-End Overlay Configuration Register 41 */ +#define REG_LCDC_HCRCHER (*(WoReg*)0xF0030440U) /**< \brief (LCDC) Hardware Cursor Channel Enable Register */ +#define REG_LCDC_HCRCHDR (*(WoReg*)0xF0030444U) /**< \brief (LCDC) Hardware Cursor Channel disable Register */ +#define REG_LCDC_HCRCHSR (*(RoReg*)0xF0030448U) /**< \brief (LCDC) Hardware Cursor Channel Status Register */ +#define REG_LCDC_HCRIER (*(WoReg*)0xF003044CU) /**< \brief (LCDC) Hardware Cursor Interrupt Enable Register */ +#define REG_LCDC_HCRIDR (*(WoReg*)0xF0030450U) /**< \brief (LCDC) Hardware Cursor Interrupt Disable Register */ +#define REG_LCDC_HCRIMR (*(RoReg*)0xF0030454U) /**< \brief (LCDC) Hardware Cursor Interrupt Mask Register */ +#define REG_LCDC_HCRISR (*(RoReg*)0xF0030458U) /**< \brief (LCDC) Hardware Cursor Interrupt Status Register */ +#define REG_LCDC_HCRHEAD (*(RwReg*)0xF003045CU) /**< \brief (LCDC) Hardware Cursor DMA Head Register */ +#define REG_LCDC_HCRADDR (*(RwReg*)0xF0030460U) /**< \brief (LCDC) Hardware cursor DMA Address Register */ +#define REG_LCDC_HCRCTRL (*(RwReg*)0xF0030464U) /**< \brief (LCDC) Hardware Cursor DMA Control Register */ +#define REG_LCDC_HCRNEXT (*(RwReg*)0xF0030468U) /**< \brief (LCDC) Hardware Cursor DMA NExt Register */ +#define REG_LCDC_HCRCFG0 (*(RwReg*)0xF003046CU) /**< \brief (LCDC) Hardware Cursor Configuration 0 Register */ +#define REG_LCDC_HCRCFG1 (*(RwReg*)0xF0030470U) /**< \brief (LCDC) Hardware Cursor Configuration 1 Register */ +#define REG_LCDC_HCRCFG2 (*(RwReg*)0xF0030474U) /**< \brief (LCDC) Hardware Cursor Configuration 2 Register */ +#define REG_LCDC_HCRCFG3 (*(RwReg*)0xF0030478U) /**< \brief (LCDC) Hardware Cursor Configuration 3 Register */ +#define REG_LCDC_HCRCFG4 (*(RwReg*)0xF003047CU) /**< \brief (LCDC) Hardware Cursor Configuration 4 Register */ +#define REG_LCDC_HCRCFG6 (*(RwReg*)0xF0030484U) /**< \brief (LCDC) Hardware Cursor Configuration 6 Register */ +#define REG_LCDC_HCRCFG7 (*(RwReg*)0xF0030488U) /**< \brief (LCDC) Hardware Cursor Configuration 7 Register */ +#define REG_LCDC_HCRCFG8 (*(RwReg*)0xF003048CU) /**< \brief (LCDC) Hardware Cursor Configuration 8 Register */ +#define REG_LCDC_HCRCFG9 (*(RwReg*)0xF0030490U) /**< \brief (LCDC) Hardware Cursor Configuration 9 Register */ +#define REG_LCDC_PPCHER (*(WoReg*)0xF0030540U) /**< \brief (LCDC) Post Processing Channel Enable Register */ +#define REG_LCDC_PPCHDR (*(WoReg*)0xF0030544U) /**< \brief (LCDC) Post Processing Channel Disable Register */ +#define REG_LCDC_PPCHSR (*(RoReg*)0xF0030548U) /**< \brief (LCDC) Post Processing Channel Status Register */ +#define REG_LCDC_PPIER (*(WoReg*)0xF003054CU) /**< \brief (LCDC) Post Processing Interrupt Enable Register */ +#define REG_LCDC_PPIDR (*(WoReg*)0xF0030550U) /**< \brief (LCDC) Post Processing Interrupt Disable Register */ +#define REG_LCDC_PPIMR (*(RoReg*)0xF0030554U) /**< \brief (LCDC) Post Processing Interrupt Mask Register */ +#define REG_LCDC_PPISR (*(RoReg*)0xF0030558U) /**< \brief (LCDC) Post Processing Interrupt Status Register */ +#define REG_LCDC_PPHEAD (*(RwReg*)0xF003055CU) /**< \brief (LCDC) Post Processing Head Register */ +#define REG_LCDC_PPADDR (*(RwReg*)0xF0030560U) /**< \brief (LCDC) Post Processing Address Register */ +#define REG_LCDC_PPCTRL (*(RwReg*)0xF0030564U) /**< \brief (LCDC) Post Processing Control Register */ +#define REG_LCDC_PPNEXT (*(RwReg*)0xF0030568U) /**< \brief (LCDC) Post Processing Next Register */ +#define REG_LCDC_PPCFG0 (*(RwReg*)0xF003056CU) /**< \brief (LCDC) Post Processing Configuration Register 0 */ +#define REG_LCDC_PPCFG1 (*(RwReg*)0xF0030570U) /**< \brief (LCDC) Post Processing Configuration Register 1 */ +#define REG_LCDC_PPCFG2 (*(RwReg*)0xF0030574U) /**< \brief (LCDC) Post Processing Configuration Register 2 */ +#define REG_LCDC_PPCFG3 (*(RwReg*)0xF0030578U) /**< \brief (LCDC) Post Processing Configuration Register 3 */ +#define REG_LCDC_PPCFG4 (*(RwReg*)0xF003057CU) /**< \brief (LCDC) Post Processing Configuration Register 4 */ +#define REG_LCDC_PPCFG5 (*(RwReg*)0xF0030580U) /**< \brief (LCDC) Post Processing Configuration Register 5 */ +#define REG_LCDC_BASECLUT (*(RwReg*)0xF0030600U) /**< \brief (LCDC) Base CLUT Register */ +#define REG_LCDC_OVR1CLUT (*(RwReg*)0xF0030A00U) /**< \brief (LCDC) Overlay 1 CLUT Register */ +#define REG_LCDC_OVR2CLUT (*(RwReg*)0xF0030E00U) /**< \brief (LCDC) Overlay 2 CLUT Register */ +#define REG_LCDC_HEOCLUT (*(RwReg*)0xF0031200U) /**< \brief (LCDC) High End Overlay CLUT Register */ +#define REG_LCDC_HCRCLUT (*(RwReg*)0xF0031600U) /**< \brief (LCDC) Hardware Cursor CLUT Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_LCDC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_matrix.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_matrix.h new file mode 100644 index 000000000..cb7c61016 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_matrix.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_MATRIX_INSTANCE_ +#define _SAMA5_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MATRIX_MCFG (0xFFFFEC00U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (0xFFFFEC40U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (0xFFFFEC80U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRBS0 (0xFFFFEC84U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ +#define REG_MATRIX_PRAS1 (0xFFFFEC88U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRBS1 (0xFFFFEC8CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ +#define REG_MATRIX_PRAS2 (0xFFFFEC90U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRBS2 (0xFFFFEC94U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ +#define REG_MATRIX_PRAS3 (0xFFFFEC98U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRBS3 (0xFFFFEC9CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ +#define REG_MATRIX_PRAS4 (0xFFFFECA0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRBS4 (0xFFFFECA4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ +#define REG_MATRIX_PRAS5 (0xFFFFECA8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRBS5 (0xFFFFECACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ +#define REG_MATRIX_PRAS6 (0xFFFFECB0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRBS6 (0xFFFFECB4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ +#define REG_MATRIX_PRAS7 (0xFFFFECB8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRBS7 (0xFFFFECBCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ +#define REG_MATRIX_PRAS8 (0xFFFFECC0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRBS8 (0xFFFFECC4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ +#define REG_MATRIX_PRAS9 (0xFFFFECC8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ +#define REG_MATRIX_PRBS9 (0xFFFFECCCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */ +#define REG_MATRIX_PRAS10 (0xFFFFECD0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */ +#define REG_MATRIX_PRBS10 (0xFFFFECD4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */ +#define REG_MATRIX_PRAS11 (0xFFFFECD8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */ +#define REG_MATRIX_PRBS11 (0xFFFFECDCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */ +#define REG_MATRIX_PRAS12 (0xFFFFECE0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */ +#define REG_MATRIX_PRBS12 (0xFFFFECE4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */ +#define REG_MATRIX_PRAS13 (0xFFFFECE8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */ +#define REG_MATRIX_PRBS13 (0xFFFFECECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */ +#define REG_MATRIX_PRAS14 (0xFFFFECF0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */ +#define REG_MATRIX_PRBS14 (0xFFFFECF4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */ +#define REG_MATRIX_PRAS15 (0xFFFFECF8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */ +#define REG_MATRIX_PRBS15 (0xFFFFECFCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */ +#define REG_MATRIX_MRCR (0xFFFFED00U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_MATRIX_SFR (0xFFFFED10U) /**< \brief (MATRIX) Special Function Register */ +#define REG_MATRIX_WPMR (0xFFFFEDE4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (0xFFFFEDE8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else +#define REG_MATRIX_MCFG (*(RwReg*)0xFFFFEC00U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (*(RwReg*)0xFFFFEC40U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (*(RwReg*)0xFFFFEC80U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRBS0 (*(RwReg*)0xFFFFEC84U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(RwReg*)0xFFFFEC88U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRBS1 (*(RwReg*)0xFFFFEC8CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(RwReg*)0xFFFFEC90U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRBS2 (*(RwReg*)0xFFFFEC94U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(RwReg*)0xFFFFEC98U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRBS3 (*(RwReg*)0xFFFFEC9CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ +#define REG_MATRIX_PRAS4 (*(RwReg*)0xFFFFECA0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRBS4 (*(RwReg*)0xFFFFECA4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ +#define REG_MATRIX_PRAS5 (*(RwReg*)0xFFFFECA8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRBS5 (*(RwReg*)0xFFFFECACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ +#define REG_MATRIX_PRAS6 (*(RwReg*)0xFFFFECB0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRBS6 (*(RwReg*)0xFFFFECB4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ +#define REG_MATRIX_PRAS7 (*(RwReg*)0xFFFFECB8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRBS7 (*(RwReg*)0xFFFFECBCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ +#define REG_MATRIX_PRAS8 (*(RwReg*)0xFFFFECC0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_PRBS8 (*(RwReg*)0xFFFFECC4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ +#define REG_MATRIX_PRAS9 (*(RwReg*)0xFFFFECC8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ +#define REG_MATRIX_PRBS9 (*(RwReg*)0xFFFFECCCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */ +#define REG_MATRIX_PRAS10 (*(RwReg*)0xFFFFECD0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */ +#define REG_MATRIX_PRBS10 (*(RwReg*)0xFFFFECD4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */ +#define REG_MATRIX_PRAS11 (*(RwReg*)0xFFFFECD8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */ +#define REG_MATRIX_PRBS11 (*(RwReg*)0xFFFFECDCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */ +#define REG_MATRIX_PRAS12 (*(RwReg*)0xFFFFECE0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */ +#define REG_MATRIX_PRBS12 (*(RwReg*)0xFFFFECE4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */ +#define REG_MATRIX_PRAS13 (*(RwReg*)0xFFFFECE8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */ +#define REG_MATRIX_PRBS13 (*(RwReg*)0xFFFFECECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */ +#define REG_MATRIX_PRAS14 (*(RwReg*)0xFFFFECF0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */ +#define REG_MATRIX_PRBS14 (*(RwReg*)0xFFFFECF4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */ +#define REG_MATRIX_PRAS15 (*(RwReg*)0xFFFFECF8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */ +#define REG_MATRIX_PRBS15 (*(RwReg*)0xFFFFECFCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */ +#define REG_MATRIX_MRCR (*(RwReg*)0xFFFFED00U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_MATRIX_SFR (*(RwReg*)0xFFFFED10U) /**< \brief (MATRIX) Special Function Register */ +#define REG_MATRIX_WPMR (*(RwReg*)0xFFFFEDE4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (*(RoReg*)0xFFFFEDE8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_MATRIX_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_mpddrc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_mpddrc.h new file mode 100644 index 000000000..e44d993fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_mpddrc.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_MPDDRC_INSTANCE_ +#define _SAMA5_MPDDRC_INSTANCE_ + +/* ========== Register definition for MPDDRC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MPDDRC_MR (0xFFFFEA00U) /**< \brief (MPDDRC) MPDDRC Mode Register */ +#define REG_MPDDRC_RTR (0xFFFFEA04U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */ +#define REG_MPDDRC_CR (0xFFFFEA08U) /**< \brief (MPDDRC) MPDDRC Configuration Register */ +#define REG_MPDDRC_TPR0 (0xFFFFEA0CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */ +#define REG_MPDDRC_TPR1 (0xFFFFEA10U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */ +#define REG_MPDDRC_TPR2 (0xFFFFEA14U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */ +#define REG_MPDDRC_LPR (0xFFFFEA1CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */ +#define REG_MPDDRC_MD (0xFFFFEA20U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */ +#define REG_MPDDRC_LPDDR2_LPR (0xFFFFEA28U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */ +#define REG_MPDDRC_LPDDR2_CAL_MR4 (0xFFFFEA2CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */ +#define REG_MPDDRC_LPDDR2_TIM_CAL (0xFFFFEA30U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */ +#define REG_MPDDRC_IO_CALIBR (0xFFFFEA34U) /**< \brief (MPDDRC) MPDDRC IO Calibration */ +#define REG_MPDDRC_OCMS (0xFFFFEA38U) /**< \brief (MPDDRC) MPDDRC OCMS Register */ +#define REG_MPDDRC_OCMS_KEY1 (0xFFFFEA3CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */ +#define REG_MPDDRC_OCMS_KEY2 (0xFFFFEA40U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */ +#define REG_MPDDRC_DLL_MOR (0xFFFFEA74U) /**< \brief (MPDDRC) MPDDRC DLL Master Offset Register */ +#define REG_MPDDRC_DLL_SOR (0xFFFFEA78U) /**< \brief (MPDDRC) MPDDRC DLL Slave Offset Register */ +#define REG_MPDDRC_DLL_MSR (0xFFFFEA7CU) /**< \brief (MPDDRC) MPDDRC DLL Master Status Register */ +#define REG_MPDDRC_DLL_S0SR (0xFFFFEA80U) /**< \brief (MPDDRC) MPDDRC DLL Slave 0 Status Register */ +#define REG_MPDDRC_DLL_S1SR (0xFFFFEA84U) /**< \brief (MPDDRC) MPDDRC DLL Slave 1 Status Register */ +#define REG_MPDDRC_DLL_S2SR (0xFFFFEA88U) /**< \brief (MPDDRC) MPDDRC DLL Slave 2 Status Register */ +#define REG_MPDDRC_DLL_S3SR (0xFFFFEA8CU) /**< \brief (MPDDRC) MPDDRC DLL Slave 3 Status Register */ +#define REG_MPDDRC_WPCR (0xFFFFEAE4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */ +#define REG_MPDDRC_WPSR (0xFFFFEAE8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */ +#else +#define REG_MPDDRC_MR (*(RwReg*)0xFFFFEA00U) /**< \brief (MPDDRC) MPDDRC Mode Register */ +#define REG_MPDDRC_RTR (*(RwReg*)0xFFFFEA04U) /**< \brief (MPDDRC) MPDDRC Refresh Timer Register */ +#define REG_MPDDRC_CR (*(RwReg*)0xFFFFEA08U) /**< \brief (MPDDRC) MPDDRC Configuration Register */ +#define REG_MPDDRC_TPR0 (*(RwReg*)0xFFFFEA0CU) /**< \brief (MPDDRC) MPDDRC Timing Parameter 0 Register */ +#define REG_MPDDRC_TPR1 (*(RwReg*)0xFFFFEA10U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 1 Register */ +#define REG_MPDDRC_TPR2 (*(RwReg*)0xFFFFEA14U) /**< \brief (MPDDRC) MPDDRC Timing Parameter 2 Register */ +#define REG_MPDDRC_LPR (*(RwReg*)0xFFFFEA1CU) /**< \brief (MPDDRC) MPDDRC Low-power Register */ +#define REG_MPDDRC_MD (*(RwReg*)0xFFFFEA20U) /**< \brief (MPDDRC) MPDDRC Memory Device Register */ +#define REG_MPDDRC_LPDDR2_LPR (*(RwReg*)0xFFFFEA28U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Low-power Register */ +#define REG_MPDDRC_LPDDR2_CAL_MR4 (*(RwReg*)0xFFFFEA2CU) /**< \brief (MPDDRC) MPDDRC LPDDR2 Calibration and MR4 Register */ +#define REG_MPDDRC_LPDDR2_TIM_CAL (*(RwReg*)0xFFFFEA30U) /**< \brief (MPDDRC) MPDDRC LPDDR2 Timing Calibration Register */ +#define REG_MPDDRC_IO_CALIBR (*(RwReg*)0xFFFFEA34U) /**< \brief (MPDDRC) MPDDRC IO Calibration */ +#define REG_MPDDRC_OCMS (*(RwReg*)0xFFFFEA38U) /**< \brief (MPDDRC) MPDDRC OCMS Register */ +#define REG_MPDDRC_OCMS_KEY1 (*(WoReg*)0xFFFFEA3CU) /**< \brief (MPDDRC) MPDDRC OCMS KEY1 Register */ +#define REG_MPDDRC_OCMS_KEY2 (*(WoReg*)0xFFFFEA40U) /**< \brief (MPDDRC) MPDDRC OCMS KEY2 Register */ +#define REG_MPDDRC_DLL_MOR (*(RwReg*)0xFFFFEA74U) /**< \brief (MPDDRC) MPDDRC DLL Master Offset Register */ +#define REG_MPDDRC_DLL_SOR (*(RwReg*)0xFFFFEA78U) /**< \brief (MPDDRC) MPDDRC DLL Slave Offset Register */ +#define REG_MPDDRC_DLL_MSR (*(RoReg*)0xFFFFEA7CU) /**< \brief (MPDDRC) MPDDRC DLL Master Status Register */ +#define REG_MPDDRC_DLL_S0SR (*(RoReg*)0xFFFFEA80U) /**< \brief (MPDDRC) MPDDRC DLL Slave 0 Status Register */ +#define REG_MPDDRC_DLL_S1SR (*(RoReg*)0xFFFFEA84U) /**< \brief (MPDDRC) MPDDRC DLL Slave 1 Status Register */ +#define REG_MPDDRC_DLL_S2SR (*(RoReg*)0xFFFFEA88U) /**< \brief (MPDDRC) MPDDRC DLL Slave 2 Status Register */ +#define REG_MPDDRC_DLL_S3SR (*(RoReg*)0xFFFFEA8CU) /**< \brief (MPDDRC) MPDDRC DLL Slave 3 Status Register */ +#define REG_MPDDRC_WPCR (*(RwReg*)0xFFFFEAE4U) /**< \brief (MPDDRC) MPDDRC Write Protect Control Register */ +#define REG_MPDDRC_WPSR (*(RoReg*)0xFFFFEAE8U) /**< \brief (MPDDRC) MPDDRC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_MPDDRC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioa.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioa.h new file mode 100644 index 000000000..21f3a912e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioa.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOA_INSTANCE_ +#define _SAMA5_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOA_PER (0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0xFFFFF218U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_IFSCDR (0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT (0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_DRIVER1 (0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */ +#define REG_PIOA_DRIVER2 (0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */ +#else +#define REG_PIOA_PER (*(WoReg*)0xFFFFF200U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(WoReg*)0xFFFFF204U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(RoReg*)0xFFFFF208U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(WoReg*)0xFFFFF210U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(WoReg*)0xFFFFF214U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(RoReg*)0xFFFFF218U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(WoReg*)0xFFFFF220U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(WoReg*)0xFFFFF224U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(RoReg*)0xFFFFF228U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(WoReg*)0xFFFFF230U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(WoReg*)0xFFFFF234U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(RwReg*)0xFFFFF238U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(RoReg*)0xFFFFF23CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(WoReg*)0xFFFFF240U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(WoReg*)0xFFFFF244U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(RoReg*)0xFFFFF248U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(RoReg*)0xFFFFF24CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(WoReg*)0xFFFFF250U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(WoReg*)0xFFFFF254U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(RoReg*)0xFFFFF258U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(WoReg*)0xFFFFF260U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(WoReg*)0xFFFFF264U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(RoReg*)0xFFFFF268U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABCDSR (*(RwReg*)0xFFFFF270U) /**< \brief (PIOA) Peripheral Select Register */ +#define REG_PIOA_IFSCDR (*(WoReg*)0xFFFFF280U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ +#define REG_PIOA_IFSCER (*(WoReg*)0xFFFFF284U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ +#define REG_PIOA_IFSCSR (*(RoReg*)0xFFFFF288U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ +#define REG_PIOA_SCDR (*(RwReg*)0xFFFFF28CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_PPDDR (*(WoReg*)0xFFFFF290U) /**< \brief (PIOA) Pad Pull-down Disable Register */ +#define REG_PIOA_PPDER (*(WoReg*)0xFFFFF294U) /**< \brief (PIOA) Pad Pull-down Enable Register */ +#define REG_PIOA_PPDSR (*(RoReg*)0xFFFFF298U) /**< \brief (PIOA) Pad Pull-down Status Register */ +#define REG_PIOA_OWER (*(WoReg*)0xFFFFF2A0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(WoReg*)0xFFFFF2A4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(RoReg*)0xFFFFF2A8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(WoReg*)0xFFFFF2B0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(WoReg*)0xFFFFF2B4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (*(RoReg*)0xFFFFF2B8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(WoReg*)0xFFFFF2C0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(WoReg*)0xFFFFF2C4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(RoReg*)0xFFFFF2C8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(WoReg*)0xFFFFF2D0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (*(WoReg*)0xFFFFF2D4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (*(RoReg*)0xFFFFF2D8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (*(RoReg*)0xFFFFF2E0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (*(RwReg*)0xFFFFF2E4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (*(RoReg*)0xFFFFF2E8U) /**< \brief (PIOA) Write Protect Status Register */ +#define REG_PIOA_SCHMITT (*(RwReg*)0xFFFFF300U) /**< \brief (PIOA) Schmitt Trigger Register */ +#define REG_PIOA_DRIVER1 (*(RwReg*)0xFFFFF318U) /**< \brief (PIOA) I/O Drive Register 1 */ +#define REG_PIOA_DRIVER2 (*(RwReg*)0xFFFFF31CU) /**< \brief (PIOA) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOA_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piob.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piob.h new file mode 100644 index 000000000..8c8a7f26d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piob.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOB_INSTANCE_ +#define _SAMA5_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOB_PER (0xFFFFF400U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0xFFFFF404U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0xFFFFF408U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0xFFFFF410U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0xFFFFF414U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0xFFFFF418U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0xFFFFF420U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0xFFFFF424U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0xFFFFF428U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0xFFFFF430U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0xFFFFF434U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0xFFFFF438U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0xFFFFF43CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0xFFFFF440U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0xFFFFF444U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0xFFFFF448U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0xFFFFF44CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0xFFFFF450U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0xFFFFF454U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0xFFFFF458U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0xFFFFF460U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0xFFFFF464U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0xFFFFF468U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (0xFFFFF470U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_IFSCDR (0xFFFFF480U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (0xFFFFF484U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (0xFFFFF488U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (0xFFFFF48CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (0xFFFFF490U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (0xFFFFF494U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (0xFFFFF498U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (0xFFFFF4A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0xFFFFF4A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0xFFFFF4A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0xFFFFF4B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0xFFFFF4B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (0xFFFFF4B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0xFFFFF4C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0xFFFFF4C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0xFFFFF4C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0xFFFFF4D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (0xFFFFF4D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (0xFFFFF4D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (0xFFFFF4E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (0xFFFFF4E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (0xFFFFF4E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT (0xFFFFF500U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_DRIVER1 (0xFFFFF518U) /**< \brief (PIOB) I/O Drive Register 1 */ +#define REG_PIOB_DRIVER2 (0xFFFFF51CU) /**< \brief (PIOB) I/O Drive Register 2 */ +#else +#define REG_PIOB_PER (*(WoReg*)0xFFFFF400U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(WoReg*)0xFFFFF404U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(RoReg*)0xFFFFF408U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(WoReg*)0xFFFFF410U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(WoReg*)0xFFFFF414U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(RoReg*)0xFFFFF418U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(WoReg*)0xFFFFF420U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(WoReg*)0xFFFFF424U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(RoReg*)0xFFFFF428U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(WoReg*)0xFFFFF430U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(WoReg*)0xFFFFF434U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(RwReg*)0xFFFFF438U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(RoReg*)0xFFFFF43CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(WoReg*)0xFFFFF440U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(WoReg*)0xFFFFF444U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(RoReg*)0xFFFFF448U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(RoReg*)0xFFFFF44CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(WoReg*)0xFFFFF450U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(WoReg*)0xFFFFF454U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(RoReg*)0xFFFFF458U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(WoReg*)0xFFFFF460U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(WoReg*)0xFFFFF464U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(RoReg*)0xFFFFF468U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABCDSR (*(RwReg*)0xFFFFF470U) /**< \brief (PIOB) Peripheral Select Register */ +#define REG_PIOB_IFSCDR (*(WoReg*)0xFFFFF480U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ +#define REG_PIOB_IFSCER (*(WoReg*)0xFFFFF484U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ +#define REG_PIOB_IFSCSR (*(RoReg*)0xFFFFF488U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ +#define REG_PIOB_SCDR (*(RwReg*)0xFFFFF48CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_PPDDR (*(WoReg*)0xFFFFF490U) /**< \brief (PIOB) Pad Pull-down Disable Register */ +#define REG_PIOB_PPDER (*(WoReg*)0xFFFFF494U) /**< \brief (PIOB) Pad Pull-down Enable Register */ +#define REG_PIOB_PPDSR (*(RoReg*)0xFFFFF498U) /**< \brief (PIOB) Pad Pull-down Status Register */ +#define REG_PIOB_OWER (*(WoReg*)0xFFFFF4A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(WoReg*)0xFFFFF4A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(RoReg*)0xFFFFF4A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(WoReg*)0xFFFFF4B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(WoReg*)0xFFFFF4B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (*(RoReg*)0xFFFFF4B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(WoReg*)0xFFFFF4C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(WoReg*)0xFFFFF4C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(RoReg*)0xFFFFF4C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(WoReg*)0xFFFFF4D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (*(WoReg*)0xFFFFF4D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (*(RoReg*)0xFFFFF4D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (*(RoReg*)0xFFFFF4E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (*(RwReg*)0xFFFFF4E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (*(RoReg*)0xFFFFF4E8U) /**< \brief (PIOB) Write Protect Status Register */ +#define REG_PIOB_SCHMITT (*(RwReg*)0xFFFFF500U) /**< \brief (PIOB) Schmitt Trigger Register */ +#define REG_PIOB_DRIVER1 (*(RwReg*)0xFFFFF518U) /**< \brief (PIOB) I/O Drive Register 1 */ +#define REG_PIOB_DRIVER2 (*(RwReg*)0xFFFFF51CU) /**< \brief (PIOB) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOB_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioc.h new file mode 100644 index 000000000..98968f043 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioc.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOC_INSTANCE_ +#define _SAMA5_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOC_PER (0xFFFFF600U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (0xFFFFF604U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (0xFFFFF608U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (0xFFFFF610U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (0xFFFFF614U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (0xFFFFF618U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (0xFFFFF620U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (0xFFFFF624U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (0xFFFFF628U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (0xFFFFF630U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (0xFFFFF634U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (0xFFFFF638U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (0xFFFFF63CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (0xFFFFF640U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (0xFFFFF644U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (0xFFFFF648U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (0xFFFFF64CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (0xFFFFF650U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (0xFFFFF654U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (0xFFFFF658U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (0xFFFFF660U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (0xFFFFF664U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (0xFFFFF668U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR (0xFFFFF670U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_IFSCDR (0xFFFFF680U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ +#define REG_PIOC_IFSCER (0xFFFFF684U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ +#define REG_PIOC_IFSCSR (0xFFFFF688U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ +#define REG_PIOC_SCDR (0xFFFFF68CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR (0xFFFFF690U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER (0xFFFFF694U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR (0xFFFFF698U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER (0xFFFFF6A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (0xFFFFF6A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (0xFFFFF6A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (0xFFFFF6B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (0xFFFFF6B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (0xFFFFF6B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (0xFFFFF6C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (0xFFFFF6C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (0xFFFFF6C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (0xFFFFF6D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (0xFFFFF6D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (0xFFFFF6D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (0xFFFFF6E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (0xFFFFF6E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (0xFFFFF6E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT (0xFFFFF700U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_DRIVER1 (0xFFFFF718U) /**< \brief (PIOC) I/O Drive Register 1 */ +#define REG_PIOC_DRIVER2 (0xFFFFF71CU) /**< \brief (PIOC) I/O Drive Register 2 */ +#else +#define REG_PIOC_PER (*(WoReg*)0xFFFFF600U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (*(WoReg*)0xFFFFF604U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (*(RoReg*)0xFFFFF608U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (*(WoReg*)0xFFFFF610U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (*(WoReg*)0xFFFFF614U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (*(RoReg*)0xFFFFF618U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (*(WoReg*)0xFFFFF620U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (*(WoReg*)0xFFFFF624U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (*(RoReg*)0xFFFFF628U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (*(WoReg*)0xFFFFF630U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (*(WoReg*)0xFFFFF634U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (*(RwReg*)0xFFFFF638U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (*(RoReg*)0xFFFFF63CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (*(WoReg*)0xFFFFF640U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (*(WoReg*)0xFFFFF644U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (*(RoReg*)0xFFFFF648U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (*(RoReg*)0xFFFFF64CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (*(WoReg*)0xFFFFF650U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (*(WoReg*)0xFFFFF654U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (*(RoReg*)0xFFFFF658U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (*(WoReg*)0xFFFFF660U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (*(WoReg*)0xFFFFF664U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (*(RoReg*)0xFFFFF668U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABCDSR (*(RwReg*)0xFFFFF670U) /**< \brief (PIOC) Peripheral Select Register */ +#define REG_PIOC_IFSCDR (*(WoReg*)0xFFFFF680U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ +#define REG_PIOC_IFSCER (*(WoReg*)0xFFFFF684U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ +#define REG_PIOC_IFSCSR (*(RoReg*)0xFFFFF688U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ +#define REG_PIOC_SCDR (*(RwReg*)0xFFFFF68CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_PPDDR (*(WoReg*)0xFFFFF690U) /**< \brief (PIOC) Pad Pull-down Disable Register */ +#define REG_PIOC_PPDER (*(WoReg*)0xFFFFF694U) /**< \brief (PIOC) Pad Pull-down Enable Register */ +#define REG_PIOC_PPDSR (*(RoReg*)0xFFFFF698U) /**< \brief (PIOC) Pad Pull-down Status Register */ +#define REG_PIOC_OWER (*(WoReg*)0xFFFFF6A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (*(WoReg*)0xFFFFF6A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (*(RoReg*)0xFFFFF6A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (*(WoReg*)0xFFFFF6B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (*(WoReg*)0xFFFFF6B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (*(RoReg*)0xFFFFF6B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (*(WoReg*)0xFFFFF6C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (*(WoReg*)0xFFFFF6C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (*(RoReg*)0xFFFFF6C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (*(WoReg*)0xFFFFF6D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (*(WoReg*)0xFFFFF6D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (*(RoReg*)0xFFFFF6D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (*(RoReg*)0xFFFFF6E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (*(RwReg*)0xFFFFF6E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (*(RoReg*)0xFFFFF6E8U) /**< \brief (PIOC) Write Protect Status Register */ +#define REG_PIOC_SCHMITT (*(RwReg*)0xFFFFF700U) /**< \brief (PIOC) Schmitt Trigger Register */ +#define REG_PIOC_DRIVER1 (*(RwReg*)0xFFFFF718U) /**< \brief (PIOC) I/O Drive Register 1 */ +#define REG_PIOC_DRIVER2 (*(RwReg*)0xFFFFF71CU) /**< \brief (PIOC) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piod.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piod.h new file mode 100644 index 000000000..c8d262dfa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_piod.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOD_INSTANCE_ +#define _SAMA5_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOD_PER (0xFFFFF800U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (0xFFFFF804U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (0xFFFFF808U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (0xFFFFF810U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (0xFFFFF814U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (0xFFFFF818U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (0xFFFFF820U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (0xFFFFF824U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (0xFFFFF828U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (0xFFFFF830U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (0xFFFFF834U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (0xFFFFF838U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (0xFFFFF83CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (0xFFFFF840U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (0xFFFFF844U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (0xFFFFF848U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (0xFFFFF84CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (0xFFFFF850U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (0xFFFFF854U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (0xFFFFF858U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (0xFFFFF860U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (0xFFFFF864U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (0xFFFFF868U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABCDSR (0xFFFFF870U) /**< \brief (PIOD) Peripheral Select Register */ +#define REG_PIOD_IFSCDR (0xFFFFF880U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ +#define REG_PIOD_IFSCER (0xFFFFF884U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ +#define REG_PIOD_IFSCSR (0xFFFFF888U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ +#define REG_PIOD_SCDR (0xFFFFF88CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_PPDDR (0xFFFFF890U) /**< \brief (PIOD) Pad Pull-down Disable Register */ +#define REG_PIOD_PPDER (0xFFFFF894U) /**< \brief (PIOD) Pad Pull-down Enable Register */ +#define REG_PIOD_PPDSR (0xFFFFF898U) /**< \brief (PIOD) Pad Pull-down Status Register */ +#define REG_PIOD_OWER (0xFFFFF8A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (0xFFFFF8A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (0xFFFFF8A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (0xFFFFF8B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (0xFFFFF8B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (0xFFFFF8B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (0xFFFFF8C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (0xFFFFF8C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (0xFFFFF8C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (0xFFFFF8D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (0xFFFFF8D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (0xFFFFF8D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (0xFFFFF8E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (0xFFFFF8E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (0xFFFFF8E8U) /**< \brief (PIOD) Write Protect Status Register */ +#define REG_PIOD_SCHMITT (0xFFFFF900U) /**< \brief (PIOD) Schmitt Trigger Register */ +#define REG_PIOD_DRIVER1 (0xFFFFF918U) /**< \brief (PIOD) I/O Drive Register 1 */ +#define REG_PIOD_DRIVER2 (0xFFFFF91CU) /**< \brief (PIOD) I/O Drive Register 2 */ +#else +#define REG_PIOD_PER (*(WoReg*)0xFFFFF800U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (*(WoReg*)0xFFFFF804U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (*(RoReg*)0xFFFFF808U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (*(WoReg*)0xFFFFF810U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (*(WoReg*)0xFFFFF814U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (*(RoReg*)0xFFFFF818U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (*(WoReg*)0xFFFFF820U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (*(WoReg*)0xFFFFF824U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (*(RoReg*)0xFFFFF828U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (*(WoReg*)0xFFFFF830U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (*(WoReg*)0xFFFFF834U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (*(RwReg*)0xFFFFF838U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (*(RoReg*)0xFFFFF83CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (*(WoReg*)0xFFFFF840U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (*(WoReg*)0xFFFFF844U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (*(RoReg*)0xFFFFF848U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (*(RoReg*)0xFFFFF84CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (*(WoReg*)0xFFFFF850U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (*(WoReg*)0xFFFFF854U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (*(RoReg*)0xFFFFF858U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (*(WoReg*)0xFFFFF860U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (*(WoReg*)0xFFFFF864U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (*(RoReg*)0xFFFFF868U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABCDSR (*(RwReg*)0xFFFFF870U) /**< \brief (PIOD) Peripheral Select Register */ +#define REG_PIOD_IFSCDR (*(WoReg*)0xFFFFF880U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ +#define REG_PIOD_IFSCER (*(WoReg*)0xFFFFF884U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ +#define REG_PIOD_IFSCSR (*(RoReg*)0xFFFFF888U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ +#define REG_PIOD_SCDR (*(RwReg*)0xFFFFF88CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_PPDDR (*(WoReg*)0xFFFFF890U) /**< \brief (PIOD) Pad Pull-down Disable Register */ +#define REG_PIOD_PPDER (*(WoReg*)0xFFFFF894U) /**< \brief (PIOD) Pad Pull-down Enable Register */ +#define REG_PIOD_PPDSR (*(RoReg*)0xFFFFF898U) /**< \brief (PIOD) Pad Pull-down Status Register */ +#define REG_PIOD_OWER (*(WoReg*)0xFFFFF8A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (*(WoReg*)0xFFFFF8A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (*(RoReg*)0xFFFFF8A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (*(WoReg*)0xFFFFF8B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (*(WoReg*)0xFFFFF8B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (*(RoReg*)0xFFFFF8B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (*(WoReg*)0xFFFFF8C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (*(WoReg*)0xFFFFF8C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (*(RoReg*)0xFFFFF8C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (*(WoReg*)0xFFFFF8D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (*(WoReg*)0xFFFFF8D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (*(RoReg*)0xFFFFF8D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (*(RoReg*)0xFFFFF8E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (*(RwReg*)0xFFFFF8E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (*(RoReg*)0xFFFFF8E8U) /**< \brief (PIOD) Write Protect Status Register */ +#define REG_PIOD_SCHMITT (*(RwReg*)0xFFFFF900U) /**< \brief (PIOD) Schmitt Trigger Register */ +#define REG_PIOD_DRIVER1 (*(RwReg*)0xFFFFF918U) /**< \brief (PIOD) I/O Drive Register 1 */ +#define REG_PIOD_DRIVER2 (*(RwReg*)0xFFFFF91CU) /**< \brief (PIOD) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOD_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioe.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioe.h new file mode 100644 index 000000000..ea5ff10e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pioe.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIOE_INSTANCE_ +#define _SAMA5_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOE_PER (0xFFFFFA00U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (0xFFFFFA04U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (0xFFFFFA08U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (0xFFFFFA10U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (0xFFFFFA14U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (0xFFFFFA18U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (0xFFFFFA20U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (0xFFFFFA24U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (0xFFFFFA28U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (0xFFFFFA30U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (0xFFFFFA34U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (0xFFFFFA38U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (0xFFFFFA3CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (0xFFFFFA40U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (0xFFFFFA44U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (0xFFFFFA48U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (0xFFFFFA4CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (0xFFFFFA50U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (0xFFFFFA54U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (0xFFFFFA58U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (0xFFFFFA60U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (0xFFFFFA64U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (0xFFFFFA68U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABCDSR (0xFFFFFA70U) /**< \brief (PIOE) Peripheral Select Register */ +#define REG_PIOE_IFSCDR (0xFFFFFA80U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ +#define REG_PIOE_IFSCER (0xFFFFFA84U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ +#define REG_PIOE_IFSCSR (0xFFFFFA88U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ +#define REG_PIOE_SCDR (0xFFFFFA8CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_PPDDR (0xFFFFFA90U) /**< \brief (PIOE) Pad Pull-down Disable Register */ +#define REG_PIOE_PPDER (0xFFFFFA94U) /**< \brief (PIOE) Pad Pull-down Enable Register */ +#define REG_PIOE_PPDSR (0xFFFFFA98U) /**< \brief (PIOE) Pad Pull-down Status Register */ +#define REG_PIOE_OWER (0xFFFFFAA0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (0xFFFFFAA4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (0xFFFFFAA8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (0xFFFFFAB0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (0xFFFFFAB4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (0xFFFFFAB8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (0xFFFFFAC0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (0xFFFFFAC4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (0xFFFFFAC8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (0xFFFFFAD0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (0xFFFFFAD4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (0xFFFFFAD8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (0xFFFFFAE0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (0xFFFFFAE4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (0xFFFFFAE8U) /**< \brief (PIOE) Write Protect Status Register */ +#define REG_PIOE_SCHMITT (0xFFFFFB00U) /**< \brief (PIOE) Schmitt Trigger Register */ +#define REG_PIOE_DRIVER1 (0xFFFFFB18U) /**< \brief (PIOE) I/O Drive Register 1 */ +#define REG_PIOE_DRIVER2 (0xFFFFFB1CU) /**< \brief (PIOE) I/O Drive Register 2 */ +#else +#define REG_PIOE_PER (*(WoReg*)0xFFFFFA00U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (*(WoReg*)0xFFFFFA04U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (*(RoReg*)0xFFFFFA08U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (*(WoReg*)0xFFFFFA10U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (*(WoReg*)0xFFFFFA14U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (*(RoReg*)0xFFFFFA18U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (*(WoReg*)0xFFFFFA20U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (*(WoReg*)0xFFFFFA24U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (*(RoReg*)0xFFFFFA28U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (*(WoReg*)0xFFFFFA30U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (*(WoReg*)0xFFFFFA34U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (*(RwReg*)0xFFFFFA38U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (*(RoReg*)0xFFFFFA3CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (*(WoReg*)0xFFFFFA40U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (*(WoReg*)0xFFFFFA44U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (*(RoReg*)0xFFFFFA48U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (*(RoReg*)0xFFFFFA4CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (*(WoReg*)0xFFFFFA50U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (*(WoReg*)0xFFFFFA54U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (*(RoReg*)0xFFFFFA58U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (*(WoReg*)0xFFFFFA60U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (*(WoReg*)0xFFFFFA64U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (*(RoReg*)0xFFFFFA68U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABCDSR (*(RwReg*)0xFFFFFA70U) /**< \brief (PIOE) Peripheral Select Register */ +#define REG_PIOE_IFSCDR (*(WoReg*)0xFFFFFA80U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ +#define REG_PIOE_IFSCER (*(WoReg*)0xFFFFFA84U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ +#define REG_PIOE_IFSCSR (*(RoReg*)0xFFFFFA88U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ +#define REG_PIOE_SCDR (*(RwReg*)0xFFFFFA8CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_PPDDR (*(WoReg*)0xFFFFFA90U) /**< \brief (PIOE) Pad Pull-down Disable Register */ +#define REG_PIOE_PPDER (*(WoReg*)0xFFFFFA94U) /**< \brief (PIOE) Pad Pull-down Enable Register */ +#define REG_PIOE_PPDSR (*(RoReg*)0xFFFFFA98U) /**< \brief (PIOE) Pad Pull-down Status Register */ +#define REG_PIOE_OWER (*(WoReg*)0xFFFFFAA0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (*(WoReg*)0xFFFFFAA4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (*(RoReg*)0xFFFFFAA8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (*(WoReg*)0xFFFFFAB0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (*(WoReg*)0xFFFFFAB4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (*(RoReg*)0xFFFFFAB8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (*(WoReg*)0xFFFFFAC0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (*(WoReg*)0xFFFFFAC4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (*(RoReg*)0xFFFFFAC8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (*(WoReg*)0xFFFFFAD0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (*(WoReg*)0xFFFFFAD4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (*(RoReg*)0xFFFFFAD8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (*(RoReg*)0xFFFFFAE0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (*(RwReg*)0xFFFFFAE4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (*(RoReg*)0xFFFFFAE8U) /**< \brief (PIOE) Write Protect Status Register */ +#define REG_PIOE_SCHMITT (*(RwReg*)0xFFFFFB00U) /**< \brief (PIOE) Schmitt Trigger Register */ +#define REG_PIOE_DRIVER1 (*(RwReg*)0xFFFFFB18U) /**< \brief (PIOE) I/O Drive Register 1 */ +#define REG_PIOE_DRIVER2 (*(RwReg*)0xFFFFFB1CU) /**< \brief (PIOE) I/O Drive Register 2 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIOE_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pit.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pit.h new file mode 100644 index 000000000..efcd222ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pit.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PIT_INSTANCE_ +#define _SAMA5_PIT_INSTANCE_ + +/* ========== Register definition for PIT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIT_MR (0xFFFFFE30U) /**< \brief (PIT) Mode Register */ +#define REG_PIT_SR (0xFFFFFE34U) /**< \brief (PIT) Status Register */ +#define REG_PIT_PIVR (0xFFFFFE38U) /**< \brief (PIT) Periodic Interval Value Register */ +#define REG_PIT_PIIR (0xFFFFFE3CU) /**< \brief (PIT) Periodic Interval Image Register */ +#else +#define REG_PIT_MR (*(RwReg*)0xFFFFFE30U) /**< \brief (PIT) Mode Register */ +#define REG_PIT_SR (*(RoReg*)0xFFFFFE34U) /**< \brief (PIT) Status Register */ +#define REG_PIT_PIVR (*(RoReg*)0xFFFFFE38U) /**< \brief (PIT) Periodic Interval Value Register */ +#define REG_PIT_PIIR (*(RoReg*)0xFFFFFE3CU) /**< \brief (PIT) Periodic Interval Image Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PIT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pmc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pmc.h new file mode 100644 index 000000000..f0d3ed071 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pmc.h @@ -0,0 +1,88 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PMC_INSTANCE_ +#define _SAMA5_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PMC_SCER (0xFFFFFC00U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0xFFFFFC04U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0xFFFFFC08U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0xFFFFFC10U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0xFFFFFC14U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0xFFFFFC18U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (0xFFFFFC1CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (0xFFFFFC20U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0xFFFFFC24U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0xFFFFFC28U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (0xFFFFFC30U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (0xFFFFFC38U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_SMD (0xFFFFFC3CU) /**< \brief (PMC) Soft Modem Clock Register */ +#define REG_PMC_PCK (0xFFFFFC40U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (0xFFFFFC60U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0xFFFFFC64U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0xFFFFFC68U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (0xFFFFFC6CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_PLLICPR (0xFFFFFC80U) /**< \brief (PMC) PLL Charge Pump Current Register */ +#define REG_PMC_WPMR (0xFFFFFCE4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (0xFFFFFCE8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (0xFFFFFD00U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (0xFFFFFD04U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (0xFFFFFD08U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (0xFFFFFD0CU) /**< \brief (PMC) Peripheral Control Register */ +#else +#define REG_PMC_SCER (*(WoReg*)0xFFFFFC00U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(WoReg*)0xFFFFFC04U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(RoReg*)0xFFFFFC08U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(WoReg*)0xFFFFFC10U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(WoReg*)0xFFFFFC14U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(RoReg*)0xFFFFFC18U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (*(RwReg*)0xFFFFFC1CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (*(RwReg*)0xFFFFFC20U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(RoReg*)0xFFFFFC24U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(RwReg*)0xFFFFFC28U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (*(RwReg*)0xFFFFFC30U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (*(RwReg*)0xFFFFFC38U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_SMD (*(RwReg*)0xFFFFFC3CU) /**< \brief (PMC) Soft Modem Clock Register */ +#define REG_PMC_PCK (*(RwReg*)0xFFFFFC40U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (*(WoReg*)0xFFFFFC60U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(WoReg*)0xFFFFFC64U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(RoReg*)0xFFFFFC68U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (*(RoReg*)0xFFFFFC6CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_PLLICPR (*(WoReg*)0xFFFFFC80U) /**< \brief (PMC) PLL Charge Pump Current Register */ +#define REG_PMC_WPMR (*(RwReg*)0xFFFFFCE4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (*(RoReg*)0xFFFFFCE8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (*(WoReg*)0xFFFFFD00U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (*(WoReg*)0xFFFFFD04U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (*(RoReg*)0xFFFFFD08U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (*(RwReg*)0xFFFFFD0CU) /**< \brief (PMC) Peripheral Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pwm.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pwm.h new file mode 100644 index 000000000..b251513ac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_pwm.h @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_PWM_INSTANCE_ +#define _SAMA5_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PWM_CLK (0xF002C000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (0xF002C004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (0xF002C008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (0xF002C00CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV1 (0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ +#define REG_PWM_FPE (0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELMR (0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_FPV2 (0xF002C0C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ +#define REG_PWM_WPCR (0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_CMPV0 (0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMUPD0 (0xF002C400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM_CMUPD1 (0xF002C420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM_CMUPD2 (0xF002C440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM_CMUPD3 (0xF002C460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ +#else +#define REG_PWM_CLK (*(RwReg*)0xF002C000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (*(WoReg*)0xF002C004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (*(WoReg*)0xF002C008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (*(RoReg*)0xF002C00CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (*(WoReg*)0xF002C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (*(WoReg*)0xF002C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (*(RoReg*)0xF002C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (*(RoReg*)0xF002C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (*(RwReg*)0xF002C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (*(RwReg*)0xF002C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (*(RwReg*)0xF002C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (*(WoReg*)0xF002C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (*(WoReg*)0xF002C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (*(WoReg*)0xF002C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (*(RoReg*)0xF002C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (*(RoReg*)0xF002C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (*(RwReg*)0xF002C044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (*(RwReg*)0xF002C048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (*(WoReg*)0xF002C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (*(WoReg*)0xF002C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (*(WoReg*)0xF002C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (*(WoReg*)0xF002C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (*(RwReg*)0xF002C05CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (*(RoReg*)0xF002C060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (*(WoReg*)0xF002C064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV1 (*(RwReg*)0xF002C068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */ +#define REG_PWM_FPE (*(RwReg*)0xF002C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ +#define REG_PWM_ELMR (*(RwReg*)0xF002C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_FPV2 (*(RwReg*)0xF002C0C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */ +#define REG_PWM_WPCR (*(WoReg*)0xF002C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (*(RoReg*)0xF002C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_CMPV0 (*(RwReg*)0xF002C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (*(WoReg*)0xF002C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (*(RwReg*)0xF002C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (*(WoReg*)0xF002C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (*(RwReg*)0xF002C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (*(WoReg*)0xF002C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (*(RwReg*)0xF002C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (*(WoReg*)0xF002C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (*(RwReg*)0xF002C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (*(WoReg*)0xF002C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (*(RwReg*)0xF002C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (*(WoReg*)0xF002C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (*(RwReg*)0xF002C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (*(WoReg*)0xF002C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (*(RwReg*)0xF002C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (*(WoReg*)0xF002C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (*(RwReg*)0xF002C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (*(WoReg*)0xF002C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (*(RwReg*)0xF002C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (*(WoReg*)0xF002C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (*(RwReg*)0xF002C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (*(WoReg*)0xF002C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (*(RwReg*)0xF002C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (*(WoReg*)0xF002C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (*(RwReg*)0xF002C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (*(WoReg*)0xF002C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (*(RwReg*)0xF002C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (*(WoReg*)0xF002C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (*(RwReg*)0xF002C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (*(WoReg*)0xF002C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (*(RwReg*)0xF002C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (*(WoReg*)0xF002C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (*(RwReg*)0xF002C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (*(RwReg*)0xF002C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (*(WoReg*)0xF002C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (*(RwReg*)0xF002C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (*(WoReg*)0xF002C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (*(RoReg*)0xF002C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (*(RwReg*)0xF002C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (*(WoReg*)0xF002C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (*(RwReg*)0xF002C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (*(RwReg*)0xF002C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (*(WoReg*)0xF002C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (*(RwReg*)0xF002C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (*(WoReg*)0xF002C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (*(RoReg*)0xF002C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (*(RwReg*)0xF002C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (*(WoReg*)0xF002C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (*(RwReg*)0xF002C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (*(RwReg*)0xF002C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (*(WoReg*)0xF002C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (*(RwReg*)0xF002C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (*(WoReg*)0xF002C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (*(RoReg*)0xF002C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (*(RwReg*)0xF002C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (*(WoReg*)0xF002C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (*(RwReg*)0xF002C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (*(RwReg*)0xF002C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (*(WoReg*)0xF002C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (*(RwReg*)0xF002C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (*(WoReg*)0xF002C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (*(RoReg*)0xF002C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (*(RwReg*)0xF002C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (*(WoReg*)0xF002C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMUPD0 (*(WoReg*)0xF002C400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */ +#define REG_PWM_CMUPD1 (*(WoReg*)0xF002C420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */ +#define REG_PWM_CMUPD2 (*(WoReg*)0xF002C440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */ +#define REG_PWM_CMUPD3 (*(WoReg*)0xF002C460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_PWM_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rstc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rstc.h new file mode 100644 index 000000000..098e42418 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rstc.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_RSTC_INSTANCE_ +#define _SAMA5_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_CR (0xFFFFFE00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (0xFFFFFE04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (0xFFFFFE08U) /**< \brief (RSTC) Mode Register */ +#else +#define REG_RSTC_CR (*(WoReg*)0xFFFFFE00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (*(RoReg*)0xFFFFFE04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (*(RwReg*)0xFFFFFE08U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_RSTC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rtc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rtc.h new file mode 100644 index 000000000..b1507a741 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_rtc.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_RTC_INSTANCE_ +#define _SAMA5_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_CR (0xFFFFFEB0U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (0xFFFFFEB4U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (0xFFFFFEB8U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (0xFFFFFEBCU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0xFFFFFEC0U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0xFFFFFEC4U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0xFFFFFEC8U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (0xFFFFFECCU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0xFFFFFED0U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0xFFFFFED4U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0xFFFFFED8U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0xFFFFFEDCU) /**< \brief (RTC) Valid Entry Register */ +#else +#define REG_RTC_CR (*(RwReg*)0xFFFFFEB0U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (*(RwReg*)0xFFFFFEB4U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (*(RwReg*)0xFFFFFEB8U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (*(RwReg*)0xFFFFFEBCU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(RwReg*)0xFFFFFEC0U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(RwReg*)0xFFFFFEC4U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(RoReg*)0xFFFFFEC8U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (*(WoReg*)0xFFFFFECCU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(WoReg*)0xFFFFFED0U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(WoReg*)0xFFFFFED4U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(RoReg*)0xFFFFFED8U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(RoReg*)0xFFFFFEDCU) /**< \brief (RTC) Valid Entry Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_RTC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sckc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sckc.h new file mode 100644 index 000000000..6f8b85299 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sckc.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SCKC_INSTANCE_ +#define _SAMA5_SCKC_INSTANCE_ + +/* ========== Register definition for SCKC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SCKC_CR (0xFFFFFE50U) /**< \brief (SCKC) Slow Clock Configuration Register */ +#else +#define REG_SCKC_CR (*(RwReg*)0xFFFFFE50U) /**< \brief (SCKC) Slow Clock Configuration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SCKC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sfr.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sfr.h new file mode 100644 index 000000000..5639ecd6b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sfr.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SFR_INSTANCE_ +#define _SAMA5_SFR_INSTANCE_ + +/* ========== Register definition for SFR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SFR_OHCIICR (0xF0038010U) /**< \brief (SFR) OHCI Interrupt Configuration Register */ +#define REG_SFR_OHCIISR (0xF0038014U) /**< \brief (SFR) OHCI Interrupt Status Register */ +#define REG_SFR_AHB (0xF0038020U) /**< \brief (SFR) AHB Configuration Register */ +#define REG_SFR_BRIDGE (0xF0038024U) /**< \brief (SFR) Bridge Configuration Register */ +#define REG_SFR_SECURE (0xF0038028U) /**< \brief (SFR) Security Configuration Register */ +#define REG_SFR_UTMICKTRIM (0xF0038030U) /**< \brief (SFR) UTMI Clock Trimming Register */ +#define REG_SFR_UTMIHSTRIM (0xF0038034U) /**< \brief (SFR) UTMI High Speed Trimming Register */ +#define REG_SFR_UTMIFSTRIM (0xF0038038U) /**< \brief (SFR) UTMI Full Speed Trimming Register */ +#define REG_SFR_UTMISWAP (0xF003803CU) /**< \brief (SFR) UTMI DP/DM Pin Swapping Register */ +#define REG_SFR_EBICFG (0xF0038040U) /**< \brief (SFR) EBI Configuration Register */ +#else +#define REG_SFR_OHCIICR (*(RwReg*)0xF0038010U) /**< \brief (SFR) OHCI Interrupt Configuration Register */ +#define REG_SFR_OHCIISR (*(RoReg*)0xF0038014U) /**< \brief (SFR) OHCI Interrupt Status Register */ +#define REG_SFR_AHB (*(RwReg*)0xF0038020U) /**< \brief (SFR) AHB Configuration Register */ +#define REG_SFR_BRIDGE (*(RwReg*)0xF0038024U) /**< \brief (SFR) Bridge Configuration Register */ +#define REG_SFR_SECURE (*(RwReg*)0xF0038028U) /**< \brief (SFR) Security Configuration Register */ +#define REG_SFR_UTMICKTRIM (*(RwReg*)0xF0038030U) /**< \brief (SFR) UTMI Clock Trimming Register */ +#define REG_SFR_UTMIHSTRIM (*(RwReg*)0xF0038034U) /**< \brief (SFR) UTMI High Speed Trimming Register */ +#define REG_SFR_UTMIFSTRIM (*(RwReg*)0xF0038038U) /**< \brief (SFR) UTMI Full Speed Trimming Register */ +#define REG_SFR_UTMISWAP (*(RwReg*)0xF003803CU) /**< \brief (SFR) UTMI DP/DM Pin Swapping Register */ +#define REG_SFR_EBICFG (*(RwReg*)0xF0038040U) /**< \brief (SFR) EBI Configuration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SFR_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sha.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sha.h new file mode 100644 index 000000000..15346be14 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_sha.h @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SHA_INSTANCE_ +#define _SAMA5_SHA_INSTANCE_ + +/* ========== Register definition for SHA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SHA_CR (0xF8034000U) /**< \brief (SHA) Control Register */ +#define REG_SHA_MR (0xF8034004U) /**< \brief (SHA) Mode Register */ +#define REG_SHA_IER (0xF8034010U) /**< \brief (SHA) Interrupt Enable Register */ +#define REG_SHA_IDR (0xF8034014U) /**< \brief (SHA) Interrupt Disable Register */ +#define REG_SHA_IMR (0xF8034018U) /**< \brief (SHA) Interrupt Mask Register */ +#define REG_SHA_ISR (0xF803401CU) /**< \brief (SHA) Interrupt Status Register */ +#define REG_SHA_IDATAR (0xF8034040U) /**< \brief (SHA) Input Data 0 Register */ +#define REG_SHA_IODATAR (0xF8034080U) /**< \brief (SHA) Input/Output Data 0 Register */ +#else +#define REG_SHA_CR (*(WoReg*)0xF8034000U) /**< \brief (SHA) Control Register */ +#define REG_SHA_MR (*(RwReg*)0xF8034004U) /**< \brief (SHA) Mode Register */ +#define REG_SHA_IER (*(WoReg*)0xF8034010U) /**< \brief (SHA) Interrupt Enable Register */ +#define REG_SHA_IDR (*(WoReg*)0xF8034014U) /**< \brief (SHA) Interrupt Disable Register */ +#define REG_SHA_IMR (*(RoReg*)0xF8034018U) /**< \brief (SHA) Interrupt Mask Register */ +#define REG_SHA_ISR (*(RoReg*)0xF803401CU) /**< \brief (SHA) Interrupt Status Register */ +#define REG_SHA_IDATAR (*(WoReg*)0xF8034040U) /**< \brief (SHA) Input Data 0 Register */ +#define REG_SHA_IODATAR (*(RwReg*)0xF8034080U) /**< \brief (SHA) Input/Output Data 0 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SHA_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_shdwc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_shdwc.h new file mode 100644 index 000000000..001623e85 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_shdwc.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SHDWC_INSTANCE_ +#define _SAMA5_SHDWC_INSTANCE_ + +/* ========== Register definition for SHDWC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SHDWC_CR (0xFFFFFE10U) /**< \brief (SHDWC) Shutdown Control Register */ +#define REG_SHDWC_MR (0xFFFFFE14U) /**< \brief (SHDWC) Shutdown Mode Register */ +#define REG_SHDWC_SR (0xFFFFFE18U) /**< \brief (SHDWC) Shutdown Status Register */ +#else +#define REG_SHDWC_CR (*(WoReg*)0xFFFFFE10U) /**< \brief (SHDWC) Shutdown Control Register */ +#define REG_SHDWC_MR (*(RwReg*)0xFFFFFE14U) /**< \brief (SHDWC) Shutdown Mode Register */ +#define REG_SHDWC_SR (*(RoReg*)0xFFFFFE18U) /**< \brief (SHDWC) Shutdown Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SHDWC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smc.h new file mode 100644 index 000000000..3e6a88170 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smc.h @@ -0,0 +1,602 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SMC_INSTANCE_ +#define _SAMA5_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SMC_CFG (0xFFFFC000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (0xFFFFC004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (0xFFFFC008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (0xFFFFC00CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (0xFFFFC010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (0xFFFFC014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (0xFFFFC018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (0xFFFFC01CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (0xFFFFC020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (0xFFFFC024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (0xFFFFC028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (0xFFFFC02CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (0xFFFFC030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (0xFFFFC034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (0xFFFFC038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (0xFFFFC03CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (0xFFFFC040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (0xFFFFC044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (0xFFFFC048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (0xFFFFC04CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (0xFFFFC050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (0xFFFFC054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (0xFFFFC058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (0xFFFFC05CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (0xFFFFC060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (0xFFFFC064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (0xFFFFC068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (0xFFFFC06CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_PMECCFG (0xFFFFC070U) /**< \brief (SMC) PMECC Configuration Register */ +#define REG_SMC_PMECCSAREA (0xFFFFC074U) /**< \brief (SMC) PMECC Spare Area Size Register */ +#define REG_SMC_PMECCSADDR (0xFFFFC078U) /**< \brief (SMC) PMECC Start Address Register */ +#define REG_SMC_PMECCEADDR (0xFFFFC07CU) /**< \brief (SMC) PMECC End Address Register */ +#define REG_SMC_PMECCTRL (0xFFFFC084U) /**< \brief (SMC) PMECC Control Register */ +#define REG_SMC_PMECCSR (0xFFFFC088U) /**< \brief (SMC) PMECC Status Register */ +#define REG_SMC_PMECCIER (0xFFFFC08CU) /**< \brief (SMC) PMECC Interrupt Enable register */ +#define REG_SMC_PMECCIDR (0xFFFFC090U) /**< \brief (SMC) PMECC Interrupt Disable Register */ +#define REG_SMC_PMECCIMR (0xFFFFC094U) /**< \brief (SMC) PMECC Interrupt Mask Register */ +#define REG_SMC_PMECCISR (0xFFFFC098U) /**< \brief (SMC) PMECC Interrupt Status Register */ +#define REG_SMC_PMECC0_0 (0xFFFFC0B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 0) */ +#define REG_SMC_PMECC1_0 (0xFFFFC0B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 0) */ +#define REG_SMC_PMECC2_0 (0xFFFFC0B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 0) */ +#define REG_SMC_PMECC3_0 (0xFFFFC0BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 0) */ +#define REG_SMC_PMECC4_0 (0xFFFFC0C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 0) */ +#define REG_SMC_PMECC5_0 (0xFFFFC0C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 0) */ +#define REG_SMC_PMECC6_0 (0xFFFFC0C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 0) */ +#define REG_SMC_PMECC7_0 (0xFFFFC0CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 0) */ +#define REG_SMC_PMECC8_0 (0xFFFFC0D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 0) */ +#define REG_SMC_PMECC9_0 (0xFFFFC0D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 0) */ +#define REG_SMC_PMECC10_0 (0xFFFFC0D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 0) */ +#define REG_SMC_PMECC0_1 (0xFFFFC0F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 1) */ +#define REG_SMC_PMECC1_1 (0xFFFFC0F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 1) */ +#define REG_SMC_PMECC2_1 (0xFFFFC0F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 1) */ +#define REG_SMC_PMECC3_1 (0xFFFFC0FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 1) */ +#define REG_SMC_PMECC4_1 (0xFFFFC100U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 1) */ +#define REG_SMC_PMECC5_1 (0xFFFFC104U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 1) */ +#define REG_SMC_PMECC6_1 (0xFFFFC108U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 1) */ +#define REG_SMC_PMECC7_1 (0xFFFFC10CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 1) */ +#define REG_SMC_PMECC8_1 (0xFFFFC110U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 1) */ +#define REG_SMC_PMECC9_1 (0xFFFFC114U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 1) */ +#define REG_SMC_PMECC10_1 (0xFFFFC118U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 1) */ +#define REG_SMC_PMECC0_2 (0xFFFFC130U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 2) */ +#define REG_SMC_PMECC1_2 (0xFFFFC134U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 2) */ +#define REG_SMC_PMECC2_2 (0xFFFFC138U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 2) */ +#define REG_SMC_PMECC3_2 (0xFFFFC13CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 2) */ +#define REG_SMC_PMECC4_2 (0xFFFFC140U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 2) */ +#define REG_SMC_PMECC5_2 (0xFFFFC144U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 2) */ +#define REG_SMC_PMECC6_2 (0xFFFFC148U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 2) */ +#define REG_SMC_PMECC7_2 (0xFFFFC14CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 2) */ +#define REG_SMC_PMECC8_2 (0xFFFFC150U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 2) */ +#define REG_SMC_PMECC9_2 (0xFFFFC154U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 2) */ +#define REG_SMC_PMECC10_2 (0xFFFFC158U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 2) */ +#define REG_SMC_PMECC0_3 (0xFFFFC170U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 3) */ +#define REG_SMC_PMECC1_3 (0xFFFFC174U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 3) */ +#define REG_SMC_PMECC2_3 (0xFFFFC178U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 3) */ +#define REG_SMC_PMECC3_3 (0xFFFFC17CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 3) */ +#define REG_SMC_PMECC4_3 (0xFFFFC180U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 3) */ +#define REG_SMC_PMECC5_3 (0xFFFFC184U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 3) */ +#define REG_SMC_PMECC6_3 (0xFFFFC188U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 3) */ +#define REG_SMC_PMECC7_3 (0xFFFFC18CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 3) */ +#define REG_SMC_PMECC8_3 (0xFFFFC190U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 3) */ +#define REG_SMC_PMECC9_3 (0xFFFFC194U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 3) */ +#define REG_SMC_PMECC10_3 (0xFFFFC198U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 3) */ +#define REG_SMC_PMECC0_4 (0xFFFFC1B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 4) */ +#define REG_SMC_PMECC1_4 (0xFFFFC1B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 4) */ +#define REG_SMC_PMECC2_4 (0xFFFFC1B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 4) */ +#define REG_SMC_PMECC3_4 (0xFFFFC1BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 4) */ +#define REG_SMC_PMECC4_4 (0xFFFFC1C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 4) */ +#define REG_SMC_PMECC5_4 (0xFFFFC1C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 4) */ +#define REG_SMC_PMECC6_4 (0xFFFFC1C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 4) */ +#define REG_SMC_PMECC7_4 (0xFFFFC1CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 4) */ +#define REG_SMC_PMECC8_4 (0xFFFFC1D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 4) */ +#define REG_SMC_PMECC9_4 (0xFFFFC1D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 4) */ +#define REG_SMC_PMECC10_4 (0xFFFFC1D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 4) */ +#define REG_SMC_PMECC0_5 (0xFFFFC1F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 5) */ +#define REG_SMC_PMECC1_5 (0xFFFFC1F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 5) */ +#define REG_SMC_PMECC2_5 (0xFFFFC1F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 5) */ +#define REG_SMC_PMECC3_5 (0xFFFFC1FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 5) */ +#define REG_SMC_PMECC4_5 (0xFFFFC200U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 5) */ +#define REG_SMC_PMECC5_5 (0xFFFFC204U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 5) */ +#define REG_SMC_PMECC6_5 (0xFFFFC208U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 5) */ +#define REG_SMC_PMECC7_5 (0xFFFFC20CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 5) */ +#define REG_SMC_PMECC8_5 (0xFFFFC210U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 5) */ +#define REG_SMC_PMECC9_5 (0xFFFFC214U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 5) */ +#define REG_SMC_PMECC10_5 (0xFFFFC218U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 5) */ +#define REG_SMC_PMECC0_6 (0xFFFFC230U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 6) */ +#define REG_SMC_PMECC1_6 (0xFFFFC234U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 6) */ +#define REG_SMC_PMECC2_6 (0xFFFFC238U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 6) */ +#define REG_SMC_PMECC3_6 (0xFFFFC23CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 6) */ +#define REG_SMC_PMECC4_6 (0xFFFFC240U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 6) */ +#define REG_SMC_PMECC5_6 (0xFFFFC244U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 6) */ +#define REG_SMC_PMECC6_6 (0xFFFFC248U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 6) */ +#define REG_SMC_PMECC7_6 (0xFFFFC24CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 6) */ +#define REG_SMC_PMECC8_6 (0xFFFFC250U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 6) */ +#define REG_SMC_PMECC9_6 (0xFFFFC254U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 6) */ +#define REG_SMC_PMECC10_6 (0xFFFFC258U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 6) */ +#define REG_SMC_PMECC0_7 (0xFFFFC270U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 7) */ +#define REG_SMC_PMECC1_7 (0xFFFFC274U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 7) */ +#define REG_SMC_PMECC2_7 (0xFFFFC278U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 7) */ +#define REG_SMC_PMECC3_7 (0xFFFFC27CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 7) */ +#define REG_SMC_PMECC4_7 (0xFFFFC280U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 7) */ +#define REG_SMC_PMECC5_7 (0xFFFFC284U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 7) */ +#define REG_SMC_PMECC6_7 (0xFFFFC288U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 7) */ +#define REG_SMC_PMECC7_7 (0xFFFFC28CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 7) */ +#define REG_SMC_PMECC8_7 (0xFFFFC290U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 7) */ +#define REG_SMC_PMECC9_7 (0xFFFFC294U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 7) */ +#define REG_SMC_PMECC10_7 (0xFFFFC298U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 7) */ +#define REG_SMC_REM0_0 (0xFFFFC2B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 0) */ +#define REG_SMC_REM1_0 (0xFFFFC2B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 0) */ +#define REG_SMC_REM2_0 (0xFFFFC2B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 0) */ +#define REG_SMC_REM3_0 (0xFFFFC2BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 0) */ +#define REG_SMC_REM4_0 (0xFFFFC2C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 0) */ +#define REG_SMC_REM5_0 (0xFFFFC2C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 0) */ +#define REG_SMC_REM6_0 (0xFFFFC2C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 0) */ +#define REG_SMC_REM7_0 (0xFFFFC2CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 0) */ +#define REG_SMC_REM8_0 (0xFFFFC2D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 0) */ +#define REG_SMC_REM9_0 (0xFFFFC2D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 0) */ +#define REG_SMC_REM10_0 (0xFFFFC2D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 0) */ +#define REG_SMC_REM11_0 (0xFFFFC2DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 0) */ +#define REG_SMC_REM0_1 (0xFFFFC2F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 1) */ +#define REG_SMC_REM1_1 (0xFFFFC2F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 1) */ +#define REG_SMC_REM2_1 (0xFFFFC2F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 1) */ +#define REG_SMC_REM3_1 (0xFFFFC2FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 1) */ +#define REG_SMC_REM4_1 (0xFFFFC300U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 1) */ +#define REG_SMC_REM5_1 (0xFFFFC304U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 1) */ +#define REG_SMC_REM6_1 (0xFFFFC308U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 1) */ +#define REG_SMC_REM7_1 (0xFFFFC30CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 1) */ +#define REG_SMC_REM8_1 (0xFFFFC310U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 1) */ +#define REG_SMC_REM9_1 (0xFFFFC314U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 1) */ +#define REG_SMC_REM10_1 (0xFFFFC318U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 1) */ +#define REG_SMC_REM11_1 (0xFFFFC31CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 1) */ +#define REG_SMC_REM0_2 (0xFFFFC330U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 2) */ +#define REG_SMC_REM1_2 (0xFFFFC334U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 2) */ +#define REG_SMC_REM2_2 (0xFFFFC338U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 2) */ +#define REG_SMC_REM3_2 (0xFFFFC33CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 2) */ +#define REG_SMC_REM4_2 (0xFFFFC340U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 2) */ +#define REG_SMC_REM5_2 (0xFFFFC344U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 2) */ +#define REG_SMC_REM6_2 (0xFFFFC348U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 2) */ +#define REG_SMC_REM7_2 (0xFFFFC34CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 2) */ +#define REG_SMC_REM8_2 (0xFFFFC350U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 2) */ +#define REG_SMC_REM9_2 (0xFFFFC354U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 2) */ +#define REG_SMC_REM10_2 (0xFFFFC358U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 2) */ +#define REG_SMC_REM11_2 (0xFFFFC35CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 2) */ +#define REG_SMC_REM0_3 (0xFFFFC370U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 3) */ +#define REG_SMC_REM1_3 (0xFFFFC374U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 3) */ +#define REG_SMC_REM2_3 (0xFFFFC378U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 3) */ +#define REG_SMC_REM3_3 (0xFFFFC37CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 3) */ +#define REG_SMC_REM4_3 (0xFFFFC380U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 3) */ +#define REG_SMC_REM5_3 (0xFFFFC384U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 3) */ +#define REG_SMC_REM6_3 (0xFFFFC388U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 3) */ +#define REG_SMC_REM7_3 (0xFFFFC38CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 3) */ +#define REG_SMC_REM8_3 (0xFFFFC390U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 3) */ +#define REG_SMC_REM9_3 (0xFFFFC394U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 3) */ +#define REG_SMC_REM10_3 (0xFFFFC398U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 3) */ +#define REG_SMC_REM11_3 (0xFFFFC39CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 3) */ +#define REG_SMC_REM0_4 (0xFFFFC3B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 4) */ +#define REG_SMC_REM1_4 (0xFFFFC3B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 4) */ +#define REG_SMC_REM2_4 (0xFFFFC3B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 4) */ +#define REG_SMC_REM3_4 (0xFFFFC3BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 4) */ +#define REG_SMC_REM4_4 (0xFFFFC3C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 4) */ +#define REG_SMC_REM5_4 (0xFFFFC3C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 4) */ +#define REG_SMC_REM6_4 (0xFFFFC3C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 4) */ +#define REG_SMC_REM7_4 (0xFFFFC3CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 4) */ +#define REG_SMC_REM8_4 (0xFFFFC3D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 4) */ +#define REG_SMC_REM9_4 (0xFFFFC3D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 4) */ +#define REG_SMC_REM10_4 (0xFFFFC3D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 4) */ +#define REG_SMC_REM11_4 (0xFFFFC3DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 4) */ +#define REG_SMC_REM0_5 (0xFFFFC3F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 5) */ +#define REG_SMC_REM1_5 (0xFFFFC3F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 5) */ +#define REG_SMC_REM2_5 (0xFFFFC3F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 5) */ +#define REG_SMC_REM3_5 (0xFFFFC3FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 5) */ +#define REG_SMC_REM4_5 (0xFFFFC400U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 5) */ +#define REG_SMC_REM5_5 (0xFFFFC404U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 5) */ +#define REG_SMC_REM6_5 (0xFFFFC408U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 5) */ +#define REG_SMC_REM7_5 (0xFFFFC40CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 5) */ +#define REG_SMC_REM8_5 (0xFFFFC410U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 5) */ +#define REG_SMC_REM9_5 (0xFFFFC414U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 5) */ +#define REG_SMC_REM10_5 (0xFFFFC418U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 5) */ +#define REG_SMC_REM11_5 (0xFFFFC41CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 5) */ +#define REG_SMC_REM0_6 (0xFFFFC430U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 6) */ +#define REG_SMC_REM1_6 (0xFFFFC434U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 6) */ +#define REG_SMC_REM2_6 (0xFFFFC438U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 6) */ +#define REG_SMC_REM3_6 (0xFFFFC43CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 6) */ +#define REG_SMC_REM4_6 (0xFFFFC440U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 6) */ +#define REG_SMC_REM5_6 (0xFFFFC444U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 6) */ +#define REG_SMC_REM6_6 (0xFFFFC448U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 6) */ +#define REG_SMC_REM7_6 (0xFFFFC44CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 6) */ +#define REG_SMC_REM8_6 (0xFFFFC450U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 6) */ +#define REG_SMC_REM9_6 (0xFFFFC454U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 6) */ +#define REG_SMC_REM10_6 (0xFFFFC458U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 6) */ +#define REG_SMC_REM11_6 (0xFFFFC45CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 6) */ +#define REG_SMC_REM0_7 (0xFFFFC470U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 7) */ +#define REG_SMC_REM1_7 (0xFFFFC474U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 7) */ +#define REG_SMC_REM2_7 (0xFFFFC478U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 7) */ +#define REG_SMC_REM3_7 (0xFFFFC47CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 7) */ +#define REG_SMC_REM4_7 (0xFFFFC480U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 7) */ +#define REG_SMC_REM5_7 (0xFFFFC484U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 7) */ +#define REG_SMC_REM6_7 (0xFFFFC488U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 7) */ +#define REG_SMC_REM7_7 (0xFFFFC48CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 7) */ +#define REG_SMC_REM8_7 (0xFFFFC490U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 7) */ +#define REG_SMC_REM9_7 (0xFFFFC494U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 7) */ +#define REG_SMC_REM10_7 (0xFFFFC498U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 7) */ +#define REG_SMC_REM11_7 (0xFFFFC49CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 7) */ +#define REG_SMC_ELCFG (0xFFFFC500U) /**< \brief (SMC) PMECC Error Location Configuration Register */ +#define REG_SMC_ELPRIM (0xFFFFC504U) /**< \brief (SMC) PMECC Error Location Primitive Register */ +#define REG_SMC_ELEN (0xFFFFC508U) /**< \brief (SMC) PMECC Error Location Enable Register */ +#define REG_SMC_ELDIS (0xFFFFC50CU) /**< \brief (SMC) PMECC Error Location Disable Register */ +#define REG_SMC_ELSR (0xFFFFC510U) /**< \brief (SMC) PMECC Error Location Status Register */ +#define REG_SMC_ELIER (0xFFFFC514U) /**< \brief (SMC) PMECC Error Location Interrupt Enable register */ +#define REG_SMC_ELIDR (0xFFFFC518U) /**< \brief (SMC) PMECC Error Location Interrupt Disable Register */ +#define REG_SMC_ELIMR (0xFFFFC51CU) /**< \brief (SMC) PMECC Error Location Interrupt Mask Register */ +#define REG_SMC_ELISR (0xFFFFC520U) /**< \brief (SMC) PMECC Error Location Interrupt Status Register */ +#define REG_SMC_SIGMA0 (0xFFFFC528U) /**< \brief (SMC) PMECC Error Location SIGMA 0 Register */ +#define REG_SMC_SIGMA1 (0xFFFFC52CU) /**< \brief (SMC) PMECC Error Location SIGMA 1 Register */ +#define REG_SMC_SIGMA2 (0xFFFFC530U) /**< \brief (SMC) PMECC Error Location SIGMA 2 Register */ +#define REG_SMC_SIGMA3 (0xFFFFC534U) /**< \brief (SMC) PMECC Error Location SIGMA 3 Register */ +#define REG_SMC_SIGMA4 (0xFFFFC538U) /**< \brief (SMC) PMECC Error Location SIGMA 4 Register */ +#define REG_SMC_SIGMA5 (0xFFFFC53CU) /**< \brief (SMC) PMECC Error Location SIGMA 5 Register */ +#define REG_SMC_SIGMA6 (0xFFFFC540U) /**< \brief (SMC) PMECC Error Location SIGMA 6 Register */ +#define REG_SMC_SIGMA7 (0xFFFFC544U) /**< \brief (SMC) PMECC Error Location SIGMA 7 Register */ +#define REG_SMC_SIGMA8 (0xFFFFC548U) /**< \brief (SMC) PMECC Error Location SIGMA 8 Register */ +#define REG_SMC_SIGMA9 (0xFFFFC54CU) /**< \brief (SMC) PMECC Error Location SIGMA 9 Register */ +#define REG_SMC_SIGMA10 (0xFFFFC550U) /**< \brief (SMC) PMECC Error Location SIGMA 10 Register */ +#define REG_SMC_SIGMA11 (0xFFFFC554U) /**< \brief (SMC) PMECC Error Location SIGMA 11 Register */ +#define REG_SMC_SIGMA12 (0xFFFFC558U) /**< \brief (SMC) PMECC Error Location SIGMA 12 Register */ +#define REG_SMC_SIGMA13 (0xFFFFC55CU) /**< \brief (SMC) PMECC Error Location SIGMA 13 Register */ +#define REG_SMC_SIGMA14 (0xFFFFC560U) /**< \brief (SMC) PMECC Error Location SIGMA 14 Register */ +#define REG_SMC_SIGMA15 (0xFFFFC564U) /**< \brief (SMC) PMECC Error Location SIGMA 15 Register */ +#define REG_SMC_SIGMA16 (0xFFFFC568U) /**< \brief (SMC) PMECC Error Location SIGMA 16 Register */ +#define REG_SMC_SIGMA17 (0xFFFFC56CU) /**< \brief (SMC) PMECC Error Location SIGMA 17 Register */ +#define REG_SMC_SIGMA18 (0xFFFFC570U) /**< \brief (SMC) PMECC Error Location SIGMA 18 Register */ +#define REG_SMC_SIGMA19 (0xFFFFC574U) /**< \brief (SMC) PMECC Error Location SIGMA 19 Register */ +#define REG_SMC_SIGMA20 (0xFFFFC578U) /**< \brief (SMC) PMECC Error Location SIGMA 20 Register */ +#define REG_SMC_SIGMA21 (0xFFFFC57CU) /**< \brief (SMC) PMECC Error Location SIGMA 21 Register */ +#define REG_SMC_SIGMA22 (0xFFFFC580U) /**< \brief (SMC) PMECC Error Location SIGMA 22 Register */ +#define REG_SMC_SIGMA23 (0xFFFFC584U) /**< \brief (SMC) PMECC Error Location SIGMA 23 Register */ +#define REG_SMC_SIGMA24 (0xFFFFC588U) /**< \brief (SMC) PMECC Error Location SIGMA 24 Register */ +#define REG_SMC_ERRLOC (0xFFFFC58CU) /**< \brief (SMC) PMECC Error Location 0 Register */ +#define REG_SMC_SETUP0 (0xFFFFC600U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (0xFFFFC604U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (0xFFFFC608U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (0xFFFFC60CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (0xFFFFC610U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (0xFFFFC614U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (0xFFFFC618U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (0xFFFFC61CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (0xFFFFC620U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (0xFFFFC624U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (0xFFFFC628U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (0xFFFFC62CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (0xFFFFC630U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (0xFFFFC634U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (0xFFFFC638U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (0xFFFFC63CU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (0xFFFFC640U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (0xFFFFC644U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (0xFFFFC648U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (0xFFFFC64CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_OCMS (0xFFFFC6A0U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (0xFFFFC6A4U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (0xFFFFC6A8U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (0xFFFFC6E4U) /**< \brief (SMC) SMC Write Protection Control Register */ +#define REG_SMC_WPSR (0xFFFFC6E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#else +#define REG_SMC_CFG (*(RwReg*)0xFFFFC000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (*(WoReg*)0xFFFFC004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (*(RoReg*)0xFFFFC008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (*(WoReg*)0xFFFFC00CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (*(WoReg*)0xFFFFC010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (*(RoReg*)0xFFFFC014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (*(RwReg*)0xFFFFC018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (*(RwReg*)0xFFFFC01CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (*(WoReg*)0xFFFFC020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (*(RwReg*)0xFFFFC024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (*(RoReg*)0xFFFFC028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (*(RoReg*)0xFFFFC02CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (*(RoReg*)0xFFFFC030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (*(RoReg*)0xFFFFC034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (*(RoReg*)0xFFFFC038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (*(RoReg*)0xFFFFC03CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (*(RoReg*)0xFFFFC040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (*(RoReg*)0xFFFFC044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (*(RoReg*)0xFFFFC048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (*(RoReg*)0xFFFFC04CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (*(RoReg*)0xFFFFC050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (*(RoReg*)0xFFFFC054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (*(RoReg*)0xFFFFC058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (*(RoReg*)0xFFFFC05CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (*(RoReg*)0xFFFFC060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (*(RoReg*)0xFFFFC064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (*(RoReg*)0xFFFFC068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (*(RoReg*)0xFFFFC06CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_PMECCFG (*(RwReg*)0xFFFFC070U) /**< \brief (SMC) PMECC Configuration Register */ +#define REG_SMC_PMECCSAREA (*(RwReg*)0xFFFFC074U) /**< \brief (SMC) PMECC Spare Area Size Register */ +#define REG_SMC_PMECCSADDR (*(RwReg*)0xFFFFC078U) /**< \brief (SMC) PMECC Start Address Register */ +#define REG_SMC_PMECCEADDR (*(RwReg*)0xFFFFC07CU) /**< \brief (SMC) PMECC End Address Register */ +#define REG_SMC_PMECCTRL (*(WoReg*)0xFFFFC084U) /**< \brief (SMC) PMECC Control Register */ +#define REG_SMC_PMECCSR (*(RoReg*)0xFFFFC088U) /**< \brief (SMC) PMECC Status Register */ +#define REG_SMC_PMECCIER (*(WoReg*)0xFFFFC08CU) /**< \brief (SMC) PMECC Interrupt Enable register */ +#define REG_SMC_PMECCIDR (*(WoReg*)0xFFFFC090U) /**< \brief (SMC) PMECC Interrupt Disable Register */ +#define REG_SMC_PMECCIMR (*(RoReg*)0xFFFFC094U) /**< \brief (SMC) PMECC Interrupt Mask Register */ +#define REG_SMC_PMECCISR (*(RoReg*)0xFFFFC098U) /**< \brief (SMC) PMECC Interrupt Status Register */ +#define REG_SMC_PMECC0_0 (*(RoReg*)0xFFFFC0B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 0) */ +#define REG_SMC_PMECC1_0 (*(RoReg*)0xFFFFC0B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 0) */ +#define REG_SMC_PMECC2_0 (*(RoReg*)0xFFFFC0B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 0) */ +#define REG_SMC_PMECC3_0 (*(RoReg*)0xFFFFC0BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 0) */ +#define REG_SMC_PMECC4_0 (*(RoReg*)0xFFFFC0C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 0) */ +#define REG_SMC_PMECC5_0 (*(RoReg*)0xFFFFC0C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 0) */ +#define REG_SMC_PMECC6_0 (*(RoReg*)0xFFFFC0C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 0) */ +#define REG_SMC_PMECC7_0 (*(RoReg*)0xFFFFC0CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 0) */ +#define REG_SMC_PMECC8_0 (*(RoReg*)0xFFFFC0D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 0) */ +#define REG_SMC_PMECC9_0 (*(RoReg*)0xFFFFC0D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 0) */ +#define REG_SMC_PMECC10_0 (*(RoReg*)0xFFFFC0D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 0) */ +#define REG_SMC_PMECC0_1 (*(RoReg*)0xFFFFC0F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 1) */ +#define REG_SMC_PMECC1_1 (*(RoReg*)0xFFFFC0F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 1) */ +#define REG_SMC_PMECC2_1 (*(RoReg*)0xFFFFC0F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 1) */ +#define REG_SMC_PMECC3_1 (*(RoReg*)0xFFFFC0FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 1) */ +#define REG_SMC_PMECC4_1 (*(RoReg*)0xFFFFC100U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 1) */ +#define REG_SMC_PMECC5_1 (*(RoReg*)0xFFFFC104U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 1) */ +#define REG_SMC_PMECC6_1 (*(RoReg*)0xFFFFC108U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 1) */ +#define REG_SMC_PMECC7_1 (*(RoReg*)0xFFFFC10CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 1) */ +#define REG_SMC_PMECC8_1 (*(RoReg*)0xFFFFC110U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 1) */ +#define REG_SMC_PMECC9_1 (*(RoReg*)0xFFFFC114U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 1) */ +#define REG_SMC_PMECC10_1 (*(RoReg*)0xFFFFC118U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 1) */ +#define REG_SMC_PMECC0_2 (*(RoReg*)0xFFFFC130U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 2) */ +#define REG_SMC_PMECC1_2 (*(RoReg*)0xFFFFC134U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 2) */ +#define REG_SMC_PMECC2_2 (*(RoReg*)0xFFFFC138U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 2) */ +#define REG_SMC_PMECC3_2 (*(RoReg*)0xFFFFC13CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 2) */ +#define REG_SMC_PMECC4_2 (*(RoReg*)0xFFFFC140U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 2) */ +#define REG_SMC_PMECC5_2 (*(RoReg*)0xFFFFC144U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 2) */ +#define REG_SMC_PMECC6_2 (*(RoReg*)0xFFFFC148U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 2) */ +#define REG_SMC_PMECC7_2 (*(RoReg*)0xFFFFC14CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 2) */ +#define REG_SMC_PMECC8_2 (*(RoReg*)0xFFFFC150U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 2) */ +#define REG_SMC_PMECC9_2 (*(RoReg*)0xFFFFC154U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 2) */ +#define REG_SMC_PMECC10_2 (*(RoReg*)0xFFFFC158U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 2) */ +#define REG_SMC_PMECC0_3 (*(RoReg*)0xFFFFC170U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 3) */ +#define REG_SMC_PMECC1_3 (*(RoReg*)0xFFFFC174U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 3) */ +#define REG_SMC_PMECC2_3 (*(RoReg*)0xFFFFC178U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 3) */ +#define REG_SMC_PMECC3_3 (*(RoReg*)0xFFFFC17CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 3) */ +#define REG_SMC_PMECC4_3 (*(RoReg*)0xFFFFC180U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 3) */ +#define REG_SMC_PMECC5_3 (*(RoReg*)0xFFFFC184U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 3) */ +#define REG_SMC_PMECC6_3 (*(RoReg*)0xFFFFC188U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 3) */ +#define REG_SMC_PMECC7_3 (*(RoReg*)0xFFFFC18CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 3) */ +#define REG_SMC_PMECC8_3 (*(RoReg*)0xFFFFC190U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 3) */ +#define REG_SMC_PMECC9_3 (*(RoReg*)0xFFFFC194U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 3) */ +#define REG_SMC_PMECC10_3 (*(RoReg*)0xFFFFC198U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 3) */ +#define REG_SMC_PMECC0_4 (*(RoReg*)0xFFFFC1B0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 4) */ +#define REG_SMC_PMECC1_4 (*(RoReg*)0xFFFFC1B4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 4) */ +#define REG_SMC_PMECC2_4 (*(RoReg*)0xFFFFC1B8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 4) */ +#define REG_SMC_PMECC3_4 (*(RoReg*)0xFFFFC1BCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 4) */ +#define REG_SMC_PMECC4_4 (*(RoReg*)0xFFFFC1C0U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 4) */ +#define REG_SMC_PMECC5_4 (*(RoReg*)0xFFFFC1C4U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 4) */ +#define REG_SMC_PMECC6_4 (*(RoReg*)0xFFFFC1C8U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 4) */ +#define REG_SMC_PMECC7_4 (*(RoReg*)0xFFFFC1CCU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 4) */ +#define REG_SMC_PMECC8_4 (*(RoReg*)0xFFFFC1D0U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 4) */ +#define REG_SMC_PMECC9_4 (*(RoReg*)0xFFFFC1D4U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 4) */ +#define REG_SMC_PMECC10_4 (*(RoReg*)0xFFFFC1D8U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 4) */ +#define REG_SMC_PMECC0_5 (*(RoReg*)0xFFFFC1F0U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 5) */ +#define REG_SMC_PMECC1_5 (*(RoReg*)0xFFFFC1F4U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 5) */ +#define REG_SMC_PMECC2_5 (*(RoReg*)0xFFFFC1F8U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 5) */ +#define REG_SMC_PMECC3_5 (*(RoReg*)0xFFFFC1FCU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 5) */ +#define REG_SMC_PMECC4_5 (*(RoReg*)0xFFFFC200U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 5) */ +#define REG_SMC_PMECC5_5 (*(RoReg*)0xFFFFC204U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 5) */ +#define REG_SMC_PMECC6_5 (*(RoReg*)0xFFFFC208U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 5) */ +#define REG_SMC_PMECC7_5 (*(RoReg*)0xFFFFC20CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 5) */ +#define REG_SMC_PMECC8_5 (*(RoReg*)0xFFFFC210U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 5) */ +#define REG_SMC_PMECC9_5 (*(RoReg*)0xFFFFC214U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 5) */ +#define REG_SMC_PMECC10_5 (*(RoReg*)0xFFFFC218U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 5) */ +#define REG_SMC_PMECC0_6 (*(RoReg*)0xFFFFC230U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 6) */ +#define REG_SMC_PMECC1_6 (*(RoReg*)0xFFFFC234U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 6) */ +#define REG_SMC_PMECC2_6 (*(RoReg*)0xFFFFC238U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 6) */ +#define REG_SMC_PMECC3_6 (*(RoReg*)0xFFFFC23CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 6) */ +#define REG_SMC_PMECC4_6 (*(RoReg*)0xFFFFC240U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 6) */ +#define REG_SMC_PMECC5_6 (*(RoReg*)0xFFFFC244U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 6) */ +#define REG_SMC_PMECC6_6 (*(RoReg*)0xFFFFC248U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 6) */ +#define REG_SMC_PMECC7_6 (*(RoReg*)0xFFFFC24CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 6) */ +#define REG_SMC_PMECC8_6 (*(RoReg*)0xFFFFC250U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 6) */ +#define REG_SMC_PMECC9_6 (*(RoReg*)0xFFFFC254U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 6) */ +#define REG_SMC_PMECC10_6 (*(RoReg*)0xFFFFC258U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 6) */ +#define REG_SMC_PMECC0_7 (*(RoReg*)0xFFFFC270U) /**< \brief (SMC) PMECC Redundancy 0 Register (sec_num = 7) */ +#define REG_SMC_PMECC1_7 (*(RoReg*)0xFFFFC274U) /**< \brief (SMC) PMECC Redundancy 1 Register (sec_num = 7) */ +#define REG_SMC_PMECC2_7 (*(RoReg*)0xFFFFC278U) /**< \brief (SMC) PMECC Redundancy 2 Register (sec_num = 7) */ +#define REG_SMC_PMECC3_7 (*(RoReg*)0xFFFFC27CU) /**< \brief (SMC) PMECC Redundancy 3 Register (sec_num = 7) */ +#define REG_SMC_PMECC4_7 (*(RoReg*)0xFFFFC280U) /**< \brief (SMC) PMECC Redundancy 4 Register (sec_num = 7) */ +#define REG_SMC_PMECC5_7 (*(RoReg*)0xFFFFC284U) /**< \brief (SMC) PMECC Redundancy 5 Register (sec_num = 7) */ +#define REG_SMC_PMECC6_7 (*(RoReg*)0xFFFFC288U) /**< \brief (SMC) PMECC Redundancy 6 Register (sec_num = 7) */ +#define REG_SMC_PMECC7_7 (*(RoReg*)0xFFFFC28CU) /**< \brief (SMC) PMECC Redundancy 7 Register (sec_num = 7) */ +#define REG_SMC_PMECC8_7 (*(RoReg*)0xFFFFC290U) /**< \brief (SMC) PMECC Redundancy 8 Register (sec_num = 7) */ +#define REG_SMC_PMECC9_7 (*(RoReg*)0xFFFFC294U) /**< \brief (SMC) PMECC Redundancy 9 Register (sec_num = 7) */ +#define REG_SMC_PMECC10_7 (*(RoReg*)0xFFFFC298U) /**< \brief (SMC) PMECC Redundancy 10 Register (sec_num = 7) */ +#define REG_SMC_REM0_0 (*(RoReg*)0xFFFFC2B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 0) */ +#define REG_SMC_REM1_0 (*(RoReg*)0xFFFFC2B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 0) */ +#define REG_SMC_REM2_0 (*(RoReg*)0xFFFFC2B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 0) */ +#define REG_SMC_REM3_0 (*(RoReg*)0xFFFFC2BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 0) */ +#define REG_SMC_REM4_0 (*(RoReg*)0xFFFFC2C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 0) */ +#define REG_SMC_REM5_0 (*(RoReg*)0xFFFFC2C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 0) */ +#define REG_SMC_REM6_0 (*(RoReg*)0xFFFFC2C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 0) */ +#define REG_SMC_REM7_0 (*(RoReg*)0xFFFFC2CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 0) */ +#define REG_SMC_REM8_0 (*(RoReg*)0xFFFFC2D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 0) */ +#define REG_SMC_REM9_0 (*(RoReg*)0xFFFFC2D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 0) */ +#define REG_SMC_REM10_0 (*(RoReg*)0xFFFFC2D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 0) */ +#define REG_SMC_REM11_0 (*(RoReg*)0xFFFFC2DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 0) */ +#define REG_SMC_REM0_1 (*(RoReg*)0xFFFFC2F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 1) */ +#define REG_SMC_REM1_1 (*(RoReg*)0xFFFFC2F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 1) */ +#define REG_SMC_REM2_1 (*(RoReg*)0xFFFFC2F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 1) */ +#define REG_SMC_REM3_1 (*(RoReg*)0xFFFFC2FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 1) */ +#define REG_SMC_REM4_1 (*(RoReg*)0xFFFFC300U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 1) */ +#define REG_SMC_REM5_1 (*(RoReg*)0xFFFFC304U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 1) */ +#define REG_SMC_REM6_1 (*(RoReg*)0xFFFFC308U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 1) */ +#define REG_SMC_REM7_1 (*(RoReg*)0xFFFFC30CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 1) */ +#define REG_SMC_REM8_1 (*(RoReg*)0xFFFFC310U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 1) */ +#define REG_SMC_REM9_1 (*(RoReg*)0xFFFFC314U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 1) */ +#define REG_SMC_REM10_1 (*(RoReg*)0xFFFFC318U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 1) */ +#define REG_SMC_REM11_1 (*(RoReg*)0xFFFFC31CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 1) */ +#define REG_SMC_REM0_2 (*(RoReg*)0xFFFFC330U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 2) */ +#define REG_SMC_REM1_2 (*(RoReg*)0xFFFFC334U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 2) */ +#define REG_SMC_REM2_2 (*(RoReg*)0xFFFFC338U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 2) */ +#define REG_SMC_REM3_2 (*(RoReg*)0xFFFFC33CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 2) */ +#define REG_SMC_REM4_2 (*(RoReg*)0xFFFFC340U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 2) */ +#define REG_SMC_REM5_2 (*(RoReg*)0xFFFFC344U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 2) */ +#define REG_SMC_REM6_2 (*(RoReg*)0xFFFFC348U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 2) */ +#define REG_SMC_REM7_2 (*(RoReg*)0xFFFFC34CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 2) */ +#define REG_SMC_REM8_2 (*(RoReg*)0xFFFFC350U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 2) */ +#define REG_SMC_REM9_2 (*(RoReg*)0xFFFFC354U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 2) */ +#define REG_SMC_REM10_2 (*(RoReg*)0xFFFFC358U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 2) */ +#define REG_SMC_REM11_2 (*(RoReg*)0xFFFFC35CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 2) */ +#define REG_SMC_REM0_3 (*(RoReg*)0xFFFFC370U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 3) */ +#define REG_SMC_REM1_3 (*(RoReg*)0xFFFFC374U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 3) */ +#define REG_SMC_REM2_3 (*(RoReg*)0xFFFFC378U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 3) */ +#define REG_SMC_REM3_3 (*(RoReg*)0xFFFFC37CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 3) */ +#define REG_SMC_REM4_3 (*(RoReg*)0xFFFFC380U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 3) */ +#define REG_SMC_REM5_3 (*(RoReg*)0xFFFFC384U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 3) */ +#define REG_SMC_REM6_3 (*(RoReg*)0xFFFFC388U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 3) */ +#define REG_SMC_REM7_3 (*(RoReg*)0xFFFFC38CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 3) */ +#define REG_SMC_REM8_3 (*(RoReg*)0xFFFFC390U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 3) */ +#define REG_SMC_REM9_3 (*(RoReg*)0xFFFFC394U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 3) */ +#define REG_SMC_REM10_3 (*(RoReg*)0xFFFFC398U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 3) */ +#define REG_SMC_REM11_3 (*(RoReg*)0xFFFFC39CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 3) */ +#define REG_SMC_REM0_4 (*(RoReg*)0xFFFFC3B0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 4) */ +#define REG_SMC_REM1_4 (*(RoReg*)0xFFFFC3B4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 4) */ +#define REG_SMC_REM2_4 (*(RoReg*)0xFFFFC3B8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 4) */ +#define REG_SMC_REM3_4 (*(RoReg*)0xFFFFC3BCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 4) */ +#define REG_SMC_REM4_4 (*(RoReg*)0xFFFFC3C0U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 4) */ +#define REG_SMC_REM5_4 (*(RoReg*)0xFFFFC3C4U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 4) */ +#define REG_SMC_REM6_4 (*(RoReg*)0xFFFFC3C8U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 4) */ +#define REG_SMC_REM7_4 (*(RoReg*)0xFFFFC3CCU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 4) */ +#define REG_SMC_REM8_4 (*(RoReg*)0xFFFFC3D0U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 4) */ +#define REG_SMC_REM9_4 (*(RoReg*)0xFFFFC3D4U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 4) */ +#define REG_SMC_REM10_4 (*(RoReg*)0xFFFFC3D8U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 4) */ +#define REG_SMC_REM11_4 (*(RoReg*)0xFFFFC3DCU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 4) */ +#define REG_SMC_REM0_5 (*(RoReg*)0xFFFFC3F0U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 5) */ +#define REG_SMC_REM1_5 (*(RoReg*)0xFFFFC3F4U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 5) */ +#define REG_SMC_REM2_5 (*(RoReg*)0xFFFFC3F8U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 5) */ +#define REG_SMC_REM3_5 (*(RoReg*)0xFFFFC3FCU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 5) */ +#define REG_SMC_REM4_5 (*(RoReg*)0xFFFFC400U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 5) */ +#define REG_SMC_REM5_5 (*(RoReg*)0xFFFFC404U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 5) */ +#define REG_SMC_REM6_5 (*(RoReg*)0xFFFFC408U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 5) */ +#define REG_SMC_REM7_5 (*(RoReg*)0xFFFFC40CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 5) */ +#define REG_SMC_REM8_5 (*(RoReg*)0xFFFFC410U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 5) */ +#define REG_SMC_REM9_5 (*(RoReg*)0xFFFFC414U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 5) */ +#define REG_SMC_REM10_5 (*(RoReg*)0xFFFFC418U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 5) */ +#define REG_SMC_REM11_5 (*(RoReg*)0xFFFFC41CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 5) */ +#define REG_SMC_REM0_6 (*(RoReg*)0xFFFFC430U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 6) */ +#define REG_SMC_REM1_6 (*(RoReg*)0xFFFFC434U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 6) */ +#define REG_SMC_REM2_6 (*(RoReg*)0xFFFFC438U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 6) */ +#define REG_SMC_REM3_6 (*(RoReg*)0xFFFFC43CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 6) */ +#define REG_SMC_REM4_6 (*(RoReg*)0xFFFFC440U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 6) */ +#define REG_SMC_REM5_6 (*(RoReg*)0xFFFFC444U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 6) */ +#define REG_SMC_REM6_6 (*(RoReg*)0xFFFFC448U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 6) */ +#define REG_SMC_REM7_6 (*(RoReg*)0xFFFFC44CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 6) */ +#define REG_SMC_REM8_6 (*(RoReg*)0xFFFFC450U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 6) */ +#define REG_SMC_REM9_6 (*(RoReg*)0xFFFFC454U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 6) */ +#define REG_SMC_REM10_6 (*(RoReg*)0xFFFFC458U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 6) */ +#define REG_SMC_REM11_6 (*(RoReg*)0xFFFFC45CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 6) */ +#define REG_SMC_REM0_7 (*(RoReg*)0xFFFFC470U) /**< \brief (SMC) PMECC Remainder 0 Register (sec_num = 7) */ +#define REG_SMC_REM1_7 (*(RoReg*)0xFFFFC474U) /**< \brief (SMC) PMECC Remainder 1 Register (sec_num = 7) */ +#define REG_SMC_REM2_7 (*(RoReg*)0xFFFFC478U) /**< \brief (SMC) PMECC Remainder 2 Register (sec_num = 7) */ +#define REG_SMC_REM3_7 (*(RoReg*)0xFFFFC47CU) /**< \brief (SMC) PMECC Remainder 3 Register (sec_num = 7) */ +#define REG_SMC_REM4_7 (*(RoReg*)0xFFFFC480U) /**< \brief (SMC) PMECC Remainder 4 Register (sec_num = 7) */ +#define REG_SMC_REM5_7 (*(RoReg*)0xFFFFC484U) /**< \brief (SMC) PMECC Remainder 5 Register (sec_num = 7) */ +#define REG_SMC_REM6_7 (*(RoReg*)0xFFFFC488U) /**< \brief (SMC) PMECC Remainder 6 Register (sec_num = 7) */ +#define REG_SMC_REM7_7 (*(RoReg*)0xFFFFC48CU) /**< \brief (SMC) PMECC Remainder 7 Register (sec_num = 7) */ +#define REG_SMC_REM8_7 (*(RoReg*)0xFFFFC490U) /**< \brief (SMC) PMECC Remainder 8 Register (sec_num = 7) */ +#define REG_SMC_REM9_7 (*(RoReg*)0xFFFFC494U) /**< \brief (SMC) PMECC Remainder 9 Register (sec_num = 7) */ +#define REG_SMC_REM10_7 (*(RoReg*)0xFFFFC498U) /**< \brief (SMC) PMECC Remainder 10 Register (sec_num = 7) */ +#define REG_SMC_REM11_7 (*(RoReg*)0xFFFFC49CU) /**< \brief (SMC) PMECC Remainder 11 Register (sec_num = 7) */ +#define REG_SMC_ELCFG (*(RwReg*)0xFFFFC500U) /**< \brief (SMC) PMECC Error Location Configuration Register */ +#define REG_SMC_ELPRIM (*(RoReg*)0xFFFFC504U) /**< \brief (SMC) PMECC Error Location Primitive Register */ +#define REG_SMC_ELEN (*(WoReg*)0xFFFFC508U) /**< \brief (SMC) PMECC Error Location Enable Register */ +#define REG_SMC_ELDIS (*(WoReg*)0xFFFFC50CU) /**< \brief (SMC) PMECC Error Location Disable Register */ +#define REG_SMC_ELSR (*(RoReg*)0xFFFFC510U) /**< \brief (SMC) PMECC Error Location Status Register */ +#define REG_SMC_ELIER (*(WoReg*)0xFFFFC514U) /**< \brief (SMC) PMECC Error Location Interrupt Enable register */ +#define REG_SMC_ELIDR (*(WoReg*)0xFFFFC518U) /**< \brief (SMC) PMECC Error Location Interrupt Disable Register */ +#define REG_SMC_ELIMR (*(RoReg*)0xFFFFC51CU) /**< \brief (SMC) PMECC Error Location Interrupt Mask Register */ +#define REG_SMC_ELISR (*(RoReg*)0xFFFFC520U) /**< \brief (SMC) PMECC Error Location Interrupt Status Register */ +#define REG_SMC_SIGMA0 (*(RwReg*)0xFFFFC528U) /**< \brief (SMC) PMECC Error Location SIGMA 0 Register */ +#define REG_SMC_SIGMA1 (*(RwReg*)0xFFFFC52CU) /**< \brief (SMC) PMECC Error Location SIGMA 1 Register */ +#define REG_SMC_SIGMA2 (*(RwReg*)0xFFFFC530U) /**< \brief (SMC) PMECC Error Location SIGMA 2 Register */ +#define REG_SMC_SIGMA3 (*(RwReg*)0xFFFFC534U) /**< \brief (SMC) PMECC Error Location SIGMA 3 Register */ +#define REG_SMC_SIGMA4 (*(RwReg*)0xFFFFC538U) /**< \brief (SMC) PMECC Error Location SIGMA 4 Register */ +#define REG_SMC_SIGMA5 (*(RwReg*)0xFFFFC53CU) /**< \brief (SMC) PMECC Error Location SIGMA 5 Register */ +#define REG_SMC_SIGMA6 (*(RwReg*)0xFFFFC540U) /**< \brief (SMC) PMECC Error Location SIGMA 6 Register */ +#define REG_SMC_SIGMA7 (*(RwReg*)0xFFFFC544U) /**< \brief (SMC) PMECC Error Location SIGMA 7 Register */ +#define REG_SMC_SIGMA8 (*(RwReg*)0xFFFFC548U) /**< \brief (SMC) PMECC Error Location SIGMA 8 Register */ +#define REG_SMC_SIGMA9 (*(RwReg*)0xFFFFC54CU) /**< \brief (SMC) PMECC Error Location SIGMA 9 Register */ +#define REG_SMC_SIGMA10 (*(RwReg*)0xFFFFC550U) /**< \brief (SMC) PMECC Error Location SIGMA 10 Register */ +#define REG_SMC_SIGMA11 (*(RwReg*)0xFFFFC554U) /**< \brief (SMC) PMECC Error Location SIGMA 11 Register */ +#define REG_SMC_SIGMA12 (*(RwReg*)0xFFFFC558U) /**< \brief (SMC) PMECC Error Location SIGMA 12 Register */ +#define REG_SMC_SIGMA13 (*(RwReg*)0xFFFFC55CU) /**< \brief (SMC) PMECC Error Location SIGMA 13 Register */ +#define REG_SMC_SIGMA14 (*(RwReg*)0xFFFFC560U) /**< \brief (SMC) PMECC Error Location SIGMA 14 Register */ +#define REG_SMC_SIGMA15 (*(RwReg*)0xFFFFC564U) /**< \brief (SMC) PMECC Error Location SIGMA 15 Register */ +#define REG_SMC_SIGMA16 (*(RwReg*)0xFFFFC568U) /**< \brief (SMC) PMECC Error Location SIGMA 16 Register */ +#define REG_SMC_SIGMA17 (*(RwReg*)0xFFFFC56CU) /**< \brief (SMC) PMECC Error Location SIGMA 17 Register */ +#define REG_SMC_SIGMA18 (*(RwReg*)0xFFFFC570U) /**< \brief (SMC) PMECC Error Location SIGMA 18 Register */ +#define REG_SMC_SIGMA19 (*(RwReg*)0xFFFFC574U) /**< \brief (SMC) PMECC Error Location SIGMA 19 Register */ +#define REG_SMC_SIGMA20 (*(RwReg*)0xFFFFC578U) /**< \brief (SMC) PMECC Error Location SIGMA 20 Register */ +#define REG_SMC_SIGMA21 (*(RwReg*)0xFFFFC57CU) /**< \brief (SMC) PMECC Error Location SIGMA 21 Register */ +#define REG_SMC_SIGMA22 (*(RwReg*)0xFFFFC580U) /**< \brief (SMC) PMECC Error Location SIGMA 22 Register */ +#define REG_SMC_SIGMA23 (*(RwReg*)0xFFFFC584U) /**< \brief (SMC) PMECC Error Location SIGMA 23 Register */ +#define REG_SMC_SIGMA24 (*(RwReg*)0xFFFFC588U) /**< \brief (SMC) PMECC Error Location SIGMA 24 Register */ +#define REG_SMC_ERRLOC (*(RoReg*)0xFFFFC58CU) /**< \brief (SMC) PMECC Error Location 0 Register */ +#define REG_SMC_SETUP0 (*(RwReg*)0xFFFFC600U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (*(RwReg*)0xFFFFC604U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (*(RwReg*)0xFFFFC608U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (*(RwReg*)0xFFFFC60CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (*(RwReg*)0xFFFFC610U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (*(RwReg*)0xFFFFC614U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (*(RwReg*)0xFFFFC618U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (*(RwReg*)0xFFFFC61CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (*(RwReg*)0xFFFFC620U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (*(RwReg*)0xFFFFC624U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (*(RwReg*)0xFFFFC628U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (*(RwReg*)0xFFFFC62CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (*(RwReg*)0xFFFFC630U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (*(RwReg*)0xFFFFC634U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (*(RwReg*)0xFFFFC638U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (*(RwReg*)0xFFFFC63CU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (*(RwReg*)0xFFFFC640U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (*(RwReg*)0xFFFFC644U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (*(RwReg*)0xFFFFC648U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (*(RwReg*)0xFFFFC64CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_OCMS (*(RwReg*)0xFFFFC6A0U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (*(WoReg*)0xFFFFC6A4U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (*(WoReg*)0xFFFFC6A8U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (*(WoReg*)0xFFFFC6E4U) /**< \brief (SMC) SMC Write Protection Control Register */ +#define REG_SMC_WPSR (*(RoReg*)0xFFFFC6E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smd.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_smd.h new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi0.h new file mode 100644 index 000000000..e917fb5ef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi0.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SPI0_INSTANCE_ +#define _SAMA5_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI0_CR (0xF0004000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (0xF0004004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (0xF0004008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (0xF000400CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (0xF0004010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (0xF0004014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (0xF0004018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (0xF000401CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (0xF0004030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (0xF00040E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (0xF00040E8U) /**< \brief (SPI0) Write Protection Status Register */ +#else +#define REG_SPI0_CR (*(WoReg*)0xF0004000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (*(RwReg*)0xF0004004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (*(RoReg*)0xF0004008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (*(WoReg*)0xF000400CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (*(RoReg*)0xF0004010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (*(WoReg*)0xF0004014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (*(WoReg*)0xF0004018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (*(RoReg*)0xF000401CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (*(RwReg*)0xF0004030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (*(RwReg*)0xF00040E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (*(RoReg*)0xF00040E8U) /**< \brief (SPI0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SPI0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi1.h new file mode 100644 index 000000000..cce19b601 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_spi1.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SPI1_INSTANCE_ +#define _SAMA5_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI1_CR (0xF8008000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (0xF8008004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (0xF8008008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (0xF800800CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (0xF8008010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (0xF8008014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (0xF8008018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (0xF800801CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (0xF8008030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (0xF80080E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (0xF80080E8U) /**< \brief (SPI1) Write Protection Status Register */ +#else +#define REG_SPI1_CR (*(WoReg*)0xF8008000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (*(RwReg*)0xF8008004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (*(RoReg*)0xF8008008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (*(WoReg*)0xF800800CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (*(RoReg*)0xF8008010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (*(WoReg*)0xF8008014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (*(WoReg*)0xF8008018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (*(RoReg*)0xF800801CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (*(RwReg*)0xF8008030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (*(RwReg*)0xF80080E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (*(RoReg*)0xF80080E8U) /**< \brief (SPI1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SPI1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc0.h new file mode 100644 index 000000000..9e721e2b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc0.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SSC0_INSTANCE_ +#define _SAMA5_SSC0_INSTANCE_ + +/* ========== Register definition for SSC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC0_CR (0xF0008000U) /**< \brief (SSC0) Control Register */ +#define REG_SSC0_CMR (0xF0008004U) /**< \brief (SSC0) Clock Mode Register */ +#define REG_SSC0_RCMR (0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */ +#define REG_SSC0_RFMR (0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */ +#define REG_SSC0_TCMR (0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */ +#define REG_SSC0_TFMR (0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */ +#define REG_SSC0_RHR (0xF0008020U) /**< \brief (SSC0) Receive Holding Register */ +#define REG_SSC0_THR (0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */ +#define REG_SSC0_RSHR (0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */ +#define REG_SSC0_TSHR (0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */ +#define REG_SSC0_RC0R (0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */ +#define REG_SSC0_RC1R (0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */ +#define REG_SSC0_SR (0xF0008040U) /**< \brief (SSC0) Status Register */ +#define REG_SSC0_IER (0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */ +#define REG_SSC0_IDR (0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */ +#define REG_SSC0_IMR (0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */ +#define REG_SSC0_WPMR (0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */ +#define REG_SSC0_WPSR (0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */ +#else +#define REG_SSC0_CR (*(WoReg*)0xF0008000U) /**< \brief (SSC0) Control Register */ +#define REG_SSC0_CMR (*(RwReg*)0xF0008004U) /**< \brief (SSC0) Clock Mode Register */ +#define REG_SSC0_RCMR (*(RwReg*)0xF0008010U) /**< \brief (SSC0) Receive Clock Mode Register */ +#define REG_SSC0_RFMR (*(RwReg*)0xF0008014U) /**< \brief (SSC0) Receive Frame Mode Register */ +#define REG_SSC0_TCMR (*(RwReg*)0xF0008018U) /**< \brief (SSC0) Transmit Clock Mode Register */ +#define REG_SSC0_TFMR (*(RwReg*)0xF000801CU) /**< \brief (SSC0) Transmit Frame Mode Register */ +#define REG_SSC0_RHR (*(RoReg*)0xF0008020U) /**< \brief (SSC0) Receive Holding Register */ +#define REG_SSC0_THR (*(WoReg*)0xF0008024U) /**< \brief (SSC0) Transmit Holding Register */ +#define REG_SSC0_RSHR (*(RoReg*)0xF0008030U) /**< \brief (SSC0) Receive Sync. Holding Register */ +#define REG_SSC0_TSHR (*(RwReg*)0xF0008034U) /**< \brief (SSC0) Transmit Sync. Holding Register */ +#define REG_SSC0_RC0R (*(RwReg*)0xF0008038U) /**< \brief (SSC0) Receive Compare 0 Register */ +#define REG_SSC0_RC1R (*(RwReg*)0xF000803CU) /**< \brief (SSC0) Receive Compare 1 Register */ +#define REG_SSC0_SR (*(RoReg*)0xF0008040U) /**< \brief (SSC0) Status Register */ +#define REG_SSC0_IER (*(WoReg*)0xF0008044U) /**< \brief (SSC0) Interrupt Enable Register */ +#define REG_SSC0_IDR (*(WoReg*)0xF0008048U) /**< \brief (SSC0) Interrupt Disable Register */ +#define REG_SSC0_IMR (*(RoReg*)0xF000804CU) /**< \brief (SSC0) Interrupt Mask Register */ +#define REG_SSC0_WPMR (*(RwReg*)0xF00080E4U) /**< \brief (SSC0) Write Protect Mode Register */ +#define REG_SSC0_WPSR (*(RoReg*)0xF00080E8U) /**< \brief (SSC0) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SSC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc1.h new file mode 100644 index 000000000..7046fa4d6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_ssc1.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_SSC1_INSTANCE_ +#define _SAMA5_SSC1_INSTANCE_ + +/* ========== Register definition for SSC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC1_CR (0xF800C000U) /**< \brief (SSC1) Control Register */ +#define REG_SSC1_CMR (0xF800C004U) /**< \brief (SSC1) Clock Mode Register */ +#define REG_SSC1_RCMR (0xF800C010U) /**< \brief (SSC1) Receive Clock Mode Register */ +#define REG_SSC1_RFMR (0xF800C014U) /**< \brief (SSC1) Receive Frame Mode Register */ +#define REG_SSC1_TCMR (0xF800C018U) /**< \brief (SSC1) Transmit Clock Mode Register */ +#define REG_SSC1_TFMR (0xF800C01CU) /**< \brief (SSC1) Transmit Frame Mode Register */ +#define REG_SSC1_RHR (0xF800C020U) /**< \brief (SSC1) Receive Holding Register */ +#define REG_SSC1_THR (0xF800C024U) /**< \brief (SSC1) Transmit Holding Register */ +#define REG_SSC1_RSHR (0xF800C030U) /**< \brief (SSC1) Receive Sync. Holding Register */ +#define REG_SSC1_TSHR (0xF800C034U) /**< \brief (SSC1) Transmit Sync. Holding Register */ +#define REG_SSC1_RC0R (0xF800C038U) /**< \brief (SSC1) Receive Compare 0 Register */ +#define REG_SSC1_RC1R (0xF800C03CU) /**< \brief (SSC1) Receive Compare 1 Register */ +#define REG_SSC1_SR (0xF800C040U) /**< \brief (SSC1) Status Register */ +#define REG_SSC1_IER (0xF800C044U) /**< \brief (SSC1) Interrupt Enable Register */ +#define REG_SSC1_IDR (0xF800C048U) /**< \brief (SSC1) Interrupt Disable Register */ +#define REG_SSC1_IMR (0xF800C04CU) /**< \brief (SSC1) Interrupt Mask Register */ +#define REG_SSC1_WPMR (0xF800C0E4U) /**< \brief (SSC1) Write Protect Mode Register */ +#define REG_SSC1_WPSR (0xF800C0E8U) /**< \brief (SSC1) Write Protect Status Register */ +#else +#define REG_SSC1_CR (*(WoReg*)0xF800C000U) /**< \brief (SSC1) Control Register */ +#define REG_SSC1_CMR (*(RwReg*)0xF800C004U) /**< \brief (SSC1) Clock Mode Register */ +#define REG_SSC1_RCMR (*(RwReg*)0xF800C010U) /**< \brief (SSC1) Receive Clock Mode Register */ +#define REG_SSC1_RFMR (*(RwReg*)0xF800C014U) /**< \brief (SSC1) Receive Frame Mode Register */ +#define REG_SSC1_TCMR (*(RwReg*)0xF800C018U) /**< \brief (SSC1) Transmit Clock Mode Register */ +#define REG_SSC1_TFMR (*(RwReg*)0xF800C01CU) /**< \brief (SSC1) Transmit Frame Mode Register */ +#define REG_SSC1_RHR (*(RoReg*)0xF800C020U) /**< \brief (SSC1) Receive Holding Register */ +#define REG_SSC1_THR (*(WoReg*)0xF800C024U) /**< \brief (SSC1) Transmit Holding Register */ +#define REG_SSC1_RSHR (*(RoReg*)0xF800C030U) /**< \brief (SSC1) Receive Sync. Holding Register */ +#define REG_SSC1_TSHR (*(RwReg*)0xF800C034U) /**< \brief (SSC1) Transmit Sync. Holding Register */ +#define REG_SSC1_RC0R (*(RwReg*)0xF800C038U) /**< \brief (SSC1) Receive Compare 0 Register */ +#define REG_SSC1_RC1R (*(RwReg*)0xF800C03CU) /**< \brief (SSC1) Receive Compare 1 Register */ +#define REG_SSC1_SR (*(RoReg*)0xF800C040U) /**< \brief (SSC1) Status Register */ +#define REG_SSC1_IER (*(WoReg*)0xF800C044U) /**< \brief (SSC1) Interrupt Enable Register */ +#define REG_SSC1_IDR (*(WoReg*)0xF800C048U) /**< \brief (SSC1) Interrupt Disable Register */ +#define REG_SSC1_IMR (*(RoReg*)0xF800C04CU) /**< \brief (SSC1) Interrupt Mask Register */ +#define REG_SSC1_WPMR (*(RwReg*)0xF800C0E4U) /**< \brief (SSC1) Write Protect Mode Register */ +#define REG_SSC1_WPSR (*(RoReg*)0xF800C0E8U) /**< \brief (SSC1) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_SSC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc0.h new file mode 100644 index 000000000..8b926fee3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc0.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TC0_INSTANCE_ +#define _SAMA5_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CCR0 (0xF0010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (0xF0010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_RAB0 (0xF001000CU) /**< \brief (TC0) Register AB (channel = 0) */ +#define REG_TC0_CV0 (0xF0010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (0xF0010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (0xF0010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (0xF001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (0xF0010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (0xF0010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (0xF0010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (0xF001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (0xF0010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (0xF0010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_RAB1 (0xF001004CU) /**< \brief (TC0) Register AB (channel = 1) */ +#define REG_TC0_CV1 (0xF0010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (0xF0010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (0xF0010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (0xF001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (0xF0010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (0xF0010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (0xF0010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (0xF001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (0xF0010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (0xF0010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_RAB2 (0xF001008CU) /**< \brief (TC0) Register AB (channel = 2) */ +#define REG_TC0_CV2 (0xF0010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (0xF0010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (0xF0010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (0xF001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (0xF00100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (0xF00100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (0xF00100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (0xF00100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (0xF00100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (0xF00100C4U) /**< \brief (TC0) Block Mode Register */ +#else +#define REG_TC0_CCR0 (*(WoReg*)0xF0010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (*(RwReg*)0xF0010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_RAB0 (*(RoReg*)0xF001000CU) /**< \brief (TC0) Register AB (channel = 0) */ +#define REG_TC0_CV0 (*(RoReg*)0xF0010010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (*(RwReg*)0xF0010014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (*(RwReg*)0xF0010018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (*(RwReg*)0xF001001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (*(RoReg*)0xF0010020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (*(WoReg*)0xF0010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (*(WoReg*)0xF0010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (*(RoReg*)0xF001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (*(WoReg*)0xF0010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (*(RwReg*)0xF0010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_RAB1 (*(RoReg*)0xF001004CU) /**< \brief (TC0) Register AB (channel = 1) */ +#define REG_TC0_CV1 (*(RoReg*)0xF0010050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (*(RwReg*)0xF0010054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (*(RwReg*)0xF0010058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (*(RwReg*)0xF001005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (*(RoReg*)0xF0010060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (*(WoReg*)0xF0010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (*(WoReg*)0xF0010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (*(RoReg*)0xF001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (*(WoReg*)0xF0010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (*(RwReg*)0xF0010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_RAB2 (*(RoReg*)0xF001008CU) /**< \brief (TC0) Register AB (channel = 2) */ +#define REG_TC0_CV2 (*(RoReg*)0xF0010090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (*(RwReg*)0xF0010094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (*(RwReg*)0xF0010098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (*(RwReg*)0xF001009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (*(RoReg*)0xF00100A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (*(WoReg*)0xF00100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (*(WoReg*)0xF00100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (*(RoReg*)0xF00100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (*(WoReg*)0xF00100C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (*(RwReg*)0xF00100C4U) /**< \brief (TC0) Block Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc1.h new file mode 100644 index 000000000..ef00b12f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tc1.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TC1_INSTANCE_ +#define _SAMA5_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CCR0 (0xF8014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (0xF8014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_RAB0 (0xF801400CU) /**< \brief (TC1) Register AB (channel = 0) */ +#define REG_TC1_CV0 (0xF8014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (0xF8014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (0xF8014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (0xF801401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (0xF8014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (0xF8014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (0xF8014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (0xF801402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (0xF8014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (0xF8014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_RAB1 (0xF801404CU) /**< \brief (TC1) Register AB (channel = 1) */ +#define REG_TC1_CV1 (0xF8014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (0xF8014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (0xF8014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (0xF801405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (0xF8014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (0xF8014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (0xF8014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (0xF801406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (0xF8014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (0xF8014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_RAB2 (0xF801408CU) /**< \brief (TC1) Register AB (channel = 2) */ +#define REG_TC1_CV2 (0xF8014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (0xF8014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (0xF8014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (0xF801409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (0xF80140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (0xF80140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (0xF80140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (0xF80140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (0xF80140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (0xF80140C4U) /**< \brief (TC1) Block Mode Register */ +#else +#define REG_TC1_CCR0 (*(WoReg*)0xF8014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (*(RwReg*)0xF8014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_RAB0 (*(RoReg*)0xF801400CU) /**< \brief (TC1) Register AB (channel = 0) */ +#define REG_TC1_CV0 (*(RoReg*)0xF8014010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (*(RwReg*)0xF8014014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (*(RwReg*)0xF8014018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (*(RwReg*)0xF801401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (*(RoReg*)0xF8014020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (*(WoReg*)0xF8014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (*(WoReg*)0xF8014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (*(RoReg*)0xF801402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (*(WoReg*)0xF8014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (*(RwReg*)0xF8014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_RAB1 (*(RoReg*)0xF801404CU) /**< \brief (TC1) Register AB (channel = 1) */ +#define REG_TC1_CV1 (*(RoReg*)0xF8014050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (*(RwReg*)0xF8014054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (*(RwReg*)0xF8014058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (*(RwReg*)0xF801405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (*(RoReg*)0xF8014060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (*(WoReg*)0xF8014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (*(WoReg*)0xF8014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (*(RoReg*)0xF801406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (*(WoReg*)0xF8014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (*(RwReg*)0xF8014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_RAB2 (*(RoReg*)0xF801408CU) /**< \brief (TC1) Register AB (channel = 2) */ +#define REG_TC1_CV2 (*(RoReg*)0xF8014090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (*(RwReg*)0xF8014094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (*(RwReg*)0xF8014098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (*(RwReg*)0xF801409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (*(RoReg*)0xF80140A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (*(WoReg*)0xF80140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (*(WoReg*)0xF80140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (*(RoReg*)0xF80140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (*(WoReg*)0xF80140C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (*(RwReg*)0xF80140C4U) /**< \brief (TC1) Block Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tdes.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tdes.h new file mode 100644 index 000000000..c3add8c89 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_tdes.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TDES_INSTANCE_ +#define _SAMA5_TDES_INSTANCE_ + +/* ========== Register definition for TDES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TDES_CR (0xF803C000U) /**< \brief (TDES) Control Register */ +#define REG_TDES_MR (0xF803C004U) /**< \brief (TDES) Mode Register */ +#define REG_TDES_IER (0xF803C010U) /**< \brief (TDES) Interrupt Enable Register */ +#define REG_TDES_IDR (0xF803C014U) /**< \brief (TDES) Interrupt Disable Register */ +#define REG_TDES_IMR (0xF803C018U) /**< \brief (TDES) Interrupt Mask Register */ +#define REG_TDES_ISR (0xF803C01CU) /**< \brief (TDES) Interrupt Status Register */ +#define REG_TDES_KEY1WR (0xF803C020U) /**< \brief (TDES) Key 1 Word Register */ +#define REG_TDES_KEY2WR (0xF803C028U) /**< \brief (TDES) Key 2 Word Register */ +#define REG_TDES_KEY3WR (0xF803C030U) /**< \brief (TDES) Key 3 Word Register */ +#define REG_TDES_IDATAR (0xF803C040U) /**< \brief (TDES) Input Data Register */ +#define REG_TDES_ODATAR (0xF803C050U) /**< \brief (TDES) Output Data Register */ +#define REG_TDES_IVR (0xF803C060U) /**< \brief (TDES) Initialization Vector Register */ +#define REG_TDES_XTEARNDR (0xF803C070U) /**< \brief (TDES) XTEA Rounds Register */ +#else +#define REG_TDES_CR (*(WoReg*)0xF803C000U) /**< \brief (TDES) Control Register */ +#define REG_TDES_MR (*(RwReg*)0xF803C004U) /**< \brief (TDES) Mode Register */ +#define REG_TDES_IER (*(WoReg*)0xF803C010U) /**< \brief (TDES) Interrupt Enable Register */ +#define REG_TDES_IDR (*(WoReg*)0xF803C014U) /**< \brief (TDES) Interrupt Disable Register */ +#define REG_TDES_IMR (*(RoReg*)0xF803C018U) /**< \brief (TDES) Interrupt Mask Register */ +#define REG_TDES_ISR (*(RoReg*)0xF803C01CU) /**< \brief (TDES) Interrupt Status Register */ +#define REG_TDES_KEY1WR (*(WoReg*)0xF803C020U) /**< \brief (TDES) Key 1 Word Register */ +#define REG_TDES_KEY2WR (*(WoReg*)0xF803C028U) /**< \brief (TDES) Key 2 Word Register */ +#define REG_TDES_KEY3WR (*(WoReg*)0xF803C030U) /**< \brief (TDES) Key 3 Word Register */ +#define REG_TDES_IDATAR (*(WoReg*)0xF803C040U) /**< \brief (TDES) Input Data Register */ +#define REG_TDES_ODATAR (*(RoReg*)0xF803C050U) /**< \brief (TDES) Output Data Register */ +#define REG_TDES_IVR (*(WoReg*)0xF803C060U) /**< \brief (TDES) Initialization Vector Register */ +#define REG_TDES_XTEARNDR (*(RwReg*)0xF803C070U) /**< \brief (TDES) XTEA Rounds Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TDES_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_trng.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_trng.h new file mode 100644 index 000000000..8730a0a31 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TRNG_INSTANCE_ +#define _SAMA5_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CR (0xF8040000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (0xF8040010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (0xF8040014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (0xF8040018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (0xF804001CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (0xF8040050U) /**< \brief (TRNG) Output Data Register */ +#else +#define REG_TRNG_CR (*(WoReg*)0xF8040000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (*(WoReg*)0xF8040010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (*(WoReg*)0xF8040014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (*(RoReg*)0xF8040018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (*(RoReg*)0xF804001CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (*(RoReg*)0xF8040050U) /**< \brief (TRNG) Output Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TRNG_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi0.h new file mode 100644 index 000000000..652561ef0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi0.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI0_INSTANCE_ +#define _SAMA5_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI0_CR (0xF0014000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (0xF0014004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (0xF0014008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (0xF001400CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (0xF0014010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (0xF0014020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (0xF0014024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (0xF0014028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (0xF001402CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (0xF0014030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (0xF0014034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_WPROT_MODE (0xF00140E4U) /**< \brief (TWI0) Protection Mode Register */ +#define REG_TWI0_WPROT_STATUS (0xF00140E8U) /**< \brief (TWI0) Protection Status Register */ +#else +#define REG_TWI0_CR (*(WoReg*)0xF0014000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (*(RwReg*)0xF0014004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (*(RwReg*)0xF0014008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (*(RwReg*)0xF001400CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (*(RwReg*)0xF0014010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (*(RoReg*)0xF0014020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (*(WoReg*)0xF0014024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (*(WoReg*)0xF0014028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (*(RoReg*)0xF001402CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (*(RoReg*)0xF0014030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (*(WoReg*)0xF0014034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_WPROT_MODE (*(RwReg*)0xF00140E4U) /**< \brief (TWI0) Protection Mode Register */ +#define REG_TWI0_WPROT_STATUS (*(RoReg*)0xF00140E8U) /**< \brief (TWI0) Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TWI0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi1.h new file mode 100644 index 000000000..2aca8afc3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi1.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI1_INSTANCE_ +#define _SAMA5_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI1_CR (0xF0018000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (0xF0018004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (0xF0018008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (0xF001800CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (0xF0018010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (0xF0018020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (0xF0018024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (0xF0018028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (0xF001802CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (0xF0018030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (0xF0018034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_WPROT_MODE (0xF00180E4U) /**< \brief (TWI1) Protection Mode Register */ +#define REG_TWI1_WPROT_STATUS (0xF00180E8U) /**< \brief (TWI1) Protection Status Register */ +#else +#define REG_TWI1_CR (*(WoReg*)0xF0018000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (*(RwReg*)0xF0018004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (*(RwReg*)0xF0018008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (*(RwReg*)0xF001800CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (*(RwReg*)0xF0018010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (*(RoReg*)0xF0018020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (*(WoReg*)0xF0018024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (*(WoReg*)0xF0018028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (*(RoReg*)0xF001802CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (*(RoReg*)0xF0018030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (*(WoReg*)0xF0018034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_WPROT_MODE (*(RwReg*)0xF00180E4U) /**< \brief (TWI1) Protection Mode Register */ +#define REG_TWI1_WPROT_STATUS (*(RoReg*)0xF00180E8U) /**< \brief (TWI1) Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TWI1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi2.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi2.h new file mode 100644 index 000000000..5fccf8321 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_twi2.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_TWI2_INSTANCE_ +#define _SAMA5_TWI2_INSTANCE_ + +/* ========== Register definition for TWI2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI2_CR (0xF801C000U) /**< \brief (TWI2) Control Register */ +#define REG_TWI2_MMR (0xF801C004U) /**< \brief (TWI2) Master Mode Register */ +#define REG_TWI2_SMR (0xF801C008U) /**< \brief (TWI2) Slave Mode Register */ +#define REG_TWI2_IADR (0xF801C00CU) /**< \brief (TWI2) Internal Address Register */ +#define REG_TWI2_CWGR (0xF801C010U) /**< \brief (TWI2) Clock Waveform Generator Register */ +#define REG_TWI2_SR (0xF801C020U) /**< \brief (TWI2) Status Register */ +#define REG_TWI2_IER (0xF801C024U) /**< \brief (TWI2) Interrupt Enable Register */ +#define REG_TWI2_IDR (0xF801C028U) /**< \brief (TWI2) Interrupt Disable Register */ +#define REG_TWI2_IMR (0xF801C02CU) /**< \brief (TWI2) Interrupt Mask Register */ +#define REG_TWI2_RHR (0xF801C030U) /**< \brief (TWI2) Receive Holding Register */ +#define REG_TWI2_THR (0xF801C034U) /**< \brief (TWI2) Transmit Holding Register */ +#define REG_TWI2_WPROT_MODE (0xF801C0E4U) /**< \brief (TWI2) Protection Mode Register */ +#define REG_TWI2_WPROT_STATUS (0xF801C0E8U) /**< \brief (TWI2) Protection Status Register */ +#else +#define REG_TWI2_CR (*(WoReg*)0xF801C000U) /**< \brief (TWI2) Control Register */ +#define REG_TWI2_MMR (*(RwReg*)0xF801C004U) /**< \brief (TWI2) Master Mode Register */ +#define REG_TWI2_SMR (*(RwReg*)0xF801C008U) /**< \brief (TWI2) Slave Mode Register */ +#define REG_TWI2_IADR (*(RwReg*)0xF801C00CU) /**< \brief (TWI2) Internal Address Register */ +#define REG_TWI2_CWGR (*(RwReg*)0xF801C010U) /**< \brief (TWI2) Clock Waveform Generator Register */ +#define REG_TWI2_SR (*(RoReg*)0xF801C020U) /**< \brief (TWI2) Status Register */ +#define REG_TWI2_IER (*(WoReg*)0xF801C024U) /**< \brief (TWI2) Interrupt Enable Register */ +#define REG_TWI2_IDR (*(WoReg*)0xF801C028U) /**< \brief (TWI2) Interrupt Disable Register */ +#define REG_TWI2_IMR (*(RoReg*)0xF801C02CU) /**< \brief (TWI2) Interrupt Mask Register */ +#define REG_TWI2_RHR (*(RoReg*)0xF801C030U) /**< \brief (TWI2) Receive Holding Register */ +#define REG_TWI2_THR (*(WoReg*)0xF801C034U) /**< \brief (TWI2) Transmit Holding Register */ +#define REG_TWI2_WPROT_MODE (*(RwReg*)0xF801C0E4U) /**< \brief (TWI2) Protection Mode Register */ +#define REG_TWI2_WPROT_STATUS (*(RoReg*)0xF801C0E8U) /**< \brief (TWI2) Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_TWI2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart0.h new file mode 100644 index 000000000..4df6164d5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart0.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UART0_INSTANCE_ +#define _SAMA5_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART0_CR (0xF0024000U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR (0xF0024004U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER (0xF0024008U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR (0xF002400CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR (0xF0024010U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR (0xF0024014U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR (0xF0024018U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR (0xF002401CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR (0xF0024020U) /**< \brief (UART0) Baud Rate Generator Register */ +#else +#define REG_UART0_CR (*(WoReg*)0xF0024000U) /**< \brief (UART0) Control Register */ +#define REG_UART0_MR (*(RwReg*)0xF0024004U) /**< \brief (UART0) Mode Register */ +#define REG_UART0_IER (*(WoReg*)0xF0024008U) /**< \brief (UART0) Interrupt Enable Register */ +#define REG_UART0_IDR (*(WoReg*)0xF002400CU) /**< \brief (UART0) Interrupt Disable Register */ +#define REG_UART0_IMR (*(RoReg*)0xF0024010U) /**< \brief (UART0) Interrupt Mask Register */ +#define REG_UART0_SR (*(RoReg*)0xF0024014U) /**< \brief (UART0) Status Register */ +#define REG_UART0_RHR (*(RoReg*)0xF0024018U) /**< \brief (UART0) Receive Holding Register */ +#define REG_UART0_THR (*(WoReg*)0xF002401CU) /**< \brief (UART0) Transmit Holding Register */ +#define REG_UART0_BRGR (*(RwReg*)0xF0024020U) /**< \brief (UART0) Baud Rate Generator Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_UART0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart1.h new file mode 100644 index 000000000..84a188f14 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_uart1.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UART1_INSTANCE_ +#define _SAMA5_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART1_CR (0xF8028000U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR (0xF8028004U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER (0xF8028008U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR (0xF802800CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR (0xF8028010U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR (0xF8028014U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR (0xF8028018U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR (0xF802801CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR (0xF8028020U) /**< \brief (UART1) Baud Rate Generator Register */ +#else +#define REG_UART1_CR (*(WoReg*)0xF8028000U) /**< \brief (UART1) Control Register */ +#define REG_UART1_MR (*(RwReg*)0xF8028004U) /**< \brief (UART1) Mode Register */ +#define REG_UART1_IER (*(WoReg*)0xF8028008U) /**< \brief (UART1) Interrupt Enable Register */ +#define REG_UART1_IDR (*(WoReg*)0xF802800CU) /**< \brief (UART1) Interrupt Disable Register */ +#define REG_UART1_IMR (*(RoReg*)0xF8028010U) /**< \brief (UART1) Interrupt Mask Register */ +#define REG_UART1_SR (*(RoReg*)0xF8028014U) /**< \brief (UART1) Status Register */ +#define REG_UART1_RHR (*(RoReg*)0xF8028018U) /**< \brief (UART1) Receive Holding Register */ +#define REG_UART1_THR (*(WoReg*)0xF802801CU) /**< \brief (UART1) Transmit Holding Register */ +#define REG_UART1_BRGR (*(RwReg*)0xF8028020U) /**< \brief (UART1) Baud Rate Generator Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_UART1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_udphs.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_udphs.h new file mode 100644 index 000000000..7d72b16ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_udphs.h @@ -0,0 +1,338 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_UDPHS_INSTANCE_ +#define _SAMA5_UDPHS_INSTANCE_ + +/* ========== Register definition for UDPHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UDPHS_CTRL (0xF8030000U) /**< \brief (UDPHS) UDPHS Control Register */ +#define REG_UDPHS_FNUM (0xF8030004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ +#define REG_UDPHS_IEN (0xF8030010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ +#define REG_UDPHS_INTSTA (0xF8030014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ +#define REG_UDPHS_CLRINT (0xF8030018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ +#define REG_UDPHS_EPTRST (0xF803001CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ +#define REG_UDPHS_TST (0xF80300E0U) /**< \brief (UDPHS) UDPHS Test Register */ +#define REG_UDPHS_IPNAME1 (0xF80300F0U) /**< \brief (UDPHS) UDPHS Name1 Register */ +#define REG_UDPHS_IPNAME2 (0xF80300F4U) /**< \brief (UDPHS) UDPHS Name2 Register */ +#define REG_UDPHS_IPFEATURES (0xF80300F8U) /**< \brief (UDPHS) UDPHS Features Register */ +#define REG_UDPHS_EPTCFG0 (0xF8030100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLENB0 (0xF8030104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLDIS0 (0xF8030108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTL0 (0xF803010CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ +#define REG_UDPHS_EPTSETSTA0 (0xF8030114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCLRSTA0 (0xF8030118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTSTA0 (0xF803011CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCFG1 (0xF8030120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLENB1 (0xF8030124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLDIS1 (0xF8030128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTL1 (0xF803012CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ +#define REG_UDPHS_EPTSETSTA1 (0xF8030134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCLRSTA1 (0xF8030138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTSTA1 (0xF803013CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCFG2 (0xF8030140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLENB2 (0xF8030144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLDIS2 (0xF8030148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTL2 (0xF803014CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ +#define REG_UDPHS_EPTSETSTA2 (0xF8030154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCLRSTA2 (0xF8030158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTSTA2 (0xF803015CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCFG3 (0xF8030160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLENB3 (0xF8030164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLDIS3 (0xF8030168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTL3 (0xF803016CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ +#define REG_UDPHS_EPTSETSTA3 (0xF8030174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCLRSTA3 (0xF8030178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTSTA3 (0xF803017CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCFG4 (0xF8030180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLENB4 (0xF8030184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLDIS4 (0xF8030188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTL4 (0xF803018CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ +#define REG_UDPHS_EPTSETSTA4 (0xF8030194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCLRSTA4 (0xF8030198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTSTA4 (0xF803019CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCFG5 (0xF80301A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLENB5 (0xF80301A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLDIS5 (0xF80301A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTL5 (0xF80301ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ +#define REG_UDPHS_EPTSETSTA5 (0xF80301B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCLRSTA5 (0xF80301B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTSTA5 (0xF80301BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCFG6 (0xF80301C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLENB6 (0xF80301C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLDIS6 (0xF80301C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTL6 (0xF80301CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ +#define REG_UDPHS_EPTSETSTA6 (0xF80301D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCLRSTA6 (0xF80301D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTSTA6 (0xF80301DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCFG7 (0xF80301E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLENB7 (0xF80301E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLDIS7 (0xF80301E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTL7 (0xF80301ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 7) */ +#define REG_UDPHS_EPTSETSTA7 (0xF80301F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCLRSTA7 (0xF80301F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTSTA7 (0xF80301FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCFG8 (0xF8030200U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLENB8 (0xF8030204U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLDIS8 (0xF8030208U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTL8 (0xF803020CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 8) */ +#define REG_UDPHS_EPTSETSTA8 (0xF8030214U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCLRSTA8 (0xF8030218U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTSTA8 (0xF803021CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCFG9 (0xF8030220U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLENB9 (0xF8030224U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLDIS9 (0xF8030228U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTL9 (0xF803022CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 9) */ +#define REG_UDPHS_EPTSETSTA9 (0xF8030234U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCLRSTA9 (0xF8030238U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTSTA9 (0xF803023CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCFG10 (0xF8030240U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLENB10 (0xF8030244U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLDIS10 (0xF8030248U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTL10 (0xF803024CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 10) */ +#define REG_UDPHS_EPTSETSTA10 (0xF8030254U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCLRSTA10 (0xF8030258U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTSTA10 (0xF803025CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCFG11 (0xF8030260U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLENB11 (0xF8030264U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLDIS11 (0xF8030268U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTL11 (0xF803026CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 11) */ +#define REG_UDPHS_EPTSETSTA11 (0xF8030274U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCLRSTA11 (0xF8030278U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTSTA11 (0xF803027CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCFG12 (0xF8030280U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLENB12 (0xF8030284U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLDIS12 (0xF8030288U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTL12 (0xF803028CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 12) */ +#define REG_UDPHS_EPTSETSTA12 (0xF8030294U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCLRSTA12 (0xF8030298U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTSTA12 (0xF803029CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCFG13 (0xF80302A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLENB13 (0xF80302A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLDIS13 (0xF80302A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTL13 (0xF80302ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 13) */ +#define REG_UDPHS_EPTSETSTA13 (0xF80302B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCLRSTA13 (0xF80302B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTSTA13 (0xF80302BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCFG14 (0xF80302C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLENB14 (0xF80302C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLDIS14 (0xF80302C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTL14 (0xF80302CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 14) */ +#define REG_UDPHS_EPTSETSTA14 (0xF80302D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCLRSTA14 (0xF80302D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTSTA14 (0xF80302DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCFG15 (0xF80302E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLENB15 (0xF80302E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLDIS15 (0xF80302E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTL15 (0xF80302ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 15) */ +#define REG_UDPHS_EPTSETSTA15 (0xF80302F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTCLRSTA15 (0xF80302F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTSTA15 (0xF80302FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 15) */ +#define REG_UDPHS_DMANXTDSC0 (0xF8030300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ +#define REG_UDPHS_DMAADDRESS0 (0xF8030304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ +#define REG_UDPHS_DMACONTROL0 (0xF8030308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ +#define REG_UDPHS_DMASTATUS0 (0xF803030CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ +#define REG_UDPHS_DMANXTDSC1 (0xF8030310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ +#define REG_UDPHS_DMAADDRESS1 (0xF8030314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ +#define REG_UDPHS_DMACONTROL1 (0xF8030318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ +#define REG_UDPHS_DMASTATUS1 (0xF803031CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ +#define REG_UDPHS_DMANXTDSC2 (0xF8030320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ +#define REG_UDPHS_DMAADDRESS2 (0xF8030324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ +#define REG_UDPHS_DMACONTROL2 (0xF8030328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ +#define REG_UDPHS_DMASTATUS2 (0xF803032CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ +#define REG_UDPHS_DMANXTDSC3 (0xF8030330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ +#define REG_UDPHS_DMAADDRESS3 (0xF8030334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ +#define REG_UDPHS_DMACONTROL3 (0xF8030338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ +#define REG_UDPHS_DMASTATUS3 (0xF803033CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ +#define REG_UDPHS_DMANXTDSC4 (0xF8030340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ +#define REG_UDPHS_DMAADDRESS4 (0xF8030344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ +#define REG_UDPHS_DMACONTROL4 (0xF8030348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ +#define REG_UDPHS_DMASTATUS4 (0xF803034CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ +#define REG_UDPHS_DMANXTDSC5 (0xF8030350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ +#define REG_UDPHS_DMAADDRESS5 (0xF8030354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ +#define REG_UDPHS_DMACONTROL5 (0xF8030358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ +#define REG_UDPHS_DMASTATUS5 (0xF803035CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ +#define REG_UDPHS_DMANXTDSC6 (0xF8030360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 6) */ +#define REG_UDPHS_DMAADDRESS6 (0xF8030364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 6) */ +#define REG_UDPHS_DMACONTROL6 (0xF8030368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 6) */ +#define REG_UDPHS_DMASTATUS6 (0xF803036CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 6) */ +#else +#define REG_UDPHS_CTRL (*(RwReg*)0xF8030000U) /**< \brief (UDPHS) UDPHS Control Register */ +#define REG_UDPHS_FNUM (*(RoReg*)0xF8030004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ +#define REG_UDPHS_IEN (*(RwReg*)0xF8030010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ +#define REG_UDPHS_INTSTA (*(RoReg*)0xF8030014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ +#define REG_UDPHS_CLRINT (*(WoReg*)0xF8030018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ +#define REG_UDPHS_EPTRST (*(WoReg*)0xF803001CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ +#define REG_UDPHS_TST (*(RwReg*)0xF80300E0U) /**< \brief (UDPHS) UDPHS Test Register */ +#define REG_UDPHS_IPNAME1 (*(RoReg*)0xF80300F0U) /**< \brief (UDPHS) UDPHS Name1 Register */ +#define REG_UDPHS_IPNAME2 (*(RoReg*)0xF80300F4U) /**< \brief (UDPHS) UDPHS Name2 Register */ +#define REG_UDPHS_IPFEATURES (*(RoReg*)0xF80300F8U) /**< \brief (UDPHS) UDPHS Features Register */ +#define REG_UDPHS_EPTCFG0 (*(RwReg*)0xF8030100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLENB0 (*(WoReg*)0xF8030104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTLDIS0 (*(WoReg*)0xF8030108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ +#define REG_UDPHS_EPTCTL0 (*(RoReg*)0xF803010CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ +#define REG_UDPHS_EPTSETSTA0 (*(WoReg*)0xF8030114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCLRSTA0 (*(WoReg*)0xF8030118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTSTA0 (*(RoReg*)0xF803011CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ +#define REG_UDPHS_EPTCFG1 (*(RwReg*)0xF8030120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLENB1 (*(WoReg*)0xF8030124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTLDIS1 (*(WoReg*)0xF8030128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ +#define REG_UDPHS_EPTCTL1 (*(RoReg*)0xF803012CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ +#define REG_UDPHS_EPTSETSTA1 (*(WoReg*)0xF8030134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCLRSTA1 (*(WoReg*)0xF8030138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTSTA1 (*(RoReg*)0xF803013CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ +#define REG_UDPHS_EPTCFG2 (*(RwReg*)0xF8030140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLENB2 (*(WoReg*)0xF8030144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTLDIS2 (*(WoReg*)0xF8030148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ +#define REG_UDPHS_EPTCTL2 (*(RoReg*)0xF803014CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ +#define REG_UDPHS_EPTSETSTA2 (*(WoReg*)0xF8030154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCLRSTA2 (*(WoReg*)0xF8030158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTSTA2 (*(RoReg*)0xF803015CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ +#define REG_UDPHS_EPTCFG3 (*(RwReg*)0xF8030160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLENB3 (*(WoReg*)0xF8030164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTLDIS3 (*(WoReg*)0xF8030168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ +#define REG_UDPHS_EPTCTL3 (*(RoReg*)0xF803016CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ +#define REG_UDPHS_EPTSETSTA3 (*(WoReg*)0xF8030174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCLRSTA3 (*(WoReg*)0xF8030178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTSTA3 (*(RoReg*)0xF803017CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ +#define REG_UDPHS_EPTCFG4 (*(RwReg*)0xF8030180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLENB4 (*(WoReg*)0xF8030184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTLDIS4 (*(WoReg*)0xF8030188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ +#define REG_UDPHS_EPTCTL4 (*(RoReg*)0xF803018CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ +#define REG_UDPHS_EPTSETSTA4 (*(WoReg*)0xF8030194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCLRSTA4 (*(WoReg*)0xF8030198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTSTA4 (*(RoReg*)0xF803019CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ +#define REG_UDPHS_EPTCFG5 (*(RwReg*)0xF80301A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLENB5 (*(WoReg*)0xF80301A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTLDIS5 (*(WoReg*)0xF80301A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ +#define REG_UDPHS_EPTCTL5 (*(RoReg*)0xF80301ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ +#define REG_UDPHS_EPTSETSTA5 (*(WoReg*)0xF80301B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCLRSTA5 (*(WoReg*)0xF80301B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTSTA5 (*(RoReg*)0xF80301BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ +#define REG_UDPHS_EPTCFG6 (*(RwReg*)0xF80301C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLENB6 (*(WoReg*)0xF80301C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTLDIS6 (*(WoReg*)0xF80301C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ +#define REG_UDPHS_EPTCTL6 (*(RoReg*)0xF80301CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ +#define REG_UDPHS_EPTSETSTA6 (*(WoReg*)0xF80301D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCLRSTA6 (*(WoReg*)0xF80301D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTSTA6 (*(RoReg*)0xF80301DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ +#define REG_UDPHS_EPTCFG7 (*(RwReg*)0xF80301E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLENB7 (*(WoReg*)0xF80301E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTLDIS7 (*(WoReg*)0xF80301E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 7) */ +#define REG_UDPHS_EPTCTL7 (*(RoReg*)0xF80301ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 7) */ +#define REG_UDPHS_EPTSETSTA7 (*(WoReg*)0xF80301F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCLRSTA7 (*(WoReg*)0xF80301F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTSTA7 (*(RoReg*)0xF80301FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 7) */ +#define REG_UDPHS_EPTCFG8 (*(RwReg*)0xF8030200U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLENB8 (*(WoReg*)0xF8030204U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTLDIS8 (*(WoReg*)0xF8030208U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 8) */ +#define REG_UDPHS_EPTCTL8 (*(RoReg*)0xF803020CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 8) */ +#define REG_UDPHS_EPTSETSTA8 (*(WoReg*)0xF8030214U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCLRSTA8 (*(WoReg*)0xF8030218U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTSTA8 (*(RoReg*)0xF803021CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 8) */ +#define REG_UDPHS_EPTCFG9 (*(RwReg*)0xF8030220U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLENB9 (*(WoReg*)0xF8030224U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTLDIS9 (*(WoReg*)0xF8030228U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 9) */ +#define REG_UDPHS_EPTCTL9 (*(RoReg*)0xF803022CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 9) */ +#define REG_UDPHS_EPTSETSTA9 (*(WoReg*)0xF8030234U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCLRSTA9 (*(WoReg*)0xF8030238U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTSTA9 (*(RoReg*)0xF803023CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 9) */ +#define REG_UDPHS_EPTCFG10 (*(RwReg*)0xF8030240U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLENB10 (*(WoReg*)0xF8030244U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTLDIS10 (*(WoReg*)0xF8030248U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 10) */ +#define REG_UDPHS_EPTCTL10 (*(RoReg*)0xF803024CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 10) */ +#define REG_UDPHS_EPTSETSTA10 (*(WoReg*)0xF8030254U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCLRSTA10 (*(WoReg*)0xF8030258U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTSTA10 (*(RoReg*)0xF803025CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 10) */ +#define REG_UDPHS_EPTCFG11 (*(RwReg*)0xF8030260U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLENB11 (*(WoReg*)0xF8030264U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTLDIS11 (*(WoReg*)0xF8030268U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 11) */ +#define REG_UDPHS_EPTCTL11 (*(RoReg*)0xF803026CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 11) */ +#define REG_UDPHS_EPTSETSTA11 (*(WoReg*)0xF8030274U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCLRSTA11 (*(WoReg*)0xF8030278U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTSTA11 (*(RoReg*)0xF803027CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 11) */ +#define REG_UDPHS_EPTCFG12 (*(RwReg*)0xF8030280U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLENB12 (*(WoReg*)0xF8030284U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTLDIS12 (*(WoReg*)0xF8030288U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 12) */ +#define REG_UDPHS_EPTCTL12 (*(RoReg*)0xF803028CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 12) */ +#define REG_UDPHS_EPTSETSTA12 (*(WoReg*)0xF8030294U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCLRSTA12 (*(WoReg*)0xF8030298U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTSTA12 (*(RoReg*)0xF803029CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 12) */ +#define REG_UDPHS_EPTCFG13 (*(RwReg*)0xF80302A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLENB13 (*(WoReg*)0xF80302A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTLDIS13 (*(WoReg*)0xF80302A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 13) */ +#define REG_UDPHS_EPTCTL13 (*(RoReg*)0xF80302ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 13) */ +#define REG_UDPHS_EPTSETSTA13 (*(WoReg*)0xF80302B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCLRSTA13 (*(WoReg*)0xF80302B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTSTA13 (*(RoReg*)0xF80302BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 13) */ +#define REG_UDPHS_EPTCFG14 (*(RwReg*)0xF80302C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLENB14 (*(WoReg*)0xF80302C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTLDIS14 (*(WoReg*)0xF80302C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 14) */ +#define REG_UDPHS_EPTCTL14 (*(RoReg*)0xF80302CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 14) */ +#define REG_UDPHS_EPTSETSTA14 (*(WoReg*)0xF80302D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCLRSTA14 (*(WoReg*)0xF80302D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTSTA14 (*(RoReg*)0xF80302DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 14) */ +#define REG_UDPHS_EPTCFG15 (*(RwReg*)0xF80302E0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLENB15 (*(WoReg*)0xF80302E4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTLDIS15 (*(WoReg*)0xF80302E8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 15) */ +#define REG_UDPHS_EPTCTL15 (*(RoReg*)0xF80302ECU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 15) */ +#define REG_UDPHS_EPTSETSTA15 (*(WoReg*)0xF80302F4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTCLRSTA15 (*(WoReg*)0xF80302F8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 15) */ +#define REG_UDPHS_EPTSTA15 (*(RoReg*)0xF80302FCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 15) */ +#define REG_UDPHS_DMANXTDSC0 (*(RwReg*)0xF8030300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */ +#define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0xF8030304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */ +#define REG_UDPHS_DMACONTROL0 (*(RwReg*)0xF8030308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */ +#define REG_UDPHS_DMASTATUS0 (*(RwReg*)0xF803030CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */ +#define REG_UDPHS_DMANXTDSC1 (*(RwReg*)0xF8030310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ +#define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0xF8030314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ +#define REG_UDPHS_DMACONTROL1 (*(RwReg*)0xF8030318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ +#define REG_UDPHS_DMASTATUS1 (*(RwReg*)0xF803031CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ +#define REG_UDPHS_DMANXTDSC2 (*(RwReg*)0xF8030320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ +#define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0xF8030324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ +#define REG_UDPHS_DMACONTROL2 (*(RwReg*)0xF8030328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ +#define REG_UDPHS_DMASTATUS2 (*(RwReg*)0xF803032CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ +#define REG_UDPHS_DMANXTDSC3 (*(RwReg*)0xF8030330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ +#define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0xF8030334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ +#define REG_UDPHS_DMACONTROL3 (*(RwReg*)0xF8030338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ +#define REG_UDPHS_DMASTATUS3 (*(RwReg*)0xF803033CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ +#define REG_UDPHS_DMANXTDSC4 (*(RwReg*)0xF8030340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ +#define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0xF8030344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ +#define REG_UDPHS_DMACONTROL4 (*(RwReg*)0xF8030348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ +#define REG_UDPHS_DMASTATUS4 (*(RwReg*)0xF803034CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ +#define REG_UDPHS_DMANXTDSC5 (*(RwReg*)0xF8030350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ +#define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0xF8030354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ +#define REG_UDPHS_DMACONTROL5 (*(RwReg*)0xF8030358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ +#define REG_UDPHS_DMASTATUS5 (*(RwReg*)0xF803035CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ +#define REG_UDPHS_DMANXTDSC6 (*(RwReg*)0xF8030360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 6) */ +#define REG_UDPHS_DMAADDRESS6 (*(RwReg*)0xF8030364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 6) */ +#define REG_UDPHS_DMACONTROL6 (*(RwReg*)0xF8030368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 6) */ +#define REG_UDPHS_DMASTATUS6 (*(RwReg*)0xF803036CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 6) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_UDPHS_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart0.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart0.h new file mode 100644 index 000000000..1fcb2fd5e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart0.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART0_INSTANCE_ +#define _SAMA5_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART0_CR (0xF001C000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (0xF001C004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (0xF001C008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (0xF001C00CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (0xF001C010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (0xF001C014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (0xF001C018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (0xF001C01CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (0xF001C020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (0xF001C024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (0xF001C028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (0xF001C040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (0xF001C044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (0xF001C04CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (0xF001C050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR (0xF001C0E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (0xF001C0E8U) /**< \brief (USART0) Write Protect Status Register */ +#else +#define REG_USART0_CR (*(WoReg*)0xF001C000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (*(RwReg*)0xF001C004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (*(WoReg*)0xF001C008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (*(WoReg*)0xF001C00CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (*(RoReg*)0xF001C010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (*(RoReg*)0xF001C014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (*(RoReg*)0xF001C018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (*(WoReg*)0xF001C01CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (*(RwReg*)0xF001C020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (*(RwReg*)0xF001C024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (*(RwReg*)0xF001C028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (*(RwReg*)0xF001C040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (*(RoReg*)0xF001C044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (*(RwReg*)0xF001C04CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (*(RwReg*)0xF001C050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_WPMR (*(RwReg*)0xF001C0E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (*(RoReg*)0xF001C0E8U) /**< \brief (USART0) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart1.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart1.h new file mode 100644 index 000000000..fb1172a61 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart1.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART1_INSTANCE_ +#define _SAMA5_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART1_CR (0xF0020000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (0xF0020004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (0xF0020008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (0xF002000CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (0xF0020010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (0xF0020014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (0xF0020018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (0xF002001CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (0xF0020020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (0xF0020024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (0xF0020028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (0xF0020040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (0xF0020044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (0xF002004CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (0xF0020050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR (0xF00200E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (0xF00200E8U) /**< \brief (USART1) Write Protect Status Register */ +#else +#define REG_USART1_CR (*(WoReg*)0xF0020000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (*(RwReg*)0xF0020004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (*(WoReg*)0xF0020008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (*(WoReg*)0xF002000CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (*(RoReg*)0xF0020010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (*(RoReg*)0xF0020014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (*(RoReg*)0xF0020018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (*(WoReg*)0xF002001CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (*(RwReg*)0xF0020020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (*(RwReg*)0xF0020024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (*(RwReg*)0xF0020028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (*(RwReg*)0xF0020040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (*(RoReg*)0xF0020044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (*(RwReg*)0xF002004CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (*(RwReg*)0xF0020050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_WPMR (*(RwReg*)0xF00200E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (*(RoReg*)0xF00200E8U) /**< \brief (USART1) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart2.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart2.h new file mode 100644 index 000000000..d8fed0174 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart2.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART2_INSTANCE_ +#define _SAMA5_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART2_CR (0xF8020000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (0xF8020004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (0xF8020008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (0xF802000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (0xF8020010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (0xF8020014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (0xF8020018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (0xF802001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (0xF8020020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (0xF8020024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (0xF8020028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (0xF8020040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (0xF8020044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (0xF802004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (0xF8020050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_WPMR (0xF80200E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (0xF80200E8U) /**< \brief (USART2) Write Protect Status Register */ +#else +#define REG_USART2_CR (*(WoReg*)0xF8020000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (*(RwReg*)0xF8020004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (*(WoReg*)0xF8020008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (*(WoReg*)0xF802000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (*(RoReg*)0xF8020010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (*(RoReg*)0xF8020014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (*(RoReg*)0xF8020018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (*(WoReg*)0xF802001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (*(RwReg*)0xF8020020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (*(RwReg*)0xF8020024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (*(RwReg*)0xF8020028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (*(RwReg*)0xF8020040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (*(RoReg*)0xF8020044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (*(RwReg*)0xF802004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (*(RwReg*)0xF8020050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_WPMR (*(RwReg*)0xF80200E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (*(RoReg*)0xF80200E8U) /**< \brief (USART2) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart3.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart3.h new file mode 100644 index 000000000..845b76b10 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_usart3.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_USART3_INSTANCE_ +#define _SAMA5_USART3_INSTANCE_ + +/* ========== Register definition for USART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART3_CR (0xF8024000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (0xF8024004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (0xF8024008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (0xF802400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (0xF8024010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (0xF8024014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (0xF8024018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (0xF802401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (0xF8024020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (0xF8024024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (0xF8024028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (0xF8024040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (0xF8024044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (0xF802404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (0xF8024050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_WPMR (0xF80240E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (0xF80240E8U) /**< \brief (USART3) Write Protect Status Register */ +#else +#define REG_USART3_CR (*(WoReg*)0xF8024000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (*(RwReg*)0xF8024004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (*(WoReg*)0xF8024008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (*(WoReg*)0xF802400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (*(RoReg*)0xF8024010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (*(RoReg*)0xF8024014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (*(RoReg*)0xF8024018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (*(WoReg*)0xF802401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (*(RwReg*)0xF8024020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (*(RwReg*)0xF8024024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (*(RwReg*)0xF8024028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (*(RwReg*)0xF8024040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (*(RoReg*)0xF8024044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (*(RwReg*)0xF802404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (*(RwReg*)0xF8024050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_WPMR (*(RwReg*)0xF80240E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (*(RoReg*)0xF80240E8U) /**< \brief (USART3) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_USART3_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_wdt.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_wdt.h new file mode 100644 index 000000000..48af56a69 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/instance/instance_wdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SAMA5_WDT_INSTANCE_ +#define _SAMA5_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CR (0xFFFFFE40U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (0xFFFFFE44U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (0xFFFFFE48U) /**< \brief (WDT) Status Register */ +#else +#define REG_WDT_CR (*(WoReg*)0xFFFFFE40U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (*(RwReg*)0xFFFFFE44U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (*(RoReg*)0xFFFFFE48U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMA5_WDT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/irq.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/irq.h new file mode 100644 index 000000000..dd499d829 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/irq.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Methods and definitions for configuring interrupts. + * + * \section Usage + * -# Configure an interrupt source using IRQ_ConfigureIT + * -# Enable or disable interrupt generation of a particular source with + * IRQ_EnableIT and IRQ_DisableIT. + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef IRQ_H +#define IRQ_H + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + + #ifdef __cplusplus + extern "C" { +#endif +extern uint32_t IRQ_ConfigureIT(uint32_t source, + uint32_t mode, // mode for AIC, priority for NVIC + void( *handler )( void )); // ISR + +extern void IRQ_EnableIT(uint32_t source); + +extern void IRQ_DisableIT(uint32_t source); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef IRQ_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/isi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/isi.h new file mode 100644 index 000000000..da81ce75e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/isi.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup isi_module + * @{ + * \section gmac_usage Usage + * - ISI_Init: initialize ISI with default parameters + * - ISI_EnableInterrupt: enable one or more interrupts + * - ISI_DisableInterrupt: disable one or more interrupts + * - ISI_Enable: enable isi module + * - ISI_Disable: disable isi module + * - ISI_CodecPathFull: enable codec path + * - ISI_SetFrame: set frame rate + * - ISI_BytesForOnePixel: return number of byte for one pixel + * - ISI_StatusRegister: return ISI status register + * - ISI_Reset: make a software reset + */ +/**@}*/ + +#ifndef ISI_H +#define ISI_H + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** ISI descriptors */ +typedef struct +{ + /** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */ + uint32_t CurrentLcdIndex; + /** set if Fifo Codec Empty is present */ + volatile uint32_t DisplayCodec; + /** upgrade for each Fifo Codec Overflow (statistics use) */ + uint32_t nb_codec_ovf; + /** upgrade for each Fifo Preview Overflow (statistics use) */ + uint32_t nb_prev_ovf; +}ISI_Descriptors; + +/** Frame Buffer Descriptors */ +typedef struct +{ + /** Address of the Current FrameBuffer */ + uint32_t Current; + /** Address of the Control */ + uint32_t Control; + /** Address of the Next FrameBuffer */ + uint32_t Next; +}ISI_FrameBufferDescriptors; + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ISI_Enable(void); +extern void ISI_Disable(void); +extern void ISI_EnableInterrupt(uint32_t flag); +extern void ISI_DisableInterrupt(uint32_t flag); +extern void ISI_CodecPathFull(void); +extern void ISI_SetFrame(uint32_t frate); +extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb); +extern void ISI_Reset(void); +extern void ISI_Init(pIsi_Video pVideo); +extern uint32_t ISI_StatusRegister(void); + +#endif //#ifndef ISI_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/mmu.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/mmu.h new file mode 100644 index 000000000..f516d118a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/mmu.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MMU_ +#define _MMU_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "../cp15/cp15.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void MMU_Initialize(uint32_t *pTB); + +#endif /* #ifndef _MMU_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pio.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pio.h new file mode 100644 index 000000000..07ff2d837 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pio.h @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * This file provides a basic API for PIO configuration and usage of + * user-controlled pins. Please refer to the board.h file for a list of + * available pin definitions. + * + * \section Usage + * + * -# Define a constant pin description array such as the following one, using + * the existing definitions provided by the board.h file if possible: + * \code + * const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; + * \endcode + * Alternatively, it is possible to add new pins by provided the full Pin + * structure: + * \code + * // Pin instance to configure PA10 & PA11 as inputs with the internal + * // pull-up enabled. + * const Pin pPins = { + * (1 << 10) | (1 << 11), + * REG_PIOA, + * ID_PIOA, + * PIO_INPUT, + * PIO_PULLUP + * }; + * \endcode + * -# Configure a pin array by calling PIO_Configure() with a pointer to the + * array and its size (which is computed using the PIO_LISTSIZE macro). + * -# Change and get the value of a user-controlled pin using the PIO_Set, + * PIO_Clear and PIO_Get methods. + * -# Get the level being currently output by a user-controlled pin configured + * as an output using PIO_GetOutputDataStatus(). + */ + +#ifndef _PIO_ +#define _PIO_ + +/* + * Headers + */ + +#include "chip.h" + +#include + +/* + * Global Definitions + */ + +/* The pin is controlled by the associated signal of peripheral A. */ +#define PIO_PERIPH_A 0 +/* The pin is controlled by the associated signal of peripheral B. */ +#define PIO_PERIPH_B 1 +/* The pin is controlled by the associated signal of peripheral C. */ +#define PIO_PERIPH_C 2 +/* The pin is controlled by the associated signal of peripheral D. */ +#define PIO_PERIPH_D 3 +/* The pin is an input. */ +#define PIO_INPUT 4 +/* The pin is an output and has a default level of 0. */ +#define PIO_OUTPUT_0 5 +/* The pin is an output and has a default level of 1. */ +#define PIO_OUTPUT_1 6 + +/* Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0 << 0) +/* The internal pin pull-up is active. */ +#define PIO_PULLUP (1 << 0) +/* The internal glitch filter is active. */ +#define PIO_DEGLITCH (1 << 1) +/* The pin is open-drain. */ +#define PIO_OPENDRAIN (1 << 2) +/* The internal pin pull-down is active. */ +#define PIO_PULLDOWN (1 << 3) +/* The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1 << 3) + +/* Enable additional interrupt modes. */ +#define PIO_IT_AIME (1 << 4) + +/* Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1 << 5) +/* Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1 << 6) + +/* Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/* High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/* Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/* Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) + +#define PIO_WPMR_WPEN_EN ( 0x01 << 0 ) + +#define PIO_WPMR_WPEN_DIS ( 0x00 << 0 ) + +#define PIO_WPMR_WPKEY_VALID ( 0x50494F << 8 ) + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * Global Macros + */ + +/** + * Calculates the size of an array of Pin instances. The array must be defined + * locally (i.e. not a pointer), otherwise the computation will not be correct. + * \param pPins Local array of Pin instances. + * \return Number of elements in array. + */ +#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) + +/* + * Global Types + */ + + +/* + * Describes the type and attribute of one PIO pin or a group of similar pins. + * The #type# field can have the following values: + * - PIO_PERIPH_A + * - PIO_PERIPH_B + * - PIO_OUTPUT_0 + * - PIO_OUTPUT_1 + * - PIO_INPUT + * + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +typedef struct _Pin +{ + /* Bitmask indicating which pin(s) to configure. */ + uint32_t mask; + /* Pointer to the PIO controller which has the pin(s). */ + Pio *pio; + /* Peripheral ID of the PIO controller which has the pin(s). */ + uint8_t id; + /* Pin type. */ + uint8_t type; + /* Pin attribute. */ + uint8_t attribute; +} Pin ; + +/* + * Global Access Macros + */ + +/* + * Global Functions + */ + +extern uint8_t PIO_Configure( const Pin *list, uint32_t size ) ; + +extern void PIO_Set( const Pin *pin ) ; + +extern void PIO_Clear( const Pin *pin ) ; + +extern uint8_t PIO_Get( const Pin *pin ) ; + +extern uint8_t PIO_GetOutputDataStatus( const Pin *pin ) ; + +extern void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff ); + +extern void PIO_EnableWriteProtect( const Pin *pin ); + +extern void PIO_DisableWriteProtect( const Pin *pin ); + +extern uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin ); + +extern void PIO_Output_Low (Pio * pio, uint32_t pioId); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pio_it.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pio_it.h new file mode 100644 index 000000000..eb0ea8ff0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pio_it.h @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Configuration and handling of interrupts on PIO status changes. The API + * provided here have several advantages over the traditional PIO interrupt + * configuration approach: + * - It is highly portable + * - It automatically demultiplexes interrupts when multiples pins have been + * configured on a single PIO controller + * - It allows a group of pins to share the same interrupt + * + * However, it also has several minor drawbacks that may prevent from using it + * in particular applications: + * - It enables the clocks of all PIO controllers + * - PIO controllers all share the same interrupt handler, which does the + * demultiplexing and can be slower than direct configuration + * - It reserves space for a fixed number of interrupts, which can be + * increased by modifying the appropriate constant in pio_it.c. + * + * \par Usage + * + * -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() + * with the desired priority (0 ... 7). + * -# Configure a status change interrupt on one or more pin(s) with + * PIO_ConfigureIt(). + * -# Enable & disable interrupts on pins using PIO_EnableIt() and + * PIO_DisableIt(). + */ + +#ifndef _PIO_IT_ +#define _PIO_IT_ + +/* + * Headers + */ + +#include "pio.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * Global functions + */ + +extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ; + +extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ; + +extern void PIO_EnableIt( const Pin *pPin ) ; + +extern void PIO_DisableIt( const Pin *pPin ) ; + +extern void PIO_IT_InterruptHandler( void ) ; + +extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ; + +extern void PIO_CaptureHandler( void ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_IT_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pit.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pit.h new file mode 100644 index 000000000..b661cd49a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pit.h @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + + +#ifndef _PIT_ +#define _PIT_ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void PIT_Init(uint32_t period, uint32_t pit_frequency); + +extern void PIT_SetPIV(uint32_t piv); + +extern void PIT_Enable(void); + +extern void PIT_Disable(void); + +extern void PIT_EnableIT(void); + +extern void PIT_DisableIT(void); + +extern uint32_t PIT_GetMode(void); + +extern uint32_t PIT_GetStatus(void); + +extern uint32_t PIT_GetPIIR(void); + +extern uint32_t PIT_GetPIVR(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIT_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pmc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pmc.h new file mode 100644 index 000000000..8128e1294 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pmc.h @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _PMC_ +#define _PMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** Peripheral clock maxinum frequency */ +typedef struct _PeripheralClockMaxFreq { + uint32_t bPeriphID; /**< Peripheral ID */ + uint32_t bMaxFrequency; /**< Max frequency*/ +} PeripheralClockMaxFreq; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void PMC_EnablePeripheral( uint32_t dwId ) ; +extern void PMC_DisablePeripheral( uint32_t dwId ) ; + +extern void PMC_EnableAllPeripherals( void ) ; +extern void PMC_DisableAllPeripherals( void ) ; + +extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ; + +extern void PMC_SelectExt32KCrystal(void); +extern void PMC_SelectInt32kCrystal(void); +extern void PMC_SelectExt12M_Osc(void); +extern void PMC_SelectInt12M_Osc(void); +extern void PMC_SwitchMck2Pll(void); +extern void PMC_SwitchMck2Main(void); +extern void PMC_SwitchMck2Slck(void); +extern void PMC_SetPllA(uint32_t pll, uint32_t cpcr); +extern void PMC_SetMckPrescaler(uint32_t prescaler); +extern void PMC_SetMckDivider(uint32_t divider); +extern void PMC_SetMckPllaDiv(uint32_t divider); +extern void PMC_DisablePllA(void); +extern uint32_t PMC_GetPeriMaxFreq( uint32_t dwId ); +extern uint32_t PMC_SetPeriMaxClock( uint32_t dwId, uint32_t mck); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pwmc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pwmc.h new file mode 100644 index 000000000..000533fb4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/pwmc.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral. + * + * \par Usage + * + * -# Configures PWM clocks A & B to run at the given frequencies using + * \ref PWMC_ConfigureClocks(). + * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt() + * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime(). + * -# Enable & disable channel using \ref PWMC_EnableChannel() and + * \ref PWMC_DisableChannel(). + * -# Enable & disable the period interrupt for the given PWM channel using + * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). + * -# Enable & disable the selected interrupts sources on a PWMC peripheral + * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). + * -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(), + * \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock(). + * -# Control PWM override output using \ref PWMC_SetOverrideValue(), + * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). + * -# Send data through the transmitter using \ref PWMC_WriteBuffer(). + * + */ + +#ifndef _PWMC_ +#define _PWMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t mode); + +extern void PWMC_EnableChannel(Pwm* pPwm,uint8_t channel); + +extern void PWMC_DisableChannel(Pwm* pPwm,uint8_t channel); + +extern void PWMC_EnableChannelIt(Pwm* pPwm,uint8_t channel); + +extern void PWMC_DisableChannelIt(Pwm* pPwm,uint8_t channel); + +extern void PWMC_ConfigureChannel(Pwm* pPwm,uint8_t channel,uint32_t mode); + +extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period); + +extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PWMC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/rstc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/rstc.h new file mode 100644 index 000000000..367bf4683 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/rstc.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _RSTC_H +#define _RSTC_H + +/*--------------------------------------------------------------------------- + * Includes + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +extern void RSTC_ConfigureMode(uint32_t rmr); + +extern void RSTC_SetUserResetEnable(uint8_t enable); + +extern void RSTC_SetUserResetInterruptEnable(uint8_t enable); + +extern void RSTC_SetExtResetLength(uint8_t powl); + +extern void RSTC_ProcessorReset(void); + +extern void RSTC_PeripheralReset(void); + +extern void RSTC_ExtReset(void); + +extern uint8_t RSTC_GetNrstLevel(void); + +extern uint8_t RSTC_IsUserResetDetected(void); + +extern uint8_t RSTC_IsBusy(void); + +extern uint32_t RSTC_GetStatus(void); + +#endif /* #ifndef _RSTC_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/rtc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/rtc.h new file mode 100644 index 000000000..5dbe15c72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/rtc.h @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Real Time Clock (RTC) controller. + * + */ + +#ifndef _RTC_ +#define _RTC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define RTC_HOUR_BIT_LEN_MASK 0x3F +#define RTC_MIN_BIT_LEN_MASK 0x7F +#define RTC_SEC_BIT_LEN_MASK 0x7F +#define RTC_CENT_BIT_LEN_MASK 0x7F +#define RTC_YEAR_BIT_LEN_MASK 0xFF +#define RTC_MONTH_BIT_LEN_MASK 0x1F +#define RTC_DATE_BIT_LEN_MASK 0x3F +#define RTC_WEEK_BIT_LEN_MASK 0x07 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ; + +extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ; + +extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ; + +extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ; + +extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) ; + +extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ; + +extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ; + +extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek ) ; + +extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek ) ; + +extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ; + +extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ; + +extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _RTC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/sha.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/sha.h new file mode 100644 index 000000000..b5a211d35 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/sha.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SHA_ +#define _SHA_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +extern void SHA_Start(void); +extern void SHA_SoftReset(void); +extern void SHA_FirstBlock(void); +extern void SHA_Configure(uint32_t mode); +extern void SHA_EnableIt(uint32_t sources); +extern void SHA_DisableIt(uint32_t sources); +extern uint32_t SHA_GetStatus(void); +extern void SHA_SetInput(uint32_t *data, uint8_t len); +extern void SHA_GetOutput(uint32_t *data); + +#endif /* #ifndef _SHA_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/smcNfc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/smcNfc.h new file mode 100644 index 000000000..c75368059 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/smcNfc.h @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** +* \file +* +* Definitions and function prototype for smc module +*/ + +#ifndef _SMC_ +#define _SMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef union _SmcStatus { + uint8_t BStatus; + struct _SmcStatusBits { + uint8_t smcSts:1, /**< NAND Flash Controller Status */ + xfrDone:1, /**< NFC Data Transfer Terminated */ + cmdDone:1, /**< Command Done */ + rbEdge: 1, /**< Ready/Busy Line 3 Edge Detected*/ + hammingReady:1; /**< Hamming ecc ready */ + } bStatus; +} SmcStatus; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* + * NFC definitions + */ + +/** Base address of NFC SRAM */ +#define NFC_SRAM_BASE_ADDRESS 0x200000 +/** Base address for NFC Address Command */ +#define NFC_CMD_BASE_ADDR 0x70000000 + + +/* -------- NFCADDR_CMD : NFC Address Command -------- */ +#define NFCADDR_CMD_CMD1 (0xFFu << 2) /* Command Register Value for Cycle 1 */ +#define NFCADDR_CMD_CMD2 (0xFFu << 10) /* Command Register Value for Cycle 2 */ +#define NFCADDR_CMD_VCMD2 (0x1u << 18) /* Valid Cycle 2 Command */ +#define NFCADDR_CMD_ACYCLE (0x7u << 19) /* Number of Address required for the current command */ +#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) /* No address cycle */ +#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) /* One address cycle */ +#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) /* Two address cycles */ +#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) /* Three address cycles */ +#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) /* Four address cycles */ +#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) /* Five address cycles */ +#define NFCADDR_CMD_CSID (0x7u << 22) /* Chip Select Identifier */ +#define NFCADDR_CMD_CSID_0 (0x0u << 22) /* CS0 */ +#define NFCADDR_CMD_CSID_1 (0x1u << 22) /* CS1 */ +#define NFCADDR_CMD_CSID_2 (0x2u << 22) /* CS2 */ +#define NFCADDR_CMD_CSID_3 (0x3u << 22) /* CS3 */ +#define NFCADDR_CMD_CSID_4 (0x4u << 22) /* CS4 */ +#define NFCADDR_CMD_CSID_5 (0x5u << 22) /* CS5 */ +#define NFCADDR_CMD_CSID_6 (0x6u << 22) /* CS6 */ +#define NFCADDR_CMD_CSID_7 (0x7u << 22) /* CS7 */ +#define NFCADDR_CMD_DATAEN (0x1u << 25) /* NFC Data Enable */ +#define NFCADDR_CMD_DATADIS (0x0u << 25) /* NFC Data disable */ +#define NFCADDR_CMD_NFCRD (0x0u << 26) /* NFC Read Enable */ +#define NFCADDR_CMD_NFCWR (0x1u << 26) /* NFC Write Enable */ +#define NFCADDR_CMD_NFCCMD (0x1u << 27) /* NFC Command Enable */ + +/* + * ECC definitions (Hsiao Code Errors) + */ + +/** A single bit was incorrect but has been recovered. */ +#define Hsiao_ERROR_SINGLEBIT 1 + +/** The original code has been corrupted. */ +#define Hsiao_ERROR_ECC 2 + +/** Multiple bits are incorrect in the data and they cannot be corrected. */ +#define Hsiao_ERROR_MULTIPLEBITS 3 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* + * NFC functions + */ + +extern void SMC_NFC_Configure(uint32_t mode); +extern void SMC_NFC_Reset(void); +extern void SMC_NFC_EnableNfc(void); +extern void SMC_NFC_EnableSpareRead(void); +extern void SMC_NFC_DisableSpareRead(void); +extern void SMC_NFC_EnableSpareWrite(void); +extern void SMC_NFC_DisableSpareWrite(void); +extern uint8_t SMC_NFC_isSpareRead(void); +extern uint8_t SMC_NFC_isSpareWrite(void); +extern uint8_t SMC_NFC_isTransferComplete(void); +extern uint8_t SMC_NFC_isReadyBusy(void); +extern uint8_t SMC_NFC_isNfcBusy(void); +extern uint32_t SMC_NFC_GetStatus(void); + +extern void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, uint32_t cycle0); +extern void SMC_NFC_Wait_CommandDone(void); +extern void SMC_NFC_Wait_XfrDone(void); +extern void SMC_NFC_Wait_RBbusy(void); +extern void SMC_NFC_Wait_HammingReady(void); + +extern void SMC_ECC_Configure(uint32_t type, uint32_t pageSize); +extern uint32_t SMC_ECC_GetCorrectoinType(void); +extern uint8_t SMC_ECC_GetStatus(uint8_t eccNumber); + +extern void SMC_ECC_GetValue(uint32_t *ecc); +extern void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, uint8_t busWidth); +extern uint8_t SMC_ECC_VerifyHsiao(uint8_t *data, uint32_t size, const uint8_t *originalCode, const uint8_t *verifyCode, uint8_t busWidth); +#endif /* #ifndef _SMC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/spi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/spi.h new file mode 100644 index 000000000..eddcd4fb0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/spi.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _SPI_ +#define _SPI_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section spi_configuration_macros SPI Configuration Macros + * - \ref SPI_PCS + * - \ref SPI_SCBR + * - \ref SPI_DLYBS + * - \ref SPI_DLYBCT + */ + +/** Calculate the PCS field value given the chip select NPCS value */ +#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF)) + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define SPI_SCBR(baudrate, masterClock) SPI_CSR_SCBR((uint32_t)(masterClock / baudrate)) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define SPI_DLYBS(delay, masterClock) SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define SPI_DLYBCT(delay, masterClock) SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1) + +/*------------------------------------------------------------------------------ */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void SPI_Enable( Spi* spi ) ; +extern void SPI_Disable( Spi* spi ) ; + +extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ; +extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ; + +extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ; +extern void SPI_SetMode( Spi* spi, uint32_t dwConfiguration ); + +extern void SPI_ChipSelect( Spi* spi, uint8_t cS); +extern void SPI_ReleaseCS( Spi* spi ); + +extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ; +extern void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast ); + +extern uint32_t SPI_Read( Spi* spi ) ; +extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ; +extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData ); + +extern uint32_t SPI_GetStatus( Spi* spi ) ; +extern uint32_t SPI_IsFinished( Spi* pSpi ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/ssc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/ssc.h new file mode 100644 index 000000000..fb66189c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/ssc.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Synchronous Serial (SSC) controller. + * + */ + +#ifndef _SSC_ +#define _SSC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock); +extern void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr); +extern void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr); +extern void SSC_EnableTransmitter(Ssc *ssc); +extern void SSC_DisableTransmitter(Ssc *ssc); +extern void SSC_EnableReceiver(Ssc *ssc); +extern void SSC_DisableReceiver(Ssc *ssc ); +extern void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_Write(Ssc *ssc, uint32_t frame); +extern uint32_t SSC_Read(Ssc *ssc ); +extern uint8_t SSC_IsRxReady(Ssc *ssc); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SSC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/tc.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/tc.h new file mode 100644 index 000000000..352bd91ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/tc.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _TC_ +#define _TC_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ; + +extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ; + +extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ; + +extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/tdes.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/tdes.h new file mode 100644 index 000000000..33cfc7d4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/tdes.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TDES_ +#define _TDES_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define MODE_SINGLE_DES 0x00 +#define MODE_TRIPLE_DES 0x01 +#define MODE_XTEA 0x02 + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +extern void TDES_Start(void); +extern void TDES_SoftReset(void); +extern void TDES_Recount(void); +extern void TDES_Configure(uint32_t mode); +extern void TDES_EnableIt(uint32_t sources); +extern void TDES_DisableIt(uint32_t sources); +extern uint32_t TDES_GetStatus(void); +extern void TDES_WriteKey1(uint32_t keyword0, uint32_t keyword1); +extern void TDES_WriteKey2(uint32_t keyword0, uint32_t keyword1); +extern void TDES_WriteKey3(uint32_t keyword0, uint32_t keyword1); +extern void TDES_SetInput(uint32_t data0, uint32_t data1); +extern void TDES_GetOutput(uint32_t *data0, uint32_t* data1); +extern void TDES_SetVector(uint32_t v0, uint32_t v1); +extern void TDES_SetXteaRounds(uint32_t rounds); + +#endif /* #ifndef _TDES_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/trace.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/trace.h new file mode 100644 index 000000000..a165c3e36 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/trace.h @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Standard output methods for reporting debug information, warnings and + * errors, which can be easily be turned on/off. + * + * \par Usage + * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually + * disable ALL traces; otherwise use DBGU_Configure(). + * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() + * TRACE_FATAL() macros to output traces throughout the program. + * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 + * and Fatal 1. Disable a group of traces by changing the value of + * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL + * are not generated. To generate no trace, use the reserved value 0. + * -# Trace disabling can be static or dynamic. If dynamic disabling is selected + * the trace level can be modified in runtime. If static disabling is selected + * the disabled traces are not compiled. + * + * \par traceLevels Trace level description + * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, + * and which do not produce meaningful information otherwise. + * -# TRACE_INFO (4): Informational trace about the program execution. Should + * enable the user to see the execution flow. + * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case + * it can be discarded safely; it may even be expected. + * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, + * but which indicates there is a problem with the code. + * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going + * any further. + */ + +#ifndef _TRACE_ +#define _TRACE_ + +/* + * Headers + */ + +#include "pio.h" + +#include + +/* + * Global Definitions + */ + +/** Softpack Version */ +#define SOFTPACK_VERSION "1.4" + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +/* By default, all traces are output except the debug one. */ +#if !defined(TRACE_LEVEL) +#define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +/* By default, trace level is static (not dynamic) */ +#if !defined(DYN_TRACES) +#define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) +#error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (DYN_TRACES==0) + #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) + #define NOTRACE + #endif +#endif + + + +/* ------------------------------------------------------------------------------ + * Global Macros + * ------------------------------------------------------------------------------ + */ + +extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ; + +/** + * Initializes the DBGU for ISP project + * + * \param mode DBGU mode. + * \param baudrate DBGU baudrate. + * \param mck Master clock frequency. + */ +#ifndef DYNTRACE +#define DYNTRACE 0 +#endif + +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsDBGU[] = {PINS_DBGU}; \ + PIO_Configure(pinsDBGU, PIO_LISTSIZE(pinsDBGU)); \ + DBGU_Configure( baudrate, mck ) ; \ + } +#endif + +/** + * Outputs a formatted string using 'printf' if the log level is high + * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. + * \param ... Additional parameters depending on formatted string. + */ +#if defined(NOTRACE) + +/* Empty macro */ +#define TRACE_DEBUG(...) { } +#define TRACE_INFO(...) { } +#define TRACE_WARNING(...) { } +#define TRACE_ERROR(...) { } +#define TRACE_FATAL(...) { while(1); } + +#define TRACE_DEBUG_WP(...) { } +#define TRACE_INFO_WP(...) { } +#define TRACE_WARNING_WP(...) { } +#define TRACE_ERROR_WP(...) { } +#define TRACE_FATAL_WP(...) { while(1); } + +#elif (DYN_TRACES == 1) + +/* Trace output depends on dwTraceLevel value */ +#define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } +#define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } +#define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } +#define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } +#define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } + +#define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } +#define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } +#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } +#define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } +#define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } + +#else + +/* Trace compilation depends on TRACE_LEVEL value */ +#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) +#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } +#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_DEBUG(...) { } +#define TRACE_DEBUG_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) +#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } +#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_INFO(...) { } +#define TRACE_INFO_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) +#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } +#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_WARNING(...) { } +#define TRACE_WARNING_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) +#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } +#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_ERROR(...) { } +#define TRACE_ERROR_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) +#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } +#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } +#else +#define TRACE_FATAL(...) { while(1); } +#define TRACE_FATAL_WP(...) { while(1); } +#endif + +#endif + + +/** + * Exported variables + */ +/** Depending on DYN_TRACES, dwTraceLevel is a modifable runtime variable or a define */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern uint32_t dwTraceLevel ; +#endif + +#endif //#ifndef TRACE_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/trng.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/trng.h new file mode 100644 index 000000000..5e4aaba21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TRNG_ +#define _TRNG_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +void TRNG_Enable(uint32_t key); +void TRNG_Disable(uint32_t key); +void TRNG_EnableIt(void); +void TRNG_DisableIt(void); +uint32_t TRNG_GetStatus(void); +uint32_t TRNG_GetRandData(void); + +#endif /* #ifndef _TRNG_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/twi.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/twi.h new file mode 100644 index 000000000..3358d2e5d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/twi.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for configuration the Two Wire Interface (TWI) peripheral. + * + */ + +#ifndef _TWI_ +#define _TWI_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ +/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/ +#define TWI_STATUS_TXRDY(status) ((status & TWI_SR_TXRDY) == TWI_SR_TXRDY) + +/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/ +#define TWI_STATUS_RXRDY(status) ((status & TWI_SR_RXRDY) == TWI_SR_RXRDY) + +/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/ +#define TWI_STATUS_TXCOMP(status) ((status & TWI_SR_TXCOMP) == TWI_SR_TXCOMP) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * External function + *----------------------------------------------------------------------------*/ + +extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck); + +extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress); + +extern void TWI_Stop(Twi *pTwi); + +extern void TWI_StartRead( + Twi *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize); + +extern uint8_t TWI_ReadByte(Twi *pTwi); + +extern void TWI_WriteByte(Twi *pTwi, uint8_t byte); + +extern void TWI_StartWrite( + Twi *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte); + +extern uint8_t TWI_ByteReceived(Twi *pTwi); + +extern uint8_t TWI_ByteSent(Twi *pTwi); + +extern uint8_t TWI_TransferComplete(Twi *pTwi); + +extern void TWI_EnableIt(Twi *pTwi, uint32_t sources); + +extern void TWI_DisableIt(Twi *pTwi, uint32_t sources); + +extern uint32_t TWI_GetStatus(Twi *pTwi); + +extern uint32_t TWI_GetMaskedStatus(Twi *pTwi); + +extern void TWI_SendSTOPCondition(Twi *pTwi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TWI_ */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/twid.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/twid.h new file mode 100644 index 000000000..585fd710c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/twid.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TWID_ +#define _TWID_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ + +/** TWI driver is currently busy. */ +#define TWID_ERROR_BUSY 1 +#define TWID_ERROR_NORSP 2 + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct _Twid +{ + /** Pointer to the underlying TWI peripheral.*/ + Twi *pTwi ; + /** Current asynchronous transfer being processed.*/ + Async *pTransfer ; +} Twid; + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +extern void TWID_Initialize( Twid *pTwid, Twi *pTwi ) ; + +extern void TWID_Handler( Twid *pTwid ) ; + +extern uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_Write( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef TWID_H + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/udphs.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/udphs.h new file mode 100644 index 000000000..93de7001a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/udphs.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +#ifndef UDPHS_H +#define UDPHS_H +/** addtogroup usbd_hal + *@{ + */ + +/** Indicates chip has an UDP High Speed. */ +#define CHIP_USB_UDPHS + +/** Indicates chip has an internal pull-up. */ +#define CHIP_USB_PULLUP_INTERNAL + +/** Number of USB endpoints */ +#define CHIP_USB_NUMENDPOINTS 7 + +/** Endpoints max paxcket size */ +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ + ((i == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_ENDPOINTS_BANKS(i) \ + ((i == 0) ? 1 : ((i == 1) ? 3 : ((i == 2) ? 3 : 2))) + +/** Endpoints DMA support */ +#define CHIP_USB_ENDPOINTS_DMA(i) \ + ((i == 0) ? 0 : 1) + +/**@}*/ +#endif /* #ifndef UDPHS_H */ diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/usart.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/usart.h new file mode 100644 index 000000000..f367ba905 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/usart.h @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * This module provides several definitions and methods for using an USART + * peripheral. + * + * \par Usage + * + * -# Enable the USART peripheral clock in the PMC. + * -# Enable the required USART PIOs (see pio.h). + * -# Configure the UART by calling USART_Configure. + * -# Enable the transmitter and/or the receiver of the USART using + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + * -# Send data through the USART using the USART_Write methods. + * -# Receive data from the USART using the USART_Read functions; the availability of data can be polled + * with USART_IsDataAvailable. + * -# Disable the transmitter and/or the receiver of the USART with + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + */ + +#ifndef _USART_ +#define _USART_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/** \section USART_mode USART modes + * This section lists several common operating modes for an USART peripheral. + * + * \b Modes + * - USART_MODE_ASYNCHRONOUS + * - USART_MODE_IRDA + */ + +/** Basic asynchronous mode, i.e. 8 bits no parity.*/ +#define USART_MODE_ASYNCHRONOUS (US_MR_CHRL_8_BIT | US_MR_PAR_NO) + +/** IRDA mode*/ +#define USART_MODE_IRDA \ + (US_MR_USART_MODE_IRDA | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_FILTER) + +/** SPI mode*/ +#define AT91C_US_USMODE_SPIM 0xE +#define US_SPI_CPOL_0 (0x0<<16) +#define US_SPI_CPHA_0 (0x0<<8) +#define US_SPI_CPOL_1 (0x1<<16) +#define US_SPI_CPHA_1 (0x1<<8) +#define US_SPI_BPMODE_0 (US_SPI_CPOL_0|US_SPI_CPHA_1) +#define US_SPI_BPMODE_1 (US_SPI_CPOL_0|US_SPI_CPHA_0) +#define US_SPI_BPMODE_2 (US_SPI_CPOL_1|US_SPI_CPHA_1) +#define US_SPI_BPMODE_3 (US_SPI_CPOL_1|US_SPI_CPHA_0) + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +extern void USART_Configure( Usart *usart, uint32_t mode, uint32_t baudrate, uint32_t masterClock ) ; +extern uint32_t USART_GetStatus( Usart *usart ) ; +extern void USART_EnableIt( Usart *usart,uint32_t mode ) ; +extern void USART_DisableIt( Usart *usart,uint32_t mode ) ; +extern uint32_t USART_GetItMask( Usart * usart ) ; +extern void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ; + +extern void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ; + +extern void USART_SetRTSEnabled(Usart *usart, uint8_t enabled); + +extern void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ; + +extern uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ; + +extern uint8_t USART_IsDataAvailable( Usart *usart ) ; + +extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); + +extern void USART_PutChar( Usart *usart, uint8_t c ) ; + +extern uint32_t USART_IsRxReady( Usart *usart ) ; + +extern uint8_t USART_GetChar( Usart *usart ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/video.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/video.h new file mode 100644 index 000000000..f0bb6f9ff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/video.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _VIDEO_H +#define _VIDEO_H + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** Type of video is YUV */ +#define YUV 0 +/** Type of video is RGB */ +#define RGB 1 + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct _isi_Video +{ + /** LCD Vertical Size */ + uint32_t lcd_vsize; + /** LCD Horizontal Size*/ + uint32_t lcd_hsize; + /** LCD Number of Bit Per Pixel*/ + uint32_t lcd_nbpp; + /** LCD Frame Buffer Address*/ + uint32_t lcd_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t Isi_fbd_base; + /** Start of Line Delay*/ + uint32_t Hblank; + /** Start of frame Delay */ + uint32_t Vblank; + /** Vertical size of the Image sensor [0..2047]*/ + uint32_t codec_vsize; + /** Horizontal size of the Image sensor [0..2047]*/ + uint32_t codec_hsize; + /** Base address for codec DMA*/ + uint32_t codec_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t codec_fbd_base; + /** Buffer index */ + uint32_t IsiPrevBuffIndex; + /** Type of video */ + uint8_t rgb_or_yuv; +}isi_Video, *pIsi_Video; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/wdt.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/wdt.h new file mode 100644 index 000000000..28c30fb04 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/include/wdt.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * Interface for Watchdog Timer (WDT) controller. + * + * \section Usage + * -# Enable watchdog with given mode using \ref WDT_Enable(). + * -# Disable watchdog using \ref WDT_Disable() + * -# Restart the watchdog using \ref WDT_Restart(). + * -# Get watchdog status using \ref WDT_GetStatus(). + * -# Caculate watchdog period value using \ref WDT_GetPeriod(). + */ + +#ifndef _WDT_ +#define _WDT_ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ; + +extern void WDT_Disable( Wdt* pWDT ) ; + +extern void WDT_Restart( Wdt* pWDT ) ; + +extern uint32_t WDT_GetStatus( Wdt* pWDT ) ; + +extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _WDT_ */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Initialized.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Initialized.c new file mode 100644 index 000000000..985bd09c6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Initialized.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported function + *----------------------------------------------------------------------------*/ + +/** + * Invoked after the USB driver has been initialized. By default, configures + * the UDP/UDPHS interrupt. + */ +void USBDCallbacks_Initialized(void) +{ +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Resumed.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Resumed.c new file mode 100644 index 000000000..68cc8fda1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Resumed.c @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "USBD_LEDs.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Invoked when the USB device leaves the Suspended state. By default, + * configures the LEDs. + */ +void USBDCallbacks_Resumed(void) +{ +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Suspended.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Suspended.c new file mode 100644 index 000000000..018b9d18e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBDCallbacks_Suspended.c @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "USBD_LEDs.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Invoked when the USB device gets suspended. By default, turns off all LEDs. + */ +void USBDCallbacks_Suspended(void) +{ + +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBD_HAL.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBD_HAL.c new file mode 100644 index 000000000..e90d053c3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/USBD_HAL.c @@ -0,0 +1,2191 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + + \file + + Implementation of USB device functions on a UDP controller. + + See \ref usbd_api_method USBD API Methods. +*/ + +/** \addtogroup usbd_hal + *@{*/ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" +#include "USBD_HAL.h" + +#include +#include +#include +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +#define DMA + +/** Maximum number of endpoints interrupts. */ +#define NUM_IT_MAX \ + ((UDPHS->UDPHS_IPFEATURES & UDPHS_IPFEATURES_EPT_NBR_MAX_Msk) ? \ + (UDPHS->UDPHS_IPFEATURES & UDPHS_IPFEATURES_EPT_NBR_MAX_Msk) : 16) +/** Maximum number of endpoint DMA interrupts */ +#define NUM_IT_MAX_DMA \ + ((UDPHS->UDPHS_IPFEATURES \ + & UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk) \ + >>UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) +/** Bits that should be shifted to access DMA control bits. */ +#define SHIFT_DMA 24 +/** Bits that should be shifted to access interrupt bits. */ +#define SHIFT_INTERUPT 8 + +/** Max size of the FMA FIFO */ +#define DMA_MAX_FIFO_SIZE (65536/1) +/** fifo space size in DW */ +#define EPT_VIRTUAL_SIZE 16384 + +/** + * \section endpoint_states_sec "UDP Endpoint states" + * + * This page lists the endpoint states. + * + * \subsection States + * - UDPHS_ENDPOINT_DISABLED + * - UDPHS_ENDPOINT_HALTED + * - UDPHS_ENDPOINT_IDLE + * - UDPHS_ENDPOINT_SENDING + * - UDPHS_ENDPOINT_RECEIVING + * - UDPHS_ENDPOINT_SENDINGM + * - UDPHS_ENDPOINT_RECEIVINGM + */ + +/** Endpoint states: Endpoint is disabled */ +#define UDPHS_ENDPOINT_DISABLED 0 +/** Endpoint states: Endpoint is halted (i.e. STALLs every request) */ +#define UDPHS_ENDPOINT_HALTED 1 +/** Endpoint states: Endpoint is idle (i.e. ready for transmission) */ +#define UDPHS_ENDPOINT_IDLE 2 +/** Endpoint states: Endpoint is sending data */ +#define UDPHS_ENDPOINT_SENDING 3 +/** Endpoint states: Endpoint is receiving data */ +#define UDPHS_ENDPOINT_RECEIVING 4 +/** Endpoint states: Endpoint is sending MBL */ +#define UDPHS_ENDPOINT_SENDINGM 5 +/** Endpoint states: Endpoint is receiving MBL */ +#define UDPHS_ENDPOINT_RECEIVINGM 6 + +/** Get Number of buffer in Multi-Buffer-List + * \param i input index + * \param o output index + * \param size list size + */ +#define MBL_NbBuffer(i, o, size) (((i)>(o))?((i)-(o)):((i)+(size)-(o))) + +/** Buffer list is full */ +#define MBL_FULL 1 +/** Buffer list is null */ +#define MBL_NULL 2 + +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ + +/** Describes header for UDP endpoint transfer. */ +typedef struct { + /** Optional callback to invoke when the transfer completes. */ + void* fCallback; + /** Optional argument to the callback function. */ + void* pArgument; + /** Transfer type */ + uint8_t transType; + /* Reserved to 32-b aligned */ + uint8_t reserved[3]; +} TransferHeader; + +/** Describes a transfer on a UDP endpoint. */ +typedef struct { + + /** Optional callback to invoke when the transfer completes. */ + TransferCallback fCallback; + /** Optional argument to the callback function. */ + void *pArgument; + /** Transfer type */ + uint8_t transType; + uint8_t reserved[3]; + /** Number of bytes which have been written into the UDP internal FIFO + * buffers. */ + int32_t buffered; + /** Pointer to a data buffer used for emission/reception. */ + uint8_t *pData; + /** Number of bytes which have been sent/received. */ + int32_t transferred; + /** Number of bytes which have not been buffered/transferred yet. */ + int32_t remaining; +} Transfer; + +/** Describes Multi Buffer List transfer on a UDP endpoint. */ +typedef struct { + /** Optional callback to invoke when the transfer completes. */ + MblTransferCallback fCallback; + /** Optional argument to the callback function. */ + void *pArgument; + /** Transfer type */ + uint8_t transType; + /** List state (OK, FULL, NULL) (run time) */ + uint8_t listState; + /** Multi-Buffer List size */ + uint16_t listSize; + /** Pointer to multi-buffer list */ + USBDTransferBuffer *pMbl; + /** Offset number of buffers to start transfer */ + uint16_t offsetSize; + /** Current processing buffer index (run time) */ + uint16_t outCurr; + /** Loast loaded buffer index (run time) */ + uint16_t outLast; + /** Current buffer for input (run time) */ + uint16_t inCurr; +} MblTransfer; + +/** + * Describes the state of an endpoint of the UDP controller. + */ +typedef struct { + + /* CSR */ + /** Current endpoint state. */ + volatile uint8_t state; + /** Current reception bank (0 or 1). */ + volatile uint8_t bank; + /** Maximum packet size for the endpoint. */ + volatile uint16_t size; + /** Describes an ongoing transfer (if current state is either + * UDPHS_ENDPOINT_SENDING or UDPHS_ENDPOINT_RECEIVING) */ + union { + TransferHeader transHdr; + Transfer singleTransfer; + MblTransfer mblTransfer; + } transfer; + /** Special case for send a ZLP */ + uint32_t sendZLP; +} Endpoint; + +/** + * DMA Descriptor. + */ +typedef struct { + void *pNxtDesc; + void *pAddr; + uint32_t dwCtrl; + uint32_t dw; +} UdphsDmaDescriptor; + +/*--------------------------------------------------------------------------- + * Internal variables + *---------------------------------------------------------------------------*/ + +/** Holds the internal state for each endpoint of the UDP. */ +static Endpoint endpoints[CHIP_USB_NUMENDPOINTS]; + +/** 7.1.20 Test Mode Support + * Test codes for the USB HS test mode. */ +static const char test_packet_buffer[] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9 + 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8 + 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJJJKKKK * 8 + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8 + 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8 + 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK * 10}, JK +}; + +/** Force FS mode */ +static const uint8_t forceUsbFS = 0; + +/** DMA link list */ +static UdphsDmaDescriptor dmaLL[5]; +static UdphsDmaDescriptor *pDmaLL; + +/*--------------------------------------------------------------------------- + * Internal Functions + *---------------------------------------------------------------------------*/ + +/** + * Enables the clock of the UDP peripheral. + * \return 1 if peripheral status changed. + */ +static uint8_t UDPHS_EnablePeripheralClock(void) +{ + if (!PMC_IsPeriphEnabled(ID_UDPHS)) { + PMC_EnablePeripheral(ID_UDPHS); + return 1; + } + return 0; +} + +/** + * Disables the UDP peripheral clock. + */ +static inline void UDPHS_DisablePeripheralClock(void) +{ + PMC_DisablePeripheral(ID_UDPHS); +} + +/** + * Enables the 480MHz USB clock. + */ +static inline void UDPHS_EnableUsbClock(void) +{ + Pmc *pPmc = PMC; + /* Enable 480Mhz UPLL */ + pPmc->CKGR_UCKR |= CKGR_UCKR_UPLLEN + | CKGR_UCKR_UPLLCOUNT(0x3) + | CKGR_UCKR_BIASCOUNT(0x1); + /* Wait until UPLL is locked */ + while((pPmc->PMC_SR & PMC_SR_LOCKU) == 0); +} + +/** + * Disables the 480MHz USB clock. + */ +static inline void UDPHS_DisableUsbClock(void) +{ + Pmc *pPmc = PMC; + /* Disable System Clock */ + //pPmc->PMC_SCDR = PMC_SCDR_UDP; + pPmc->CKGR_UCKR &= ~(uint32_t)CKGR_UCKR_UPLLEN; +} + +/** + * Enables the BIAS. + */ +static inline void UDPHS_EnableBIAS(void) +{ + Pmc *pPmc = PMC; + pPmc->CKGR_UCKR |= CKGR_UCKR_BIASEN; +} + +/** + * Disables the BIAS. + */ +static inline void UDPHS_DisableBIAS(void) +{ + Pmc *pPmc = PMC; + pPmc->CKGR_UCKR &= ~(uint32_t)CKGR_UCKR_BIASEN; +} + +/** + * Handles a completed transfer on the given endpoint, invoking the + * configured callback if any. + * \param bEndpoint Number of the endpoint for which the transfer has completed. + * \param bStatus Status code returned by the transfer operation + */ +static void UDPHS_EndOfTransfer(uint8_t bEndpoint, uint8_t bStatus) +{ + Endpoint *pEp = &(endpoints[bEndpoint]); + + /* Check that endpoint was sending or receiving data */ + if ( (pEp->state == UDPHS_ENDPOINT_RECEIVING) + || (pEp->state == UDPHS_ENDPOINT_SENDING) ) + { + Transfer *pXfr = (Transfer*)&(pEp->transfer); + uint32_t transferred = pXfr->transferred; + uint32_t remaining = pXfr->remaining + pXfr->buffered; + + TRACE_DEBUG_WP("EoT "); + if (pEp->state == UDPHS_ENDPOINT_SENDING) + pEp->sendZLP = 0; + pEp->state = UDPHS_ENDPOINT_IDLE; + pXfr->pData = 0; + pXfr->transferred = -1; + pXfr->buffered = -1; + pXfr->remaining = -1; + + /* Invoke callback */ + if (pXfr->fCallback) + { + pXfr->fCallback(pXfr->pArgument, bStatus, transferred, remaining); + } + else + { + TRACE_DEBUG_WP("NoCB "); + } + } + else if ( (pEp->state == UDPHS_ENDPOINT_RECEIVINGM) + || (pEp->state == UDPHS_ENDPOINT_SENDINGM) ) + { + MblTransfer *pXfr = (MblTransfer*)&(pEp->transfer); + TRACE_DEBUG_WP("EoMT "); + + pEp->state = UDPHS_ENDPOINT_IDLE; + pXfr->listState = 0; + pXfr->outCurr = pXfr->inCurr = pXfr->outLast = 0; + /* Invoke callback */ + if (pXfr->fCallback) + { + pXfr->fCallback(pXfr->pArgument, bStatus); + } + else + { + TRACE_DEBUG_WP("NoCB "); + } + } +} + +/** + * Update multi-buffer-transfer descriptors. + * \param pTransfer Pointer to instance MblTransfer. + * \param size Size of bytes that processed. + * \param forceEnd Force the buffer END. + * \return 1 if current buffer ended. + */ +static uint8_t UDPHS_MblUpdate(MblTransfer *pTransfer, + USBDTransferBuffer * pBi, + uint16_t size, + uint8_t forceEnd) +{ + /* Update transfer descriptor */ + pBi->remaining -= size; + /* Check if list NULL */ + if (pTransfer->listState == MBL_NULL) { + return 1; + } + /* Check if current buffer ended */ + if (pBi->remaining == 0 || forceEnd || size == 0) { + + /* Process to next buffer */ + if ((++ pTransfer->outCurr) == pTransfer->listSize) + pTransfer->outCurr = 0; + /* Check buffer NULL case */ + if (pTransfer->outCurr == pTransfer->inCurr) + pTransfer->listState = MBL_NULL; + else { + pTransfer->listState = 0; + /* Continue transfer, prepare for next operation */ + pBi = &pTransfer->pMbl[pTransfer->outCurr]; + pBi->buffered = 0; + pBi->transferred = 0; + pBi->remaining = pBi->size; + } + return 1; + } + return 0; +} + +/** + * Transfers a data payload from the current tranfer buffer to the endpoint + * FIFO + * \param bEndpoint Number of the endpoint which is sending data. + */ +static uint8_t UDPHS_MblWriteFifo(uint8_t bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->outCurr]); + uint8_t *pFifo; + int32_t size; + + volatile uint8_t * pBytes; + volatile uint8_t bufferEnd = 1; + + /* Get the number of bytes to send */ + size = pEndpoint->size; + if (size > pBi->remaining) size = pBi->remaining; + + TRACE_DEBUG_WP("w%d.%d ", pTransfer->outCurr, size); + + /* Record last accessed buffer */ + pTransfer->outLast = pTransfer->outCurr; + + pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]); + pBi->buffered += size; + bufferEnd = UDPHS_MblUpdate(pTransfer, pBi, size, 0); + + /* Write packet in the FIFO buffer */ + pFifo = (uint8_t*)((uint32_t*)UDPHS_RAM_ADDR + + (EPT_VIRTUAL_SIZE * bEndpoint)); + if (size) { + int32_t c8 = size >> 3; + int32_t c1 = size & 0x7; + for (; c8; c8 --) { + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + } + for (; c1; c1 --) { + *(pFifo++) = *(pBytes ++); + } + } + return bufferEnd; +} + +#if 0 +/** + * Transfers a data payload from an endpoint FIFO to the current transfer + * buffer, if NULL packet received, the current buffer is ENDed. + * \param bEndpoint Endpoint number. + * \param wPacketSize Size of received data packet */ + * \return 1 if the buffer ENDed. */ + */ +static uint8_t UDPHS_MblReadFifo(uint8_t bEndpoint, uint16_t wPacketSize) +{ + + return 0; +} +*/ +#endif +/** + * Transfers a data payload from the current tranfer buffer to the endpoint + * FIFO + * \param bEndpoint Number of the endpoint which is sending data. + */ +static void UDPHS_WritePayload(uint8_t bEndpoint, int32_t size) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + uint8_t *pFifo; + + /* Get the number of bytes to send */ + if (size > pTransfer->remaining) + { + size = pTransfer->remaining; + } + + /* Update transfer descriptor information */ + pTransfer->buffered += size; + pTransfer->remaining -= size; + + /* Write packet in the FIFO buffer */ + pFifo = (uint8_t*)((uint32_t*)UDPHS_RAM_ADDR + + (EPT_VIRTUAL_SIZE * bEndpoint)); + for (; size; size --) + { + *(pFifo ++) = *(pTransfer->pData ++); + } +} + +/** + * Transfers a data payload from an endpoint FIFO to the current transfer buffer + * \param bEndpoint Endpoint number. + * \param wPacketSize Size of received data packet + */ +static void UDPHS_ReadPayload(uint8_t bEndpoint, int32_t wPacketSize) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + uint8_t *pFifo; + /* Check that the requested size is not bigger than the remaining transfer */ + if (wPacketSize > pTransfer->remaining) { + + pTransfer->buffered += wPacketSize - pTransfer->remaining; + wPacketSize = pTransfer->remaining; + } + + /* Update transfer descriptor information */ + pTransfer->remaining -= wPacketSize; + pTransfer->transferred += wPacketSize; + + /* Retrieve packet */ + pFifo = (uint8_t*)((uint32_t*)UDPHS_RAM_ADDR + + (EPT_VIRTUAL_SIZE * bEndpoint)); + while (wPacketSize > 0) + { + *(pTransfer->pData ++) = *(pFifo ++); + wPacketSize--; + } +} + +/** + * Received SETUP packet from endpoint 0 FIFO + * \param pRequest Generic USB SETUP request sent over Control endpoints + */ +static void UDPHS_ReadRequest(USBGenericRequest *pRequest) +{ + uint32_t *pData = (uint32_t *)(void*)pRequest; + volatile uint32_t *pFifo; + pFifo = (volatile uint32_t*)UDPHS_RAM_ADDR; + *pData ++ = *pFifo; + pFifo = (volatile uint32_t*)UDPHS_RAM_ADDR; + *pData = *pFifo; +} + +/** + * Endpoint interrupt handler. + * Handle IN/OUT transfers, received SETUP packets and STALLing + * \param bEndpoint Index of endpoint + */ +static void UDPHS_EndpointHandler(uint8_t bEndpoint) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pEpt = &pUdp->UDPHS_EPT[bEndpoint]; + //UdphsDma *pDma = &pUdp->UDPHS_DMA[bEndpoint]; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + //MblTransfer *pMblt = (MblTransfer*)&(pEp->transfer); + uint32_t status = pEpt->UDPHS_EPTSTA; + uint32_t type = pEpt->UDPHS_EPTCFG & UDPHS_EPTCFG_EPT_TYPE_Msk; + uint32_t reqBuf[2]; + USBGenericRequest *pReq = (USBGenericRequest *)reqBuf; + uint16_t wPktSize; + + TRACE_DEBUG_WP("Ep%d ", bEndpoint); + //TRACE_DEBUG_WP("St:%x ", status); + /* IN packet sent */ + if ( (pEpt->UDPHS_EPTCTL & UDPHS_EPTCTL_TX_PK_RDY) + && (0 == (status & UDPHS_EPTSTA_TX_PK_RDY)) ) + { + TRACE_DEBUG_WP("Wr "); + + /* Multi-buffer-list transfer state */ + if ( pEp->state == UDPHS_ENDPOINT_SENDINGM ) + { + } + /* Sending state */ + else if ( pEp->state == UDPHS_ENDPOINT_SENDING ) + { + if (pXfr->buffered) + { + pXfr->transferred += pXfr->buffered; + pXfr->buffered = 0; + } + if((pXfr->transferred % pEp->size == 0) && ( pXfr->remaining == 0) && ( pXfr->transferred > 0)&&(pEp->sendZLP == 0)) + { + pEp->sendZLP = 1; // Force ZLP transmission in total length is a multiple of endpoint size + + } + + if ( pXfr->buffered == 0 + && pXfr->transferred == 0 + && pXfr->remaining == 0 + && pEp->sendZLP == 0 ) + { + pEp->sendZLP = 1; + } + + /* End of Xfr ? */ + if ( pXfr->remaining + || pEp->sendZLP == 1) + { + if(pEp->sendZLP == 1) + { + // A null packet will be send, keep trace of it : Change this value only if ZLP will be send!!! + pEp->sendZLP = 2; + } + + /* Transfer remaining */ + TRACE_DEBUG_WP("%d ", pEp->size); + /* Send next packet */ + UDPHS_WritePayload(bEndpoint, pEp->size); + pEpt->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY; + } + else + { + TRACE_DEBUG_WP("l%d ", pXfr->transferred); + /* Disable interrupt on none-control EP */ + if (type != UDPHS_EPTCFG_EPT_TYPE_CTRL8) + { + pUdp->UDPHS_IEN &= ~(UDPHS_IEN_EPT_0 << bEndpoint); + } + pEpt->UDPHS_EPTCTLDIS = UDPHS_EPTCTLDIS_TX_PK_RDY; + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + pEp->sendZLP = 0; + } + } + else + { + TRACE_DEBUG("Err Wr %d\n\r", pEp->sendZLP); + } + } + /* OUT packet received */ + if ( UDPHS_EPTSTA_RX_BK_RDY & status ) + { + TRACE_DEBUG_WP("Rd "); + + /* NOT in receiving state */ + if (pEp->state != UDPHS_ENDPOINT_RECEIVING) + { + /* Check if ACK received on a Control EP */ + if ( (UDPHS_EPTCFG_EPT_TYPE_CTRL8 == type) + && (0 == (status & UDPHS_EPTSTA_BYTE_COUNT_Msk)) ) + { + TRACE_DEBUG_WP("Ack "); + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY; + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + /* data has been STALLed */ + else if (UDPHS_EPTSTA_FRCESTALL & status) + { + TRACE_DEBUG_WP("Discard "); + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY; + } + /* NAK the data */ + else + { + TRACE_DEBUG_WP("Nak "); + pUdp->UDPHS_IEN &= ~(UDPHS_IEN_EPT_0 << bEndpoint); + } + } + /* In read state */ + else + { + wPktSize = (uint16_t)((status & UDPHS_EPTSTA_BYTE_COUNT_Msk) >> UDPHS_EPTSTA_BYTE_COUNT_Pos); + + TRACE_DEBUG_WP("%d ", wPktSize); + UDPHS_ReadPayload(bEndpoint, wPktSize); + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY; + /* Check if transfer is finished */ + if (pXfr->remaining == 0 || wPktSize < pEp->size) + { + pEpt->UDPHS_EPTCTLDIS = UDPHS_EPTCTLDIS_RX_BK_RDY; + + /* Disable interrupt if not control EP */ + if (UDPHS_EPTCFG_EPT_TYPE_CTRL8 != type) + { + pUdp->UDPHS_IEN &= ~(UDPHS_IEN_EPT_0 << bEndpoint); + } + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + } + } + /* STALL sent */ + if ( UDPHS_EPTSTA_STALL_SNT & status ) + { + /* Acknowledge */ + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_STALL_SNT; + + /* ISO error */ + if (type == UDPHS_EPTCFG_EPT_TYPE_ISO) + { + TRACE_WARNING("IsoE[%d]\n\r", bEndpoint); + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + } + /* If EP is not halted, clear STALL */ + else + { + TRACE_WARNING("Stall[%d]\n\r", bEndpoint); + + if (pEp->state != UDPHS_ENDPOINT_HALTED) + { + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_FRCESTALL; + } + } + } + /* SETUP packet received */ + if ( UDPHS_EPTSTA_RX_SETUP & status ) + { + /* If a transfer was pending, complete it + Handles the case where during the status phase of a control write + transfer, the host receives the device ZLP and ack it, but the ack + is not received by the device */ + if (pEp->state == UDPHS_ENDPOINT_RECEIVING + || pEp->state == UDPHS_ENDPOINT_RECEIVINGM + || pEp->state == UDPHS_ENDPOINT_SENDING + || pEp->state == UDPHS_ENDPOINT_SENDINGM) + { + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + + /* ISO Err Flow */ + if (type == UDPHS_EPTCFG_EPT_TYPE_ISO) + { + TRACE_WARNING("IsoFE[%d]\n\r", bEndpoint); + /* Acknowledge setup packet */ + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_SETUP; + } + else + { + TRACE_DEBUG_WP("Stup "); + + /* Copy setup */ + UDPHS_ReadRequest(pReq); + /* Acknowledge setup packet */ + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_SETUP; + /* Handler */ + USBD_RequestHandler(bEndpoint, pReq); + } + } +} +#ifdef DMA +/** + * DMA Single transfer + * \param bEndpoint EP number. + * \pXfr Pointer to transfer instance. + * \dwCfg DMA Control configuration (excluding length). + */ +static inline void UDPHS_DmaSingle(uint8_t bEndpoint, Transfer *pXfr, uint32_t dwCfg) +{ + Udphs *pUdp = UDPHS; + + /* Single transfer */ + CP15_coherent_dcache_for_dma ((uint32_t)&pXfr->pData[pXfr->transferred], ((uint32_t)&pXfr->pData[pXfr->transferred]) + pXfr->buffered); + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS = + (uint32_t)&pXfr->pData[pXfr->transferred]; + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS; + /* Interrupt enable */ + pUdp->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint); + + TRACE_DEBUG_WP("Dma[B%d:T%d] ", pXfr->buffered, pXfr->transferred); + /* DMA Configure */ + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0 + | UDPHS_DMACONTROL_BUFF_LENGTH(pXfr->buffered) + | dwCfg; +} +/** + * Endpoint DMA interrupt handler. + * This function handles DMA interrupts. + * \param bEndpoint Index of endpoint + */ +static void UDPHS_DmaHandler(uint8_t bEndpoint) +{ + Udphs *pUdp = UDPHS; + //UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint]; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + + uint32_t dwDmaSr; + int32_t iRemain, iXfred; + uint8_t bRc = USBD_STATUS_SUCCESS; + + CP15_flush_dcache_for_dma ((uint32_t)&pXfr->pData[pXfr->transferred], ((uint32_t)&pXfr->pData[pXfr->transferred]) + pXfr->buffered); + dwDmaSr = pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS; + TRACE_DEBUG_WP("iDma%d,%x ", bEndpoint, dwDmaSr); + /* Mbl transfer */ + if (pEp->state == UDPHS_ENDPOINT_SENDINGM) + { + /* Not implemented */ + return; + } + else if (pEp->state == UDPHS_ENDPOINT_RECEIVINGM) + { + /* Not implemented */ + return; + } + + /* Disable DMA interrupt to avoid receiving 2 (B_EN and TR_EN) */ + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL &= ~(UDPHS_DMACONTROL_END_TR_EN + |UDPHS_DMACONTROL_END_B_EN); + if (UDPHS_DMASTATUS_END_BF_ST & dwDmaSr) + { + TRACE_DEBUG_WP("EoDmaB "); + /* BUFF_COUNT holds the number of untransmitted bytes. + BUFF_COUNT is equal to zero in case of good transfer */ + iRemain = (dwDmaSr & UDPHS_DMASTATUS_BUFF_COUNT_Msk) + >> UDPHS_DMASTATUS_BUFF_COUNT_Pos; + TRACE_DEBUG_WP("C%d ", iRemain); + iXfred = pXfr->buffered - iRemain; + + pXfr->transferred += iXfred; + pXfr->buffered = iRemain; + pXfr->remaining -= iXfred; + TRACE_DEBUG_WP("[B%d:T%d:R%d] ", pXfr->buffered, pXfr->transferred, pXfr->remaining); + /* There is still data */ + if (pXfr->remaining + pXfr->buffered > 0) + { + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + { + pXfr->buffered = DMA_MAX_FIFO_SIZE; + } + else + { + pXfr->buffered = pXfr->remaining; + } + /* Single transfer again */ + UDPHS_DmaSingle(bEndpoint, pXfr, UDPHS_DMACONTROL_END_TR_EN + | UDPHS_DMACONTROL_END_TR_IT + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT + | UDPHS_DMACONTROL_CHANN_ENB); + } + } + else if (UDPHS_DMASTATUS_END_TR_ST & dwDmaSr) + { + TRACE_DEBUG_WP("EoDmaT "); + pXfr->transferred = pXfr->buffered - + ((dwDmaSr & UDPHS_DMASTATUS_BUFF_COUNT_Msk) + >> UDPHS_DMASTATUS_BUFF_COUNT_Pos); + pXfr->remaining = 0; + + TRACE_DEBUG_WP("[B%d:T%d] ", pXfr->buffered, pXfr->transferred); + } + else + { + TRACE_ERROR("UDPHS_DmaHandler: ST 0x%X\n\r", (unsigned int)dwDmaSr); + bRc = USBD_STATUS_ABORTED; + } + /* Callback */ + if (pXfr->remaining == 0) + { + UDPHS_EndOfTransfer(bEndpoint, bRc); + + } + +} +#endif +/** + * Sends data through a USB endpoint. Sets up the transfer descriptor, + * writes one or two data payloads (depending on the number of FIFO bank + * for the endpoint) and then starts the actual transfer. The operation is + * complete when all the data has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param pEndpoint Pointer to Endpoint struct. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +static inline uint8_t UDPHS_Write(uint8_t bEndpoint, + const void *pData, + uint32_t dLength) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint]; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + /* Return if busy */ + if (pEp->state != UDPHS_ENDPOINT_IDLE) + { + return USBD_STATUS_LOCKED; + } + /* Sending state */ + pEp->state = UDPHS_ENDPOINT_SENDING; + TRACE_DEBUG_WP("Wr%d(%d) ", bEndpoint, dLength); + pEp->sendZLP = 0; + /* Setup transfer descriptor */ + pXfr->pData = (void*) pData; + pXfr->remaining = dLength; + pXfr->buffered = 0; + pXfr->transferred = 0; + #ifdef DMA + /* 1. DMA supported, 2. Not ZLP */ + if (CHIP_USB_ENDPOINTS_DMA(bEndpoint) + && pXfr->remaining > 0) + { + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + { + /* Transfer the max */ + pXfr->buffered = DMA_MAX_FIFO_SIZE; + } + else + { + /* Good size */ + pXfr->buffered = pXfr->remaining; + } + /* Single transfer */ + UDPHS_DmaSingle(bEndpoint, pXfr, UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT + | UDPHS_DMACONTROL_CHANN_ENB); + return USBD_STATUS_SUCCESS; + } + #endif + + /* Enable IT */ + pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint ); + pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_TX_PK_RDY; + return USBD_STATUS_SUCCESS; +} + +/** + * Sends data through a USB endpoint. Sets up the transfer descriptor list, + * writes one or two data payloads (depending on the number of FIFO bank + * for the endpoint) and then starts the actual transfer. The operation is + * complete when all the transfer buffer in the list has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param pEndpoint Pointer to Endpoint struct. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +static inline uint8_t UDPHS_AddWr(uint8_t bEndpoint, + const void *pData, + uint32_t dLength) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint]; + + Endpoint *pEp = &(endpoints[bEndpoint]); + MblTransfer *pMbl = (MblTransfer*)&(pEp->transfer); + USBDTransferBuffer *pTx; + /* Check parameter */ + if (dLength >= 0x10000) + { + return USBD_STATUS_INVALID_PARAMETER; + } + /* Data in process */ + if (pEp->state > UDPHS_ENDPOINT_IDLE) + { /* MBL transfer */ + if (pMbl->transType) + { + if (pMbl->listState == MBL_FULL) + { + return USBD_STATUS_LOCKED; + } + } + else + { + return USBD_STATUS_LOCKED; + } + } + + TRACE_DEBUG_WP("AddW%d(%d) ", bEndpoint, dLength); + /* Add buffer to buffer list and update index */ + pTx = &(pMbl->pMbl[pMbl->inCurr]); + pTx->pBuffer = (uint8_t*)pData; + pTx->size = pTx->remaining = dLength; + pTx->transferred = pTx->buffered = 0; + /* Update input index */ + if (pMbl->inCurr >= (pMbl->listSize-1)) pMbl->inCurr = 0; + else pMbl->inCurr ++; + if (pMbl->inCurr == pMbl->outCurr) pMbl->listState = MBL_FULL; + else pMbl->listState = 0; + /* Start sending when offset achieved */ + if (MBL_NbBuffer(pMbl->inCurr, pMbl->outCurr, pMbl->listSize) + >= pMbl->offsetSize + && pEp->state == UDPHS_ENDPOINT_IDLE) + { + uint8_t nbBanks = CHIP_USB_ENDPOINTS_BANKS(bEndpoint); + + /* Change state */ + pEp->state = UDPHS_ENDPOINT_SENDINGM; + + TRACE_DEBUG_WP("StartM "); + + /* Fill data into FIFO */ + for (; + nbBanks && pMbl->pMbl[pMbl->inCurr].remaining; + nbBanks --) + { + UDPHS_MblWriteFifo(bEndpoint); + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY; + } + + /* Enable interrupt */ + pUdp->UDPHS_IEN |= (UDPHS_IEN_EPT_0 << bEndpoint); + pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_TX_PK_RDY; + + } + + return USBD_STATUS_SUCCESS; +} + +/** + * Reads incoming data on an USB endpoint This methods sets the transfer + * descriptor and activate the endpoint interrupt. The actual transfer is + * then carried out by the endpoint interrupt handler. The Read operation + * finishes either when the buffer is full, or a short packet (inferior to + * endpoint maximum size) is received. + * + * *The buffer must be kept allocated until the transfer is finished*. + * \param bEndpoint Endpoint number. + * \param pData Pointer to a data buffer. + * \param dLength Size of the data buffer in bytes. + * \return USBD_STATUS_SUCCESS if the read operation has been started; + * otherwise, the corresponding error code. + */ +static inline uint8_t UDPHS_Read(uint8_t bEndpoint, + void *pData, + uint32_t dLength) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint]; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + /* Return if busy */ + if (pEp->state != UDPHS_ENDPOINT_IDLE) + { + return USBD_STATUS_LOCKED; + } + /* Receiving state */ + pEp->state = UDPHS_ENDPOINT_RECEIVING; + + TRACE_DEBUG_WP("Rd%d(%d) ", bEndpoint, dLength); + /* Setup transfer descriptor */ + pXfr->pData = (void*) pData; + pXfr->remaining = dLength; + pXfr->buffered = 0; + pXfr->transferred = 0; + + #ifdef DMA + /* If: 1. DMA supported, 2. Has data */ + if (CHIP_USB_ENDPOINTS_DMA(bEndpoint) + && pXfr->remaining > 0) + { + /* DMA XFR size adjust */ + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + pXfr->buffered = DMA_MAX_FIFO_SIZE; + else + pXfr->buffered = pXfr->remaining; + /* Single transfer */ + UDPHS_DmaSingle(bEndpoint, pXfr, UDPHS_DMACONTROL_END_TR_EN + | UDPHS_DMACONTROL_END_TR_IT + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT + | UDPHS_DMACONTROL_CHANN_ENB); + return USBD_STATUS_SUCCESS; + } + #endif + + /* Enable IT */ + pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint ); + pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RX_BK_RDY; + + return USBD_STATUS_SUCCESS; +} +#if 0 +/** + * Reads incoming data on an USB endpoint This methods sets the transfer + * descriptor and activate the endpoint interrupt. The actual transfer is + * then carried out by the endpoint interrupt handler. The Read operation + * finishes either when the buffer is full, or a short packet (inferior to + * endpoint maximum size) is received. + * + * *The buffer must be kept allocated until the transfer is finished*. + * \param bEndpoint Endpoint number. + * \param pData Pointer to a data buffer. + * \param dLength Size of the data buffer in bytes. + * \return USBD_STATUS_SUCCESS if the read operation has been started; + * otherwise, the corresponding error code. + */ +static inline uint8_t UDPHS_AddRd(uint8_t bEndpoint, + void *pData, + uint32_t dLength) +{ + return USBD_STATUS_SW_NOT_SUPPORTED; +} +#endif +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ +extern void USBD_IrqHandler(void); +/** + * USBD (UDP) interrupt handler + * Manages device resume, suspend, end of bus reset. + * Forwards endpoint events to the appropriate handler. + */ +void USBD_IrqHandler(void) +{ + Udphs *pUdp = UDPHS; + + uint32_t status; + uint8_t numIt; + + status = pUdp->UDPHS_INTSTA; + status &= pUdp->UDPHS_IEN; + + /* Handle all UDPHS interrupts */ + TRACE_DEBUG_WP("\n\r%c ", USBD_HAL_IsHighSpeed() ? 'H' : 'F'); + while( status ) + { + /* SOF */ + if (status & UDPHS_INTSTA_INT_SOF) + { + TRACE_DEBUG_WP("SOF "); + /* SOF handler */ + //USBD_SofHandler(); + + /* Acknowledge interrupt */ + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF; + status &= ~(uint32_t)UDPHS_INTSTA_INT_SOF; + } + /* Suspend, treated last */ + else if (status == UDPHS_INTSTA_DET_SUSPD) + { + TRACE_WARNING_WP("Susp "); + /* Enable wakeup */ + pUdp->UDPHS_IEN |= (UDPHS_IEN_WAKE_UP | UDPHS_IEN_ENDOFRSM); + pUdp->UDPHS_IEN &= ~(uint32_t)UDPHS_IEN_DET_SUSPD; + + /* Acknowledge interrupt */ + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD | UDPHS_CLRINT_WAKE_UP; + + USBD_SuspendHandler(); + } + /* Resume */ + else if ( (status & UDPHS_INTSTA_WAKE_UP) + || (status & UDPHS_INTSTA_ENDOFRSM) ) + { + USBD_ResumeHandler(); + + TRACE_INFO_WP("Rsm "); + + /* Acknowledge interrupt */ + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP + | UDPHS_CLRINT_ENDOFRSM + | UDPHS_CLRINT_DET_SUSPD; + + pUdp->UDPHS_IEN |= UDPHS_IEN_ENDOFRSM | UDPHS_IEN_DET_SUSPD; + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_ENDOFRSM; + pUdp->UDPHS_IEN &= ~(uint32_t)UDPHS_IEN_WAKE_UP; + } + /* Bus reset */ + else if (status & UDPHS_INTSTA_ENDRESET) + { + TRACE_DEBUG_WP("EoB "); + /* Flush and enable the suspend interrupt */ + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_DET_SUSPD; + pUdp->UDPHS_IEN |= UDPHS_IEN_DET_SUSPD; + + /* Reset handler */ + USBD_ResetHandler(); + + /* Acknowledge interrupt */ + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET; + } + /* Upstream resume */ + else if (status & UDPHS_INTSTA_UPSTR_RES) + { + TRACE_DEBUG_WP("ExtRes "); + /* Acknowledge interrupt */ + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES; + } + /* Endpoints */ + else + { + #ifdef DMA + for (numIt = 0; numIt < NUM_IT_MAX; numIt ++) + { + if (status & (1 << SHIFT_DMA << numIt)) + { + UDPHS_DmaHandler(numIt); + } + else if (status & (UDPHS_INTSTA_EPT_0 << numIt)) + { + UDPHS_EndpointHandler(numIt); + } + } + #else + for (numIt = 0; numIt < NUM_IT_MAX; numIt ++) + { + if (status & (UDPHS_INTSTA_EPT_0 << numIt)) + { + UDPHS_EndpointHandler(numIt); + } + } + #endif + } + + /* Update interrupt status */ + status = pUdp->UDPHS_INTSTA; + status &= pUdp->UDPHS_IEN; + + TRACE_DEBUG_WP("\n\r"); + if (status) + { + TRACE_DEBUG_WP(" - "); + } + } +} + +/** + * \brief Reset endpoints and disable them. + * -# Terminate transfer if there is any, with given status; + * -# Reset the endpoint & disable it. + * \param bmEPs Bitmap for endpoints to reset. + * \param bStatus Status passed to terminate transfer on endpoint. + * \param bKeepCfg 1 to keep old endpoint configuration. + * \note Use USBD_HAL_ConfigureEP() to configure and enable endpoint + if not keeping old configuration. + * \sa USBD_HAL_ConfigureEP(). + */ +void USBD_HAL_ResetEPs(uint32_t bmEPs, uint8_t bStatus, uint8_t bKeepCfg) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pHwEp; + + Endpoint *pEndpoint; + uint32_t tmp = bmEPs & ((1<UDPHS_EPT[ep]; + + /* Disable ISR */ + pUdp->UDPHS_IEN &= ~(epBit << SHIFT_INTERUPT); + /* Kill pending Banks ?? */ + #if 0 + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + #endif + + /* Reset transfer information */ + pEndpoint = &(endpoints[ep]); + /* Reset endpoint state */ + pEndpoint->bank = 0; + /* Endpoint configure */ + epCfg = pHwEp->UDPHS_EPTCFG; + /* Reset endpoint */ + pUdp->UDPHS_EPTRST = epBit; + /* Restore configure */ + if (bKeepCfg) + { + pHwEp->UDPHS_EPTCFG = epCfg; + } + else + { + pEndpoint->state = UDPHS_ENDPOINT_DISABLED; + } + + /* Terminate transfer on this EP */ + UDPHS_EndOfTransfer(ep, bStatus); + } + epBit <<= 1; + } +} + +/** + * Cancel pending READ/WRITE + * \param bmEPs Bitmap for endpoints to reset. + * \note EP callback is invoked with USBD_STATUS_CANCELED. + */ +void USBD_HAL_CancelIo(uint32_t bmEPs) +{ + Udphs *pUdp = UDPHS; + //UdphsEpt *pHwEp = NULL; + + uint32_t tmp = bmEPs & ((1<UDPHS_EPT[ep]; + + /* Disable ISR */ + pUdp->UDPHS_IEN &= ~(epBit << SHIFT_INTERUPT); + /* Kill pending Banks ?? */ + #if 0 + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + #endif + + /* Terminate transfer on this EP */ + UDPHS_EndOfTransfer(ep, USBD_STATUS_CANCELED); + } + epBit <<= 1; + } +} + +/** + * Configures an endpoint according to its endpoint Descriptor. + * \param pDescriptor Pointer to an endpoint descriptor. + * \return The endpoint address. + */ +uint8_t USBD_HAL_ConfigureEP(const USBEndpointDescriptor *pDescriptor) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pEpt; + //UdphsDma *pDma; + + Endpoint *pEndpoint; + uint8_t bEndpoint; + uint8_t bType; + uint8_t bEndpointDir; + //uint8_t bInterval = 0; + uint8_t bNbTrans = 1; + uint8_t bSizeEpt = 0; + uint8_t bHs = ((pUdp->UDPHS_INTSTA & UDPHS_INTSTA_SPEED) > 0); + + /* NULL descriptor -> Control endpoint 0 */ + if (pDescriptor == 0) + { + + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + pEpt = &(pUdp->UDPHS_EPT[0]); + bType = USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0); + pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(0); + } + /* Device descriptor -> Control endpoint 0 */ + else if (pDescriptor->bDescriptorType == USBGenericDescriptor_DEVICE) + { + USBDeviceDescriptor *pDevDesc = (USBDeviceDescriptor*)pDescriptor; + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + pEpt = &(pUdp->UDPHS_EPT[0]); + bType = USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size =pDevDesc->bMaxPacketSize0; + pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(0); + } + /* Endpoint descriptor */ + else + { + /* The endpoint number */ + bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); + pEndpoint = &(endpoints[bEndpoint]); + pEpt = &(pUdp->UDPHS_EPT[bEndpoint]); + /* Transfer type: Control, Isochronous, Bulk, Interrupt */ + bType = USBEndpointDescriptor_GetType(pDescriptor); + /* interval */ + //bInterval = USBEndpointDescriptor_GetInterval(pDescriptor); + /* Direction, ignored for control endpoints */ + bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); + pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); + pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(bEndpoint); + + /* Convert descriptor value to EP configuration */ + if (bHs) { /* HS Interval, *125us */ + + /* MPS: Bit12,11 specify NB_TRANS, as USB 2.0 Spec. */ + bNbTrans = ((pEndpoint->size >> 11) & 0x3); + if (bNbTrans == 3) + bNbTrans = 1; + else + bNbTrans ++; + + /* Mask, bit 10..0 is the size */ + pEndpoint->size &= 0x7FF; + } + } + + //TRACE_DEBUG_WP("CfgE%d ", bEndpoint); + + /* Abort the current transfer is the endpoint was configured and in + Write or Read state */ + if( (pEndpoint->state == UDPHS_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDPHS_ENDPOINT_SENDING) + || (pEndpoint->state == UDPHS_ENDPOINT_RECEIVINGM) + || (pEndpoint->state == UDPHS_ENDPOINT_SENDINGM) ) { + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); + } + pEndpoint->state = UDPHS_ENDPOINT_IDLE; + + /* Disable endpoint */ + pEpt->UDPHS_EPTCTLDIS = UDPHS_EPTCTLDIS_SHRT_PCKT + | UDPHS_EPTCTLDIS_BUSY_BANK + | UDPHS_EPTCTLDIS_NAK_OUT + | UDPHS_EPTCTLDIS_NAK_IN + | UDPHS_EPTCTLDIS_STALL_SNT + | UDPHS_EPTCTLDIS_RX_SETUP + | UDPHS_EPTCTLDIS_TX_PK_RDY + | UDPHS_EPTCTLDIS_RX_BK_RDY + | UDPHS_EPTCTLDIS_ERR_OVFLW + | UDPHS_EPTCTLDIS_MDATA_RX + | UDPHS_EPTCTLDIS_DATAX_RX + | UDPHS_EPTCTLDIS_NYET_DIS + | UDPHS_EPTCTLDIS_INTDIS_DMA + | UDPHS_EPTCTLDIS_AUTO_VALID + | UDPHS_EPTCTLDIS_EPT_DISABL + ; + /* Reset Endpoint Fifos */ + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL; + pUdp->UDPHS_EPTRST = 1 << bEndpoint; + /* Configure endpoint size */ + if( pEndpoint->size <= 8 ) + bSizeEpt = 0; + else if ( pEndpoint->size <= 16 ) + bSizeEpt = 1; + else if ( pEndpoint->size <= 32 ) + bSizeEpt = 2; + else if ( pEndpoint->size <= 64 ) + bSizeEpt = 3; + else if ( pEndpoint->size <= 128 ) + bSizeEpt = 4; + else if ( pEndpoint->size <= 256 ) + bSizeEpt = 5; + else if ( pEndpoint->size <= 512 ) + bSizeEpt = 6; + else if ( pEndpoint->size <= 1024 ) + bSizeEpt = 7; + + /* Configure endpoint */ + if (bType == USBEndpointDescriptor_CONTROL) + { + pUdp->UDPHS_IEN |= (UDPHS_IEN_EPT_0 << bEndpoint); + } + + pEpt->UDPHS_EPTCFG = bSizeEpt + | ( bEndpointDir << 3) + | ( bType << 4) + | ((pEndpoint->bank) << 6) + | ( bNbTrans << 8) + ; + while( (UDPHS_EPTCFG_EPT_MAPD & pEpt->UDPHS_EPTCFG) == 0 ) { + + /* resolved by clearing the reset IT in good place */ + TRACE_ERROR("PB bEndpoint: 0x%X\n\r", bEndpoint); + TRACE_ERROR("PB bSizeEpt: 0x%X\n\r", bSizeEpt); + TRACE_ERROR("PB bEndpointDir: 0x%X\n\r", bEndpointDir); + TRACE_ERROR("PB bType: 0x%X\n\r", bType); + TRACE_ERROR("PB pEndpoint->bank: 0x%X\n\r", pEndpoint->bank); + TRACE_ERROR("PB UDPHS_EPTCFG: 0x%X\n\r", (unsigned int)pEpt->UDPHS_EPTCFG); + for(;;); + } + + if (bType == USBEndpointDescriptor_CONTROL) + { + pEpt->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RX_BK_RDY + | UDPHS_EPTCTLENB_RX_SETUP + | UDPHS_EPTCTLENB_EPT_ENABL; + } + else + { +#ifndef DMA + pEpt->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL; +#else + pEpt->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_AUTO_VALID | UDPHS_EPTCTLENB_EPT_ENABL; +#endif + } + + //TRACE_DEBUG_WP("<%x,%x,%x> ", pEpt->UDPHS_EPTCFG, pEpt->UDPHS_EPTCTL, pEpt->UDPHS_EPTSTA); + return bEndpoint; +} + +/** + * Set callback for a USB endpoint for transfer (read/write). + * + * \param bEP Endpoint number. + * \param fCallback Optional callback function to invoke when the transfer is + * complete. + * \param pCbData Optional pointer to data to the callback function. + * \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED if endpoint is busy. + */ +uint8_t USBD_HAL_SetTransferCallback(uint8_t bEP, + TransferCallback fCallback, + void *pCbData) +{ + Endpoint *pEndpoint = &(endpoints[bEP]); + TransferHeader *pTransfer = (TransferHeader*)&(pEndpoint->transfer); + /* Check that the endpoint is not transferring */ + if (pEndpoint->state > UDPHS_ENDPOINT_IDLE) { + return USBD_STATUS_LOCKED; + } + TRACE_DEBUG_WP("sXfrCb "); + /* Setup the transfer callback and extension data */ + pTransfer->fCallback = (void*)fCallback; + pTransfer->pArgument = pCbData; + return USBD_STATUS_SUCCESS; +} + +/** + * Configure an endpoint to use multi-buffer-list transfer mode. + * The buffers can be added by _Read/_Write function. + * \param pMbList Pointer to a multi-buffer list used, NULL to disable MBL. + * \param mblSize Multi-buffer list size (number of buffers can be queued) + * \param startOffset When number of buffer achieve this offset transfer start + */ +uint8_t USBD_HAL_SetupMblTransfer( uint8_t bEndpoint, + USBDTransferBuffer* pMbList, + uint16_t mblSize, + uint16_t startOffset) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pXfr = (MblTransfer*)&(pEndpoint->transfer); + uint16_t i; + /* Check that the endpoint is not transferring */ + if (pEndpoint->state > UDPHS_ENDPOINT_IDLE) { + return USBD_STATUS_LOCKED; + } + TRACE_DEBUG_WP("sMblXfr "); + /* Enable Multi-Buffer Transfer List */ + if (pMbList) { + /* Reset list items */ + for (i = 0; i < mblSize; i --) { + pMbList[i].pBuffer = NULL; + pMbList[i].size = 0; + pMbList[i].transferred = 0; + pMbList[i].buffered = 0; + pMbList[i].remaining = 0; + } + /* Setup transfer */ + pXfr->transType = 1; + pXfr->listState = 0; /* OK */ + pXfr->listSize = mblSize; + pXfr->pMbl = pMbList; + pXfr->outCurr = pXfr->outLast = 0; + pXfr->inCurr = 0; + pXfr->offsetSize = startOffset; + } + /* Disable Multi-Buffer Transfer */ + else { + pXfr->transType = 0; + pXfr->pMbl = NULL; + pXfr->listSize = 0; + pXfr->offsetSize = 1; + } + return USBD_STATUS_SUCCESS; +} + +/** + * Sends data through a USB endpoint. Sets up the transfer descriptor, + * writes one or two data payloads (depending on the number of FIFO bank + * for the endpoint) and then starts the actual transfer. The operation is + * complete when all the data has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param bEndpoint Endpoint number. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +uint8_t USBD_HAL_Write( uint8_t bEndpoint, + const void *pData, + uint32_t dLength) +{ + if (endpoints[bEndpoint].transfer.transHdr.transType) + return UDPHS_AddWr(bEndpoint, pData, dLength); + else + return UDPHS_Write(bEndpoint, pData, dLength); +} + +/** + * Special write function. + * Sends data through a USB endpoint. Sets up the transfer descriptor, + * writes header and one or two data payloads (depending on the number of + * FIFO bank for the endpoint) and then starts the actual transfer. The + * operation is complete when all the data has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param bEndpoint Endpoint number. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +uint8_t USBD_HAL_WrWithHdr(uint8_t bEndpoint, + const void * pHdr, uint8_t bHdrLen, + const void * pData,uint32_t dLength) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pHwEp = &pUdp->UDPHS_EPT[bEndpoint]; + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + /* Return if DMA is not supported */ + if (!CHIP_USB_ENDPOINTS_DMA(bEndpoint)) + { + return USBD_STATUS_HW_NOT_SUPPORTED; + } + +#ifdef DMA + /* Return if busy */ + if (pEp->state != UDPHS_ENDPOINT_IDLE) + { + return USBD_STATUS_LOCKED; + } + /* Sending state */ + pEp->state = UDPHS_ENDPOINT_SENDING; + TRACE_DEBUG_WP("Wr%d(%d+%d) ", bEndpoint, bHdrLen, dLength); + + pEp->sendZLP = 0; + + /* Setup transfer descriptor */ + pXfr->pData = (void*) pData; + pXfr->remaining = bHdrLen + dLength; + pXfr->buffered = 0; + pXfr->transferred = 0; + + /* 1. DMA supported always, 2. Not ZLP */ + if (bHdrLen + dLength > 0) + { + uint8_t bNbTrans = (pHwEp->UDPHS_EPTCFG & UDPHS_EPTCFG_NB_TRANS_Msk) + >> UDPHS_EPTCFG_NB_TRANS_Pos; + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + { + /* Transfer the max */ + pXfr->buffered = DMA_MAX_FIFO_SIZE; + } + else + { + /* Good size, total size */ + pXfr->buffered = pXfr->remaining; + } + + /* LD1: header - load to fifo without interrupt */ + /* Header discarded if exceed the DMA FIFO length */ + //if (bHdrLen > DMA_MAX_FIFO_SIZE) bHdrLen = DMA_MAX_FIFO_SIZE; + pDmaLL[0].pNxtDesc = (void*)&pDmaLL[1]; + pDmaLL[0].pAddr = (void*)pHdr; + pDmaLL[0].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(bHdrLen) + | UDPHS_DMACONTROL_LDNXT_DSC; + /* High bandwidth ISO EP, max size n*ep_size */ + if (bNbTrans > 1) { + uint8_t* pU8 = (uint8_t*)pData; + uint32_t maxSize = bNbTrans * pEp->size; + dLength = pXfr->buffered - bHdrLen; + if (dLength > maxSize) dLength = maxSize; + #if 0 /* Prepare banks by 1 DMA descriptor -- NK if not standard EP size, works! */ + /* LD2: data - load to fifo with interrupt */ + pDmaLL[1].pNxtDesc = (void*)NULL; + pDmaLL[1].pAddr = (void*)pU8; + pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(dLength) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT; + #else + uint32_t pktLen, ndxData = 0; + /* LD2: data - bank 0 */ + pktLen = pEp->size - bHdrLen; + if (pktLen >= dLength) { /* It's the last DMA LLI */ + pDmaLL[1].pNxtDesc = (void*)NULL; + pDmaLL[1].pAddr = (void*)pU8; + pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(dLength) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT; + } + else { + pDmaLL[1].pNxtDesc = (void*)&pDmaLL[2]; + pDmaLL[1].pAddr = (void*)pU8; + pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(pktLen) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_LDNXT_DSC; + dLength -= pktLen; ndxData += pktLen; + /* LD3: data - bank 1 */ + pktLen = pEp->size; + if (pktLen >= dLength) { /* It's the last */ + pDmaLL[1].pNxtDesc = (void*) NULL; + pDmaLL[1].pAddr = (void*)&pU8[ndxData]; + pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(dLength) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT; + } + else { + pDmaLL[2].pNxtDesc = (void*)&pDmaLL[3]; + pDmaLL[2].pAddr = (void*)&pU8[ndxData]; + pDmaLL[2].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(pktLen) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_LDNXT_DSC; + dLength -= pktLen; ndxData += pktLen; + /* LD4: data - bank 2 */ + pDmaLL[3].pNxtDesc = (void*) NULL; + pDmaLL[3].pAddr = (void*)&pU8[ndxData]; + pDmaLL[3].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(dLength) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT; + } + } + #endif + } + else { /* Normal, fill all data */ + /* LD2: data - load to fifo with interrupt */ + dLength = pXfr->buffered - bHdrLen; + pDmaLL[1].pNxtDesc = (void*)NULL; + pDmaLL[1].pAddr = (void*)pData; + pDmaLL[1].dwCtrl = UDPHS_DMACONTROL_CHANN_ENB + | UDPHS_DMACONTROL_BUFF_LENGTH(dLength) + | UDPHS_DMACONTROL_END_B_EN + | UDPHS_DMACONTROL_END_BUFFIT; + } + /* Interrupt enable */ + pUdp->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint); + /* Start transfer with LLI */ + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMANXTDSC = (uint32_t)pDmaLL; + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; + pUdp->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = UDPHS_DMACONTROL_LDNXT_DSC; + return USBD_STATUS_SUCCESS; + } +#endif + + /* Enable IT */ + pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint ); + pHwEp->UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_TX_PK_RDY; + return USBD_STATUS_SUCCESS; +} + +/** + * Reads incoming data on an USB endpoint This methods sets the transfer + * descriptor and activate the endpoint interrupt. The actual transfer is + * then carried out by the endpoint interrupt handler. The Read operation + * finishes either when the buffer is full, or a short packet (inferior to + * endpoint maximum size) is received. + * + * *The buffer must be kept allocated until the transfer is finished*. + * \param bEndpoint Endpoint number. + * \param pData Pointer to a data buffer. + * \param dLength Size of the data buffer in bytes. + * \return USBD_STATUS_SUCCESS if the read operation has been started; + * otherwise, the corresponding error code. + */ +uint8_t USBD_HAL_Read(uint8_t bEndpoint, + void *pData, + uint32_t dLength) +{ + if (endpoints[bEndpoint].transfer.transHdr.transType) + return USBD_STATUS_SW_NOT_SUPPORTED; + else + return UDPHS_Read(bEndpoint, pData, dLength); +} + +/** + * \brief Enable Pull-up, connect. + * + * -# Enable HW access if needed + * -# Enable Pull-Up + * -# Disable HW access if needed + */ +void USBD_HAL_Connect(void) +{ + Udphs *pUdp = UDPHS; + + uint8_t dis = UDPHS_EnablePeripheralClock(); + pUdp->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; + pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_DETACH; + if (dis) UDPHS_DisablePeripheralClock(); +} + +/** + * \brief Disable Pull-up, disconnect. + * + * -# Enable HW access if needed + * -# Disable PULL-Up + * -# Disable HW access if needed + */ +void USBD_HAL_Disconnect(void) +{ + Udphs *pUdp = UDPHS; + + uint8_t dis = UDPHS_EnablePeripheralClock(); + pUdp->UDPHS_CTRL |= UDPHS_CTRL_DETACH; + pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_PULLD_DIS; + if (dis) UDPHS_DisablePeripheralClock(); +} + +/** + * Starts a remote wake-up procedure. + */ +void USBD_HAL_RemoteWakeUp(void) +{ + Udphs *pUdp = UDPHS; + + UDPHS_EnablePeripheralClock(); + UDPHS_EnableUsbClock(); + + TRACE_INFO_WP("RWUp "); + + /* Activates a remote wakeup (edge on ESR), then clear ESR */ + pUdp->UDPHS_CTRL |= UDPHS_CTRL_REWAKEUP; + while(pUdp->UDPHS_CTRL & UDPHS_CTRL_REWAKEUP) + { + TRACE_DEBUG_WP("w"); + } + UDPHS_EnableBIAS(); +} + +/** + * Sets the device address to the given value. + * \param address New device address. + */ +void USBD_HAL_SetAddress(uint8_t address) +{ + Udphs *pUdp = UDPHS; + + if (address) + { + pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_DEV_ADDR_Msk; + pUdp->UDPHS_CTRL |= address | UDPHS_CTRL_FADDR_EN; + } + else + { + pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_FADDR_EN; + } +} + +/** + * Sets the current device configuration. + * \param cfgnum - Configuration number to set. + */ +void USBD_HAL_SetConfiguration(uint8_t cfgnum) +{ + /* Nothing to do now */ + cfgnum = cfgnum; +} + +/** + * Initializes the USB HW Access driver. + */ +void USBD_HAL_Init(void) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pEpt; + UdphsDma *pDma; + uint32_t i; +#ifdef DMA + /* DMA Link list should be 16-bytes aligned */ + if ((uint32_t)dmaLL & 0xFFFFFFF0) + pDmaLL = (UdphsDmaDescriptor*)((uint32_t)&dmaLL[1] & 0xFFFFFFF0); + else + pDmaLL = (UdphsDmaDescriptor*)((uint32_t)&dmaLL[0]); +#endif + /* Must before USB & TXVC access! */ + UDPHS_EnablePeripheralClock(); + + /* Reset & disable endpoints */ + USBD_HAL_ResetEPs(0xFFFFFFFF, USBD_STATUS_RESET, 0); + + /* Configure the pull-up on D+ and disconnect it */ + pUdp->UDPHS_CTRL |= UDPHS_CTRL_DETACH; + pUdp->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; + + /* Reset IP */ + pUdp->UDPHS_CTRL &= ~(uint32_t)UDPHS_CTRL_EN_UDPHS; + pUdp->UDPHS_CTRL |= UDPHS_CTRL_EN_UDPHS; + + /* (XCHQ[2010.1.21], IP recomendation, setup clock after reset IP) */ + UDPHS_EnableUsbClock(); + + /* Initialize DMA */ + for (i = 1; + i < ((pUdp->UDPHS_IPFEATURES & UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk) >> 4); + i ++) + { + pEpt = &pUdp->UDPHS_EPT[i]; + pDma = &pUdp->UDPHS_DMA[i]; + /* DMA stop */ + pDma->UDPHS_DMACONTROL = 0; + /* Disable endpoint */ + pEpt->UDPHS_EPTCTLDIS = (uint32_t)UDPHS_EPTCTLDIS_SHRT_PCKT + | UDPHS_EPTCTLDIS_BUSY_BANK + | UDPHS_EPTCTLDIS_NAK_OUT + | UDPHS_EPTCTLDIS_NAK_IN + | UDPHS_EPTCTLDIS_STALL_SNT + | UDPHS_EPTCTLDIS_RX_SETUP + | UDPHS_EPTCTLDIS_TX_PK_RDY + | UDPHS_EPTCTLDIS_TX_COMPLT + | UDPHS_EPTCTLDIS_RX_BK_RDY + | UDPHS_EPTCTLDIS_ERR_OVFLW + | UDPHS_EPTCTLDIS_MDATA_RX + | UDPHS_EPTCTLDIS_DATAX_RX + | UDPHS_EPTCTLDIS_NYET_DIS + | UDPHS_EPTCTLDIS_INTDIS_DMA + | UDPHS_EPTCTLDIS_AUTO_VALID + | UDPHS_EPTCTLDIS_EPT_DISABL + ; + /* Clear status endpoint */ + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ + | UDPHS_EPTCLRSTA_FRCESTALL + | UDPHS_EPTCLRSTA_RX_BK_RDY + | UDPHS_EPTCLRSTA_TX_COMPLT + | UDPHS_EPTCLRSTA_RX_SETUP + | UDPHS_EPTCLRSTA_STALL_SNT + | UDPHS_EPTCLRSTA_NAK_IN + | UDPHS_EPTCLRSTA_NAK_OUT + ; + /* Reset endpoint config */ + pEpt->UDPHS_EPTCTLENB = 0; + /* Reset DMA channel (Buffer count and Control field) */ + pDma->UDPHS_DMACONTROL = UDPHS_DMACONTROL_LDNXT_DSC; + /* Reset DMA channel */ + pDma->UDPHS_DMACONTROL = 0; + /* Clear DMA channel status (read to clear) */ + pDma->UDPHS_DMASTATUS = pDma->UDPHS_DMASTATUS; + } + + /* Force Full-Speed */ + pUdp->UDPHS_TST = forceUsbFS ? UDPHS_TST_SPEED_CFG_FULL_SPEED : 0; + + pUdp->UDPHS_IEN = 0; + pUdp->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES + | UDPHS_CLRINT_ENDOFRSM + | UDPHS_CLRINT_WAKE_UP + | UDPHS_CLRINT_ENDRESET + | UDPHS_CLRINT_INT_SOF + | UDPHS_CLRINT_MICRO_SOF + | UDPHS_CLRINT_DET_SUSPD + ; + + /* Enable interrupts */ + pUdp->UDPHS_IEN = UDPHS_IEN_ENDOFRSM + | UDPHS_IEN_WAKE_UP + | UDPHS_IEN_DET_SUSPD; + + /* Disable USB clocks */ + UDPHS_DisableUsbClock(); +} + +/** + * Causes the given endpoint to acknowledge the next packet it receives + * with a STALL handshake except setup request. + * \param bEP Endpoint number. + * \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. + */ +uint8_t USBD_HAL_Stall(uint8_t bEP) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pEpt = &pUdp->UDPHS_EPT[bEP]; + + Endpoint *pEndpoint = &(endpoints[bEP]); + + /* Check that endpoint is in Idle state */ + if (pEndpoint->state != UDPHS_ENDPOINT_IDLE) + { + TRACE_WARNING("UDP_Stall: EP%d locked\n\r", bEP); + return USBD_STATUS_LOCKED; + } + /* STALL endpoint */ + pEpt->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_FRCESTALL; + + TRACE_DEBUG_WP("Stall%d ", bEP); + return USBD_STATUS_SUCCESS; +} + +/** + * Sets/Clear/Get the HALT state on the endpoint. + * In HALT state, the endpoint should keep stalling any packet. + * \param bEndpoint Endpoint number. + * \param ctl Control code CLR/HALT/READ. + * 0: Clear HALT state; + * 1: Set HALT state; + * .: Return HALT status. + * \return USBD_STATUS_INVALID_PARAMETER if endpoint not exist, + * otherwise endpoint halt status. + */ +uint8_t USBD_HAL_Halt(uint8_t bEndpoint, uint8_t ctl) +{ + Udphs *pUdp = UDPHS; + UdphsEpt *pEpt = &pUdp->UDPHS_EPT[bEndpoint]; + + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + uint8_t status = 0; + + /* SET Halt */ + if (ctl == 1) + { + /* Check that endpoint is enabled and not already in Halt state */ + if ((pEndpoint->state != UDPHS_ENDPOINT_DISABLED) + && (pEndpoint->state != UDPHS_ENDPOINT_HALTED)) + { + + TRACE_DEBUG_WP("Halt%d ", bEndpoint); + + /* Abort the current transfer if necessary */ + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + + /* Put endpoint into Halt state */ + pEndpoint->state = UDPHS_ENDPOINT_HALTED; + pEpt->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_FRCESTALL; + + #ifdef DMA + if (CHIP_USB_ENDPOINTS_DMA(bEndpoint)) + { + /* Enable the endpoint DMA interrupt */ + pUdp->UDPHS_IEN |= ( 1 << SHIFT_DMA << bEndpoint ); + } + else + { + /* Enable the endpoint interrupt */ + pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint ); + } + #else + /* Enable the endpoint interrupt */ + pUdp->UDPHS_IEN |= ( UDPHS_IEN_EPT_0 << bEndpoint ); + #endif + } + } + /* CLEAR Halt */ + else if (ctl == 0) + { + /* Check if the endpoint is halted */ + if (pEndpoint->state == UDPHS_ENDPOINT_HALTED) + { + + TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); + + /* Return endpoint to Idle state */ + pEndpoint->state = UDPHS_ENDPOINT_IDLE; + + /* Clear FORCESTALL flag */ + pEpt->UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ + | UDPHS_EPTCLRSTA_FRCESTALL; + + /* Reset Endpoint Fifos */ + pUdp->UDPHS_EPTRST = (1 << bEndpoint); + } + } + + /* Return Halt status */ + if (pEndpoint->state == UDPHS_ENDPOINT_HALTED) + { + status = 1; + } + return( status ); +} + +/** + * Indicates if the device is running in high or full-speed. Always returns 0 + * since UDP does not support high-speed mode. + */ +uint8_t USBD_HAL_IsHighSpeed(void) +{ + Udphs *pUdp = UDPHS; + return (pUdp->UDPHS_INTSTA & UDPHS_INTSTA_SPEED); +} + +/** + * Suspend USB Device HW Interface + * + * -# Disable transceiver + * -# Disable USB Clock + * -# Disable USB Peripheral + */ +void USBD_HAL_Suspend(void) +{ + /* The device enters the Suspended state */ + UDPHS_DisableBIAS(); + UDPHS_DisableUsbClock(); + UDPHS_DisablePeripheralClock(); +} + +/** + * Activate USB Device HW Interface + * -# Enable USB Peripheral + * -# Enable USB Clock + * -# Enable transceiver + */ +void USBD_HAL_Activate(void) +{ + UDPHS_EnablePeripheralClock(); + UDPHS_EnableUsbClock(); + UDPHS_EnableBIAS(); +} + +/** + * Certification test for High Speed device. + * \param bIndex Test to be done + */ +void USBD_HAL_Test( uint8_t bIndex ) +{ + Udphs *pUdp = UDPHS; + uint8_t *pFifo; + uint32_t i; + + /* remove suspend for TEST */ + pUdp->UDPHS_IEN &= ~UDPHS_IEN_DET_SUSPD; + /* force High Speed (remove suspend) */ + pUdp->UDPHS_TST |= UDPHS_TST_SPEED_CFG_HIGH_SPEED; + + switch( bIndex ) { + + case USBFeatureRequest_TESTPACKET: + TRACE_DEBUG_WP("TEST_PACKET "); + + pUdp->UDPHS_DMA[1].UDPHS_DMACONTROL = 0; + pUdp->UDPHS_DMA[2].UDPHS_DMACONTROL = 0; + + /* Configure endpoint 2, 64 bytes, direction IN, type BULK, 1 bank */ + pUdp->UDPHS_EPT[2].UDPHS_EPTCFG = UDPHS_EPTCFG_EPT_SIZE_64 + | UDPHS_EPTCFG_EPT_DIR + | UDPHS_EPTCFG_EPT_TYPE_BULK + | UDPHS_EPTCFG_BK_NUMBER_1; + while( (pUdp->UDPHS_EPT[2].UDPHS_EPTCFG & UDPHS_EPTCFG_EPT_MAPD) != UDPHS_EPTCFG_EPT_MAPD ); + pUdp->UDPHS_EPT[2].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL; + + /* Write FIFO */ + pFifo = (uint8_t*)((uint32_t *)(UDPHS_RAM_ADDR) + (EPT_VIRTUAL_SIZE * 2)); + for( i=0; iUDPHS_TST |= UDPHS_TST_TST_PKT; + /* Send packet */ + pUdp->UDPHS_EPT[2].UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY; + break; + + case USBFeatureRequest_TESTJ: + TRACE_DEBUG_WP("TEST_J "); + pUdp->UDPHS_TST = UDPHS_TST_TST_J; + break; + + case USBFeatureRequest_TESTK: + TRACE_DEBUG_WP("TEST_K "); + pUdp->UDPHS_TST = UDPHS_TST_TST_K; + break; + + case USBFeatureRequest_TESTSE0NAK: + TRACE_DEBUG_WP("TEST_SEO_NAK "); + pUdp->UDPHS_IEN = 0; // for test + break; + + case USBFeatureRequest_TESTSENDZLP: + //while( 0 != (pUdp->UDPHS_EPT[0].UDPHS_EPTSTA & UDPHS_EPTSETSTA_TX_PK_RDY ) ) {} + pUdp->UDPHS_EPT[0].UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_TX_PK_RDY; + //while( 0 != (pUdp->UDPHS_EPT[0].UDPHS_EPTSTA & UDPHS_EPTSETSTA_TX_PK_RDY ) ) {} + TRACE_DEBUG_WP("SEND_ZLP "); + break; + } + TRACE_DEBUG_WP("\n\r"); +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/adc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/adc.c new file mode 100644 index 000000000..da60061cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/adc.c @@ -0,0 +1,729 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup adc_module Working with ADC + * \ingroup peripherals_module + * The ADC driver provides the interface to configure and use the ADC peripheral. + * \n + * + * It converts the analog input to digital format. The converted result could be + * 12bit or 10bit. The ADC supports up to 16 analog lines. + * + * To Enable a ADC conversion,the user has to follow these few steps: + *
    + *
  • Select an appropriate reference voltage on ADVREF
    • + *
  • Configure the ADC according to its requirements and special needs,which + * could be broken down into several parts: + * -# Select the resolution by setting or clearing ADC_MR_LOWRES bit in + * ADC_MR (Mode Register) + * -# Set ADC clock by setting ADC_MR_PRESCAL bits in ADC_MR, the clock is + * calculated with ADCClock = MCK / ( (PRESCAL+1) * 2 ) + * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively + * in ADC_MR. +
    • + *
  • Start conversion by setting ADC_CR_START in ADC_CR.
    • + *
+ * + * For more accurate information, please look at the ADC section of the + * Datasheet. + * + * Related files :\n + * \ref adc.c\n + * \ref adc.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * Implementation of Analog-to-Digital Converter (ADC). + * + */ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Current working clock */ +static uint32_t dwAdcClock = 0; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Initialize the ADC controller + * + * \param pAdc Pointer to an Adc instance. + * \param dwID ADC Index + */ +extern void ADC_Initialize( Adc* pAdc, uint32_t dwID ) +{ + /* Enable peripheral clock*/ + PMC_EnablePeripheral(dwID); + + /* Reset the controller */ + pAdc->ADC_CR = ADC_CR_SWRST; + + /* Reset Mode Register */ + pAdc->ADC_MR = 0; + +} + +/** + * \brief Set ADC clock. + * + * \param pAdc Pointer to an Adc instance. + * \param dwPres prescal value + * \param dwMck Board MCK (Hz) + * + * \return ADC clock + */ + +extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwClk, uint32_t dwMck ) +{ + uint32_t dwPres, dwMr; + /* Formula for PRESCAL is: + PRESCAL = (MCK / (2 * ADCCLK)) + 1 + First, we do the division, multiplied by 10 to get higher precision + If the last digit is not zero, we round up to avoid generating a higher + than required frequency. */ + dwPres = (dwMck * 5) / dwClk; + if (dwPres % 10) dwPres = dwPres / 10; + else + { + if (dwPres == 0) return 0; + dwPres = dwPres / 10 - 1; + } + + dwMr = ADC_MR_PRESCAL(dwPres); + if (dwMr == 0) return 0; + + dwMr |= (pAdc->ADC_MR & ~ADC_MR_PRESCAL_Msk); + pAdc->ADC_MR = dwMr; + + dwAdcClock = dwMck / (dwPres + 1) / 2; + //dwAdcClock = dwAdcClock / 1000 * 1000; + return dwAdcClock; +} + +/** + * \brief Set ADC timing. + * + * \param pAdc Pointer to an Adc instance. + * \param dwStartup startup value + * \param dwTracking tracking value + * \param dwSettling settling value + */ +extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling ) +{ + uint32_t dwMr; + + dwMr = pAdc->ADC_MR; + dwMr &= (~ADC_MR_STARTUP_Msk) & (~ADC_MR_TRACKTIM_Msk) & (~ADC_MR_SETTLING_Msk); + + /* Formula: + * Startup Time = startup value / ADCClock + * Transfer Time = (TRANSFER * 2 + 3) / ADCClock + * Tracking Time = (TRACKTIM + 1) / ADCClock + * Settling Time = settling value / ADCClock + */ + dwMr |= dwStartup | dwTracking | dwSettling; + pAdc->ADC_MR |= dwMr; +} + +/** + * \brief Set ADC trigger. + * + * \param pAdc Pointer to an Adc instance. + * \param dwTrgSel Trigger selection + */ +extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel ) +{ + uint32_t dwMr; + + dwMr = pAdc->ADC_MR; + dwMr &= ~ADC_MR_TRGSEL_Msk; + dwMr |= dwTrgSel; + pAdc->ADC_MR |= dwMr; +} + +/** + * Sets the trigger mode to following: + * - \ref ADC_TRGR_TRGMOD_NO_TRIGGER + * - \ref ADC_TRGR_TRGMOD_EX_TRIG_RISE + * - \ref ADC_TRGR_TRGMOD_EX_TRIG_FALL + * - \ref ADC_TRGR_TRGMOD_EX_TRIG_ANY + * - \ref ADC_TRGR_TRGMOD_PEN_TIRG + * - \ref ADC_TRGR_TRGMOD_PERID_TRIG + * - \ref ADC_TRGR_TRGMOD_CONTINUOUS + * \param pAdc Pointer to an Adc instance. + * \param dwMode Trigger mode. + */ +void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode) +{ + uint32_t dwTrgr = pAdc->ADC_TRGR & ~ADC_TRGR_TRGMOD_Msk; + pAdc->ADC_TRGR = dwTrgr | dwMode; +} + +/** + * \brief Enable/Disable low resolution. + * + * \param pAdc Pointer to an Adc instance. + * \param bEnDis Enable/Disable low resolution. + */ +extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis ) +{ + if ( bEnDis ) + { + pAdc->ADC_MR |= ADC_MR_LOWRES; + } + else + { + pAdc->ADC_MR &= ~ADC_MR_LOWRES; + } +} + +/** + * \brief Enable/Disable sleep mode. + * + * \param pAdc Pointer to an Adc instance. + * \param bEnDis Enable/Disable sleep mode. + */ +extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis ) +{ + if ( bEnDis ) + { + pAdc->ADC_MR |= ADC_MR_SLEEP; + } + else + { + pAdc->ADC_MR &= ~ADC_MR_SLEEP; + } +} + +/** + * \brief Enable/Disable fast wake up. + * + * \param pAdc Pointer to an Adc instance. + * \param bEnDis Enable/Disable fast wake up in sleep mode. + */ +extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis ) +{ + if ( bEnDis ) + { + pAdc->ADC_MR |= ADC_MR_FWUP; + } + else + { + pAdc->ADC_MR &= ~ADC_MR_FWUP; + } +} + +/** + * \brief Enable/Disable seqnence mode. + * + * \param pAdc Pointer to an Adc instance. + * \param bEnDis Enable/Disable seqnence mode. + */ +extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis ) +{ + if ( bEnDis ) + { + /* User Sequence Mode: The sequence respects what is defined in + ADC_SEQR1 and ADC_SEQR2 */ + pAdc->ADC_MR |= ADC_MR_USEQ; + } + else + { + /* Normal Mode: The controller converts channels in a simple numeric order. */ + pAdc->ADC_MR &= ~ADC_MR_USEQ; + } +} + +/** + * \brief Set channel sequence. + * + * \param pAdc Pointer to an Adc instance. + * \param dwSEQ1 Sequence 1 ~ 8 channel number. + * \param dwSEQ2 Sequence 9 ~ 16 channel number. + */ +extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 ) +{ + pAdc->ADC_SEQR1 = dwSEQ1; + pAdc->ADC_SEQR2 = dwSEQ2; +} + +/** + * \brief Set channel sequence by given channel list. + * + * \param pAdc Pointer to an Adc instance. + * \param ucChList Channel list. + * \param ucNumCh Number of channels in list. + */ +extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh ) +{ + uint8_t i; + uint8_t ucShift; + + pAdc->ADC_SEQR1 = 0; + for (i = 0, ucShift = 0; i < 8; i ++, ucShift += 4) + { + if (i >= ucNumCh) return; + pAdc->ADC_SEQR1 |= ucChList[i] << ucShift; + + } + pAdc->ADC_SEQR2 = 0; + for (ucShift = 0; i < 16; i ++, ucShift += 4) + { + if (i >= ucNumCh) return; + pAdc->ADC_SEQR2 |= ucChList[i] << ucShift; + } +} + +/** + * \brief Set analog change. + * IF enabled, it allows different analog settings for each channel, + * otherwise, DIFF0, GAIN0 and OFF0 are used for all channels. + * + * \param pAdc Pointer to an Adc instance. + * \param bEnDis Enable/Disable. + */ +extern void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis ) +{ + if ( bEnDis ) + { + pAdc->ADC_MR |= ADC_MR_ANACH; + } + else + { + pAdc->ADC_MR &= ~ADC_MR_ANACH; + } +} + +/** + * \brief Set "TAG" mode, show channel number in last data or not. + * + * \param pAdc Pointer to an Adc instance. + * \param bEnDis Enable/Disable TAG value. + */ +extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis ) +{ + if ( bEnDis ) + { + pAdc->ADC_EMR |= ADC_EMR_TAG; + } + else + { + pAdc->ADC_EMR &= ~ADC_EMR_TAG; + } +} + +/** + * \brief Set compare channel. + * + * \param pAdc Pointer to an Adc instance. + * \param dwChannel channel number to be set,16 for all channels + */ +extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) +{ + assert( dwChannel <= 16 ) ; + + if ( dwChannel < 16 ) + { + pAdc->ADC_EMR &= ~(ADC_EMR_CMPALL); + pAdc->ADC_EMR &= ~(ADC_EMR_CMPSEL_Msk); + pAdc->ADC_EMR |= (dwChannel << ADC_EMR_CMPSEL_Pos); + } + else + { + pAdc->ADC_EMR |= ADC_EMR_CMPALL; + } +} + +/** + * \brief Set compare mode. + * + * \param pAdc Pointer to an Adc instance. + * \param dwMode compare mode + */ +extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) +{ + pAdc->ADC_EMR &= ~(ADC_EMR_CMPMODE_Msk); + pAdc->ADC_EMR |= (dwMode & ADC_EMR_CMPMODE_Msk); +} + +/** + * \brief Set comparsion window. + * + * \param pAdc Pointer to an Adc instance. + * \param dwHi_Lo Comparison Window + */ +extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) +{ + pAdc->ADC_CWR = dwHi_Lo ; +} + +/** + * \brief Get startup value. + */ +static uint32_t GetStartupValue( uint32_t dwStartup ) +{ + uint32_t dwStartupValue = 0; + + if( dwStartup == 0 ) + dwStartupValue = 0; + else if( dwStartup == 1 ) + dwStartupValue = 8; + else if( dwStartup == 2 ) + dwStartupValue = 16; + else if( dwStartup == 3 ) + dwStartupValue = 24; + else if( dwStartup == 4 ) + dwStartupValue = 64; + else if( dwStartup == 5 ) + dwStartupValue = 80; + else if( dwStartup == 6 ) + dwStartupValue = 96; + else if( dwStartup == 7 ) + dwStartupValue = 112; + else if( dwStartup == 8 ) + dwStartupValue = 512; + else if( dwStartup == 9 ) + dwStartupValue = 576; + else if( dwStartup == 10 ) + dwStartupValue = 640; + else if( dwStartup == 11 ) + dwStartupValue = 704; + else if( dwStartup == 12 ) + dwStartupValue = 768; + else if( dwStartup == 13 ) + dwStartupValue = 832; + else if( dwStartup == 14 ) + dwStartupValue = 896; + else if( dwStartup == 15 ) + dwStartupValue = 960; + + return dwStartupValue; +} + +/** + * \brief Check if ADC configuration is right. + * + * \param pAdc Pointer to an Adc instance. + * \param dwMck Board MCK (Hz) + * + * \return 0 if check ok, others if not ok. + */ +extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMck ) +{ + uint8_t bOk = 0; + uint32_t dwMr; + uint32_t dwPres; + uint32_t dwStartup; + uint32_t dwClock; + uint32_t dwTemp; + + dwMr = pAdc->ADC_MR; + + dwPres = (dwMr & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos; + /* Formula: ADCClock = MCK / ( (PRESCAL+1) * 2 ) */ + dwClock = dwMck / ( (dwPres + 1) * 2 ); + if (dwClock > ADC_CLOCK_MAX) + { + printf("ADC clock is too high (out of specification: %d Hz)\r\n", (int)ADC_CLOCK_MAX); + bOk = 1; + } + + dwStartup = (dwMr & ADC_MR_STARTUP_Msk) >> ADC_MR_STARTUP_Pos; + if (dwMr & ADC_MR_SLEEP_SLEEP) + { + if( pAdc->ADC_MR & ADC_MR_FWUP_ON ) + { + /* Fast Wake Up Sleep Mode: 12µs */ + dwTemp = ADC_STARTUP_FAST_MAX * dwClock / 1000000; + if( dwTemp > GetStartupValue(dwStartup) ) + { + printf("Startup time too small: %d, programmed: %d\r\n", (int)dwTemp, (int)(GetStartupValue(dwStartup))); + bOk = 1; + } + } + } + + return bOk; +} + +/** + * \brief Return the Channel Converted Data + * + * \param pAdc Pointer to an Adc instance. + * \param dwChannel channel to get converted value + */ +extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) +{ + uint32_t dwData = 0; + + assert( dwChannel < 16 ) ; + + dwData = pAdc->ADC_CDR[dwChannel]; + + return dwData ; +} + + +/** + * Sets the ADC startup time. + * \param pAdc Pointer to an Adc instance. + * \param dwUs Startup time in uS. + */ +void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs ) +{ + uint32_t dwStart; + uint32_t dwMr; + + if (dwAdcClock == 0) return; + /* Formula for STARTUP is: + STARTUP = (time x ADCCLK) / (1000000) - 1 + Division multiplied by 10 for higher precision */ + + dwStart = (dwUs * dwAdcClock) / (100000); + if (dwStart % 10) dwStart /= 10; + else + { + dwStart /= 10; + if (dwStart) dwStart --; + } + if (dwStart > 896) dwMr = ADC_MR_STARTUP_SUT960; + else if (dwStart > 832) dwMr = ADC_MR_STARTUP_SUT896; + else if (dwStart > 768) dwMr = ADC_MR_STARTUP_SUT832; + else if (dwStart > 704) dwMr = ADC_MR_STARTUP_SUT768; + else if (dwStart > 640) dwMr = ADC_MR_STARTUP_SUT704; + else if (dwStart > 576) dwMr = ADC_MR_STARTUP_SUT640; + else if (dwStart > 512) dwMr = ADC_MR_STARTUP_SUT576; + else if (dwStart > 112) dwMr = ADC_MR_STARTUP_SUT512; + else if (dwStart > 96) dwMr = ADC_MR_STARTUP_SUT112; + else if (dwStart > 80) dwMr = ADC_MR_STARTUP_SUT96; + else if (dwStart > 64) dwMr = ADC_MR_STARTUP_SUT80; + else if (dwStart > 24) dwMr = ADC_MR_STARTUP_SUT64; + else if (dwStart > 16) dwMr = ADC_MR_STARTUP_SUT24; + else if (dwStart > 8) dwMr = ADC_MR_STARTUP_SUT16; + else if (dwStart > 0) dwMr = ADC_MR_STARTUP_SUT8; + else dwMr = ADC_MR_STARTUP_SUT0; + + dwMr |= pAdc->ADC_MR & ~ADC_MR_STARTUP_Msk; + pAdc->ADC_MR = dwMr; +} + + +/** + * Set ADC tracking time + * \param pAdc Pointer to an Adc instance. + * \param dwNs Tracking time in nS. + */ +void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs ) +{ + uint32_t dwShtim; + uint32_t dwMr; + + if (dwAdcClock == 0) return; + /* Formula for SHTIM is: + SHTIM = (time x ADCCLK) / (1000000000) - 1 + Since 1 billion is close to the maximum value for an integer, we first + divide ADCCLK by 1000 to avoid an overflow */ + dwShtim = (dwNs * (dwAdcClock / 1000)) / 100000; + if (dwShtim % 10) dwShtim /= 10; + else + { + dwShtim /= 10; + if (dwShtim) dwShtim --; + } + dwMr = ADC_MR_TRACKTIM(dwShtim); + dwMr |= pAdc->ADC_MR & ~ADC_MR_TRACKTIM_Msk; + pAdc->ADC_MR = dwMr; +} + + +/** + * Sets the trigger period. + * \param pAdc Pointer to an Adc instance. + * \param dwPeriod Trigger period in nS. + */ +void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod) +{ + uint32_t dwTrgper; + uint32_t dwDiv = 100000000; + uint32_t dwTrgr; + if (dwAdcClock == 0) return; + while (dwPeriod >= 10 && dwDiv >= 10) + { + dwPeriod /= 10; dwDiv /= 10; + } + dwTrgper = (dwPeriod * dwAdcClock) / dwDiv; + if (dwTrgper % 10) dwTrgper /= 10; + else + { + dwTrgper /= 10; + if (dwTrgper) dwTrgper --; + } + dwTrgr = ADC_TRGR_TRGPER(dwTrgper); + dwTrgr |= pAdc->ADC_TRGR & ~ADC_TRGR_TRGPER_Msk; + pAdc->ADC_TRGR = dwTrgr; +} + + +/** + * Start screen calibration (VDD/GND measurement) + * \param pAdc Pointer to an Adc instance. + */ +void ADC_TsCalibration( Adc *pAdc ) +{ + pAdc->ADC_CR = ADC_CR_TSCALIB; +} + +/** + * Sets the operation mode of the touch screen ADC. The mode can be: + * - \ref ADC_TSMR_TSMODE_NONE (TSADC off) + * - \ref ADC_TSMR_TSMODE_4_WIRE_NO_PM + * - \ref ADC_TSMR_TSMODE_4_WIRE (CH 0~3 used) + * - \ref ADC_TSMR_TSMODE_5_WIRE (CH 0~4 used) + * \param pADC Pointer to an Adc instance. + * \param dwMode Desired mode + */ +void ADC_SetTsMode(Adc* pADC, uint32_t dwMode) +{ + pADC->ADC_TSMR = (pADC->ADC_TSMR & ~ADC_TSMR_TSMODE_Msk) | dwMode; +} + +/** + * Sets the touchscreen pan debounce time. + * \param pADC Pointer to an Adc instance. + * \param dwTime Debounce time in nS. + */ +void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime) +{ + uint32_t dwDiv = 1000000000; + uint32_t dwClk = dwAdcClock; + uint32_t dwPenbc = 0; + uint32_t dwTarget, dwCurrent; + uint32_t dwTsmr; + if (dwTime == 0 || dwAdcClock == 0) return; + /* Divide time & ADCCLK to avoid overflows */ + while ((dwDiv > 1) && ((dwTime % 10) == 0)) + { + dwTime /= 10; dwDiv /= 10; + } + while ((dwDiv > 1) && ((dwClk & 10) == 0)) + { + dwClk /= 10; dwDiv /= 10; + } + /* Compute PENDBC */ + dwTarget = dwTime * dwClk / dwDiv; + dwCurrent = 1; + while (dwCurrent < dwTarget) + { + dwPenbc ++; dwCurrent *= 2; + } + dwTsmr = ADC_TSMR_PENDBC(dwPenbc); + if (dwTsmr == 0) return; + dwTsmr |= pADC->ADC_TSMR & ~ADC_TSMR_PENDBC_Msk; + pADC->ADC_TSMR = dwTsmr; +} + +/** + * Enable/Disable touch screen pen detection. + * \param pADC Pointer to an Adc instance. + * \param bEnDis If true, pen detection is enabled; + * in normal mode otherwise. + */ +void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis) +{ + if (bEnDis) + pADC->ADC_TSMR |= ADC_TSMR_PENDET; + else + pADC->ADC_TSMR &= ~ADC_TSMR_PENDET; +} + + +/** + * Sets the average of the touch screen ADC. The mode can be: + * - \ref ADC_TSMR_TSAV_NO_FILTER (No filtering) + * - \ref ADC_TSMR_TSAV_AVG2CONV (Average 2 conversions) + * - \ref ADC_TSMR_TSAV_AVG4CONV (Average 4 conversions) + * - \ref ADC_TSMR_TSAV_AVG8CONV (Average 8 conversions) + * \param pADC Pointer to an Adc instance. + * \param dwMode Desired mode + */ +void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv) +{ + uint32_t dwMr = pADC->ADC_TSMR & ~ADC_TSMR_TSAV_Msk; + uint32_t dwTSAV = dwAvg2Conv >> ADC_TSMR_TSAV_Pos; + uint32_t dwTSFREQ = (dwMr & ADC_TSMR_TSFREQ_Msk) >> ADC_TSMR_TSFREQ_Pos; + if (dwTSAV) + { + if (dwTSAV > dwTSFREQ) + { + dwMr &= ~ADC_TSMR_TSFREQ_Msk; + dwMr |= ADC_TSMR_TSFREQ(dwTSAV); + } + } + pADC->ADC_TSMR = dwMr | dwAvg2Conv; +} + +/** + * Return X measurement position value. + * \param pADC Pointer to an Adc instance. + */ +uint32_t ADC_GetTsXPosition(Adc *pADC) +{ + return pADC->ADC_XPOSR; +} + +/** + * Return Y measurement position value. + * \param pADC Pointer to an Adc instance. + */ +uint32_t ADC_GetTsYPosition(Adc *pADC) +{ + return pADC->ADC_YPOSR; +} + +/** + * Return Z measurement position value. + * \param pADC Pointer to an Adc instance. + */ +uint32_t ADC_GetTsPressure(Adc *pADC) +{ + return pADC->ADC_PRESSR; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/aes.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/aes.c new file mode 100644 index 000000000..4eb7d6f85 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/aes.c @@ -0,0 +1,274 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup aes_module Working with AES + * \ingroup peripherals_module + * The AES driver provides the interface to configure and use the AES peripheral. + * \n + * + * The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm + * that can be used to protect electronic data. The AES algorithm is a symmetric block + * cipher that can encrypt (encipher) and decrypt (decipher) information. + * Encryption converts data to an unintelligible form called ciphertext. + * Decrypting the ciphertext converts the data back into its original form, + * called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection + * between the encryption and the decryption processes. The AES is capable of using cryptographic + * keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. + * This 128-bit/192-bit/256-bit key is defined in the Key Registers (AES_KEYWRx) and set by + * AES_WriteKey(). The input to the encryption processes of the CBC, CFB, and OFB modes includes, + * in addition to the plaintext, a 128-bit data block called the initialization vector (IV), + * which must be set with AES_SetVector(). + * The initialization vector is used in an initial step in the encryption of a message and + * in the corresponding decryption of the message. The Initialization Vector Registers are + * also used by the CTR mode to set the counter value. + * + * To Enable a AES encryption and decryption,the user has to follow these few steps: + *
    + *
  • A software triggered hardware reset of the AES interface is performed by AES_SoftReset().
    • + *
  • Configure AES algorithm mode, key mode, start mode and operation mode by AES_Configure().
    • + *
  • Input AES data for encryption and decryption with function AES_SetInput()
    • + *
  • Set AES key with fucntion AES_WriteKey().
    • + *
  • To start the encryption or the decryption process with AES_Start()
    • + *
  • To get the encryption or decryption reslut by AES_GetOutput()
    • + *
+ * + * + * For more accurate information, please look at the AES section of the + * Datasheet. + * + * Related files :\n + * \ref aes.c\n + * \ref aes.h\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Advanced Encryption Standard (AES) + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Starts Manual encryption/decryption process. + */ +void AES_Start(void) +{ + AES->AES_CR = AES_CR_START; +} + +/** + * \brief Resets the AES. A software triggered hardware reset of the AES interface is performed. + */ +void AES_SoftReset(void) +{ + AES->AES_CR = AES_CR_SWRST; +} + +/** + * \brief Restarts the countermeasures generator to an internal pre-defined value. + */ +void AES_Recount(void) +{ + AES->AES_CR = AES_CR_LOADSEED; +} + +/** + * \brief Configures an AES peripheral with the specified parameters. + * \param mode Desired value for the AES mode register (see the datasheet). + */ +void AES_Configure(uint32_t mode) +{ + AES->AES_MR = mode; +} + +/** + * \brief Enables the selected interrupts sources on a AES peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void AES_EnableIt(uint32_t sources) +{ + AES->AES_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a AES peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void AES_DisableIt(uint32_t sources) +{ + AES->AES_IDR = sources; +} + +/** + * \brief Get the current status register of the given AES peripheral. + * \return AES status register. + */ +uint32_t AES_GetStatus(void) +{ + return AES->AES_ISR; +} + +/** + * \brief Set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption. + * \param pKey Pointer to a 16/24/32 bytes cipher key. + * \param keyLength length of key + */ +void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength) +{ + AES->AES_KEYWR[0] = pKey[0]; + AES->AES_KEYWR[1] = pKey[1]; + AES->AES_KEYWR[2] = pKey[2]; + AES->AES_KEYWR[3] = pKey[3]; + + if( keyLength >= 24 ) { + AES->AES_KEYWR[4] = pKey[4]; + AES->AES_KEYWR[5] = pKey[5]; + } + if( keyLength == 32 ) { + AES->AES_KEYWR[6] = pKey[6]; + AES->AES_KEYWR[7] = pKey[7]; + } +} + +/** + * \brief Set the for 32-bit input Data allow to set the 128-bit data block used for encryption/decryption. + * \param data Pointer to the 16-bytes data to cipher/decipher. + */ +void AES_SetInput(uint32_t *data) +{ + uint8_t i; + for (i = 0; i< 4; i++) + AES->AES_IDATAR[i] = data[i]; +} + +/** + * \brief Get the four 32-bit data contain the 128-bit data block which has been encrypted/decrypted. + * \param data pointer to the word that has been encrypted/decrypted.. + */ +void AES_GetOutput(uint32_t *data) +{ + uint8_t i; + for (i = 0; i< 4; i++) + data[i] = AES->AES_ODATAR[i]; +} + +/** + * \brief Set four 64-bit initialization vector data block, which is used by some + * modes of operation as an additional initial input. + * \param pVector point to the word of the initialization vector. + */ +void AES_SetVector(const uint32_t *pVector) +{ + AES->AES_IVR[0] = pVector[0]; + AES->AES_IVR[1] = pVector[1]; + AES->AES_IVR[2] = pVector[2]; + AES->AES_IVR[3] = pVector[3]; +} + + +/** + * \brief Set Length in bytes of the AAD data that is to be processed. + * \param len Length. + */ +void AES_SetAadLen(uint32_t len) +{ + AES->AES_AADLENR = len; +} + +/** + * \brief Set Length in bytes of the Length in bytes of the + * plaintext/ciphertext (C) data that is to be processed.. + * \param len Length. + */ +void AES_SetDataLen(uint32_t len) +{ + AES->AES_CLENR = len; +} + +/** + * \brief Set The four 32-bit Hash Word registers expose the intermediate GHASH value. + * May be read to save the current GHASH value so processing can later be resumed, + * presumably on a later message fragment. modes of operation as an additional initial input. + * \param hash point to the word of the hash. + */ +void AES_SetGcmHash(uint32_t * hash) +{ + uint8_t i; + for (i = 0; i< 4; i++) + AES->AES_GHASHR[i] = hash[i]; +} + + +/** + * \brief Get The four 32-bit Tag which contain the final 128-bit GCM Authentication tag + * ¡°T¡± when GCM processing is complete. + * \param tag point to the word of the tag. + */ +void AES_GetGcmTag(uint32_t * tag) +{ + uint8_t i; + for (i = 0; i< 4; i++) + tag[i] = AES->AES_TAGR[i] ; +} + +/** + * \brief Reports the current value of the 32-bit GCM counter + * \param counter Point to value of GCM counter. + */ +void AES_GetGcmCounter(uint32_t * counter) +{ + *counter = AES->AES_CTRR; +} + + +/** + * \brief Get the four 32-bit data contain the 128-bit H value computed from the KEYW value + * \param data point to the word that has been encrypted/decrypted.. + */ +void AES_GetGcmH(uint32_t *h) +{ + uint8_t i; + for (i = 0; i< 4; i++) + h[i] = AES->AES_GCMHR[i]; +} + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/aic.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/aic.c new file mode 100644 index 000000000..8fa1f4071 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/aic.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup aic_module + * + * The Advanced Interrupt Controller (AIC) is an 8-level priority, individually + * maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. + * + * \section Usage + *
    + *
  • Each interrupt source can be enabled or disabled by using the IRQ_EnableIT() and IRQ_DisableIT()
    • + *
  • Configure the AIC interrupt to its requirements and special needs,such as priorty + * level, source type and configure the addresses of the corresponding handler for each interrupt source + * could be setting by IRQ_ConfigureIT().
    • + *
  • Start conversion by setting ADC_CR_START in ADC_CR.
    • + *
+ * + * For more accurate information, please look at the AIC section of the + * Datasheet. + * + * Related files :\n + * \ref aic.c\n + * \ref irq.h\n + */ +/*@{*/ +/*@}*/ + + /** + * \file + * + * Implementation of Advanced Interrupt Controller (AIC) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures an interrupt in the AIC. The interrupt is identified by its + * source (ID_xxx) and is configured to use the specified mode and + * interrupt handler function. Mode is the value that will be put in AIC_SMRx + * and the function address will be set in AIC_SVRx. + * The interrupt is disabled before configuration, so it is useless + * to do it before calling this function. When AIC_ConfigureIT returns, the + * interrupt will always be disabled and cleared; it must be enabled by a + * call to AIC_EnableIT(). + * + * \param source Interrupt source to configure. + * \param mode Triggering mode and priority of the interrupt. + * \param handler Interrupt handler function. + */ +uint32_t IRQ_ConfigureIT(uint32_t source, + uint32_t mode, + void( *handler )( void )) +{ + uint32_t prevHandler; + PMC->PMC_PCER1 = (1 << ( ID_IRQ - 32)); + AIC->AIC_SSR = source; + prevHandler = AIC->AIC_SVR; + /* Disable the interrupt first */ + AIC->AIC_IDCR = AIC_IDCR_INTD; + /* Configure mode and handler */ + AIC->AIC_SMR = mode; + AIC->AIC_SVR = (uint32_t) handler; + /* Clear interrupt */ + AIC->AIC_ICCR = AIC_ICCR_INTCLR; + return prevHandler; +} + + +/** + * \brief Enables interrupts coming from the given (unique) source (ID_xxx). + * + * \param source Interrupt source to enable. + */ +void IRQ_EnableIT(uint32_t source) +{ + AIC->AIC_SSR = source; + AIC->AIC_IECR = AIC_IECR_INTEN; +} + +/** + * \brief Disables interrupts coming from the given (unique) source (ID_xxx). + * + * \param source Interrupt source to disable. + */ +void IRQ_DisableIT(uint32_t source) +{ + AIC->AIC_SSR = source; + AIC->AIC_IDCR = AIC_IDCR_INTD ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/async.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/async.c new file mode 100644 index 000000000..2b52e83e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/async.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Provide a routine for asynchronos transfer. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + /** + * \brief Returns 1 if the given transfer has ended; otherwise returns 0. + * \param pAsync Pointer to an Async instance. + */ +uint32_t ASYNC_IsFinished( Async* pAsync ) +{ + return (pAsync->status != ASYNC_STATUS_PENDING) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/can.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/can.c new file mode 100644 index 000000000..0ef9d5c2c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/can.c @@ -0,0 +1,697 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * Implements functions for Controller Area Network (CAN) + * peripheral operations. + */ +/** \addtogroup can_module + *@{*/ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#if defined(REG_CAN0_MR) || defined(REG_CAN_MR) + +/* ----------- CAN_MR Operations --------------- */ +/** + * \brief Set CAN Mode Register (CAN_MR) + * \param pCan Pointer to Can instance. + * \param dwMr Mode register settings. + */ +void CAN_ConfigureMode(Can *pCan, uint32_t dwMr) +{ + pCan->CAN_MR = dwMr; +} + +/** + * \brief CAN Controller Enable/Disable + * \param pCan Pointer to Can instance. + * \param bEnDis 1 to enable and 0 to disable. + */ +void CAN_Enable(Can *pCan, uint8_t bEnDis) +{ + if (bEnDis) pCan->CAN_MR |= CAN_MR_CANEN; + else pCan->CAN_MR &= ~CAN_MR_CANEN; +} + +/** + * \brief CAN Low Power Mode Enable/Disable + * \param pCan Pointer to Can instance. + * \param bEnDis 1 to enable and 0 to disable. + */ +void CAN_EnableLowPower(Can *pCan, uint8_t bEnDis) +{ + if (bEnDis) pCan->CAN_MR |= CAN_MR_LPM; + else pCan->CAN_MR &= ~CAN_MR_LPM; +} + +/** + * \brief CAN Autobaud/Listen mode + * \param pCan Pointer to Can instance. + * \param bEnDis 1 to enable and 0 to disable. + */ +void CAN_EnableAutobaud(Can *pCan, uint8_t bEnDis) +{ + if (bEnDis) pCan->CAN_MR |= CAN_MR_ABM; + else pCan->CAN_MR &= ~CAN_MR_ABM; +} + +/** + * \brief CAN Overload Frame Enable/Disable + * \param pCan Pointer to Can instance. + * \param bEnDis 1 to enable and 0 to disable. + */ +void CAN_EnableOverloadFrame(Can *pCan, uint8_t bEnDis) +{ + if (bEnDis) pCan->CAN_MR |= CAN_MR_OVL; + else pCan->CAN_MR &= ~CAN_MR_OVL; +} + +/** + * \brief CAN Timestamp capture mode (@EOF/@SOF). + * \param pCan Pointer to Can instance. + * \param bEofSof 1 for EOF/0 for SOF. + */ +void CAN_EnableTimeStampEof(Can *pCan, uint8_t bEofSof) +{ + if (bEofSof) pCan->CAN_MR |= CAN_MR_TEOF; + else pCan->CAN_MR &= ~CAN_MR_TEOF; +} + +/** + * \brief CAN Time Triggered Mode Enable/Disable + * \param pCan Pointer to Can instance. + * \param bEnDis Enable/Disable Time Trigger Mode. + */ +void CAN_EnableTimeTriggerMode(Can *pCan, uint8_t bEnDis) +{ + if (bEnDis) pCan->CAN_MR |= CAN_MR_TTM; + else pCan->CAN_MR &= ~CAN_MR_TTM; +} + +/** + * \brief CAN Timer Freeze Enable/Disable + * \param pCan Pointer to Can instance. + * \param bEnDis Enable/Disable Timer Freeze. + */ +void CAN_EnableTimerFreeze(Can *pCan, uint8_t bEnDis) +{ + if (bEnDis) pCan->CAN_MR |= CAN_MR_TIMFRZ; + else pCan->CAN_MR &= ~CAN_MR_TIMFRZ; +} + +/** + * \brief CAN Repeat Disable/Enable. + * \param pCan Pointer to Can instance. + * \param bEnDis Disable/Enable Repeat. + */ +void CAN_DisableRepeat(Can *pCan, uint8_t bDisEn) +{ + if (bDisEn) pCan->CAN_MR |= CAN_MR_DRPT; + else pCan->CAN_MR &= ~CAN_MR_DRPT; +} + +/* ---------- Interrupt settings ------------- */ + +/** + * \brief CAN Interrupts Enable + * \param pCan Pointer to Can instance. + * \param dwSources Interrupt sources bits. + */ +void CAN_EnableIt(Can *pCan, uint32_t dwSources) +{ + pCan->CAN_IER = dwSources; +} + +/** + * \brief CAN Interrupts Disable + * \param pCan Pointer to Can instance. + * \param dwSources Interrupt sources bits. + */ +void CAN_DisableIt(Can *pCan, uint32_t dwSources) +{ + pCan->CAN_IDR = dwSources; +} + +/** + * \brief Return CAN Interrupts Masks + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetItMask(Can *pCan) +{ + return pCan->CAN_IMR; +} + +/** + * \brief Return CAN Statuses + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetStatus(Can *pCan) +{ + return pCan->CAN_SR; +} + +/** + * \brief Calculate and configure the baudrate + * \param pCan Pointer to Can instance. + * \param dwBaudrate Baudrate value (kB/s) + * allowed: 100, 800, 500, 250, 125, 50, 25, 10 + * \param dwMck MCK. + * \return 1 in success, otherwise return 0. + */ +uint8_t CAN_CalcBaudrate(Can *pCan, uint32_t dwBaudrate, uint32_t dwMck) +{ + uint32_t BRP, PROPAG, PHASE1, PHASE2, SJW; + uint8_t TQ; + uint32_t t1t2; + uint32_t maxClock; + uint32_t id = ID_CAN0; + + if ((uint32_t)pCan == (uint32_t)CAN0) id = ID_CAN0; + else if ((uint32_t)pCan == (uint32_t)CAN1) id = ID_CAN1; + maxClock = PMC_SetPeriMaxClock(id, dwMck); + + if (dwBaudrate >= 1000) TQ = 8; + else TQ = 16; + BRP = (maxClock / (dwBaudrate * 1000 * TQ)) - 1; + if (BRP == 0) { + return 0; + } + + /* Timing delay: + Delay Bus Driver - 50ns + Delay Receiver - 30ns + Delay Bus Line (20m) - 110ns */ + if ( (TQ * dwBaudrate * 2 * (50+30+110)/1000000) >= 1 ) + PROPAG = (TQ * dwBaudrate * 2 * (50+30+110)/1000000) - 1; + else + PROPAG = 0; + t1t2 = TQ - 1 - (PROPAG + 1); + + if ( (t1t2 & 0x01) == 0x01 ) { + PHASE1 = ((t1t2 - 1) / 2) - 1; + PHASE2 = PHASE1 + 1; + } + else { + PHASE1 = ((t1t2) / 2) - 1; + PHASE2 = PHASE1; + } + + if ( 1 > (4/(PHASE1 + 1)) ) SJW = 3; + else SJW = PHASE1; + + if ( (PROPAG + PHASE1 + PHASE2) != (uint32_t)(TQ - 4) ) { + return 0; + } + + pCan->CAN_BR = CAN_BR_PHASE2(PHASE2) + | CAN_BR_PHASE1(PHASE1) + | CAN_BR_PROPAG(PROPAG) + | CAN_BR_SJW(SJW) + | CAN_BR_BRP(BRP) + | CAN_BR_SMP_ONCE; + return 1; +} + +/** + * \brief Set CAN baudrate register + * \param pCan Pointer to Can instance. + * \param dwBr Setting value for CAN_BR. + */ +void CAN_ConfigureBaudrate(Can *pCan, uint32_t dwBr) +{ + pCan->CAN_BR = dwBr; +} + +/** + * \brief Set CAN Sampling Mode + * \param pCan Pointer to Can instance. + * \param bAvg3 Sample 3 times/sample once at sample point. + */ +void CAN_SetSamplingMode(Can *pCan, uint8_t bAvg3) +{ + if (bAvg3) pCan->CAN_BR |= CAN_BR_SMP; + else pCan->CAN_BR &= ~CAN_BR_SMP; +} + +/** + * \brief Return CAN Timer Register + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetTimer(Can *pCan) +{ + return pCan->CAN_TIM; +} + +/** + * \brief Return CAN TimeStamp Register + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetTimestamp(Can *pCan) +{ + return pCan->CAN_TIMESTP; +} + +/** + * \brief Return Error Count (TEC << 16) + REC + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetErrorCount(Can *pCan) +{ + return pCan->CAN_ECR; +} + +/** + * \brief Return Receive Error Count + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetRxErrorCount(Can *pCan) +{ + return (pCan->CAN_ECR & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +/** + * \brief Return Transmit Error Count + * \param pCan Pointer to Can instance. + */ +uint32_t CAN_GetTxErrorCount(Can *pCan) +{ + return (pCan->CAN_ECR & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +/** + * \brief Set Transfer Command Register to initialize transfer requests. + * \param pCan Pointer to Can instance. + * \param dwRequests Transfer Command Requests. + */ +void CAN_Command(Can *pCan, uint32_t dwRequests) +{ + pCan->CAN_TCR = dwRequests; +} + +/** + * \brief Resets CAN internal timer counter. + * \param pCan Pointer to Can instance. + */ +void CAN_ResetTimer(Can *pCan) +{ + pCan->CAN_TCR = CAN_TCR_TIMRST; +} + +/** + * \brief Request transfer on mailbox. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +void CAN_Tx(Can *pCan, uint8_t bMb) +{ + pCan->CAN_TCR = CAN_TCR_MB0 << bMb; +} + +/** + * \brief Abort transfer on several mailboxes. + * \param pCan Pointer to Can instance. + * \param dwAborts Abort requests. + */ +void CAN_Abort(Can *pCan, uint32_t dwAborts) +{ + pCan->CAN_ACR = dwAborts; +} + +/** + * \brief Abort transfer on single mailbox. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +void CAN_AbortMailbox(Can *pCan, uint8_t bMb) +{ + pCan->CAN_ACR = CAN_ACR_MB0 << bMb; +} + +/** + * \brief Configure CAN Message Mode (_MMRx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMr Mode settings. + */ +void CAN_ConfigureMessageMode(Can *pCan, uint8_t bMb, uint32_t dwMr) +{ + pCan->CAN_MB[bMb].CAN_MMR = dwMr; +} + +/** + * \brief Return CAN Message Mode (_MMRx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetMessageMode(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MMR; +} + +/** + * \brief Set Mailbox Timemark for Time Triggered Mode. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param bTimemarks Mailbox timemarks. + */ +void CAN_SetTimemark(Can *pCan, uint8_t bMb, uint8_t bTimemarks) +{ + uint32_t dwMmr = (pCan->CAN_MB[bMb].CAN_MMR) & (~0xFFu); + pCan->CAN_MB[bMb].CAN_MMR = dwMmr | ((bTimemarks << 0) & 0xFF); +} + +/** + * \brief Set Mailbox Priority. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param bPriority Mailbox Priority. + */ +void CAN_SetPriority(Can *pCan, uint8_t bMb, uint8_t bPriority) +{ + uint32_t dwMmr = (pCan->CAN_MB[bMb].CAN_MMR & ~CAN_MMR_PRIOR_Msk); + pCan->CAN_MB[bMb].CAN_MMR = dwMmr | CAN_MMR_PRIOR(bPriority); +} + +/** + * \brief Set Mailbox Object Type. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param bType Mailbox Object Type. + */ +void CAN_SetObjectType(Can *pCan, uint8_t bMb, uint8_t bType) +{ + uint32_t dwMr = (pCan->CAN_MB[bMb].CAN_MMR & CAN_MMR_MOT_Msk) >> CAN_MMR_MOT_Pos; + pCan->CAN_MB[bMb].CAN_MMR |= dwMr | ((bType << CAN_MMR_MOT_Pos) & CAN_MMR_MOT_Msk); +} + +/** + * \brief Configure CAN Message Acceptance Mask (_MAMx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMam The setting value for _MAMx. + */ +void CAN_ConfigureMessageAcceptanceMask(Can *pCan, uint8_t bMb, uint32_t dwMAM) +{ + pCan->CAN_MB[bMb].CAN_MAM = dwMAM; +} + +/** + * \brief Return CAN Message Acceptance Mask (_MAMx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetMessageAcceptanceMask(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MAM; +} + +/** + * \brief Configure Identifier Version in CAN Message Acceptance Mask (_MAMx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param bIdCfg IDvA and IDvB/IDvA only Identify. + */ +void CAN_ConfigureIdentifierMask(Can *pCan, uint8_t bMb, uint8_t bIdCfg) +{ + if (bIdCfg) pCan->CAN_MB[bMb].CAN_MAM |= CAN_MAM_MIDE; + else pCan->CAN_MB[bMb].CAN_MAM &= ~CAN_MAM_MIDE; +} + +/** + * \brief Set Identifier for standard frame mode (MIDvA) mask + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMIDvA Identifier for standard frame mode. + */ +void CAN_SetMIDvAMask(Can *pCan, uint8_t bMb, uint32_t dwIDvA) +{ + uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MAM & CAN_MAM_MIDvA_Msk; + pCan->CAN_MB[bMb].CAN_MAM = dwMam | CAN_MAM_MIDvA(dwIDvA); +} + +/** + * \brief Set Complementary bits for identifier in extended frame mode (MIDvB) mask + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMIDvB Identifier for extended frame mode. + */ +void CAN_SetMIDvBMask(Can *pCan, uint8_t bMb, uint32_t dwIDvA) +{ + uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MAM & CAN_MAM_MIDvB_Msk; + pCan->CAN_MB[bMb].CAN_MAM = dwMam | CAN_MAM_MIDvB(dwIDvA); +} + +/** + * \brief Configure CAN Message ID (_MIDx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMID The setting value for _MIDx. + */ +void CAN_ConfigureMessageID(Can *pCan, uint8_t bMb, uint32_t dwMID) +{ + pCan->CAN_MB[bMb].CAN_MID = dwMID; +} + +/** + * \brief Return CAN Message ID (_MIDx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetMessageID(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MID; +} + +/** + * \brief Configure Identifier Version in CAN Message ID register (_MIDx) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param bIdVer 2.0 Part B/2.0 Part A. + */ +void CAN_ConfigureIdVer(Can *pCan, uint8_t bMb, uint8_t bIdVer) +{ + uint32_t dwMid = pCan->CAN_MB[bMb].CAN_MID & CAN_MID_MIDE; + pCan->CAN_MB[bMb].CAN_MID = dwMid | (bIdVer ? CAN_MID_MIDE : 0); +} + +/** + * \brief Set Identifier for standard frame mode (MIDvA) value + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMIDvA Identifier for standard frame mode. + */ +void CAN_SetMIDvA(Can *pCan, uint8_t bMb, uint32_t dwIDvA) +{ + uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MID & CAN_MID_MIDvA_Msk; + pCan->CAN_MB[bMb].CAN_MID = dwMam | CAN_MID_MIDvA(dwIDvA); +} + +/** + * \brief Set Complementary bits for identifier in extended frame mode (MIDvB) value + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwMIDvB Identifier for extended frame mode. + */ +void CAN_SetMIDvB(Can *pCan, uint8_t bMb, uint32_t dwIDvA) +{ + uint32_t dwMam = pCan->CAN_MB[bMb].CAN_MID & CAN_MID_MIDvB_Msk; + pCan->CAN_MB[bMb].CAN_MID = dwMam | CAN_MID_MIDvB(dwIDvA); +} + +/** + * \brief Return CAN Message Family ID (Masked ID) + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetFamilyID(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MFID; +} + +/** + * \brief Return CAN Message Status + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetMessageStatus(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MSR; +} + +/** + * \brief Return CAN Message Data Low + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetMessageDataL(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MDL; +} + +/** + * \brief Set CAN Message Data Low + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwL Data Low Value. + */ +void CAN_SetMessageDataL(Can *pCan, uint8_t bMb, uint32_t dwL) +{ + pCan->CAN_MB[bMb].CAN_MDL = dwL; +} + +/** + * \brief Set CAN Message Data High + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwH Data High Value. + */ +void CAN_SetMessageDataH(Can *pCan, uint8_t bMb, uint32_t dwH) +{ + pCan->CAN_MB[bMb].CAN_MDH = dwH; +} + +/** + * \brief Return CAN Message Data High + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint32_t CAN_GetMessageDataH(Can *pCan, uint8_t bMb) +{ + return pCan->CAN_MB[bMb].CAN_MDH; +} + +/** + * \brief Copy DW array to CAN Message Data. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param pDwData Pointer to a buffer for data. + */ +void CAN_SetMessage(Can *pCan, uint8_t bMb, uint32_t *pDwData) +{ + pCan->CAN_MB[bMb].CAN_MDL = pDwData[0]; + pCan->CAN_MB[bMb].CAN_MDH = pDwData[1]; +} + +/** + * \brief Copy CAN Message Data to DW array. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param pDwData Pointer to a buffer for data. + */ +void CAN_GetMessage(Can *pCan, uint8_t bMb, uint32_t *pDwData) +{ + pDwData[0] = pCan->CAN_MB[bMb].CAN_MDL; + pDwData[1] = pCan->CAN_MB[bMb].CAN_MDH; +} + +/** + * \brief Set CAN Message Data in u64 + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +void CAN_SetMessageData64(Can *pCan, uint8_t bMb, uint64_t u64) +{ + pCan->CAN_MB[bMb].CAN_MDL = (uint32_t)u64; + pCan->CAN_MB[bMb].CAN_MDH = (u64 >> 32); +} + +/** + * \brief Return CAN Message Data in u64 + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +uint64_t CAN_GetMessageData64(Can *pCan, uint8_t bMb) +{ + uint64_t ddwMd = (uint64_t)pCan->CAN_MB[bMb].CAN_MDH << 32; + ddwMd += pCan->CAN_MB[bMb].CAN_MDL; + return ddwMd; +} + +/** + * \brief Set CAN Message Control Register (_MCRx). + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param dwCtrl Control value. + */ +void CAN_MessageControl(Can *pCan, uint8_t bMb, uint32_t dwCtrl) +{ + pCan->CAN_MB[bMb].CAN_MCR = dwCtrl; +} + +/** + * \brief Start remote frame. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +void CAN_MessageRemote(Can *pCan, uint8_t bMb) +{ + pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MRTR; +} + +/** + * \brief Abort transmission. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +void CAN_MessageAbort(Can *pCan, uint8_t bMb) +{ + pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MACR; +} + +/** + * \brief Start transmission. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + * \param bLen Message length. + */ +void CAN_MessageTx(Can *pCan, uint8_t bMb, uint8_t bLen) +{ + pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MTCR | CAN_MCR_MDLC(bLen); +} + +/** + * \brief Start reception. + * \param pCan Pointer to Can instance. + * \param bMb Mailbox number. + */ +void CAN_MessageRx(Can *pCan, uint8_t bMb) +{ + pCan->CAN_MB[bMb].CAN_MCR = CAN_MCR_MTCR; +} + +#endif +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/dmac.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/dmac.c new file mode 100644 index 000000000..d1441fda7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/dmac.c @@ -0,0 +1,638 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of DMA controller (DMAC). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include +/** \addtogroup dmac_functions DMAC Functions + *@{ + */ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures an DMAC peripheral with modified round robin arbiter. + * + * \param pDmac Pointer to the DMAC peripheral. + */ +void DMAC_Modified_Arbiter( Dmac *pDmac) +{ + assert(pDmac); + pDmac->DMAC_GCFG = DMAC_GCFG_ARB_CFG ; +} + +/** + * \brief Enables a DMAC peripheral. + * + * \param pDmac Pointer to the DMAC peripheral. + */ +void DMAC_Enable( Dmac *pDmac ) +{ + assert(pDmac); + pDmac->DMAC_EN = DMAC_EN_ENABLE; +} + +/** + * \brief Disables a DMAC peripheral. + * + * \param pDmac Pointer to the DMAC peripheral . + */ +void DMAC_Disable( Dmac *pDmac ) +{ + assert(pDmac); + pDmac->DMAC_EN = ~(uint32_t)DMAC_EN_ENABLE; +} + +/** + * \brief Enables DMAC interrupt. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param dwInteruptMask IT to be enabled. + */ +void DMAC_EnableIt (Dmac *pDmac, uint32_t dwInteruptMask ) +{ + assert(pDmac); + pDmac->DMAC_EBCIER = dwInteruptMask; +} + +/** + * \brief Disables DMAC interrupt + * + * \param pDmac Pointer to the DMAC peripheral. + * \param dwInteruptMask IT to be enabled + */ +void DMAC_DisableIt (Dmac *pDmac, uint32_t dwInteruptMask ) +{ + assert(pDmac); + pDmac->DMAC_EBCIDR = dwInteruptMask; +} + +/** + * \brief Get DMAC Interrupt Mask Status. + * + * \param pDmac Pointer to the DMAC peripheral. + * \return DMAC Error, buffer transfer and chained buffer + * transfer interrupt mask register value. + */ +uint32_t DMAC_GetInterruptMask( Dmac *pDmac ) +{ + assert(pDmac); + return (pDmac->DMAC_EBCIMR); +} + +/** + * \brief Get DMAC Error, buffer transfer and chained buffer + * transfer status register. + * + * \param pDmac Pointer to the DMAC peripheral. + * \return DMAC Error, buffer transfer and chained buffer + * transfer status register. + */ +uint32_t DMAC_GetStatus( Dmac *pDmac ) +{ + assert(pDmac); + return (pDmac->DMAC_EBCISR); +} + +/** + * \brief Get DMAC Error, buffer transfer and chained buffer + * transfer status register of the given DMAC peripheral, but + * masking interrupt sources which are not currently enabled. + * + * \param pDmac Pointer to the DMAC peripheral. + * \return DMAC Error, buffer transfer and chained buffer + * transfer status register. + */ +uint32_t DMAC_GetMaskedStatus( Dmac *pDmac ) +{ + uint32_t _dwStatus; + assert(pDmac); + _dwStatus = pDmac->DMAC_EBCISR; + _dwStatus &= pDmac->DMAC_EBCIMR; + return _dwStatus; +} + +/** + * \brief enables the relevant channel of given DMAC. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_EnableChannel( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CHER |= DMAC_CHER_ENA0 << channel; +} + +/** + * \brief enables the relevant channels of given DMAC. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param bmChannels Channels bitmap. + */ +void DMAC_EnableChannels( Dmac *pDmac, uint8_t bmChannels ) +{ + assert(pDmac); + pDmac->DMAC_CHER = bmChannels; +} + +/** + * \brief Disables the relevant channel of given DMAC. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_DisableChannel( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CHDR |= DMAC_CHDR_DIS0 << channel; +} + +/** + * \brief Disables the relevant channels of given DMAC. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param bmChannels Channels bitmap. + */ +void DMAC_DisableChannels( Dmac *pDmac, uint8_t bmChannels ) +{ + assert(pDmac); + pDmac->DMAC_CHDR = bmChannels; +} + +/** + * \brief freezes the relevant channel of given DMAC. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_SuspendChannel( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CHER |= DMAC_CHER_SUSP0 << channel; +} + +/** + * \brief resumes the current channel from an automatic + * stall state of given DMAC. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_KeepChannel( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CHER |= DMAC_CHER_KEEP0 << channel; +} + +/** + * \brief resume the channel transfer restoring its context. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_RestoreChannel( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CHDR |= DMAC_CHDR_RES0 << channel; +} + +/** + * \brief Get DMAC channel handler Status. + * + * \param pDmac Pointer to the DMAC peripheral. + * \return DMAC channel handler status register. + */ +uint32_t DMAC_GetChannelStatus( Dmac *pDmac ) +{ + assert(pDmac); + return (pDmac->DMAC_CHSR); +} + +/** + * \brief Set DMAC source address in a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param saddr sources address. + * \note This register must be aligned with the source transfer width. + */ +void DMAC_SetSourceAddr( Dmac *pDmac, + uint8_t channel, + uint32_t saddr ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_SADDR = saddr; +} + +/** + * \brief Return DMAC source address of a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t DMAC_GetSourceAddr( Dmac *pDmac, + uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + return pDmac->DMAC_CH_NUM[channel].DMAC_SADDR; +} + +/** + * \brief Set DMAC destination address in a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param daddr sources address. + * \note This register must be aligned with the source transfer width. + */ +void DMAC_SetDestinationAddr( Dmac *pDmac, + uint8_t channel, + uint32_t daddr ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_DADDR = daddr; +} + +/** + * \brief Return DMAC destination address of a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t DMAC_GetDestinationAddr( Dmac *pDmac, + uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + return pDmac->DMAC_CH_NUM[channel].DMAC_DADDR; +} + +/** + * \brief Set DMAC descriptor address used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param descr Buffer Transfer descriptor address + * \param descrIf AHB-Lite interface to be fetched + */ +void DMAC_SetDescriptorAddr( Dmac *pDmac, + uint8_t channel, + uint32_t descr, + uint8_t descrif ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + assert(descrif < 2); + //pDmac->DMAC_CH_NUM[channel].DMAC_DSCR = DMAC_DSCR_DSCR( descr ) | descrif; + pDmac->DMAC_CH_NUM[channel].DMAC_DSCR = ( descr & 0xFFFFFFFC ) | descrif; +} + +/** + * \brief Set DMAC controlA used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param controlA Configuration for controlA register. + */ +void DMAC_SetControlA( Dmac *pDmac, + uint8_t channel, + uint32_t controlA ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA = controlA; +} + + +/** + * \brief Set DMAC buffer transfer size used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param bsize number of transfers to be performed. + */ +void DMAC_SetBufferSize( Dmac *pDmac, + uint8_t channel, + uint16_t bsize) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA &= ~DMAC_CTRLA_BTSIZE_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA |= DMAC_CTRLA_BTSIZE( bsize ); +} + +/** + * \brief Set DMAC single transfer size used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param srcWidth source width for single transfer. + * \param dstWidth destination width for single transfer. + */ + void DMAC_SetSingleTransferSize ( Dmac *pDmac, + uint8_t channel, + uint8_t srcWidth, + uint8_t dstWidth ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA &= ~DMAC_CTRLA_SRC_WIDTH_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA &= ~DMAC_CTRLA_DST_WIDTH_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA |= srcWidth | dstWidth; +} + +/** + * \brief Set DMAC single transfer size used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param scSize Size of source chunk transfer. + * \param dcSize Size of destination chunk transfer. + */ +void DMAC_SetChunkTransferSize ( Dmac *pDmac, + uint8_t channel, + uint8_t scSize, + uint8_t dcSize) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA &= ~DMAC_CTRLA_SCSIZE_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA &= ~DMAC_CTRLA_DCSIZE_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLA |= scSize | dcSize; +} + +/** + * \brief Set DMAC controlB used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param controlB Configuration for controlA register. + */ +void DMAC_SetControlB( Dmac *pDmac, + uint8_t channel, + uint32_t controlB ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB = controlB; +} + +/** + * \brief Enables DMAC automatic multiple buffer transfer + * mode used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_EnableAutoMode( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB |= DMAC_CTRLB_AUTO; +} + +/** + * \brief Disable DMAC automatic multiple buffer transfer + * mode used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + */ +void DMAC_DisableAutoMode( Dmac *pDmac, uint8_t channel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_AUTO; +} + +/** + * \brief Select DMAC AHB source interface. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param srcIf Source AHB-Lite interface. + * \param dstIf Destination AHB-Lite interface. + */ +void DMAC_SelectAHBInterface( Dmac *pDmac, + uint8_t channel, + uint8_t srcIf, + uint8_t dstIf ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_SIF_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_DIF_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB |= srcIf | dstIf; +} + + +/** + * \brief Set DMAC Picture-in-Picture mode for source and destination. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param srcPip Source picture-in-picture mode. + * \param srcPip destination picture-in-picture mode. + */ +void DMAC_SetPipMode( Dmac *pDmac, + uint8_t channel, + uint8_t srcPip, + uint8_t dstPip ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM ); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_SRC_PIP; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_DST_PIP; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB |= srcPip | dstPip; +} + +/** + * \brief Set DMAC buffer descriptor fetch mode. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param srcDscr Source buffer descriptor fetch mode. + * \param dstDscr destination buffer descriptor fetch mode. + */ +void DMAC_SetDescFetchMode( Dmac *pDmac, + uint8_t channel, + uint8_t srcDscr, + uint8_t dstDscr ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM ); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_SRC_DSCR; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_DST_DSCR; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB |= srcDscr | dstDscr; +} + +/** + * \brief Set DMAC control B register Flow control bit field. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param flow which device controls the size of the buffer transfer. + */ +void DMAC_SetFlowControl( Dmac *pDmac, + uint8_t channel, + uint8_t flowControl ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB &= ~DMAC_CTRLB_FC_Msk; + pDmac->DMAC_CH_NUM[channel].DMAC_CTRLB |= flowControl; +} + +/** + * \brief Set DMAC CFG register used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param configuration Configuration for CFG register. + */ +void DMAC_SetCFG( Dmac *pDmac, + uint8_t channel, + uint32_t configuration ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_CFG = configuration; +} + +/** + * \brief Set DMAC buffer reload mode. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param srcRep Source buffer reload mode. + * \param dstRep Destination buffer reload mode. + */ +void DMAC_SetReloadMode( Dmac *pDmac, + uint8_t channel, + uint8_t srcRep, + uint8_t dstRep ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM ); + pDmac->DMAC_CH_NUM[channel].DMAC_CFG &= ~DMAC_CFG_SRC_REP; + pDmac->DMAC_CH_NUM[channel].DMAC_CFG &= ~DMAC_CFG_DST_REP; + pDmac->DMAC_CH_NUM[channel].DMAC_CFG |= srcRep | dstRep; +} + +/** + * \brief Set DMAC SW/HW handshaking interface used to + * trigger a transfer request. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param srcH2sel Source handshaking interface. + * \param dstH2sel Destination handshaking interface. + */ +void DMAC_SethandshakeInterface( Dmac *pDmac, + uint8_t channel, + uint8_t srcH2sel, + uint8_t dstH2sel ) +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM ); + pDmac->DMAC_CH_NUM[channel].DMAC_CFG &= ~DMAC_CFG_SRC_H2SEL; + pDmac->DMAC_CH_NUM[channel].DMAC_CFG &= ~DMAC_CFG_DST_H2SEL; + pDmac->DMAC_CH_NUM[channel].DMAC_CFG |= srcH2sel | dstH2sel; +} + + +/** + * \brief Set DMAC source PIP configuration used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param pipHole the value to add to the address when the programmable + * boundary has been reached. + * \param pipBoundary the number of source transfers to perform before + * the automatic address increment operation. + */ +void DMAC_SetSourcePip( Dmac *pDmac, + uint8_t channel, + uint16_t pipHole, + uint16_t pipBoundary) + +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_SPIP = DMAC_SPIP_SPIP_HOLE( pipHole ) | + DMAC_SPIP_SPIP_BOUNDARY( pipBoundary ); +} + +/** + * \brief Set DMAC destination PIP configuration used by a DMAC channel. + * + * \param pDmac Pointer to the DMAC peripheral. + * \param channel Particular channel number. + * \param pipHole the value to add to the address when the programmable + * boundary has been reached. + * \param pipBoundary the number of source transfers to perform before + * the automatic address increment operation. + */ +void DMAC_SetDestPip( Dmac *pDmac, + uint8_t channel, + uint16_t pipHole, + uint16_t pipBoundary) + +{ + assert(pDmac); + assert(channel < DMAC_CHANNEL_NUM); + pDmac->DMAC_CH_NUM[channel].DMAC_DPIP = DMAC_DPIP_DPIP_HOLE( pipHole ) | + DMAC_DPIP_DPIP_BOUNDARY( pipBoundary ); +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/emac.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/emac.c new file mode 100644 index 000000000..a7787eb06 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/emac.c @@ -0,0 +1,562 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + +/** \addtogroup emac_functions + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Write control value + */ +void EMAC_NetworkControl(Emac *pEmac, uint32_t bmNCR) +{ + pEmac->EMAC_NCR = bmNCR; +} + +uint32_t EMAC_GetNetworkControl(Emac *pEmac) +{ + return pEmac->EMAC_NCR; +} + +/** + * Enable/Disable EMAC receive. + */ +void EMAC_ReceiveEnable(Emac* pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCR |= EMAC_NCR_RE; + else pEmac->EMAC_NCR &= ~EMAC_NCR_RE; +} + +/** + * Enable/Disable EMAC transmit. + */ +void EMAC_TransmitEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCR |= EMAC_NCR_TE; + else pEmac->EMAC_NCR &= ~EMAC_NCR_TE; +} + +/** + * Enable/Disable EMAC management. + */ +void EMAC_ManagementEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCR |= EMAC_NCR_MPE; + else pEmac->EMAC_NCR &= ~EMAC_NCR_MPE; +} + +/** + * Clear all statistics registers + */ +void EMAC_ClearStatistics(Emac *pEmac) +{ + pEmac->EMAC_NCR |= EMAC_NCR_CLRSTAT; + //pEmac->EMAC_NCR &= ~EMAC_NCR_CLRSTAT; +} + +/** + * Increase all statistics registers + */ +void EMAC_IncreaseStatistics(Emac *pEmac) +{ + pEmac->EMAC_NCR |= EMAC_NCR_INCSTAT; + //pEmac->EMAC_NCR &= ~EMAC_NCR_INCSTAT; +} + +/** + * Enable/Disable statistics registers writing. + */ +void EMAC_StatisticsWriteEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCR |= EMAC_NCR_WESTAT; + else pEmac->EMAC_NCR &= ~EMAC_NCR_WESTAT; +} + +/** + * In half-duplex mode, forces collisions on all received frames. + */ +void EMAC_BackPressureEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCR |= EMAC_NCR_BP; + else pEmac->EMAC_NCR &= ~EMAC_NCR_BP; +} + +/** + * Start transmission + */ +void EMAC_TransmissionStart(Emac *pEmac) +{ + pEmac->EMAC_NCR |= EMAC_NCR_TSTART; +} + +/** + * Halt transmission + */ +void EMAC_TransmissionHalt(Emac *pEmac) +{ + pEmac->EMAC_NCR |= EMAC_NCR_THALT; +} + +/** + * Setup network configuration register + */ +void EMAC_Configure(Emac *pEmac, uint32_t dwCfg) +{ + pEmac->EMAC_NCFGR = dwCfg; +} + +/** + * Return network configuration. + */ +uint32_t EMAC_GetConfigure(Emac *pEmac) +{ + return pEmac->EMAC_NCFGR; +} + +/** + * Set speed. + * \param bSpeed 1 to indicate 100Mbps, 0 for 10Mbps. + */ +void EMAC_SetSpeed(Emac *pEmac, uint8_t bSpeed) +{ + if (bSpeed) pEmac->EMAC_NCFGR |= EMAC_NCFGR_SPD; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_SPD; +} + + +/** + * Enable/Disable Full-Duplex mode + */ +void EMAC_FullDuplexEnable(Emac *pEmac, uint8_t bFD) +{ + if (bFD) pEmac->EMAC_NCFGR |= EMAC_NCFGR_FD; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_FD; +} + +/** + * Enable/Disable Copy(Receive) All Valid Frames + */ +void EMAC_CpyAllEnable(Emac *pEmac, uint8_t bCAF) +{ + if (bCAF) pEmac->EMAC_NCFGR |= EMAC_NCFGR_CAF; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_CAF; +} + +/** + * Enable/Disable jumbo frames (up to 10240 bytes). + */ +void EMAC_JumboFrameEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_JFRAME; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_JFRAME; +} + +/** + * Disable/Enable broadcase receiving. + */ +void EMAC_BroadcastDisable(Emac *pEmac, uint8_t bDisEna) +{ + if (bDisEna) pEmac->EMAC_NCFGR |= EMAC_NCFGR_NBC; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_NBC; +} + +/** + * Enable/Disable multicast hash + */ +void EMAC_MulticastHashEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_UNI; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_UNI; +} + +/** + * Enable/Disable big frames (over 1518, up to 1536) + */ +void EMAC_BigFrameEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_BIG; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_BIG; +} + +/** + * Set MDC clock divider + * \return 1 if success. + */ +uint8_t EMAC_SetClock(Emac *pEmac, uint32_t dwMck) +{ + uint8_t bCLK = 0; + + /* Not supported */ + if (dwMck > 160*1000*1000) + { + return 0; + } + else if (dwMck > 80*1000*1000) + { + bCLK = 3; + } + else if (dwMck > 40*1000*1000) + { + bCLK = 2; + } + else if (dwMck > 20*1000*1000) + { + bCLK = 1; + } + + pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_CLK_Msk; + pEmac->EMAC_NCFGR |= (EMAC_NCFGR_CLK_Msk & ((bCLK) << EMAC_NCFGR_CLK_Pos)); + + return 1; +} + +/** + * Enable/Disable retry test + */ +void EMAC_RetryTestEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_RTY; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_RTY; +} + +/** + * Enable/Disable pause (when a valid pause frame received). + */ +void EMAC_PauseFrameEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_PAE; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_PAE; +} + +/** + * Set receive buffer offset to 0 ~ 3. + */ +void EMAC_SetRxBufferOffset(Emac *pEmac, uint8_t bOffset) +{ + pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_RBOF_Msk; + pEmac->EMAC_NCFGR |= (EMAC_NCFGR_RBOF_Msk & ((bOffset) << EMAC_NCFGR_RBOF_Pos)); +} + +/** + * Enable/Disable receive length field checking + */ +void EMAC_RxLenthCheckEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_RLCE; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_RLCE; +} + +/** + * Enable/Disable discarding FCS field of received frames. + */ +void EMAC_DiscardFCSEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_DRFCS; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_DRFCS; +} + + +/** + * Enable/Disable frames to be received in half-duplex mode + * while transmitting. + */ +void EMAC_EFRHD(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_EFRHD; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_EFRHD; +} + +/** + * Enable/Disable ignore RX FCS + */ +void EMAC_IRXFCS(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_NCFGR |= EMAC_NCFGR_IRXFCS; + else pEmac->EMAC_NCFGR &= ~EMAC_NCFGR_IRXFCS; +} + +/** + * Return Network Status + */ +uint32_t EMAC_GetStatus(Emac *pEmac) +{ + return pEmac->EMAC_NSR; +} + +/** + * Return mdio_in pin status + */ +uint8_t EMAC_GetMDIO(Emac *pEmac) +{ + return ((pEmac->EMAC_NSR & EMAC_NSR_MDIO) > 0); +} + +/** + * Return 1 if PHY is idle + */ +uint8_t EMAC_IsIdle(Emac *pEmac) +{ + return ((pEmac->EMAC_NSR & EMAC_NSR_IDLE) > 0); +} + +/** + * Return transmit status + */ +uint32_t EMAC_GetTxStatus(Emac *pEmac) +{ + return pEmac->EMAC_TSR; +} + +/** + * Clear transmit status + */ +void EMAC_ClearTxStatus(Emac *pEmac, uint32_t dwStatus) +{ + pEmac->EMAC_TSR = dwStatus; +} + +/** + * Return receive status + */ +uint32_t EMAC_GetRxStatus(Emac *pEmac) +{ + return pEmac->EMAC_RSR; +} + +/** + * Clear receive status + */ +void EMAC_ClearRxStatus(Emac *pEmac, uint32_t dwStatus) +{ + pEmac->EMAC_RSR = dwStatus; +} + +/** + * Set Rx Queue + */ +void EMAC_SetRxQueue(Emac *pEmac, uint32_t dwAddr) +{ + pEmac->EMAC_RBQP = EMAC_RBQP_ADDR_Msk & dwAddr; +} + +/** + * Get Rx Queue Address + */ +uint32_t EMAC_GetRxQueue(Emac *pEmac) +{ + return pEmac->EMAC_RBQP; +} + +/** + * Set Tx Queue + */ +void EMAC_SetTxQueue(Emac *pEmac, uint32_t dwAddr) +{ + pEmac->EMAC_TBQP = EMAC_TBQP_ADDR_Msk & dwAddr; +} + +/** + * Get Tx Queue + */ +uint32_t EMAC_GetTxQueue(Emac *pEmac) +{ + return pEmac->EMAC_TBQP; +} + +/** + * Enable interrupt(s). + */ +void EMAC_EnableIt(Emac *pEmac, uint32_t dwSources) +{ + pEmac->EMAC_IER = dwSources; +} + +/** + * Disable interrupt(s). + */ +void EMAC_DisableIt(Emac *pEmac, uint32_t dwSources) +{ + pEmac->EMAC_IDR = dwSources; +} + +/** + * Return interrupt status. + */ +uint32_t EMAC_GetItStatus(Emac *pEmac) +{ + return pEmac->EMAC_ISR; +} + +/** + * Return interrupt mask. + */ +uint32_t EMAC_GetItMask(Emac *pEmac) +{ + return pEmac->EMAC_IMR; +} + +/** + * Execute PHY maintanance command + */ +void EMAC_PHYMaintain(Emac *pEmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData) +{ + /* Wait until bus idle */ + while((pEmac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Write maintain register */ + pEmac->EMAC_MAN = EMAC_MAN_CODE(0x02) | EMAC_MAN_SOF(0x1) + | EMAC_MAN_PHYA(bPhyAddr) + | EMAC_MAN_REGA(bRegAddr) + | EMAC_MAN_RW((bRW ? 0x2 : 0x1)) + | EMAC_MAN_DATA(wData) + ; +} + +/** + * Return PHY maintainance data returned + */ +uint16_t EMAC_PHYData(Emac *pEmac) +{ + /* Wait until bus idle */ + while((pEmac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Return data */ + return (uint16_t)(pEmac->EMAC_MAN & EMAC_MAN_DATA_Msk); +} + +/** + * Set pause time. + */ +void EMAC_SetPauseTime(Emac *pEmac, uint16_t wPTime) +{ + pEmac->EMAC_PTR = wPTime; +} + +/** + * Set Hash + */ +void EMAC_SetHash(Emac *pEmac, uint32_t dwHashTop, uint32_t dwHashBottom) +{ + pEmac->EMAC_HRB = dwHashBottom; + pEmac->EMAC_HRT = dwHashTop; +} + +/** + * Set Hash + */ +void EMAC_SetHash64(Emac *pEmac, uint64_t ddwHash) +{ + pEmac->EMAC_HRB = (uint32_t)ddwHash; + pEmac->EMAC_HRT = (uint32_t)(ddwHash >> 32); +} + +/** + * Set MAC Address + */ +void EMAC_SetAddress(Emac *pEmac, uint8_t bIndex, uint8_t *pMacAddr) +{ + pEmac->EMAC_SA[bIndex].EMAC_SAxB = (pMacAddr[3] << 24) + | (pMacAddr[2] << 16) + | (pMacAddr[1] << 8) + | (pMacAddr[0] ) + ; + pEmac->EMAC_SA[bIndex].EMAC_SAxT = (pMacAddr[5] << 8) + | (pMacAddr[4] ) + ; +} + +/** + * Set MAC Address via 2 DW + */ +void EMAC_SetAddress32(Emac *pEmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB) +{ + pEmac->EMAC_SA[bIndex].EMAC_SAxB = dwMacB; + pEmac->EMAC_SA[bIndex].EMAC_SAxT = dwMacT; +} + +/** + * Set MAC Address via int64 + */ +void EMAC_SetAddress64(Emac *pEmac, uint8_t bIndex, uint64_t ddwMac) +{ + pEmac->EMAC_SA[bIndex].EMAC_SAxB = (uint32_t)ddwMac; + pEmac->EMAC_SA[bIndex].EMAC_SAxT = (uint32_t)(ddwMac >> 32); +} + +/** + * Set Type ID + */ +void EMAC_SetTypeID(Emac *pEmac, uint16_t wTID) +{ + pEmac->EMAC_TID = EMAC_TID_TID(wTID); +} + +/** + * Get Type ID + */ +uint16_t EMAC_GetTypeID(Emac *pEmac) +{ + return (pEmac->EMAC_TID & EMAC_TID_TID_Msk); +} + +/** + * Enable/Disable RMII + */ +void EMAC_RMIIEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_USRIO |= EMAC_USRIO_RMII; + else pEmac->EMAC_USRIO &= ~EMAC_USRIO_RMII; +} + +/** + * Enable/Disable transceiver input clock + */ +void EMAC_TransceiverClockEnable(Emac *pEmac, uint8_t bEnaDis) +{ + if (bEnaDis) pEmac->EMAC_USRIO |= EMAC_USRIO_CLKEN; + else pEmac->EMAC_USRIO &= ~EMAC_USRIO_CLKEN; +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/fuse.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/fuse.c new file mode 100644 index 000000000..d8c5b5595 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/fuse.c @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \addtogroup fuse_module Working with FUSE + * The Fuse driver provides the Interface for configuration the FUSE + * peripheral. + * + * For more accurate information, please look at the FUSE section of the + * Datasheet. + * + * Related files :\n + * \ref fuse.c\n + * \ref fuse.h.\n +*/ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of FUSE controller. + * + */ +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ +#include "chip.h" + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + + /** + * \brief Read fuse vlaue by given word position. + * + * \param wordPosition select the 32-bit word 0 to 9. + */ + +uint32_t FUSE_Read (uint8_t wordPosition ) +{ + uint32_t fuse; + /* Enable peripheral clock. */ + PMC->PMC_PCER1 = (1 << (ID_FUSE - 32 )); + /* Request read fuse */ + FUSE->FUSE_CR = FUSE_CR_RRQ | FUSE_CR_KEY_VALID; + /* RS and WS bits of the Fuse Index register (FUSE_IR) must be at level one + before issuing the read request */ + while (!((FUSE->FUSE_IR & (FUSE_IR_WS | FUSE_IR_RS)) == (FUSE_IR_WS | FUSE_IR_RS))); + /* Read fuse values, The fuse states are automatically read on CORE startup and are available for reading in the + SR_REG_NB Fuse Status (FUSE_SRx) registers. */ + fuse = FUSE->FUSE_SR[wordPosition]; + /* Disable peripheral clock.*/ + PMC->PMC_PCDR1 = (1 << (ID_FUSE -32 )); + return fuse; +} + +/** + * \brief Program fuse vlaue by given word position. + * + * \param data word to be program. + * \param wordPosition select the 32-bit word 0 to 9. + */ + +void FUSE_Write (uint32_t data, uint8_t wordPosition ) +{ + /* Enable peripheral clock. */ + PMC->PMC_PCER1 = (1 << (ID_FUSE - 32 )); + /* Select the word to write, using the SELW field of the Fuse_Index register (FUSE_IR). */ + FUSE->FUSE_IR = (FUSE_IR_WSEL(wordPosition)); + /* Write the word to program in the Fuse_Data register (FUSE_DR).*/ + FUSE->FUSE_DR = data; + /* Check that RS and WS bits of the Fuse_Index register are at level one (no read and + no write pending). */ + while (!((FUSE->FUSE_IR & (FUSE_IR_WS | FUSE_IR_RS)) == (FUSE_IR_WS | FUSE_IR_RS))); + /* Write the WRQ bit of the Fuse_Control register (FUSE_CR) to begin the fuse programming. */ + FUSE->FUSE_CR = FUSE_CR_WRQ | FUSE_CR_KEY_VALID; + /* Check the WS bit of FUSE_SRx, when WS has a value of ¡°1¡± the fuse write process + is over. */ + while (!((FUSE->FUSE_IR & FUSE_IR_WS) == FUSE_IR_WS)); + /* Disable peripheral clock. */ + PMC->PMC_PCDR1 = (1 << (ID_FUSE - 32 )); +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/gmac.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/gmac.c new file mode 100644 index 000000000..0d664b0ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/gmac.c @@ -0,0 +1,503 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** The buffer addresses written into the descriptors must be aligned so the + last few bits are zero. These bits have special meaning for the GMAC + peripheral and cannot be used as part of the address.*/ + +#define GMAC_ADDRESS_MASK ((uint32_t)0xFFFFFFFC) +#define GMAC_LENGTH_FRAME ((uint32_t)0x3FFF) /** Length of frame mask */ +/** receive buffer descriptor bits */ +#define GMAC_RX_OWNERSHIP_BIT (1 << 0) +#define GMAC_RX_WRAP_BIT (1 << 1) +#define GMAC_RX_SOF_BIT (1 << 14) +#define GMAC_RX_EOF_BIT (1 << 15) + +/** Transmit buffer descriptor bits */ +#define GMAC_TX_LAST_BUFFER_BIT (1 << 15) +#define GMAC_TX_WRAP_BIT (1 << 30) +#define GMAC_TX_USED_BIT (1 << 31) +#define GMAC_TX_RLE_BIT (1 << 29) /** Retry Limit Exceeded */ +#define GMAC_TX_UND_BIT (1 << 28) /** Tx Buffer Underrun */ +#define GMAC_TX_ERR_BIT (1 << 27) /** Exhausted in mid-frame */ +#define GMAC_TX_ERR_BITS \ + (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT) + +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Return 1 if PHY is idle + */ +uint8_t GMAC_IsIdle(Gmac *pGmac) +{ + return ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) > 0); +} + + +/** + * Execute PHY maintanance command + */ +void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData) +{ + /* Wait until bus idle */ + while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Write maintain register */ + pGmac->GMAC_MAN = (~GMAC_MAN_WZO & GMAC_MAN_CLTTO) + | (GMAC_MAN_OP(bRW ? 0x2 : 0x1)) + | GMAC_MAN_WTN(0x02) + | GMAC_MAN_PHYA(bPhyAddr) + | GMAC_MAN_REGA(bRegAddr) + | GMAC_MAN_DATA(wData) ; +} + +/** + * Return PHY maintainance data returned + */ +uint16_t GMAC_PHYData(Gmac *pGmac) +{ + /* Wait until bus idle */ + while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Return data */ + return (uint16_t)(pGmac->GMAC_MAN & GMAC_MAN_DATA_Msk); +} + +/** + * \brief Set MDC clock according to current board clock. Per 802.3, MDC should be + * less then 2.5MHz. + * \param pGmac Pointer to an Gmac instance. + * \param mck Mdc clock + * \return 1 if successfully, 0 if MDC clock not found. + */ +uint8_t GMAC_SetMdcClock( Gmac *pGmac, uint32_t mck ) +{ + uint32_t clock_dividor; + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + if (mck <= 20000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_8; // MDC clock = MCK/8 + } + else if (mck <= 40000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_16; // MDC clock = MCK/16 + } + else if (mck <= 80000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_32; // MDC clock = MCK/32 + } + else if (mck <= 160000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_64; // MDC clock = MCK/64 + } + else if (mck <= 240000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_96; // MDC clock = MCK/96 + } + else if (mck <= 320000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_128; // MDC clock = MCK/128 + } + else if (mck <= 540000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_224; // MDC clock = MCK/224 + } + else { + TRACE_ERROR("E: No valid MDC clock.\n\r"); + return 0; + } + pGmac->GMAC_NCFGR = (pGmac->GMAC_NCFGR & (~GMAC_NCFGR_CLK_Msk)) | clock_dividor; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); + return 1; +} + +/** + * \brief Enable MDI with PHY + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_EnableMdio( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_NCR |= GMAC_NCR_MPE; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief Enable MDI with PHY + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_DisableMdio( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_NCR &= ~GMAC_NCR_MPE; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief Enable MII mode for GMAC, called once after autonegotiate + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_EnableMII( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_UR &= ~GMAC_UR_RGMII; + /*Gigabit Mode disable */ + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief Enable GMII mode for GMAC, called once after autonegotiate + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_EnableGMII( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + /* Gigabit Mode enable */ + pGmac->GMAC_NCFGR |= GMAC_NCFGR_GBE; + /* RGMII disable */ + pGmac->GMAC_UR &= ~GMAC_UR_RGMII; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + + +/** + * \brief Enable RGMII mode for GMAC, called once after autonegotiate + * \param pGmac Pointer to an Gmac instance. + * \param duplex: 1 full duplex 0 half duplex + * \param speed: 0 10M 1 100M 2 1000M + */ +void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE; + if (duplex == GMAC_DUPLEX_HALF) + { + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; + } + else + { + pGmac->GMAC_NCFGR |= GMAC_NCFGR_FD; + } + + + if (speed == GMAC_SPEED_10M) + { + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; + } + else if(speed == GMAC_SPEED_100M) + { + pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; + } + else + { + pGmac->GMAC_NCFGR |= GMAC_NCFGR_GBE; + } + + /* RGMII enable */ + pGmac->GMAC_UR |= GMAC_UR_RGMII; + return; +} + +/** + * \brief Setup the GMAC for the link : speed 100M/10M and Full/Half duplex + * \param pGmac Pointer to an Gmac instance. + * \param speed Link speed, 0 for 10M, 1 for 100M, 2 for 1000M + * \param fullduplex 1 for Full Duplex mode + */ +void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex) +{ + uint32_t ncfgr; + ncfgr = pGmac->GMAC_NCFGR; + ncfgr &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD); + if (speed) { + + ncfgr |= GMAC_NCFGR_SPD; + } + if (fullduplex) { + + ncfgr |= GMAC_NCFGR_FD; + } + pGmac->GMAC_NCFGR = ncfgr; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief set local loop back + * \param pGmac Pointer to an Gmac instance. + */ +uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_LBL; + return 0; +} + +/** + * Return interrupt mask. + */ +uint32_t GMAC_GetItMask(Gmac *pGmac) +{ + return pGmac->GMAC_IMR; +} + + +/** + * Return transmit status + */ +uint32_t GMAC_GetTxStatus(Gmac *pGmac) +{ + return pGmac->GMAC_TSR; +} + +/** + * Clear transmit status + */ +void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus) +{ + pGmac->GMAC_TSR = dwStatus; +} + +/** + * Return receive status + */ +uint32_t GMAC_GetRxStatus(Gmac *pGmac) +{ + return pGmac->GMAC_RSR; +} + +/** + * Clear receive status + */ +void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus) +{ + pGmac->GMAC_RSR = dwStatus; +} + + +/** + * Enable/Disable GMAC receive. + */ +void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis) +{ + if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_RXEN; + else pGmac->GMAC_NCR &= ~GMAC_NCR_RXEN; +} + +/** + * Enable/Disable GMAC transmit. + */ +void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis) +{ + if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_TXEN; + else pGmac->GMAC_NCR &= ~GMAC_NCR_TXEN; +} + + +/** + * Set Rx Queue + */ +void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr) +{ + pGmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & dwAddr; +} + +/** + * Get Rx Queue Address + */ +uint32_t GMAC_GetRxQueue(Gmac *pGmac) +{ + return pGmac->GMAC_RBQB; +} + +/** + * Set Tx Queue + */ +void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr) +{ + pGmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & dwAddr; +} + +/** + * Get Tx Queue + */ +uint32_t GMAC_GetTxQueue(Gmac *pGmac) +{ + return pGmac->GMAC_TBQB; +} + + +/** + * Write control value + */ +void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR) +{ + pGmac->GMAC_NCR = bmNCR; +} + + +/** + * Get control value + */ +uint32_t GMAC_GetNetworkControl(Gmac *pGmac) +{ + return pGmac->GMAC_NCR; +} + + +/** + * Enable interrupt(s). + */ +void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources) +{ + pGmac->GMAC_IER = dwSources; +} + +/** + * Disable interrupt(s). + */ +void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources) +{ + pGmac->GMAC_IDR = dwSources; +} + +/** + * Return interrupt status. + */ +uint32_t GMAC_GetItStatus(Gmac *pGmac) +{ + return pGmac->GMAC_ISR; +} + + +/** + * Set MAC Address + */ +void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr) +{ + pGmac->GMAC_SA[bIndex].GMAC_SAB = (pMacAddr[3] << 24) + | (pMacAddr[2] << 16) + | (pMacAddr[1] << 8) + | (pMacAddr[0] ) + ; + pGmac->GMAC_SA[bIndex].GMAC_SAT = (pMacAddr[5] << 8) + | (pMacAddr[4] ) + ; +} + +/** + * Set MAC Address via 2 DW + */ +void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB) +{ + pGmac->GMAC_SA[bIndex].GMAC_SAB = dwMacB; + pGmac->GMAC_SA[bIndex].GMAC_SAT = dwMacT; +} + +/** + * Set MAC Address via int64 + */ +void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac) +{ + pGmac->GMAC_SA[bIndex].GMAC_SAB = (uint32_t)ddwMac; + pGmac->GMAC_SA[bIndex].GMAC_SAT = (uint32_t)(ddwMac >> 32); +} + + +/** + * Clear all statistics registers + */ +void GMAC_ClearStatistics(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_CLRSTAT; +} + +/** + * Increase all statistics registers + */ +void GMAC_IncreaseStatistics(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_INCSTAT; +} + +/** + * Enable/Disable statistics registers writing. + */ +void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis) +{ + if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_WESTAT; + else pGmac->GMAC_NCR &= ~GMAC_NCR_WESTAT; +} + + +/** + * Setup network configuration register + */ +void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg) +{ + pGmac->GMAC_NCFGR = dwCfg; +} + +/** + * Return network configuration. + */ +uint32_t GMAC_GetConfigure(Gmac *pGmac) +{ + return pGmac->GMAC_NCFGR; +} + + +/** + * Start transmission + */ +void GMAC_TransmissionStart(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_TSTART; +} + +/** + * Halt transmission + */ +void GMAC_TransmissionHalt(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_THALT; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/hsmci.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/hsmci.c new file mode 100644 index 000000000..4ad661392 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/hsmci.c @@ -0,0 +1,597 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * + * Implementation of High Speed MultiMedia Card Interface (HSMCI) controller. + */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** \addtogroup hsmci_functions + *@{ + */ + +/** + * \brief Enable Multi-Media Interface + * + * \param pRMci Pointer to a Hsmci instance + */ +extern void HSMCI_Enable(Hsmci* pRMci) +{ + pRMci->HSMCI_CR = HSMCI_CR_MCIEN; +} + +/** + * \brief Disable Multi-Media Interface + * + * \param pRMci Pointer to a Hsmci instance + */ +extern void HSMCI_Disable(Hsmci* pRMci) +{ + pRMci->HSMCI_CR = HSMCI_CR_MCIDIS; +} + +/** + * \brief Reset (& Disable) Multi-Media Interface + * + * \param mci Pointer to a Hsmci instance + * \param bBackup Backup registers values to keep previous settings, including + * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. + */ +extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup) +{ + if (bBackup) + { + uint32_t mr = pRMci->HSMCI_MR; + uint32_t dtor = pRMci->HSMCI_DTOR; + uint32_t sdcr = pRMci->HSMCI_SDCR; + uint32_t cstor = pRMci->HSMCI_CSTOR; + uint32_t dma = pRMci->HSMCI_DMA; + uint32_t cfg = pRMci->HSMCI_CFG; + + pRMci->HSMCI_CR = HSMCI_CR_SWRST; + + pRMci->HSMCI_MR = mr; + pRMci->HSMCI_DTOR = dtor; + pRMci->HSMCI_SDCR = sdcr; + pRMci->HSMCI_CSTOR = cstor; + pRMci->HSMCI_DMA = dma; + pRMci->HSMCI_CFG = cfg; + } + else + { + pRMci->HSMCI_CR = HSMCI_CR_SWRST; + } +} + +/** + * \brief Select slot + * \param pRMci Pointer to a Hsmci instance + * \param bSlot Slot ID (0~3 for A~D). + */ +extern void HSMCI_Select(Hsmci *pRMci, uint8_t bSlot, uint8_t bBusWidth) +{ + uint32_t dwSdcr; + dwSdcr = (HSMCI_SDCR_SDCSEL_Msk & bSlot); + switch(bBusWidth) + { + case 1: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1; + break; + case 4: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4; + break; + case 8: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8; + break; + } +} + +/** + * \brief Set slot + * \param pRMci Pointer to a Hsmci instance + * \param bSlot Slot ID (0~3 for A~D). + */ +extern void HSMCI_SetSlot(Hsmci *pRMci, uint8_t bSlot) +{ + uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCSEL_Msk; + pRMci->HSMCI_SDCR = dwSdcr | (HSMCI_SDCR_SDCSEL_Msk & bSlot); +} + +/** + * \brief Set bus width of MCI + * \param pRMci Pointer to a Hsmci instance + * \param bBusWidth 1,4 or 8 (bits). + */ +extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth) +{ + uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk; + switch(bBusWidth) + { + case 1: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1; + break; + case 4: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4; + break; + case 8: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8; + break; + } +} + +/** + * \brief Return bus width setting. + * + * \param pRMci Pointer to an MCI instance. + * \return 1, 4 or 8. + */ +extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci) +{ + switch(pRMci->HSMCI_SDCR & HSMCI_SDCR_SDCBUS_Msk) + { + case HSMCI_SDCR_SDCBUS_1: return 1; + case HSMCI_SDCR_SDCBUS_4: return 4; + case HSMCI_SDCR_SDCBUS_8: return 8; + } + return 0; +} + +/** + * \brief Configures a MCI peripheral as specified. + * + * \param pRMci Pointer to an MCI instance. + * \param dwMode Value of the MCI Mode register. + */ +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode) +{ + pRMci->HSMCI_MR = dwMode; +} + +/** + * \brief Return mode register + * \param pRMci Pointer to an MCI instance. + */ +extern uint32_t HSMCI_GetMode(Hsmci * pRMci) +{ + return pRMci->HSMCI_MR; +} + +/** + * \brief Enable/Disable R/W proof + * + * \param pRMci Pointer to an MCI instance. + * \param bRdProof Read proof enable/disable. + * \param bWrProof Write proof enable/disable. + */ +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof) +{ + uint32_t mr = pRMci->HSMCI_MR; + pRMci->HSMCI_MR = (mr & (~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF))) + | (bRdProof ? HSMCI_MR_RDPROOF : 0) + | (bWrProof ? HSMCI_MR_WRPROOF : 0) + ; +} + +/** + * \brief Padding value setting. + * + * \param pRMci Pointer to an MCI instance. + * \param bPadvEn Padding value 0xFF/0x00. + */ +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv) +{ + if (bPadv) + { + pRMci->HSMCI_MR |= HSMCI_MR_PADV; + } + else + { + pRMci->HSMCI_MR &= ~HSMCI_MR_PADV; + } +} + +/** + * \brief Force byte transfer enable/disable. + * + * \param pRMci Pointer to an MCI instance. + * \param bFByteEn FBYTE enable/disable. + */ +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn) +{ + if (bFByteEn) + { + pRMci->HSMCI_MR |= HSMCI_MR_FBYTE; + } + else + { + pRMci->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } +} + +/** + * \brief Check if Force Byte mode enabled. + * + * \param pRMci Pointer to an MCI instance. + * \return 1 if _FBYTE is enabled. + */ +extern uint8_t HSMCI_IsFByteEnabled(Hsmci *pRMci) +{ + return ((pRMci->HSMCI_MR & HSMCI_MR_FBYTE) > 0); +} + +/** + * \brief Set Clock Divider & Power save divider for MCI. + * + * \param pRMci Pointer to an MCI instance. + * \param bClkDiv Clock Divider value (0 ~ 255). + * \param bPwsDiv Power Saving Divider (1 ~ 7). + */ +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv) +{ + uint32_t mr = pRMci->HSMCI_MR; + uint32_t clkdiv ,clkodd; + clkdiv = bClkDiv - 2 ; + clkodd = (bClkDiv & 1)? HSMCI_MR_CLKODD: 0; + clkdiv = clkdiv >> 1; + + pRMci->HSMCI_MR = (mr & ~(HSMCI_MR_CLKDIV_Msk | HSMCI_MR_PWSDIV_Msk)) + | HSMCI_MR_CLKDIV(clkdiv) + | HSMCI_MR_PWSDIV(bPwsDiv) + | clkodd + ; +} + +/** + * \brief Enables one or more interrupt sources of MCI peripheral. + * + * \param pRMci Pointer to an Hsmci instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources) +{ + pRMci->HSMCI_IER = dwSources; +} + +/** + * \brief Disable one or more interrupt sources of MCI peripheral. + * + * \param pRMci Pointer to an Hsmci instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources) +{ + pRMci->HSMCI_IDR = dwSources; +} + +/** + * \brief Return the interrupt mask register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI interrupt mask register. + */ +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci) +{ + return (pRMci->HSMCI_IMR) ; +} + +/** + * \brief Set block len & count for transfer + * + * \param pRMci Pointer to an Hsmci instance. + * \param wBlkLen Block size. + * \param wCnt Block(byte) count. + */ +extern void HSMCI_ConfigureTransfer(Hsmci *pRMci, + uint16_t wBlkLen, + uint16_t wCnt) +{ + pRMci->HSMCI_BLKR = (wBlkLen << 16) | wCnt; +} + +/** + * \brief Set block length + * + * Count is reset to 0. + * + * \param pRMci Pointer to an Hsmci instance. + * \param wBlkSize Block size. + */ +extern void HSMCI_SetBlockLen(Hsmci *pRMci, uint16_t wBlkSize) +{ + pRMci->HSMCI_BLKR = wBlkSize << 16; +} + +/** + * \brief Set block (byte) count + * + * \param pRMci Pointer to an Hsmci instance. + * \param wBlkCnt Block(byte) count. + */ +extern void HSMCI_SetBlockCount(Hsmci *pRMci, uint16_t wBlkCnt) +{ + pRMci->HSMCI_BLKR |= wBlkCnt; +} + +/** + * \brief Configure the Completion Signal Timeout + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Completion Signal Timeout configure. + */ +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_CSTOR = dwConfigure; +} + +/** + * \brief Configure the Data Timeout + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Data Timeout configure. + */ +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_DTOR = dwConfigure; +} + +/** + * \brief Send command + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwCmd Command register value. + * \param dwArg Argument register value. + */ +extern void HSMCI_SendCmd(Hsmci *pRMci, uint32_t dwCmd, uint32_t dwArg) +{ + pRMci->HSMCI_ARGR = dwArg; + pRMci->HSMCI_CMDR = dwCmd; +} + + +/** + * \brief Return the response register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI response register. + */ +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci) +{ + return pRMci->HSMCI_RSPR[0]; +} + +/** + * \brief Return the receive data register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI receive data register. + */ +extern uint32_t HSMCI_Read(Hsmci *pRMci) +{ + return pRMci->HSMCI_RDR; +} + +/** + * \brief Read from FIFO + * + * \param pRMci Pointer to an Hsmci instance. + * \param pdwData Pointer to data buffer. + * \param dwSize Size of data buffer (in DWord). + */ +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize) +{ + volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO); + register uint32_t c4, c1; + + if (dwSize == 0) + return; + + c4 = dwSize >> 2; + c1 = dwSize & 0x3; + + for(;c4;c4 --) + { + *pdwData ++ = *pFIFO ++; + *pdwData ++ = *pFIFO ++; + *pdwData ++ = *pFIFO ++; + *pdwData ++ = *pFIFO ++; + } + for(;c1;c1 --) + { + *pdwData ++ = *pFIFO ++; + } +} + +/** + * \brief Sends data through MCI peripheral. + * + * \param pRMci Pointer to an Hsmci instance. + * \param + */ +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData) +{ + pRMci->HSMCI_TDR = dwData; +} + +/** + * \brief Write to FIFO + * + * \param pRMci Pointer to an Hsmci instance. + * \param pdwData Pointer to data buffer. + * \param dwSize Size of data buffer (In DWord). + */ +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize) +{ + volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO); + register uint32_t c4, c1; + + if (dwSize == 0) + return; + + c4 = dwSize >> 2; + c1 = dwSize & 0x3; + + for(;c4;c4 --) + { + *pFIFO ++ = *pdwData ++; + *pFIFO ++ = *pdwData ++; + *pFIFO ++ = *pdwData ++; + *pFIFO ++ = *pdwData ++; + } + for(;c1;c1 --) + { + *pFIFO ++ = *pdwData ++; + } +} + +/** + * \brief Return the status register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI status register. + */ +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci) +{ + return pRMci->HSMCI_SR; +} + +/** + * \brief Configure the HSMCI DMA + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Configure value. + */ +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_DMA = dwConfigure; +} + +/** + * \brief Enable the HSMCI DMA + * + * \param pRMci Pointer to an Hsmci instance. + * \param bEnable 1 to enable, 0 to disable. + */ +extern void HSMCI_EnableDma(Hsmci *pRMci, uint8_t bEnable) +{ + if (bEnable) + { + pRMci->HSMCI_DMA |= HSMCI_DMA_DMAEN ;//| HSMCI_DMA_CHKSIZE_32; + } + else + { + pRMci->HSMCI_DMA &= ~HSMCI_DMA_DMAEN; + } +} + +/** + * \brief Enable the HSMCI DMA + * + * \param pRMci Pointer to an Hsmci instance. + * \param bOffset Offset value. + */ +extern void HSMCI_SetDmaOffset(Hsmci *pRMci, uint8_t bOffset) +{ + uint32_t dwDma = pRMci->HSMCI_DMA & (~HSMCI_DMA_OFFSET_Msk); + pRMci->HSMCI_DMA = dwDma | HSMCI_DMA_OFFSET(bOffset); +} + +/** + * \brief Configure the HSMCI + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Configure value. + */ +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_CFG = dwConfigure; +} + +/** + * \brief Enable/Disable High-Speed mode for MCI + * + * \param pRMci Pointer to an Hsmci instance. + * \param bHsEnable Enable/Disable high-speed. + */ +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable) +{ + if (bHsEnable) + { + pRMci->HSMCI_CFG |= HSMCI_CFG_HSMODE; + } + else + { + pRMci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; + } +} + +/** + * \brief Check if High-speed mode is enabled on MCI + * \param pRMci Pointer to an Hsmci instance. + * \return 1 + */ +extern uint8_t HSMCI_IsHsEnabled(Hsmci * pRMci) +{ + return ((pRMci->HSMCI_CFG & HSMCI_CFG_HSMODE) > 0); +} + +/** + * \brief Configure the Write Protection Mode + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure WP mode configure value. + */ +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_WPMR = dwConfigure; +} + +/** + * \brief Return the write protect status register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI write protect status register. + */ +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci) +{ + return pRMci->HSMCI_WPSR; +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/isi.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/isi.c new file mode 100644 index 000000000..5d19b11f0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/isi.c @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enable ISI + */ +void ISI_Enable(void) +{ + REG_ISI_CR |= ISI_CR_ISI_EN; + while( (REG_ISI_SR & ISI_CR_ISI_EN)!=ISI_CR_ISI_EN); + REG_ISI_DMA_CHER |= ISI_DMA_CHER_P_CH_EN | ISI_DMA_CHER_C_CH_EN; +} + + +/** + * \brief Disable ISI + */ +void ISI_Disable(void) +{ + REG_ISI_CR |= ISI_CR_ISI_DIS; + REG_ISI_DMA_CHDR |= ISI_DMA_CHDR_P_CH_DIS; +} + + +/** + * \brief Enable ISI interrupt + * \param flag of interrupt to enable + */ +void ISI_EnableInterrupt(uint32_t flag) +{ + REG_ISI_IER = flag; +} + + +/** + * \brief Disable ISI interrupt + * \param flag of interrupt to disable + */ +void ISI_DisableInterrupt(uint32_t flag) +{ + REG_ISI_IDR = flag; +} + + + +/** + * \brief Return ISI status register + * \return Status of ISI register + */ +uint32_t ISI_StatusRegister(void) +{ + return(REG_ISI_SR); +} + + +/** + * \brief Enable Codec path for capture next frame + */ +void ISI_CodecPathFull(void) +{ + // The codec path is enabled and the next frame is captured. + // Both codec and preview datapaths are working simultaneously + REG_ISI_CR |= ISI_CR_ISI_CDC; + REG_ISI_CFG1 |= ISI_CFG1_FULL; +} + + +/** + * \brief Set frame rate + * \param frate frame rate capture + */ +void ISI_SetFrame(uint32_t frate) +{ + if( frate > 7 ) { + TRACE_ERROR("FRate too big\n\r"); + frate = 7; + } + REG_ISI_CFG1 |= ISI_CFG1_FRATE(frate); +} + + +/** + * \brief Get the number of byte per pixels + * \param bmpRgb BMP type can be YUV or RGB + */ +uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb) +{ + uint8_t nbByte_Pixel; + + if (bmpRgb == RGB) { + if ((REG_ISI_CFG2 & ISI_CFG2_RGB_MODE) == ISI_CFG2_RGB_MODE){ + // RGB: 5:6:5 16bits/pixels + nbByte_Pixel = 2; + } + else { + // RGB: 8:8:8 24bits/pixels + nbByte_Pixel = 3; + } + } + else { + // YUV: 2 pixels for 4 bytes + nbByte_Pixel = 2; + } + return nbByte_Pixel; +} + + +/** + * \brief Reset ISI + */ +void ISI_Reset(void) +{ + uint32_t timeout=0; + + // Resets the image sensor interface. + // Finish capturing the current frame and then shut down the module. + REG_ISI_CR = ISI_CR_ISI_SRST | ISI_CR_ISI_DIS; + // wait Software reset has completed successfully. + while( (!(REG_ISI_SR & ISI_SR_SRST)) + && (timeout < 0x5000) ){ + timeout++; + } + if( timeout == 0x5000 ) { + TRACE_ERROR("ISI-Reset timeout\n\r"); + } +} + +/** + * \brief ISI initialize + * \param pVideo structure of video driver + */ +void ISI_Init(pIsi_Video pVideo) +{ + uint32_t hRatio, vRatio; + ISI_Reset(); + + // SLD pixel clock periods to wait before the beginning of a line. + // SFD lines are skipped at the beginning of the frame. + REG_ISI_CFG1 |= ISI_CFG1_SLD(pVideo->Hblank) + ISI_CFG1_SFD(pVideo->Vblank); + TRACE_DEBUG("ISI_CFG1=0x%X\n\r", REG_ISI_CFG1); + + // IM_VSIZE: Vertical size of the Image sensor [0..2047] + // Vertical size = IM_VSIZE + 1 + // IM_HSIZE: Horizontal size of the Image sensor [0..2047] + // Horizontal size = IM_HSIZE + 1 + // YCC_SWAP : YCC image data + REG_ISI_CFG2 = ISI_CFG2_IM_VSIZE(pVideo->codec_vsize - 1) + + ISI_CFG2_IM_HSIZE(pVideo->codec_hsize - 1); + + if (pVideo->rgb_or_yuv == RGB) { + REG_ISI_CFG2 |= ISI_CFG2_COL_SPACE | ISI_CFG2_RGB_MODE ; + } + else { + REG_ISI_CFG2|= ISI_CFG2_YCC_SWAP(2) ; + } + TRACE_DEBUG("ISI_CFG2=0x%X\n\r", REG_ISI_CFG2); + + // Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode). + // Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode). + + if( (pVideo->lcd_vsize > 480) || (pVideo->lcd_hsize > 640)) { + TRACE_ERROR("Size LCD bad define %u, %u\n\r",(unsigned int)pVideo->lcd_vsize ,(unsigned int)pVideo->lcd_hsize); + REG_ISI_PSIZE = ((480 - 1) ) + (((640-1) << 16) ); + } + else { + REG_ISI_PSIZE = ((pVideo->lcd_vsize -1)) + (((pVideo->lcd_hsize -1) << 16) ); + } + // DEC_FACTOR is 8-bit width, range is from 16 to 255. + // Values from 0 to 16 do not perform any decimation. + //REG_ISI_PDECF = (16 * pVideo->codec_hsize)/640; + hRatio = (16 * pVideo->codec_hsize)/(pVideo->lcd_hsize); + vRatio = (16 * pVideo->codec_vsize)/(pVideo->lcd_vsize); + REG_ISI_PDECF = (hRatio > vRatio )? vRatio: hRatio; + + if (REG_ISI_PDECF < 16) REG_ISI_PDECF = 16; + + REG_ISI_DMA_P_DSCR = pVideo->Isi_fbd_base; + REG_ISI_DMA_P_CTRL = ISI_DMA_P_CTRL_P_FETCH; + REG_ISI_DMA_P_ADDR = pVideo->lcd_fb_addr; + + REG_ISI_DMA_C_DSCR = pVideo->codec_fbd_base; + REG_ISI_DMA_C_CTRL = ISI_DMA_C_CTRL_C_FETCH; + REG_ISI_DMA_C_ADDR = pVideo->codec_fb_addr; + + // C0: Color Space Conversion Matrix Coefficient C0 + // C1: Color Space Conversion Matrix Coefficient C1 + // C2: Color Space Conversion Matrix Coefficient C2 + // C3: Color Space Conversion Matrix Coefficient C3 + REG_ISI_Y2R_SET0 = ISI_Y2R_SET0_C0(0x95) + + ISI_Y2R_SET0_C1(0xFF) + + ISI_Y2R_SET0_C2(0x68) + + ISI_Y2R_SET0_C3(0x32); + + // C4: Color Space Conversion Matrix coefficient C4 + // Yoff: Color Space Conversion Luminance 128 offset + // Croff: Color Space Conversion Red Chrominance 16 offset + // Cboff: Color Space Conversion Blue Chrominance 16 offset + REG_ISI_Y2R_SET1 = ISI_Y2R_SET1_C4(0xCC) + + ISI_Y2R_SET1_Yoff + + ISI_Y2R_SET1_Croff + + ISI_Y2R_SET1_Cboff; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/mmu.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/mmu.c new file mode 100644 index 000000000..a2aeb93a8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/mmu.c @@ -0,0 +1,243 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** + * \addtogroup mmu MMU Initialization + * + * \section Usage + * + * Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or + * translation table entries. TLBs avoid the requirement for every memory access to perform a translation table + * lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a + * similar way to the requirements for caches, the architecture only defines certain principles for TLBs: + * + * The MMU supports memory accesses based on memory sections or pages: + * Supersections Consist of 16MB blocks of memory. Support for Supersections is optional. + * -# Sections Consist of 1MB blocks of memory. + * -# Large pages Consist of 64KB blocks of memory. + * -# Small pages Consist of 4KB blocks of memory. + * + * Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry. + * Memory region attributes + * Each TLB entry has an associated set of memory region attributes. These control accesses to the caches, + * how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent. + * + * Related files:\n + * \ref mmu.c\n + * \ref mmu.h \n + */ + +/*------------------------------------------------------------------------------ */ +/* Headers */ +/*------------------------------------------------------------------------------ */ +#include + +/*------------------------------------------------------------------------------ */ +/* Exported functions */ +/*------------------------------------------------------------------------------ */ + +/** + * \brief Initializes MMU. + * \param pTB Address of the translation table. + */ +void MMU_Initialize(uint32_t *pTB) +{ + unsigned int index; + unsigned int addr; + + /* Reset table entries */ + for (index = 0; index < 4096; index++) + pTB[index] = 0; + + /* section Boot (code + data)*/ + /* ROM address (after remap) 0x0000_0000*/ + pTB[0x000] = (0x000 << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* section ROM (code + data) */ + /* ROM address (after remap) 0x0010_0000 */ + pTB[0x001] = (0x001 << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* section NFC SRAM */ + /* SRAM address 0x0020_0000 */ + pTB[0x002] = (0x002 << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* section RAM 0 */ + /* SRAM address (after remap) 0x0030_0000 */ + pTB[0x003] = (0x003 << 20)| // Physical Address + ( 1 << 12)| // TEX[0] + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 1 << 3)| // C bit : cachable => YES + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* section NFC SRAM */ + /* SRAM address 0x0040_0000 */ + for(addr = 0x4; addr < 0xB; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + + /* section PERIPH */ + /* periph address 0xF000_0000 */ + pTB[0xF00] = (0xF00ul << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0 + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section PERIPH */ + /* periph address 0xF800_0000 */ + pTB[0xF80] = (0xF80ul << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section PERIPH */ + /* periph address 0xFFF0_0000 */ + pTB[0xFFF] = (0xFFFul << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section EBI CS0 */ + /* periph address 0x1000_0000 */ + for(addr = 0x100; addr < 0x200; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0 + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section EBI CS1 */ + /* periph address 0x4000_0000 */ + for(addr = 0x400; addr < 0x500; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section EBI CS2 */ + /* periph address 0x5000_0000 */ + for(addr = 0x500; addr < 0x600; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section EBI CS3 */ + /* periph address 0x6000_0000 */ + for(addr = 0x600; addr < 0x700; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section NFC */ + /* periph address 0x7000_0000 */ + for(addr = 0x700; addr < 0x800; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => NO + ( 0 << 2)| // B bit : write-back => NO + ( 2 << 0); // Set as 1 Mbyte section + + /* section SDRAM/DDRAM */ + /* periph address 0x2000_0000 */ + for(addr = 0x200; addr < 0x230; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 1 << 12)| // TEX[0] + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 1 << 3)| // C bit : cachable => YES + ( 1 << 2)| // B bit : write-back => YES + ( 2 << 0); // Set as 1 Mbyte section + +/* section SDRAM/DDRAM */ + /* periph address 0x2100_0000 */ + for(addr = 0x230; addr < 0x280; addr++) + pTB[addr] = (addr << 20)| // Physical Address + ( 3 << 10)| // Access in supervisor mode (AP) + ( 0xF << 5)| // Domain 0xF + ( 1 << 4)| // (XN) + ( 0 << 3)| // C bit : cachable => No + ( 0 << 2)| // B bit : write-back => No + ( 2 << 0); // Set as 1 Mbyte section + + CP15_WriteTTB((unsigned int)pTB); + /* Program the domain access register */ + CP15_WriteDomainAccessControl(0xC0000000); // only domain 15: access are not checked +} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pio.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pio.c new file mode 100644 index 000000000..62443fe5e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pio.c @@ -0,0 +1,516 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled by + * peripheral A. Optionally, the corresponding internal pull-up(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralA( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PPDDR = mask; + pio->PIO_PUER = mask; + } + else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] &= (~mask & abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] &= (~mask & abcdsr); + pio->PIO_PDR = mask; + +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled by + * peripheral B. Optionally, the corresponding internal pull-up(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralB( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PPDDR = mask; + pio->PIO_PUER = mask; + } + else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] = (mask | abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] &= (~mask & abcdsr); + + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled by + * peripheral C. Optionally, the corresponding internal pull-up(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralC( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PPDDR = mask; + pio->PIO_PUER = mask; + } + else { + + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] &= (~mask & abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] = (mask | abcdsr); + + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled by + * peripheral D. Optionally, the corresponding internal pull-up(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralD( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + + pio->PIO_PPDDR = mask; + pio->PIO_PUER = mask; + } + else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] = (mask | abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] = (mask | abcdsr); + + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally, + * the corresponding internal pull-up(s) and glitch filter(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask indicating which pin(s) to configure as input(s). + * \param enablePullUp Indicates if the internal pull-up(s) must be enabled. + * \param enableFilter Indicates if the glitch filter(s) must be enabled. + */ +static void PIO_SetInput( + Pio *pio, + unsigned int mask, + unsigned char attribute) +{ + /* Disable interrupts */ + pio->PIO_IDR = mask; + + /* Enable pull-up(s) if necessary */ + if (attribute & PIO_PULLUP) + { + pio->PIO_PPDDR = mask; + pio->PIO_PUER = mask; + } + else + { + pio->PIO_PUDR = mask; + } + /* Enable Input Filter if necessary */ + if (attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) + pio->PIO_IFER = mask; + else + pio->PIO_IFDR = mask; + + /* Enable de-glitch or de-bounce if necessary */ + if (attribute & PIO_DEGLITCH) { + pio->PIO_IFSCDR = mask; + } else if (attribute & PIO_DEBOUNCE) { + pio->PIO_IFSCER = mask; + } + + /* Configure pin as input */ + pio->PIO_ODR = mask; + pio->PIO_PER = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as outputs, with the + * given default value. Optionally, the multi-drive feature can be enabled + * on the pin(s). + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask indicating which pin(s) to configure. + * \param defaultValue Default level on the pin(s). + * \param enableMultiDrive Indicates if the pin(s) shall be configured as + * open-drain. + * \param enablePullUp Indicates if the pin shall have its pull-up activated. + */ +static void PIO_SetOutput( + Pio *pio, + unsigned int mask, + unsigned char defaultValue, + unsigned char enableMultiDrive, + unsigned char enablePullUp) +{ + /* Disable interrupts */ + pio->PIO_IDR = mask; + + /* Enable pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PPDDR = mask; + pio->PIO_PUER = mask; + } + else { + pio->PIO_PUDR = mask; + } + + /* Enable multi-drive if necessary */ + if (enableMultiDrive) { + + pio->PIO_MDER = mask; + } + else { + + pio->PIO_MDDR = mask; + } + + /* Set default value */ + if (defaultValue) { + + pio->PIO_SODR = mask; + } + else { + + pio->PIO_CODR = mask; + } + + /* Configure pin(s) as output(s) */ + pio->PIO_OER = mask; + pio->PIO_PER = mask; +} + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a list of Pin instances, each of which can either hold a single + * pin or a group of pins, depending on the mask value; all pins are configured + * by this function. The size of the array must also be provided and is easily + * computed using PIO_LISTSIZE whenever its length is not known in advance. + * + * \param list Pointer to a list of Pin instances. + * \param size Size of the Pin list (calculated using PIO_LISTSIZE). + * + * \return 1 if the pins have been configured properly; otherwise 0. + */ +uint8_t PIO_Configure( const Pin *list, uint32_t size ) +{ + /* Configure pins */ + while ( size > 0 ) + { + switch ( list->type ) + { + + case PIO_PERIPH_A: + PIO_SetPeripheralA(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_B: + PIO_SetPeripheralB(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_C: + PIO_SetPeripheralC(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_D: + PIO_SetPeripheralD(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + case PIO_INPUT: + PMC_EnablePeripheral(list->id); + PIO_SetInput(list->pio, + list->mask, + list->attribute); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + PIO_SetOutput(list->pio, + list->mask, + (list->type == PIO_OUTPUT_1), + (list->attribute & PIO_OPENDRAIN) ? 1 : 0, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: return 0; + } + + list++; + size--; + } + + return 1; +} + +/** + * \brief Sets a high output level on all the PIOs defined in the given Pin instance. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will memorize the value they are changed to outputs. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ +void PIO_Set(const Pin *pin) +{ + pin->pio->PIO_SODR = pin->mask; +} + +/** + * \brief Sets a low output level on all the PIOs defined in the given Pin instance. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will memorize the value they are changed to outputs. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ +void PIO_Clear(const Pin *pin) +{ + pin->pio->PIO_CODR = pin->mask; +} + +/** + * \brief Returns 1 if one or more PIO of the given Pin instance currently have + * a high level; otherwise returns 0. This method returns the actual value that + * is being read on the pin. To return the supposed output value of a pin, use + * PIO_GetOutputDataStatus() instead. + * + * \param pin Pointer to a Pin instance describing one or more pins. + * + * \return 1 if the Pin instance contains at least one PIO that currently has + * a high level; otherwise 0. + */ +unsigned char PIO_Get( const Pin *pin ) +{ + unsigned int reg ; + + if ( (pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1) ) + { + reg = pin->pio->PIO_ODSR ; + } + else + { + reg = pin->pio->PIO_PDSR ; + } + + if ( (reg & pin->mask) == 0 ) + { + return 0 ; + } + else + { + return 1 ; + } +} + +/** + * \brief Returns 1 if one or more PIO of the given Pin are configured to output a + * high level (even if they are not output). + * To get the actual value of the pin, use PIO_Get() instead. + * + * \param pin Pointer to a Pin instance describing one or more pins. + * + * \return 1 if the Pin instance contains at least one PIO that is configured + * to output a high level; otherwise 0. + */ +unsigned char PIO_GetOutputDataStatus(const Pin *pin) +{ + if ((pin->pio->PIO_ODSR & pin->mask) == 0) + { + return 0; + } + else + { + return 1; + } +} + +/* + * \brief Configures Glitch or Debouncing filter for input. + * + * \param pin Pointer to a Pin instance describing one or more pins. + * \param cuttoff Cutt off frequency for debounce filter. + */ +void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff ) +{ + Pio *pio = pin->pio; + + if (cuttoff == 0) + { + pio->PIO_IFSCDR = pin->mask; + pio->PIO_SCDR = 0; + } + else + { + /* set Debouncing, 0 bit field no effect */ + pio->PIO_IFSCER = pin->mask; + /* the lowest 14 bits work */ + pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF; + } +} + +/* + * \brief Enable write protect. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ + + +void PIO_EnableWriteProtect( const Pin *pin ) +{ + Pio *pio = pin->pio; + + pio->PIO_WPMR = ( PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_EN ); +} + +/* + * \brief Disable write protect. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ + +void PIO_DisableWriteProtect( const Pin *pin ) +{ + Pio *pio = pin->pio; + + pio->PIO_WPMR = ( PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_DIS ); +} + +/* + * \brief Get write protect violation information. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ + +uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin ) +{ + Pio *pio = pin->pio; + return (pio->PIO_WPSR); +} + + + +/* + * \brief Configure all pio output low + * + * \param pin Pointer to a Pin instance describing one or more pins. + * \param pioId PIO ID + */ + +void PIO_Output_Low (Pio * pio, uint32_t pioId) +{ + PMC->PMC_PCER0 = 1 << pioId; + pio->PIO_PUDR = 0xFFFFFFFF; // all Pull-up Disable + pio->PIO_PPDDR = 0xFFFFFFFF; // all Pull-down Disable + pio->PIO_PER = 0xFFFFFFFF; // all PIO enable + pio->PIO_OER = 0xFFFFFFFF; // all PIO output mode + pio->PIO_CODR = 0xFFFFFFFF; // all PIO clear output +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pio_it.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pio_it.c new file mode 100644 index 000000000..b3c09ef90 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pio_it.c @@ -0,0 +1,292 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/* Maximum number of interrupt sources that can be defined. This + * constant can be increased, but the current value is the smallest possible + * that will be compatible with all existing projects. */ +#define MAX_INTERRUPT_SOURCES 7 + +/*---------------------------------------------------------------------------- + * Local types + *----------------------------------------------------------------------------*/ + +/** + * Describes a PIO interrupt source, including the PIO instance triggering the + * interrupt and the associated interrupt handler. + */ +typedef struct _InterruptSource +{ + /* Pointer to the source pin instance. */ + const Pin *pPin; + + /* Interrupt handler. */ + void (*handler)( const Pin* ) ; +} InterruptSource ; + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/* List of interrupt sources. */ +static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ; + +/* Number of currently defined interrupt sources. */ +static uint32_t _dwNumSources = 0; + +/*---------------------------------------------------------------------------- + * Local Functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Handles all interrupts on the given PIO controller. + * \param id PIO controller ID. + * \param pPio PIO controller base address. + */ +extern void PioInterruptHandler( uint32_t id, Pio *pPio ) +{ + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pPio->PIO_ISR; + status &= pPio->PIO_IMR; + + /* Check pending events */ + if ( status != 0 ) + { + TRACE_DEBUG( "PIO interrupt on PIO controller #%d\n\r", id ) ; + + /* Find triggering source */ + i = 0; + while ( status != 0 ) + { + /* There cannot be an unconfigured source enabled. */ + assert(i < _dwNumSources); + + /* Source is configured on the same controller */ + if (_aIntSources[i].pPin->id == id) + { + /* Source has PIOs whose statuses have changed */ + if ( (status & _aIntSources[i].pPin->mask) != 0 ) + { + TRACE_DEBUG( "Interrupt source #%d triggered\n\r", i ) ; + + _aIntSources[i].handler(_aIntSources[i].pPin); + status &= ~(_aIntSources[i].pPin->mask); + } + } + i++; + } + } +} + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ + +/** + * Generic PIO interrupt handler. Single entry point for interrupts coming + * from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to + * the user-configured handlers. + */ +void PIO_IT_InterruptHandler(void) +{ + PioInterruptHandler(ID_PIOA, PIOA); + PioInterruptHandler(ID_PIOB, PIOB); + PioInterruptHandler(ID_PIOC, PIOC); + PioInterruptHandler(ID_PIOD, PIOD); + PioInterruptHandler(ID_PIOE, PIOE); +} + +/** + * \brief Initializes the PIO interrupt management logic + * + * The desired priority of PIO interrupts must be provided. + * Calling this function multiple times result in the reset of currently + * configured interrupts. + * + * \param priority PIO controller interrupts priority. + */ +extern void PIO_InitializeInterrupts( uint32_t dwPriority ) +{ + TRACE_DEBUG( "PIO_Initialize()\n\r" ) ; + + /* Reset sources */ + _dwNumSources = 0 ; + + /* Configure PIO interrupt sources */ + TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ; + PMC_EnablePeripheral( ID_PIOA ) ; + PIOA->PIO_ISR ; + PIOA->PIO_IDR = 0xFFFFFFFF ; + IRQ_ConfigureIT(ID_PIOA, dwPriority, PIO_IT_InterruptHandler); + IRQ_EnableIT(ID_PIOA); + + /* Configure PIO interrupt sources */ + TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ; + PMC_EnablePeripheral( ID_PIOC ) ; + PIOC->PIO_ISR ; + PIOC->PIO_IDR = 0xFFFFFFFF ; + IRQ_ConfigureIT(ID_PIOC, dwPriority, PIO_IT_InterruptHandler); + IRQ_EnableIT(ID_PIOC); + + /* Configure PIO interrupt sources */ + TRACE_DEBUG( "PIO_Initialize: Configuring PIOD\n\r" ) ; + PMC_EnablePeripheral( ID_PIOD ) ; + PIOD->PIO_ISR ; + PIOD->PIO_IDR = 0xFFFFFFFF ; + IRQ_ConfigureIT(ID_PIOD, dwPriority, PIO_IT_InterruptHandler); + IRQ_EnableIT(ID_PIOD); + + /* Configure PIO interrupt sources */ + TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ; + PMC_EnablePeripheral( ID_PIOE ) ; + PIOE->PIO_ISR ; + PIOE->PIO_IDR = 0xFFFFFFFF ; + IRQ_ConfigureIT(ID_PIOE, dwPriority, PIO_IT_InterruptHandler); + IRQ_EnableIT(ID_PIOE); + +} + +/** + * Configures a PIO or a group of PIO to generate an interrupt on status + * change. The provided interrupt handler will be called with the triggering + * pin as its parameter (enabling different pin instances to share the same + * handler). + * \param pPin Pointer to a Pin instance. + * \param handler Interrupt handler function pointer. + */ +extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) +{ + Pio* pio ; + InterruptSource* pSource ; + + TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ; + + assert( pPin ) ; + pio = pPin->pio ; + assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ; + + /* Define new source */ + TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%d.\n\r", _dwNumSources ) ; + + pSource = &(_aIntSources[_dwNumSources]) ; + pSource->pPin = pPin ; + pSource->handler = handler ; + _dwNumSources++ ; + + /* PIO3 with additional interrupt support + * Configure additional interrupt mode registers */ + if ( pPin->attribute & PIO_IT_AIME ) + { + // enable additional interrupt mode + pio->PIO_AIMER = pPin->mask ; + + // if bit field of selected pin is 1, set as Rising Edge/High level detection event + if ( pPin->attribute & PIO_IT_RE_OR_HL ) + { + pio->PIO_REHLSR = pPin->mask ; + } + else + { + pio->PIO_FELLSR = pPin->mask; + } + + /* if bit field of selected pin is 1, set as edge detection source */ + if (pPin->attribute & PIO_IT_EDGE) + pio->PIO_ESR = pPin->mask; + else + pio->PIO_LSR = pPin->mask; + } + else + { + /* disable additional interrupt mode */ + pio->PIO_AIMDR = pPin->mask; + } +} + +/** + * Enables the given interrupt source if it has been configured. The status + * register of the corresponding PIO controller is cleared prior to enabling + * the interrupt. + * \param pPin Interrupt source to enable. + */ +extern void PIO_EnableIt( const Pin *pPin ) +{ + TRACE_DEBUG( "PIO_EnableIt()\n\r" ) ; + + assert( pPin != NULL ) ; + +#ifndef NOASSERT + uint32_t i = 0; + uint32_t dwFound = 0; + + while ( (i < _dwNumSources) && !dwFound ) + { + if ( _aIntSources[i].pPin == pPin ) + { + dwFound = 1 ; + } + i++ ; + } + assert( dwFound != 0 ) ; +#endif + + pPin->pio->PIO_ISR; + pPin->pio->PIO_IER = pPin->mask ; +} + +/** + * Disables a given interrupt source, with no added side effects. + * + * \param pPin Interrupt source to disable. + */ +extern void PIO_DisableIt( const Pin *pPin ) +{ + assert( pPin != NULL ) ; + + TRACE_DEBUG( "PIO_DisableIt()\n\r" ) ; + + pPin->pio->PIO_IDR = pPin->mask; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pit.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pit.c new file mode 100644 index 000000000..51a1be421 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pit.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \addtogroup pit_module Working with PIT + * The PIT driver provides the Interface for configuration the Periodic + * Interval Timer (PIT) peripheral. + * + *
    + *
  • Initialize the PIT with the desired period using PIT_Init(). + * Alternatively, the Periodic Interval Value (PIV) can be configured + * manually using PIT_SetPIV().
    • + *
  • Start the PIT counting using PIT_Enable(). + *
  • Enable & disable the PIT interrupt using PIT_EnableIT() and + * PIT_DisableIT().
    • + *
  • Retrieve the current status of the PIT using PIT_GetStatus().
    • + *
  • To get the current value of the internal counter and the number of ticks + * that have occurred, use either PIT_GetPIVR() or PIT_GetPIIR() depending + * on whether you want the values to be cleared or not.
    • + * + *
+ * For more accurate information, please look at the PIT section of the + * Datasheet. + * + * Related files :\n + * \ref pit.c\n + * \ref pit.h.\n +*/ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of PIT (Periodic Interval Timer) controller. + * + */ +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ +#include "chip.h" + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + + /** + * \brief Initialize the Periodic Interval Timer to generate a tick at the + * specified period, given the current master clock frequency. + * + * \param uperiod Period in uSecond. + * \param pit_frequency Master clock frequency in MHz. + */ + +void PIT_Init(uint32_t period, uint32_t pit_frequency) +{ + PIT->PIT_MR = period? (period * pit_frequency + 8) >> 4 : 0; + PIT->PIT_MR |= PIT_MR_PITEN; +} + +/** + * \brief Set the Periodic Interval Value of the PIT. + * + * \param piv PIV value to set. + */ +void PIT_SetPIV(uint32_t piv) +{ + uint32_t dwMr = PIT->PIT_MR & (~PIT_MR_PIV_Msk); + PIT->PIT_MR = dwMr | PIT_MR_PIV(piv); +} + +/** + * \brief Enables the PIT if this is not already the case. + * + */ +void PIT_Enable(void) +{ + PIT->PIT_MR |= PIT_MR_PITEN; +} + +/** + * \brief Disnables the PIT when PIV value is reached. + * + */ +void PIT_Disable(void) +{ + PIT->PIT_MR &= ~PIT_MR_PITEN; +} + +/** + * \brief Enable the PIT periodic interrupt. + * + */ +void PIT_EnableIT(void) +{ + PIT->PIT_MR |= PIT_MR_PITIEN; +} + +/** + * \brief Disables the PIT periodic interrupt. + * + */ +void PIT_DisableIT(void) +{ + PIT->PIT_MR &= ~PIT_MR_PITIEN; +} + +/** + * \brief Returns the value of the PIT mode register. + * + * \return PIT_MR value. + */ +uint32_t PIT_GetMode(void) +{ + return PIT->PIT_MR; +} + +/** + * \brief Returns the value of the PIT status register, clearing it as a side effect. + * + * \return PIT_SR value. + */ +uint32_t PIT_GetStatus(void) +{ + return PIT->PIT_SR; +} + +/** + * \brief Returns the value of the PIT Image Register, to read PICNT and CPIV without + * clearing the current values. + * + * \return PIT_PIIR value. + */ +uint32_t PIT_GetPIIR(void) +{ + return PIT->PIT_PIIR; +} + +/** + * \brief Returns the value of the PIT Value Register, clearing it as a side effect. + * + * \return PITC_PIVR value. + */ +uint32_t PIT_GetPIVR(void) +{ + return PIT->PIT_PIVR; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pmc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pmc.c new file mode 100644 index 000000000..48347c2dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pmc.c @@ -0,0 +1,428 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define MAX_PERI_ID ID_MPDDRC + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ +/** Array of Max peripheral Frequence support for SAMA5 chip*/ +static const PeripheralClockMaxFreq periClkMaxFreq[] = { + /* peripheral ID, Max frequency */ + {ID_FIQ , 133000000 }, + {ID_SYS , 133000000 }, + {ID_DBGU , 66000000 }, + {ID_PIT , 133000000 }, + {ID_WDT , 133000000 }, + {ID_SMC , 133000000 }, + {ID_PIOA , 133000000 }, + {ID_PIOB , 133000000 }, + {ID_PIOC , 133000000 }, + {ID_PIOD , 133000000 }, + {ID_PIOE , 133000000 }, + {ID_SMD , 24000000 }, + {ID_USART0 , 66000000 }, + {ID_USART1 , 66000000 }, + {ID_USART2 , 66000000 }, + {ID_USART3 , 66000000 }, + {ID_UART0 , 66000000 }, + {ID_UART1 , 66000000 }, + {ID_TWI0 , 33000000 }, + {ID_TWI1 , 33000000 }, + {ID_TWI2 , 33000000 }, + {ID_HSMCI0 , 133000000 }, + {ID_HSMCI1 , 133000000 }, + {ID_HSMCI2 , 133000000 }, + {ID_SPI0 , 133000000 }, + {ID_SPI1 , 133000000 }, + {ID_TC0 , 66000000 }, + {ID_TC1 , 66000000 }, + {ID_PWM , 133000000 }, + {ID_ADC , 66000000 }, + {ID_DMAC0 , 133000000 }, + {ID_DMAC1 , 133000000 }, + {ID_UHPHS , 133000000 }, + {ID_UDPHS , 133000000 }, + {ID_GMAC , 133000000 }, + {ID_EMAC , 133000000 }, + {ID_LCDC , 133000000 }, + {ID_ISI , 133000000 }, + {ID_SSC0 , 66000000 }, + {ID_SSC1 , 66000000 }, + {ID_CAN0 , 66000000 }, + {ID_CAN1 , 66000000 }, + {ID_SHA , 133000000 }, + {ID_AES , 133000000 }, + {ID_TDES , 133000000 }, + {ID_TRNG , 133000000 }, + {ID_ARM , 133000000 }, + {ID_IRQ , 133000000 }, + {ID_FUSE , 133000000 }, + {ID_MPDDRC , 133000000 } +}; +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Get maxinum frequency clock for giving pripheral ID. + * + * \param id Peripheral ID (ID_xxx). + */ +extern uint32_t PMC_GetPeriMaxFreq( uint32_t dwId ) +{ + uint8_t i; + for (i = 0; i < MAX_PERI_ID; i++) { + if ( dwId == periClkMaxFreq[i].bPeriphID) return periClkMaxFreq[i].bMaxFrequency; + } + return 0; +} + +/** + * \brief Set maxinum frequency clock for giving pripheral ID. + * + * \param id Peripheral ID (ID_xxx). + * \param mck Master clock. + * \return Peripheral clock. + */ +extern uint32_t PMC_SetPeriMaxClock( uint32_t dwId, uint32_t mck) +{ + uint32_t maxClock; + uint8_t i; + /* Disable peripher clock */ + PMC->PMC_PCR = PMC_PCR_PID(dwId) | PMC_PCR_CMD; + maxClock = PMC_GetPeriMaxFreq(dwId); + for ( i = 0; i < 4; i++) { + if ( mck / (1 << i ) <= maxClock) break; + } + PMC->PMC_PCR = PMC_PCR_PID(dwId) | PMC_PCR_CMD | (i << PMC_PCR_DIV_Pos) | PMC_PCR_EN; + return maxClock; +} + +/** + * \brief Enables the clock of a peripheral. The peripheral ID is used + * to identify which peripheral is targetted. + * + * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). + * + * \param id Peripheral ID (ID_xxx). + */ +extern void PMC_EnablePeripheral( uint32_t dwId ) +{ + if (dwId < 32) + { + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) ) + { + // TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", dwId ) ; + } + else + { + PMC->PMC_PCER0 = (1 << dwId) ; + } + } else { + if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << ( dwId - 32))) == ((uint32_t)1 << (dwId - 32)) ) + { + // TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", dwId ) ; + } + else + { + PMC->PMC_PCER1 = 1 << (dwId - 32) ; + } + } +} + +/** + * \brief Disables the clock of a peripheral. The peripheral ID is used + * to identify which peripheral is targetted. + * + * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). + * + * \param id Peripheral ID (ID_xxx). + */ +extern void PMC_DisablePeripheral( uint32_t dwId ) +{ + if (dwId < 32) + { + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) + { + TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", (unsigned int)dwId ) ; + } + else + { + PMC->PMC_PCDR0 = 1 << dwId ; + } + } else { + if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << (dwId - 32))) != ((uint32_t)1 << (dwId - 32)) ) + { + TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", (unsigned int)dwId ) ; + } + else + { + PMC->PMC_PCDR1 = 1 << (dwId - 32) ; + } + } +} + +/** + * \brief Enable all the periph clock via PMC. + */ +extern void PMC_EnableAllPeripherals( void ) +{ + PMC->PMC_PCER0 = 0xFFFFFFFF ; + PMC->PMC_PCER1 = 0xFFFFFFFF ; + TRACE_DEBUG( "Enable all periph clocks\n\r" ) ; +} + +/** + * \brief Disable all the periph clock via PMC. + */ +extern void PMC_DisableAllPeripherals( void ) +{ + TRACE_DEBUG( "Disable all periph clocks\n\r" ) ; + PMC->PMC_PCDR0 = 0xFFFFFFFF ; + PMC->PMC_PCDR1 = 0xFFFFFFFF ; +} + +/** + * \brief Get Periph Status for the given peripheral ID. + * + * \param id Peripheral ID (ID_xxx). + */ +extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) +{ + if (dwId < 32) { + return ( PMC->PMC_PCSR0 & (1 << dwId) ) ; + } else { + return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ; + } +} + +/** + * \brief Select external 32K crystal. + */ +extern void PMC_SelectExt32KCrystal(void) +{ + volatile uint32_t count; + /* Switch from internal RC 32kHz to external OSC 32 kHz */ + /* before switch slow clock source, switch MCK to Main Clock*/ + //PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + //while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + /* enable external OSC 32 kHz */ + SCKC->SCKC_CR |= SCKC_CR_OSC32EN; + /* Wait 32,768 Hz Startup Time for clock stabilization (software loop) */ + for (count = 0; count < 0x1000; count++); + /* disable OSC 32 kHz bypass */ + SCKC->SCKC_CR &= ~SCKC_CR_OSC32BYP; + /* switch slow clock source to external OSC 32 kHz */ + SCKC->SCKC_CR = (SCKC->SCKC_CR & ~SCKC_CR_OSCSEL) | SCKC_CR_OSCSEL_XTAL; + /* Wait 5 slow clock cycles for internal resynchronization*/ + for (count = 0; count < 0x1000; count++); + /* wait slow clock status change for external OSC 32 kHz selection */ + // while(!(PMC->PMC_SR & PMC_SR_OSCSELS)); + /* disable internal RC 32 kHz */ + SCKC->SCKC_CR &= ~SCKC_CR_RCEN; +} + +/** + * \brief Select internal 32K crystal. + */ +extern void PMC_SelectInt32kCrystal(void) +{ + /* switch from external RC 32kHz to internal OSC 32 kHz */ + volatile uint32_t count; + /* before switch slow clock source, switch MCK to Main Clock */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + /* enable internal RC 32 kHz */ + SCKC->SCKC_CR |= SCKC_CR_RCEN; + /* Wait 32,768 Hz Startup Time for clock stabilization (software loop)*/ + for (count = 0; count < 0x1000; count++); + /* switch slow clock source to internal OSC 32 kHz */ + SCKC->SCKC_CR = (SCKC->SCKC_CR & ~SCKC_CR_OSCSEL) | SCKC_CR_OSCSEL_RC; + /* Wait 5 slow clock cycles for internal resynchronization */ + for (count = 0; count < 0x1000; count++); + /* wait slow clock status change for internal RC 32 kHz selection */ + // while(PMC->PMC_SR & PMC_SR_OSCSELS); + /* disable external OSC 32 kHz */ + SCKC->SCKC_CR &= ~SCKC_CR_OSC32EN; +} + +/** + * \brief Select external 12M OSC. + */ +extern void PMC_SelectExt12M_Osc(void) +{ + /* switch from internal RC 12 MHz to external OSC 12 MHz */ + /* wait Main XTAL Oscillator stabilisation*/ + if ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) == CKGR_MOR_MOSCSEL) return; + /* enable external OSC 12 MHz */ + PMC->CKGR_MOR |= CKGR_MOR_MOSCXTEN | CKGR_MOR_KEY(0x37); + /* wait Main CLK Ready */ + while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY)); + /* disable external OSC 12 MHz bypass */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | CKGR_MOR_KEY(0x37); + /* switch MAIN clock to external OSC 12 MHz*/ + PMC->CKGR_MOR |= CKGR_MOR_MOSCSEL | CKGR_MOR_KEY(0x37); + /* wait MAIN clock status change for external OSC 12 MHz selection*/ + while(!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + /* in case where MCK is running on MAIN CLK */ + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + /* disable internal RC 12 MHz*/ + //PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY(0x37); +} + +/** + * \brief Select internal 12M OSC. + */ +extern void PMC_SelectInt12M_Osc(void) +{ + uint32_t count; + /* switch from external OSC 12 MHz to internal RC 12 MHz*/ + /* enable internal RC 12 MHz */ + PMC->CKGR_MOR |= CKGR_MOR_MOSCRCEN | CKGR_MOR_KEY(0x37); + /* Wait internal 12 MHz RC Startup Time for clock stabilization (software loop) */ + for (count = 0; count < 0x100000; count++); + /* switch MAIN clock to internal RC 12 MHz */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_KEY(0x37); + /* wait MAIN clock status change for internal RC 12 MHz selection*/ + while(PMC->PMC_SR & PMC_SR_MOSCSELS); + /* in case where MCK is running on MAIN CLK */ + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + /* disable external OSC 12 MHz */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | CKGR_MOR_KEY(0x37); +} + +/** + * \brief Switch PMC from MCK to PLL clock. + */ +extern void PMC_SwitchMck2Pll(void) +{ + /* Select PLL as input clock for PCK and MCK */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_PLLA_CLK ; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + + +/** + * \brief Switch PMC from MCK to main clock. + */ +extern void PMC_SwitchMck2Main(void) +{ + /* Select Main Oscillator as input clock for PCK and MCK */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_PCK_CSS_MAIN_CLK ; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + + +/** + * \brief Switch PMC from MCK to slow clock. + */ +extern void PMC_SwitchMck2Slck(void) +{ + /* Select Slow Clock as input clock for PCK and MCK */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_PCK_CSS_SLOW_CLK ; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + + +/** + * \brief Configure MCK Prescaler. + * \param prescaler prescaler value. + */ +extern void PMC_SetMckPrescaler(uint32_t prescaler) +{ + /* Change MCK Prescaler divider in PMC_MCKR register */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk) | prescaler; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Configure MCK PLLA divider. + * \param divider PLL divider value. + */ +extern void PMC_SetMckPllaDiv(uint32_t divider) +{ + if ((PMC->PMC_MCKR & PMC_MCKR_PLLADIV2_DIV2) == PMC_MCKR_PLLADIV2_DIV2) + { + if(divider == PMC_MCKR_PLLADIV2_NOT_DIV2) { + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PLLADIV2_DIV2); + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); + } + } else { + if(divider == PMC_MCKR_PLLADIV2_DIV2) { + PMC->PMC_MCKR = (PMC->PMC_MCKR | PMC_MCKR_PLLADIV2_DIV2); + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); + } + } +} + +/** + * \brief Configure MCK Divider. + * \param divider divider value. + */ +extern void PMC_SetMckDivider(uint32_t divider) +{ + /* change MCK Prescaler divider in PMC_MCKR register */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk) | divider; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Configure PLL Register. + * \param pll pll value. + * \param cpcr cpcr value. + */ +extern void PMC_SetPllA(uint32_t pll, uint32_t cpcr) +{ + PMC->CKGR_PLLAR = pll; + PMC->PMC_PLLICPR = cpcr; + while( !(PMC->PMC_SR & PMC_SR_LOCKA) ); +} + +/** + * \brief Disable PLLA Register. + */ +extern void PMC_DisablePllA(void) +{ + PMC->CKGR_PLLAR = (PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk) | CKGR_PLLAR_MULA(0); +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pwmc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pwmc.c new file mode 100644 index 000000000..7b253494b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/pwmc.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup pwm_module Working with PWM + * The PWM driver provides the interface to configure and use the PWM + * peripheral. + * + * The PWM macrocell controls square output waveforms of 4 channels. + * Characteristics of output waveforms such as period, duty-cycle can be configured.\n + * + * Before enabling the channels, they must have been configured first. + * The main settings include: + *
    + *
  • Configuration of the clock generator.
    • + *
  • Selection of the clock for each channel.
    • + *
  • Configuration of output waveform characteristics, such as period, duty-cycle etc.
    • + *
+ * + * After the channels is enabled, the user must use respective update registers + * to change the wave characteristics to prevent unexpected output waveform. + * i.e. PWM_CUPDx register should be used if user want to change duty-cycle + * when the channel is enabled. + * + * For more accurate information, please look at the PWM section of the + * Datasheet. + * + * Related files :\n + * \ref pwmc.c\n + * \ref pwmc.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of the Pulse Width Modulation Controller (PWM) peripheral. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures PWM clocks + */ +void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t mode) +{ + pPwm->PWM_CLK= mode; +} + +/** + * \brief Enables the given PWM channel. + * + * This does NOT enable the corresponding pin;this must be done in the user code. + * + * \param channel Channel number. + */ +void PWMC_EnableChannel(Pwm* pPwm,uint8_t channel) +{ + pPwm->PWM_ENA= 0x1ul<PWM_SR & (1 << channel)) != 0); + * + * \param channel Channel number. + */ +void PWMC_DisableChannel(Pwm* pPwm,uint8_t channel) +{ + pPwm->PWM_DIS= 0x1ul<PWM_IER1= 0x1ul<PWM_IDR1 = 0x1ul<PWM_CH_NUM[channel].PWM_CMR= mode; +} + +/** + * \brief Sets the period value used by a PWM channel. + * + * This function writes directly to the CPRD register if the channel is disabled; + * otherwise, it uses the update register CPRDUPD. + * + * \param channel Channel number. + * \param period Period value. + */ +void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period) +{ + /* If channel is disabled, write to CPRD */ + if ((pPwm->PWM_SR & (1 << channel)) == 0) { + pPwm->PWM_CH_NUM[channel].PWM_CPRD = period; + } + /* Otherwise use update register */ + else { + pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period; + } +} + +/** + * \brief Sets the duty cycle used by a PWM channel. + * This function writes directly to the CDTY register if the channel is disabled; + * otherwise it uses the update register CDTYUPD. + * Note that the duty cycle must always be inferior or equal to the channel + * period. + * + * \param channel Channel number. + * \param duty Duty cycle value. + */ +void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty) +{ + assert(duty <= pPwm->PWM_CH_NUM[channel].PWM_CPRD); + + /* If channel is disabled, write to CDTY */ + if ((pPwm->PWM_SR & (1 << channel)) == 0) { + pPwm->PWM_CH_NUM[channel].PWM_CDTY = duty; + } + /* Otherwise use update register */ + else { + pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = duty; + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/rstc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/rstc.c new file mode 100644 index 000000000..af5c3fe7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/rstc.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Defines + *---------------------------------------------------------------------------*/ + +/** Keywords to write to the reset registers */ +#define RSTC_KEY_PASSWORD RSTC_MR_KEY(0xA5U) + +#define RSTC_MR_URSTEN (1ul ) +#define RSTC_MR_URSTIEN (1ul << 4) + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * Configure the mode of the RSTC peripheral. + * The configuration is computed by the lib (RSTC_RMR_*). + * \param mr Desired mode configuration. + */ +void RSTC_ConfigureMode(uint32_t mr) +{ + Rstc *pHw = RSTC; + mr &= ~RSTC_MR_KEY_Msk; + pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD; +} + +/** + * Enable/Disable the detection of a low level on the pin NRST as User Reset + * \param enable 1 to enable & 0 to disable. + */ +void RSTC_SetUserResetEnable(uint8_t enable) +{ + Rstc *pHw = RSTC; + uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk); + if (enable) + { + mr |= RSTC_MR_URSTEN; + } + else + { + mr &= ~RSTC_MR_URSTEN; + } + pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD; +} + +/** + * Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST). + * \param enable 1 to enable & 0 to disable. + */ +void RSTC_SetUserResetInterruptEnable(uint8_t enable) +{ + Rstc *pHw = RSTC; + uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk); + if (enable) + { + mr |= RSTC_MR_URSTIEN; + } + else { + + mr &= ~RSTC_MR_URSTIEN; + } + pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD; +} + +/** + * Setup the external reset length. The length is asserted during a time of + * pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s. + * \param powl Power length defined. + */ +void RSTC_SetExtResetLength(uint8_t powl) +{ + Rstc *pHw = RSTC; + uint32_t mr = pHw->RSTC_MR; + mr &= ~(RSTC_MR_KEY_Msk | RSTC_MR_ERSTL_Msk); + mr |= RSTC_MR_ERSTL(powl); + pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD; +} + + +/** + * Resets the processor. + */ +void RSTC_ProcessorReset(void) +{ + Rstc *pHw = RSTC; + pHw->RSTC_CR = RSTC_CR_PROCRST | RSTC_KEY_PASSWORD; +} + +/** + * Resets the peripherals. + */ +void RSTC_PeripheralReset(void) +{ + Rstc *pHw = RSTC; + pHw->RSTC_CR = RSTC_CR_PERRST | RSTC_KEY_PASSWORD; +} + +/** + * Asserts the NRST pin for external resets. + */ +void RSTC_ExtReset(void) +{ + Rstc *pHw = RSTC; + pHw->RSTC_CR = RSTC_CR_EXTRST | RSTC_KEY_PASSWORD; +} + +/** + * Return NRST pin level ( 1 or 0 ). + */ +uint8_t RSTC_GetNrstLevel(void) +{ + Rstc *pHw = RSTC; + return ((pHw->RSTC_SR & RSTC_SR_NRSTL) > 0); +} + +/** + * Returns 1 if at least one high-to-low transition of NRST (User Reset) has + * been detected since the last read of RSTC_RSR. + */ +uint8_t RSTC_IsUserResetDetected(void) +{ + Rstc *pHw = RSTC; + if (pHw->RSTC_SR & RSTC_SR_URSTS) + { + return 1; + } + return 0; +} + +/** + * Return 1 if a software reset command is being performed by the reset + * controller. The reset controller is busy. + */ +uint8_t RSTC_IsBusy(void) +{ + Rstc *pHw = RSTC; + if (pHw->RSTC_SR & RSTC_SR_SRCMP) + { + return 1; + } + return 0; +} + +/** + * Get the status + */ +uint32_t RSTC_GetStatus(void) +{ + Rstc *pHw = RSTC; + return (pHw->RSTC_SR); +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/rtc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/rtc.c new file mode 100644 index 000000000..7348001a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/rtc.c @@ -0,0 +1,464 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup rtc_module Working with RTC + * The RTC driver provides the interface to configure and use the RTC + * peripheral. + * + * It manages date, time, and alarms.\n + * This timer is clocked by the 32kHz system clock, and is not impacted by + * power management settings (PMC). To be accurate, it is better to use an + * external 32kHz crystal instead of the internal 32kHz RC.\n + * + * It uses BCD format, and time can be set in AM/PM or 24h mode through a + * configuration bit in the mode register.\n + * + * To update date or time, the user has to follow these few steps : + *
    + *
  • Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
    • + *
  • Polling or IRQ on the ACKUPD bit of RTC_CR,
    • + *
  • Clear ACKUPD bit in RTC_SCCR,
    • + *
  • Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
    • + *
  • Clear UPDTIM and/or UPDCAL bit in RTC_CR.
    • + *
+ * An alarm can be set to happen on month, date, hours, minutes or seconds, + * by setting the proper "Enable" bit of each of these fields in the Time and + * Calendar registers. + * This allows a large number of configurations to be available for the user. + * Alarm occurence can be detected even by polling or interrupt. + * + * A check of the validity of the date and time format and values written by the user is automatically done. + * Errors are reported through the Valid Entry Register. + * + * For more accurate information, please look at the RTC section of the + * Datasheet. + * + * Related files :\n + * \ref rtc.c\n + * \ref rtc.h.\n +*/ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Real Time Clock (RTC) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Sets the RTC in either 12 or 24 hour mode. + * + * \param mode Hour mode. + */ +extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) +{ + assert((dwMode & 0xFFFFFFFE) == 0); + + pRtc->RTC_MR = dwMode ; +} + +/** + * \brief Gets the RTC mode. + * + * \return Hour mode. + */ +extern uint32_t RTC_GetHourMode( Rtc* pRtc ) +{ + uint32_t dwMode ; + + TRACE_DEBUG( "RTC_SetHourMode()\n\r" ) ; + + dwMode = pRtc->RTC_MR; + dwMode &= 0xFFFFFFFE; + + return dwMode ; +} + +/** + * \brief Enables the selected interrupt sources of the RTC. + * + * \param sources Interrupt sources to enable. + */ +extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) +{ + assert((dwSources & (uint32_t)(~0x1F)) == 0); + + TRACE_DEBUG( "RTC_EnableIt()\n\r" ) ; + + pRtc->RTC_IER = dwSources ; +} + +/** +* \brief Disables the selected interrupt sources of the RTC. +* +* \param sources Interrupt sources to disable. +*/ +extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) +{ + assert((dwSources & (uint32_t)(~0x1F)) == 0); + + TRACE_DEBUG( "RTC_DisableIt()\n\r" ) ; + + pRtc->RTC_IDR = dwSources ; +} + +/** + * \brief Sets the current time in the RTC. + * + * \note In successive update operations, the user must wait at least one second + * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these + * bits again. Please look at the RTC section of the datasheet for detail. + * + * \param ucHour Current hour in 12 or 24 hour mode. + * \param ucMinute Current minute. + * \param ucSecond Current second. + * + * \return 0 sucess, 1 fail to set + */ +extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) +{ + uint32_t dwTime=0 ; + uint8_t ucHour_bcd ; + uint8_t ucMin_bcd ; + uint8_t ucSec_bcd ; + + TRACE_DEBUG( "RTC_SetTime(%02d:%02d:%02d)\n\r", ucHour, ucMinute, ucSecond ) ; + + /* if 12-hour mode, set AMPM bit */ + if ( (pRtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD ) + { + if ( ucHour > 12 ) + { + ucHour -= 12 ; + dwTime |= RTC_TIMR_AMPM ; + } + } + ucHour_bcd = (ucHour%10) | ((ucHour/10)<<4) ; + ucMin_bcd = (ucMinute%10) | ((ucMinute/10)<<4) ; + ucSec_bcd = (ucSecond%10) | ((ucSecond/10)<<4) ; + + /* value overflow */ + if ( (ucHour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) | + (ucMin_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) | + (ucSec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK))) + { + return 1 ; + } + + dwTime = ucSec_bcd | (ucMin_bcd << 8) | (ucHour_bcd<<16) ; + + pRtc->RTC_CR |= RTC_CR_UPDTIM ; + while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ; + pRtc->RTC_SCCR = RTC_SCCR_ACKCLR ; + pRtc->RTC_TIMR = dwTime ; + pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ; + pRtc->RTC_SCCR |= RTC_SCCR_SECCLR ; + + return (int)(pRtc->RTC_VER & RTC_VER_NVTIM) ; +} + +/** + * \brief Retrieves the current time as stored in the RTC in several variables. + * + * \param pucHour If not null, current hour is stored in this variable. + * \param pucMinute If not null, current minute is stored in this variable. + * \param pucSecond If not null, current second is stored in this variable. + */ +extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) +{ + uint32_t dwTime ; + + TRACE_DEBUG( "RTC_GetTime()\n\r" ) ; + + /* Get current RTC time */ + dwTime = pRtc->RTC_TIMR ; + while ( dwTime != pRtc->RTC_TIMR ) + { + dwTime = pRtc->RTC_TIMR ; + } + + /* Hour */ + if ( pucHour ) + { + *pucHour = ((dwTime & 0x00300000) >> 20) * 10 + + ((dwTime & 0x000F0000) >> 16); + + if ( (dwTime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM ) + { + *pucHour += 12 ; + } + } + + /* Minute */ + if ( pucMinute ) + { + *pucMinute = ((dwTime & 0x00007000) >> 12) * 10 + + ((dwTime & 0x00000F00) >> 8); + } + + /* Second */ + if ( pucSecond ) + { + *pucSecond = ((dwTime & 0x00000070) >> 4) * 10 + + (dwTime & 0x0000000F); + } +} + +/** + * \brief Sets a time alarm on the RTC. + * The match is performed only on the provided variables; + * Setting all pointers to 0 disables the time alarm. + * + * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for + * AM (as expected in the time registers). + * + * \param pucHour If not null, the time alarm will hour-match this value. + * \param pucMinute If not null, the time alarm will minute-match this value. + * \param pucSecond If not null, the time alarm will second-match this value. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) +{ + uint32_t dwAlarm=0 ; + + TRACE_DEBUG( "RTC_SetTimeAlarm()\n\r" ) ; + + /* Hour */ + if ( pucHour ) + { + dwAlarm |= RTC_TIMALR_HOUREN | ((*pucHour / 10) << 20) | ((*pucHour % 10) << 16); + } + + /* Minute */ + if ( pucMinute ) + { + dwAlarm |= RTC_TIMALR_MINEN | ((*pucMinute / 10) << 12) | ((*pucMinute % 10) << 8); + } + + /* Second */ + if ( pucSecond ) + { + dwAlarm |= RTC_TIMALR_SECEN | ((*pucSecond / 10) << 4) | (*pucSecond % 10); + } + + pRtc->RTC_TIMALR = dwAlarm ; + + return (int)(pRtc->RTC_VER & RTC_VER_NVTIMALR) ; +} + +/** + * \brief Retrieves the current year, month and day from the RTC. + * Month, day and week values are numbered starting at 1. + * + * \param pYwear Current year (optional). + * \param pucMonth Current month (optional). + * \param pucDay Current day (optional). + * \param pucWeek Current day in current week (optional). + */ +extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek ) +{ + uint32_t dwDate ; + + /* Get current date (multiple reads are necessary to insure a stable value) */ + do + { + dwDate = pRtc->RTC_CALR ; + } + while ( dwDate != pRtc->RTC_CALR ) ; + + /* Retrieve year */ + if ( pwYear ) + { + *pwYear = (((dwDate >> 4) & 0x7) * 1000) + + ((dwDate & 0xF) * 100) + + (((dwDate >> 12) & 0xF) * 10) + + ((dwDate >> 8) & 0xF); + } + + /* Retrieve month */ + if ( pucMonth ) + { + *pucMonth = (((dwDate >> 20) & 1) * 10) + ((dwDate >> 16) & 0xF); + } + + /* Retrieve day */ + if ( pucDay ) + { + *pucDay = (((dwDate >> 28) & 0x3) * 10) + ((dwDate >> 24) & 0xF); + } + + /* Retrieve week */ + if ( pucWeek ) + { + *pucWeek = ((dwDate >> 21) & 0x7); + } +} + +/** + * \brief Sets the current year, month and day in the RTC. + * Month, day and week values must be numbered starting from 1. + * + * \note In successive update operations, the user must wait at least one second + * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these + * bits again. Please look at the RTC section of the datasheet for detail. + * + * \param wYear Current year. + * \param ucMonth Current month. + * \param ucDay Current day. + * \param ucWeek Day number in current week. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek ) +{ + uint32_t wDate ; + uint8_t ucCent_bcd ; + uint8_t ucYear_bcd ; + uint8_t ucMonth_bcd ; + uint8_t ucDay_bcd ; + uint8_t ucWeek_bcd ; + + ucCent_bcd = ((wYear/100)%10) | ((wYear/1000)<<4); + ucYear_bcd = (wYear%10) | (((wYear/10)%10)<<4); + ucMonth_bcd = ((ucMonth%10) | (ucMonth/10)<<4); + ucDay_bcd = ((ucDay%10) | (ucDay/10)<<4); + ucWeek_bcd = ((ucWeek%10) | (ucWeek/10)<<4); + + /* value over flow */ + if ( (ucCent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) | + (ucYear_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) | + (ucMonth_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) | + (ucWeek_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) | + (ucDay_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK)) + ) + { + return 1 ; + } + + + /* Convert values to date register value */ + wDate = ucCent_bcd | + (ucYear_bcd << 8) | + (ucMonth_bcd << 16) | + (ucWeek_bcd << 21) | + (ucDay_bcd << 24); + + /* Update calendar register */ + pRtc->RTC_CR |= RTC_CR_UPDCAL ; + while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ; + + pRtc->RTC_SCCR = RTC_SCCR_ACKCLR; + pRtc->RTC_CALR = wDate ; + pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ; + pRtc->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */ + + return (int)(pRtc->RTC_VER & RTC_VER_NVCAL) ; +} + +/** + * \brief Sets a date alarm in the RTC. + * The alarm will match only the provided values; + * Passing a null-pointer disables the corresponding field match. + * + * \param pucMonth If not null, the RTC alarm will month-match this value. + * \param pucDay If not null, the RTC alarm will day-match this value. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) +{ + uint32_t dwAlarm ; + + dwAlarm = ((pucMonth) || (pucDay)) ? (0) : (0x01010000); + + TRACE_DEBUG( "RTC_SetDateAlarm()\n\r" ) ; + + /* Compute alarm field value */ + if ( pucMonth ) + { + dwAlarm |= RTC_CALALR_MTHEN | ((*pucMonth / 10) << 20) | ((*pucMonth % 10) << 16); + } + + if ( pucDay ) + { + dwAlarm |= RTC_CALALR_DATEEN | ((*pucDay / 10) << 28) | ((*pucDay % 10) << 24); + } + + /* Set alarm */ + pRtc->RTC_CALALR = dwAlarm ; + + return (int)(pRtc->RTC_VER & RTC_VER_NVCALALR) ; +} + +/** + * \brief Clear flag bits of status clear command register in the RTC. + * + * \param mask Bits mask of cleared events + */ +extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) +{ + /* Clear all flag bits in status clear command register */ + dwMask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR ; + + pRtc->RTC_SCCR = dwMask ; +} + +/** + * \brief Get flag bits of status register in the RTC. + * + * \param mask Bits mask of Status Register + * + * \return Status register & mask + */ +extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) +{ + uint32_t dwEvent ; + + dwEvent = pRtc->RTC_SR ; + + return (dwEvent & dwMask) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/sha.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/sha.c new file mode 100644 index 000000000..5691ea800 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/sha.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup sha_module Working with SHA + * \ingroup peripherals_module + * The SHA driver provides the interface to configure and use the SHA peripheral. + * \n + * + * The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2 + * specification. The first block of the message must be indicated to the module by a specific + * command. The SHA module produces a N-bit message digest each time a block is written and + * processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256, 384 for SHA384, + * 512 for SHA512. + * + * To Enable a SHA encryption and decrypt,the user has to follow these few steps: + *
    + *
  • Configure SHA algorithm mode, key mode, start mode and operation mode by SHA_Configure().
    • + *
  • Set SHA_FirstBlock() to indicates that the next block to process is the first one of a message.
    • + *
  • Input data for encryption by SHA_SetInput().
    • + *
  • To start the encryption process with SHA_Start()
    • + *
  • To get the encryption reslut by SHA_GetOutput()
    • + *
+ * + * For more accurate information, please look at the SHA section of the + * Datasheet. + * + * Related files :\n + * \ref sha.c\n + * \ref sha.h\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Secure Hash Algorithm (SHA) + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Starts Manual hash algorithm process. + */ +void SHA_Start(void) +{ + SHA->SHA_CR = SHA_CR_START; +} + +/** + * \brief Resets the SHA. A software triggered hardware reset of the SHA interface is performed. + */ +void SHA_SoftReset(void) +{ + SHA->SHA_CR = SHA_CR_SWRST; +} + +/** + * \brief Indicates that the next block to process is the first one of a message. + */ +void SHA_FirstBlock(void) +{ + SHA->SHA_CR = SHA_CR_FIRST; +} + +/** + * \brief Configures an SHA peripheral with the specified parameters. + * \param mode Desired value for the SHA mode register (see the datasheet). + */ +void SHA_Configure(uint32_t mode) +{ + SHA->SHA_MR = mode; +} + +/** + * \brief Enables the selected interrupts sources on a SHA peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void SHA_EnableIt(uint32_t sources) +{ + SHA->SHA_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a SHA peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void SHA_DisableIt(uint32_t sources) +{ + SHA->SHA_IDR = sources; +} + +/** + * \brief Get the current status register of the given SHA peripheral. + * \return SHA status register. + */ +uint32_t SHA_GetStatus(void) +{ + return SHA->SHA_ISR; +} + +/** + * \brief Set the 32-bit Input Data registers allow to load the data block used for hash processing. + * \param data Pointer data block. + * \param len 512/1024-bits block size + */ +void SHA_SetInput(uint32_t *data, uint8_t len) +{ + uint8_t i; + uint8_t num; + num = len <= 16 ? len: 16; + for (i = 0; i < num ; i++) + SHA->SHA_IDATAR[i] = (data[i]); + num = len > 16 ? len - 16: 0; + for (i = 0; i < num; i++) + SHA->SHA_IODATAR[i] = (data[i+16]); +} + +/** + * \brief Getread the resulting message digest and to write the second part of the message block when the +* SHA algorithm is SHA-384 or SHA-512. + * \param data pointer to the word that has been encrypted/decrypted.. + */ +void SHA_GetOutput(uint32_t *data) +{ + uint8_t i; + for (i = 0; i < 16; i++) + data[i] = SHA->SHA_IODATAR[i]; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/smcNfc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/smcNfc.c new file mode 100644 index 000000000..60b6b97dd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/smcNfc.c @@ -0,0 +1,742 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ +/** + * \file + * + * Implementation of NFC functions. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +static SmcStatus smcStatus; +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Counts and return the number of bits set to '1' in the given hsiao code. + * \param code Hsizo code. + */ +static unsigned char CountBitsInByte(unsigned char byte) +{ + unsigned char count = 0; + while (byte > 0) { + + if (byte & 1) { + + count++; + } + byte >>= 1; + } + + return count; +} + +/** + * \brief Counts and return the number of bits set to '1' in the given hsiao code. + * \param code Hsizo code. + */ +static unsigned char CountBitsInCode(unsigned char *code) +{ + return CountBitsInByte(code[0]) + + CountBitsInByte(code[1]) + + CountBitsInByte(code[2]); +} + +/** + * \brief Clear the corresponding interrupt flag. + */ +static void SMC_Clear_Status (void) +{ + smcStatus.BStatus = 0; +} + +/** + * \brief Check the STATUS and set the corresponding interrupt flag. + */ +static void SMC_Handler(void) +{ + uint32_t status; + status = SMC->SMC_SR; +#if 0 + if ((status & SMC_SR_SMCSTS) == SMC_SR_SMCSTS) + /* NAND Flash Controller is enabled */ + smcStatus.bStatus.smcSts = 1; +#endif + if ((status & SMC_SR_XFRDONE) == SMC_SR_XFRDONE) + /* When set to one, this flag indicates that the NFC has terminated the Data Transfer. This flag is reset after a status read + operation. */ + smcStatus.bStatus.xfrDone = 1; + if ((status & SMC_SR_CMDDONE) == SMC_SR_CMDDONE) + /* When set to one, this flag indicates that the NFC has terminated the Command. This flag is reset after a status read + operation.*/ + smcStatus.bStatus.cmdDone = 1; + if ((status & (1<<24)) == (1<<24)) + /* If set to one, this flag indicates that an edge has been detected on the Ready/Busy Line x. Depending on the EDGE CTRL + field located in the SMC_CFG register, only rising or falling edge is detected. This flag is reset after a status read operation. */ + smcStatus.bStatus.rbEdge = 1; + if ((status & SMC_SR_ECCRDY) == SMC_SR_ECCRDY) + /* When set to one, this flag indicates that the Hamming ECC computation is completed. This flag is reset after a status read + operation.*/ + smcStatus.bStatus.hammingReady = 1; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Sets NFC configuration. + * \param cfg NFC configuration. + */ +void SMC_NFC_Configure(uint32_t cfg) +{ + SMC->SMC_CFG = cfg; +} + +/** + * \brief Reset NFC controller. + */ +void SMC_NFC_Reset(void) +{ + /* Disable all the SMC NFC interrupts */ + SMC->SMC_IDR = 0xFFFFFFFF; + SMC->SMC_CTRL = 0; +} + +/** + * \brief Enable NFC controller. + */ +void SMC_NFC_EnableNfc(void) +{ + SMC->SMC_CTRL |= SMC_CTRL_NFCEN; +} + +/** + * \brief Enable NFC controller reads both main and spare area in read mode. + */ +void SMC_NFC_EnableSpareRead(void) +{ + SMC->SMC_CFG |= SMC_CFG_RSPARE; +} + +/** + * \brief The NFC controller skips spare area in read mode. + */ +void SMC_NFC_DisableSpareRead(void) +{ + SMC->SMC_CFG &= (~SMC_CFG_RSPARE); +} + +/** + * \brief Enables the NFC controller writes both main and spare area in write + */ +void SMC_NFC_EnableSpareWrite(void) +{ + SMC->SMC_CFG |= SMC_CFG_WSPARE; +} + +/** + * \brief The NFC controller skips spare area in write mode. + */ +void SMC_NFC_DisableSpareWrite(void) +{ + SMC->SMC_CFG &= (~SMC_CFG_WSPARE); +} + +/** + * \brief Check if spare area be read in read mode. + * + * \return Returns 1 if NFC controller reads both main and spare area in + * read mode, otherwise returns 0. + */ +uint8_t SMC_NFC_isSpareRead(void) +{ + return (((SMC->SMC_CFG) >> 9) & 0x1); +} + +/** + * \brief Check if spare area be written in write mode. + * + * \return Returns 1 if NFC controller writes both main and spare area in + * write mode, otherwise returns 0. + */ +uint8_t SMC_NFC_isSpareWrite(void) +{ + return (((SMC->SMC_CFG) >> 8) & 0x1); +} + +/** + * \brief Check if NFC transfer complete. + * \return Returns 1 if NFC controller has terminated the data transmission, + * otherwise returns 0. + */ +uint8_t SMC_NFC_isTransferComplete(void) +{ + return ((SMC->SMC_SR & SMC_SR_XFRDONE) == SMC_SR_XFRDONE); +} + +/** + * \brief Check Ready/Busy line. + * + * \return Returns 1 if edge has been detected on the Ready/Busy line, + * otherwise returns 0. + */ +uint8_t SMC_NFC_isReadyBusy(void) +{ + return ((SMC->SMC_SR & SMC_SR_RB_EDGE0) == SMC_SR_RB_EDGE0); +} + +/** + * \brief Check if NFC Controller is busy. + * + * \return Returns 1 if NFC Controller is activated and accesses the memory device, + * otherwise returns 0. + */ +uint8_t SMC_NFC_isNfcBusy(void) +{ + return ((SMC->SMC_SR & SMC_SR_NFCBUSY) == SMC_SR_NFCBUSY); +} + +/** + * \brief Get NFC Status. + * + * \return Returns the current status register of SMC NFC Status Register. + * This resets the internal value of the status register, so further + * read may yield different values. + */ +uint32_t SMC_NFC_GetStatus(void) +{ + return SMC->SMC_SR; +} + +/* + * HOST command functions + */ + +/** + * \brief Check if the host controller is busy. + * \return Returns 1 if the host controller is busy, otherwise returns 0. + */ +static uint8_t SMC_NFC_isHostBusy(void) +{ + return (((*((volatile uint32_t *) (NFC_CMD_BASE_ADDR + NFCADDR_CMD_NFCCMD))) & 0x8000000) == 0x8000000); +} + +/** + * \brief Wait for NFC command has done. +*/ +void SMC_NFC_Wait_CommandDone(void) +{ + while (smcStatus.bStatus.cmdDone == 0) + { + SMC_Handler(); + } +} + +/** + * \brief Wait for NFC Data Transfer Terminated. +*/ +void SMC_NFC_Wait_XfrDone(void) +{ + while (smcStatus.bStatus.xfrDone == 0) + { + SMC_Handler(); + } +} + +/** + * \brief Wait for NFC Data Transfer Terminated. +*/ +void SMC_NFC_Wait_HammingReady(void) +{ + while (smcStatus.bStatus.hammingReady ==0) + { + SMC_Handler(); + } +} + +/** + * \brief Wait for NFC Ready/Busy Line 3 Edge Detected. +*/ +void SMC_NFC_Wait_RBbusy(void) +{ + while (smcStatus.bStatus.rbEdge == 0) + { + SMC_Handler(); + } +} + +/** + * \brief Uses the HOST nandflash conntroller to send a command to the NFC. + * \param cmd command to send. + * \param addressCycle address cycle when command access id decoded. + * \param cycle0 address at first cycle. + */ +void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, uint32_t cycle0) +{ + volatile uint32_t *pCommandAddress; + SMC_Clear_Status(); + /* Wait until host controller is not busy. */ + while(SMC_NFC_isHostBusy()); + /* Send the command plus the ADDR_CYCLE */ + pCommandAddress = (volatile uint32_t *) (cmd + NFC_CMD_BASE_ADDR); + SMC->SMC_ADDR = cycle0; + *pCommandAddress = addressCycle; + SMC_NFC_Wait_CommandDone(); +} + +/* ECC function */ + +/** + * \brief Get 24-bit ECC code for 8-bit data path NAND flash. + * 24-bit ECC is generated in order to perform one bit correction + * for 512 byte in page 512/1024/2048/4096 for 8-bit words + * + * \param size Data size in bytes. + * \param code Codes buffer. + */ +static void _smc_ecc_GetW9BitPer512Ecc(uint32_t pageDataSize, uint8_t *code) +{ + uint8_t i; + uint8_t numEcc; + uint32_t eccParity; + uint32_t ecc[16]; + + SMC_ECC_GetValue(ecc); + numEcc = pageDataSize / 512; + /* P2048' P1024' P512' P256' P128' P64' P32' P16' --- 3rd. Ecc Byte to store */ + /* P8' P4' P2' P1' P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */ + /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */ + for (i = 0; i < numEcc; i++) { + /* Get Parity and NParity value. */ + eccParity = ecc[i]; + eccParity = ~eccParity; + code[i * 3] = eccParity & 0xff; + code[i * 3 + 1] = (eccParity >> 8) & 0xff; + code[i * 3 + 2] = (eccParity >> 16) & 0xff; + } +} + +/** + * \brief Get 24-bit ECC code for 8-bit data path NAND flash. + * 24-bit ECC is generated in order to perform one bit correction + * for 256 byte in page 512/1024/2048/4096 for 8-bit words + * + * \param size Data size in bytes. + * \param code Codes buffer. + */ +static void _smc_ecc_GetW8BitPer256Ecc(uint32_t pageDataSize, uint8_t *code) +{ + uint8_t i; + uint8_t numEcc; + uint32_t eccParity; + uint32_t ecc[16]; + + SMC_ECC_GetValue(ecc); + numEcc = pageDataSize / 256; + + /* P2048' P1024' P512' P256' P128' P64' P32' P16' --- 3rd. Ecc Byte to store */ + /* P8' P4' P2' P1' P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */ + /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */ + for (i = 0; i < numEcc; i++) { + /* Get Parity and NParity value. */ + eccParity = ecc[i]; + eccParity = ~eccParity; + TRACE_DEBUG("ecc Parity%d is 0x%08x \n\r", (int)i, (uint32_t)eccParity); + code[i * 3] = eccParity & 0xff; + code[i * 3 + 1] = (eccParity >> 8) & 0xff; + code[i * 3 + 2] = (eccParity >> 16) & 0xff; + } +} + +/** + * \breif Get 32-bit ECC code for 16-bit data path NAND flash. + * 32-bit ECC is generated in order to perform one bit correction + * for a page in page 512/1024/2048/4096 for 16-bit words + * + * \param size Data size in bytes. + * \param code Codes buffer. + */ +static void _smc_ecc_GetW12BitPerPageEcc(uint32_t pageDataSize, uint8_t *code) +{ + uint32_t eccParity; + uint32_t eccNparity; + uint32_t ecc[16]; + + pageDataSize = pageDataSize; /* stop warning */ + /* Get Parity value. */ + SMC_ECC_GetValue(ecc); + + /* ---- P16384'P8192'P4096'P2048' P1024'P512'P256' --- 4th. Ecc Byte to store */ + /* P128' P64' P32' P16' P8' P4' P2' P1' --- 3rd. Ecc Byte to store */ + /* ---- P16384 P8192 P4096 P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */ + /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */ + + /* Invert codes (linux compatibility) */ + eccParity = ecc[0]; + eccNparity = ecc[1]; + code[0] = eccParity & 0xff; + code[1] = (eccParity >> 8 )& 0xff; + code[2] = eccNparity & 0xff; + code[3] = (eccNparity >> 8 )& 0xff; +} + + +/** + * \brief Configures ECC mode. + * \param type Type of correction. + * \param pageSize Page size of NAND flash device. + */ +void SMC_ECC_Configure(uint32_t type, uint32_t pageSize) +{ + /* Software Reset ECC. */ + SMC->SMC_ECC_CTRL = (0x1 << 1) ; + SMC->SMC_ECC_MD = type | pageSize; +} + +/** + * \brief Get ECC correction type. + * + * \return Returns type of ECC correction setting. + */ +uint32_t SMC_ECC_GetCorrectoinType(void) +{ + return ((SMC->SMC_ECC_MD)& SMC_ECC_MD_TYPCORREC_Msk); +} + +/** + * \brief Get ECC status. + * \param eccNumber ecc parity number from 0 to 15. + * + * \return Returns ECC status by giving ecc number. + */ +uint8_t SMC_ECC_GetStatus(uint8_t eccNumber) +{ + uint32_t status; + + if (eccNumber < 8){ + status = SMC->SMC_ECC_SR1; + } + else { + status = SMC->SMC_ECC_SR2; + eccNumber -=8; + } + return ((status >> (eccNumber * 4)) & 0x07); +} + +/** + * \brief Get all ECC parity and Nparity value. + */ +void SMC_ECC_GetValue(uint32_t *ecc) +{ + ecc[0] = SMC->SMC_ECC_PR0; + ecc[1] = SMC->SMC_ECC_PR1; + ecc[2] = SMC->SMC_ECC_PR2; + ecc[3] = SMC->SMC_ECC_PR3; + ecc[4] = SMC->SMC_ECC_PR4; + ecc[5] = SMC->SMC_ECC_PR5; + ecc[6] = SMC->SMC_ECC_PR6; + ecc[7] = SMC->SMC_ECC_PR7; + ecc[8] = SMC->SMC_ECC_PR8; + ecc[9] = SMC->SMC_ECC_PR9; + ecc[10] = SMC->SMC_ECC_PR10; + ecc[11] = SMC->SMC_ECC_PR11; + ecc[12] = SMC->SMC_ECC_PR12; + ecc[13] = SMC->SMC_ECC_PR13; + ecc[14] = SMC->SMC_ECC_PR14; + ecc[15] = SMC->SMC_ECC_PR15; +} + +/** + * \brief verifies 4-bytes hsiao codes for a data block whose size is a page Size + * word. Page words block is verified between the given HSIAO code + * generated by hardware and original HSIAO codes store has been previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + */ +static uint8_t _smc_ecc_VerifyW12BitPerPageEcc( + uint8_t *data, + const uint8_t *originalCode, + const uint8_t *verifyCode) +{ + uint8_t correctionCode[4]; + uint8_t bitCount; + // Xor both codes together + correctionCode[0] = verifyCode[0] ^ originalCode[0]; + correctionCode[1] = verifyCode[1] ^ originalCode[1]; + correctionCode[2] = verifyCode[2] ^ originalCode[2]; + correctionCode[3] = verifyCode[3] ^ originalCode[3]; + TRACE_DEBUG("Correction code = %02X %02X %02X %02X\n\r", + correctionCode[0], correctionCode[1], correctionCode[2], correctionCode[3]); + /* If all bytes are 0, there is no error */ + if ((correctionCode[0] == 0) + && (correctionCode[1] == 0) + && (correctionCode[2] == 0) + && (correctionCode[3] == 0)) { + + return 0; + } + /* If there is a single bit error, there are 15 bits set to 1 */ + bitCount = CountBitsInByte(correctionCode[0]) + + CountBitsInByte(correctionCode[1]) + + CountBitsInByte(correctionCode[2]) + + CountBitsInByte(correctionCode[3]); + if (bitCount == 15) { + /* Get byte and bit indexes */ + uint16_t byte = (correctionCode[0] & 0xf0) >> 4; + byte |= (correctionCode[1] & 0xff) << 4; + uint8_t bit = correctionCode[0] & 0x0f; + /* Correct bit */ + printf("Correcting byte #%d at bit %d\n\r", byte, bit); + data[byte] ^= (1 << bit); + + return Hsiao_ERROR_SINGLEBIT; + } + + /* Check if ECC has been corrupted */ + if (bitCount == 1) { + return Hsiao_ERROR_ECC; + } + /* Otherwise, this is a multi-bit error */ + else { + return Hsiao_ERROR_MULTIPLEBITS; + } +} + +/** + * \brief erifies 3-bytes hsiao codes for a data block whose size is a page Size + * word. Page words block is verified between the given HSIAO code + * generated by hardware and original HSIAO codes store has been previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + */ +static uint8_t _smc_ecc_VerifyW8BitPer256Ecc( + uint8_t *data, + uint32_t size, + const uint8_t *originalCode, + const uint8_t *verifyCode) +{ + uint8_t correctionCode[3]; + uint32_t position = 0; + uint8_t byte; + uint8_t bit; + uint8_t error = 0; + + TRACE_DEBUG("_smc_ecc_VerifyW8BitPer256Ecc()\n\r"); + while (position < size) { + /* Xor both codes together */ + correctionCode[0] = verifyCode[0] ^ originalCode[0]; + correctionCode[1] = verifyCode[1] ^ originalCode[1]; + correctionCode[2] = verifyCode[2] ^ originalCode[2]; + TRACE_DEBUG("Correction code = %02X %02X %02X\n\r", + correctionCode[0], correctionCode[1], correctionCode[2]); + + /* If all bytes are 0, there is no error */ + if ( correctionCode[0] || correctionCode[1] || correctionCode[2]) { + /* If there is a single bit error, there are 11 bits set to 1 */ + if (CountBitsInCode(correctionCode) == 11) { + /* Get byte and bit indexes */ + byte = (correctionCode[0] & 0xf8) >> 3; + byte |= (correctionCode[1] & 0x07) << 5; + bit = correctionCode[0] & 0x07; + /* Correct bit */ + printf("Correcting byte #%u at bit %u\n\r", (unsigned int)(position + byte), (unsigned int)bit); + data[byte] ^= (1 << bit); + error = Hsiao_ERROR_SINGLEBIT; + } + /* Check if ECC has been corrupted */ + else if (CountBitsInCode(correctionCode) == 1) { + return Hsiao_ERROR_ECC; + } + else { + /* Otherwise, this is a multi-bit error */ + return Hsiao_ERROR_MULTIPLEBITS; + } + } + data += 256; + originalCode += 3; + verifyCode += 3; + position += 256; + } + return error; +} + +/** + * \brief 3-bytes hsiao codes for a data block whose size is multiple of + * 512 bytes. Each 512-bytes block is verified between the given HSIAO code + * generated by hardware and original HSIAO codes store has been previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + */ +static uint8_t _smc_ecc_VerifyW9BitPer512Ecc( + uint8_t *data, + uint32_t size, + const uint8_t *originalCode, + const uint8_t *verifyCode) +{ + uint8_t correctionCode[3]; + uint32_t position = 0; + uint16_t byte; + uint8_t bit; + uint8_t error = 0; + + TRACE_DEBUG("_smc_ecc_VerifyW9BitPer512Ecc()\n\r"); + while (position < size) { + /* Xor both codes together */ + correctionCode[0] = verifyCode[0] ^ originalCode[0]; + correctionCode[1] = verifyCode[1] ^ originalCode[1]; + correctionCode[2] = verifyCode[2] ^ originalCode[2]; + TRACE_DEBUG("Correction code = %02X %02X %02X\n\r", + correctionCode[0], correctionCode[1], correctionCode[2]); + + /* If all bytes are 0, there is no error */ + if ( correctionCode[0] || correctionCode[1] || correctionCode[2]) { + // If there is a single bit error, there are 11 bits set to 1 + if (CountBitsInCode(correctionCode) == 12) { + /* Get byte and bit indexes */ + byte = (correctionCode[0] & 0xf8) >> 3; + byte |= (correctionCode[1] & 0x0f) << 5; + bit = correctionCode[0] & 0x07; + /* Correct bit */ + printf("Correcting byte #%u at bit %u\n\r", (unsigned int)(position + byte), (unsigned int)bit); + data[byte] ^= (1 << bit); + error = Hsiao_ERROR_SINGLEBIT; + } + /* Check if ECC has been corrupted */ + else if (CountBitsInCode(correctionCode) == 1) { + return Hsiao_ERROR_ECC; + } + else { + /* Otherwise, this is a multi-bit error */ + return Hsiao_ERROR_MULTIPLEBITS; + } + } + data += 512; + originalCode += 3; + verifyCode += 3; + position += 512; + } + return error; +} + +/** + * Get ECC code for 8bit/16-bit data path NAND flash by giving data path. + * 24-bit or 32-bit ECC is generated in order to perform one bit correction + * for a page in page 512/1024/2048/4096. + * + * \param size Data size in bytes. + * \param code Codes buffer. + * \param busWidth 8bit/16bit data path. + */ +void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, uint8_t busWidth) +{ + uint8_t correctionType; + + correctionType = SMC_ECC_GetCorrectoinType(); + /* For 16-bit data path */ + if (busWidth == 16 && correctionType == SMC_ECC_MD_TYPCORREC_CPAGE ) + _smc_ecc_GetW12BitPerPageEcc(pageDataSize, code); + /* For 8-bit data path */ + else { + switch (correctionType){ + case SMC_ECC_MD_TYPCORREC_CPAGE: + _smc_ecc_GetW12BitPerPageEcc(pageDataSize, code); + break; + case SMC_ECC_MD_TYPCORREC_C256B: + _smc_ecc_GetW8BitPer256Ecc(pageDataSize, code); + break; + case SMC_ECC_MD_TYPCORREC_C512B: + _smc_ecc_GetW9BitPer512Ecc(pageDataSize, code); + break; + } + } +} + + +/** + * Verifies hsiao codes for a data block. The block is verified between the given + * HSIAO code generated by hardware and original HSIAO codes store has been + * previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param size Size of the data in words. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + * \param dataPath 8bit/16bit data path. +*/ +uint8_t SMC_ECC_VerifyHsiao( + uint8_t *data, + uint32_t size, + const uint8_t *originalCode, + const uint8_t *verifyCode, + uint8_t busWidth) +{ + uint8_t correctionType; + uint8_t error = 0; + correctionType = SMC_ECC_GetCorrectoinType(); + /* For 16-bit data path */ + if (busWidth == 16 && (correctionType == SMC_ECC_MD_TYPCORREC_CPAGE) ) { + error = _smc_ecc_VerifyW12BitPerPageEcc((uint8_t*)data, originalCode, verifyCode); + } + /* For 8-bit data path */ + else { + switch (correctionType){ + case SMC_ECC_MD_TYPCORREC_CPAGE: + error = _smc_ecc_VerifyW12BitPerPageEcc(data, originalCode, verifyCode); + + break; + case SMC_ECC_MD_TYPCORREC_C256B: + error = _smc_ecc_VerifyW8BitPer256Ecc(data, size, originalCode, verifyCode); + break; + case SMC_ECC_MD_TYPCORREC_C512B: + error = _smc_ecc_VerifyW9BitPer512Ecc(data, size, originalCode, verifyCode); + break; + } + } + return error; +} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/spi.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/spi.c new file mode 100644 index 000000000..bd25749bc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/spi.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup spi_module Working with SPI + * The SPI driver provides the interface to configure and use the SPI + * peripheral. + * + * The Serial Peripheral Interface (SPI) circuit is a synchronous serial + * data link that provides communication with external devices in Master + * or Slave Mode. + * + * To use the SPI, the user has to follow these few steps: + * -# Enable the SPI pins required by the application (see pio.h). + * -# Configure the SPI using the \ref SPI_Configure(). This enables the + * peripheral clock. The mode register is loaded with the given value. + * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS(). + * -# Enable the SPI by calling \ref SPI_Enable(). + * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read() + * must be called after \ref SPI_Write() to retrieve the last value read. + * -# Disable the SPI by calling \ref SPI_Disable(). + * + * For more accurate information, please look at the SPI section of the + * Datasheet. + * + * Related files :\n + * \ref spi.c\n + * \ref spi.h.\n +*/ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of Serial Peripheral Interface (SPI) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables a SPI peripheral. + * + * \param spi Pointer to an Spi instance. + */ +extern void SPI_Enable( Spi* spi ) +{ + spi->SPI_CR = SPI_CR_SPIEN ; +} + +/** + * \brief Disables a SPI peripheral. + * + * \param spi Pointer to an Spi instance. + */ +extern void SPI_Disable( Spi* spi ) +{ + spi->SPI_CR = SPI_CR_SPIDIS ; +} + +/** + * \brief Enables one or more interrupt sources of a SPI peripheral. + * + * \param spi Pointer to an Spi instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) +{ + spi->SPI_IER = dwSources ; +} + +/** + * \brief Disables one or more interrupt sources of a SPI peripheral. + * + * \param spi Pointer to an Spi instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) +{ + spi->SPI_IDR = dwSources ; +} + +/** + * \brief Configures a SPI peripheral as specified. The configuration can be computed + * using several macros (see \ref spi_configuration_macros). + * + * \param spi Pointer to an Spi instance. + * \param id Peripheral ID of the SPI. + * \param configuration Value of the SPI configuration register. + */ +extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) +{ + PMC_EnablePeripheral( dwId ) ; + spi->SPI_CR = SPI_CR_SPIDIS ; + + /* Execute a software reset of the SPI twice */ + spi->SPI_CR = SPI_CR_SWRST ; + spi->SPI_CR = SPI_CR_SWRST ; + spi->SPI_MR = dwConfiguration ; +} + +/** + * \brief Configures SPI chip select. + * + * \param spi Pointer to an Spi instance. + * \param cS Chip select of NPSCx. + */ +extern void SPI_ChipSelect( Spi* spi, uint8_t cS) +{ + spi->SPI_MR |= SPI_MR_PCS_Msk ; + spi->SPI_MR &= ~(SPI_MR_PCS ( cS )) ; +} + +/** + * \brief Configures SPI Mode Register. + * + * \param spi Pointer to an Spi instance. + * \param configuration Value of the SPI mode register. + */ +extern void SPI_SetMode( Spi* spi, + uint32_t dwConfiguration ) +{ + spi->SPI_MR = dwConfiguration ; +} + +/** + * \brief Configures SPI to release last used CS line. + * + * \param spi Pointer to an Spi instance. + */ +extern void SPI_ReleaseCS( Spi* spi ) +{ + spi->SPI_CR = SPI_CR_LASTXFER ; +} + + +/** + * \brief Configures a chip select of a SPI peripheral. The chip select configuration + * is computed using several macros (see \ref spi_configuration_macros). + * + * \param spi Pointer to an Spi instance. + * \param npcs Chip select to configure (0, 1, 2 or 3). + * \param configuration Desired chip select configuration. + */ +void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) +{ + spi->SPI_CSR[dwNpcs] = dwConfiguration ; +} + +/** + * \brief Configures a chip select active mode of a SPI peripheral. + * + * \param spi Pointer to an Spi instance. + * \param dwNpcs Chip select to configure (0, 1, 2 or 3). + * \param bReleaseOnLast CS controlled by last transfer. + * SPI_ReleaseCS() is used to deactive CS. + */ +void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast ) +{ + if (bReleaseOnLast) + { + spi->SPI_CSR[dwNpcs] |= SPI_CSR_CSAAT; + } + else + { + spi->SPI_CSR[dwNpcs] &= ~SPI_CSR_CSAAT; + } +} + +/** + * \brief Get the current status register of the given SPI peripheral. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param spi Pointer to a Spi instance. + * \return SPI status register. + */ +extern uint32_t SPI_GetStatus( Spi* spi ) +{ + return spi->SPI_SR ; +} + +/** + * \brief Reads and returns the last word of data received by a SPI peripheral. This + * method must be called after a successful SPI_Write call. + * + * \param spi Pointer to an Spi instance. + * + * \return readed data. + */ +extern uint32_t SPI_Read( Spi* spi ) +{ + while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ; + + return spi->SPI_RDR & 0xFFFF ; +} + +/** + * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed + * peripheral select, the npcs value is meaningless. Otherwise, it identifies + * the component which shall be addressed. + * + * \param spi Pointer to an Spi instance. + * \param npcs Chip select of the component to address (0, 1, 2 or 3). + * \param data Word of data to send. + */ +extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) +{ + /* Send data */ + while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ; + spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ; + while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ; +} + +/** + * \brief Sends last data through a SPI peripheral. + * If the SPI is configured to use a fixed peripheral select, the npcs value is + * meaningless. Otherwise, it identifies the component which shall be addressed. + * + * \param spi Pointer to an Spi instance. + * \param npcs Chip select of the component to address (0, 1, 2 or 3). + * \param data Word of data to send. + */ +extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData ) +{ + /* Send data */ + while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ; + spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) | SPI_TDR_LASTXFER ; + while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ; +} + +/** + * \brief Check if SPI transfer finish. + * + * \param spi Pointer to an Spi instance. + * + * \return Returns 1 if there is no pending write operation on the SPI; otherwise + * returns 0. + */ +extern uint32_t SPI_IsFinished( Spi* spi ) +{ + return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/ssc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/ssc.c new file mode 100644 index 000000000..6ab87045b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/ssc.c @@ -0,0 +1,219 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup ssc_module Working with SSC + * The SSC driver provides the interface to configure and use the SSC + * peripheral. + * + * !Usage + * + * -# Enable the SSC interface pins. + * -# Configure the SSC to operate at a specific frequency by calling + * SSC_Configure(). This function enables the peripheral clock of the SSC, + * but not its PIOs. + * -# Configure the transmitter and/or the receiver using the + * SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions. + * -# Enable the PIOs or the transmitter and/or the received. + * -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter() + * and SSC_EnableReceiver() + * -# Send data through the transmitter using SSC_Write() + * -# Receive data from the receiver using SSC_Read() + * -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter() + * and SSC_DisableReceiver() + * + * For more accurate information, please look at the SSC section of the + * Datasheet. + * + * Related files :\n + * \ref ssc.c\n + * \ref ssc.h.\n +*/ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Synchronous Serial (SSC) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a SSC peripheral.If the divided clock is not used, the master + * clock frequency can be set to 0. + * \note The emitter and transmitter are disabled by this function. + * \param ssc Pointer to an SSC instance. + * \param bitRate bit rate. + * \param masterClock master clock. + */ +void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock) +{ + uint32_t id; + uint32_t maxClock; + id = (ssc == SSC0 )? ID_SSC0 : ID_SSC1; + maxClock = PMC_SetPeriMaxClock(id, masterClock); + + /* Reset, disable receiver & transmitter */ + ssc->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST; + + /* Configure clock frequency */ + if (bitRate != 0) { + + ssc->SSC_CMR = maxClock / (2 * bitRate); + } + else { + + ssc->SSC_CMR = 0; + } + /* Enable SSC peripheral clock */ + PMC_EnablePeripheral(id); +} + +/** + * \brief Configures the transmitter of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param tcmr Transmit Clock Mode Register value. + * \param tfmr Transmit Frame Mode Register value. + */ +void SSC_ConfigureTransmitter(Ssc *ssc,uint32_t tcmr, uint32_t tfmr) +{ + ssc->SSC_TCMR = tcmr; + ssc->SSC_TFMR = tfmr; +} + +/** + * \brief Configures the receiver of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param rcmr Receive Clock Mode Register value. + * \param rfmr Receive Frame Mode Register value. + */ +void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr) +{ + ssc->SSC_RCMR = rcmr; + ssc->SSC_RFMR = rfmr; +} + +/** + * \brief Enables the transmitter of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_EnableTransmitter(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_TXEN; +} + +/** + * \brief Disables the transmitter of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_DisableTransmitter(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_TXDIS; +} + +/** + * \brief Enables the receiver of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_EnableReceiver(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_RXEN; +} + +/** + * \brief Disables the receiver of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_DisableReceiver(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_RXDIS; +} + +/** + * \brief Enables one or more interrupt sources of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources) +{ + ssc->SSC_IER = sources; +} + +/** + * \brief Disables one or more interrupt sources of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources) +{ + ssc->SSC_IDR = sources; +} + +/** + * \brief Sends one data frame through a SSC peripheral. If another frame is currently + * being sent, this function waits for the previous transfer to complete. + * \param ssc Pointer to an SSC instance. + * \param frame Data frame to send. + */ +void SSC_Write(Ssc *ssc, uint32_t frame) +{ + while ((ssc->SSC_SR & SSC_SR_TXRDY) == 0); + ssc->SSC_THR = frame; +} + +/** + * \brief Waits until one frame is received on a SSC peripheral, and returns it. + * \param ssc Pointer to an SSC instance. + */ +uint32_t SSC_Read(Ssc *ssc) +{ + while ((ssc->SSC_SR & SSC_SR_RXRDY) == 0); + return ssc->SSC_RHR; +} + +/** + * \brief Return 1 if one frame is received, 0 otherwise. + * \param ssc Pointer to an SSC instance. + */ +uint8_t SSC_IsRxReady(Ssc *ssc) +{ + return ((ssc->SSC_SR & SSC_SR_RXRDY) > 0); +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/tc.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/tc.c new file mode 100644 index 000000000..f19e3126a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/tc.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup tc_module + * The TC driver provides the Interface to configure the Timer Counter (TC). + * + * \section Usage + *
    + *
  • Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically.
    • + *
  • Configure a Timer Counter in the desired mode using TC_Configure().
    • + *
  • Start or stop the timer clock using TC_Start() and TC_Stop().
    • + * + *
+ * For more accurate information, please look at the TC section of the Datasheet. + * + * Related files :\n + * \ref tc.c\n + * \ref tc.h.\n +*/ + + /** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +/** + * \file + * + * Implementation of Timer Counter (TC). + * + */ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +/** + * \brief Configures a Timer Counter Channel + * + * Configures a Timer Counter to operate in the given mode. Timer is stopped + * after configuration and must be restarted with TC_Start(). All the + * interrupts of the timer are also disabled. + * + * \param pTc Pointer to a Tc instance. + * \param channel Channel number. + * \param mode Operating mode (TC_CMR value). + */ +extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) +{ + TcChannel* pTcCh ; + + assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ; + pTcCh = pTc->TC_CHANNEL+dwChannel ; + + /* Disable TC clock */ + pTcCh->TC_CCR = TC_CCR_CLKDIS ; + + /* Disable interrupts */ + pTcCh->TC_IDR = 0xFFFFFFFF ; + + /* Clear status register */ + pTcCh->TC_SR ; + + /* Set mode */ + pTcCh->TC_CMR = dwMode ; +} + +/** + * \brief Reset and Start the TC Channel + * + * Enables the timer clock and performs a software reset to start the counting. + * + * \param pTc Pointer to a Tc instance. + * \param dwChannel Channel number. + */ +extern void TC_Start( Tc *pTc, uint32_t dwChannel ) +{ + TcChannel* pTcCh ; + + assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ; + + pTcCh = pTc->TC_CHANNEL+dwChannel ; + pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ; +} + +/** + * \brief Stop TC Channel + * + * Disables the timer clock, stopping the counting. + * + * \param pTc Pointer to a Tc instance. + * \param dwChannel Channel number. + */ +extern void TC_Stop(Tc *pTc, uint32_t dwChannel ) +{ + TcChannel* pTcCh ; + + assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ; + + pTcCh = pTc->TC_CHANNEL+dwChannel ; + pTcCh->TC_CCR = TC_CCR_CLKDIS ; +} + +/** + * \brief Find best MCK divisor + * + * Finds the best MCK divisor given the timer frequency and MCK. The result + * is guaranteed to satisfy the following equation: + * \code + * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) + * \endcode + * with DIV being the highest possible value. + * + * \param dwFreq Desired timer frequency. + * \param dwMCk Master clock frequency. + * \param dwDiv Divisor value. + * \param dwTcClks TCCLKS field value for divisor. + * \param dwBoardMCK Board clock frequency. + * + * \return 1 if a proper divisor has been found, otherwise 0. + */ +extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) +{ + const uint32_t adwDivisors[5] = { 2, 8, 32, 128, dwBoardMCK / 32768 } ; + + uint32_t dwIndex = 0 ; + + /* Satisfy lower bound */ + while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) ) + { + dwIndex++ ; + + /* If no divisor can be found, return 0 */ + if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] )) ) + { + return 0 ; + } + } + + /* Try to maximize DIV while satisfying upper bound */ + while ( dwIndex < 4 ) + { + + if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) ) + { + break ; + } + dwIndex++ ; + } + + /* Store results */ + if ( dwDiv ) + { + *dwDiv = adwDivisors[dwIndex] ; + } + if ( dwTcClks ) + { + *dwTcClks = dwIndex ; + } + + return 1 ; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/tdes.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/tdes.c new file mode 100644 index 000000000..873724fcf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/tdes.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup tdes_module Working with TDES + * \ingroup peripherals_module + * The TDES driver provides the interface to configure and use the TDES peripheral. + * \n + * + * The Data Encryption Standard (DES) and the Triple Data Encryption Algorithm (TDES) specify + * FIPS-approved cryptographic algorithms that can be used to protect electronic data. The TDES + * bit in the TDES Mode Register (TDES_MR) is used to select either the single DES or the Triple + * DES mode by function TDES_Configure(). + * A DES is capable of using cryptographic keys of 64 bits to encrypt and decrypt data in blocks of + * 64 bits, Date input can be set with TDES_SetInput(). This 64-bit key is defined in the Key 1 Word + * Registers (TDES_KEY1WRx) and set by TDES_WriteKey1. A TDES key consists of three DES keys, + * which is also referred to as a key bundle. These three 64-bit keys are defined, respectively, + * in the Key 1, 2 and 3 Word Registers (TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx). + * In Triple DES mode (TDESMOD set to 1), the KEYMOD bit in the TDES Mode Register is used to choose between a two- and a three-key + * algorithm: + * + * To Enable a TDES encryption and decryption,the user has to follow these few steps: + *
    + *
  • A software triggered hardware reset of the TDES interface is performed by TDES_SoftReset().
    • + *
  • Configure TDES algorithm mode, key mode, start mode and operation mode by TDES_Configure().
    • + *
  • Set DES key with fucntion TDES_WriteKey1(), TDES_WriteKey2(), or TDES_WriteKey3().
    • + *
  • Input TDES data for encryption and decryption with function TDES_SetInput()
    • + *
  • To start the encryption or the decryption process with TDES_Start()
    • + *
  • To get the encryption or decryption reslut by TDES_GetOutput()
    • + *
+ * + * For more accurate information, please look at the TDES section of the + * Datasheet. + * + * Related files :\n + * \ref tdes.c\n + * \ref tdes.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * Implementation of Triple Data Encryption Standard (TDES). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Starts Manual encryption/decryption process. + */ +void TDES_Start(void) +{ + TDES->TDES_CR = TDES_CR_START; +} + +/** + * \brief Resets the TDES. A software triggered hardware reset of the TDES interface is performed. + */ +void TDES_SoftReset(void) +{ + TDES->TDES_CR = TDES_CR_SWRST; +} + +/** + * \brief Restarts the countermeasures generator to an internal pre-defined value. + */ +void TDES_Recount(void) +{ + TDES->TDES_CR = TDES_CR_LOADSEED; +} + +/** + * \brief Configures an TDES peripheral with the specified parameters. + * \param mode Desired value for the TDES mode register (see the datasheet). + */ +void TDES_Configure(uint32_t mode) +{ + TDES->TDES_MR = mode; +} + +/** + * \brief Enables the selected interrupts sources on a TDES peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void TDES_EnableIt(uint32_t sources) +{ + TDES->TDES_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a TDES peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void TDES_DisableIt(uint32_t sources) +{ + TDES->TDES_IDR = sources; +} + +/** + * \brief Get the current status register of the given TDES peripheral. + * \return TDES status register. + */ +uint32_t TDES_GetStatus(void) +{ + return TDES->TDES_ISR; +} + +/** + * \brief Set KEY1. + * \param keyword0 key word 0 + * \param keyword0 key word 1 + */ +void TDES_WriteKey1(uint32_t keyword0, uint32_t keyword1) +{ + TDES->TDES_KEY1WR[0] = keyword0; + TDES->TDES_KEY1WR[1] = keyword1; +} + +/** + * \brief Set KEY2. + * \param keyword0 key word 0 + * \param keyword0 key word 1 + */ +void TDES_WriteKey2(uint32_t keyword0, uint32_t keyword1) +{ + TDES->TDES_KEY2WR[0] = keyword0; + TDES->TDES_KEY2WR[1] = keyword1; +} + +/** + * \brief Set KEY3. + * \param keyword0 key word 0 + * \param keyword0 key word 1 + */ +void TDES_WriteKey3(uint32_t keyword0, uint32_t keyword1) +{ + TDES->TDES_KEY3WR[0] = keyword0; + TDES->TDES_KEY3WR[1] = keyword1; +} + +/** + * \brief Set the two 32-bit input Data allow to set the 64-bit data block used for encryption/decryption. + * \param data0 corresponds to the first word of the data to be encrypted/decrypted + * \param data1 corresponds to the last word of the data to be encrypted/decrypted + */ +void TDES_SetInput(uint32_t data0, uint32_t data1) +{ + TDES->TDES_IDATAR[0] = data0; + TDES->TDES_IDATAR[1] = data1; +} + +/** + * \brief Get the two 32-bit data contain the 64-bit data block which has been encrypted/decrypted. + * \param data0 point to the first word. + * \param data1 point to the last word. + */ +void TDES_GetOutput(uint32_t *data0, uint32_t *data1) +{ + *data0 = TDES->TDES_ODATAR[0]; + *data1 = TDES->TDES_ODATAR[1]; +} + +/** + * \brief Set the 64-bit initialization vector data block, which is used by some + * modes of operation as an additional initial input. + * \param v0 corresponds to the first word of the initialization vector. + * \param v1 corresponds to the last word of the initialization vector. + */ +void TDES_SetVector(uint32_t v0, uint32_t v1) +{ + TDES->TDES_IVR[0] = v0; + TDES->TDES_IVR[1] = v1; +} + +/** + * \brief Set the 6-bit complete rounds. + * \param rounds corresponds to rounds+1 complete round. + */ +void TDES_SetXteaRounds(uint32_t rounds) +{ + TDES->TDES_XTEARNDR = rounds; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/trng.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/trng.c new file mode 100644 index 000000000..12d7ea9c0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/trng.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup rtng_module Working with RTNG + * \ingroup peripherals_module + * The TRNG driver provides the interface to configure and use the TRNG peripheral. + * \n + * + * The True Random Number Generator (TRNG) passes the American NIST Special Publication + * 800-22 and Diehard Random Tests Suites. As soon as the TRNG is enabled (TRNG_Enable()), + * the generator provides one 32-bit value every 84 clock cycles. + * Interrupt trng_int can be enabled through TRNG_EnableIt()(respectively disabled in TRNG_IDR). + * This interrupt is set when a new random value is available and is cleared when the status + * register is read (TRNG_SR register). The flag DATRDY of the status register (TRNG_ISR) is set + * when the random data is ready to be read out on the 32-bit output data through TRNG_GetRandData(). + * + * For more accurate information, please look at the SHA section of the + * Datasheet. + * + * Related files :\n + * \ref trng.c\n + * \ref trng.h\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of True Random Number Generator (TRNG) + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables the TRNG to provide Random Values. + * \param key This key is to be written when the ENABLE bit is set. + */ +void TRNG_Enable(uint32_t key) +{ + TRNG->TRNG_CR = TRNG_CR_ENABLE | TRNG_CR_KEY(key); +} + +/** + * \brief Disables the TRNG to provide Random Values. + * \param key This key is to be written when the DISABLE bit is set. + */ +void TRNG_Disable(uint32_t key) +{ + TRNG->TRNG_CR = TRNG_CR_KEY(key); +} + +/** + * \brief Data Ready Interrupt enable. + */ +void TRNG_EnableIt(void) +{ + TRNG->TRNG_IER = TRNG_IER_DATRDY; +} + +/** + * \brief Data Ready Interrupt Disable. + */ +void TRNG_DisableIt(void) +{ + TRNG->TRNG_IDR = TRNG_IDR_DATRDY; +} + +/** + * \brief Get the current status register of the given TRNG peripheral. + * \return TRNG status register. + */ +uint32_t TRNG_GetStatus(void) +{ + return TRNG->TRNG_ISR; +} + +/** + * \brief Get the 32-bit Output Data from TRNG peripheral. + * \return TRNG output data. + */ +uint32_t TRNG_GetRandData(void) +{ + return TRNG->TRNG_ODATA; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/twi.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/twi.c new file mode 100644 index 000000000..983e8efc9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/twi.c @@ -0,0 +1,386 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup twi_module Working with TWI + * The TWI driver provides the interface to configure and use the TWI + * peripheral. + * + * \section Usage + *
    + *
  • Configures a TWI peripheral to operate in master mode, at the given + * frequency (in Hz) using TWI_Configure().
    • + *
  • Sends a STOP condition on the TWI using TWI_Stop().
    • + *
  • Starts a read operation on the TWI bus with the specified slave using + * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever + * a byte is available (poll using TWI_ByteReceived()).
    • + *
  • Starts a write operation on the TWI to access the selected slave using + * TWI_StartWrite(). A byte of data must be provided to start the write; + * other bytes are written next.
    • + *
  • Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte(). + * This function must be called once before TWI_StartWrite() with the first byte of data + * to send, then it shall be called repeatedly after that to send the remaining bytes.
    • + *
  • Check if a byte has been received and can be read on the given TWI + * peripheral using TWI_ByteReceived().< + * Check if a byte has been sent using TWI_ByteSent().
    • + *
  • Check if the current transmission is complete (the STOP has been sent) + * using TWI_TransferComplete().
    • + *
  • Enables & disable the selected interrupts sources on a TWI peripheral + * using TWI_EnableIt() and TWI_DisableIt().
    • + *
  • Get current status register of the given TWI peripheral using + * TWI_GetStatus(). Get current status register of the given TWI peripheral, but + * masking interrupt sources which are not currently enabled using + * TWI_GetMaskedStatus().
    • + *
+ * For more accurate information, please look at the TWI section of the + * Datasheet. + * + * Related files :\n + * \ref twi.c\n + * \ref twi.h.\n +*/ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of Two Wire Interface (TWI). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a TWI peripheral to operate in master mode, at the given + * frequency (in Hz). The duty cycle of the TWI clock is set to 50%. + * \param pTwi Pointer to an Twi instance. + * \param twck Desired TWI clock frequency. + * \param mck Master clock frequency. + */ +void TWI_ConfigureMaster( Twi* pTwi, uint32_t dwTwCk, uint32_t dwMCk ) +{ + uint32_t dwCkDiv = 0 ; + uint32_t dwClDiv ; + uint32_t dwOk = 0 ; + uint32_t id = ID_TWI0; + uint32_t maxClock; + + TRACE_DEBUG( "TWI_ConfigureMaster()\n\r" ) ; + assert( pTwi ) ; + + /* SVEN: TWI Slave Mode Enabled */ + pTwi->TWI_CR = TWI_CR_SVEN ; + /* Reset the TWI */ + pTwi->TWI_CR = TWI_CR_SWRST ; + pTwi->TWI_RHR ; + + /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */ + pTwi->TWI_CR = TWI_CR_SVDIS ; + pTwi->TWI_CR = TWI_CR_MSDIS ; + + /* Set master mode */ + pTwi->TWI_CR = TWI_CR_MSEN ; + if ((uint32_t)pTwi == (uint32_t)TWI0) id = ID_TWI0; + else if ((uint32_t)pTwi == (uint32_t)TWI1) id = ID_TWI1; + else if ((uint32_t)pTwi == (uint32_t)TWI2) id = ID_TWI2; + + maxClock = PMC_SetPeriMaxClock(id, dwMCk); + + /* Configure clock */ + while ( !dwOk ) + { + dwClDiv = ((maxClock / (2 * dwTwCk)) - 8) / (1<TWI_CWGR = 0 ; + pTwi->TWI_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv ; +} + +/** + * \brief Configures a TWI peripheral to operate in slave mode. + * \param pTwi Pointer to an Twi instance. + * \param slaveAddress Slave address. + */ +void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress) +{ + uint32_t i; + + /* TWI software reset */ + pTwi->TWI_CR = TWI_CR_SWRST; + pTwi->TWI_RHR; + + /* Wait at least 10 ms */ + for (i=0; i < 1000000; i++); + + /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/ + pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS; + + /* Configure slave address. */ + pTwi->TWI_SMR = 0; + pTwi->TWI_SMR = TWI_SMR_SADR(slaveAddress); + + /* SVEN: TWI Slave Mode Enabled */ + pTwi->TWI_CR = TWI_CR_SVEN; + + /* Wait at least 10 ms */ + for (i=0; i < 1000000; i++); + assert( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS ) ; +} + +/** + * \brief Sends a STOP condition on the TWI. + * \param pTwi Pointer to an Twi instance. + */ +void TWI_Stop( Twi *pTwi ) +{ + assert( pTwi != NULL ) ; + + pTwi->TWI_CR = TWI_CR_STOP; +} + +/** + * \brief Starts a read operation on the TWI bus with the specified slave, it returns + * immediately. Data must then be read using TWI_ReadByte() whenever a byte is + * available (poll using TWI_ByteReceived()). + * \param pTwi Pointer to an Twi instance. + * \param address Slave address on the bus. + * \param iaddress Optional internal address bytes. + * \param isize Number of internal address bytes. + */ +void TWI_StartRead( + Twi *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize) +{ + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Set slave address and number of internal address bytes. */ + pTwi->TWI_MMR = 0; + pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16); + + /* Set internal address bytes */ + pTwi->TWI_IADR = 0; + pTwi->TWI_IADR = iaddress; + + /* Send START condition */ + pTwi->TWI_CR = TWI_CR_START; +} + +/** + * \brief Reads a byte from the TWI bus. The read operation must have been started + * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()). + * \param pTwi Pointer to an Twi instance. + * \return byte read. + */ +uint8_t TWI_ReadByte(Twi *pTwi) +{ + assert( pTwi != NULL ) ; + + return pTwi->TWI_RHR; +} + +/** + * \brief Sends a byte of data to one of the TWI slaves on the bus. + * \note This function must be called once before TWI_StartWrite() with + * the first byte of data to send, then it shall be called repeatedly + * after that to send the remaining bytes. + * \param pTwi Pointer to an Twi instance. + * \param byte Byte to send. + */ +void TWI_WriteByte(Twi *pTwi, uint8_t byte) +{ + assert( pTwi != NULL ) ; + + pTwi->TWI_THR = byte; +} + +/** + * \brief Starts a write operation on the TWI to access the selected slave, then + * returns immediately. A byte of data must be provided to start the write; + * other bytes are written next. + * after that to send the remaining bytes. + * \param pTwi Pointer to an Twi instance. + * \param address Address of slave to acccess on the bus. + * \param iaddress Optional slave internal address. + * \param isize Number of internal address bytes. + * \param byte First byte to send. + */ +void TWI_StartWrite( + Twi *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte) +{ + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Set slave address and number of internal address bytes. */ + pTwi->TWI_MMR = 0; + pTwi->TWI_MMR = (isize << 8) | (address << 16); + + /* Set internal address bytes. */ + pTwi->TWI_IADR = 0; + pTwi->TWI_IADR = iaddress; + + /* Write first byte to send.*/ + TWI_WriteByte(pTwi, byte); +} + +/** + * \brief Check if a byte have been receiced from TWI. + * \param pTwi Pointer to an Twi instance. + * \return 1 if a byte has been received and can be read on the given TWI + * peripheral; otherwise, returns 0. This function resets the status register. + */ +uint8_t TWI_ByteReceived(Twi *pTwi) +{ + return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY); +} + +/** + * \brief Check if a byte have been sent to TWI. + * \param pTwi Pointer to an Twi instance. + * \return 1 if a byte has been sent so another one can be stored for + * transmission; otherwise returns 0. This function clears the status register. + */ +uint8_t TWI_ByteSent(Twi *pTwi) +{ + return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY); +} + +/** + * \brief Check if current transmission is complet. + * \param pTwi Pointer to an Twi instance. + * \return 1 if the current transmission is complete (the STOP has been sent); + * otherwise returns 0. + */ +uint8_t TWI_TransferComplete(Twi *pTwi) +{ + return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP); +} + +/** + * \brief Enables the selected interrupts sources on a TWI peripheral. + * \param pTwi Pointer to an Twi instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void TWI_EnableIt(Twi *pTwi, uint32_t sources) +{ + assert( pTwi != NULL ) ; + assert( (sources & 0xFFFFF088) == 0 ) ; + + pTwi->TWI_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a TWI peripheral. + * \param pTwi Pointer to an Twi instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void TWI_DisableIt(Twi *pTwi, uint32_t sources) +{ + assert( pTwi != NULL ) ; + assert( (sources & 0xFFFFF088) == 0 ) ; + + pTwi->TWI_IDR = sources; +} + +/** + * \brief Get the current status register of the given TWI peripheral. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param pTwi Pointer to an Twi instance. + * \return TWI status register. + */ +uint32_t TWI_GetStatus(Twi *pTwi) +{ + assert( pTwi != NULL ) ; + + return pTwi->TWI_SR; +} + +/** + * \brief Returns the current status register of the given TWI peripheral, but + * masking interrupt sources which are not currently enabled. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param pTwi Pointer to an Twi instance. + */ +uint32_t TWI_GetMaskedStatus(Twi *pTwi) +{ + uint32_t status; + + assert( pTwi != NULL ) ; + + status = pTwi->TWI_SR; + status &= pTwi->TWI_IMR; + + return status; +} + +/** + * \brief Sends a STOP condition. STOP Condition is sent just after completing + * the current byte transmission in master read mode. + * \param pTwi Pointer to an Twi instance. + */ +void TWI_SendSTOPCondition(Twi *pTwi) +{ + assert( pTwi != NULL ) ; + + pTwi->TWI_CR |= TWI_CR_STOP; +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/twid.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/twid.c new file mode 100644 index 000000000..709eda9cd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/twid.c @@ -0,0 +1,411 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define TWITIMEOUTMAX 0xfffff + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** TWI driver callback function.*/ +typedef void (*TwiCallback)(Async *); + +/** \brief TWI asynchronous transfer descriptor.*/ +typedef struct _AsyncTwi { + + /** Asynchronous transfer status. */ + volatile uint32_t status; + // Callback function to invoke when transfer completes or fails.*/ + TwiCallback callback; + /** Pointer to the data buffer.*/ + uint8_t *pData; + /** Total number of bytes to transfer.*/ + uint32_t num; + /** Number of already transferred bytes.*/ + uint32_t transferred; + +} AsyncTwi; + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes a TWI driver instance, using the given TWI peripheral. + * \note The peripheral must have been initialized properly before calling this function. + * \param pTwid Pointer to the Twid instance to initialize. + * \param pTwi Pointer to the TWI peripheral to use. + */ +void TWID_Initialize(Twid *pTwid, Twi *pTwi) +{ + TRACE_DEBUG( "TWID_Initialize()\n\r" ) ; + assert( pTwid != NULL ) ; + assert( pTwi != NULL ) ; + + /* Initialize driver. */ + pTwid->pTwi = pTwi; + pTwid->pTransfer = 0; +} + + +/** + * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer + * occuring on the bus. This function MUST be called by the interrupt service + * routine of the TWI peripheral if asynchronous read/write are needed. + * \param pTwid Pointer to a Twid instance. + */ +void TWID_Handler( Twid *pTwid ) +{ + uint32_t status; + AsyncTwi *pTransfer ; + Twi *pTwi ; + + assert( pTwid != NULL ) ; + + pTransfer = (AsyncTwi*)pTwid->pTransfer ; + assert( pTransfer != NULL ) ; + pTwi = pTwid->pTwi ; + assert( pTwi != NULL ) ; + + /* Retrieve interrupt status */ + status = TWI_GetMaskedStatus(pTwi); + + /* Byte received */ + if (TWI_STATUS_RXRDY(status)) { + + pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi); + pTransfer->transferred++; + + /* check for transfer finish */ + if (pTransfer->transferred == pTransfer->num) { + + TWI_DisableIt(pTwi, TWI_IDR_RXRDY); + TWI_EnableIt(pTwi, TWI_IER_TXCOMP); + } + /* Last byte? */ + else if (pTransfer->transferred == (pTransfer->num - 1)) { + + TWI_Stop(pTwi); + } + } + /* Byte sent*/ + else if (TWI_STATUS_TXRDY(status)) { + + /* Transfer finished ? */ + if (pTransfer->transferred == pTransfer->num) { + + TWI_DisableIt(pTwi, TWI_IDR_TXRDY); + TWI_EnableIt(pTwi, TWI_IER_TXCOMP); + TWI_SendSTOPCondition(pTwi); + } + /* Bytes remaining */ + else { + + TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]); + pTransfer->transferred++; + } + } + /* Transfer complete*/ + else if (TWI_STATUS_TXCOMP(status)) { + + TWI_DisableIt(pTwi, TWI_IDR_TXCOMP); + pTransfer->status = 0; + if (pTransfer->callback) { + pTransfer->callback((Async *)(void*) pTransfer); + } + pTwid->pTransfer = 0; + } +} + +/** + * \brief Asynchronously reads data from a slave on the TWI bus. An optional + * callback function is triggered when the transfer is complete. + * \param pTwid Pointer to a Twid instance. + * \param address TWI slave address. + * \param iaddress Optional slave internal address. + * \param isize Internal address size in bytes. + * \param pData Data buffer for storing received bytes. + * \param num Number of bytes to read. + * \param pAsync Asynchronous transfer descriptor. + * \return 0 if the transfer has been started; otherwise returns a TWI error code. + */ +uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync) +{ + Twi *pTwi; + AsyncTwi *pTransfer; + uint32_t timeout = 0; + uint32_t i = 0; + uint32_t status; + + assert( pTwid != NULL ) ; + pTwi = pTwid->pTwi; + pTransfer = (AsyncTwi *) pTwid->pTransfer; + + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Check that no transfer is already pending*/ + if (pTransfer) { + + TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); + return TWID_ERROR_BUSY; + } + + /* Asynchronous transfer*/ + if (pAsync) { + + /* Update the transfer descriptor */ + pTwid->pTransfer = pAsync; + pTransfer = (AsyncTwi *) pAsync; + pTransfer->status = ASYNC_STATUS_PENDING; + pTransfer->pData = pData; + pTransfer->num = num; + pTransfer->transferred = 0; + + /* Enable read interrupt and start the transfer */ + TWI_EnableIt(pTwi, TWI_IER_RXRDY); + TWI_StartRead(pTwi, address, iaddress, isize); + } + /* Synchronous transfer*/ + else { + + /* Start read*/ + TWI_StartRead(pTwi, address, iaddress, isize); + if (num != 1) + { + status = TWI_GetStatus(pTwi); + + if(status & TWI_SR_NACK) + TRACE_ERROR("TWID NACK error\n\r"); + timeout = 0; + while( ! (status & TWI_SR_RXRDY) && (++timeout 0) { + + /* Last byte ?*/ + if (num == 1) { + + TWI_Stop(pTwi); + } + + /* Wait for byte then read and store it*/ + timeout = 0; + while( !TWI_ByteReceived(pTwi) && (++timeoutpTwi; + AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; + uint32_t timeout = 0; + uint32_t status; + uint8_t singleTransfer = 0; + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + if(num == 1) singleTransfer = 1; + /* Check that no transfer is already pending */ + if (pTransfer) { + + TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); + return TWID_ERROR_BUSY; + } + + /* Asynchronous transfer */ + if (pAsync) { + + /* Update the transfer descriptor */ + pTwid->pTransfer = pAsync; + pTransfer = (AsyncTwi *) pAsync; + pTransfer->status = ASYNC_STATUS_PENDING; + pTransfer->pData = pData; + pTransfer->num = num; + pTransfer->transferred = 1; + + /* Enable write interrupt and start the transfer */ + TWI_StartWrite(pTwi, address, iaddress, isize, *pData); + TWI_EnableIt(pTwi, TWI_IER_TXRDY); + } + /* Synchronous transfer*/ + else { + + // Start write + TWI_StartWrite(pTwi, address, iaddress, isize, *pData++); + num--; + if (singleTransfer) { + /* Send a STOP condition */ + TWI_SendSTOPCondition(pTwi); + } + status = TWI_GetStatus(pTwi); + + if(status & TWI_SR_NACK) + TRACE_ERROR("TWID NACK error\n\r"); + while( !(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX) ) + { + status = TWI_GetStatus(pTwi); + } + if (timeout == TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout BS\n\r"); + } + timeout = 0; + /* Send all bytes */ + while (num > 0) { + + /* Wait before sending the next byte */ + timeout = 0; + TWI_WriteByte(pTwi, *pData++); + status = TWI_GetStatus(pTwi); + + if(status & TWI_SR_NACK) + TRACE_ERROR("TWID NACK error\n\r"); + while( !(status & TWI_SR_TXRDY) && (timeout++ < TWITIMEOUTMAX) ) + { + status = TWI_GetStatus(pTwi); + } + if (timeout == TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout BS\n\r"); + } + + + num--; + } + + /* Wait for actual end of transfer */ + timeout = 0; + if (!singleTransfer) { + /* Send a STOP condition */ + TWI_SendSTOPCondition(pTwi); + } + while( !TWI_TransferComplete(pTwi) && (++timeout + *
  • Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by: + * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register).
    • + * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) + * -# Setting baudrate which is different from mode to mode. + + *
  • Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.
    • + *
  • Read from or write to the peripheral with \ref dmad_module
    • + * + * + * For more accurate information, please look at the USART section of the + * Datasheet. + * + * Related files :\n + * \ref usart.c\n + * \ref usart.h\n +*/ + + + +/** + * \file + * + * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter) + * controller. + * + */ +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +/** + * \brief Configures an USART peripheral with the specified parameters. + * + * + * \param usart Pointer to the USART peripheral to configure. + * \param mode Desired value for the USART mode register (see the datasheet). + * \param baudrate Baudrate at which the USART should operate (in Hz). + * \param masterClock Frequency of the system master clock (in Hz). + */ +void USART_Configure(Usart *usart, + uint32_t mode, + uint32_t baudrate, + uint32_t masterClock) +{ + uint32_t maxClock; + uint32_t id = ID_USART0; + maxClock = masterClock; + /* Reset and disable receiver & transmitter*/ + usart->US_CR = US_CR_RSTRX | US_CR_RSTTX + | US_CR_RXDIS | US_CR_TXDIS; + if ((uint32_t)usart == (uint32_t)USART0) id = ID_USART0; + else if ((uint32_t)usart == (uint32_t)USART1) id = ID_USART1; + else if ((uint32_t)usart == (uint32_t)USART2) id = ID_USART2; + else if ((uint32_t)usart == (uint32_t)USART3) id = ID_USART3; + /* Configure mode*/ + usart->US_MR = mode; + maxClock = PMC_SetPeriMaxClock(id, masterClock); + /* Configure baudrate*/ + /* Asynchronous, no oversampling*/ + if (((mode & US_MR_SYNC) == 0) + && ((mode & US_MR_OVER) == 0)) + { + usart->US_BRGR = (maxClock / baudrate) / 16; + } + if( ((mode & US_MR_USART_MODE_SPI_MASTER) == US_MR_USART_MODE_SPI_MASTER) + || ((mode & US_MR_SYNC) == US_MR_SYNC)) + { + if( (mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK) + { + usart->US_BRGR = maxClock / baudrate; + } + else + { + if ( (mode & US_MR_USCLKS_DIV) == US_MR_USCLKS_DIV) + { + usart->US_BRGR = maxClock / baudrate / 8; + } + } + } + /* TODO other modes*/ +} +/** + * \brief Enables or disables the transmitter of an USART peripheral. + * + * + * \param usart Pointer to an USART peripheral + * \param enabled If true, the transmitter is enabled; otherwise it is + * disabled. + */ +void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled) +{ + if (enabled) { + + usart->US_CR = US_CR_TXEN; + } + else { + + usart->US_CR = US_CR_TXDIS; + } +} + +/** + * \brief Enables or disables the receiver of an USART peripheral + * + * + * \param usart Pointer to an USART peripheral + * \param enabled If true, the receiver is enabled; otherwise it is disabled. + */ +void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled) +{ + if (enabled) { + + usart->US_CR = US_CR_RXEN; + } + else { + + usart->US_CR = US_CR_RXDIS; + } +} + +/** + * \brief Enables or disables the Request To Send (RTS) of an USART peripheral + * + * + * \param usart Pointer to an USART peripheral + * \param enabled If true, the RTS is enabled (0); otherwise it is disabled. + */ +void USART_SetRTSEnabled( Usart *usart, uint8_t enabled) +{ + if (enabled) { + + usart->US_CR = US_CR_RTSEN; + } + else { + + usart->US_CR = US_CR_RTSDIS; + } +} + +/** + * \brief Sends one packet of data through the specified USART peripheral. This + * function operates synchronously, so it only returns when the data has been + * actually sent. + * + * + * \param usart Pointer to an USART peripheral. + * \param data Data to send including 9nth bit and sync field if necessary (in + * the same format as the US_THR register in the datasheet). + * \param timeOut Time out value (0 = no timeout). + */ +void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut) +{ + if (timeOut == 0) { + + while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); + } + else { + + while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) { + + if (timeOut == 0) { + + TRACE_ERROR("USART_Write: Timed out.\n\r"); + return; + } + timeOut--; + } + } + + usart->US_THR = data; +} + + +/** + * \brief Reads and return a packet of data on the specified USART peripheral. This + * function operates asynchronously, so it waits until some data has been + * received. + * + * \param usart Pointer to an USART peripheral. + * \param timeOut Time out value (0 -> no timeout). + */ +uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut) +{ + if (timeOut == 0) { + + while ((usart->US_CSR & US_CSR_RXRDY) == 0); + } + else { + + while ((usart->US_CSR & US_CSR_RXRDY) == 0) { + + if (timeOut == 0) { + + TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ; + return 0; + } + timeOut--; + } + } + + return usart->US_RHR; +} + +/** + * \brief Returns 1 if some data has been received and can be read from an USART; + * otherwise returns 0. + * + * \param usart Pointer to an Usart instance. + */ +uint8_t USART_IsDataAvailable(Usart *usart) +{ + if ((usart->US_CSR & US_CSR_RXRDY) != 0) { + + return 1; + } + else { + + return 0; + } +} + +/** + * \brief Sets the filter value for the IRDA demodulator. + * + * \param pUsart Pointer to an Usart instance. + * \param filter Filter value. + */ +void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter) +{ + assert( pUsart != NULL ) ; + + pUsart->US_IF = filter; +} + +/** + * \brief Sends one packet of data through the specified USART peripheral. This + * function operates synchronously, so it only returns when the data has been + * actually sent. + * + * \param usart Pointer to an USART peripheral. + * \param c Character to send + */ +void USART_PutChar( Usart *usart, uint8_t c) +{ + /* Wait for the transmitter to be ready*/ + while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); + + /* Send character*/ + usart->US_THR = c; + + /* Wait for the transfer to complete*/ + while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); +} + +/** + * \brief Return 1 if a character can be read in USART + * \param usart Pointer to an USART peripheral. + */ +uint32_t USART_IsRxReady(Usart *usart) +{ + return (usart->US_CSR & US_CSR_RXRDY); +} + +/** + * \brief Get present status + * \param usart Pointer to an USART peripheral. + */ +uint32_t USART_GetStatus(Usart *usart) +{ + return usart->US_CSR; +} + +/** + * \brief Enable interrupt + * \param usart Pointer to an USART peripheral. + * \param mode Interrupt mode. + */ +void USART_EnableIt(Usart *usart,uint32_t mode) +{ + usart->US_IER = mode; +} + +/** + * \brief Disable interrupt + * \param usart Pointer to an USART peripheral. + * \param mode Interrupt mode. + */ +void USART_DisableIt(Usart *usart,uint32_t mode) +{ + usart->US_IDR = mode; +} + +/** + * \brief Return interrupt mask + * \param usart Pointer to an USART peripheral. + */ +uint32_t USART_GetItMask(Usart *usart) +{ + return usart->US_IMR; +} + +/** + * \brief Reads and returns a character from the USART. + * + * \note This function is synchronous (i.e. uses polling). + * \param usart Pointer to an USART peripheral. + * \return Character received. + */ +uint8_t USART_GetChar(Usart *usart) +{ + while ((usart->US_CSR & US_CSR_RXRDY) == 0); + return usart->US_RHR; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/video.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/video.c new file mode 100644 index 000000000..468ac938a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/video.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS uint32_tERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +//----------------------------------------------------------------------------- +/// Conversion YCrCb to RGB:
    +/// R = 1.164(Yi ?16) + 1.596(Cr ?128)
    +/// G = 1.164(Yi ?16) ?0.813(Cr ?128) ?0.391(Cb ?128)
    +/// B = 1.164(Yi ?16) + 2.018(Cb ?128)
    +/// +/// Pixel i+1:
    +/// YCrCb to RGB:
    +/// R = 1.164(Yi+1 ?16) + 1.596(Cr ?128)
    +/// G = 1.164(Yi+1 ?16) ?0.813(Cr ?128) ?0.391(Cb ?128)
    +/// B = 1.164(Yi+1 ?16) + 2.018(Cb ?128) +/// \param ycc Source buffer (YCC) +/// \param rgb Destination buffer (RGB) +/// \param len Length of buffer +//----------------------------------------------------------------------------- +void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len) +{ + int32_t r_calc_i; + int32_t g_calc_i; + int32_t b_calc_i; + int32_t r_calc_i_incr; + int32_t g_calc_i_incr; + int32_t b_calc_i_incr; + int32_t cr_i; + int32_t y_i; + int32_t cb_i; + int32_t y_i_incr; + int32_t val; + int32_t val1; + int32_t val2; + int32_t val3; + int32_t val4; + int32_t val5; + uint32_t i; + + for(i = 0; i < len; i++) + { +#if 1 + cb_i = (int32_t)ycc[4*i]; + y_i = (int32_t )ycc[4*i+1]; + cr_i = (int32_t )ycc[4*i+2]; + y_i_incr =(int32_t )ycc[4*i+3]; +#endif + val = 1164*(y_i-16); + val1 = 1164*(y_i_incr-16); + val2 = 1596*(cr_i- 128); + val3 = 813*(cb_i-128); + val4 = 392*(cr_i-128); + val5 = 2017*(cb_i-128); + + r_calc_i = (val + val2)/1000; + g_calc_i = (val - val3 - val4)/1000; + b_calc_i = (val + val5)/1000; + r_calc_i_incr = (val1 + val2)/1000; + g_calc_i_incr = (val1 - val3 - val4)/1000; + b_calc_i_incr = (val1 + val5)/1000; + + if (r_calc_i < 0) + r_calc_i = 0; + else if (r_calc_i > 255) + r_calc_i = 255; + + if (g_calc_i < 0) + g_calc_i = 0; + else if (g_calc_i > 255) + g_calc_i = 255; + + if (b_calc_i < 0) + b_calc_i = 0; + else if (b_calc_i > 255) + b_calc_i = 255; + + if (r_calc_i_incr < 0) + r_calc_i_incr = 0; + else if (r_calc_i_incr > 255) + r_calc_i_incr = 255; + + if (g_calc_i_incr < 0) + g_calc_i_incr = 0; + else if (g_calc_i_incr > 255) + g_calc_i_incr = 255; + + if (b_calc_i_incr < 0) + b_calc_i_incr = 0; + else if (b_calc_i_incr > 255) + b_calc_i_incr = 255; + //R1[4:0] G1[5:0] B1[4:0] R0[4:0] G0[5:0] B0[4:0] + *rgb++ = (((uint16_t )b_calc_i & 0xF8) >> 3) + | ((((uint16_t)g_calc_i & 0xFC) >> 2) << 5) + | ((((uint16_t)r_calc_i & 0xF8) >> 3) << 11); + + *rgb++ = (((uint16_t )b_calc_i_incr & 0xF8) >> 3) + | ((((uint16_t)g_calc_i_incr & 0xFC) >> 2) << 5) + | ((((uint16_t)r_calc_i_incr & 0xF8) >> 3) << 11); + } +} + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/wdt.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/wdt.c new file mode 100644 index 000000000..ffb8a4906 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/AtmelFiles/libchip_sama5d3x/source/wdt.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of Watchdog Timer (WDT) controller. + * + */ + +/** \addtogroup wdt_module Working with WDT + * The WDT driver provides the interface to configure and use the WDT + * peripheral. + * + * The WDT can be used to prevent system lock-up if the software becomes + * trapped in a deadlock. It can generate a general reset or a processor + * reset only. It is clocked by slow clock divided by 128. + * + * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz) + * and external reset generation enabled. The user must either disable it or + * reprogram it to meet the application requires. + * + * To use the WDT, the user could follow these few steps: + *
      + *
    • Enable watchdog with given mode using \ref WDT_Enable(). + *
    • Restart the watchdog using \ref WDT_Restart() within the watchdog period. + *
    + * + * For more accurate information, please look at the WDT section of the + * Datasheet. + * + * \note + * The Watchdog Mode Register (WDT_MR) can be written only once.\n + * + * Related files :\n + * \ref wdt.c\n + * \ref wdt.h.\n + */ +/*@{*/ +/*@}*/ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enable watchdog with given mode. + * + * \note The Watchdog Mode Register (WDT_MR) can be written only once. + * Only a processor reset resets it. + * + * \param dwMode WDT mode to be set + */ +extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) +{ + pWDT->WDT_MR = dwMode ; +} + +/** + * \brief Disable watchdog. + * + * \note The Watchdog Mode Register (WDT_MR) can be written only once. + * Only a processor reset resets it. + */ +extern void WDT_Disable( Wdt* pWDT ) +{ + pWDT->WDT_MR = WDT_MR_WDDIS; +} + +/** + * \brief Watchdog restart. + */ +extern void WDT_Restart( Wdt* pWDT ) +{ + pWDT->WDT_CR = 0xA5000001; +} + +/** + * \brief Watchdog get status. + */ +extern uint32_t WDT_GetStatus( Wdt* pWDT ) +{ + return (pWDT->WDT_SR & 0x3) ; +} + +/** + * \brief Watchdog get period. + * + * \param dwMs desired watchdog period in millisecond. + */ +extern uint32_t WDT_GetPeriod( uint32_t dwMs ) +{ + if ( (dwMs < 4) || (dwMs > 16000) ) + { + return 0 ; + } + return ((dwMs << 8) / 1000) ; +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..55c34e7f5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOSConfig.h @@ -0,0 +1,202 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* + * The FreeRTOS Cortex-A port implements a full interrupt nesting model. + * + * Interrupts that are assigned a priority at or below + * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM + * generic interrupt controller [GIC] means a priority that has a numerical + * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API + * functions and will nest. + * + * Interrupts that are assigned a priority above + * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical + * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS + * API functions, will nest, and will not be masked by FreeRTOS critical + * sections (although it is necessary for interrupts to be globally disabled + * extremely briefly as the interrupt mask is updated in the GIC). + * + * FreeRTOS functions that can be called from an interrupt are those that end in + * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable + * interrupt entry to be shorter, faster, simpler and smaller. + */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 25 + + +#define configCPU_CLOCK_HZ 100000000UL +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configPERIPHERAL_CLOCK_HZ ( 33333000UL ) +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 160 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38912 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Prevent C code being included in assembly files when the IAR compiler is +used. */ +#ifndef __IASMARM__ + /* Run time stats gathering definitions. */ + unsigned long ulGetRunTimeCounterValue( void ); + void vInitialiseRunTimeStats( void ); + + #define configGENERATE_RUN_TIME_STATS 0 +// #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseRunTimeStats() +// #define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue() + + /* The size of the global output buffer that is available for use when there + are multiple command interpreters running at once (for example, one on a UART + and one on TCP/IP). This is done to prevent an output buffer being defined by + each implementation - which would waste RAM. In this case, there is only one + command interpreter running. */ + #define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 + + /* Normal assert() semantics without relying on the provision of an assert.h + header file. */ + void vAssertCalled( const char * pcFile, unsigned long ulLine ); + #define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); + + + + /****** Hardware specific settings. *******************************************/ + + /* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ + void vConfigureTickInterrupt( void ); + #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() +#endif /* __IASMARM__ */ + +/* The following constants describe the hardware, and are correct for the +Atmel SAMA5 MPU. */ +#define configINTERRUPT_CONTROLLER_BASE_ADDRESS 0xE8201000 +#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET 0x1000 +#define configUNIQUE_INTERRUPT_PRIORITIES 32 + +/* Map the FreeRTOS IRQ and SVC/SWI handlers to the names used in the C startup +code (which is where the vector table is defined). */ +#define FreeRTOS_IRQ_Handler IRQ_Handler +#define FreeRTOS_SWI_Handler SWI_Handler + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c new file mode 100644 index 000000000..cdde1261f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/FreeRTOS_tick_config.c @@ -0,0 +1,97 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "Task.h" + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Atmel SAMA5. + */ +void vConfigureTickInterrupt( void ) +{ +#warning Needs implementing. +} +/*-----------------------------------------------------------*/ +void vApplicationIRQHandler( uint32_t ulICCIAR ); +void vApplicationIRQHandler( uint32_t ulICCIAR ) +{ +uint32_t ulInterruptID; + + /* Re-enable interrupts. */ + __asm ( "cpsie i" ); + + /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value + with 0x3FF. */ + ulInterruptID = ulICCIAR & 0x3FFUL; + +#warning Needs implementing. +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c new file mode 100644 index 000000000..1922b0d0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/LEDs.c @@ -0,0 +1,96 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + * This file is called ParTest.c for historic reasons. Originally it stood for + * PARallel port TEST. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue ) +{ +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..f5a8a5ee4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewd @@ -0,0 +1,1352 @@ + + + + 2 + + sram + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + 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$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..282b86765 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.ewp @@ -0,0 +1,1058 @@ + + + + 2 + + sram + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 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+ $PROJ_DIR$\AtmelFiles\libchip_sama5d3x\source\tc.c + + + $PROJ_DIR$\AtmelFiles\libchip_sama5d3x\source\wdt.c + + + + + FreeRTOS Source + + portable + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA9\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CA9\portASM.s + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + $PROJ_DIR$\atmel_main.c + + + $PROJ_DIR$\FreeRTOS_tick_config.c + + + $PROJ_DIR$\FreeRTOSConfig.h + + + $PROJ_DIR$\LEDs.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\main_blinky.c + + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/atmel_main.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/atmel_main.c new file mode 100644 index 000000000..8f1225fff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/atmel_main.c @@ -0,0 +1,433 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \page getting-started Getting Started with sama5d3 Microcontrollers + * + * \section Purpose + * + * The Getting Started example will help new users get familiar with Atmel's + * sama5d3x microcontroller. This basic application shows the startup + * sequence of a chip and how to use its core peripherals. + * + * \section Requirements + * + * This package can be used with sama5d3 xplained board. + * + * \section Description + * + * The demonstration program makes two LEDs on the board blink at a fixed rate. + * This rate is generated by using Time tick timer. The blinking can be stopped + * using two buttons (one for each LED). If there is no enough buttons on board, please + * type "1" or "2" in the terminal application on PC to control the LEDs + * instead. + * + * \section Usage + * + * -# Build the program and download it inside the xplained board. Please + * refer to the + * + * SAM-BA User Guide, the + * + * GNU-Based Software Development + * application note or to the + * + * IAR EWARM User Guide, + * depending on your chosen solution. + * -# On the computer, open and configure a terminal application + * (e.g. HyperTerminal on Microsoft Windows) with these settings: + * - 115200 bauds + * - 8 bits of data + * - No parity + * - 1 stop bit + * - No flow control + * -# Start the application. + * -# Two LEDs should start blinking on the board. In the terminal window, the + * following text should appear (values depend on the board and chip used): + * \code + * -- Getting Started Example xxx -- + * -- SAMxxxxx-xx + * -- Compiled: xxx xx xxxx xx:xx:xx -- + * \endcode + * -# Pressing and release button 1 or type "1" in the terminal application on + * PC should make the first LED stop & restart blinking. + * Pressing and release button 2 or type "1" in the terminal application on + * PC should make the other LED stop & restart blinking. + * + * \section References + * - getting-started/main.c + * - pio.h + * - pio_it.h + * - led.h + * - trace.h + */ + +/** \file + * + * This file contains all the specific code for the getting-started example. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +#define NO_PUSHBUTTON + +/** IRQ priority for PIO (The lower the value, the greater the priority) */ +#define IRQ_PRIOR_PIO 0 + +/** LED0 blink time, LED1 blink half this time, in ms */ +#define BLINK_PERIOD 1000 + +/** Delay for pushbutton debouncing (in milliseconds). */ +#define DEBOUNCE_TIME 500 + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +#ifndef NO_PUSHBUTTON +/** Pushbutton \#1 pin instance. */ +const Pin pinPB1 = PIN_PUSHBUTTON_1 ; +/** Pushbutton \#1 pin instance. */ +const Pin pinPB2 = PIN_PUSHBUTTON_2 ; +#endif + +/** LED0 blinking control. */ +volatile bool bLed0Active = true ; + +/** LED1 blinking control. */ +volatile bool bLed1Active = true ; + +/** Global timestamp in milliseconds since start of application */ +volatile uint32_t dwTimeStamp = 0; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Process Buttons Events + * + * Change active states of LEDs when corresponding button events happened. + */ +static void ProcessButtonEvt( uint8_t ucButton ) +{ + if ( ucButton == 0 ) + { + bLed0Active = !bLed0Active ; + if ( !bLed0Active ) + { + LED_Clear( 0 ); + } + } + else + { + bLed1Active = !bLed1Active ; + + /* Enable LED#2 and TC if they were disabled */ + if ( bLed1Active ) + { + LED_Set( 1 ); + TC_Start( TC0, 0 ); + } + /* Disable LED#2 and TC if they were enabled */ + else + { + LED_Clear( 1 ); + TC_Stop( TC0, 0 ); + } + } +} + +#ifndef NO_PUSHBUTTON +/** + * \brief Handler for Button 1 rising edge interrupt. + * + * Handle process led1 status change. + */ +static void _Button1_Handler( const Pin* pin ) +{ + pin = pin; + ProcessButtonEvt( 0 ) ; +} + +/** + * \brief Handler for Button 2 falling edge interrupt. + * + * Handle process led2 status change. + */ +static void _Button2_Handler( const Pin* pin ) +{ + pin = pin; + ProcessButtonEvt( 1 ) ; +} +#else +/** + * \brief Handler for DBGU input. + * + * Handle process LED1 or LED2 status change. + */ +static void _DBGU_Handler( void ) +{ + uint8_t key; + if ( !DBGU_IsRxReady( ) ) return ; + key = DBGU_GetChar( ) ; + switch ( key ) + { + case '1': case '2': + ProcessButtonEvt( key - '1' ) ; + break; + } +} +#endif + +/** + * \brief Handler for PIT interrupt. + */ +static void _Pit_Handler( void ) +{ + uint32_t status; + + /* Read the PIT status register */ + status = PIT_GetStatus() & PIT_SR_PITS; + if (status != 0) { + /* 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. + Read the PIVR to acknowledge interrupt and get number of ticks + Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. */ + dwTimeStamp += (PIT_GetPIVR() >> 20); + } +} + +/** + * \brief Handler for Sysc interrupts. + */ +static void _Sysc_Handler( void ) +{ + _Pit_Handler( ) ; + #ifdef NO_PUSHBUTTON + _DBGU_Handler( ) ; + #endif +} + +/** + * \brief Configure the periodic interval timer (PIT) to generate an interrupt every + * interrupt every millisecond + */ +static void ConfigurePit(void) +{ + PMC->PMC_PCER0 = 1 << ID_PIT; + /* Initialize the PIT to the desired frequency */ + PIT_Init(BLINK_PERIOD, BOARD_MCK / 1000000); + /* Configure interrupt on PIT */ + IRQ_ConfigureIT(ID_PIT, 0, _Sysc_Handler); + IRQ_EnableIT(ID_PIT); + PIT_EnableIT(); + /* Enable the pit */ + PIT_Enable(); +} + +#ifndef NO_PUSHBUTTON +/** + * \brief Configure the Pushbuttons + * + * Configure the PIO as inputs and generate corresponding interrupt when + * pressed or released. + */ +static void _ConfigureButtons( void ) +{ + /* Configure pios as inputs. */ + PIO_Configure( &pinPB1, 1 ) ; + PIO_Configure( &pinPB2, 1 ) ; + + /* Adjust pio debounce filter patameters, uses 10 Hz filter. */ + PIO_SetDebounceFilter( &pinPB1, 10 ) ; + PIO_SetDebounceFilter( &pinPB1, 10 ) ; + + /* Enable PIO controller IRQs. */ + PIO_InitializeInterrupts(0); + /* Initialize pios interrupt handlers, see PIO definition in board.h. */ + PIO_ConfigureIt(&pinPB1, (void (*)(const Pin *))_Button1_Handler); + PIO_ConfigureIt(&pinPB2, (void (*)(const Pin *))_Button2_Handler); + + /* Enable PIO line interrupts. */ + PIO_EnableIt( &pinPB1 ) ; + PIO_EnableIt( &pinPB2 ) ; +} +#endif + +/** + * \brief Configure LEDs + * + * Configures LEDs \#1 and \#2 (cleared by default). + */ +static void _ConfigureLeds( void ) +{ + LED_Configure( 0 ) ; + LED_Configure( 1 ) ; +} + +/** + * Interrupt handler for TC0 interrupt. Toggles the state of LED\#2. + */ +static void TC0_IrqHandler( void ) +{ + volatile uint32_t dummy; + /* Clear status bit to acknowledge interrupt */ + dummy = TC0->TC_CHANNEL[ 0 ].TC_SR ; + + /** Toggle LED state. */ + LED_Toggle( 1 ) ; + printf( "2 " ) ; +} + +/** + * Configure Timer Counter 0 to generate an interrupt every 250ms. + */ +static void _ConfigureTc( void ) +{ + uint32_t div; + uint32_t tcclks; + + /** Enable peripheral clock. */ + PMC->PMC_PCER0 = 1 << ID_TC0; + + /** Configure TC for a 4Hz frequency and trigger on RC compare. */ + TC_FindMckDivisor( 4, BOARD_MCK, &div, &tcclks, BOARD_MCK ); + TC_Configure( TC0, 0, tcclks | TC_CMR_CPCTRG ); + TC0->TC_CHANNEL[ 0 ].TC_RC = ( BOARD_MCK / div ) / 4; + + /* Configure and enable interrupt on RC compare */ + IRQ_ConfigureIT(ID_TC0, 0, TC0_IrqHandler); + TC0->TC_CHANNEL[ 0 ].TC_IER = TC_IER_CPCS; + IRQ_EnableIT(ID_TC0); + + /** Start the counter if LED1 is enabled. */ + if ( bLed1Active ) + { + TC_Start( TC0, 0 ); + } +} + +/** + * Waits for the given number of milliseconds (using the dwTimeStamp generated + * by the SAM3's microcontrollers's system tick). + * \param delay Delay to wait for, in milliseconds. + */ +static void _Wait( unsigned long delay ) +{ + volatile uint32_t start = dwTimeStamp; + uint32_t elapsed; + do { + elapsed = dwTimeStamp; + elapsed -= start; + } + while (elapsed < delay); +} + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief getting-started Application entry point. + * + * \return Unused (ANSI-C compatibility). + */ +int atmel_main( void ); +int atmel_main( void ) +{ + /* Disable watchdog */ + WDT_Disable( WDT ) ; +#if defined (ddram) + MMU_Initialize((uint32_t *)0x30C000); + CP15_EnableMMU(); + CP15_EnableDcache(); + CP15_EnableIcache(); +#endif + + /* Output example information */ + printf( "-- Getting Started Example %s --\n\r", SOFTPACK_VERSION ) ; + printf( "-- %s\n\r", BOARD_NAME ) ; + printf( "-- Compiled: %s %s --\n\r", __DATE__, __TIME__ ) ; + + /* Configure PIT. */ + printf( "Configure PIT \n\r" ) ; +//__asm volatile( "cpsid i" ); + ConfigurePit() ; + + /* PIO configuration for LEDs and Buttons. */ + PIO_InitializeInterrupts( IRQ_PRIOR_PIO ) ; + + printf( "Configure TC.\n\r" ); + _ConfigureTc() ; + + printf( "Configure LED PIOs.\n\r" ) ; + _ConfigureLeds() ; + +#ifndef NO_PUSHBUTTON + printf( "Configure buttons with debouncing.\n\r" ) ; + _ConfigureButtons() ; + printf( "Press USRBP1 to Start/Stop the blue LED D1 blinking.\n\r" ) ; + printf( "Press USRBP2 to Start/Stop the red LED D2 blinking.\n\r" ) ; + +#else + printf( "No push buttons, uses DBG key 1 & 2 instead.\n\r" ) ; + printf( "Press 1 to Start/Stop the blue LED D1 blinking.\n\r" ) ; + printf( "Press 2 to Start/Stop the red LED D2 blinking.\n\r" ) ; + +#endif + + while ( 1 ) + { + /* Wait for LED to be active */ + while( !bLed0Active ); + + /* Toggle LED state if active */ + if ( bLed0Active ) + { + LED_Toggle( 0 ); + printf( "1 " ); + } + + /* Wait for 500ms */ + _Wait(500); + } +} diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c new file mode 100644 index 000000000..76c1d814a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main.c @@ -0,0 +1,229 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and FreeRTOS hook functions. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ +extern int atmel_main( void ); +int main( void ) +{ + atmel_main(); + + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char * pcFile, unsigned long ulLine ) +{ +volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + } + #endif +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main_blinky.c new file mode 100644 index 000000000..8a8a35949 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/main_blinky.c @@ -0,0 +1,232 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides three demo applications. A simple blinky + * style project, a more comprehensive test and demo application, and an + * lwIP example. The mainSELECTED_APPLICATION setting in main.c is used to + * select between the three. See the notes on using mainSELECTED_APPLICATION + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* The LED toggled by the Rx task. */ +#define mainTASK_LED ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + vParTestToggleLED( mainTASK_LED ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.crun b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.crun new file mode 100644 index 000000000..5bb5acca4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.crun @@ -0,0 +1,16 @@ + + + + 1 + + + * + * + * + 0 + 1 + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..229c1342a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,97 @@ + + + + + + + + + 201622 + + 20 + 1216 + 324 + 81 + + + + + + + + 124272727 + + + + + + Disassembly_I0 + + + + 50020 + + + + 11 + + + + + + + + + TabID-13925-23874 + Debug Log + Debug-Log + + + + TabID-13402-23884 + Build + Build + + + + + 0 + + + TabID-24673-23877 + Workspace + Workspace + + + RTOSDemo + + + + 0 + + + TabID-2653-23881 + Disassembly + Disassembly + + + + + 0 + + + + + + TextEditor$WS_DIR$\..\..\..\..\..\..\..\DevTools\IAR Systems\Embedded Workbench 7.0\arm\doc\infocenter\index.ENU.htmlTextEditor$WS_DIR$\..\..\..\..\..\..\..\DevTools\IAR Systems\Embedded Workbench 7.0\rl78\doc\infocenter\index.ENU.htmlTextEditor$WS_DIR$\atmel_main.c0000036411999119992TextEditor$WS_DIR$\AtmelFiles\libboard_sama5d3x-ek\source\board_cstartup_iar.s0000015967776777TextEditor$WS_DIR$\AtmelFiles\libboard_sama5d3x-ek\source\board_memories.c0000014286228622TextEditor$WS_DIR$\FreeRTOS_tick_config.c000004442924292TextEditor$WS_DIR$\main.c0000010258705870TextEditor$WS_DIR$\main_blinky.c0000011568506850TextEditor$WS_DIR$\FreeRTOSConfig.h00000172945494540100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2718198-2-2200200119048203252119048731707-2-2718605-2-2200200119048203252361310731707-2-21981682-2-216842001002381203252119048203252 + + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.ddram.cspy.bat b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.ddram.cspy.bat new file mode 100644 index 000000000..097b81288 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.ddram.cspy.bat @@ -0,0 +1,24 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll" %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D3x_Xplained_IAR\..\..\..\..\libraries\libboard_sama5d3x-ek\resources\ewarm\sama5d3x-ek-ddram.mac" --backend -B "--endian=little" "--cpu=Cortex-A5" "--fpu=None" "-p" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\CONFIG\debugger\Atmel\ATSAMA5D35.ddf" "--drv_verify_download" "--semihosting=none" "--device=ATSAMA5D35" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--drv_catch_exceptions=0x000" + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..317a9571f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.dni @@ -0,0 +1,47 @@ +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[JLinkDriver] +WatchCond=_ 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +CStepIntDis=_ 0 +[DebugChecksum] +Checksum=1381722156 +[Exceptions] +StopOnUncaught=_ 0 +StopOnThrow=_ 0 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[CallStackLog] +Enabled=0 +[DriverProfiling] +Enabled=0 +Mode=0 +Graph=0 +Symbiont=0 +Exclusions= +[Disassemble mode] +mode=0 +[Breakpoints2] +Bp0=_ 0 "EMUL_CODE" "0x0030558C" 0 0 1 "" 0 "" 0 +Count=1 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.sram.cspy.bat b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.sram.cspy.bat new file mode 100644 index 000000000..aafa61bf9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.sram.cspy.bat @@ -0,0 +1,24 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +"C:\DevTools\IAR Systems\Embedded Workbench 7.0\common\bin\cspybat" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armproc.dll" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armjlink.dll" %1 --plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\bin\armbat.dll" --macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_A5_SAMA5D3x_Xplained_IAR\AtmelFiles\libboard_sama5d3x-ek\resources\ewarm\sama5d3x-ek-sram.mac" --backend -B "--endian=little" "--cpu=Cortex-A5" "--fpu=VFPv4Neon" "-p" "C:\DevTools\IAR Systems\Embedded Workbench 7.0\arm\CONFIG\debugger\Atmel\ATSAMA5D35.ddf" "--drv_verify_download" "--semihosting=none" "--device=ATSAMA5D35" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--drv_catch_exceptions=0x000" + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..544088e4a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,78 @@ + + + + + + RTOSDemo/sram + + + + + + + + + 251272727 + + + + Action + Check + Source File + + + 100 + 400 + 200 + + + + + + + + 20121632481 + 181624 + + + + + + + TabID-22351-19008 + Workspace + Workspace + + + RTOSDemo + + + + 0 + + + TabID-21076-19237 + Build + Build + + + TabID-23502-23081Debug LogDebug-Log + + 0 + + + + + + TextEditor$WS_DIR$\..\..\..\..\..\..\..\DevTools\IAR Systems\Embedded Workbench 7.0\arm\doc\infocenter\index.ENU.htmlTextEditor$WS_DIR$\..\..\..\..\..\..\..\DevTools\IAR Systems\Embedded Workbench 7.0\rl78\doc\infocenter\index.ENU.htmlTextEditor$WS_DIR$\atmel_main.c0000036411999119992TextEditor$WS_DIR$\AtmelFiles\libboard_sama5d3x-ek\source\board_cstartup_iar.s0000015967776777TextEditor$WS_DIR$\AtmelFiles\libboard_sama5d3x-ek\source\board_memories.c0000014286228622TextEditor$WS_DIR$\FreeRTOS_tick_config.c000004442924292TextEditor$WS_DIR$\main.c0000010258705870TextEditor$WS_DIR$\main_blinky.c0000011568506850TextEditor$WS_DIR$\FreeRTOSConfig.h00000172945494540100000010000001 + + + + + + + iaridepm.enu1-2-2555325-2-2200200119048203252194643566057-2-23851682-2-216843871002381393293119048203252 + + + + diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..403b5ce58 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 66 66 1326 815 3 diff --git a/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo_sram.jlink b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo_sram.jlink new file mode 100644 index 000000000..de1b137f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A5_SAMA5D3x_Xplained_IAR/settings/RTOSDemo_sram.jlink @@ -0,0 +1,34 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF