From: Marek Vasut <marex@denx.de>
Date: Sun, 14 Sep 2014 23:45:14 +0000 (+0200)
Subject: arm: socfpga: cache: Enable PL310 L2 cache
X-Git-Tag: v2014.10-rc3~2^2~11
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b5e9b296251f138ef9f9cfc15f408710a24831cd;p=u-boot

arm: socfpga: cache: Enable PL310 L2 cache

Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
---

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index de60bb2f06..c8986d9811 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -27,6 +27,8 @@
 
 #define CONFIG_SYS_ARM_CACHE_WRITEALLOC
 #define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET